Case check for LVS

[d-m-bailey]

spice ignores case, verilog (by default?) doesn't.

netgen's LVS can go either way - ignoring case is spice file is read first, considering case if verilog is read first.

This can cause problems (failure to match) when the layout has cells with conflicting case, eg. Buffer and BUFFER.

Suggested solution is to flag cell names and text/nets that have mixed case in the layout, spice and verilog files.