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15 | 15 | #include "clang/Basic/MacroBuilder.h" |
16 | 16 | #include "clang/Basic/TargetBuiltins.h" |
17 | 17 | #include "llvm/TargetParser/PPCTargetParser.h" |
18 | | -#include <optional> |
19 | 18 |
|
20 | 19 | using namespace clang; |
21 | 20 | using namespace clang::targets; |
@@ -517,14 +516,129 @@ static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, |
517 | 516 | bool PPCTargetInfo::initFeatureMap( |
518 | 517 | llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, |
519 | 518 | const std::vector<std::string> &FeaturesVec) const { |
| 519 | + Features["altivec"] = llvm::StringSwitch<bool>(CPU) |
| 520 | + .Case("7400", true) |
| 521 | + .Case("g4", true) |
| 522 | + .Case("7450", true) |
| 523 | + .Case("g4+", true) |
| 524 | + .Case("970", true) |
| 525 | + .Case("g5", true) |
| 526 | + .Case("pwr6", true) |
| 527 | + .Case("pwr7", true) |
| 528 | + .Case("pwr8", true) |
| 529 | + .Case("pwr9", true) |
| 530 | + .Case("ppc64", true) |
| 531 | + .Case("ppc64le", true) |
| 532 | + .Default(false); |
| 533 | + |
| 534 | + Features["power9-vector"] = (CPU == "pwr9"); |
| 535 | + Features["crypto"] = llvm::StringSwitch<bool>(CPU) |
| 536 | + .Case("ppc64le", true) |
| 537 | + .Case("pwr9", true) |
| 538 | + .Case("pwr8", true) |
| 539 | + .Default(false); |
| 540 | + Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) |
| 541 | + .Case("ppc64le", true) |
| 542 | + .Case("pwr9", true) |
| 543 | + .Case("pwr8", true) |
| 544 | + .Default(false); |
| 545 | + Features["bpermd"] = llvm::StringSwitch<bool>(CPU) |
| 546 | + .Case("ppc64le", true) |
| 547 | + .Case("pwr9", true) |
| 548 | + .Case("pwr8", true) |
| 549 | + .Case("pwr7", true) |
| 550 | + .Default(false); |
| 551 | + Features["extdiv"] = llvm::StringSwitch<bool>(CPU) |
| 552 | + .Case("ppc64le", true) |
| 553 | + .Case("pwr9", true) |
| 554 | + .Case("pwr8", true) |
| 555 | + .Case("pwr7", true) |
| 556 | + .Default(false); |
| 557 | + Features["direct-move"] = llvm::StringSwitch<bool>(CPU) |
| 558 | + .Case("ppc64le", true) |
| 559 | + .Case("pwr9", true) |
| 560 | + .Case("pwr8", true) |
| 561 | + .Default(false); |
| 562 | + Features["crbits"] = llvm::StringSwitch<bool>(CPU) |
| 563 | + .Case("ppc64le", true) |
| 564 | + .Case("pwr9", true) |
| 565 | + .Case("pwr8", true) |
| 566 | + .Default(false); |
| 567 | + Features["vsx"] = llvm::StringSwitch<bool>(CPU) |
| 568 | + .Case("ppc64le", true) |
| 569 | + .Case("pwr9", true) |
| 570 | + .Case("pwr8", true) |
| 571 | + .Case("pwr7", true) |
| 572 | + .Default(false); |
| 573 | + Features["htm"] = llvm::StringSwitch<bool>(CPU) |
| 574 | + .Case("ppc64le", true) |
| 575 | + .Case("pwr9", true) |
| 576 | + .Case("pwr8", true) |
| 577 | + .Default(false); |
| 578 | + |
| 579 | + // ROP Protect is off by default. |
| 580 | + Features["rop-protect"] = false; |
| 581 | + // Privileged instructions are off by default. |
| 582 | + Features["privileged"] = false; |
520 | 583 |
|
521 | | - const llvm::Triple &TheTriple = getTriple(); |
| 584 | + if (getTriple().isOSAIX()) { |
| 585 | + // The code generated by the -maix-small-local-[exec|dynamic]-tls option is |
| 586 | + // turned off by default. |
| 587 | + Features["aix-small-local-exec-tls"] = false; |
| 588 | + Features["aix-small-local-dynamic-tls"] = false; |
| 589 | + |
| 590 | + // Turn off TLS model opt by default. |
| 591 | + Features["aix-shared-lib-tls-model-opt"] = false; |
| 592 | + } |
| 593 | + |
| 594 | + Features["spe"] = llvm::StringSwitch<bool>(CPU) |
| 595 | + .Case("8548", true) |
| 596 | + .Case("e500", true) |
| 597 | + .Default(false); |
| 598 | + |
| 599 | + Features["isa-v206-instructions"] = llvm::StringSwitch<bool>(CPU) |
| 600 | + .Case("ppc64le", true) |
| 601 | + .Case("pwr9", true) |
| 602 | + .Case("pwr8", true) |
| 603 | + .Case("pwr7", true) |
| 604 | + .Case("a2", true) |
| 605 | + .Default(false); |
| 606 | + |
| 607 | + Features["isa-v207-instructions"] = llvm::StringSwitch<bool>(CPU) |
| 608 | + .Case("ppc64le", true) |
| 609 | + .Case("pwr9", true) |
| 610 | + .Case("pwr8", true) |
| 611 | + .Default(false); |
| 612 | + |
| 613 | + Features["isa-v30-instructions"] = |
| 614 | + llvm::StringSwitch<bool>(CPU).Case("pwr9", true).Default(false); |
| 615 | + |
| 616 | + Features["quadword-atomics"] = |
| 617 | + getTriple().isArch64Bit() && llvm::StringSwitch<bool>(CPU) |
| 618 | + .Case("pwr9", true) |
| 619 | + .Case("pwr8", true) |
| 620 | + .Default(false); |
| 621 | + |
| 622 | + // Power10 includes all the same features as Power9 plus any features specific |
| 623 | + // to the Power10 core. |
| 624 | + if (CPU == "pwr10" || CPU == "power10") { |
| 625 | + initFeatureMap(Features, Diags, "pwr9", FeaturesVec); |
| 626 | + addP10SpecificFeatures(Features); |
| 627 | + } |
| 628 | + |
| 629 | + // Power11 includes all the same features as Power10 plus any features |
| 630 | + // specific to the Power11 core. |
| 631 | + if (CPU == "pwr11" || CPU == "power11") { |
| 632 | + initFeatureMap(Features, Diags, "pwr10", FeaturesVec); |
| 633 | + addP11SpecificFeatures(Features); |
| 634 | + } |
522 | 635 |
|
523 | | - std::optional<llvm::StringMap<bool>> FeaturesOpt = |
524 | | - llvm::PPC::getPPCDefaultTargetFeatures(TheTriple, |
525 | | - llvm::PPC::normalizeCPUName(CPU)); |
526 | | - if (FeaturesOpt) |
527 | | - Features = FeaturesOpt.value(); |
| 636 | + // Future CPU should include all of the features of Power 11 as well as any |
| 637 | + // additional features (yet to be determined) specific to it. |
| 638 | + if (CPU == "future") { |
| 639 | + initFeatureMap(Features, Diags, "pwr11", FeaturesVec); |
| 640 | + addFutureSpecificFeatures(Features); |
| 641 | + } |
528 | 642 |
|
529 | 643 | if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) |
530 | 644 | return false; |
@@ -586,6 +700,26 @@ bool PPCTargetInfo::initFeatureMap( |
586 | 700 | return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); |
587 | 701 | } |
588 | 702 |
|
| 703 | +// Add any Power10 specific features. |
| 704 | +void PPCTargetInfo::addP10SpecificFeatures( |
| 705 | + llvm::StringMap<bool> &Features) const { |
| 706 | + Features["htm"] = false; // HTM was removed for P10. |
| 707 | + Features["paired-vector-memops"] = true; |
| 708 | + Features["mma"] = true; |
| 709 | + Features["power10-vector"] = true; |
| 710 | + Features["pcrelative-memops"] = true; |
| 711 | + Features["prefix-instrs"] = true; |
| 712 | + Features["isa-v31-instructions"] = true; |
| 713 | +} |
| 714 | + |
| 715 | +// Add any Power11 specific features. |
| 716 | +void PPCTargetInfo::addP11SpecificFeatures( |
| 717 | + llvm::StringMap<bool> &Features) const {} |
| 718 | + |
| 719 | +// Add features specific to the "Future" CPU. |
| 720 | +void PPCTargetInfo::addFutureSpecificFeatures( |
| 721 | + llvm::StringMap<bool> &Features) const {} |
| 722 | + |
589 | 723 | bool PPCTargetInfo::hasFeature(StringRef Feature) const { |
590 | 724 | return llvm::StringSwitch<bool>(Feature) |
591 | 725 | .Case("powerpc", true) |
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