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Merge pull request #11 from eki-project/feature/squeeze
[Squeeze] Introduce Squeeze and Unsqueeze hardware operators
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/******************************************************************************
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* Copyright (C) 2024, Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* @author Thomas B. Preußer <thomas.preusser@amd.com>
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* @brief Wiring-only pass-thru AXI-Stream connector.
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*/
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module passthru_axi #(
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int unsigned DATA_WIDTH
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)(
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// Global Control - NOT USED
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input logic ap_clk,
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input logic ap_rst_n,
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// Input Stream
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input logic [DATA_WIDTH-1:0] s_axis_tdata,
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input logic s_axis_tvalid,
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output logic s_axis_tready,
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// Output Stream
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output logic [DATA_WIDTH-1:0] m_axis_tdata,
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output logic m_axis_tvalid,
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input logic m_axis_tready
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);
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// Simple pass-through Connection
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assign m_axis_tdata = s_axis_tdata;
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assign m_axis_tvalid = s_axis_tvalid;
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assign s_axis_tready = m_axis_tready;
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endmodule : passthru_axi
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/******************************************************************************
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* Copyright (C) 2024, Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* @author Thomas B. Preußer <thomas.preusser@amd.com>
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* @brief Verilog wrapper for IP packaging.
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*/
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module $MODULE_NAME_AXI_WRAPPER$ #(
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int unsigned DATA_WIDTH = $DATA_WIDTH$
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)(
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// Global Control - NOT USED
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(* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF s_axis:m_axis, ASSOCIATED_RESET ap_rst_n" *)
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(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ap_clk CLK" *)
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input ap_clk,
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(* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *)
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input ap_rst_n,
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// Input Stream
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input logic [DATA_BITS-1:0] s_axis_tdata,
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input logic s_axis_tvalid,
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output logic s_axis_tready,
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// Output Stream
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output logic [DATA_BITS-1:0] m_axis_tdata,
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output logic m_axis_tvalid,
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input logic m_axis_tready
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);
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passthru_axi #(.DATA_BITS(DATA_BITS)) core (
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.ap_clk(ap_clk), .ap_rst_n(ap_rst_n),
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.s_axis_tdata(s_axis_tdata), .s_axis_tvalid(s_axis_tvalid), .s_axis_tready(s_axis_tready),
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.m_axis_tdata(m_axis_tdata), .m_axis_tvalid(m_axis_tvalid), .m_axis_tready(m_axis_tready)
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);
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endmodule // $MODULE_NAME_AXI_WRAPPER$

src/finn/custom_op/fpgadataflow/__init__.py

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# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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# The base class of all generic custom operations before specializing to either
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# HLS or RTL backend
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from finn.custom_op.fpgadataflow.hwcustomop import HWCustomOp
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# Dictionary of HWCustomOp implementations
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custom_op = dict()
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# Registers a class into the custom_op dictionary
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# Note: This must be defined first, before importing any custom op
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# implementation to avoid "importing partially initialized module" issues.
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def register_custom_op(cls):
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# The class must actually implement HWCustomOp
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assert issubclass(cls, HWCustomOp), f"{cls} must subclass {HWCustomOp}"
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# Insert the class into the custom_op dictionary by its name
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custom_op[cls.__name__] = cls # noqa: Some weird type annotation issue?
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# Pass through the class unmodified
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return cls
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# flake8: noqa
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# Disable linting from here, as all import will be flagged E402 and maybe F401
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# Import the submodule containing the Squeeze operation
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# Note: This will automatically register all decorated classes into this domain
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import finn.custom_op.fpgadataflow.squeeze
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# Import the submodule containing the Unsqueeze operation
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import finn.custom_op.fpgadataflow.unsqueeze
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from finn.custom_op.fpgadataflow.addstreams import AddStreams
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from finn.custom_op.fpgadataflow.channelwise_op import ChannelwiseOp
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from finn.custom_op.fpgadataflow.concat import StreamingConcat
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from finn.custom_op.fpgadataflow.upsampler import UpsampleNearestNeighbour
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from finn.custom_op.fpgadataflow.vectorvectoractivation import VVAU
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custom_op = dict()
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# make sure new HLSCustomOp subclasses are imported here so that they get
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# registered and plug in correctly into the infrastructure
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custom_op["MVAU"] = MVAU

src/finn/custom_op/fpgadataflow/hls/__init__.py

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# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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# The base class of all HWCustomOp specializations to HLS backend implementation
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from finn.custom_op.fpgadataflow.hlsbackend import HLSBackend
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# The base class of all generic custom operations before specializing to either
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# HLS or RTL backend
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from finn.custom_op.fpgadataflow.hwcustomop import HWCustomOp
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# Dictionary of HLSBackend implementations
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custom_op = dict()
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# Registers a class into the custom_op dictionary
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# Note: This must be defined first, before importing any custom op
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# implementation to avoid "importing partially initialized module" issues.
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def register_custom_op(cls):
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# The class must actually implement HWCustomOp
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assert issubclass(cls, HWCustomOp), f"{cls} must subclass {HWCustomOp}"
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# The class must also implement the HLSBackend
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assert issubclass(cls, HLSBackend), f"{cls} must subclass {HLSBackend}"
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# Insert the class into the custom_op dictionary by its name
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custom_op[cls.__name__] = cls # noqa: Some weird type annotation issue?
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# Pass through the class unmodified
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return cls
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# flake8: noqa
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# Disable linting from here, as all import will be flagged E402 and maybe F401
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# Import the submodule containing the specialization of the Squeeze operation
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# Note: This will automatically register all decorated classes into this domain
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import finn.custom_op.fpgadataflow.hls.squeeze_hls
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# Import the submodule containing the specialization of the Unsqueeze operation
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import finn.custom_op.fpgadataflow.hls.unsqueeze_hls
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from finn.custom_op.fpgadataflow.hls.addstreams_hls import AddStreams_hls
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from finn.custom_op.fpgadataflow.hls.channelwise_op_hls import ChannelwiseOp_hls
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from finn.custom_op.fpgadataflow.hls.checksum_hls import CheckSum_hls
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from finn.custom_op.fpgadataflow.hls.upsampler_hls import UpsampleNearestNeighbour_hls
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from finn.custom_op.fpgadataflow.hls.vectorvectoractivation_hls import VVAU_hls
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custom_op = dict()
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# make sure new HLSCustomOp subclasses are imported here so that they get
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# registered and plug in correctly into the infrastructure
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custom_op["AddStreams_hls"] = AddStreams_hls

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