Scope name contains `.`

[raczben]

I try to parse this vcd file:
https://raw.githubusercontent.com/DanieleParravicini/regex_coprocessor/refs/heads/master/scripts/sim/test2x2_regex22_string1.vcd

There is a module which name contains a . at line 216:

$scope module genblk1.a_topology $end

this cause the following error:

RuntimeError: No var at path AXI_top_tb_from_compiled.dut.a_regex_coprocessor.genblk1.a_topology.clk

The code is the same like this: #92 (comment)

[oscargus]

This is an inherent problem... In e.g. Surfer we are using . to distinguish between levels in the hierarchy. This is quite convenient when typing the hierarchy, but as it turns out, not really a good idea. It seems like the only valid hierarchy separates is space, which is quite inconvenient from a parsing perspective and also reads quite bad...

RuntimeError: No var at path AXI_top_tb_from_compiled dut a_regex_coprocessor genblk1.a_topology clk

However, with that said, I guess one will just have to adapt somehow...

Edit:
Maybe we should just change to / (which is what ModelSim/Questa use), although I am quite sure / is just as valid as .

Actually, reading the 2005 Verilog standard (the newest I could find), it says:

"A simple identifier shall be any sequence of letters, digits, dollar signs ($), and underscore characters (_). "

"Escaped identifiers shall start with the backslash character () and end with white space (space, tab,
newline). "

[ekiwi]

@raczben : do you have a link to the Verilog source where this originates from? Also, which simulator is this VCD generated by?

[andreasWallner]

@oscargus I think even on the surfer side we could stick with the "." -> but escape actual uses of the dot in identifiers (like you'd have to do if you use them in verilog.

@ekiwi I don't have an example for you at hand, but those are somewhat common for post-synthesis / post-layout netlists, depending on the tool they use ".", "$" or some other special char...