Skip to content

Commit 0225d12

Browse files
stsdcstsdc
committed
Update structs according to ver. 3.10.0
1 parent db42263 commit 0225d12

File tree

1 file changed

+86
-71
lines changed

1 file changed

+86
-71
lines changed

‎vapi/pci.vapi‎

Lines changed: 86 additions & 71 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,33 @@ namespace Pci {
33

44
public const int LIB_VERSION;
55

6+
// version 3.13.0
7+
// [CCode (cname = "int", cprefix = "PCI_ACCESS_", has_type_id = false)]
8+
// public enum AccessType {
9+
// AUTO, /* Autodetection */
10+
// SYS_BUS_PCI, /* Linux /sys/bus/pci */
11+
// PROC_BUS_PCI, /* Linux /proc/bus/pci */
12+
// I386_TYPE1, /* i386 ports, type 1 */
13+
// I386_TYPE2, /* i386 ports, type 2 */
14+
// FBSD_DEVICE, /* FreeBSD /dev/pci */
15+
// AIX_DEVICE, /* /dev/pci0, /dev/bus0, etc. */
16+
// NBSD_LIBPCI, /* NetBSD libpci */
17+
// OBSD_DEVICE, /* OpenBSD /dev/pci */
18+
// DUMP, /* Dump file */
19+
// DARWIN, /* Darwin */
20+
// SYLIXOS_DEVICE, /* SylixOS pci */
21+
// HURD, /* GNU/Hurd */
22+
// WIN32_CFGMGR32, /* Win32 cfgmgr32.dll */
23+
// WIN32_KLDBG, /* Win32 kldbgdrv.sys */
24+
// WIN32_SYSDBG, /* Win32 NT SysDbg */
25+
// MMIO_TYPE1, /* MMIO ports, type 1 */
26+
// MMIO_TYPE1_EXT, /* MMIO ports, type 1 extended */
27+
// ECAM, /* PCIe ECAM via /dev/mem */
28+
// AOS_EXPANSION, /* AmigaOS Expansion library */
29+
// MAX
30+
// }
31+
32+
// version 3.10.0
633
[CCode (cname = "int", cprefix = "PCI_ACCESS_", has_type_id = false)]
734
public enum AccessType {
835
AUTO, /* Autodetection */
@@ -18,22 +45,15 @@ namespace Pci {
1845
DARWIN, /* Darwin */
1946
SYLIXOS_DEVICE, /* SylixOS pci */
2047
HURD, /* GNU/Hurd */
21-
WIN32_CFGMGR32, /* Win32 cfgmgr32.dll */
22-
WIN32_KLDBG, /* Win32 kldbgdrv.sys */
23-
WIN32_SYSDBG, /* Win32 NT SysDbg */
24-
MMIO_TYPE1, /* MMIO ports, type 1 */
25-
MMIO_TYPE1_EXT, /* MMIO ports, type 1 extended */
26-
// ECAM, /* PCIe ECAM via /dev/mem */
27-
AOS_EXPANSION, /* AmigaOS Expansion library */
2848
MAX
2949
}
3050

3151
[SimpleType, CCode (cname = "pciaddr_t", has_type_id = false)]
32-
public struct PciAddr : uint64 { }
52+
public struct PciAddr : uint64 {}
3353

3454
[CCode (cname = "pci_cap", has_type_id = false)]
3555
public struct Cap {
36-
Cap *next;
56+
Cap * next;
3757
uint16 id; /* PCI_CAP_ID_xxx */
3858
uint16 type; /* PCI_CAP_xxx */
3959
uint addr; /* Position in the config space */
@@ -46,7 +66,7 @@ namespace Pci {
4666
int writeable; /* Open in read/write mode */
4767
int buscentric; /* Bus-centric view of the world */
4868

49-
char *id_file_name; /* Name of ID list file (use pci_set_name_list_path()) */
69+
char * id_file_name; /* Name of ID list file (use pci_set_name_list_path()) */
5070
int free_id_name; /* Set if id_file_name is malloced */
5171
int numeric_ids; /* Enforce PCI_LOOKUP_NUMERIC (>1 => PCI_LOOKUP_MIXED) */
5272

@@ -60,69 +80,64 @@ namespace Pci {
6080
// void (*warning)(char *msg, ...) PCI_PRINTF (1,2); /* Write a warning message */
6181
// void (*debug)(char *msg, ...) PCI_PRINTF (1,2); /* Write a debugging message */
6282

63-
Dev *devices; /* Devices found on this bus */
83+
Dev * devices; /* Devices found on this bus */
6484

6585
[CCode (cname = "pci_init")]
6686
public Access (Access acess);
67-
}
68-
69-
/* Initialize PCI access */
70-
[CCode (cname = "pci_alloc")]
71-
Access *pci_alloc ();
72-
73-
/* Scanning of devices */
74-
[CCode (cname = "pci_scan_bus")]
75-
void pci_scan_bus(Access *acc);
76-
77-
78-
[CCode (cname = "struct pci_dev", has_type_id = false)]
79-
public struct Dev {
80-
Dev *next; /* Next device in the chain */
81-
uint16 domain_16; /* 16-bit version of the PCI domain for backward compatibility */
82-
/* 0xffff if the real domain doesn't fit in 16 bits */
83-
84-
/* Bus inside domain, device and function */
85-
uint8 bus;
86-
uint8 dev;
87-
uint8 func;
88-
89-
/* These fields are set by pci_fill_info() */
90-
uint known_fields; /* Set of info fields already known (see pci_fill_info()) */
91-
92-
/* Identity of the device */
93-
uint16 vendor_id;
94-
uint16 device_id;
95-
96-
uint16 device_class; /* PCI device class */
97-
int irq; /* IRQ number */
98-
PciAddr base_addr[6]; /* Base addresses including flags in lower bits */
99-
PciAddr size[6]; /* Region sizes */
100-
PciAddr rom_base_addr; /* Expansion ROM base address */
101-
PciAddr rom_size; /* Expansion ROM size */
102-
Cap *first_cap; /* List of capabilities */
103-
char *phy_slot; /* Physical slot */
104-
char *module_alias; /* Linux kernel module alias */
105-
char *label; /* Device name as exported by BIOS */
106-
int numa_node; /* NUMA node */
107-
PciAddr flags[6]; /* PCI_IORESOURCE_* flags for regions */
108-
PciAddr rom_flags; /* PCI_IORESOURCE_* flags for expansion ROM */
109-
int domain; /* PCI domain (host bridge) */
110-
PciAddr bridge_base_addr[4]; /* Bridge base addresses (without flags) */
111-
PciAddr bridge_size[4]; /* Bridge sizes */
112-
PciAddr bridge_flags[4]; /* PCI_IORESOURCE_* flags for bridge addresses */
113-
114-
/* Programming interface for device_class and revision id */
115-
uint8 prog_if;
116-
uint8 rev_id;
117-
118-
/* Subsystem vendor id and subsystem id */
119-
uint16 subsys_vendor_id;
120-
uint16 subsys_id;
121-
Dev *parent; /* Parent device, does not have to be always accessible */
122-
int no_config_access; /* No access to config space for this device */
123-
uint32 rcd_link_cap; /* Link Capabilities register for Restricted CXL Devices */
124-
uint16 rcd_link_status; /* Link Status register for RCD */
125-
uint16 rcd_link_ctrl; /* Link Control register for RCD */
126-
}
87+
}
88+
89+
/* Initialize PCI access */
90+
[CCode (cname = "pci_alloc")]
91+
Access * pci_alloc ();
92+
93+
/* Scanning of devices */
94+
[CCode (cname = "pci_scan_bus")]
95+
void pci_scan_bus (Access * acc);
96+
97+
[CCode (cname = "pci_methods")]
98+
public struct Methods {}
99+
100+
[CCode (cname = "pci_property")]
101+
public struct Property {}
102+
103+
104+
[CCode (cname = "struct pci_dev", has_type_id = false)]
105+
public struct Dev {
106+
Dev * next; /* Next device in the chain */
107+
uint16 domain_16; /* 16-bit version of the PCI domain for backward compatibility */
108+
/* 0xffff if the real domain doesn't fit in 16 bits */
109+
uint8 bus;
110+
uint8 dev;
111+
uint8 func; /* Bus inside domain, device and function */
112+
113+
/* These fields are set by pci_fill_info() */
114+
uint known_fields; /* Set of info fields already known (see pci_fill_info()) */
115+
uint16 vendor_id;
116+
uint16 device_id; /* Identity of the device */
117+
uint16 device_class; /* PCI device class */
118+
int irq; /* IRQ number */
119+
PciAddr base_addr[6]; /* Base addresses including flags in lower bits */
120+
PciAddr size[6]; /* Region sizes */
121+
PciAddr rom_base_addr; /* Expansion ROM base address */
122+
PciAddr rom_size; /* Expansion ROM size */
123+
Cap * first_cap; /* List of capabilities */
124+
char * phy_slot; /* Physical slot */
125+
char * module_alias; /* Linux kernel module alias */
126+
char * label; /* Device name as exported by BIOS */
127+
int numa_node; /* NUMA node */
128+
PciAddr flags[6]; /* PCI_IORESOURCE_* flags for regions */
129+
PciAddr rom_flags; /* PCI_IORESOURCE_* flags for expansion ROM */
130+
int domain; /* PCI domain (host bridge) */
131+
132+
/* Fields used internally */
133+
Access * access;
134+
Methods * methods;
135+
uint8 * cache; /* Cached config registers */
136+
int cache_len;
137+
int hdrtype; /* Cached low 7 bits of header type, -1 if unknown */
138+
void * aux; /* Auxiliary data for use by the back-end */
139+
Property * properties; /* A linked list of extra properties */
140+
Cap * last_cap; /* Last capability in the list */
141+
}
127142

128143
}

0 commit comments

Comments
 (0)