Merge branch 'timer_update_management' of github.com:WattStep/embassy into time

Author: xoviat

embassy-stm32/CHANGELOG.md

@@ -8,6 +8,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 ## Unreleased - ReleaseDate
 
 - feat: Add waveform methods to ComplementaryPwm
+- fix: Avoid generating timer update events when updating the frequency ([#4890](https://github.com/embassy-rs/embassy/pull/4890))
 - chore: cleanup low-power add time
 - fix: Allow setting SAI peripheral `frame_length` to `256`
 - fix: flash erase on dual-bank STM32Gxxx

embassy-stm32/src/timer/complementary_pwm.rs

@@ -77,8 +77,6 @@ impl<'d, T: AdvancedInstance4Channel> ComplementaryPwm<'d, T> {
 
         this.inner.set_counting_mode(counting_mode);
         this.set_frequency(freq);
-        this.inner.start();
-
         this.inner.enable_outputs();
 
         [Channel::Ch1, Channel::Ch2, Channel::Ch3, Channel::Ch4]
@@ -89,6 +87,10 @@ impl<'d, T: AdvancedInstance4Channel> ComplementaryPwm<'d, T> {
             });
         this.inner.set_autoreload_preload(true);
 
+        // Generate update event so pre-load registers are written to the shadow registers
+        this.inner.generate_update_event();
+        this.inner.start();
+
         this
     }
 
@@ -160,8 +162,8 @@ impl<'d, T: AdvancedInstance4Channel> ComplementaryPwm<'d, T> {
 
     /// Set PWM frequency.
     ///
-    /// Note: when you call this, the max duty value changes, so you will have to
-    /// call `set_duty` on all channels with the duty calculated based on the new max duty.
+    /// Note: that the frequency will not be applied in the timer until an update event
+    /// occurs.
     pub fn set_frequency(&mut self, freq: Hertz) {
         let multiplier = if self.inner.get_counting_mode().is_center_aligned() {
             2u8

embassy-stm32/src/timer/input_capture.rs

@@ -60,6 +60,7 @@ impl<'d, T: GeneralInstance4Channel> InputCapture<'d, T> {
         this.inner.set_counting_mode(counting_mode);
         this.inner.set_tick_freq(freq);
         this.inner.enable_outputs(); // Required for advanced timers, see GeneralInstance4Channel for details
+        this.inner.generate_update_event();
         this.inner.start();
 
         // enable NVIC interrupt

embassy-stm32/src/timer/low_level.rs

@@ -272,6 +272,16 @@ impl<'d, T: CoreInstance> Timer<'d, T> {
         self.regs_core().cr1().modify(|r| r.set_cen(true));
     }
 
+    /// Generate timer update event from software.
+    ///
+    /// Set URS to avoid generating interrupt or DMA request. This update event is only
+    /// used to load value from pre-load registers.
+    pub fn generate_update_event(&self) {
+        self.regs_core().cr1().modify(|r| r.set_urs(vals::Urs::COUNTER_ONLY));
+        self.regs_core().egr().write(|r| r.set_ug(true));
+        self.regs_core().cr1().modify(|r| r.set_urs(vals::Urs::ANY_EVENT));
+    }
+
     /// Stop the timer.
     pub fn stop(&self) {
         self.regs_core().cr1().modify(|r| r.set_cen(false));
@@ -322,10 +332,6 @@ impl<'d, T: CoreInstance> Timer<'d, T> {
                 let regs = self.regs_core();
                 regs.psc().write_value(psc);
                 regs.arr().write(|r| r.set_arr(arr));
-
-                regs.cr1().modify(|r| r.set_urs(vals::Urs::COUNTER_ONLY));
-                regs.egr().write(|r| r.set_ug(true));
-                regs.cr1().modify(|r| r.set_urs(vals::Urs::ANY_EVENT));
             }
             #[cfg(not(stm32l0))]
             TimerBits::Bits32 => {
@@ -335,10 +341,6 @@ impl<'d, T: CoreInstance> Timer<'d, T> {
                 let regs = self.regs_gp32_unchecked();
                 regs.psc().write_value(psc);
                 regs.arr().write_value(arr);
-
-                regs.cr1().modify(|r| r.set_urs(vals::Urs::COUNTER_ONLY));
-                regs.egr().write(|r| r.set_ug(true));
-                regs.cr1().modify(|r| r.set_urs(vals::Urs::ANY_EVENT));
             }
         }
     }

embassy-stm32/src/timer/pwm_input.rs

@@ -47,6 +47,7 @@ impl<'d, T: GeneralInstance4Channel> PwmInput<'d, T> {
         inner.set_counting_mode(CountingMode::EdgeAlignedUp);
         inner.set_tick_freq(freq);
         inner.enable_outputs(); // Required for advanced timers, see GeneralInstance4Channel for details
+        inner.generate_update_event();
         inner.start();
 
         // Configuration steps from ST RM0390 (STM32F446) chapter 17.3.6

embassy-stm32/src/timer/simple_pwm.rs

@@ -198,7 +198,6 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
         this.inner.set_counting_mode(counting_mode);
         this.set_frequency(freq);
         this.inner.enable_outputs(); // Required for advanced timers, see GeneralInstance4Channel for details
-        this.inner.start();
 
         [Channel::Ch1, Channel::Ch2, Channel::Ch3, Channel::Ch4]
             .iter()
@@ -207,6 +206,11 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
 
                 this.inner.set_output_compare_preload(channel, true);
             });
+        this.inner.set_autoreload_preload(true);
+
+        // Generate update event so pre-load registers are written to the shadow registers
+        this.inner.generate_update_event();
+        this.inner.start();
 
         this
     }
@@ -285,8 +289,8 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
 
     /// Set PWM frequency.
     ///
-    /// Note: when you call this, the max duty value changes, so you will have to
-    /// call `set_duty` on all channels with the duty calculated based on the new max duty.
+    /// Note: that the frequency will not be applied in the timer until an update event
+    /// occurs.
     pub fn set_frequency(&mut self, freq: Hertz) {
         // TODO: prevent ARR = u16::MAX?
         let multiplier = if self.inner.get_counting_mode().is_center_aligned() {