Merge branch 'main' into time

Author: xoviat

embassy-stm32/CHANGELOG.md

@@ -8,6 +8,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 ## Unreleased - ReleaseDate
 
 - chore: cleanup low-power add time
+- fix: Allow setting SAI peripheral `frame_length` to `256`
 - fix: flash erase on dual-bank STM32Gxxx
 - feat: Add support for STM32N657X0
 - feat: timer: Add 32-bit timer support to SimplePwm waveform_up method following waveform pattern ([#4717](https://github.com/embassy-rs/embassy/pull/4717))
@@ -59,6 +60,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - adc: reogranize and cleanup somewhat. require sample_time to be passed on conversion
 - fix: stm32/i2c v2 slave: prevent misaligned reads, error false positives, and incorrect counts of bytes read/written
 - feat: add flash support for c0 family ([#4874](https://github.com/embassy-rs/embassy/pull/4874))
+- fix: fixing channel numbers on vbat and vddcore for adc on adc
+- adc: adding disable to vbat
 
 ## 0.4.0 - 2025-08-26
 

embassy-stm32/src/adc/g4.rs

@@ -1,3 +1,5 @@
+#[cfg(stm32g4)]
+use pac::adc::regs::Difsel as DifselReg;
 #[allow(unused)]
 #[cfg(stm32h7)]
 use pac::adc::vals::{Adcaldif, Difsel, Exten};
@@ -179,6 +181,9 @@ impl<T: Instance> super::SealedAnyInstance for T {
             w.set_l(sequence.len() as u8 - 1);
         });
 
+        #[cfg(stm32g4)]
+        let mut difsel = DifselReg::default();
+
         // Configure channels and ranks
         for (_i, ((ch, is_differential), sample_time)) in sequence.enumerate() {
             let sample_time = sample_time.into();
@@ -214,22 +219,25 @@ impl<T: Instance> super::SealedAnyInstance for T {
 
             #[cfg(stm32g4)]
             {
-                T::regs().cr().modify(|w| w.set_aden(false)); // disable adc
-
-                T::regs().difsel().modify(|w| {
-                    w.set_difsel(
+                if ch < 18 {
+                    difsel.set_difsel(
                         ch.into(),
                         if is_differential {
                             Difsel::DIFFERENTIAL
                         } else {
                             Difsel::SINGLE_ENDED
                         },
                     );
-                });
-
-                T::regs().cr().modify(|w| w.set_aden(true)); // enable adc
+                }
             }
         }
+
+        #[cfg(stm32g4)]
+        {
+            T::regs().cr().modify(|w| w.set_aden(false));
+            T::regs().difsel().write_value(difsel);
+            T::enable();
+        }
     }
 }
 
@@ -412,7 +420,6 @@ impl<'d, T: Instance + AnyInstance> Adc<'d, T> {
             NR_INJECTED_RANKS
         );
 
-        T::stop();
         T::enable();
 
         T::regs().jsqr().modify(|w| w.set_jl(N as u8 - 1));

embassy-stm32/src/adc/v3.rs

@@ -65,7 +65,7 @@ impl<T: Instance> super::SealedSpecialConverter<super::Vbat> for T {
 }
 #[cfg(any(adc_h5, adc_h7rs))]
 impl<T: Instance> super::SealedSpecialConverter<super::Vbat> for T {
-    const CHANNEL: u8 = 2;
+    const CHANNEL: u8 = 16;
 }
 #[cfg(adc_u0)]
 impl<T: Instance> super::SealedSpecialConverter<super::Vbat> for T {
@@ -82,7 +82,7 @@ cfg_if! {
         impl<T: Instance> super::AdcChannel<T> for VddCore {}
         impl<T: Instance> super::SealedAdcChannel<T> for VddCore {
             fn channel(&self) -> u8 {
-                6
+                17
             }
         }
     }
@@ -575,6 +575,24 @@ impl<'d, T: Instance> Adc<'d, T> {
         Vbat {}
     }
 
+    pub fn disable_vbat(&self) {
+        cfg_if! {
+            if #[cfg(any(adc_g0, adc_u0))] {
+                T::regs().ccr().modify(|reg| {
+                    reg.set_vbaten(false);
+                });
+            } else if #[cfg(any(adc_h5, adc_h7rs))] {
+                T::common_regs().ccr().modify(|reg| {
+                    reg.set_vbaten(false);
+                });
+            } else {
+                T::common_regs().ccr().modify(|reg| {
+                    reg.set_ch18sel(false);
+                });
+            }
+        }
+    }
+
     /*
     /// Convert a raw sample from the `Temperature` to deg C
     pub fn to_degrees_centigrade(sample: u16) -> f32 {

embassy-stm32/src/sai/mod.rs

@@ -391,7 +391,7 @@ pub struct Config {
     pub frame_sync_polarity: FrameSyncPolarity,
     pub frame_sync_active_level_length: word::U7,
     pub frame_sync_definition: FrameSyncDefinition,
-    pub frame_length: u8,
+    pub frame_length: u16,
     pub clock_strobe: ClockStrobe,
     pub output_drive: OutputDrive,
     pub master_clock_divider: Option<MasterClockDivider>,
@@ -696,7 +696,7 @@ impl<'d, T: Instance, W: word::Word> Sai<'d, T, W> {
             w.set_fspol(config.frame_sync_polarity.fspol());
             w.set_fsdef(config.frame_sync_definition.fsdef());
             w.set_fsall(config.frame_sync_active_level_length.0 as u8 - 1);
-            w.set_frl(config.frame_length - 1);
+            w.set_frl((config.frame_length - 1).try_into().unwrap());
         });
 
         ch.slotr().modify(|w| {

embassy-stm32/src/timer/simple_pwm.rs

@@ -309,7 +309,9 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
     /// Generate a sequence of PWM waveform
     ///
     /// Note:
-    /// you will need to provide corresponding TIMx_UP DMA channel to use this method.
+    /// You will need to provide corresponding `TIMx_UP` DMA channel to use this method.
+    /// Also be aware that embassy timers use one of timers internally. It is possible to
+    /// switch this timer by using `time-driver-timX` feature.
     pub async fn waveform_up(&mut self, dma: Peri<'_, impl super::UpDma<T>>, channel: Channel, duty: &[u16]) {
         #[allow(clippy::let_unit_value)] // eg. stm32f334
         let req = dma.request();
@@ -397,18 +399,23 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
     ///
     /// For example, if using channels 1 through 4, a buffer of 4 update steps might look like:
     ///
+    /// ```rust,ignore
     /// let dma_buf: [u16; 16] = [
     ///     ch1_duty_1, ch2_duty_1, ch3_duty_1, ch4_duty_1, // update 1
     ///     ch1_duty_2, ch2_duty_2, ch3_duty_2, ch4_duty_2, // update 2
     ///     ch1_duty_3, ch2_duty_3, ch3_duty_3, ch4_duty_3, // update 3
     ///     ch1_duty_4, ch2_duty_4, ch3_duty_4, ch4_duty_4, // update 4
     /// ];
+    /// ```
     ///
-    /// Each group of N values (where N = number of channels) is transferred on one update event,
+    /// Each group of `N` values (where `N` is number of channels) is transferred on one update event,
     /// updating the duty cycles of all selected channels simultaneously.
     ///
     /// Note:
-    /// you will need to provide corresponding TIMx_UP DMA channel to use this method.
+    /// You will need to provide corresponding `TIMx_UP` DMA channel to use this method.
+    /// Also be aware that embassy timers use one of timers internally. It is possible to
+    /// switch this timer by using `time-driver-timX` feature.
+    ///
     pub async fn waveform_up_multi_channel(
         &mut self,
         dma: Peri<'_, impl super::UpDma<T>>,

examples/stm32h723/src/bin/spdifrx.rs

@@ -167,7 +167,7 @@ fn new_sai_transmitter<'d>(
     sai_config.slot_count = hal::sai::word::U4(CHANNEL_COUNT as u8);
     sai_config.slot_enable = 0xFFFF; // All slots
     sai_config.data_size = sai::DataSize::Data32;
-    sai_config.frame_length = (CHANNEL_COUNT * 32) as u8;
+    sai_config.frame_length = (CHANNEL_COUNT * 32) as u16;
     sai_config.master_clock_divider = None;
 
     let (sub_block_tx, _) = hal::sai::split_subblocks(sai);