diff --git a/embassy-stm32/CHANGELOG.md b/embassy-stm32/CHANGELOG.md
index 87a8ef7c93..ebcb82d441 100644
--- a/embassy-stm32/CHANGELOG.md
+++ b/embassy-stm32/CHANGELOG.md
@@ -7,6 +7,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 
 ## Unreleased - ReleaseDate
 
+- fix: cycle usart on idle termination
 - fix: Fixed ADC4 enable() for WBA
 - feat: allow use of anyadcchannel for adc4
 - fix: fix incorrect logic for buffered usart transmission complete.
diff --git a/embassy-stm32/src/usart/mod.rs b/embassy-stm32/src/usart/mod.rs
index 0e7da634df..45b09ec00f 100644
--- a/embassy-stm32/src/usart/mod.rs
+++ b/embassy-stm32/src/usart/mod.rs
@@ -765,6 +765,8 @@ impl<'d> UartRx<'d, Async> {
                 w.set_peie(false);
                 // disable idle line interrupt
                 w.set_idleie(false);
+                // disable uart to clear any data present
+                w.set_ue(!enable_idle_line_detection)
             });
             r.cr3().modify(|w| {
                 // disable Error Interrupt: (Frame error, Noise error, Overrun error)
@@ -772,6 +774,8 @@ impl<'d> UartRx<'d, Async> {
                 // disable DMA Rx Request
                 w.set_dmar(false);
             });
+
+            r.cr1().modify(|w| w.set_ue(true));
         });
 
         let ch = self.rx_dma.as_mut().unwrap();