diff --git a/src/chips/nrf51/pac.rs b/src/chips/nrf51/pac.rs index 01d078d..8312db1 100644 --- a/src/chips/nrf51/pac.rs +++ b/src/chips/nrf51/pac.rs @@ -1,4 +1,4 @@ -#![doc = "Peripheral access API (generated using chiptool v0.1.0 (218daa7 2024-01-15))"] +#![doc = "Peripheral access API (generated using chiptool v0.1.0 (4df74f6 2024-11-11))"] #[derive(Copy, Clone, Debug, PartialEq, Eq)] pub enum Interrupt { #[doc = "0 - POWER_CLOCK"] diff --git a/src/chips/nrf52805/pac.rs b/src/chips/nrf52805/pac.rs index db7e86f..283d521 100644 --- a/src/chips/nrf52805/pac.rs +++ b/src/chips/nrf52805/pac.rs @@ -1,4 +1,4 @@ -#![doc = "Peripheral access API (generated using chiptool v0.1.0 (218daa7 2024-01-15))"] +#![doc = "Peripheral access API (generated using chiptool v0.1.0 (4df74f6 2024-11-11))"] #[derive(Copy, Clone, Debug, PartialEq, Eq)] pub enum Interrupt { #[doc = "0 - POWER_CLOCK"] @@ -16765,6 +16765,12 @@ pub mod uicr { assert!(n < 32usize); unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x80usize + n * 4usize) as _) } } + #[doc = "Description collection: Reserved for Nordic MDK"] + #[inline(always)] + pub const fn nrfmdk(self, n: usize) -> crate::common::Reg { + assert!(n < 8usize); + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0100usize + n * 4usize) as _) } + } #[doc = "Description collection: Mapping of the nRESET function (see POWER chapter for details)"] #[inline(always)] pub const fn pselreset( @@ -16812,7 +16818,9 @@ pub mod uicr { impl Pall { #[doc = "Enable"] pub const ENABLED: Self = Self(0x0); - #[doc = "Disable"] + #[doc = "Hardware disable of access port protection for devices where access port protection is controlled by hardware and software"] + pub const HW_DISABLED: Self = Self(0x5a); + #[doc = "Hardware disable of access port protection for devices where access port protection is controlled by hardware"] pub const DISABLED: Self = Self(0xff); } impl Pall { diff --git a/src/chips/nrf52810/pac.rs b/src/chips/nrf52810/pac.rs index efae8fa..16af58e 100644 --- a/src/chips/nrf52810/pac.rs +++ b/src/chips/nrf52810/pac.rs @@ -1,4 +1,4 @@ -#![doc = "Peripheral access API (generated using chiptool v0.1.0 (218daa7 2024-01-15))"] +#![doc = "Peripheral access API (generated using chiptool v0.1.0 (4df74f6 2024-11-11))"] #[derive(Copy, Clone, Debug, PartialEq, Eq)] pub enum Interrupt { #[doc = "0 - POWER_CLOCK"] @@ -150,6 +150,9 @@ pub const FICR: ficr::Ficr = unsafe { ficr::Ficr::from_ptr(0x1000_0000usize as _ pub const UICR: uicr::Uicr = unsafe { uicr::Uicr::from_ptr(0x1000_1000usize as _) }; #[doc = "Block Protect"] pub const BPROT: bprot::Bprot = unsafe { bprot::Bprot::from_ptr(0x4000_0000usize as _) }; +#[doc = "Only for emulation on devices that support hardened AP-PROTECT."] +pub const APPROTECT: approtect::Approtect = + unsafe { approtect::Approtect::from_ptr(0x4000_0000usize as _) }; #[doc = "Clock control"] pub const CLOCK: clock::Clock = unsafe { clock::Clock::from_ptr(0x4000_0000usize as _) }; #[doc = "Power control"] @@ -469,6 +472,141 @@ pub mod aar { } } } +pub mod approtect { + #[doc = "Only for emulation on devices that support hardened AP-PROTECT."] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Approtect { + ptr: *mut u8, + } + unsafe impl Send for Approtect {} + unsafe impl Sync for Approtect {} + impl Approtect { + #[inline(always)] + pub const unsafe fn from_ptr(ptr: *mut ()) -> Self { + Self { ptr: ptr as _ } + } + #[inline(always)] + pub const fn as_ptr(&self) -> *mut () { + self.ptr as _ + } + #[doc = "Software force enable APPROTECT mechanism until next reset."] + #[inline(always)] + pub const fn forceprotect( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0550usize) as _) } + } + #[doc = "Software disable APPROTECT mechanism"] + #[inline(always)] + pub const fn disable(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0558usize) as _) } + } + } + pub mod regs { + #[doc = "Software disable APPROTECT mechanism"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Disable(pub u32); + impl Disable { + #[doc = "Software disable APPROTECT mechanism"] + #[inline(always)] + pub const fn disable(&self) -> super::vals::Disable { + let val = (self.0 >> 0usize) & 0xff; + super::vals::Disable::from_bits(val as u8) + } + #[doc = "Software disable APPROTECT mechanism"] + #[inline(always)] + pub fn set_disable(&mut self, val: super::vals::Disable) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val.to_bits() as u32) & 0xff) << 0usize); + } + } + impl Default for Disable { + #[inline(always)] + fn default() -> Disable { + Disable(0) + } + } + #[doc = "Software force enable APPROTECT mechanism until next reset."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Forceprotect(pub u32); + impl Forceprotect { + #[doc = "Write 0x0 to force enable APPROTECT mechanism"] + #[inline(always)] + pub const fn forceprotect(&self) -> super::vals::Forceprotect { + let val = (self.0 >> 0usize) & 0xff; + super::vals::Forceprotect::from_bits(val as u8) + } + #[doc = "Write 0x0 to force enable APPROTECT mechanism"] + #[inline(always)] + pub fn set_forceprotect(&mut self, val: super::vals::Forceprotect) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val.to_bits() as u32) & 0xff) << 0usize); + } + } + impl Default for Forceprotect { + #[inline(always)] + fn default() -> Forceprotect { + Forceprotect(0) + } + } + } + pub mod vals { + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Disable(pub u8); + impl Disable { + #[doc = "Software disable APPROTECT mechanism"] + pub const SW_DISABLE: Self = Self(0x5a); + } + impl Disable { + pub const fn from_bits(val: u8) -> Disable { + Self(val & 0xff) + } + pub const fn to_bits(self) -> u8 { + self.0 + } + } + impl From for Disable { + #[inline(always)] + fn from(val: u8) -> Disable { + Disable::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: Disable) -> u8 { + Disable::to_bits(val) + } + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Forceprotect(pub u8); + impl Forceprotect { + #[doc = "Software force enable APPROTECT mechanism"] + pub const FORCE: Self = Self(0x0); + } + impl Forceprotect { + pub const fn from_bits(val: u8) -> Forceprotect { + Self(val & 0xff) + } + pub const fn to_bits(self) -> u8 { + self.0 + } + } + impl From for Forceprotect { + #[inline(always)] + fn from(val: u8) -> Forceprotect { + Forceprotect::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: Forceprotect) -> u8 { + Forceprotect::to_bits(val) + } + } + } +} pub mod bprot { #[doc = "Block Protect"] #[derive(Copy, Clone, Eq, PartialEq)] @@ -3869,6 +4007,8 @@ pub mod ficr { pub const QF: Self = Self(0x2000); #[doc = "QCxx - 32-pin QFN"] pub const QC: Self = Self(0x2003); + #[doc = "CAxx - WLCSP"] + pub const CA: Self = Self(0x2004); #[doc = "Unspecified"] pub const UNSPECIFIED: Self = Self(0xffff_ffff); } @@ -3898,6 +4038,10 @@ pub mod ficr { impl Part { #[doc = "nRF52810"] pub const N52810: Self = Self(0x0005_2810); + #[doc = "nRF52811"] + pub const N52811: Self = Self(0x0005_2811); + #[doc = "nRF52832"] + pub const N52832: Self = Self(0x0005_2832); #[doc = "Unspecified"] pub const UNSPECIFIED: Self = Self(0xffff_ffff); } @@ -5615,12 +5759,12 @@ pub mod power { pub const fn as_ptr(&self) -> *mut () { self.ptr as _ } - #[doc = "Enable constant latency mode"] + #[doc = "Enable Constant Latency mode"] #[inline(always)] pub const fn tasks_constlat(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x78usize) as _) } } - #[doc = "Enable low power mode (variable latency)"] + #[doc = "Enable Low-power mode (variable latency)"] #[inline(always)] pub const fn tasks_lowpwr(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x7cusize) as _) } @@ -14572,13 +14716,13 @@ pub mod timer { #[doc = "Description collection: Capture Timer value to CC\\[n\\] register"] #[inline(always)] pub const fn tasks_capture(self, n: usize) -> crate::common::Reg { - assert!(n < 4usize); + assert!(n < 6usize); unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x40usize + n * 4usize) as _) } } #[doc = "Description collection: Compare event on CC\\[n\\] match"] #[inline(always)] pub const fn events_compare(self, n: usize) -> crate::common::Reg { - assert!(n < 4usize); + assert!(n < 6usize); unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0140usize + n * 4usize) as _) } } #[doc = "Shortcuts between local events and tasks"] @@ -14614,7 +14758,7 @@ pub mod timer { #[doc = "Description collection: Capture/Compare register n"] #[inline(always)] pub const fn cc(self, n: usize) -> crate::common::Reg { - assert!(n < 4usize); + assert!(n < 6usize); unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0540usize + n * 4usize) as _) } } } @@ -14650,7 +14794,7 @@ pub mod timer { #[doc = "Write '1' to disable interrupt for event COMPARE\\[0\\]"] #[inline(always)] pub const fn compare(&self, n: usize) -> bool { - assert!(n < 4usize); + assert!(n < 6usize); let offs = 16usize + n * 1usize; let val = (self.0 >> offs) & 0x01; val != 0 @@ -14658,7 +14802,7 @@ pub mod timer { #[doc = "Write '1' to disable interrupt for event COMPARE\\[0\\]"] #[inline(always)] pub fn set_compare(&mut self, n: usize, val: bool) { - assert!(n < 4usize); + assert!(n < 6usize); let offs = 16usize + n * 1usize; self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); } @@ -14723,7 +14867,7 @@ pub mod timer { #[doc = "Shortcut between event COMPARE\\[0\\] and task CLEAR"] #[inline(always)] pub const fn compare_clear(&self, n: usize) -> bool { - assert!(n < 4usize); + assert!(n < 6usize); let offs = 0usize + n * 1usize; let val = (self.0 >> offs) & 0x01; val != 0 @@ -14731,14 +14875,14 @@ pub mod timer { #[doc = "Shortcut between event COMPARE\\[0\\] and task CLEAR"] #[inline(always)] pub fn set_compare_clear(&mut self, n: usize, val: bool) { - assert!(n < 4usize); + assert!(n < 6usize); let offs = 0usize + n * 1usize; self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); } #[doc = "Shortcut between event COMPARE\\[0\\] and task STOP"] #[inline(always)] pub const fn compare_stop(&self, n: usize) -> bool { - assert!(n < 4usize); + assert!(n < 6usize); let offs = 8usize + n * 1usize; let val = (self.0 >> offs) & 0x01; val != 0 @@ -14746,7 +14890,7 @@ pub mod timer { #[doc = "Shortcut between event COMPARE\\[0\\] and task STOP"] #[inline(always)] pub fn set_compare_stop(&mut self, n: usize, val: bool) { - assert!(n < 4usize); + assert!(n < 6usize); let offs = 8usize + n * 1usize; self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); } @@ -18413,7 +18557,7 @@ pub mod uicr { #[doc = "Description collection: Reserved for Nordic firmware design"] #[inline(always)] pub const fn nrffw(self, n: usize) -> crate::common::Reg { - assert!(n < 15usize); + assert!(n < 13usize); unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize + n * 4usize) as _) } } #[doc = "Description collection: Reserved for Nordic hardware design"] @@ -18428,6 +18572,12 @@ pub mod uicr { assert!(n < 32usize); unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x80usize + n * 4usize) as _) } } + #[doc = "Description collection: Reserved for Nordic MDK"] + #[inline(always)] + pub const fn nrfmdk(self, n: usize) -> crate::common::Reg { + assert!(n < 8usize); + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0100usize + n * 4usize) as _) } + } #[doc = "Description collection: Mapping of the nRESET function (see POWER chapter for details)"] #[inline(always)] pub const fn pselreset( @@ -18475,7 +18625,9 @@ pub mod uicr { impl Pall { #[doc = "Enable"] pub const ENABLED: Self = Self(0x0); - #[doc = "Disable"] + #[doc = "Hardware disable of access port protection for devices where access port protection is controlled by hardware and software"] + pub const HW_DISABLED: Self = Self(0x5a); + #[doc = "Hardware disable of access port protection for devices where access port protection is controlled by hardware"] pub const DISABLED: Self = Self(0xff); } impl Pall { diff --git a/src/chips/nrf52811/pac.rs b/src/chips/nrf52811/pac.rs index 392cb13..a2955a9 100644 --- a/src/chips/nrf52811/pac.rs +++ b/src/chips/nrf52811/pac.rs @@ -1,4 +1,4 @@ -#![doc = "Peripheral access API (generated using chiptool v0.1.0 (218daa7 2024-01-15))"] +#![doc = "Peripheral access API (generated using chiptool v0.1.0 (4df74f6 2024-11-11))"] #[derive(Copy, Clone, Debug, PartialEq, Eq)] pub enum Interrupt { #[doc = "0 - POWER_CLOCK"] @@ -7,10 +7,10 @@ pub enum Interrupt { RADIO = 1, #[doc = "2 - UARTE0_UART0"] UARTE0_UART0 = 2, - #[doc = "3 - TWIM0_TWIS0_TWI0_SPIM0_SPIS0_SPI0"] - TWIM0_TWIS0_TWI0_SPIM0_SPIS0_SPI0 = 3, - #[doc = "4 - SPIM1_SPIS1_SPI1"] - SPIM1_SPIS1_SPI1 = 4, + #[doc = "3 - TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1"] + TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1 = 3, + #[doc = "4 - SPIM0_SPIS0_SPI0"] + SPIM0_SPIS0_SPI0 = 4, #[doc = "6 - GPIOTE"] GPIOTE = 6, #[doc = "7 - SAADC"] @@ -68,8 +68,8 @@ mod _vectors { fn POWER_CLOCK(); fn RADIO(); fn UARTE0_UART0(); - fn TWIM0_TWIS0_TWI0_SPIM0_SPIS0_SPI0(); - fn SPIM1_SPIS1_SPI1(); + fn TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1(); + fn SPIM0_SPIS0_SPI0(); fn GPIOTE(); fn SAADC(); fn TIMER0(); @@ -108,10 +108,10 @@ mod _vectors { _handler: UARTE0_UART0, }, Vector { - _handler: TWIM0_TWIS0_TWI0_SPIM0_SPIS0_SPI0, + _handler: TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1, }, Vector { - _handler: SPIM1_SPIS1_SPI1, + _handler: SPIM0_SPIS0_SPI0, }, Vector { _reserved: 0 }, Vector { _handler: GPIOTE }, @@ -148,6 +148,9 @@ mod _vectors { pub const FICR: ficr::Ficr = unsafe { ficr::Ficr::from_ptr(0x1000_0000usize as _) }; #[doc = "User information configuration registers"] pub const UICR: uicr::Uicr = unsafe { uicr::Uicr::from_ptr(0x1000_1000usize as _) }; +#[doc = "Access Port Protection"] +pub const APPROTECT: approtect::Approtect = + unsafe { approtect::Approtect::from_ptr(0x4000_0000usize as _) }; #[doc = "Block Protect"] pub const BPROT: bprot::Bprot = unsafe { bprot::Bprot::from_ptr(0x4000_0000usize as _) }; #[doc = "Clock control"] @@ -161,11 +164,11 @@ pub const UART0: uart::Uart = unsafe { uart::Uart::from_ptr(0x4000_2000usize as #[doc = "UART with EasyDMA"] pub const UARTE0: uarte::Uarte = unsafe { uarte::Uarte::from_ptr(0x4000_2000usize as _) }; #[doc = "Serial Peripheral Interface 0"] -pub const SPI0: spi::Spi = unsafe { spi::Spi::from_ptr(0x4000_3000usize as _) }; +pub const SPI1: spi1::Spi1 = unsafe { spi1::Spi1::from_ptr(0x4000_3000usize as _) }; #[doc = "Serial Peripheral Interface Master with EasyDMA 0"] -pub const SPIM0: spim::Spim = unsafe { spim::Spim::from_ptr(0x4000_3000usize as _) }; +pub const SPIM1: spim1::Spim1 = unsafe { spim1::Spim1::from_ptr(0x4000_3000usize as _) }; #[doc = "SPI Slave 0"] -pub const SPIS0: spis::Spis = unsafe { spis::Spis::from_ptr(0x4000_3000usize as _) }; +pub const SPIS1: spis1::Spis1 = unsafe { spis1::Spis1::from_ptr(0x4000_3000usize as _) }; #[doc = "I2C compatible Two-Wire Interface"] pub const TWI0: twi::Twi = unsafe { twi::Twi::from_ptr(0x4000_3000usize as _) }; #[doc = "I2C compatible Two-Wire Master Interface with EasyDMA"] @@ -173,11 +176,11 @@ pub const TWIM0: twim::Twim = unsafe { twim::Twim::from_ptr(0x4000_3000usize as #[doc = "I2C compatible Two-Wire Slave Interface with EasyDMA"] pub const TWIS0: twis::Twis = unsafe { twis::Twis::from_ptr(0x4000_3000usize as _) }; #[doc = "Serial Peripheral Interface 1"] -pub const SPI1: spi::Spi = unsafe { spi::Spi::from_ptr(0x4000_4000usize as _) }; +pub const SPI0: spi1::Spi1 = unsafe { spi1::Spi1::from_ptr(0x4000_4000usize as _) }; #[doc = "Serial Peripheral Interface Master with EasyDMA 1"] -pub const SPIM1: spim::Spim = unsafe { spim::Spim::from_ptr(0x4000_4000usize as _) }; +pub const SPIM0: spim1::Spim1 = unsafe { spim1::Spim1::from_ptr(0x4000_4000usize as _) }; #[doc = "SPI Slave 1"] -pub const SPIS1: spis::Spis = unsafe { spis::Spis::from_ptr(0x4000_4000usize as _) }; +pub const SPIS0: spis1::Spis1 = unsafe { spis1::Spis1::from_ptr(0x4000_4000usize as _) }; #[doc = "GPIO Tasks and Events"] pub const GPIOTE: gpiote::Gpiote = unsafe { gpiote::Gpiote::from_ptr(0x4000_6000usize as _) }; #[doc = "Analog to Digital Converter"] @@ -198,7 +201,7 @@ pub const RNG: rng::Rng = unsafe { rng::Rng::from_ptr(0x4000_d000usize as _) }; pub const ECB: ecb::Ecb = unsafe { ecb::Ecb::from_ptr(0x4000_e000usize as _) }; #[doc = "Accelerated Address Resolver"] pub const AAR: aar::Aar = unsafe { aar::Aar::from_ptr(0x4000_f000usize as _) }; -#[doc = "AES CCM Mode Encryption"] +#[doc = "AES CCM mode encryption"] pub const CCM: ccm::Ccm = unsafe { ccm::Ccm::from_ptr(0x4000_f000usize as _) }; #[doc = "Watchdog Timer"] pub const WDT: wdt::Wdt = unsafe { wdt::Wdt::from_ptr(0x4001_0000usize as _) }; @@ -208,11 +211,11 @@ pub const RTC1: rtc::Rtc = unsafe { rtc::Rtc::from_ptr(0x4001_1000usize as _) }; pub const QDEC: qdec::Qdec = unsafe { qdec::Qdec::from_ptr(0x4001_2000usize as _) }; #[doc = "Comparator"] pub const COMP: comp::Comp = unsafe { comp::Comp::from_ptr(0x4001_3000usize as _) }; -#[doc = "Event Generator Unit 0"] +#[doc = "Event generator unit 0"] pub const EGU0: egu::Egu = unsafe { egu::Egu::from_ptr(0x4001_4000usize as _) }; #[doc = "Software interrupt 0"] pub const SWI0: swi::Swi = unsafe { swi::Swi::from_ptr(0x4001_4000usize as _) }; -#[doc = "Event Generator Unit 1"] +#[doc = "Event generator unit 1"] pub const EGU1: egu::Egu = unsafe { egu::Egu::from_ptr(0x4001_5000usize as _) }; #[doc = "Software interrupt 1"] pub const SWI1: swi::Swi = unsafe { swi::Swi::from_ptr(0x4001_5000usize as _) }; @@ -475,6 +478,141 @@ pub mod aar { } } } +pub mod approtect { + #[doc = "Access Port Protection"] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Approtect { + ptr: *mut u8, + } + unsafe impl Send for Approtect {} + unsafe impl Sync for Approtect {} + impl Approtect { + #[inline(always)] + pub const unsafe fn from_ptr(ptr: *mut ()) -> Self { + Self { ptr: ptr as _ } + } + #[inline(always)] + pub const fn as_ptr(&self) -> *mut () { + self.ptr as _ + } + #[doc = "Software force enable APPROTECT mechanism until next reset."] + #[inline(always)] + pub const fn forceprotect( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0550usize) as _) } + } + #[doc = "Software disable APPROTECT mechanism"] + #[inline(always)] + pub const fn disable(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0558usize) as _) } + } + } + pub mod regs { + #[doc = "Software disable APPROTECT mechanism"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Disable(pub u32); + impl Disable { + #[doc = "Software disable APPROTECT mechanism"] + #[inline(always)] + pub const fn disable(&self) -> super::vals::Disable { + let val = (self.0 >> 0usize) & 0xff; + super::vals::Disable::from_bits(val as u8) + } + #[doc = "Software disable APPROTECT mechanism"] + #[inline(always)] + pub fn set_disable(&mut self, val: super::vals::Disable) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val.to_bits() as u32) & 0xff) << 0usize); + } + } + impl Default for Disable { + #[inline(always)] + fn default() -> Disable { + Disable(0) + } + } + #[doc = "Software force enable APPROTECT mechanism until next reset."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Forceprotect(pub u32); + impl Forceprotect { + #[doc = "Write 0x0 to force enable APPROTECT mechanism"] + #[inline(always)] + pub const fn forceprotect(&self) -> super::vals::Forceprotect { + let val = (self.0 >> 0usize) & 0xff; + super::vals::Forceprotect::from_bits(val as u8) + } + #[doc = "Write 0x0 to force enable APPROTECT mechanism"] + #[inline(always)] + pub fn set_forceprotect(&mut self, val: super::vals::Forceprotect) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val.to_bits() as u32) & 0xff) << 0usize); + } + } + impl Default for Forceprotect { + #[inline(always)] + fn default() -> Forceprotect { + Forceprotect(0) + } + } + } + pub mod vals { + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Disable(pub u8); + impl Disable { + #[doc = "Software disable APPROTECT mechanism"] + pub const SW_DISABLE: Self = Self(0x5a); + } + impl Disable { + pub const fn from_bits(val: u8) -> Disable { + Self(val & 0xff) + } + pub const fn to_bits(self) -> u8 { + self.0 + } + } + impl From for Disable { + #[inline(always)] + fn from(val: u8) -> Disable { + Disable::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: Disable) -> u8 { + Disable::to_bits(val) + } + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Forceprotect(pub u8); + impl Forceprotect { + #[doc = "Software force enable APPROTECT mechanism"] + pub const FORCE: Self = Self(0x0); + } + impl Forceprotect { + pub const fn from_bits(val: u8) -> Forceprotect { + Self(val & 0xff) + } + pub const fn to_bits(self) -> u8 { + self.0 + } + } + impl From for Forceprotect { + #[inline(always)] + fn from(val: u8) -> Forceprotect { + Forceprotect::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: Forceprotect) -> u8 { + Forceprotect::to_bits(val) + } + } + } +} pub mod bprot { #[doc = "Block Protect"] #[derive(Copy, Clone, Eq, PartialEq)] @@ -1121,7 +1259,7 @@ pub mod bprot { } } pub mod ccm { - #[doc = "AES CCM Mode Encryption"] + #[doc = "AES CCM mode encryption"] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Ccm { ptr: *mut u8, @@ -1137,7 +1275,7 @@ pub mod ccm { pub const fn as_ptr(&self) -> *mut () { self.ptr as _ } - #[doc = "Start generation of key-stream. This operation will stop by itself when completed."] + #[doc = "Start generation of keystream. This operation will stop by itself when completed."] #[inline(always)] pub const fn tasks_ksgen(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } @@ -1157,7 +1295,7 @@ pub mod ccm { pub const fn tasks_rateoverride(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } } - #[doc = "Key-stream generation complete"] + #[doc = "Keystream generation complete"] #[inline(always)] pub const fn events_endksgen(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0100usize) as _) } @@ -1202,7 +1340,7 @@ pub mod ccm { pub const fn mode(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0504usize) as _) } } - #[doc = "Pointer to data structure holding AES key and NONCE vector"] + #[doc = "Pointer to data structure holding the AES key and the NONCE vector"] #[inline(always)] pub const fn cnfptr(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0508usize) as _) } @@ -1222,7 +1360,7 @@ pub mod ccm { pub const fn scratchptr(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0514usize) as _) } } - #[doc = "Length of key-stream generated when MODE.LENGTH = Extended."] + #[doc = "Length of keystream generated when MODE.LENGTH = Extended"] #[inline(always)] pub const fn maxpacketsize( self, @@ -1306,18 +1444,18 @@ pub mod ccm { Inten(0) } } - #[doc = "Length of key-stream generated when MODE.LENGTH = Extended."] + #[doc = "Length of keystream generated when MODE.LENGTH = Extended"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Maxpacketsize(pub u32); impl Maxpacketsize { - #[doc = "Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted."] + #[doc = "Length of keystream generated when MODE.LENGTH = Extended. This value must be greater than or equal to the subsequent packet payload to be encrypted/decrypted."] #[inline(always)] pub const fn maxpacketsize(&self) -> u8 { let val = (self.0 >> 0usize) & 0xff; val as u8 } - #[doc = "Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted."] + #[doc = "Length of keystream generated when MODE.LENGTH = Extended. This value must be greater than or equal to the subsequent packet payload to be encrypted/decrypted."] #[inline(always)] pub fn set_maxpacketsize(&mut self, val: u8) { self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); @@ -1357,13 +1495,13 @@ pub mod ccm { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Mode(pub u32); impl Mode { - #[doc = "The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered."] + #[doc = "The mode of operation to be used. Settings in this register apply whenever either the KSGEN task or the CRYPT task is triggered."] #[inline(always)] pub const fn mode(&self) -> super::vals::Mode { let val = (self.0 >> 0usize) & 0x01; super::vals::Mode::from_bits(val as u8) } - #[doc = "The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered."] + #[doc = "The mode of operation to be used. Settings in this register apply whenever either the KSGEN task or the CRYPT task is triggered."] #[inline(always)] pub fn set_mode(&mut self, val: super::vals::Mode) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); @@ -1404,13 +1542,13 @@ pub mod ccm { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Rateoverride(pub u32); impl Rateoverride { - #[doc = "Data rate override setting."] + #[doc = "Data rate override setting"] #[inline(always)] pub const fn rateoverride(&self) -> super::vals::Rateoverride { let val = (self.0 >> 0usize) & 0x03; super::vals::Rateoverride::from_bits(val as u8) } - #[doc = "Data rate override setting."] + #[doc = "Data rate override setting"] #[inline(always)] pub fn set_rateoverride(&mut self, val: super::vals::Rateoverride) { self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); @@ -1454,9 +1592,9 @@ pub mod ccm { _1MBIT = 0x0, #[doc = "2 Mbps"] _2MBIT = 0x01, - #[doc = "125 Kbps"] + #[doc = "125 kbps"] _125KBPS = 0x02, - #[doc = "500 Kbps"] + #[doc = "500 kbps"] _500KBPS = 0x03, } impl Datarate { @@ -1516,9 +1654,9 @@ pub mod ccm { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Length { - #[doc = "Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packet payloads up to 27 bytes will be generated."] + #[doc = "Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A keystream for packet payloads up to 27 bytes will be generated."] DEFAULT = 0x0, - #[doc = "Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packet payloads up to MAXPACKETSIZE bytes will be generated."] + #[doc = "Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A keystream for packet payloads up to MAXPACKETSIZE bytes will be generated."] EXTENDED = 0x01, } impl Length { @@ -1610,9 +1748,9 @@ pub mod ccm { _1MBIT = 0x0, #[doc = "2 Mbps"] _2MBIT = 0x01, - #[doc = "125 Kbps"] + #[doc = "125 kbps"] _125KBPS = 0x02, - #[doc = "500 Kbps"] + #[doc = "500 kbps"] _500KBPS = 0x03, } impl Rateoverride { @@ -2981,7 +3119,7 @@ pub mod ecb { } } pub mod egu { - #[doc = "Event Generator Unit 0"] + #[doc = "Event generator unit 0"] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Egu { ptr: *mut u8, @@ -7913,7 +8051,7 @@ pub mod radio { pub const fn events_framestart(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0138usize) as _) } } - #[doc = "Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register"] + #[doc = "Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register."] #[inline(always)] pub const fn events_edend(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x013cusize) as _) } @@ -7958,7 +8096,12 @@ pub mod radio { pub const fn events_mhrmatch(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x015cusize) as _) } } - #[doc = "Generated when last bit is sent on air"] + #[doc = "Preamble indicator"] + #[inline(always)] + pub const fn events_sync(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0168usize) as _) } + } + #[doc = "Generated when last bit is sent on air, or received from air"] #[inline(always)] pub const fn events_phyend(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x016cusize) as _) } @@ -8162,7 +8305,7 @@ pub mod radio { } #[doc = "IEEE 802.15.4 energy detect level"] #[inline(always)] - pub const fn edsample(self) -> crate::common::Reg { + pub const fn edsample(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0668usize) as _) } } #[doc = "IEEE 802.15.4 clear channel assessment control"] @@ -8330,13 +8473,13 @@ pub mod radio { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Crccnf(pub u32); impl Crccnf { - #[doc = "CRC length in number of bytes."] + #[doc = "CRC length in number of bytes For MODE Ble_LR125Kbit and Ble_LR500Kbit, only LEN set to 3 is supported"] #[inline(always)] pub const fn len(&self) -> super::vals::Len { let val = (self.0 >> 0usize) & 0x03; super::vals::Len::from_bits(val as u8) } - #[doc = "CRC length in number of bytes."] + #[doc = "CRC length in number of bytes For MODE Ble_LR125Kbit and Ble_LR500Kbit, only LEN set to 3 is supported"] #[inline(always)] pub fn set_len(&mut self, val: super::vals::Len) { self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); @@ -8479,25 +8622,25 @@ pub mod radio { pub fn set_ctetimevalidrange(&mut self, val: super::vals::Ctetimevalidrange) { self.0 = (self.0 & !(0x03 << 6usize)) | (((val.to_bits() as u32) & 0x03) << 6usize); } - #[doc = "Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set"] + #[doc = "Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set."] #[inline(always)] pub const fn cteinlinerxmode1us(&self) -> super::vals::Cteinlinerxmode1us { let val = (self.0 >> 10usize) & 0x07; super::vals::Cteinlinerxmode1us::from_bits(val as u8) } - #[doc = "Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set"] + #[doc = "Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set."] #[inline(always)] pub fn set_cteinlinerxmode1us(&mut self, val: super::vals::Cteinlinerxmode1us) { self.0 = (self.0 & !(0x07 << 10usize)) | (((val.to_bits() as u32) & 0x07) << 10usize); } - #[doc = "Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set"] + #[doc = "Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set."] #[inline(always)] pub const fn cteinlinerxmode2us(&self) -> super::vals::Cteinlinerxmode2us { let val = (self.0 >> 13usize) & 0x07; super::vals::Cteinlinerxmode2us::from_bits(val as u8) } - #[doc = "Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set"] + #[doc = "Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set."] #[inline(always)] pub fn set_cteinlinerxmode2us(&mut self, val: super::vals::Cteinlinerxmode2us) { self.0 = @@ -9080,13 +9223,13 @@ pub mod radio { pub fn set_frequency(&mut self, val: u8) { self.0 = (self.0 & !(0x7f << 0usize)) | (((val as u32) & 0x7f) << 0usize); } - #[doc = "Channel map selection."] + #[doc = "Channel map selection"] #[inline(always)] pub const fn map(&self) -> super::vals::Map { let val = (self.0 >> 8usize) & 0x01; super::vals::Map::from_bits(val as u8) } - #[doc = "Channel map selection."] + #[doc = "Channel map selection"] #[inline(always)] pub fn set_map(&mut self, val: super::vals::Map) { self.0 = (self.0 & !(0x01 << 8usize)) | (((val.to_bits() as u32) & 0x01) << 8usize); @@ -9334,6 +9477,17 @@ pub mod radio { pub fn set_mhrmatch(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); } + #[doc = "Write '1' to disable interrupt for event SYNC"] + #[inline(always)] + pub const fn sync(&self) -> bool { + let val = (self.0 >> 26usize) & 0x01; + val != 0 + } + #[doc = "Write '1' to disable interrupt for event SYNC"] + #[inline(always)] + pub fn set_sync(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); + } #[doc = "Write '1' to disable interrupt for event PHYEND"] #[inline(always)] pub const fn phyend(&self) -> bool { @@ -9448,35 +9602,35 @@ pub mod radio { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Pcnf0(pub u32); impl Pcnf0 { - #[doc = "Length on air of LENGTH field in number of bits."] + #[doc = "Length on air of LENGTH field in number of bits"] #[inline(always)] pub const fn lflen(&self) -> u8 { let val = (self.0 >> 0usize) & 0x0f; val as u8 } - #[doc = "Length on air of LENGTH field in number of bits."] + #[doc = "Length on air of LENGTH field in number of bits"] #[inline(always)] pub fn set_lflen(&mut self, val: u8) { self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); } - #[doc = "Length on air of S0 field in number of bytes."] + #[doc = "Length on air of S0 field in number of bytes"] #[inline(always)] pub const fn s0len(&self) -> bool { let val = (self.0 >> 8usize) & 0x01; val != 0 } - #[doc = "Length on air of S0 field in number of bytes."] + #[doc = "Length on air of S0 field in number of bytes"] #[inline(always)] pub fn set_s0len(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); } - #[doc = "Length on air of S1 field in number of bits."] + #[doc = "Length on air of S1 field in number of bits"] #[inline(always)] pub const fn s1len(&self) -> u8 { let val = (self.0 >> 16usize) & 0x0f; val as u8 } - #[doc = "Length on air of S1 field in number of bits."] + #[doc = "Length on air of S1 field in number of bits"] #[inline(always)] pub fn set_s1len(&mut self, val: u8) { self.0 = (self.0 & !(0x0f << 16usize)) | (((val as u32) & 0x0f) << 16usize); @@ -9788,13 +9942,13 @@ pub mod radio { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Rssisample(pub u32); impl Rssisample { - #[doc = "RSSI sample"] + #[doc = "RSSI sample."] #[inline(always)] pub const fn rssisample(&self) -> u8 { let val = (self.0 >> 0usize) & 0x7f; val as u8 } - #[doc = "RSSI sample"] + #[doc = "RSSI sample."] #[inline(always)] pub fn set_rssisample(&mut self, val: u8) { self.0 = (self.0 & !(0x7f << 0usize)) | (((val as u32) & 0x7f) << 0usize); @@ -10225,13 +10379,13 @@ pub mod radio { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Switchpattern(pub u32); impl Switchpattern { - #[doc = "Fill array of GPIO patterns for antenna control"] + #[doc = "Fill array of GPIO patterns for antenna control."] #[inline(always)] pub const fn switchpattern(&self) -> u8 { let val = (self.0 >> 0usize) & 0xff; val as u8 } - #[doc = "Fill array of GPIO patterns for antenna control"] + #[doc = "Fill array of GPIO patterns for antenna control."] #[inline(always)] pub fn set_switchpattern(&mut self, val: u8) { self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); @@ -10248,13 +10402,13 @@ pub mod radio { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Tifs(pub u32); impl Tifs { - #[doc = "Interframe spacing in us"] + #[doc = "Interframe spacing in us."] #[inline(always)] pub const fn tifs(&self) -> u16 { let val = (self.0 >> 0usize) & 0x03ff; val as u16 } - #[doc = "Interframe spacing in us"] + #[doc = "Interframe spacing in us."] #[inline(always)] pub fn set_tifs(&mut self, val: u16) { self.0 = (self.0 & !(0x03ff << 0usize)) | (((val as u32) & 0x03ff) << 0usize); @@ -10356,9 +10510,9 @@ pub mod radio { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Cistat { - #[doc = "Frame is received at 125kbps"] + #[doc = "Frame is received at 125 kbps"] LR125KBIT = 0x0, - #[doc = "Frame is received at 500kbps"] + #[doc = "Frame is received at 500 kbps"] LR500KBIT = 0x01, _RESERVED_2 = 0x02, _RESERVED_3 = 0x03, @@ -10449,17 +10603,17 @@ pub mod radio { #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Cteinlinerxmode1us { _RESERVED_0 = 0x0, - #[doc = "4us"] + #[doc = "4 us"] _4US = 0x01, - #[doc = "2us"] + #[doc = "2 us"] _2US = 0x02, - #[doc = "1us"] + #[doc = "1 us"] _1US = 0x03, - #[doc = "0.5us"] + #[doc = "0.5 us"] _500NS = 0x04, - #[doc = "0.25us"] + #[doc = "0.25 us"] _250NS = 0x05, - #[doc = "0.125us"] + #[doc = "0.125 us"] _125NS = 0x06, _RESERVED_7 = 0x07, } @@ -10489,17 +10643,17 @@ pub mod radio { #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Cteinlinerxmode2us { _RESERVED_0 = 0x0, - #[doc = "4us"] + #[doc = "4 us"] _4US = 0x01, - #[doc = "2us"] + #[doc = "2 us"] _2US = 0x02, - #[doc = "1us"] + #[doc = "1 us"] _1US = 0x03, - #[doc = "0.5us"] + #[doc = "0.5 us"] _500NS = 0x04, - #[doc = "0.25us"] + #[doc = "0.25 us"] _250NS = 0x05, - #[doc = "0.125us"] + #[doc = "0.125 us"] _125NS = 0x06, _RESERVED_7 = 0x07, } @@ -10528,11 +10682,11 @@ pub mod radio { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Ctetimevalidrange { - #[doc = "20 in 8us unit (default) Set to 20 if parsed CTETime is larger han 20"] + #[doc = "20 in 8 us unit (default) Set to 20 if parsed CTETime is larger than 20"] _20 = 0x0, - #[doc = "31 in 8us unit"] + #[doc = "31 in 8 us unit"] _31 = 0x01, - #[doc = "63 in 8us unit"] + #[doc = "63 in 8 us unit"] _63 = 0x02, _RESERVED_3 = 0x03, } @@ -10866,7 +11020,7 @@ pub mod radio { pub enum Ru { #[doc = "Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51"] DEFAULT = 0x0, - #[doc = "Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specification for more information"] + #[doc = "Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specifications for more information"] FAST = 0x01, } impl Ru { @@ -11109,17 +11263,17 @@ pub mod radio { #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Tsamplespacing { _RESERVED_0 = 0x0, - #[doc = "4us"] + #[doc = "4 us"] _4US = 0x01, - #[doc = "2us"] + #[doc = "2 us"] _2US = 0x02, - #[doc = "1us"] + #[doc = "1 us"] _1US = 0x03, - #[doc = "0.5us"] + #[doc = "0.5 us"] _500NS = 0x04, - #[doc = "0.25us"] + #[doc = "0.25 us"] _250NS = 0x05, - #[doc = "0.125us"] + #[doc = "0.125 us"] _125NS = 0x06, _RESERVED_7 = 0x07, } @@ -11149,17 +11303,17 @@ pub mod radio { #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Tsamplespacingref { _RESERVED_0 = 0x0, - #[doc = "4us"] + #[doc = "4 us"] _4US = 0x01, - #[doc = "2us"] + #[doc = "2 us"] _2US = 0x02, - #[doc = "1us"] + #[doc = "1 us"] _1US = 0x03, - #[doc = "0.5us"] + #[doc = "0.5 us"] _500NS = 0x04, - #[doc = "0.25us"] + #[doc = "0.25 us"] _250NS = 0x05, - #[doc = "0.125us"] + #[doc = "0.125 us"] _125NS = 0x06, _RESERVED_7 = 0x07, } @@ -11189,11 +11343,11 @@ pub mod radio { #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Tswitchspacing { _RESERVED_0 = 0x0, - #[doc = "4us"] + #[doc = "4 us"] _4US = 0x01, - #[doc = "2us"] + #[doc = "2 us"] _2US = 0x02, - #[doc = "1us"] + #[doc = "1 us"] _1US = 0x03, _RESERVED_4 = 0x04, _RESERVED_5 = 0x05, @@ -13519,7 +13673,7 @@ pub mod shared { } } } -pub mod spi { +pub mod spi1 { #[doc = "Unspecified"] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Psel { @@ -13558,12 +13712,12 @@ pub mod spi { } #[doc = "Serial Peripheral Interface 0"] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Spi { + pub struct Spi1 { ptr: *mut u8, } - unsafe impl Send for Spi {} - unsafe impl Sync for Spi {} - impl Spi { + unsafe impl Send for Spi1 {} + unsafe impl Sync for Spi1 {} + impl Spi1 { #[inline(always)] pub const unsafe fn from_ptr(ptr: *mut ()) -> Self { Self { ptr: ptr as _ } @@ -13957,7 +14111,7 @@ pub mod spi { } } } -pub mod spim { +pub mod spim1 { #[doc = "Unspecified"] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Psel { @@ -14033,12 +14187,12 @@ pub mod spim { } #[doc = "Serial Peripheral Interface Master with EasyDMA 0"] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Spim { + pub struct Spim1 { ptr: *mut u8, } - unsafe impl Send for Spim {} - unsafe impl Sync for Spim {} - impl Spim { + unsafe impl Send for Spim1 {} + unsafe impl Sync for Spim1 {} + impl Spim1 { #[inline(always)] pub const unsafe fn from_ptr(ptr: *mut ()) -> Self { Self { ptr: ptr as _ } @@ -14765,7 +14919,7 @@ pub mod spim { } } } -pub mod spis { +pub mod spis1 { #[doc = "Unspecified"] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Psel { @@ -14846,12 +15000,12 @@ pub mod spis { } #[doc = "SPI Slave 0"] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Spis { + pub struct Spis1 { ptr: *mut u8, } - unsafe impl Send for Spis {} - unsafe impl Sync for Spis {} - impl Spis { + unsafe impl Send for Spis1 {} + unsafe impl Sync for Spis1 {} + impl Spis1 { #[inline(always)] pub const unsafe fn from_ptr(ptr: *mut ()) -> Self { Self { ptr: ptr as _ } @@ -15265,25 +15419,25 @@ pub mod spis { impl Status { #[doc = "TX buffer over-read detected, and prevented"] #[inline(always)] - pub const fn overread(&self) -> bool { + pub const fn overread(&self) -> super::vals::Overread { let val = (self.0 >> 0usize) & 0x01; - val != 0 + super::vals::Overread::from_bits(val as u8) } #[doc = "TX buffer over-read detected, and prevented"] #[inline(always)] - pub fn set_overread(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + pub fn set_overread(&mut self, val: super::vals::Overread) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); } #[doc = "RX buffer overflow detected, and prevented"] #[inline(always)] - pub const fn overflow(&self) -> bool { + pub const fn overflow(&self) -> super::vals::Overflow { let val = (self.0 >> 1usize) & 0x01; - val != 0 + super::vals::Overflow::from_bits(val as u8) } #[doc = "RX buffer overflow detected, and prevented"] #[inline(always)] - pub fn set_overflow(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + pub fn set_overflow(&mut self, val: super::vals::Overflow) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val.to_bits() as u32) & 0x01) << 1usize); } } impl Default for Status { @@ -15499,6 +15653,66 @@ pub mod spis { } #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum Overflow { + #[doc = "Read: error not present"] + NOT_PRESENT = 0x0, + #[doc = "Read: error present"] + R_PRESENT_W_CLEAR = 0x01, + } + impl Overflow { + #[inline(always)] + pub const fn from_bits(val: u8) -> Overflow { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for Overflow { + #[inline(always)] + fn from(val: u8) -> Overflow { + Overflow::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: Overflow) -> u8 { + Overflow::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum Overread { + #[doc = "Read: error not present"] + NOT_PRESENT = 0x0, + #[doc = "Read: error present"] + R_PRESENT_W_CLEAR = 0x01, + } + impl Overread { + #[inline(always)] + pub const fn from_bits(val: u8) -> Overread { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for Overread { + #[inline(always)] + fn from(val: u8) -> Overread { + Overread::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: Overread) -> u8 { + Overread::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum RxdListList { #[doc = "Disable EasyDMA list"] DISABLED = 0x0, @@ -20072,6 +20286,12 @@ pub mod uicr { assert!(n < 32usize); unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x80usize + n * 4usize) as _) } } + #[doc = "Description collection: Reserved for Nordic MDK"] + #[inline(always)] + pub const fn nrfmdk(self, n: usize) -> crate::common::Reg { + assert!(n < 8usize); + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0100usize + n * 4usize) as _) } + } #[doc = "Description collection: Mapping of the nRESET function (see POWER chapter for details)"] #[inline(always)] pub const fn pselreset( @@ -20119,7 +20339,9 @@ pub mod uicr { impl Pall { #[doc = "Enable"] pub const ENABLED: Self = Self(0x0); - #[doc = "Disable"] + #[doc = "Hardware disable of access port protection for devices where access port protection is controlled by hardware and software"] + pub const HW_DISABLED: Self = Self(0x5a); + #[doc = "Hardware disable of access port protection for devices where access port protection is controlled by hardware"] pub const DISABLED: Self = Self(0xff); } impl Pall { diff --git a/src/chips/nrf52820/pac.rs b/src/chips/nrf52820/pac.rs index 2cc9c87..5485320 100644 --- a/src/chips/nrf52820/pac.rs +++ b/src/chips/nrf52820/pac.rs @@ -1,4 +1,4 @@ -#![doc = "Peripheral access API (generated using chiptool v0.1.0 (218daa7 2024-01-15))"] +#![doc = "Peripheral access API (generated using chiptool v0.1.0 (4df74f6 2024-11-11))"] #[derive(Copy, Clone, Debug, PartialEq, Eq)] pub enum Interrupt { #[doc = "0 - POWER_CLOCK"] @@ -218,7 +218,7 @@ pub const RNG: rng::Rng = unsafe { rng::Rng::from_ptr(0x4000_d000usize as _) }; pub const ECB: ecb::Ecb = unsafe { ecb::Ecb::from_ptr(0x4000_e000usize as _) }; #[doc = "Accelerated Address Resolver"] pub const AAR: aar::Aar = unsafe { aar::Aar::from_ptr(0x4000_f000usize as _) }; -#[doc = "AES CCM Mode Encryption"] +#[doc = "AES CCM mode encryption"] pub const CCM: ccm::Ccm = unsafe { ccm::Ccm::from_ptr(0x4000_f000usize as _) }; #[doc = "Watchdog Timer"] pub const WDT: wdt::Wdt = unsafe { wdt::Wdt::from_ptr(0x4001_0000usize as _) }; @@ -550,7 +550,7 @@ pub mod acl { pub const fn addr(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } - #[doc = "Description cluster: Size of region to protect counting from address ACL\\[n\\].ADDR. Write '0' as no effect."] + #[doc = "Description cluster: Size of region to protect counting from address ACL\\[n\\].ADDR. Writing a '0' has no effect."] #[inline(always)] pub const fn size(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } @@ -567,24 +567,24 @@ pub mod acl { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Perm(pub u32); impl Perm { - #[doc = "Configure write and erase permissions for region n. Write '0' has no effect."] + #[doc = "Configure write and erase permissions for region n. Writing a '0' has no effect."] #[inline(always)] pub const fn write(&self) -> super::vals::Write { let val = (self.0 >> 1usize) & 0x01; super::vals::Write::from_bits(val as u8) } - #[doc = "Configure write and erase permissions for region n. Write '0' has no effect."] + #[doc = "Configure write and erase permissions for region n. Writing a '0' has no effect."] #[inline(always)] pub fn set_write(&mut self, val: super::vals::Write) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val.to_bits() as u32) & 0x01) << 1usize); } - #[doc = "Configure read permissions for region n. Write '0' has no effect."] + #[doc = "Configure read permissions for region n. Writing a '0' has no effect."] #[inline(always)] pub const fn read(&self) -> super::vals::Read { let val = (self.0 >> 2usize) & 0x01; super::vals::Read::from_bits(val as u8) } - #[doc = "Configure read permissions for region n. Write '0' has no effect."] + #[doc = "Configure read permissions for region n. Writing a '0' has no effect."] #[inline(always)] pub fn set_read(&mut self, val: super::vals::Read) { self.0 = (self.0 & !(0x01 << 2usize)) | (((val.to_bits() as u32) & 0x01) << 2usize); @@ -601,9 +601,9 @@ pub mod acl { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Read { - #[doc = "Allow read instructions to region n"] + #[doc = "Allow read instructions to region n."] ENABLE = 0x0, - #[doc = "Block read instructions to region n"] + #[doc = "Block read instructions to region n."] DISABLE = 0x01, } impl Read { @@ -631,9 +631,9 @@ pub mod acl { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Write { - #[doc = "Allow write and erase instructions to region n"] + #[doc = "Allow write and erase instructions to region n."] ENABLE = 0x0, - #[doc = "Block write and erase instructions to region n"] + #[doc = "Block write and erase instructions to region n."] DISABLE = 0x01, } impl Write { @@ -796,7 +796,7 @@ pub mod approtect { } } pub mod ccm { - #[doc = "AES CCM Mode Encryption"] + #[doc = "AES CCM mode encryption"] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Ccm { ptr: *mut u8, @@ -877,7 +877,7 @@ pub mod ccm { pub const fn mode(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0504usize) as _) } } - #[doc = "Pointer to data structure holding AES key and NONCE vector"] + #[doc = "Pointer to data structure holding the AES key and the NONCE vector"] #[inline(always)] pub const fn cnfptr(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0508usize) as _) } @@ -897,7 +897,7 @@ pub mod ccm { pub const fn scratchptr(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0514usize) as _) } } - #[doc = "Length of keystream generated when MODE.LENGTH = Extended."] + #[doc = "Length of keystream generated when MODE.LENGTH = Extended"] #[inline(always)] pub const fn maxpacketsize( self, @@ -911,6 +911,11 @@ pub mod ccm { ) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x051cusize) as _) } } + #[doc = "Header (S0) mask."] + #[inline(always)] + pub const fn headermask(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0520usize) as _) } + } } pub mod regs { #[doc = "Enable"] @@ -936,6 +941,29 @@ pub mod ccm { Enable(0) } } + #[doc = "Header (S0) mask."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Headermask(pub u32); + impl Headermask { + #[doc = "Header (S0) mask"] + #[inline(always)] + pub const fn headermask(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 + } + #[doc = "Header (S0) mask"] + #[inline(always)] + pub fn set_headermask(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); + } + } + impl Default for Headermask { + #[inline(always)] + fn default() -> Headermask { + Headermask(0) + } + } #[doc = "Disable interrupt"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -981,18 +1009,18 @@ pub mod ccm { Inten(0) } } - #[doc = "Length of keystream generated when MODE.LENGTH = Extended."] + #[doc = "Length of keystream generated when MODE.LENGTH = Extended"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Maxpacketsize(pub u32); impl Maxpacketsize { - #[doc = "Length of keystream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted."] + #[doc = "Length of keystream generated when MODE.LENGTH = Extended. This value must be greater than or equal to the subsequent packet payload to be encrypted/decrypted."] #[inline(always)] pub const fn maxpacketsize(&self) -> u8 { let val = (self.0 >> 0usize) & 0xff; val as u8 } - #[doc = "Length of keystream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted."] + #[doc = "Length of keystream generated when MODE.LENGTH = Extended. This value must be greater than or equal to the subsequent packet payload to be encrypted/decrypted."] #[inline(always)] pub fn set_maxpacketsize(&mut self, val: u8) { self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); @@ -1032,13 +1060,13 @@ pub mod ccm { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Mode(pub u32); impl Mode { - #[doc = "The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered."] + #[doc = "The mode of operation to be used. Settings in this register apply whenever either the KSGEN task or the CRYPT task is triggered."] #[inline(always)] pub const fn mode(&self) -> super::vals::Mode { let val = (self.0 >> 0usize) & 0x01; super::vals::Mode::from_bits(val as u8) } - #[doc = "The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered."] + #[doc = "The mode of operation to be used. Settings in this register apply whenever either the KSGEN task or the CRYPT task is triggered."] #[inline(always)] pub fn set_mode(&mut self, val: super::vals::Mode) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); @@ -1079,13 +1107,13 @@ pub mod ccm { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Rateoverride(pub u32); impl Rateoverride { - #[doc = "Data rate override setting."] + #[doc = "Data rate override setting"] #[inline(always)] pub const fn rateoverride(&self) -> super::vals::Rateoverride { let val = (self.0 >> 0usize) & 0x03; super::vals::Rateoverride::from_bits(val as u8) } - #[doc = "Data rate override setting."] + #[doc = "Data rate override setting"] #[inline(always)] pub fn set_rateoverride(&mut self, val: super::vals::Rateoverride) { self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); @@ -1129,9 +1157,9 @@ pub mod ccm { _1MBIT = 0x0, #[doc = "2 Mbps"] _2MBIT = 0x01, - #[doc = "125 Kbps"] + #[doc = "125 kbps"] _125KBPS = 0x02, - #[doc = "500 Kbps"] + #[doc = "500 kbps"] _500KBPS = 0x03, } impl Datarate { @@ -1285,9 +1313,9 @@ pub mod ccm { _1MBIT = 0x0, #[doc = "2 Mbps"] _2MBIT = 0x01, - #[doc = "125 Kbps"] + #[doc = "125 kbps"] _125KBPS = 0x02, - #[doc = "500 Kbps"] + #[doc = "500 kbps"] _500KBPS = 0x03, } impl Rateoverride { @@ -3694,15 +3722,15 @@ pub mod ficr { #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub struct Flash(pub u32); impl Flash { - #[doc = "128 kByte FLASH"] + #[doc = "128 kB FLASH"] pub const K128: Self = Self(0x80); - #[doc = "256 kByte FLASH"] + #[doc = "256 kB FLASH"] pub const K256: Self = Self(0x0100); - #[doc = "512 kByte FLASH"] + #[doc = "512 kB FLASH"] pub const K512: Self = Self(0x0200); - #[doc = "1 MByte FLASH"] + #[doc = "1 MB FLASH"] pub const K1024: Self = Self(0x0400); - #[doc = "2 MByte FLASH"] + #[doc = "2 MB FLASH"] pub const K2048: Self = Self(0x0800); #[doc = "Unspecified"] pub const UNSPECIFIED: Self = Self(0xffff_ffff); @@ -3822,15 +3850,15 @@ pub mod ficr { #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub struct Ram(pub u32); impl Ram { - #[doc = "16 kByte RAM"] + #[doc = "16 kB RAM"] pub const K16: Self = Self(0x10); - #[doc = "32 kByte RAM"] + #[doc = "32 kB RAM"] pub const K32: Self = Self(0x20); - #[doc = "64 kByte RAM"] + #[doc = "64 kB RAM"] pub const K64: Self = Self(0x40); - #[doc = "128 kByte RAM"] + #[doc = "128 kB RAM"] pub const K128: Self = Self(0x80); - #[doc = "256 kByte RAM"] + #[doc = "256 kB RAM"] pub const K256: Self = Self(0x0100); #[doc = "Unspecified"] pub const UNSPECIFIED: Self = Self(0xffff_ffff); @@ -3867,6 +3895,8 @@ pub mod ficr { pub const AAC0: Self = Self(0x4141_4330); #[doc = "AAC1"] pub const AAC1: Self = Self(0x4141_4331); + #[doc = "AAD0"] + pub const AAD0: Self = Self(0x4141_4430); #[doc = "Unspecified"] pub const UNSPECIFIED: Self = Self(0xffff_ffff); } @@ -7872,24 +7902,24 @@ pub mod radio { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Dfectrl2(pub u32); impl Dfectrl2 { - #[doc = "Signed value offset after the end of the CRC before starting switching in number of 16M cycles"] + #[doc = "Signed value offset after the end of the CRC before starting switching in number of 16 MHz clock cycles"] #[inline(always)] pub const fn tswitchoffset(&self) -> u16 { let val = (self.0 >> 0usize) & 0x1fff; val as u16 } - #[doc = "Signed value offset after the end of the CRC before starting switching in number of 16M cycles"] + #[doc = "Signed value offset after the end of the CRC before starting switching in number of 16 MHz clock cycles"] #[inline(always)] pub fn set_tswitchoffset(&mut self, val: u16) { self.0 = (self.0 & !(0x1fff << 0usize)) | (((val as u32) & 0x1fff) << 0usize); } - #[doc = "Signed value offset before starting sampling in number of 16M cycles relative to the beginning of the REFERENCE state - 12 us after switching start"] + #[doc = "Signed value offset in number of 16 MHz clock cycles for fine tuning of the sampling instant for all IQ samples. With TSAMPLEOFFSET=0 the first sample is taken immediately at the start of the reference period"] #[inline(always)] pub const fn tsampleoffset(&self) -> u16 { let val = (self.0 >> 16usize) & 0x0fff; val as u16 } - #[doc = "Signed value offset before starting sampling in number of 16M cycles relative to the beginning of the REFERENCE state - 12 us after switching start"] + #[doc = "Signed value offset in number of 16 MHz clock cycles for fine tuning of the sampling instant for all IQ samples. With TSAMPLEOFFSET=0 the first sample is taken immediately at the start of the reference period"] #[inline(always)] pub fn set_tsampleoffset(&mut self, val: u16) { self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize); @@ -8445,13 +8475,13 @@ pub mod radio { self.0 = (self.0 & !(0x01 << 20usize)) | (((val.to_bits() as u32) & 0x01) << 20usize); } - #[doc = "Length of code indicator - long range"] + #[doc = "Length of code indicator - Long Range"] #[inline(always)] pub const fn cilen(&self) -> u8 { let val = (self.0 >> 22usize) & 0x03; val as u8 } - #[doc = "Length of code indicator - long range"] + #[doc = "Length of code indicator - Long Range"] #[inline(always)] pub fn set_cilen(&mut self, val: u8) { self.0 = (self.0 & !(0x03 << 22usize)) | (((val as u32) & 0x03) << 22usize); @@ -9673,9 +9703,9 @@ pub mod radio { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Map { - #[doc = "Channel map between 2400 MHZ .. 2500 MHz"] + #[doc = "Channel map between 2400 MHz and 2500 MHz"] DEFAULT = 0x0, - #[doc = "Channel map between 2360 MHZ .. 2460 MHz"] + #[doc = "Channel map between 2360 MHz and 2460 MHz"] LOW = 0x01, } impl Map { @@ -9712,9 +9742,9 @@ pub mod radio { BLE_1MBIT = 0x03, #[doc = "2 Mbps BLE"] BLE_2MBIT = 0x04, - #[doc = "Long range 125 kbps TX, 125 kbps and 500 kbps RX"] + #[doc = "Long Range 125 kbps TX, 125 kbps and 500 kbps RX"] BLE_LR125KBIT = 0x05, - #[doc = "Long range 500 kbps TX, 125 kbps and 500 kbps RX"] + #[doc = "Long Range 500 kbps TX, 125 kbps and 500 kbps RX"] BLE_LR500KBIT = 0x06, _RESERVED_7 = 0x07, _RESERVED_8 = 0x08, @@ -9788,7 +9818,7 @@ pub mod radio { _16BIT = 0x01, #[doc = "32-bit zero preamble - used for IEEE 802.15.4"] _32BIT_ZERO = 0x02, - #[doc = "Preamble - used for BLE long range"] + #[doc = "Preamble - used for Bluetooth LE Long Range"] LONG_RANGE = 0x03, } impl Plen { diff --git a/src/chips/nrf52832/pac.rs b/src/chips/nrf52832/pac.rs index c128950..ece1813 100644 --- a/src/chips/nrf52832/pac.rs +++ b/src/chips/nrf52832/pac.rs @@ -1,4 +1,4 @@ -#![doc = "Peripheral access API (generated using chiptool v0.1.0 (218daa7 2024-01-15))"] +#![doc = "Peripheral access API (generated using chiptool v0.1.0 (4df74f6 2024-11-11))"] #[derive(Copy, Clone, Debug, PartialEq, Eq)] pub enum Interrupt { #[doc = "0 - POWER_CLOCK"] diff --git a/src/chips/nrf52833/pac.rs b/src/chips/nrf52833/pac.rs index bd4eaa7..3a32f86 100644 --- a/src/chips/nrf52833/pac.rs +++ b/src/chips/nrf52833/pac.rs @@ -1,4 +1,4 @@ -#![doc = "Peripheral access API (generated using chiptool v0.1.0 (218daa7 2024-01-15))"] +#![doc = "Peripheral access API (generated using chiptool v0.1.0 (4df74f6 2024-11-11))"] #[derive(Copy, Clone, Debug, PartialEq, Eq)] pub enum Interrupt { #[doc = "0 - POWER_CLOCK"] @@ -220,6 +220,9 @@ mod _vectors { pub const FICR: ficr::Ficr = unsafe { ficr::Ficr::from_ptr(0x1000_0000usize as _) }; #[doc = "User information configuration registers"] pub const UICR: uicr::Uicr = unsafe { uicr::Uicr::from_ptr(0x1000_1000usize as _) }; +#[doc = "Access Port Protection"] +pub const APPROTECT: approtect::Approtect = + unsafe { approtect::Approtect::from_ptr(0x4000_0000usize as _) }; #[doc = "Clock control"] pub const CLOCK: clock::Clock = unsafe { clock::Clock::from_ptr(0x4000_0000usize as _) }; #[doc = "Power control"] @@ -276,7 +279,7 @@ pub const RNG: rng::Rng = unsafe { rng::Rng::from_ptr(0x4000_d000usize as _) }; pub const ECB: ecb::Ecb = unsafe { ecb::Ecb::from_ptr(0x4000_e000usize as _) }; #[doc = "Accelerated Address Resolver"] pub const AAR: aar::Aar = unsafe { aar::Aar::from_ptr(0x4000_f000usize as _) }; -#[doc = "AES CCM Mode Encryption"] +#[doc = "AES CCM mode encryption"] pub const CCM: ccm::Ccm = unsafe { ccm::Ccm::from_ptr(0x4000_f000usize as _) }; #[doc = "Watchdog Timer"] pub const WDT: wdt::Wdt = unsafe { wdt::Wdt::from_ptr(0x4001_0000usize as _) }; @@ -520,13 +523,13 @@ pub mod aar { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Nirk(pub u32); impl Nirk { - #[doc = "Number of Identity root keys available in the IRK data structure"] + #[doc = "Number of Identity Root Keys available in the IRK data structure"] #[inline(always)] pub const fn nirk(&self) -> u8 { let val = (self.0 >> 0usize) & 0x1f; val as u8 } - #[doc = "Number of Identity root keys available in the IRK data structure"] + #[doc = "Number of Identity Root Keys available in the IRK data structure"] #[inline(always)] pub fn set_nirk(&mut self, val: u8) { self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize); @@ -637,12 +640,12 @@ pub mod acl { pub const fn as_ptr(&self) -> *mut () { self.ptr as _ } - #[doc = "Description cluster: Configure the word-aligned start address of region n to protect"] + #[doc = "Description cluster: Start address of region to protect. The start address must be word-aligned."] #[inline(always)] pub const fn addr(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } - #[doc = "Description cluster: Size of region to protect counting from address ACL\\[n\\].ADDR. Write '0' as no effect."] + #[doc = "Description cluster: Size of region to protect counting from address ACL\\[n\\].ADDR. Writing a '0' has no effect."] #[inline(always)] pub const fn size(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } @@ -659,24 +662,24 @@ pub mod acl { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Perm(pub u32); impl Perm { - #[doc = "Configure write and erase permissions for region n. Write '0' has no effect."] + #[doc = "Configure write and erase permissions for region n. Writing a '0' has no effect."] #[inline(always)] pub const fn write(&self) -> super::vals::Write { let val = (self.0 >> 1usize) & 0x01; super::vals::Write::from_bits(val as u8) } - #[doc = "Configure write and erase permissions for region n. Write '0' has no effect."] + #[doc = "Configure write and erase permissions for region n. Writing a '0' has no effect."] #[inline(always)] pub fn set_write(&mut self, val: super::vals::Write) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val.to_bits() as u32) & 0x01) << 1usize); } - #[doc = "Configure read permissions for region n. Write '0' has no effect."] + #[doc = "Configure read permissions for region n. Writing a '0' has no effect."] #[inline(always)] pub const fn read(&self) -> super::vals::Read { let val = (self.0 >> 2usize) & 0x01; super::vals::Read::from_bits(val as u8) } - #[doc = "Configure read permissions for region n. Write '0' has no effect."] + #[doc = "Configure read permissions for region n. Writing a '0' has no effect."] #[inline(always)] pub fn set_read(&mut self, val: super::vals::Read) { self.0 = (self.0 & !(0x01 << 2usize)) | (((val.to_bits() as u32) & 0x01) << 2usize); @@ -693,9 +696,9 @@ pub mod acl { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Read { - #[doc = "Allow read instructions to region n"] + #[doc = "Allow read instructions to region n."] ENABLE = 0x0, - #[doc = "Block read instructions to region n"] + #[doc = "Block read instructions to region n."] DISABLE = 0x01, } impl Read { @@ -723,9 +726,9 @@ pub mod acl { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Write { - #[doc = "Allow write and erase instructions to region n"] + #[doc = "Allow write and erase instructions to region n."] ENABLE = 0x0, - #[doc = "Block write and erase instructions to region n"] + #[doc = "Block write and erase instructions to region n."] DISABLE = 0x01, } impl Write { @@ -752,8 +755,143 @@ pub mod acl { } } } +pub mod approtect { + #[doc = "Access Port Protection"] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Approtect { + ptr: *mut u8, + } + unsafe impl Send for Approtect {} + unsafe impl Sync for Approtect {} + impl Approtect { + #[inline(always)] + pub const unsafe fn from_ptr(ptr: *mut ()) -> Self { + Self { ptr: ptr as _ } + } + #[inline(always)] + pub const fn as_ptr(&self) -> *mut () { + self.ptr as _ + } + #[doc = "Software force enable APPROTECT mechanism until next reset."] + #[inline(always)] + pub const fn forceprotect( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0550usize) as _) } + } + #[doc = "Software disable APPROTECT mechanism"] + #[inline(always)] + pub const fn disable(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0558usize) as _) } + } + } + pub mod regs { + #[doc = "Software disable APPROTECT mechanism"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Disable(pub u32); + impl Disable { + #[doc = "Software disable APPROTECT mechanism"] + #[inline(always)] + pub const fn disable(&self) -> super::vals::Disable { + let val = (self.0 >> 0usize) & 0xff; + super::vals::Disable::from_bits(val as u8) + } + #[doc = "Software disable APPROTECT mechanism"] + #[inline(always)] + pub fn set_disable(&mut self, val: super::vals::Disable) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val.to_bits() as u32) & 0xff) << 0usize); + } + } + impl Default for Disable { + #[inline(always)] + fn default() -> Disable { + Disable(0) + } + } + #[doc = "Software force enable APPROTECT mechanism until next reset."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Forceprotect(pub u32); + impl Forceprotect { + #[doc = "Write 0x0 to force enable APPROTECT mechanism"] + #[inline(always)] + pub const fn forceprotect(&self) -> super::vals::Forceprotect { + let val = (self.0 >> 0usize) & 0xff; + super::vals::Forceprotect::from_bits(val as u8) + } + #[doc = "Write 0x0 to force enable APPROTECT mechanism"] + #[inline(always)] + pub fn set_forceprotect(&mut self, val: super::vals::Forceprotect) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val.to_bits() as u32) & 0xff) << 0usize); + } + } + impl Default for Forceprotect { + #[inline(always)] + fn default() -> Forceprotect { + Forceprotect(0) + } + } + } + pub mod vals { + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Disable(pub u8); + impl Disable { + #[doc = "Software disable APPROTECT mechanism"] + pub const SW_DISABLE: Self = Self(0x5a); + } + impl Disable { + pub const fn from_bits(val: u8) -> Disable { + Self(val & 0xff) + } + pub const fn to_bits(self) -> u8 { + self.0 + } + } + impl From for Disable { + #[inline(always)] + fn from(val: u8) -> Disable { + Disable::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: Disable) -> u8 { + Disable::to_bits(val) + } + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Forceprotect(pub u8); + impl Forceprotect { + #[doc = "Software force enable APPROTECT mechanism"] + pub const FORCE: Self = Self(0x0); + } + impl Forceprotect { + pub const fn from_bits(val: u8) -> Forceprotect { + Self(val & 0xff) + } + pub const fn to_bits(self) -> u8 { + self.0 + } + } + impl From for Forceprotect { + #[inline(always)] + fn from(val: u8) -> Forceprotect { + Forceprotect::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: Forceprotect) -> u8 { + Forceprotect::to_bits(val) + } + } + } +} pub mod ccm { - #[doc = "AES CCM Mode Encryption"] + #[doc = "AES CCM mode encryption"] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Ccm { ptr: *mut u8, @@ -769,7 +907,7 @@ pub mod ccm { pub const fn as_ptr(&self) -> *mut () { self.ptr as _ } - #[doc = "Start generation of key-stream. This operation will stop by itself when completed."] + #[doc = "Start generation of keystream. This operation will stop by itself when completed."] #[inline(always)] pub const fn tasks_ksgen(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } @@ -789,7 +927,7 @@ pub mod ccm { pub const fn tasks_rateoverride(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } } - #[doc = "Key-stream generation complete"] + #[doc = "Keystream generation complete"] #[inline(always)] pub const fn events_endksgen(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0100usize) as _) } @@ -834,7 +972,7 @@ pub mod ccm { pub const fn mode(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0504usize) as _) } } - #[doc = "Pointer to data structure holding AES key and NONCE vector"] + #[doc = "Pointer to data structure holding the AES key and the NONCE vector"] #[inline(always)] pub const fn cnfptr(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0508usize) as _) } @@ -854,7 +992,7 @@ pub mod ccm { pub const fn scratchptr(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0514usize) as _) } } - #[doc = "Length of key-stream generated when MODE.LENGTH = Extended."] + #[doc = "Length of keystream generated when MODE.LENGTH = Extended"] #[inline(always)] pub const fn maxpacketsize( self, @@ -868,6 +1006,11 @@ pub mod ccm { ) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x051cusize) as _) } } + #[doc = "Header (S0) mask."] + #[inline(always)] + pub const fn headermask(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0520usize) as _) } + } } pub mod regs { #[doc = "Enable"] @@ -893,6 +1036,29 @@ pub mod ccm { Enable(0) } } + #[doc = "Header (S0) mask."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Headermask(pub u32); + impl Headermask { + #[doc = "Header (S0) mask"] + #[inline(always)] + pub const fn headermask(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 + } + #[doc = "Header (S0) mask"] + #[inline(always)] + pub fn set_headermask(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); + } + } + impl Default for Headermask { + #[inline(always)] + fn default() -> Headermask { + Headermask(0) + } + } #[doc = "Disable interrupt"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -938,18 +1104,18 @@ pub mod ccm { Inten(0) } } - #[doc = "Length of key-stream generated when MODE.LENGTH = Extended."] + #[doc = "Length of keystream generated when MODE.LENGTH = Extended"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Maxpacketsize(pub u32); impl Maxpacketsize { - #[doc = "Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted."] + #[doc = "Length of keystream generated when MODE.LENGTH = Extended. This value must be greater than or equal to the subsequent packet payload to be encrypted/decrypted."] #[inline(always)] pub const fn maxpacketsize(&self) -> u8 { let val = (self.0 >> 0usize) & 0xff; val as u8 } - #[doc = "Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted."] + #[doc = "Length of keystream generated when MODE.LENGTH = Extended. This value must be greater than or equal to the subsequent packet payload to be encrypted/decrypted."] #[inline(always)] pub fn set_maxpacketsize(&mut self, val: u8) { self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); @@ -989,13 +1155,13 @@ pub mod ccm { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Mode(pub u32); impl Mode { - #[doc = "The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered."] + #[doc = "The mode of operation to be used. Settings in this register apply whenever either the KSGEN task or the CRYPT task is triggered."] #[inline(always)] pub const fn mode(&self) -> super::vals::Mode { let val = (self.0 >> 0usize) & 0x01; super::vals::Mode::from_bits(val as u8) } - #[doc = "The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered."] + #[doc = "The mode of operation to be used. Settings in this register apply whenever either the KSGEN task or the CRYPT task is triggered."] #[inline(always)] pub fn set_mode(&mut self, val: super::vals::Mode) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); @@ -1036,13 +1202,13 @@ pub mod ccm { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Rateoverride(pub u32); impl Rateoverride { - #[doc = "Data rate override setting."] + #[doc = "Data rate override setting"] #[inline(always)] pub const fn rateoverride(&self) -> super::vals::Rateoverride { let val = (self.0 >> 0usize) & 0x03; super::vals::Rateoverride::from_bits(val as u8) } - #[doc = "Data rate override setting."] + #[doc = "Data rate override setting"] #[inline(always)] pub fn set_rateoverride(&mut self, val: super::vals::Rateoverride) { self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); @@ -1086,9 +1252,9 @@ pub mod ccm { _1MBIT = 0x0, #[doc = "2 Mbps"] _2MBIT = 0x01, - #[doc = "125 Kbps"] + #[doc = "125 kbps"] _125KBPS = 0x02, - #[doc = "500 Kbps"] + #[doc = "500 kbps"] _500KBPS = 0x03, } impl Datarate { @@ -1148,9 +1314,9 @@ pub mod ccm { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Length { - #[doc = "Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packet payloads up to 27 bytes will be generated."] + #[doc = "Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A keystream for packet payloads up to 27 bytes will be generated."] DEFAULT = 0x0, - #[doc = "Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packet payloads up to MAXPACKETSIZE bytes will be generated."] + #[doc = "Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A keystream for packet payloads up to MAXPACKETSIZE bytes will be generated."] EXTENDED = 0x01, } impl Length { @@ -1242,9 +1408,9 @@ pub mod ccm { _1MBIT = 0x0, #[doc = "2 Mbps"] _2MBIT = 0x01, - #[doc = "125 Kbps"] + #[doc = "125 kbps"] _125KBPS = 0x02, - #[doc = "500 Kbps"] + #[doc = "500 kbps"] _500KBPS = 0x03, } impl Rateoverride { @@ -4068,11 +4234,11 @@ pub mod ficr { #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub struct Package(pub u32); impl Package { - #[doc = "QIxx - 73-pin aQFN"] + #[doc = "QIxx - 7x7 73-pin aQFN"] pub const QI: Self = Self(0x2004); - #[doc = "QDxx - 40-pin QFN"] + #[doc = "QDxx - 5x5 40-pin QFN"] pub const QD: Self = Self(0x2007); - #[doc = "CJxx - WLCSP"] + #[doc = "CJxx - 3.175 x 3.175 WLCSP"] pub const CJ: Self = Self(0x2008); #[doc = "Unspecified"] pub const UNSPECIFIED: Self = Self(0xffff_ffff); @@ -4101,6 +4267,8 @@ pub mod ficr { #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub struct Part(pub u32); impl Part { + #[doc = "nRF52820"] + pub const N52820: Self = Self(0x0005_2820); #[doc = "nRF52833"] pub const N52833: Self = Self(0x0005_2833); #[doc = "nRF52840"] @@ -4198,10 +4366,16 @@ pub mod ficr { #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub struct Variant(pub u32); impl Variant { + #[doc = "AAA0"] + pub const AAA0: Self = Self(0x4141_4130); + #[doc = "AAA1"] + pub const AAA1: Self = Self(0x4141_4131); #[doc = "AAAA"] pub const AAAA: Self = Self(0x4141_4141); #[doc = "AAAB"] pub const AAAB: Self = Self(0x4141_4142); + #[doc = "AAB0"] + pub const AAB0: Self = Self(0x4141_4230); #[doc = "Unspecified"] pub const UNSPECIFIED: Self = Self(0xffff_ffff); } @@ -4308,7 +4482,7 @@ pub mod gpio { pub const fn latch(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0520usize) as _) } } - #[doc = "Select between default DETECT signal behaviour and LDETECT mode"] + #[doc = "Select between default DETECT signal behavior and LDETECT mode"] #[inline(always)] pub const fn detectmode(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0524usize) as _) } @@ -4324,18 +4498,18 @@ pub mod gpio { } } pub mod regs { - #[doc = "Select between default DETECT signal behaviour and LDETECT mode"] + #[doc = "Select between default DETECT signal behavior and LDETECT mode"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Detectmode(pub u32); impl Detectmode { - #[doc = "Select between default DETECT signal behaviour and LDETECT mode"] + #[doc = "Select between default DETECT signal behavior and LDETECT mode"] #[inline(always)] pub const fn detectmode(&self) -> super::vals::Detectmode { let val = (self.0 >> 0usize) & 0x01; super::vals::Detectmode::from_bits(val as u8) } - #[doc = "Select between default DETECT signal behaviour and LDETECT mode"] + #[doc = "Select between default DETECT signal behavior and LDETECT mode"] #[inline(always)] pub fn set_detectmode(&mut self, val: super::vals::Detectmode) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); @@ -4638,7 +4812,7 @@ pub mod gpio { pub enum Detectmode { #[doc = "DETECT directly connected to PIN DETECT signals"] DEFAULT = 0x0, - #[doc = "Use the latched LDETECT behaviour"] + #[doc = "Use the latched LDETECT behavior"] LDETECT = 0x01, } impl Detectmode { @@ -10604,12 +10778,12 @@ pub mod ppi { pub const fn as_ptr(&self) -> *mut () { self.ptr as _ } - #[doc = "Description cluster: Channel n event end-point"] + #[doc = "Description cluster: Channel n event endpoint"] #[inline(always)] pub const fn eep(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } - #[doc = "Description cluster: Channel n task end-point"] + #[doc = "Description cluster: Channel n task endpoint"] #[inline(always)] pub const fn tep(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } @@ -10631,7 +10805,7 @@ pub mod ppi { pub const fn as_ptr(&self) -> *mut () { self.ptr as _ } - #[doc = "Description cluster: Channel n task end-point"] + #[doc = "Description cluster: Channel n task endpoint"] #[inline(always)] pub const fn tep(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } @@ -11951,13 +12125,13 @@ pub mod qdec { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Reportper(pub u32); impl Reportper { - #[doc = "Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated"] + #[doc = "Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated."] #[inline(always)] pub const fn reportper(&self) -> super::vals::Reportper { let val = (self.0 >> 0usize) & 0x0f; super::vals::Reportper::from_bits(val as u8) } - #[doc = "Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated"] + #[doc = "Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated."] #[inline(always)] pub fn set_reportper(&mut self, val: super::vals::Reportper) { self.0 = (self.0 & !(0x0f << 0usize)) | (((val.to_bits() as u32) & 0x0f) << 0usize); @@ -12116,23 +12290,23 @@ pub mod qdec { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Reportper { - #[doc = "10 samples / report"] + #[doc = "10 samples/report"] _10SMPL = 0x0, - #[doc = "40 samples / report"] + #[doc = "40 samples/report"] _40SMPL = 0x01, - #[doc = "80 samples / report"] + #[doc = "80 samples/report"] _80SMPL = 0x02, - #[doc = "120 samples / report"] + #[doc = "120 samples/report"] _120SMPL = 0x03, - #[doc = "160 samples / report"] + #[doc = "160 samples/report"] _160SMPL = 0x04, - #[doc = "200 samples / report"] + #[doc = "200 samples/report"] _200SMPL = 0x05, - #[doc = "240 samples / report"] + #[doc = "240 samples/report"] _240SMPL = 0x06, - #[doc = "280 samples / report"] + #[doc = "280 samples/report"] _280SMPL = 0x07, - #[doc = "1 sample / report"] + #[doc = "1 sample/report"] _1SMPL = 0x08, _RESERVED_9 = 0x09, _RESERVED_a = 0x0a, @@ -12419,7 +12593,7 @@ pub mod radio { pub const fn events_framestart(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0138usize) as _) } } - #[doc = "Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register"] + #[doc = "Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register."] #[inline(always)] pub const fn events_edend(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x013cusize) as _) } @@ -12841,13 +13015,13 @@ pub mod radio { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Crccnf(pub u32); impl Crccnf { - #[doc = "CRC length in number of bytes."] + #[doc = "CRC length in number of bytes For MODE Ble_LR125Kbit and Ble_LR500Kbit, only LEN set to 3 is supported"] #[inline(always)] pub const fn len(&self) -> super::vals::Len { let val = (self.0 >> 0usize) & 0x03; super::vals::Len::from_bits(val as u8) } - #[doc = "CRC length in number of bytes."] + #[doc = "CRC length in number of bytes For MODE Ble_LR125Kbit and Ble_LR500Kbit, only LEN set to 3 is supported"] #[inline(always)] pub fn set_len(&mut self, val: super::vals::Len) { self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); @@ -12990,25 +13164,25 @@ pub mod radio { pub fn set_ctetimevalidrange(&mut self, val: super::vals::Ctetimevalidrange) { self.0 = (self.0 & !(0x03 << 6usize)) | (((val.to_bits() as u32) & 0x03) << 6usize); } - #[doc = "Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set"] + #[doc = "Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set."] #[inline(always)] pub const fn cteinlinerxmode1us(&self) -> super::vals::Cteinlinerxmode1us { let val = (self.0 >> 10usize) & 0x07; super::vals::Cteinlinerxmode1us::from_bits(val as u8) } - #[doc = "Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set"] + #[doc = "Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set."] #[inline(always)] pub fn set_cteinlinerxmode1us(&mut self, val: super::vals::Cteinlinerxmode1us) { self.0 = (self.0 & !(0x07 << 10usize)) | (((val.to_bits() as u32) & 0x07) << 10usize); } - #[doc = "Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set"] + #[doc = "Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set."] #[inline(always)] pub const fn cteinlinerxmode2us(&self) -> super::vals::Cteinlinerxmode2us { let val = (self.0 >> 13usize) & 0x07; super::vals::Cteinlinerxmode2us::from_bits(val as u8) } - #[doc = "Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set"] + #[doc = "Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set."] #[inline(always)] pub fn set_cteinlinerxmode2us(&mut self, val: super::vals::Cteinlinerxmode2us) { self.0 = @@ -13603,13 +13777,13 @@ pub mod radio { pub fn set_frequency(&mut self, val: u8) { self.0 = (self.0 & !(0x7f << 0usize)) | (((val as u32) & 0x7f) << 0usize); } - #[doc = "Channel map selection."] + #[doc = "Channel map selection"] #[inline(always)] pub const fn map(&self) -> super::vals::Map { let val = (self.0 >> 8usize) & 0x01; super::vals::Map::from_bits(val as u8) } - #[doc = "Channel map selection."] + #[doc = "Channel map selection"] #[inline(always)] pub fn set_map(&mut self, val: super::vals::Map) { self.0 = (self.0 & !(0x01 << 8usize)) | (((val.to_bits() as u32) & 0x01) << 8usize); @@ -13982,35 +14156,35 @@ pub mod radio { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Pcnf0(pub u32); impl Pcnf0 { - #[doc = "Length on air of LENGTH field in number of bits."] + #[doc = "Length on air of LENGTH field in number of bits"] #[inline(always)] pub const fn lflen(&self) -> u8 { let val = (self.0 >> 0usize) & 0x0f; val as u8 } - #[doc = "Length on air of LENGTH field in number of bits."] + #[doc = "Length on air of LENGTH field in number of bits"] #[inline(always)] pub fn set_lflen(&mut self, val: u8) { self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); } - #[doc = "Length on air of S0 field in number of bytes."] + #[doc = "Length on air of S0 field in number of bytes"] #[inline(always)] pub const fn s0len(&self) -> bool { let val = (self.0 >> 8usize) & 0x01; val != 0 } - #[doc = "Length on air of S0 field in number of bytes."] + #[doc = "Length on air of S0 field in number of bytes"] #[inline(always)] pub fn set_s0len(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); } - #[doc = "Length on air of S1 field in number of bits."] + #[doc = "Length on air of S1 field in number of bits"] #[inline(always)] pub const fn s1len(&self) -> u8 { let val = (self.0 >> 16usize) & 0x0f; val as u8 } - #[doc = "Length on air of S1 field in number of bits."] + #[doc = "Length on air of S1 field in number of bits"] #[inline(always)] pub fn set_s1len(&mut self, val: u8) { self.0 = (self.0 & !(0x0f << 16usize)) | (((val as u32) & 0x0f) << 16usize); @@ -14322,13 +14496,13 @@ pub mod radio { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Rssisample(pub u32); impl Rssisample { - #[doc = "RSSI sample"] + #[doc = "RSSI sample."] #[inline(always)] pub const fn rssisample(&self) -> u8 { let val = (self.0 >> 0usize) & 0x7f; val as u8 } - #[doc = "RSSI sample"] + #[doc = "RSSI sample."] #[inline(always)] pub fn set_rssisample(&mut self, val: u8) { self.0 = (self.0 & !(0x7f << 0usize)) | (((val as u32) & 0x7f) << 0usize); @@ -14759,13 +14933,13 @@ pub mod radio { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Switchpattern(pub u32); impl Switchpattern { - #[doc = "Fill array of GPIO patterns for antenna control"] + #[doc = "Fill array of GPIO patterns for antenna control."] #[inline(always)] pub const fn switchpattern(&self) -> u8 { let val = (self.0 >> 0usize) & 0xff; val as u8 } - #[doc = "Fill array of GPIO patterns for antenna control"] + #[doc = "Fill array of GPIO patterns for antenna control."] #[inline(always)] pub fn set_switchpattern(&mut self, val: u8) { self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); @@ -14782,13 +14956,13 @@ pub mod radio { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Tifs(pub u32); impl Tifs { - #[doc = "Interframe spacing in us"] + #[doc = "Interframe spacing in us."] #[inline(always)] pub const fn tifs(&self) -> u16 { let val = (self.0 >> 0usize) & 0x03ff; val as u16 } - #[doc = "Interframe spacing in us"] + #[doc = "Interframe spacing in us."] #[inline(always)] pub fn set_tifs(&mut self, val: u16) { self.0 = (self.0 & !(0x03ff << 0usize)) | (((val as u32) & 0x03ff) << 0usize); @@ -14983,17 +15157,17 @@ pub mod radio { #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Cteinlinerxmode1us { _RESERVED_0 = 0x0, - #[doc = "4us"] + #[doc = "4 us"] _4US = 0x01, - #[doc = "2us"] + #[doc = "2 us"] _2US = 0x02, - #[doc = "1us"] + #[doc = "1 us"] _1US = 0x03, - #[doc = "0.5us"] + #[doc = "0.5 us"] _500NS = 0x04, - #[doc = "0.25us"] + #[doc = "0.25 us"] _250NS = 0x05, - #[doc = "0.125us"] + #[doc = "0.125 us"] _125NS = 0x06, _RESERVED_7 = 0x07, } @@ -15023,17 +15197,17 @@ pub mod radio { #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Cteinlinerxmode2us { _RESERVED_0 = 0x0, - #[doc = "4us"] + #[doc = "4 us"] _4US = 0x01, - #[doc = "2us"] + #[doc = "2 us"] _2US = 0x02, - #[doc = "1us"] + #[doc = "1 us"] _1US = 0x03, - #[doc = "0.5us"] + #[doc = "0.5 us"] _500NS = 0x04, - #[doc = "0.25us"] + #[doc = "0.25 us"] _250NS = 0x05, - #[doc = "0.125us"] + #[doc = "0.125 us"] _125NS = 0x06, _RESERVED_7 = 0x07, } @@ -15062,11 +15236,11 @@ pub mod radio { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Ctetimevalidrange { - #[doc = "20 in 8us unit (default) Set to 20 if parsed CTETime is larger han 20"] + #[doc = "20 in 8 us unit (default) Set to 20 if parsed CTETime is larger than 20"] _20 = 0x0, - #[doc = "31 in 8us unit"] + #[doc = "31 in 8 us unit"] _31 = 0x01, - #[doc = "63 in 8us unit"] + #[doc = "63 in 8 us unit"] _63 = 0x02, _RESERVED_3 = 0x03, } @@ -15443,7 +15617,7 @@ pub mod radio { pub enum Ru { #[doc = "Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51"] DEFAULT = 0x0, - #[doc = "Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specification for more information"] + #[doc = "Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specifications for more information"] FAST = 0x01, } impl Ru { @@ -15686,17 +15860,17 @@ pub mod radio { #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Tsamplespacing { _RESERVED_0 = 0x0, - #[doc = "4us"] + #[doc = "4 us"] _4US = 0x01, - #[doc = "2us"] + #[doc = "2 us"] _2US = 0x02, - #[doc = "1us"] + #[doc = "1 us"] _1US = 0x03, - #[doc = "0.5us"] + #[doc = "0.5 us"] _500NS = 0x04, - #[doc = "0.25us"] + #[doc = "0.25 us"] _250NS = 0x05, - #[doc = "0.125us"] + #[doc = "0.125 us"] _125NS = 0x06, _RESERVED_7 = 0x07, } @@ -15726,17 +15900,17 @@ pub mod radio { #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Tsamplespacingref { _RESERVED_0 = 0x0, - #[doc = "4us"] + #[doc = "4 us"] _4US = 0x01, - #[doc = "2us"] + #[doc = "2 us"] _2US = 0x02, - #[doc = "1us"] + #[doc = "1 us"] _1US = 0x03, - #[doc = "0.5us"] + #[doc = "0.5 us"] _500NS = 0x04, - #[doc = "0.25us"] + #[doc = "0.25 us"] _250NS = 0x05, - #[doc = "0.125us"] + #[doc = "0.125 us"] _125NS = 0x06, _RESERVED_7 = 0x07, } @@ -15766,11 +15940,11 @@ pub mod radio { #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Tswitchspacing { _RESERVED_0 = 0x0, - #[doc = "4us"] + #[doc = "4 us"] _4US = 0x01, - #[doc = "2us"] + #[doc = "2 us"] _2US = 0x02, - #[doc = "1us"] + #[doc = "1 us"] _1US = 0x03, _RESERVED_4 = 0x04, _RESERVED_5 = 0x05, @@ -16334,7 +16508,7 @@ pub mod rtc { pub const fn counter(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0504usize) as _) } } - #[doc = "12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped"] + #[doc = "12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is stopped."] #[inline(always)] pub const fn prescaler(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0508usize) as _) } @@ -16707,7 +16881,7 @@ pub mod rtc { Inten(0) } } - #[doc = "12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped"] + #[doc = "12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is stopped."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Prescaler(pub u32); @@ -18356,13 +18530,13 @@ pub mod spi { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Txd(pub u32); impl Txd { - #[doc = "TX data to send. Double buffered"] + #[doc = "TX data to send. Double buffered."] #[inline(always)] pub const fn txd(&self) -> u8 { let val = (self.0 >> 0usize) & 0xff; val as u8 } - #[doc = "TX data to send. Double buffered"] + #[doc = "TX data to send. Double buffered."] #[inline(always)] pub fn set_txd(&mut self, val: u8) { self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); @@ -18733,7 +18907,7 @@ pub mod spim { pub const fn intenclr(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0308usize) as _) } } - #[doc = "Stall status for EasyDMA RAM accesses. The fields in this register is set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU."] + #[doc = "Stall status for EasyDMA RAM accesses. The fields in this register are set to STALL by hardware whenever a stall occurs and can be cleared (set to NOSTALL) by the CPU."] #[inline(always)] pub const fn stallstat(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0400usize) as _) } @@ -19200,7 +19374,7 @@ pub mod spim { Shorts(0) } } - #[doc = "Stall status for EasyDMA RAM accesses. The fields in this register is set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU."] + #[doc = "Stall status for EasyDMA RAM accesses. The fields in this register are set to STALL by hardware whenever a stall occurs and can be cleared (set to NOSTALL) by the CPU."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Stallstat(pub u32); @@ -20481,105 +20655,105 @@ pub mod temp { pub const fn temp(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0508usize) as _) } } - #[doc = "Slope of 1st piece wise linear function"] + #[doc = "Slope of first piecewise linear function"] #[inline(always)] pub const fn a0(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0520usize) as _) } } - #[doc = "Slope of 2nd piece wise linear function"] + #[doc = "Slope of second piecewise linear function"] #[inline(always)] pub const fn a1(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0524usize) as _) } } - #[doc = "Slope of 3rd piece wise linear function"] + #[doc = "Slope of third piecewise linear function"] #[inline(always)] pub const fn a2(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0528usize) as _) } } - #[doc = "Slope of 4th piece wise linear function"] + #[doc = "Slope of fourth piecewise linear function"] #[inline(always)] pub const fn a3(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x052cusize) as _) } } - #[doc = "Slope of 5th piece wise linear function"] + #[doc = "Slope of fifth piecewise linear function"] #[inline(always)] pub const fn a4(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0530usize) as _) } } - #[doc = "Slope of 6th piece wise linear function"] + #[doc = "Slope of sixth piecewise linear function"] #[inline(always)] pub const fn a5(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0534usize) as _) } } - #[doc = "y-intercept of 1st piece wise linear function"] + #[doc = "y-intercept of first piecewise linear function"] #[inline(always)] pub const fn b0(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0540usize) as _) } } - #[doc = "y-intercept of 2nd piece wise linear function"] + #[doc = "y-intercept of second piecewise linear function"] #[inline(always)] pub const fn b1(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0544usize) as _) } } - #[doc = "y-intercept of 3rd piece wise linear function"] + #[doc = "y-intercept of third piecewise linear function"] #[inline(always)] pub const fn b2(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0548usize) as _) } } - #[doc = "y-intercept of 4th piece wise linear function"] + #[doc = "y-intercept of fourth piecewise linear function"] #[inline(always)] pub const fn b3(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x054cusize) as _) } } - #[doc = "y-intercept of 5th piece wise linear function"] + #[doc = "y-intercept of fifth piecewise linear function"] #[inline(always)] pub const fn b4(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0550usize) as _) } } - #[doc = "y-intercept of 6th piece wise linear function"] + #[doc = "y-intercept of sixth piecewise linear function"] #[inline(always)] pub const fn b5(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0554usize) as _) } } - #[doc = "End point of 1st piece wise linear function"] + #[doc = "End point of first piecewise linear function"] #[inline(always)] pub const fn t0(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0560usize) as _) } } - #[doc = "End point of 2nd piece wise linear function"] + #[doc = "End point of second piecewise linear function"] #[inline(always)] pub const fn t1(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0564usize) as _) } } - #[doc = "End point of 3rd piece wise linear function"] + #[doc = "End point of third piecewise linear function"] #[inline(always)] pub const fn t2(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0568usize) as _) } } - #[doc = "End point of 4th piece wise linear function"] + #[doc = "End point of fourth piecewise linear function"] #[inline(always)] pub const fn t3(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x056cusize) as _) } } - #[doc = "End point of 5th piece wise linear function"] + #[doc = "End point of fifth piecewise linear function"] #[inline(always)] pub const fn t4(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0570usize) as _) } } } pub mod regs { - #[doc = "Slope of 1st piece wise linear function"] + #[doc = "Slope of first piecewise linear function"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct A0(pub u32); impl A0 { - #[doc = "Slope of 1st piece wise linear function"] + #[doc = "Slope of first piecewise linear function"] #[inline(always)] pub const fn a0(&self) -> u16 { let val = (self.0 >> 0usize) & 0x0fff; val as u16 } - #[doc = "Slope of 1st piece wise linear function"] + #[doc = "Slope of first piecewise linear function"] #[inline(always)] pub fn set_a0(&mut self, val: u16) { self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); @@ -20591,18 +20765,18 @@ pub mod temp { A0(0) } } - #[doc = "Slope of 2nd piece wise linear function"] + #[doc = "Slope of second piecewise linear function"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct A1(pub u32); impl A1 { - #[doc = "Slope of 2nd piece wise linear function"] + #[doc = "Slope of second piecewise linear function"] #[inline(always)] pub const fn a1(&self) -> u16 { let val = (self.0 >> 0usize) & 0x0fff; val as u16 } - #[doc = "Slope of 2nd piece wise linear function"] + #[doc = "Slope of second piecewise linear function"] #[inline(always)] pub fn set_a1(&mut self, val: u16) { self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); @@ -20614,18 +20788,18 @@ pub mod temp { A1(0) } } - #[doc = "Slope of 3rd piece wise linear function"] + #[doc = "Slope of third piecewise linear function"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct A2(pub u32); impl A2 { - #[doc = "Slope of 3rd piece wise linear function"] + #[doc = "Slope of third piecewise linear function"] #[inline(always)] pub const fn a2(&self) -> u16 { let val = (self.0 >> 0usize) & 0x0fff; val as u16 } - #[doc = "Slope of 3rd piece wise linear function"] + #[doc = "Slope of third piecewise linear function"] #[inline(always)] pub fn set_a2(&mut self, val: u16) { self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); @@ -20637,18 +20811,18 @@ pub mod temp { A2(0) } } - #[doc = "Slope of 4th piece wise linear function"] + #[doc = "Slope of fourth piecewise linear function"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct A3(pub u32); impl A3 { - #[doc = "Slope of 4th piece wise linear function"] + #[doc = "Slope of fourth piecewise linear function"] #[inline(always)] pub const fn a3(&self) -> u16 { let val = (self.0 >> 0usize) & 0x0fff; val as u16 } - #[doc = "Slope of 4th piece wise linear function"] + #[doc = "Slope of fourth piecewise linear function"] #[inline(always)] pub fn set_a3(&mut self, val: u16) { self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); @@ -20660,18 +20834,18 @@ pub mod temp { A3(0) } } - #[doc = "Slope of 5th piece wise linear function"] + #[doc = "Slope of fifth piecewise linear function"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct A4(pub u32); impl A4 { - #[doc = "Slope of 5th piece wise linear function"] + #[doc = "Slope of fifth piecewise linear function"] #[inline(always)] pub const fn a4(&self) -> u16 { let val = (self.0 >> 0usize) & 0x0fff; val as u16 } - #[doc = "Slope of 5th piece wise linear function"] + #[doc = "Slope of fifth piecewise linear function"] #[inline(always)] pub fn set_a4(&mut self, val: u16) { self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); @@ -20683,18 +20857,18 @@ pub mod temp { A4(0) } } - #[doc = "Slope of 6th piece wise linear function"] + #[doc = "Slope of sixth piecewise linear function"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct A5(pub u32); impl A5 { - #[doc = "Slope of 6th piece wise linear function"] + #[doc = "Slope of sixth piecewise linear function"] #[inline(always)] pub const fn a5(&self) -> u16 { let val = (self.0 >> 0usize) & 0x0fff; val as u16 } - #[doc = "Slope of 6th piece wise linear function"] + #[doc = "Slope of sixth piecewise linear function"] #[inline(always)] pub fn set_a5(&mut self, val: u16) { self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); @@ -20706,18 +20880,18 @@ pub mod temp { A5(0) } } - #[doc = "y-intercept of 1st piece wise linear function"] + #[doc = "y-intercept of first piecewise linear function"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct B0(pub u32); impl B0 { - #[doc = "y-intercept of 1st piece wise linear function"] + #[doc = "y-intercept of first piecewise linear function"] #[inline(always)] pub const fn b0(&self) -> u16 { let val = (self.0 >> 0usize) & 0x3fff; val as u16 } - #[doc = "y-intercept of 1st piece wise linear function"] + #[doc = "y-intercept of first piecewise linear function"] #[inline(always)] pub fn set_b0(&mut self, val: u16) { self.0 = (self.0 & !(0x3fff << 0usize)) | (((val as u32) & 0x3fff) << 0usize); @@ -20729,18 +20903,18 @@ pub mod temp { B0(0) } } - #[doc = "y-intercept of 2nd piece wise linear function"] + #[doc = "y-intercept of second piecewise linear function"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct B1(pub u32); impl B1 { - #[doc = "y-intercept of 2nd piece wise linear function"] + #[doc = "y-intercept of second piecewise linear function"] #[inline(always)] pub const fn b1(&self) -> u16 { let val = (self.0 >> 0usize) & 0x3fff; val as u16 } - #[doc = "y-intercept of 2nd piece wise linear function"] + #[doc = "y-intercept of second piecewise linear function"] #[inline(always)] pub fn set_b1(&mut self, val: u16) { self.0 = (self.0 & !(0x3fff << 0usize)) | (((val as u32) & 0x3fff) << 0usize); @@ -20752,18 +20926,18 @@ pub mod temp { B1(0) } } - #[doc = "y-intercept of 3rd piece wise linear function"] + #[doc = "y-intercept of third piecewise linear function"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct B2(pub u32); impl B2 { - #[doc = "y-intercept of 3rd piece wise linear function"] + #[doc = "y-intercept of third piecewise linear function"] #[inline(always)] pub const fn b2(&self) -> u16 { let val = (self.0 >> 0usize) & 0x3fff; val as u16 } - #[doc = "y-intercept of 3rd piece wise linear function"] + #[doc = "y-intercept of third piecewise linear function"] #[inline(always)] pub fn set_b2(&mut self, val: u16) { self.0 = (self.0 & !(0x3fff << 0usize)) | (((val as u32) & 0x3fff) << 0usize); @@ -20775,18 +20949,18 @@ pub mod temp { B2(0) } } - #[doc = "y-intercept of 4th piece wise linear function"] + #[doc = "y-intercept of fourth piecewise linear function"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct B3(pub u32); impl B3 { - #[doc = "y-intercept of 4th piece wise linear function"] + #[doc = "y-intercept of fourth piecewise linear function"] #[inline(always)] pub const fn b3(&self) -> u16 { let val = (self.0 >> 0usize) & 0x3fff; val as u16 } - #[doc = "y-intercept of 4th piece wise linear function"] + #[doc = "y-intercept of fourth piecewise linear function"] #[inline(always)] pub fn set_b3(&mut self, val: u16) { self.0 = (self.0 & !(0x3fff << 0usize)) | (((val as u32) & 0x3fff) << 0usize); @@ -20798,18 +20972,18 @@ pub mod temp { B3(0) } } - #[doc = "y-intercept of 5th piece wise linear function"] + #[doc = "y-intercept of fifth piecewise linear function"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct B4(pub u32); impl B4 { - #[doc = "y-intercept of 5th piece wise linear function"] + #[doc = "y-intercept of fifth piecewise linear function"] #[inline(always)] pub const fn b4(&self) -> u16 { let val = (self.0 >> 0usize) & 0x3fff; val as u16 } - #[doc = "y-intercept of 5th piece wise linear function"] + #[doc = "y-intercept of fifth piecewise linear function"] #[inline(always)] pub fn set_b4(&mut self, val: u16) { self.0 = (self.0 & !(0x3fff << 0usize)) | (((val as u32) & 0x3fff) << 0usize); @@ -20821,18 +20995,18 @@ pub mod temp { B4(0) } } - #[doc = "y-intercept of 6th piece wise linear function"] + #[doc = "y-intercept of sixth piecewise linear function"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct B5(pub u32); impl B5 { - #[doc = "y-intercept of 6th piece wise linear function"] + #[doc = "y-intercept of sixth piecewise linear function"] #[inline(always)] pub const fn b5(&self) -> u16 { let val = (self.0 >> 0usize) & 0x3fff; val as u16 } - #[doc = "y-intercept of 6th piece wise linear function"] + #[doc = "y-intercept of sixth piecewise linear function"] #[inline(always)] pub fn set_b5(&mut self, val: u16) { self.0 = (self.0 & !(0x3fff << 0usize)) | (((val as u32) & 0x3fff) << 0usize); @@ -20867,18 +21041,18 @@ pub mod temp { Inten(0) } } - #[doc = "End point of 1st piece wise linear function"] + #[doc = "End point of first piecewise linear function"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct T0(pub u32); impl T0 { - #[doc = "End point of 1st piece wise linear function"] + #[doc = "End point of first piecewise linear function"] #[inline(always)] pub const fn t0(&self) -> u8 { let val = (self.0 >> 0usize) & 0xff; val as u8 } - #[doc = "End point of 1st piece wise linear function"] + #[doc = "End point of first piecewise linear function"] #[inline(always)] pub fn set_t0(&mut self, val: u8) { self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); @@ -20890,18 +21064,18 @@ pub mod temp { T0(0) } } - #[doc = "End point of 2nd piece wise linear function"] + #[doc = "End point of second piecewise linear function"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct T1(pub u32); impl T1 { - #[doc = "End point of 2nd piece wise linear function"] + #[doc = "End point of second piecewise linear function"] #[inline(always)] pub const fn t1(&self) -> u8 { let val = (self.0 >> 0usize) & 0xff; val as u8 } - #[doc = "End point of 2nd piece wise linear function"] + #[doc = "End point of second piecewise linear function"] #[inline(always)] pub fn set_t1(&mut self, val: u8) { self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); @@ -20913,18 +21087,18 @@ pub mod temp { T1(0) } } - #[doc = "End point of 3rd piece wise linear function"] + #[doc = "End point of third piecewise linear function"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct T2(pub u32); impl T2 { - #[doc = "End point of 3rd piece wise linear function"] + #[doc = "End point of third piecewise linear function"] #[inline(always)] pub const fn t2(&self) -> u8 { let val = (self.0 >> 0usize) & 0xff; val as u8 } - #[doc = "End point of 3rd piece wise linear function"] + #[doc = "End point of third piecewise linear function"] #[inline(always)] pub fn set_t2(&mut self, val: u8) { self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); @@ -20936,18 +21110,18 @@ pub mod temp { T2(0) } } - #[doc = "End point of 4th piece wise linear function"] + #[doc = "End point of fourth piecewise linear function"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct T3(pub u32); impl T3 { - #[doc = "End point of 4th piece wise linear function"] + #[doc = "End point of fourth piecewise linear function"] #[inline(always)] pub const fn t3(&self) -> u8 { let val = (self.0 >> 0usize) & 0xff; val as u8 } - #[doc = "End point of 4th piece wise linear function"] + #[doc = "End point of fourth piecewise linear function"] #[inline(always)] pub fn set_t3(&mut self, val: u8) { self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); @@ -20959,18 +21133,18 @@ pub mod temp { T3(0) } } - #[doc = "End point of 5th piece wise linear function"] + #[doc = "End point of fifth piecewise linear function"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct T4(pub u32); impl T4 { - #[doc = "End point of 5th piece wise linear function"] + #[doc = "End point of fifth piecewise linear function"] #[inline(always)] pub const fn t4(&self) -> u8 { let val = (self.0 >> 0usize) & 0xff; val as u8 } - #[doc = "End point of 5th piece wise linear function"] + #[doc = "End point of fifth piecewise linear function"] #[inline(always)] pub fn set_t4(&mut self, val: u8) { self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); @@ -21904,7 +22078,7 @@ pub mod twim { pub const fn events_error(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0124usize) as _) } } - #[doc = "Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended."] + #[doc = "SUSPEND task has been issued, TWI traffic is now suspended."] #[inline(always)] pub const fn events_suspended(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0148usize) as _) } @@ -23046,13 +23220,13 @@ pub mod twis { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Match(pub u32); impl Match { - #[doc = "Which of the addresses in {ADDRESS} matched the incoming address"] + #[doc = "Indication of which address in {ADDRESS} that matched the incoming address"] #[inline(always)] pub const fn match_(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Which of the addresses in {ADDRESS} matched the incoming address"] + #[doc = "Indication of which address in {ADDRESS} that matched the incoming address"] #[inline(always)] pub fn set_match_(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); @@ -24272,7 +24446,7 @@ pub mod uarte { pub const fn intenclr(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0308usize) as _) } } - #[doc = "Error source Note : this register is read / write one to clear."] + #[doc = "Error source This register is read/write one to clear."] #[inline(always)] pub const fn errorsrc(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0480usize) as _) } @@ -24412,7 +24586,7 @@ pub mod uarte { Enable(0) } } - #[doc = "Error source Note : this register is read / write one to clear."] + #[doc = "Error source This register is read/write one to clear."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Errorsrc(pub u32); @@ -24767,7 +24941,7 @@ pub mod uarte { pub const BAUD460800: Self = Self(0x0740_0000); #[doc = "921600 baud (actual rate: 941176)"] pub const BAUD921600: Self = Self(0x0f00_0000); - #[doc = "1Mega baud"] + #[doc = "1 megabaud"] pub const BAUD1M: Self = Self(0x1000_0000); } impl Baudrate { @@ -24991,7 +25165,7 @@ pub mod uicr { pub const fn debugctrl(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0210usize) as _) } } - #[doc = "Output voltage from REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - VREG0DROP."] + #[doc = "Output voltage from REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - V_VDDH-VDD."] #[inline(always)] pub const fn regout0(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0304usize) as _) } @@ -25078,7 +25252,7 @@ pub mod uicr { Nfcpins(0) } } - #[doc = "Output voltage from REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - VREG0DROP."] + #[doc = "Output voltage from REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - V_VDDH-VDD."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Regout0(pub u32); @@ -25167,7 +25341,9 @@ pub mod uicr { impl Pall { #[doc = "Enable"] pub const ENABLED: Self = Self(0x0); - #[doc = "Disable"] + #[doc = "Hardware disable of access port protection for devices where access port protection is controlled by hardware and software"] + pub const HW_DISABLED: Self = Self(0x5a); + #[doc = "Hardware disable of access port protection for devices where access port protection is controlled by hardware"] pub const DISABLED: Self = Self(0xff); } impl Pall { @@ -25193,9 +25369,9 @@ pub mod uicr { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Protect { - #[doc = "Operation as GPIO pins. Same protection as normal GPIO pins"] + #[doc = "Operation as GPIO pins. Same protection as normal GPIO pins."] DISABLED = 0x0, - #[doc = "Operation as NFC antenna pins. Configures the protection for NFC operation"] + #[doc = "Operation as NFC antenna pins. Configures the protection for NFC operation."] NFC = 0x01, } impl Protect { @@ -27405,7 +27581,7 @@ pub mod usbd { #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub struct Split(pub u16); impl Split { - #[doc = "Full buffer dedicated to either iso IN or OUT"] + #[doc = "Full buffer dedicated to either ISO IN or OUT"] pub const ONE_DIR: Self = Self(0x0); #[doc = "Lower half for IN, upper half for OUT"] pub const HALF_IN: Self = Self(0x80); diff --git a/src/chips/nrf52840/pac.rs b/src/chips/nrf52840/pac.rs index 96dc91d..d3c3f83 100644 --- a/src/chips/nrf52840/pac.rs +++ b/src/chips/nrf52840/pac.rs @@ -1,16 +1,16 @@ -#![doc = "Peripheral access API (generated using chiptool v0.1.0 (218daa7 2024-01-15))"] +#![doc = "Peripheral access API (generated using chiptool v0.1.0 (4df74f6 2024-11-11))"] #[derive(Copy, Clone, Debug, PartialEq, Eq)] pub enum Interrupt { - #[doc = "0 - POWER_CLOCK"] - POWER_CLOCK = 0, + #[doc = "0 - CLOCK_POWER"] + CLOCK_POWER = 0, #[doc = "1 - RADIO"] RADIO = 1, - #[doc = "2 - UARTE0_UART0"] - UARTE0_UART0 = 2, - #[doc = "3 - SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0"] - SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 = 3, - #[doc = "4 - SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1"] - SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 = 4, + #[doc = "2 - UART0_UARTE0"] + UART0_UARTE0 = 2, + #[doc = "3 - SPI0_SPIM0_SPIS0_TWI0_TWIM0_TWIS0"] + SPI0_SPIM0_SPIS0_TWI0_TWIM0_TWIS0 = 3, + #[doc = "4 - SPI1_SPIM1_SPIS1_TWI1_TWIM1_TWIS1"] + SPI1_SPIM1_SPIS1_TWI1_TWIM1_TWIS1 = 4, #[doc = "5 - NFCT"] NFCT = 5, #[doc = "6 - GPIOTE"] @@ -31,8 +31,8 @@ pub enum Interrupt { RNG = 13, #[doc = "14 - ECB"] ECB = 14, - #[doc = "15 - CCM_AAR"] - CCM_AAR = 15, + #[doc = "15 - AAR_CCM"] + AAR_CCM = 15, #[doc = "16 - WDT"] WDT = 16, #[doc = "17 - RTC1"] @@ -41,18 +41,18 @@ pub enum Interrupt { QDEC = 18, #[doc = "19 - COMP_LPCOMP"] COMP_LPCOMP = 19, - #[doc = "20 - SWI0_EGU0"] - SWI0_EGU0 = 20, - #[doc = "21 - SWI1_EGU1"] - SWI1_EGU1 = 21, - #[doc = "22 - SWI2_EGU2"] - SWI2_EGU2 = 22, - #[doc = "23 - SWI3_EGU3"] - SWI3_EGU3 = 23, - #[doc = "24 - SWI4_EGU4"] - SWI4_EGU4 = 24, - #[doc = "25 - SWI5_EGU5"] - SWI5_EGU5 = 25, + #[doc = "20 - EGU0_SWI0"] + EGU0_SWI0 = 20, + #[doc = "21 - EGU1_SWI1"] + EGU1_SWI1 = 21, + #[doc = "22 - EGU2_SWI2"] + EGU2_SWI2 = 22, + #[doc = "23 - EGU3_SWI3"] + EGU3_SWI3 = 23, + #[doc = "24 - EGU4_SWI4"] + EGU4_SWI4 = 24, + #[doc = "25 - EGU5_SWI5"] + EGU5_SWI5 = 25, #[doc = "26 - TIMER3"] TIMER3 = 26, #[doc = "27 - TIMER4"] @@ -67,8 +67,8 @@ pub enum Interrupt { PWM1 = 33, #[doc = "34 - PWM2"] PWM2 = 34, - #[doc = "35 - SPIM2_SPIS2_SPI2"] - SPIM2_SPIS2_SPI2 = 35, + #[doc = "35 - SPI2_SPIM2_SPIS2"] + SPI2_SPIM2_SPIS2 = 35, #[doc = "36 - RTC2"] RTC2 = 36, #[doc = "37 - I2S"] @@ -97,11 +97,11 @@ unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt { #[cfg(feature = "rt")] mod _vectors { extern "C" { - fn POWER_CLOCK(); + fn CLOCK_POWER(); fn RADIO(); - fn UARTE0_UART0(); - fn SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0(); - fn SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1(); + fn UART0_UARTE0(); + fn SPI0_SPIM0_SPIS0_TWI0_TWIM0_TWIS0(); + fn SPI1_SPIM1_SPIS1_TWI1_TWIM1_TWIS1(); fn NFCT(); fn GPIOTE(); fn SAADC(); @@ -112,17 +112,17 @@ mod _vectors { fn TEMP(); fn RNG(); fn ECB(); - fn CCM_AAR(); + fn AAR_CCM(); fn WDT(); fn RTC1(); fn QDEC(); fn COMP_LPCOMP(); - fn SWI0_EGU0(); - fn SWI1_EGU1(); - fn SWI2_EGU2(); - fn SWI3_EGU3(); - fn SWI4_EGU4(); - fn SWI5_EGU5(); + fn EGU0_SWI0(); + fn EGU1_SWI1(); + fn EGU2_SWI2(); + fn EGU3_SWI3(); + fn EGU4_SWI4(); + fn EGU5_SWI5(); fn TIMER3(); fn TIMER4(); fn PWM0(); @@ -130,7 +130,7 @@ mod _vectors { fn MWU(); fn PWM1(); fn PWM2(); - fn SPIM2_SPIS2_SPI2(); + fn SPI2_SPIM2_SPIS2(); fn RTC2(); fn I2S(); fn FPU(); @@ -149,17 +149,17 @@ mod _vectors { #[no_mangle] pub static __INTERRUPTS: [Vector; 48] = [ Vector { - _handler: POWER_CLOCK, + _handler: CLOCK_POWER, }, Vector { _handler: RADIO }, Vector { - _handler: UARTE0_UART0, + _handler: UART0_UARTE0, }, Vector { - _handler: SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0, + _handler: SPI0_SPIM0_SPIS0_TWI0_TWIM0_TWIS0, }, Vector { - _handler: SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1, + _handler: SPI1_SPIM1_SPIS1_TWI1_TWIM1_TWIS1, }, Vector { _handler: NFCT }, Vector { _handler: GPIOTE }, @@ -171,7 +171,7 @@ mod _vectors { Vector { _handler: TEMP }, Vector { _handler: RNG }, Vector { _handler: ECB }, - Vector { _handler: CCM_AAR }, + Vector { _handler: AAR_CCM }, Vector { _handler: WDT }, Vector { _handler: RTC1 }, Vector { _handler: QDEC }, @@ -179,22 +179,22 @@ mod _vectors { _handler: COMP_LPCOMP, }, Vector { - _handler: SWI0_EGU0, + _handler: EGU0_SWI0, }, Vector { - _handler: SWI1_EGU1, + _handler: EGU1_SWI1, }, Vector { - _handler: SWI2_EGU2, + _handler: EGU2_SWI2, }, Vector { - _handler: SWI3_EGU3, + _handler: EGU3_SWI3, }, Vector { - _handler: SWI4_EGU4, + _handler: EGU4_SWI4, }, Vector { - _handler: SWI5_EGU5, + _handler: EGU5_SWI5, }, Vector { _handler: TIMER3 }, Vector { _handler: TIMER4 }, @@ -206,7 +206,7 @@ mod _vectors { Vector { _handler: PWM1 }, Vector { _handler: PWM2 }, Vector { - _handler: SPIM2_SPIS2_SPI2, + _handler: SPI2_SPIM2_SPIS2, }, Vector { _handler: RTC2 }, Vector { _handler: I2S }, @@ -228,6 +228,9 @@ mod _vectors { pub const FICR: ficr::Ficr = unsafe { ficr::Ficr::from_ptr(0x1000_0000usize as _) }; #[doc = "User information configuration registers"] pub const UICR: uicr::Uicr = unsafe { uicr::Uicr::from_ptr(0x1000_1000usize as _) }; +#[doc = "Access Port Protection"] +pub const APPROTECT: approtect::Approtect = + unsafe { approtect::Approtect::from_ptr(0x4000_0000usize as _) }; #[doc = "Clock control"] pub const CLOCK: clock::Clock = unsafe { clock::Clock::from_ptr(0x4000_0000usize as _) }; #[doc = "Power control"] @@ -284,7 +287,7 @@ pub const RNG: rng::Rng = unsafe { rng::Rng::from_ptr(0x4000_d000usize as _) }; pub const ECB: ecb::Ecb = unsafe { ecb::Ecb::from_ptr(0x4000_e000usize as _) }; #[doc = "Accelerated Address Resolver"] pub const AAR: aar::Aar = unsafe { aar::Aar::from_ptr(0x4000_f000usize as _) }; -#[doc = "AES CCM Mode Encryption"] +#[doc = "AES CCM mode encryption"] pub const CCM: ccm::Ccm = unsafe { ccm::Ccm::from_ptr(0x4000_f000usize as _) }; #[doc = "Watchdog Timer"] pub const WDT: wdt::Wdt = unsafe { wdt::Wdt::from_ptr(0x4001_0000usize as _) }; @@ -294,36 +297,36 @@ pub const RTC1: rtc::Rtc = unsafe { rtc::Rtc::from_ptr(0x4001_1000usize as _) }; pub const QDEC: qdec::Qdec = unsafe { qdec::Qdec::from_ptr(0x4001_2000usize as _) }; #[doc = "Comparator"] pub const COMP: comp::Comp = unsafe { comp::Comp::from_ptr(0x4001_3000usize as _) }; -#[doc = "Low Power Comparator"] +#[doc = "Low-power comparator"] pub const LPCOMP: lpcomp::Lpcomp = unsafe { lpcomp::Lpcomp::from_ptr(0x4001_3000usize as _) }; -#[doc = "Event Generator Unit 0"] +#[doc = "Event generator unit 0"] pub const EGU0: egu::Egu = unsafe { egu::Egu::from_ptr(0x4001_4000usize as _) }; #[doc = "Software interrupt 0"] pub const SWI0: swi::Swi = unsafe { swi::Swi::from_ptr(0x4001_4000usize as _) }; -#[doc = "Event Generator Unit 1"] +#[doc = "Event generator unit 1"] pub const EGU1: egu::Egu = unsafe { egu::Egu::from_ptr(0x4001_5000usize as _) }; #[doc = "Software interrupt 1"] pub const SWI1: swi::Swi = unsafe { swi::Swi::from_ptr(0x4001_5000usize as _) }; -#[doc = "Event Generator Unit 2"] +#[doc = "Event generator unit 2"] pub const EGU2: egu::Egu = unsafe { egu::Egu::from_ptr(0x4001_6000usize as _) }; #[doc = "Software interrupt 2"] pub const SWI2: swi::Swi = unsafe { swi::Swi::from_ptr(0x4001_6000usize as _) }; -#[doc = "Event Generator Unit 3"] +#[doc = "Event generator unit 3"] pub const EGU3: egu::Egu = unsafe { egu::Egu::from_ptr(0x4001_7000usize as _) }; #[doc = "Software interrupt 3"] pub const SWI3: swi::Swi = unsafe { swi::Swi::from_ptr(0x4001_7000usize as _) }; -#[doc = "Event Generator Unit 4"] +#[doc = "Event generator unit 4"] pub const EGU4: egu::Egu = unsafe { egu::Egu::from_ptr(0x4001_8000usize as _) }; #[doc = "Software interrupt 4"] pub const SWI4: swi::Swi = unsafe { swi::Swi::from_ptr(0x4001_8000usize as _) }; -#[doc = "Event Generator Unit 5"] +#[doc = "Event generator unit 5"] pub const EGU5: egu::Egu = unsafe { egu::Egu::from_ptr(0x4001_9000usize as _) }; #[doc = "Software interrupt 5"] pub const SWI5: swi::Swi = unsafe { swi::Swi::from_ptr(0x4001_9000usize as _) }; #[doc = "Timer/Counter 3"] -pub const TIMER3: timer3::Timer3 = unsafe { timer3::Timer3::from_ptr(0x4001_a000usize as _) }; +pub const TIMER3: timer::Timer = unsafe { timer::Timer::from_ptr(0x4001_a000usize as _) }; #[doc = "Timer/Counter 4"] -pub const TIMER4: timer3::Timer3 = unsafe { timer3::Timer3::from_ptr(0x4001_b000usize as _) }; +pub const TIMER4: timer::Timer = unsafe { timer::Timer::from_ptr(0x4001_b000usize as _) }; #[doc = "Pulse width modulation unit 0"] pub const PWM0: pwm::Pwm = unsafe { pwm::Pwm::from_ptr(0x4001_c000usize as _) }; #[doc = "Pulse Density Modulation (Digital Microphone) Interface"] @@ -362,16 +365,38 @@ pub const QSPI: qspi::Qspi = unsafe { qspi::Qspi::from_ptr(0x4002_9000usize as _ pub const PWM3: pwm::Pwm = unsafe { pwm::Pwm::from_ptr(0x4002_d000usize as _) }; #[doc = "Serial Peripheral Interface Master with EasyDMA 3"] pub const SPIM3: spim::Spim = unsafe { spim::Spim::from_ptr(0x4002_f000usize as _) }; -#[doc = "GPIO Port 1"] +#[doc = "GPIO Port 0"] pub const P0: gpio::Gpio = unsafe { gpio::Gpio::from_ptr(0x5000_0000usize as _) }; -#[doc = "GPIO Port 2"] +#[doc = "GPIO Port 1"] pub const P1: gpio::Gpio = unsafe { gpio::Gpio::from_ptr(0x5000_0300usize as _) }; -#[doc = "CRYPTOCELL HOST_RGF interface"] -pub const CC_HOST_RGF: cc_host_rgf::CcHostRgf = - unsafe { cc_host_rgf::CcHostRgf::from_ptr(0x5002_a000usize as _) }; -#[doc = "ARM TrustZone CryptoCell register interface"] +#[doc = "CRYPTOCELL register interface"] pub const CRYPTOCELL: cryptocell::Cryptocell = unsafe { cryptocell::Cryptocell::from_ptr(0x5002_a000usize as _) }; +#[doc = "CRYPTOCELL AES engine"] +pub const CC_AES: cc_aes::CcAes = unsafe { cc_aes::CcAes::from_ptr(0x5002_b000usize as _) }; +#[doc = "CRYPTOCELL CHACHA engine"] +pub const CC_CHACHA: cc_chacha::CcChacha = + unsafe { cc_chacha::CcChacha::from_ptr(0x5002_b000usize as _) }; +#[doc = "CRYPTOCELL CTL interface"] +pub const CC_CTL: cc_ctl::CcCtl = unsafe { cc_ctl::CcCtl::from_ptr(0x5002_b000usize as _) }; +#[doc = "CRYPTOCELL Data IN interface"] +pub const CC_DIN: cc_din::CcDin = unsafe { cc_din::CcDin::from_ptr(0x5002_b000usize as _) }; +#[doc = "CRYPTOCELL Data OUT interface"] +pub const CC_DOUT: cc_dout::CcDout = unsafe { cc_dout::CcDout::from_ptr(0x5002_b000usize as _) }; +#[doc = "CRYPTOCELL HASH engine"] +pub const CC_HASH: cc_hash::CcHash = unsafe { cc_hash::CcHash::from_ptr(0x5002_b000usize as _) }; +#[doc = "CRYPTOCELL HOST register interface"] +pub const CC_HOST_RGF: cc_host_rgf::CcHostRgf = + unsafe { cc_host_rgf::CcHostRgf::from_ptr(0x5002_b000usize as _) }; +#[doc = "CRYPTOCELL MISC interface"] +pub const CC_MISC: cc_misc::CcMisc = unsafe { cc_misc::CcMisc::from_ptr(0x5002_b000usize as _) }; +#[doc = "CRYPTOCELL PKA engine"] +pub const CC_PKA: cc_pka::CcPka = unsafe { cc_pka::CcPka::from_ptr(0x5002_b000usize as _) }; +#[doc = "CRYPTOCELL RNG engine"] +pub const CC_RNG: cc_rng::CcRng = unsafe { cc_rng::CcRng::from_ptr(0x5002_b000usize as _) }; +#[doc = "CRYPTOCELL RNG SRAM interface"] +pub const CC_RNG_SRAM: cc_rng_sram::CcRngSram = + unsafe { cc_rng_sram::CcRngSram::from_ptr(0x5002_b000usize as _) }; #[doc = r" Number available in the NVIC for configuring priority"] #[cfg(feature = "rt")] pub const NVIC_PRIO_BITS: u8 = 3; @@ -491,35 +516,35 @@ pub mod aar { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Inten(pub u32); impl Inten { - #[doc = "Write '1' to disable interrupt for END event"] + #[doc = "Write '1' to disable interrupt for event END"] #[inline(always)] pub const fn end(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for END event"] + #[doc = "Write '1' to disable interrupt for event END"] #[inline(always)] pub fn set_end(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - #[doc = "Write '1' to disable interrupt for RESOLVED event"] + #[doc = "Write '1' to disable interrupt for event RESOLVED"] #[inline(always)] pub const fn resolved(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for RESOLVED event"] + #[doc = "Write '1' to disable interrupt for event RESOLVED"] #[inline(always)] pub fn set_resolved(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } - #[doc = "Write '1' to disable interrupt for NOTRESOLVED event"] + #[doc = "Write '1' to disable interrupt for event NOTRESOLVED"] #[inline(always)] pub const fn notresolved(&self) -> bool { let val = (self.0 >> 2usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for NOTRESOLVED event"] + #[doc = "Write '1' to disable interrupt for event NOTRESOLVED"] #[inline(always)] pub fn set_notresolved(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); @@ -536,13 +561,13 @@ pub mod aar { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Nirk(pub u32); impl Nirk { - #[doc = "Number of Identity root keys available in the IRK data structure"] + #[doc = "Number of Identity Root Keys available in the IRK data structure"] #[inline(always)] pub const fn nirk(&self) -> u8 { let val = (self.0 >> 0usize) & 0x1f; val as u8 } - #[doc = "Number of Identity root keys available in the IRK data structure"] + #[doc = "Number of Identity Root Keys available in the IRK data structure"] #[inline(always)] pub fn set_nirk(&mut self, val: u8) { self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize); @@ -653,51 +678,46 @@ pub mod acl { pub const fn as_ptr(&self) -> *mut () { self.ptr as _ } - #[doc = "Description cluster\\[n\\]: Configure the word-aligned start address of region n to protect"] + #[doc = "Description cluster: Start address of region to protect. The start address must be word-aligned."] #[inline(always)] pub const fn addr(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } - #[doc = "Description cluster\\[n\\]: Size of region to protect counting from address ACL\\[n\\].ADDR. Write '0' as no effect."] + #[doc = "Description cluster: Size of region to protect counting from address ACL\\[n\\].ADDR. Writing a '0' has no effect."] #[inline(always)] pub const fn size(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } - #[doc = "Description cluster\\[n\\]: Access permissions for region n as defined by start address ACL\\[n\\].ADDR and size ACL\\[n\\].SIZE"] + #[doc = "Description cluster: Access permissions for region n as defined by start address ACL\\[n\\].ADDR and size ACL\\[n\\].SIZE"] #[inline(always)] pub const fn perm(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } - #[doc = "Unspecified"] - #[inline(always)] - pub const fn unused0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } - } } pub mod regs { - #[doc = "Description cluster\\[n\\]: Access permissions for region n as defined by start address ACL\\[n\\].ADDR and size ACL\\[n\\].SIZE"] + #[doc = "Description cluster: Access permissions for region n as defined by start address ACL\\[n\\].ADDR and size ACL\\[n\\].SIZE"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Perm(pub u32); impl Perm { - #[doc = "Configure write and erase permissions for region n. Write '0' has no effect."] + #[doc = "Configure write and erase permissions for region n. Writing a '0' has no effect."] #[inline(always)] pub const fn write(&self) -> super::vals::Write { let val = (self.0 >> 1usize) & 0x01; super::vals::Write::from_bits(val as u8) } - #[doc = "Configure write and erase permissions for region n. Write '0' has no effect."] + #[doc = "Configure write and erase permissions for region n. Writing a '0' has no effect."] #[inline(always)] pub fn set_write(&mut self, val: super::vals::Write) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val.to_bits() as u32) & 0x01) << 1usize); } - #[doc = "Configure read permissions for region n. Write '0' has no effect."] + #[doc = "Configure read permissions for region n. Writing a '0' has no effect."] #[inline(always)] pub const fn read(&self) -> super::vals::Read { let val = (self.0 >> 2usize) & 0x01; super::vals::Read::from_bits(val as u8) } - #[doc = "Configure read permissions for region n. Write '0' has no effect."] + #[doc = "Configure read permissions for region n. Writing a '0' has no effect."] #[inline(always)] pub fn set_read(&mut self, val: super::vals::Read) { self.0 = (self.0 & !(0x01 << 2usize)) | (((val.to_bits() as u32) & 0x01) << 2usize); @@ -714,9 +734,9 @@ pub mod acl { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Read { - #[doc = "Allow read instructions to region n"] + #[doc = "Allow read instructions to region n."] ENABLE = 0x0, - #[doc = "Block read instructions to region n"] + #[doc = "Block read instructions to region n."] DISABLE = 0x01, } impl Read { @@ -744,9 +764,9 @@ pub mod acl { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Write { - #[doc = "Allow write and erase instructions to region n"] + #[doc = "Allow write and erase instructions to region n."] ENABLE = 0x0, - #[doc = "Block write and erase instructions to region n"] + #[doc = "Block write and erase instructions to region n."] DISABLE = 0x01, } impl Write { @@ -773,15 +793,15 @@ pub mod acl { } } } -pub mod cc_host_rgf { - #[doc = "CRYPTOCELL HOST_RGF interface"] +pub mod approtect { + #[doc = "Access Port Protection"] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct CcHostRgf { + pub struct Approtect { ptr: *mut u8, } - unsafe impl Send for CcHostRgf {} - unsafe impl Sync for CcHostRgf {} - impl CcHostRgf { + unsafe impl Send for Approtect {} + unsafe impl Sync for Approtect {} + impl Approtect { #[inline(always)] pub const unsafe fn from_ptr(ptr: *mut ()) -> Self { Self { ptr: ptr as _ } @@ -790,209 +810,133 @@ pub mod cc_host_rgf { pub const fn as_ptr(&self) -> *mut () { self.ptr as _ } - #[doc = "AES hardware key select"] - #[inline(always)] - pub const fn host_cryptokey_sel( - self, - ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1a38usize) as _) } - } - #[doc = "This write-once register is the K_PRTL lock register. When this register is set, K_PRTL can not be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain."] + #[doc = "Software force enable APPROTECT mechanism until next reset."] #[inline(always)] - pub const fn host_iot_kprtl_lock( + pub const fn forceprotect( self, - ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1a4cusize) as _) } - } - #[doc = "This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained."] - #[inline(always)] - pub const fn host_iot_kdr0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1a50usize) as _) } - } - #[doc = "This register holds bits 63:32 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain."] - #[inline(always)] - pub const fn host_iot_kdr1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1a54usize) as _) } - } - #[doc = "This register holds bits 95:64 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain."] - #[inline(always)] - pub const fn host_iot_kdr2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1a58usize) as _) } - } - #[doc = "This register holds bits 127:96 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain."] - #[inline(always)] - pub const fn host_iot_kdr3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1a5cusize) as _) } + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0550usize) as _) } } - #[doc = "Controls lifecycle state (LCS) for CRYPTOCELL subsystem"] + #[doc = "Software disable APPROTECT mechanism"] #[inline(always)] - pub const fn host_iot_lcs(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1a60usize) as _) } + pub const fn disable(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0558usize) as _) } } } pub mod regs { - #[doc = "AES hardware key select"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct HostCryptokeySel(pub u32); - impl HostCryptokeySel { - #[doc = "Select the source of the HW key that is used by the AES engine"] - #[inline(always)] - pub const fn host_cryptokey_sel(&self) -> super::vals::HostCryptokeySel { - let val = (self.0 >> 0usize) & 0x03; - super::vals::HostCryptokeySel::from_bits(val as u8) - } - #[doc = "Select the source of the HW key that is used by the AES engine"] - #[inline(always)] - pub fn set_host_cryptokey_sel(&mut self, val: super::vals::HostCryptokeySel) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - } - impl Default for HostCryptokeySel { - #[inline(always)] - fn default() -> HostCryptokeySel { - HostCryptokeySel(0) - } - } - #[doc = "This write-once register is the K_PRTL lock register. When this register is set, K_PRTL can not be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain."] + #[doc = "Software disable APPROTECT mechanism"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct HostIotKprtlLock(pub u32); - impl HostIotKprtlLock { - #[doc = "This register is the K_PRTL lock register. When this register is set, K_PRTL can not be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain."] + pub struct Disable(pub u32); + impl Disable { + #[doc = "Software disable APPROTECT mechanism"] #[inline(always)] - pub const fn host_iot_kprtl_lock(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 + pub const fn disable(&self) -> super::vals::Disable { + let val = (self.0 >> 0usize) & 0xff; + super::vals::Disable::from_bits(val as u8) } - #[doc = "This register is the K_PRTL lock register. When this register is set, K_PRTL can not be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain."] + #[doc = "Software disable APPROTECT mechanism"] #[inline(always)] - pub fn set_host_iot_kprtl_lock(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + pub fn set_disable(&mut self, val: super::vals::Disable) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val.to_bits() as u32) & 0xff) << 0usize); } } - impl Default for HostIotKprtlLock { + impl Default for Disable { #[inline(always)] - fn default() -> HostIotKprtlLock { - HostIotKprtlLock(0) + fn default() -> Disable { + Disable(0) } } - #[doc = "Controls lifecycle state (LCS) for CRYPTOCELL subsystem"] + #[doc = "Software force enable APPROTECT mechanism until next reset."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct HostIotLcs(pub u32); - impl HostIotLcs { - #[doc = "Lifecycle state value. This field is write-once per reset."] - #[inline(always)] - pub const fn lcs(&self) -> super::vals::Lcs { - let val = (self.0 >> 0usize) & 0x07; - super::vals::Lcs::from_bits(val as u8) - } - #[doc = "Lifecycle state value. This field is write-once per reset."] - #[inline(always)] - pub fn set_lcs(&mut self, val: super::vals::Lcs) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); - } - #[doc = "This field is read-only and indicates if CRYPTOCELL LCS has been successfully configured since last reset"] + pub struct Forceprotect(pub u32); + impl Forceprotect { + #[doc = "Write 0x0 to force enable APPROTECT mechanism"] #[inline(always)] - pub const fn lcs_is_valid(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 + pub const fn forceprotect(&self) -> super::vals::Forceprotect { + let val = (self.0 >> 0usize) & 0xff; + super::vals::Forceprotect::from_bits(val as u8) } - #[doc = "This field is read-only and indicates if CRYPTOCELL LCS has been successfully configured since last reset"] + #[doc = "Write 0x0 to force enable APPROTECT mechanism"] #[inline(always)] - pub fn set_lcs_is_valid(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + pub fn set_forceprotect(&mut self, val: super::vals::Forceprotect) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val.to_bits() as u32) & 0xff) << 0usize); } } - impl Default for HostIotLcs { + impl Default for Forceprotect { #[inline(always)] - fn default() -> HostIotLcs { - HostIotLcs(0) + fn default() -> Forceprotect { + Forceprotect(0) } } } pub mod vals { - #[repr(u8)] + #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub enum HostCryptokeySel { - #[doc = "Use device root key K_DR from CRYPTOCELL AO power domain"] - K_DR = 0x0, - #[doc = "Use hard-coded RTL key K_PRTL"] - K_PRTL = 0x01, - #[doc = "Use provided session key"] - SESSION = 0x02, - _RESERVED_3 = 0x03, + pub struct Disable(pub u8); + impl Disable { + #[doc = "Software disable APPROTECT mechanism"] + pub const SW_DISABLE: Self = Self(0x5a); } - impl HostCryptokeySel { - #[inline(always)] - pub const fn from_bits(val: u8) -> HostCryptokeySel { - unsafe { core::mem::transmute(val & 0x03) } + impl Disable { + pub const fn from_bits(val: u8) -> Disable { + Self(val & 0xff) } - #[inline(always)] pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } + self.0 } } - impl From for HostCryptokeySel { + impl From for Disable { #[inline(always)] - fn from(val: u8) -> HostCryptokeySel { - HostCryptokeySel::from_bits(val) + fn from(val: u8) -> Disable { + Disable::from_bits(val) } } - impl From for u8 { + impl From for u8 { #[inline(always)] - fn from(val: HostCryptokeySel) -> u8 { - HostCryptokeySel::to_bits(val) + fn from(val: Disable) -> u8 { + Disable::to_bits(val) } } - #[repr(u8)] + #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub enum Lcs { - #[doc = "CC310 operates in debug mode"] - DEBUG = 0x0, - _RESERVED_1 = 0x01, - #[doc = "CC310 operates in secure mode"] - SECURE = 0x02, - _RESERVED_3 = 0x03, - _RESERVED_4 = 0x04, - _RESERVED_5 = 0x05, - _RESERVED_6 = 0x06, - _RESERVED_7 = 0x07, + pub struct Forceprotect(pub u8); + impl Forceprotect { + #[doc = "Software force enable APPROTECT mechanism"] + pub const FORCE: Self = Self(0x0); } - impl Lcs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Lcs { - unsafe { core::mem::transmute(val & 0x07) } + impl Forceprotect { + pub const fn from_bits(val: u8) -> Forceprotect { + Self(val & 0xff) } - #[inline(always)] pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } + self.0 } } - impl From for Lcs { + impl From for Forceprotect { #[inline(always)] - fn from(val: u8) -> Lcs { - Lcs::from_bits(val) + fn from(val: u8) -> Forceprotect { + Forceprotect::from_bits(val) } } - impl From for u8 { + impl From for u8 { #[inline(always)] - fn from(val: Lcs) -> u8 { - Lcs::to_bits(val) + fn from(val: Forceprotect) -> u8 { + Forceprotect::to_bits(val) } } } } -pub mod ccm { - #[doc = "AES CCM Mode Encryption"] +pub mod cc_aes { + #[doc = "CRYPTOCELL AES engine"] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ccm { + pub struct CcAes { ptr: *mut u8, } - unsafe impl Send for Ccm {} - unsafe impl Sync for Ccm {} - impl Ccm { + unsafe impl Send for CcAes {} + unsafe impl Sync for CcAes {} + impl CcAes { #[inline(always)] pub const unsafe fn from_ptr(ptr: *mut ()) -> Self { Self { ptr: ptr as _ } @@ -1001,423 +945,529 @@ pub mod ccm { pub const fn as_ptr(&self) -> *mut () { self.ptr as _ } - #[doc = "Start generation of key-stream. This operation will stop by itself when completed."] - #[inline(always)] - pub const fn tasks_ksgen(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } - } - #[doc = "Start encryption/decryption. This operation will stop by itself when completed."] - #[inline(always)] - pub const fn tasks_crypt(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } - } - #[doc = "Stop encryption/decryption"] - #[inline(always)] - pub const fn tasks_stop(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } - } - #[doc = "Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption"] - #[inline(always)] - pub const fn tasks_rateoverride(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } - } - #[doc = "Key-stream generation complete"] - #[inline(always)] - pub const fn events_endksgen(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0100usize) as _) } - } - #[doc = "Encrypt/decrypt complete"] - #[inline(always)] - pub const fn events_endcrypt(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0104usize) as _) } - } - #[doc = "Deprecated register - CCM error event"] - #[inline(always)] - pub const fn events_error(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0108usize) as _) } - } - #[doc = "Shortcut register"] + #[doc = "Description collection: AES key value to use. The initial AES_KEY_0\\[0\\] register holds the least significant bits \\[31:0\\] of the key value."] #[inline(always)] - pub const fn shorts(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0200usize) as _) } + pub const fn aes_key_0(self, n: usize) -> crate::common::Reg { + assert!(n < 8usize); + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0400usize + n * 4usize) as _) } } - #[doc = "Enable interrupt"] + #[doc = "Description collection: AES Initialization Vector (IV) to use. The initial AES_IV_0\\[0\\] register holds the least significant bits \\[31:0\\] of the IV."] #[inline(always)] - pub const fn intenset(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0304usize) as _) } + pub const fn aes_iv_0(self, n: usize) -> crate::common::Reg { + assert!(n < 4usize); + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0440usize + n * 4usize) as _) } } - #[doc = "Disable interrupt"] + #[doc = "Description collection: AES counter (CTR) to use. The initial AES_CTR\\[0\\] register holds the least significant bits \\[31:0\\] of the CTR."] #[inline(always)] - pub const fn intenclr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0308usize) as _) } + pub const fn aes_ctr(self, n: usize) -> crate::common::Reg { + assert!(n < 4usize); + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0460usize + n * 4usize) as _) } } - #[doc = "MIC check result"] + #[doc = "Status register for AES engine activity."] #[inline(always)] - pub const fn micstatus(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0400usize) as _) } + pub const fn aes_busy(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0470usize) as _) } } - #[doc = "Enable"] + #[doc = "Writing to this address trigger sampling of the HW key to the AES_KEY_0 register"] #[inline(always)] - pub const fn enable(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0500usize) as _) } + pub const fn aes_sk(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0478usize) as _) } } - #[doc = "Operation mode"] + #[doc = "Writing to this address triggers the AES engine to generate K1 and K2 for AES-CMAC operations."] #[inline(always)] - pub const fn mode(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0504usize) as _) } + pub const fn aes_cmac_init( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x047cusize) as _) } } - #[doc = "Pointer to data structure holding AES key and NONCE vector"] + #[doc = "This register should be set with the amount of remaining bytes until the end of the current AES operation."] #[inline(always)] - pub const fn cnfptr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0508usize) as _) } + pub const fn aes_remaining_bytes(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04bcusize) as _) } } - #[doc = "Input pointer"] + #[doc = "Control the AES engine behavior."] #[inline(always)] - pub const fn inptr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x050cusize) as _) } + pub const fn aes_control(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04c0usize) as _) } } - #[doc = "Output pointer"] + #[doc = "Hardware configuration of the AES engine. Reset value holds the supported features."] #[inline(always)] - pub const fn outptr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0510usize) as _) } + pub const fn aes_hw_flags(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04c8usize) as _) } } - #[doc = "Pointer to data area used for temporary storage"] + #[doc = "This register enables the AES CTR no increment mode in which the counter mode is not incremented between two blocks"] #[inline(always)] - pub const fn scratchptr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0514usize) as _) } + pub const fn aes_ctr_no_increment( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04d8usize) as _) } } - #[doc = "Length of key-stream generated when MODE.LENGTH = Extended."] + #[doc = "Reset the AES engine."] #[inline(always)] - pub const fn maxpacketsize( - self, - ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0518usize) as _) } + pub const fn aes_sw_reset(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04f4usize) as _) } } - #[doc = "Data rate override setting."] + #[doc = "Writing to this address triggers the AES engine to perform a CMAC operation with size 0. The CMAC result can be read from the AES_IV_0 register."] #[inline(always)] - pub const fn rateoverride( + pub const fn aes_cmac_size0_kick( self, - ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x051cusize) as _) } + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0524usize) as _) } } } pub mod regs { - #[doc = "Enable"] + #[doc = "Status register for AES engine activity."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Enable(pub u32); - impl Enable { - #[doc = "Enable or disable CCM"] + pub struct AesBusy(pub u32); + impl AesBusy { + #[doc = "AES engine status."] #[inline(always)] - pub const fn enable(&self) -> super::vals::Enable { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Enable::from_bits(val as u8) + pub const fn status(&self) -> super::vals::Status { + let val = (self.0 >> 0usize) & 0x01; + super::vals::Status::from_bits(val as u8) } - #[doc = "Enable or disable CCM"] + #[doc = "AES engine status."] #[inline(always)] - pub fn set_enable(&mut self, val: super::vals::Enable) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); + pub fn set_status(&mut self, val: super::vals::Status) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); } } - impl Default for Enable { + impl Default for AesBusy { #[inline(always)] - fn default() -> Enable { - Enable(0) + fn default() -> AesBusy { + AesBusy(0) } } - #[doc = "Disable interrupt"] + #[doc = "Writing to this address triggers the AES engine to generate K1 and K2 for AES-CMAC operations."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Inten(pub u32); - impl Inten { - #[doc = "Write '1' to disable interrupt for ENDKSGEN event"] + pub struct AesCmacInit(pub u32); + impl AesCmacInit { + #[doc = "Generate K1 and K2 for the AES-CMAC operations."] #[inline(always)] - pub const fn endksgen(&self) -> bool { + pub const fn enable(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for ENDKSGEN event"] + #[doc = "Generate K1 and K2 for the AES-CMAC operations."] #[inline(always)] - pub fn set_endksgen(&mut self, val: bool) { + pub fn set_enable(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - #[doc = "Write '1' to disable interrupt for ENDCRYPT event"] + } + impl Default for AesCmacInit { #[inline(always)] - pub const fn endcrypt(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 + fn default() -> AesCmacInit { + AesCmacInit(0) } - #[doc = "Write '1' to disable interrupt for ENDCRYPT event"] + } + #[doc = "Writing to this address triggers the AES engine to perform a CMAC operation with size 0. The CMAC result can be read from the AES_IV_0 register."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct AesCmacSize0Kick(pub u32); + impl AesCmacSize0Kick { + #[doc = "Force AES CMAC operation with size 0."] #[inline(always)] - pub fn set_endcrypt(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Write '1' to disable interrupt for ERROR event"] - #[inline(always)] - pub const fn error(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; + pub const fn enable(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for ERROR event"] + #[doc = "Force AES CMAC operation with size 0."] #[inline(always)] - pub fn set_error(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + pub fn set_enable(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } } - impl Default for Inten { + impl Default for AesCmacSize0Kick { #[inline(always)] - fn default() -> Inten { - Inten(0) + fn default() -> AesCmacSize0Kick { + AesCmacSize0Kick(0) } } - #[doc = "Length of key-stream generated when MODE.LENGTH = Extended."] + #[doc = "Control the AES engine behavior."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Maxpacketsize(pub u32); - impl Maxpacketsize { - #[doc = "Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted."] + pub struct AesControl(pub u32); + impl AesControl { + #[doc = "Set AES encrypt or decrypt mode in non-tunneling operations."] #[inline(always)] - pub const fn maxpacketsize(&self) -> u8 { - let val = (self.0 >> 0usize) & 0xff; - val as u8 + pub const fn dec_key0(&self) -> super::vals::DecKey0 { + let val = (self.0 >> 0usize) & 0x01; + super::vals::DecKey0::from_bits(val as u8) } - #[doc = "Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted."] + #[doc = "Set AES encrypt or decrypt mode in non-tunneling operations."] #[inline(always)] - pub fn set_maxpacketsize(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); + pub fn set_dec_key0(&mut self, val: super::vals::DecKey0) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); + } + #[doc = "Set the AES mode."] + #[inline(always)] + pub const fn mode_key0(&self) -> super::vals::ModeKey0 { + let val = (self.0 >> 2usize) & 0x07; + super::vals::ModeKey0::from_bits(val as u8) + } + #[doc = "Set the AES mode."] + #[inline(always)] + pub fn set_mode_key0(&mut self, val: super::vals::ModeKey0) { + self.0 = (self.0 & !(0x07 << 2usize)) | (((val.to_bits() as u32) & 0x07) << 2usize); + } + #[doc = "Set the AES key length."] + #[inline(always)] + pub const fn nk_key0(&self) -> super::vals::NkKey0 { + let val = (self.0 >> 12usize) & 0x03; + super::vals::NkKey0::from_bits(val as u8) + } + #[doc = "Set the AES key length."] + #[inline(always)] + pub fn set_nk_key0(&mut self, val: super::vals::NkKey0) { + self.0 = + (self.0 & !(0x03 << 12usize)) | (((val.to_bits() as u32) & 0x03) << 12usize); + } + #[doc = "This field determines the value that is written to AES_KEY_0, when AES_SK is kicked."] + #[inline(always)] + pub const fn aes_xor_cryptokey(&self) -> bool { + let val = (self.0 >> 29usize) & 0x01; + val != 0 + } + #[doc = "This field determines the value that is written to AES_KEY_0, when AES_SK is kicked."] + #[inline(always)] + pub fn set_aes_xor_cryptokey(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize); + } + #[doc = "Using direct access and not the DIN-DOUT DMA interface"] + #[inline(always)] + pub const fn direct_access(&self) -> bool { + let val = (self.0 >> 31usize) & 0x01; + val != 0 + } + #[doc = "Using direct access and not the DIN-DOUT DMA interface"] + #[inline(always)] + pub fn set_direct_access(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); } } - impl Default for Maxpacketsize { + impl Default for AesControl { #[inline(always)] - fn default() -> Maxpacketsize { - Maxpacketsize(0) + fn default() -> AesControl { + AesControl(0) } } - #[doc = "MIC check result"] + #[doc = "This register enables the AES CTR no increment mode in which the counter mode is not incremented between two blocks"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Micstatus(pub u32); - impl Micstatus { - #[doc = "The result of the MIC check performed during the previous decryption operation"] + pub struct AesCtrNoIncrement(pub u32); + impl AesCtrNoIncrement { + #[doc = "This field enables the AES CTR no increment mode in which the counter mode is not incremented between two blocks"] #[inline(always)] - pub const fn micstatus(&self) -> super::vals::Micstatus { + pub const fn enable(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; - super::vals::Micstatus::from_bits(val as u8) + val != 0 } - #[doc = "The result of the MIC check performed during the previous decryption operation"] + #[doc = "This field enables the AES CTR no increment mode in which the counter mode is not incremented between two blocks"] #[inline(always)] - pub fn set_micstatus(&mut self, val: super::vals::Micstatus) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); + pub fn set_enable(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } } - impl Default for Micstatus { + impl Default for AesCtrNoIncrement { #[inline(always)] - fn default() -> Micstatus { - Micstatus(0) + fn default() -> AesCtrNoIncrement { + AesCtrNoIncrement(0) } } - #[doc = "Operation mode"] + #[doc = "Hardware configuration of the AES engine. Reset value holds the supported features."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Mode(pub u32); - impl Mode { - #[doc = "The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered."] + pub struct AesHwFlags(pub u32); + impl AesHwFlags { + #[doc = "If this flag is set, the engine support 192 bits and 256 bits key size."] #[inline(always)] - pub const fn mode(&self) -> super::vals::Mode { + pub const fn support_256_192_key(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; - super::vals::Mode::from_bits(val as u8) + val != 0 } - #[doc = "The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered."] + #[doc = "If this flag is set, the engine support 192 bits and 256 bits key size."] #[inline(always)] - pub fn set_mode(&mut self, val: super::vals::Mode) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); + pub fn set_support_256_192_key(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - #[doc = "Radio data rate that the CCM shall run synchronous with"] + #[doc = "If this flag is set, the engine support AES_LARGE_RKEK."] #[inline(always)] - pub const fn datarate(&self) -> super::vals::Datarate { - let val = (self.0 >> 16usize) & 0x03; - super::vals::Datarate::from_bits(val as u8) + pub const fn aes_large_rkek(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 } - #[doc = "Radio data rate that the CCM shall run synchronous with"] + #[doc = "If this flag is set, the engine support AES_LARGE_RKEK."] #[inline(always)] - pub fn set_datarate(&mut self, val: super::vals::Datarate) { - self.0 = - (self.0 & !(0x03 << 16usize)) | (((val.to_bits() as u32) & 0x03) << 16usize); + pub fn set_aes_large_rkek(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } - #[doc = "Packet length configuration"] + #[doc = "If this flag is set, the engine support DPA countermeasures."] #[inline(always)] - pub const fn length(&self) -> super::vals::Length { - let val = (self.0 >> 24usize) & 0x01; - super::vals::Length::from_bits(val as u8) + pub const fn dpa_cntrmsr_exist(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 } - #[doc = "Packet length configuration"] + #[doc = "If this flag is set, the engine support DPA countermeasures."] #[inline(always)] - pub fn set_length(&mut self, val: super::vals::Length) { - self.0 = - (self.0 & !(0x01 << 24usize)) | (((val.to_bits() as u32) & 0x01) << 24usize); + pub fn set_dpa_cntrmsr_exist(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "If this flag is set, the engine support AES CTR mode."] + #[inline(always)] + pub const fn ctr_exist(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "If this flag is set, the engine support AES CTR mode."] + #[inline(always)] + pub fn set_ctr_exist(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "If this flag is set, the engine only support encrypt operations."] + #[inline(always)] + pub const fn only_encrypt(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "If this flag is set, the engine only support encrypt operations."] + #[inline(always)] + pub fn set_only_encrypt(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "If this flag is set, the engine uses SBOX tables."] + #[inline(always)] + pub const fn use_sbox_table(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "If this flag is set, the engine uses SBOX tables."] + #[inline(always)] + pub fn set_use_sbox_table(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "If this flag is set, the engine uses 5 SBOX where each AES round takes 4 cycles."] + #[inline(always)] + pub const fn use_5_sboxes(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "If this flag is set, the engine uses 5 SBOX where each AES round takes 4 cycles."] + #[inline(always)] + pub fn set_use_5_sboxes(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "If this flag is set, the engine contains the PREV_IV register for faster AES XCBC MAC calculation."] + #[inline(always)] + pub const fn aes_support_prev_iv(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "If this flag is set, the engine contains the PREV_IV register for faster AES XCBC MAC calculation."] + #[inline(always)] + pub fn set_aes_support_prev_iv(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "If this flag is set, the engine support tunneling operations."] + #[inline(always)] + pub const fn aes_tunnel_exist(&self) -> bool { + let val = (self.0 >> 10usize) & 0x01; + val != 0 + } + #[doc = "If this flag is set, the engine support tunneling operations."] + #[inline(always)] + pub fn set_aes_tunnel_exist(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); + } + #[doc = "If this flag is set, the engine support a second register set for tunneling operations."] + #[inline(always)] + pub const fn second_regs_set_exist(&self) -> bool { + let val = (self.0 >> 11usize) & 0x01; + val != 0 + } + #[doc = "If this flag is set, the engine support a second register set for tunneling operations."] + #[inline(always)] + pub fn set_second_regs_set_exist(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); + } + #[doc = "If this flag is set, the engine support DFA countermeasures."] + #[inline(always)] + pub const fn dfa_cntrmsr_exist(&self) -> bool { + let val = (self.0 >> 12usize) & 0x01; + val != 0 + } + #[doc = "If this flag is set, the engine support DFA countermeasures."] + #[inline(always)] + pub fn set_dfa_cntrmsr_exist(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); } } - impl Default for Mode { + impl Default for AesHwFlags { #[inline(always)] - fn default() -> Mode { - Mode(0) + fn default() -> AesHwFlags { + AesHwFlags(0) } } - #[doc = "Data rate override setting."] + #[doc = "Writing to this address trigger sampling of the HW key to the AES_KEY_0 register"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Rateoverride(pub u32); - impl Rateoverride { - #[doc = "Data rate override setting."] + pub struct AesSk(pub u32); + impl AesSk { + #[doc = "Sample HW key to AES_KEY_0 registers."] #[inline(always)] - pub const fn rateoverride(&self) -> super::vals::Rateoverride { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Rateoverride::from_bits(val as u8) + pub const fn aes_sk(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 } - #[doc = "Data rate override setting."] + #[doc = "Sample HW key to AES_KEY_0 registers."] #[inline(always)] - pub fn set_rateoverride(&mut self, val: super::vals::Rateoverride) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); + pub fn set_aes_sk(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } } - impl Default for Rateoverride { + impl Default for AesSk { #[inline(always)] - fn default() -> Rateoverride { - Rateoverride(0) + fn default() -> AesSk { + AesSk(0) } } - #[doc = "Shortcut register"] + #[doc = "Reset the AES engine."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Shorts(pub u32); - impl Shorts { - #[doc = "Shortcut between ENDKSGEN event and CRYPT task"] + pub struct AesSwReset(pub u32); + impl AesSwReset { + #[doc = "Writing any value to this address resets the AES engine. The reset takes 4 CPU clock cycles to complete."] #[inline(always)] - pub const fn endksgen_crypt(&self) -> bool { + pub const fn reset(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Shortcut between ENDKSGEN event and CRYPT task"] + #[doc = "Writing any value to this address resets the AES engine. The reset takes 4 CPU clock cycles to complete."] #[inline(always)] - pub fn set_endksgen_crypt(&mut self, val: bool) { + pub fn set_reset(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } } - impl Default for Shorts { + impl Default for AesSwReset { #[inline(always)] - fn default() -> Shorts { - Shorts(0) + fn default() -> AesSwReset { + AesSwReset(0) } } } pub mod vals { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub enum Datarate { - #[doc = "1 Mbps"] - _1MBIT = 0x0, - #[doc = "2 Mbps"] - _2MBIT = 0x01, - #[doc = "125 Kbps"] - _125KBPS = 0x02, - #[doc = "500 Kbps"] - _500KBPS = 0x03, + pub enum DecKey0 { + #[doc = "Perform AES encryption"] + ENCRYPT = 0x0, + #[doc = "Perform AES decryption"] + DECRYPT = 0x01, } - impl Datarate { + impl DecKey0 { #[inline(always)] - pub const fn from_bits(val: u8) -> Datarate { - unsafe { core::mem::transmute(val & 0x03) } + pub const fn from_bits(val: u8) -> DecKey0 { + unsafe { core::mem::transmute(val & 0x01) } } #[inline(always)] pub const fn to_bits(self) -> u8 { unsafe { core::mem::transmute(self) } } } - impl From for Datarate { + impl From for DecKey0 { #[inline(always)] - fn from(val: u8) -> Datarate { - Datarate::from_bits(val) + fn from(val: u8) -> DecKey0 { + DecKey0::from_bits(val) } } - impl From for u8 { + impl From for u8 { #[inline(always)] - fn from(val: Datarate) -> u8 { - Datarate::to_bits(val) + fn from(val: DecKey0) -> u8 { + DecKey0::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub enum Enable { - #[doc = "Disable"] - DISABLED = 0x0, - _RESERVED_1 = 0x01, - #[doc = "Enable"] - ENABLED = 0x02, - _RESERVED_3 = 0x03, + pub enum ModeKey0 { + #[doc = "Electronic codebook mode"] + ECB = 0x0, + #[doc = "Cipher block chaining mode"] + CBC = 0x01, + #[doc = "Counter mode"] + CTR = 0x02, + #[doc = "Cipher Block Chaining Message Authentication Code"] + CBC_MAC = 0x03, + _RESERVED_4 = 0x04, + _RESERVED_5 = 0x05, + _RESERVED_6 = 0x06, + #[doc = "Cipher-based Message Authentication Code"] + CMAC = 0x07, } - impl Enable { + impl ModeKey0 { #[inline(always)] - pub const fn from_bits(val: u8) -> Enable { - unsafe { core::mem::transmute(val & 0x03) } + pub const fn from_bits(val: u8) -> ModeKey0 { + unsafe { core::mem::transmute(val & 0x07) } } #[inline(always)] pub const fn to_bits(self) -> u8 { unsafe { core::mem::transmute(self) } } } - impl From for Enable { + impl From for ModeKey0 { #[inline(always)] - fn from(val: u8) -> Enable { - Enable::from_bits(val) + fn from(val: u8) -> ModeKey0 { + ModeKey0::from_bits(val) } } - impl From for u8 { + impl From for u8 { #[inline(always)] - fn from(val: Enable) -> u8 { - Enable::to_bits(val) + fn from(val: ModeKey0) -> u8 { + ModeKey0::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub enum Length { - #[doc = "Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packet payloads up to 27 bytes will be generated."] - DEFAULT = 0x0, - #[doc = "Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packet payloads up to MAXPACKETSIZE bytes will be generated."] - EXTENDED = 0x01, + pub enum NkKey0 { + #[doc = "128 bits key length"] + _128BITS = 0x0, + _RESERVED_1 = 0x01, + _RESERVED_2 = 0x02, + _RESERVED_3 = 0x03, } - impl Length { + impl NkKey0 { #[inline(always)] - pub const fn from_bits(val: u8) -> Length { - unsafe { core::mem::transmute(val & 0x01) } + pub const fn from_bits(val: u8) -> NkKey0 { + unsafe { core::mem::transmute(val & 0x03) } } #[inline(always)] pub const fn to_bits(self) -> u8 { unsafe { core::mem::transmute(self) } } } - impl From for Length { + impl From for NkKey0 { #[inline(always)] - fn from(val: u8) -> Length { - Length::from_bits(val) + fn from(val: u8) -> NkKey0 { + NkKey0::from_bits(val) } } - impl From for u8 { + impl From for u8 { #[inline(always)] - fn from(val: Length) -> u8 { - Length::to_bits(val) + fn from(val: NkKey0) -> u8 { + NkKey0::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub enum Micstatus { - #[doc = "MIC check failed"] - CHECK_FAILED = 0x0, - #[doc = "MIC check passed"] - CHECK_PASSED = 0x01, + pub enum Status { + #[doc = "AES engine is idle"] + IDLE = 0x0, + #[doc = "AES engine is busy"] + BUSY = 0x01, } - impl Micstatus { + impl Status { #[inline(always)] - pub const fn from_bits(val: u8) -> Micstatus { + pub const fn from_bits(val: u8) -> Status { unsafe { core::mem::transmute(val & 0x01) } } #[inline(always)] @@ -1425,93 +1475,29 @@ pub mod ccm { unsafe { core::mem::transmute(self) } } } - impl From for Micstatus { + impl From for Status { #[inline(always)] - fn from(val: u8) -> Micstatus { - Micstatus::from_bits(val) + fn from(val: u8) -> Status { + Status::from_bits(val) } } - impl From for u8 { + impl From for u8 { #[inline(always)] - fn from(val: Micstatus) -> u8 { - Micstatus::to_bits(val) - } - } - #[repr(u8)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub enum Mode { - #[doc = "AES CCM packet encryption mode"] - ENCRYPTION = 0x0, - #[doc = "AES CCM packet decryption mode"] - DECRYPTION = 0x01, - } - impl Mode { - #[inline(always)] - pub const fn from_bits(val: u8) -> Mode { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } - } - impl From for Mode { - #[inline(always)] - fn from(val: u8) -> Mode { - Mode::from_bits(val) - } - } - impl From for u8 { - #[inline(always)] - fn from(val: Mode) -> u8 { - Mode::to_bits(val) - } - } - #[repr(u8)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub enum Rateoverride { - #[doc = "1 Mbps"] - _1MBIT = 0x0, - #[doc = "2 Mbps"] - _2MBIT = 0x01, - #[doc = "125 Kbps"] - _125KBPS = 0x02, - #[doc = "500 Kbps"] - _500KBPS = 0x03, - } - impl Rateoverride { - #[inline(always)] - pub const fn from_bits(val: u8) -> Rateoverride { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } - } - impl From for Rateoverride { - #[inline(always)] - fn from(val: u8) -> Rateoverride { - Rateoverride::from_bits(val) - } - } - impl From for u8 { - #[inline(always)] - fn from(val: Rateoverride) -> u8 { - Rateoverride::to_bits(val) + fn from(val: Status) -> u8 { + Status::to_bits(val) } } } } -pub mod clock { - #[doc = "Clock control"] +pub mod cc_chacha { + #[doc = "CRYPTOCELL CHACHA engine"] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Clock { + pub struct CcChacha { ptr: *mut u8, } - unsafe impl Send for Clock {} - unsafe impl Sync for Clock {} - impl Clock { + unsafe impl Send for CcChacha {} + unsafe impl Sync for CcChacha {} + impl CcChacha { #[inline(always)] pub const unsafe fn from_ptr(ptr: *mut ()) -> Self { Self { ptr: ptr as _ } @@ -1520,526 +1506,490 @@ pub mod clock { pub const fn as_ptr(&self) -> *mut () { self.ptr as _ } - #[doc = "Start HFXO crystal oscillator"] - #[inline(always)] - pub const fn tasks_hfclkstart(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } - } - #[doc = "Stop HFXO crystal oscillator"] - #[inline(always)] - pub const fn tasks_hfclkstop(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } - } - #[doc = "Start LFCLK"] - #[inline(always)] - pub const fn tasks_lfclkstart(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } - } - #[doc = "Stop LFCLK"] - #[inline(always)] - pub const fn tasks_lfclkstop(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } - } - #[doc = "Start calibration of LFRC"] - #[inline(always)] - pub const fn tasks_cal(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } - } - #[doc = "Start calibration timer"] - #[inline(always)] - pub const fn tasks_ctstart(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) } - } - #[doc = "Stop calibration timer"] - #[inline(always)] - pub const fn tasks_ctstop(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) } - } - #[doc = "HFXO crystal oscillator started"] - #[inline(always)] - pub const fn events_hfclkstarted(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0100usize) as _) } - } - #[doc = "LFCLK started"] - #[inline(always)] - pub const fn events_lfclkstarted(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0104usize) as _) } - } - #[doc = "Calibration of LFRC completed"] - #[inline(always)] - pub const fn events_done(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x010cusize) as _) } - } - #[doc = "Calibration timer timeout"] - #[inline(always)] - pub const fn events_ctto(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0110usize) as _) } - } - #[doc = "Calibration timer has been started and is ready to process new tasks"] + #[doc = "Control the CHACHA engine behavior."] #[inline(always)] - pub const fn events_ctstarted(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0128usize) as _) } + pub const fn chacha_control( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0380usize) as _) } } - #[doc = "Calibration timer has been stopped and is ready to process new tasks"] + #[doc = "CHACHA engine HW version"] #[inline(always)] - pub const fn events_ctstopped(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x012cusize) as _) } + pub const fn chacha_version(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0384usize) as _) } } - #[doc = "Enable interrupt"] + #[doc = "Description collection: CHACHA key value to use. The initial CHACHA_KEY\\[0\\] register holds the least significant bits \\[31:0\\] of the key value."] #[inline(always)] - pub const fn intenset(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0304usize) as _) } + pub const fn chacha_key(self, n: usize) -> crate::common::Reg { + assert!(n < 8usize); + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0388usize + n * 4usize) as _) } } - #[doc = "Disable interrupt"] + #[doc = "Description collection: CHACHA Initialization Vector (IV) to use. The IV is also known as the nonce."] #[inline(always)] - pub const fn intenclr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0308usize) as _) } + pub const fn chacha_iv(self, n: usize) -> crate::common::Reg { + assert!(n < 2usize); + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x03a8usize + n * 4usize) as _) } } - #[doc = "Status indicating that HFCLKSTART task has been triggered"] + #[doc = "Status register for CHACHA engine activity."] #[inline(always)] - pub const fn hfclkrun(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0408usize) as _) } + pub const fn chacha_busy(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x03b0usize) as _) } } - #[doc = "HFCLK status"] + #[doc = "Hardware configuration of the CHACHA engine. Reset value holds the supported features."] #[inline(always)] - pub const fn hfclkstat(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x040cusize) as _) } + pub const fn chacha_hw_flags( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x03b4usize) as _) } } - #[doc = "Status indicating that LFCLKSTART task has been triggered"] + #[doc = "Store the LSB value of the block counter, in order to support suspend/resume of operation"] #[inline(always)] - pub const fn lfclkrun(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0414usize) as _) } + pub const fn chacha_block_cnt_lsb(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x03b8usize) as _) } } - #[doc = "LFCLK status"] + #[doc = "Store the MSB value of the block counter, in order to support suspend/resume of operation"] #[inline(always)] - pub const fn lfclkstat(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0418usize) as _) } + pub const fn chacha_block_cnt_msb(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x03bcusize) as _) } } - #[doc = "Copy of LFCLKSRC register, set when LFCLKSTART task was triggered"] + #[doc = "Reset the CHACHA engine."] #[inline(always)] - pub const fn lfclksrccopy( + pub const fn chacha_sw_reset( self, - ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x041cusize) as _) } - } - #[doc = "Clock source for the LFCLK"] - #[inline(always)] - pub const fn lfclksrc(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0518usize) as _) } + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x03c0usize) as _) } } - #[doc = "HFXO debounce time. The HFXO is started by triggering the TASKS_HFCLKSTART task."] + #[doc = "Description collection: The auto-generated key to use in Poly1305 MAC calculation. The initial CHACHA_POLY1305_KEY\\[0\\] register holds the least significant bits \\[31:0\\] of the key value."] #[inline(always)] - pub const fn hfxodebounce( + pub const fn chacha_poly1305_key( self, - ) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0528usize) as _) } - } - #[doc = "Calibration timer interval"] - #[inline(always)] - pub const fn ctiv(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0538usize) as _) } + n: usize, + ) -> crate::common::Reg { + assert!(n < 8usize); + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x03c4usize + n * 4usize) as _) } } - #[doc = "Clocking options for the trace port debug interface"] + #[doc = "CHACHA engine data order configuration."] #[inline(always)] - pub const fn traceconfig(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x055cusize) as _) } + pub const fn chacha_endianness( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x03e4usize) as _) } } - #[doc = "LFRC mode configuration"] + #[doc = "Debug register for the CHACHA engine"] #[inline(always)] - pub const fn lfrcmode(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x05b4usize) as _) } + pub const fn chacha_debug(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x03e8usize) as _) } } } pub mod regs { - #[doc = "Calibration timer interval"] + #[doc = "Status register for CHACHA engine activity."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Ctiv(pub u32); - impl Ctiv { - #[doc = "Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds."] + pub struct ChachaBusy(pub u32); + impl ChachaBusy { + #[doc = "CHACHA engine status."] #[inline(always)] - pub const fn ctiv(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x7f; - val as u8 + pub const fn status(&self) -> super::vals::Status { + let val = (self.0 >> 0usize) & 0x01; + super::vals::Status::from_bits(val as u8) } - #[doc = "Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds."] + #[doc = "CHACHA engine status."] #[inline(always)] - pub fn set_ctiv(&mut self, val: u8) { - self.0 = (self.0 & !(0x7f << 0usize)) | (((val as u32) & 0x7f) << 0usize); + pub fn set_status(&mut self, val: super::vals::Status) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); } } - impl Default for Ctiv { + impl Default for ChachaBusy { #[inline(always)] - fn default() -> Ctiv { - Ctiv(0) + fn default() -> ChachaBusy { + ChachaBusy(0) } } - #[doc = "Status indicating that HFCLKSTART task has been triggered"] + #[doc = "Control the CHACHA engine behavior."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Hfclkrun(pub u32); - impl Hfclkrun { - #[doc = "HFCLKSTART task triggered or not"] + pub struct ChachaControl(pub u32); + impl ChachaControl { + #[doc = "Run engine in ChaCha or Salsa mode"] #[inline(always)] - pub const fn status(&self) -> bool { + pub const fn chacha_or_salsa(&self) -> super::vals::ChachaOrSalsa { let val = (self.0 >> 0usize) & 0x01; + super::vals::ChachaOrSalsa::from_bits(val as u8) + } + #[doc = "Run engine in ChaCha or Salsa mode"] + #[inline(always)] + pub fn set_chacha_or_salsa(&mut self, val: super::vals::ChachaOrSalsa) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); + } + #[doc = "Perform initialization for a new message"] + #[inline(always)] + pub const fn init(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; val != 0 } - #[doc = "HFCLKSTART task triggered or not"] + #[doc = "Perform initialization for a new message"] #[inline(always)] - pub fn set_status(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + pub fn set_init(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } - } - impl Default for Hfclkrun { + #[doc = "Generate the key to use in Poly1305 message authentication code calculation."] #[inline(always)] - fn default() -> Hfclkrun { - Hfclkrun(0) + pub const fn gen_key_poly1305(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 } - } - #[doc = "HFCLK status"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Hfclkstat(pub u32); - impl Hfclkstat { - #[doc = "Source of HFCLK"] + #[doc = "Generate the key to use in Poly1305 message authentication code calculation."] #[inline(always)] - pub const fn src(&self) -> super::vals::HfclkstatSrc { - let val = (self.0 >> 0usize) & 0x01; - super::vals::HfclkstatSrc::from_bits(val as u8) + pub fn set_gen_key_poly1305(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); } - #[doc = "Source of HFCLK"] + #[doc = "Key length selection."] #[inline(always)] - pub fn set_src(&mut self, val: super::vals::HfclkstatSrc) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); + pub const fn key_len(&self) -> super::vals::KeyLen { + let val = (self.0 >> 3usize) & 0x01; + super::vals::KeyLen::from_bits(val as u8) } - #[doc = "HFCLK state"] + #[doc = "Key length selection."] #[inline(always)] - pub const fn state(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; + pub fn set_key_len(&mut self, val: super::vals::KeyLen) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val.to_bits() as u32) & 0x01) << 3usize); + } + #[doc = "Set number of permutation rounds, default value is 20."] + #[inline(always)] + pub const fn num_of_rounds(&self) -> super::vals::NumOfRounds { + let val = (self.0 >> 4usize) & 0x03; + super::vals::NumOfRounds::from_bits(val as u8) + } + #[doc = "Set number of permutation rounds, default value is 20."] + #[inline(always)] + pub fn set_num_of_rounds(&mut self, val: super::vals::NumOfRounds) { + self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); + } + #[doc = "Reset block counter for new messages"] + #[inline(always)] + pub const fn reset_block_cnt(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; val != 0 } - #[doc = "HFCLK state"] + #[doc = "Reset block counter for new messages"] #[inline(always)] - pub fn set_state(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + pub fn set_reset_block_cnt(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "Use 96 bits Initialization Vector (IV)"] + #[inline(always)] + pub const fn use_iv_96bit(&self) -> bool { + let val = (self.0 >> 10usize) & 0x01; + val != 0 + } + #[doc = "Use 96 bits Initialization Vector (IV)"] + #[inline(always)] + pub fn set_use_iv_96bit(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); } } - impl Default for Hfclkstat { + impl Default for ChachaControl { #[inline(always)] - fn default() -> Hfclkstat { - Hfclkstat(0) + fn default() -> ChachaControl { + ChachaControl(0) } } - #[doc = "HFXO debounce time. The HFXO is started by triggering the TASKS_HFCLKSTART task."] + #[doc = "Debug register for the CHACHA engine"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Hfxodebounce(pub u32); - impl Hfxodebounce { - #[doc = "HFXO debounce time. Debounce time = HFXODEBOUNCE * 16 us."] + pub struct ChachaDebug(pub u32); + impl ChachaDebug { + #[doc = "Reflects the debug state of the CHACHA FSM."] #[inline(always)] - pub const fn hfxodebounce(&self) -> super::vals::Hfxodebounce { - let val = (self.0 >> 0usize) & 0xff; - super::vals::Hfxodebounce::from_bits(val as u8) + pub const fn fsm_state(&self) -> super::vals::FsmState { + let val = (self.0 >> 0usize) & 0x03; + super::vals::FsmState::from_bits(val as u8) } - #[doc = "HFXO debounce time. Debounce time = HFXODEBOUNCE * 16 us."] + #[doc = "Reflects the debug state of the CHACHA FSM."] #[inline(always)] - pub fn set_hfxodebounce(&mut self, val: super::vals::Hfxodebounce) { - self.0 = (self.0 & !(0xff << 0usize)) | (((val.to_bits() as u32) & 0xff) << 0usize); + pub fn set_fsm_state(&mut self, val: super::vals::FsmState) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); } } - impl Default for Hfxodebounce { + impl Default for ChachaDebug { #[inline(always)] - fn default() -> Hfxodebounce { - Hfxodebounce(0) + fn default() -> ChachaDebug { + ChachaDebug(0) } } - #[doc = "Disable interrupt"] + #[doc = "CHACHA engine data order configuration."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Inten(pub u32); - impl Inten { - #[doc = "Write '1' to disable interrupt for HFCLKSTARTED event"] + pub struct ChachaEndianness(pub u32); + impl ChachaEndianness { + #[doc = "Change the word order of the input data."] #[inline(always)] - pub const fn hfclkstarted(&self) -> bool { + pub const fn chacha_din_word_order(&self) -> super::vals::ChachaDinWordOrder { let val = (self.0 >> 0usize) & 0x01; - val != 0 + super::vals::ChachaDinWordOrder::from_bits(val as u8) } - #[doc = "Write '1' to disable interrupt for HFCLKSTARTED event"] + #[doc = "Change the word order of the input data."] #[inline(always)] - pub fn set_hfclkstarted(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + pub fn set_chacha_din_word_order(&mut self, val: super::vals::ChachaDinWordOrder) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); } - #[doc = "Write '1' to disable interrupt for LFCLKSTARTED event"] + #[doc = "Change the byte order of the input data."] #[inline(always)] - pub const fn lfclkstarted(&self) -> bool { + pub const fn chacha_din_byte_order(&self) -> super::vals::ChachaDinByteOrder { let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Write '1' to disable interrupt for LFCLKSTARTED event"] - #[inline(always)] - pub fn set_lfclkstarted(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Write '1' to disable interrupt for DONE event"] - #[inline(always)] - pub const fn done(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 + super::vals::ChachaDinByteOrder::from_bits(val as u8) } - #[doc = "Write '1' to disable interrupt for DONE event"] + #[doc = "Change the byte order of the input data."] #[inline(always)] - pub fn set_done(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + pub fn set_chacha_din_byte_order(&mut self, val: super::vals::ChachaDinByteOrder) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val.to_bits() as u32) & 0x01) << 1usize); } - #[doc = "Write '1' to disable interrupt for CTTO event"] + #[doc = "Change the quarter of a matrix order in the engine."] #[inline(always)] - pub const fn ctto(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 + pub const fn chacha_core_matrix_lbe_order( + &self, + ) -> super::vals::ChachaCoreMatrixLbeOrder { + let val = (self.0 >> 2usize) & 0x01; + super::vals::ChachaCoreMatrixLbeOrder::from_bits(val as u8) } - #[doc = "Write '1' to disable interrupt for CTTO event"] + #[doc = "Change the quarter of a matrix order in the engine."] #[inline(always)] - pub fn set_ctto(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + pub fn set_chacha_core_matrix_lbe_order( + &mut self, + val: super::vals::ChachaCoreMatrixLbeOrder, + ) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val.to_bits() as u32) & 0x01) << 2usize); } - #[doc = "Write '1' to disable interrupt for CTSTARTED event"] + #[doc = "Change the word order of the output data."] #[inline(always)] - pub const fn ctstarted(&self) -> bool { - let val = (self.0 >> 10usize) & 0x01; - val != 0 + pub const fn chacha_dout_word_order(&self) -> super::vals::ChachaDoutWordOrder { + let val = (self.0 >> 3usize) & 0x01; + super::vals::ChachaDoutWordOrder::from_bits(val as u8) } - #[doc = "Write '1' to disable interrupt for CTSTARTED event"] + #[doc = "Change the word order of the output data."] #[inline(always)] - pub fn set_ctstarted(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); + pub fn set_chacha_dout_word_order(&mut self, val: super::vals::ChachaDoutWordOrder) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val.to_bits() as u32) & 0x01) << 3usize); } - #[doc = "Write '1' to disable interrupt for CTSTOPPED event"] + #[doc = "Change the byte order of the output data."] #[inline(always)] - pub const fn ctstopped(&self) -> bool { - let val = (self.0 >> 11usize) & 0x01; - val != 0 + pub const fn chacha_dout_byte_order(&self) -> super::vals::ChachaDoutByteOrder { + let val = (self.0 >> 4usize) & 0x01; + super::vals::ChachaDoutByteOrder::from_bits(val as u8) } - #[doc = "Write '1' to disable interrupt for CTSTOPPED event"] + #[doc = "Change the byte order of the output data."] #[inline(always)] - pub fn set_ctstopped(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); + pub fn set_chacha_dout_byte_order(&mut self, val: super::vals::ChachaDoutByteOrder) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val.to_bits() as u32) & 0x01) << 4usize); } } - impl Default for Inten { + impl Default for ChachaEndianness { #[inline(always)] - fn default() -> Inten { - Inten(0) + fn default() -> ChachaEndianness { + ChachaEndianness(0) } } - #[doc = "Status indicating that LFCLKSTART task has been triggered"] + #[doc = "Hardware configuration of the CHACHA engine. Reset value holds the supported features."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Lfclkrun(pub u32); - impl Lfclkrun { - #[doc = "LFCLKSTART task triggered or not"] + pub struct ChachaHwFlags(pub u32); + impl ChachaHwFlags { + #[doc = "If this flag is set, the engine include ChaCha support"] #[inline(always)] - pub const fn status(&self) -> bool { + pub const fn chacha_exists(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "LFCLKSTART task triggered or not"] + #[doc = "If this flag is set, the engine include ChaCha support"] #[inline(always)] - pub fn set_status(&mut self, val: bool) { + pub fn set_chacha_exists(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - } - impl Default for Lfclkrun { - #[inline(always)] - fn default() -> Lfclkrun { - Lfclkrun(0) - } - } - #[doc = "Clock source for the LFCLK"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Lfclksrc(pub u32); - impl Lfclksrc { - #[doc = "Clock source"] - #[inline(always)] - pub const fn src(&self) -> super::vals::Lfclksrc { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Lfclksrc::from_bits(val as u8) - } - #[doc = "Clock source"] - #[inline(always)] - pub fn set_src(&mut self, val: super::vals::Lfclksrc) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Enable or disable bypass of LFCLK crystal oscillator with external clock source"] + #[doc = "If this flag is set, the engine include Salsa support"] #[inline(always)] - pub const fn bypass(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; + pub const fn salsa_exists(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; val != 0 } - #[doc = "Enable or disable bypass of LFCLK crystal oscillator with external clock source"] + #[doc = "If this flag is set, the engine include Salsa support"] #[inline(always)] - pub fn set_bypass(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + pub fn set_salsa_exists(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } - #[doc = "Enable or disable external source for LFCLK"] + #[doc = "If this flag is set, the next matrix calculated when the current one is written to data output path."] #[inline(always)] - pub const fn external(&self) -> bool { - let val = (self.0 >> 17usize) & 0x01; + pub const fn fast_chacha(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; val != 0 } - #[doc = "Enable or disable external source for LFCLK"] + #[doc = "If this flag is set, the next matrix calculated when the current one is written to data output path."] #[inline(always)] - pub fn set_external(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); + pub fn set_fast_chacha(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); } } - impl Default for Lfclksrc { + impl Default for ChachaHwFlags { #[inline(always)] - fn default() -> Lfclksrc { - Lfclksrc(0) + fn default() -> ChachaHwFlags { + ChachaHwFlags(0) } } - #[doc = "Copy of LFCLKSRC register, set when LFCLKSTART task was triggered"] + #[doc = "Reset the CHACHA engine."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Lfclksrccopy(pub u32); - impl Lfclksrccopy { - #[doc = "Clock source"] + pub struct ChachaSwReset(pub u32); + impl ChachaSwReset { + #[doc = "Writing any value to this address resets the CHACHA engine. The reset takes 4 CPU clock cycles to complete."] #[inline(always)] - pub const fn src(&self) -> super::vals::Lfclksrc { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Lfclksrc::from_bits(val as u8) + pub const fn reset(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 } - #[doc = "Clock source"] + #[doc = "Writing any value to this address resets the CHACHA engine. The reset takes 4 CPU clock cycles to complete."] #[inline(always)] - pub fn set_src(&mut self, val: super::vals::Lfclksrc) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); + pub fn set_reset(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } } - impl Default for Lfclksrccopy { + impl Default for ChachaSwReset { #[inline(always)] - fn default() -> Lfclksrccopy { - Lfclksrccopy(0) + fn default() -> ChachaSwReset { + ChachaSwReset(0) } } - #[doc = "LFCLK status"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Lfclkstat(pub u32); - impl Lfclkstat { - #[doc = "Source of LFCLK"] + } + pub mod vals { + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum ChachaCoreMatrixLbeOrder { + #[doc = "Use default quarter of matrix order, where quarters are ordered as follows: q0, q1, q2, q3. Each quarter represents a 128-bits section of the matrix."] + DEFAULT = 0x0, + #[doc = "Reverse the order of matrix quarters, where quarters are re-ordered as follows: q3, q2, q1, q0. Each quarter represents a 128-bits section of the matrix."] + REVERSE = 0x01, + } + impl ChachaCoreMatrixLbeOrder { #[inline(always)] - pub const fn src(&self) -> super::vals::Lfclksrc { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Lfclksrc::from_bits(val as u8) + pub const fn from_bits(val: u8) -> ChachaCoreMatrixLbeOrder { + unsafe { core::mem::transmute(val & 0x01) } } - #[doc = "Source of LFCLK"] #[inline(always)] - pub fn set_src(&mut self, val: super::vals::Lfclksrc) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } } - #[doc = "LFCLK state"] + } + impl From for ChachaCoreMatrixLbeOrder { #[inline(always)] - pub const fn state(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 + fn from(val: u8) -> ChachaCoreMatrixLbeOrder { + ChachaCoreMatrixLbeOrder::from_bits(val) } - #[doc = "LFCLK state"] + } + impl From for u8 { #[inline(always)] - pub fn set_state(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + fn from(val: ChachaCoreMatrixLbeOrder) -> u8 { + ChachaCoreMatrixLbeOrder::to_bits(val) } } - impl Default for Lfclkstat { + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum ChachaDinByteOrder { + #[doc = "Use default byte order within each input word, where bytes are ordered as follows: B0, B1, B2, B3."] + DEFAULT = 0x0, + #[doc = "Reverse the byte order within each input word, where bytes are re-ordered as follows: B3, B2, B1, B0."] + REVERSE = 0x01, + } + impl ChachaDinByteOrder { #[inline(always)] - fn default() -> Lfclkstat { - Lfclkstat(0) + pub const fn from_bits(val: u8) -> ChachaDinByteOrder { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } } } - #[doc = "LFRC mode configuration"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Lfrcmode(pub u32); - impl Lfrcmode { - #[doc = "Set LFRC mode"] + impl From for ChachaDinByteOrder { #[inline(always)] - pub const fn mode(&self) -> super::vals::Mode { - let val = (self.0 >> 0usize) & 0x01; - super::vals::Mode::from_bits(val as u8) + fn from(val: u8) -> ChachaDinByteOrder { + ChachaDinByteOrder::from_bits(val) } - #[doc = "Set LFRC mode"] + } + impl From for u8 { #[inline(always)] - pub fn set_mode(&mut self, val: super::vals::Mode) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); + fn from(val: ChachaDinByteOrder) -> u8 { + ChachaDinByteOrder::to_bits(val) } - #[doc = "Active LFRC mode. This field is read only."] + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum ChachaDinWordOrder { + #[doc = "Use default word order for 128-bits input, where words are ordered as follows: w0, w1, w2, w3."] + DEFAULT = 0x0, + #[doc = "Reverses the word order for 128-bits input, where words are re-ordered as follows: w3, w2, w1, w0."] + REVERSE = 0x01, + } + impl ChachaDinWordOrder { #[inline(always)] - pub const fn status(&self) -> super::vals::LfrcmodeStatus { - let val = (self.0 >> 16usize) & 0x01; - super::vals::LfrcmodeStatus::from_bits(val as u8) + pub const fn from_bits(val: u8) -> ChachaDinWordOrder { + unsafe { core::mem::transmute(val & 0x01) } } - #[doc = "Active LFRC mode. This field is read only."] #[inline(always)] - pub fn set_status(&mut self, val: super::vals::LfrcmodeStatus) { - self.0 = - (self.0 & !(0x01 << 16usize)) | (((val.to_bits() as u32) & 0x01) << 16usize); + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } } } - impl Default for Lfrcmode { + impl From for ChachaDinWordOrder { #[inline(always)] - fn default() -> Lfrcmode { - Lfrcmode(0) + fn from(val: u8) -> ChachaDinWordOrder { + ChachaDinWordOrder::from_bits(val) } } - #[doc = "Clocking options for the trace port debug interface"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Traceconfig(pub u32); - impl Traceconfig { - #[doc = "Speed of trace port clock. Note that the TRACECLK pin will output this clock divided by two."] + impl From for u8 { #[inline(always)] - pub const fn traceportspeed(&self) -> super::vals::Traceportspeed { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Traceportspeed::from_bits(val as u8) + fn from(val: ChachaDinWordOrder) -> u8 { + ChachaDinWordOrder::to_bits(val) } - #[doc = "Speed of trace port clock. Note that the TRACECLK pin will output this clock divided by two."] + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum ChachaDoutByteOrder { + #[doc = "Use default byte order within each output word, where bytes are ordered as follows: B0, B1, B2, B3."] + DEFAULT = 0x0, + #[doc = "Reverse the byte order within each output word, where bytes are re-ordered as follows: B3, B2, B1, B0."] + REVERSE = 0x01, + } + impl ChachaDoutByteOrder { #[inline(always)] - pub fn set_traceportspeed(&mut self, val: super::vals::Traceportspeed) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); + pub const fn from_bits(val: u8) -> ChachaDoutByteOrder { + unsafe { core::mem::transmute(val & 0x01) } } - #[doc = "Pin multiplexing of trace signals. See pin assignment chapter for more details."] #[inline(always)] - pub const fn tracemux(&self) -> super::vals::Tracemux { - let val = (self.0 >> 16usize) & 0x03; - super::vals::Tracemux::from_bits(val as u8) + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } } - #[doc = "Pin multiplexing of trace signals. See pin assignment chapter for more details."] + } + impl From for ChachaDoutByteOrder { #[inline(always)] - pub fn set_tracemux(&mut self, val: super::vals::Tracemux) { - self.0 = - (self.0 & !(0x03 << 16usize)) | (((val.to_bits() as u32) & 0x03) << 16usize); + fn from(val: u8) -> ChachaDoutByteOrder { + ChachaDoutByteOrder::from_bits(val) } } - impl Default for Traceconfig { + impl From for u8 { #[inline(always)] - fn default() -> Traceconfig { - Traceconfig(0) + fn from(val: ChachaDoutByteOrder) -> u8 { + ChachaDoutByteOrder::to_bits(val) } } - } - pub mod vals { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub enum HfclkstatSrc { - #[doc = "64 MHz internal oscillator (HFINT)"] - RC = 0x0, - #[doc = "64 MHz crystal oscillator (HFXO)"] - XTAL = 0x01, + pub enum ChachaDoutWordOrder { + #[doc = "Uses default word order for 128-bits output, where words are ordered as follows: w0, w1, w2, w3."] + DEFAULT = 0x0, + #[doc = "Reverse the word order for 128-bits output, where words are re-ordered as follows: w3, w2, w1, w0."] + REVERSE = 0x01, } - impl HfclkstatSrc { + impl ChachaDoutWordOrder { #[inline(always)] - pub const fn from_bits(val: u8) -> HfclkstatSrc { + pub const fn from_bits(val: u8) -> ChachaDoutWordOrder { unsafe { core::mem::transmute(val & 0x01) } } #[inline(always)] @@ -2047,121 +1997,93 @@ pub mod clock { unsafe { core::mem::transmute(self) } } } - impl From for HfclkstatSrc { + impl From for ChachaDoutWordOrder { #[inline(always)] - fn from(val: u8) -> HfclkstatSrc { - HfclkstatSrc::from_bits(val) + fn from(val: u8) -> ChachaDoutWordOrder { + ChachaDoutWordOrder::from_bits(val) } } - impl From for u8 { + impl From for u8 { #[inline(always)] - fn from(val: HfclkstatSrc) -> u8 { - HfclkstatSrc::to_bits(val) + fn from(val: ChachaDoutWordOrder) -> u8 { + ChachaDoutWordOrder::to_bits(val) } } - #[repr(transparent)] + #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Hfxodebounce(pub u8); - impl Hfxodebounce { - #[doc = "256 us debounce time. Recommended for TSX-3225, FA-20H and FA-128 crystals."] - pub const DB256US: Self = Self(0x10); - #[doc = "1024 us debounce time. Recommended for NX1612AA and NX1210AB crystals."] - pub const DB1024US: Self = Self(0x40); + pub enum ChachaOrSalsa { + #[doc = "Run engine in ChaCha mode"] + CHA_CHA = 0x0, + #[doc = "Run engine in Salsa mode"] + SALSA = 0x01, } - impl Hfxodebounce { - pub const fn from_bits(val: u8) -> Hfxodebounce { - Self(val & 0xff) - } - pub const fn to_bits(self) -> u8 { - self.0 - } - } - impl From for Hfxodebounce { - #[inline(always)] - fn from(val: u8) -> Hfxodebounce { - Hfxodebounce::from_bits(val) - } - } - impl From for u8 { - #[inline(always)] - fn from(val: Hfxodebounce) -> u8 { - Hfxodebounce::to_bits(val) - } - } - #[repr(u8)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub enum Lfclksrc { - #[doc = "32.768 kHz RC oscillator (LFRC)"] - RC = 0x0, - #[doc = "32.768 kHz crystal oscillator (LFXO)"] - XTAL = 0x01, - #[doc = "32.768 kHz synthesized from HFCLK (LFSYNT)"] - SYNTH = 0x02, - _RESERVED_3 = 0x03, - } - impl Lfclksrc { + impl ChachaOrSalsa { #[inline(always)] - pub const fn from_bits(val: u8) -> Lfclksrc { - unsafe { core::mem::transmute(val & 0x03) } + pub const fn from_bits(val: u8) -> ChachaOrSalsa { + unsafe { core::mem::transmute(val & 0x01) } } #[inline(always)] pub const fn to_bits(self) -> u8 { unsafe { core::mem::transmute(self) } } } - impl From for Lfclksrc { + impl From for ChachaOrSalsa { #[inline(always)] - fn from(val: u8) -> Lfclksrc { - Lfclksrc::from_bits(val) + fn from(val: u8) -> ChachaOrSalsa { + ChachaOrSalsa::from_bits(val) } } - impl From for u8 { + impl From for u8 { #[inline(always)] - fn from(val: Lfclksrc) -> u8 { - Lfclksrc::to_bits(val) + fn from(val: ChachaOrSalsa) -> u8 { + ChachaOrSalsa::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub enum LfrcmodeStatus { - #[doc = "Normal mode"] - NORMAL = 0x0, - #[doc = "Ultra-low power mode (ULP)"] - ULP = 0x01, - } - impl LfrcmodeStatus { - #[inline(always)] - pub const fn from_bits(val: u8) -> LfrcmodeStatus { - unsafe { core::mem::transmute(val & 0x01) } + pub enum FsmState { + #[doc = "CHACHA FSM is in idle state"] + IDLE_STATE = 0x0, + #[doc = "CHACHA FSM is in init state"] + INIT_STATE = 0x01, + #[doc = "CHACHA FSM is in rounds state"] + ROUNDS_STATE = 0x02, + #[doc = "CHACHA FSM is in final state"] + FINAL_STATE = 0x03, + } + impl FsmState { + #[inline(always)] + pub const fn from_bits(val: u8) -> FsmState { + unsafe { core::mem::transmute(val & 0x03) } } #[inline(always)] pub const fn to_bits(self) -> u8 { unsafe { core::mem::transmute(self) } } } - impl From for LfrcmodeStatus { + impl From for FsmState { #[inline(always)] - fn from(val: u8) -> LfrcmodeStatus { - LfrcmodeStatus::from_bits(val) + fn from(val: u8) -> FsmState { + FsmState::from_bits(val) } } - impl From for u8 { + impl From for u8 { #[inline(always)] - fn from(val: LfrcmodeStatus) -> u8 { - LfrcmodeStatus::to_bits(val) + fn from(val: FsmState) -> u8 { + FsmState::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub enum Mode { - #[doc = "Normal mode"] - NORMAL = 0x0, - #[doc = "Ultra-low power mode (ULP)"] - ULP = 0x01, + pub enum KeyLen { + #[doc = "Use 256 bits key length"] + _256BITS = 0x0, + #[doc = "Use 128 bits key length"] + _128BITS = 0x01, } - impl Mode { + impl KeyLen { #[inline(always)] - pub const fn from_bits(val: u8) -> Mode { + pub const fn from_bits(val: u8) -> KeyLen { unsafe { core::mem::transmute(val & 0x01) } } #[inline(always)] @@ -2169,32 +2091,32 @@ pub mod clock { unsafe { core::mem::transmute(self) } } } - impl From for Mode { + impl From for KeyLen { #[inline(always)] - fn from(val: u8) -> Mode { - Mode::from_bits(val) + fn from(val: u8) -> KeyLen { + KeyLen::from_bits(val) } } - impl From for u8 { + impl From for u8 { #[inline(always)] - fn from(val: Mode) -> u8 { - Mode::to_bits(val) + fn from(val: KeyLen) -> u8 { + KeyLen::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub enum Tracemux { - #[doc = "No trace signals routed to pins. All pins can be used as regular GPIOs."] - GPIO = 0x0, - #[doc = "SWO trace signal routed to pin. Remaining pins can be used as regular GPIOs."] - SERIAL = 0x01, - #[doc = "All trace signals (TRACECLK and TRACEDATA\\[n\\]) routed to pins."] - PARALLEL = 0x02, + pub enum NumOfRounds { + #[doc = "Use 20 rounds of rotation (default)"] + DEFAULT = 0x0, + #[doc = "Use 12 rounds of rotation"] + _12ROUNDS = 0x01, + #[doc = "Use 8 rounds of rotation"] + _8ROUNDS = 0x02, _RESERVED_3 = 0x03, } - impl Tracemux { + impl NumOfRounds { #[inline(always)] - pub const fn from_bits(val: u8) -> Tracemux { + pub const fn from_bits(val: u8) -> NumOfRounds { unsafe { core::mem::transmute(val & 0x03) } } #[inline(always)] @@ -2202,140 +2124,59 @@ pub mod clock { unsafe { core::mem::transmute(self) } } } - impl From for Tracemux { + impl From for NumOfRounds { #[inline(always)] - fn from(val: u8) -> Tracemux { - Tracemux::from_bits(val) + fn from(val: u8) -> NumOfRounds { + NumOfRounds::from_bits(val) } } - impl From for u8 { + impl From for u8 { #[inline(always)] - fn from(val: Tracemux) -> u8 { - Tracemux::to_bits(val) + fn from(val: NumOfRounds) -> u8 { + NumOfRounds::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub enum Traceportspeed { - #[doc = "32 MHz trace port clock (TRACECLK = 16 MHz)"] - _32MHZ = 0x0, - #[doc = "16 MHz trace port clock (TRACECLK = 8 MHz)"] - _16MHZ = 0x01, - #[doc = "8 MHz trace port clock (TRACECLK = 4 MHz)"] - _8MHZ = 0x02, - #[doc = "4 MHz trace port clock (TRACECLK = 2 MHz)"] - _4MHZ = 0x03, + pub enum Status { + #[doc = "CHACHA engine is idle"] + IDLE = 0x0, + #[doc = "CHACHA engine is busy"] + BUSY = 0x01, } - impl Traceportspeed { + impl Status { #[inline(always)] - pub const fn from_bits(val: u8) -> Traceportspeed { - unsafe { core::mem::transmute(val & 0x03) } + pub const fn from_bits(val: u8) -> Status { + unsafe { core::mem::transmute(val & 0x01) } } #[inline(always)] pub const fn to_bits(self) -> u8 { unsafe { core::mem::transmute(self) } } } - impl From for Traceportspeed { + impl From for Status { #[inline(always)] - fn from(val: u8) -> Traceportspeed { - Traceportspeed::from_bits(val) + fn from(val: u8) -> Status { + Status::from_bits(val) } } - impl From for u8 { + impl From for u8 { #[inline(always)] - fn from(val: Traceportspeed) -> u8 { - Traceportspeed::to_bits(val) - } - } - } -} -pub mod common { - use core::marker::PhantomData; - #[derive(Copy, Clone, PartialEq, Eq)] - pub struct RW; - #[derive(Copy, Clone, PartialEq, Eq)] - pub struct R; - #[derive(Copy, Clone, PartialEq, Eq)] - pub struct W; - mod sealed { - use super::*; - pub trait Access {} - impl Access for R {} - impl Access for W {} - impl Access for RW {} - } - pub trait Access: sealed::Access + Copy {} - impl Access for R {} - impl Access for W {} - impl Access for RW {} - pub trait Read: Access {} - impl Read for RW {} - impl Read for R {} - pub trait Write: Access {} - impl Write for RW {} - impl Write for W {} - #[derive(Copy, Clone, PartialEq, Eq)] - pub struct Reg { - ptr: *mut u8, - phantom: PhantomData<*mut (T, A)>, - } - unsafe impl Send for Reg {} - unsafe impl Sync for Reg {} - impl Reg { - #[allow(clippy::missing_safety_doc)] - #[inline(always)] - pub const unsafe fn from_ptr(ptr: *mut T) -> Self { - Self { - ptr: ptr as _, - phantom: PhantomData, + fn from(val: Status) -> u8 { + Status::to_bits(val) } } - #[inline(always)] - pub const fn as_ptr(&self) -> *mut T { - self.ptr as _ - } - } - impl Reg { - #[inline(always)] - pub fn read(&self) -> T { - unsafe { (self.ptr as *mut T).read_volatile() } - } - } - impl Reg { - #[inline(always)] - pub fn write_value(&self, val: T) { - unsafe { (self.ptr as *mut T).write_volatile(val) } - } - } - impl Reg { - #[inline(always)] - pub fn write(&self, f: impl FnOnce(&mut T) -> R) -> R { - let mut val = Default::default(); - let res = f(&mut val); - self.write_value(val); - res - } - } - impl Reg { - #[inline(always)] - pub fn modify(&self, f: impl FnOnce(&mut T) -> R) -> R { - let mut val = self.read(); - let res = f(&mut val); - self.write_value(val); - res - } } } -pub mod comp { - #[doc = "Comparator"] +pub mod cc_ctl { + #[doc = "CRYPTOCELL CTL interface"] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Comp { + pub struct CcCtl { ptr: *mut u8, } - unsafe impl Send for Comp {} - unsafe impl Sync for Comp {} - impl Comp { + unsafe impl Send for CcCtl {} + unsafe impl Sync for CcCtl {} + impl CcCtl { #[inline(always)] pub const unsafe fn from_ptr(ptr: *mut ()) -> Self { Self { ptr: ptr as _ } @@ -2344,519 +2185,649 @@ pub mod comp { pub const fn as_ptr(&self) -> *mut () { self.ptr as _ } - #[doc = "Start comparator"] - #[inline(always)] - pub const fn tasks_start(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } - } - #[doc = "Stop comparator"] + #[doc = "Defines the cryptographic flow."] #[inline(always)] - pub const fn tasks_stop(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } + pub const fn crypto_ctl(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0900usize) as _) } } - #[doc = "Sample comparator value"] + #[doc = "Status register for cryptographic cores engine activity."] #[inline(always)] - pub const fn tasks_sample(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } + pub const fn crypto_busy(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0910usize) as _) } } - #[doc = "COMP is ready and output is valid"] + #[doc = "Status register for HASH engine activity."] #[inline(always)] - pub const fn events_ready(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0100usize) as _) } + pub const fn hash_busy(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x091cusize) as _) } } - #[doc = "Downward crossing"] + #[doc = "A general-purpose read/write register."] #[inline(always)] - pub const fn events_down(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0104usize) as _) } + pub const fn context_id(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0930usize) as _) } } - #[doc = "Upward crossing"] - #[inline(always)] - pub const fn events_up(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0108usize) as _) } + } + pub mod regs { + #[doc = "A general-purpose read/write register."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct ContextId(pub u32); + impl ContextId { + #[doc = "Context ID"] + #[inline(always)] + pub const fn context_id(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 + } + #[doc = "Context ID"] + #[inline(always)] + pub fn set_context_id(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); + } } - #[doc = "Downward or upward crossing"] - #[inline(always)] - pub const fn events_cross(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x010cusize) as _) } + impl Default for ContextId { + #[inline(always)] + fn default() -> ContextId { + ContextId(0) + } } - #[doc = "Shortcut register"] - #[inline(always)] - pub const fn shorts(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0200usize) as _) } + #[doc = "Status register for cryptographic cores engine activity."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct CryptoBusy(pub u32); + impl CryptoBusy { + #[doc = "Cryptographic core engines status."] + #[inline(always)] + pub const fn status(&self) -> super::vals::CryptoBusyStatus { + let val = (self.0 >> 0usize) & 0x01; + super::vals::CryptoBusyStatus::from_bits(val as u8) + } + #[doc = "Cryptographic core engines status."] + #[inline(always)] + pub fn set_status(&mut self, val: super::vals::CryptoBusyStatus) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); + } } - #[doc = "Enable or disable interrupt"] - #[inline(always)] - pub const fn inten(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0300usize) as _) } + impl Default for CryptoBusy { + #[inline(always)] + fn default() -> CryptoBusy { + CryptoBusy(0) + } } - #[doc = "Enable interrupt"] - #[inline(always)] - pub const fn intenset(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0304usize) as _) } + #[doc = "Defines the cryptographic flow."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct CryptoCtl(pub u32); + impl CryptoCtl { + #[doc = "Configure the cryptographic engine mode."] + #[inline(always)] + pub const fn mode(&self) -> super::vals::Mode { + let val = (self.0 >> 0usize) & 0x1f; + super::vals::Mode::from_bits(val as u8) + } + #[doc = "Configure the cryptographic engine mode."] + #[inline(always)] + pub fn set_mode(&mut self, val: super::vals::Mode) { + self.0 = (self.0 & !(0x1f << 0usize)) | (((val.to_bits() as u32) & 0x1f) << 0usize); + } } - #[doc = "Disable interrupt"] + impl Default for CryptoCtl { + #[inline(always)] + fn default() -> CryptoCtl { + CryptoCtl(0) + } + } + #[doc = "Status register for HASH engine activity."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct HashBusy(pub u32); + impl HashBusy { + #[doc = "Hash engine status."] + #[inline(always)] + pub const fn status(&self) -> super::vals::HashBusyStatus { + let val = (self.0 >> 0usize) & 0x01; + super::vals::HashBusyStatus::from_bits(val as u8) + } + #[doc = "Hash engine status."] + #[inline(always)] + pub fn set_status(&mut self, val: super::vals::HashBusyStatus) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); + } + } + impl Default for HashBusy { + #[inline(always)] + fn default() -> HashBusy { + HashBusy(0) + } + } + } + pub mod vals { + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum CryptoBusyStatus { + #[doc = "Cryptographic core engines are idle"] + IDLE = 0x0, + #[doc = "Cryptographic core engines are busy"] + BUSY = 0x01, + } + impl CryptoBusyStatus { + #[inline(always)] + pub const fn from_bits(val: u8) -> CryptoBusyStatus { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for CryptoBusyStatus { + #[inline(always)] + fn from(val: u8) -> CryptoBusyStatus { + CryptoBusyStatus::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: CryptoBusyStatus) -> u8 { + CryptoBusyStatus::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum HashBusyStatus { + #[doc = "HASH engine is idle"] + IDLE = 0x0, + #[doc = "HASH engine is busy"] + BUSY = 0x01, + } + impl HashBusyStatus { + #[inline(always)] + pub const fn from_bits(val: u8) -> HashBusyStatus { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for HashBusyStatus { + #[inline(always)] + fn from(val: u8) -> HashBusyStatus { + HashBusyStatus::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: HashBusyStatus) -> u8 { + HashBusyStatus::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum Mode { + #[doc = "Bypass cryptographic engine"] + BYPASS = 0x0, + #[doc = "Use AES engine"] + AESACTIVE = 0x01, + #[doc = "Pipe AES engine output to HASH engine input"] + AESTO_HASH_ACTIVE = 0x02, + #[doc = "Process input using both AES and HASH engine in parallell"] + AESAND_HASH_ACTIVE = 0x03, + _RESERVED_4 = 0x04, + _RESERVED_5 = 0x05, + _RESERVED_6 = 0x06, + #[doc = "Use HASH engine"] + HASH_ACTIVE = 0x07, + _RESERVED_8 = 0x08, + #[doc = "Calculate AES MAC and bypass"] + AESMACAND_BYPASS_ACTIVE = 0x09, + #[doc = "Pipe AES engine output to HASH engine input. The resulting digest output is piped to DOUT buffer."] + AESTO_HASH_AND_DOUTACTIVE = 0x0a, + _RESERVED_b = 0x0b, + _RESERVED_c = 0x0c, + _RESERVED_d = 0x0d, + _RESERVED_e = 0x0e, + _RESERVED_f = 0x0f, + #[doc = "Use CHACHA engine"] + CHA_CHA_ACTIVE = 0x10, + _RESERVED_11 = 0x11, + _RESERVED_12 = 0x12, + _RESERVED_13 = 0x13, + _RESERVED_14 = 0x14, + _RESERVED_15 = 0x15, + _RESERVED_16 = 0x16, + _RESERVED_17 = 0x17, + _RESERVED_18 = 0x18, + _RESERVED_19 = 0x19, + _RESERVED_1a = 0x1a, + _RESERVED_1b = 0x1b, + _RESERVED_1c = 0x1c, + _RESERVED_1d = 0x1d, + _RESERVED_1e = 0x1e, + _RESERVED_1f = 0x1f, + } + impl Mode { + #[inline(always)] + pub const fn from_bits(val: u8) -> Mode { + unsafe { core::mem::transmute(val & 0x1f) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for Mode { + #[inline(always)] + fn from(val: u8) -> Mode { + Mode::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: Mode) -> u8 { + Mode::to_bits(val) + } + } + } +} +pub mod cc_din { + #[doc = "CRYPTOCELL Data IN interface"] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct CcDin { + ptr: *mut u8, + } + unsafe impl Send for CcDin {} + unsafe impl Sync for CcDin {} + impl CcDin { #[inline(always)] - pub const fn intenclr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0308usize) as _) } + pub const unsafe fn from_ptr(ptr: *mut ()) -> Self { + Self { ptr: ptr as _ } } - #[doc = "Compare result"] #[inline(always)] - pub const fn result(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0400usize) as _) } + pub const fn as_ptr(&self) -> *mut () { + self.ptr as _ } - #[doc = "COMP enable"] + #[doc = "Used by CPU to write data directly to the DIN buffer, which is then sent to the cryptographic engines for processing."] #[inline(always)] - pub const fn enable(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0500usize) as _) } + pub const fn din_buffer(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0c00usize) as _) } } - #[doc = "Pin select"] + #[doc = "Status register for DIN DMA engine activity when accessing memory."] #[inline(always)] - pub const fn psel(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0504usize) as _) } + pub const fn din_dma_mem_busy( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0c20usize) as _) } } - #[doc = "Reference source select for single-ended mode"] + #[doc = "Data source address in memory."] #[inline(always)] - pub const fn refsel(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0508usize) as _) } + pub const fn src_mem_addr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0c28usize) as _) } } - #[doc = "External reference select"] + #[doc = "The number of bytes to be read from memory. Writing to this register triggers the DMA operation."] #[inline(always)] - pub const fn extrefsel(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x050cusize) as _) } + pub const fn src_mem_size(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0c2cusize) as _) } } - #[doc = "Threshold configuration for hysteresis unit"] + #[doc = "Data source address in RNG SRAM."] #[inline(always)] - pub const fn th(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0530usize) as _) } + pub const fn src_sram_addr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0c30usize) as _) } } - #[doc = "Mode configuration"] + #[doc = "The number of bytes to be read from RNG SRAM. Writing to this register triggers the DMA operation."] #[inline(always)] - pub const fn mode(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0534usize) as _) } + pub const fn src_sram_size(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0c34usize) as _) } } - #[doc = "Comparator hysteresis enable"] + #[doc = "Status register for DIN DMA engine activity when accessing RNG SRAM."] #[inline(always)] - pub const fn hyst(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0538usize) as _) } + pub const fn din_dma_sram_busy( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0c38usize) as _) } + } + #[doc = "Configure the endianness of DIN DMA transactions towards RNG SRAM."] + #[inline(always)] + pub const fn din_dma_sram_endianness( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0c3cusize) as _) } + } + #[doc = "Reset the DIN DMA engine."] + #[inline(always)] + pub const fn din_sw_reset(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0c44usize) as _) } + } + #[doc = "Specifies the number of bytes the CPU will write to the DIN_BUFFER, ensuring the cryptographic engine processes the correct amount of data."] + #[inline(always)] + pub const fn din_cpu_data(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0c48usize) as _) } + } + #[doc = "Indicates that the next CPU write to the DIN_BUFFER is the last in the sequence. This is needed only when the data size is NOT modulo 4 (e.g. HASH padding)."] + #[inline(always)] + pub const fn din_write_align( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0c4cusize) as _) } + } + #[doc = "Register indicating if DIN FIFO is empty and if more data can be accepted."] + #[inline(always)] + pub const fn din_fifo_empty( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0c50usize) as _) } + } + #[doc = "Reset the DIN FIFO, effectively clearing the FIFO for new data."] + #[inline(always)] + pub const fn din_fifo_reset( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0c58usize) as _) } } } pub mod regs { - #[doc = "COMP enable"] + #[doc = "Specifies the number of bytes the CPU will write to the DIN_BUFFER, ensuring the cryptographic engine processes the correct amount of data."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Enable(pub u32); - impl Enable { - #[doc = "Enable or disable COMP"] + pub struct DinCpuData(pub u32); + impl DinCpuData { + #[doc = "When using CPU direct write to the DIN_BUFFER, the size of input data in bytes should be written to this register."] #[inline(always)] - pub const fn enable(&self) -> super::vals::Enable { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Enable::from_bits(val as u8) + pub const fn size(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 } - #[doc = "Enable or disable COMP"] + #[doc = "When using CPU direct write to the DIN_BUFFER, the size of input data in bytes should be written to this register."] #[inline(always)] - pub fn set_enable(&mut self, val: super::vals::Enable) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); + pub fn set_size(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); } } - impl Default for Enable { + impl Default for DinCpuData { #[inline(always)] - fn default() -> Enable { - Enable(0) + fn default() -> DinCpuData { + DinCpuData(0) } } - #[doc = "External reference select"] + #[doc = "Status register for DIN DMA engine activity when accessing memory."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Extrefsel(pub u32); - impl Extrefsel { - #[doc = "External analog reference select"] + pub struct DinDmaMemBusy(pub u32); + impl DinDmaMemBusy { + #[doc = "DIN memory DMA engine status."] #[inline(always)] - pub const fn extrefsel(&self) -> super::vals::Extrefsel { - let val = (self.0 >> 0usize) & 0x07; - super::vals::Extrefsel::from_bits(val as u8) + pub const fn status(&self) -> super::vals::DinDmaMemBusyStatus { + let val = (self.0 >> 0usize) & 0x01; + super::vals::DinDmaMemBusyStatus::from_bits(val as u8) } - #[doc = "External analog reference select"] + #[doc = "DIN memory DMA engine status."] #[inline(always)] - pub fn set_extrefsel(&mut self, val: super::vals::Extrefsel) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); + pub fn set_status(&mut self, val: super::vals::DinDmaMemBusyStatus) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); } } - impl Default for Extrefsel { + impl Default for DinDmaMemBusy { #[inline(always)] - fn default() -> Extrefsel { - Extrefsel(0) + fn default() -> DinDmaMemBusy { + DinDmaMemBusy(0) } } - #[doc = "Comparator hysteresis enable"] + #[doc = "Status register for DIN DMA engine activity when accessing RNG SRAM."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Hyst(pub u32); - impl Hyst { - #[doc = "Comparator hysteresis"] + pub struct DinDmaSramBusy(pub u32); + impl DinDmaSramBusy { + #[doc = "DIN RNG SRAM DMA engine status."] #[inline(always)] - pub const fn hyst(&self) -> super::vals::Hyst { + pub const fn status(&self) -> super::vals::DinDmaSramBusyStatus { let val = (self.0 >> 0usize) & 0x01; - super::vals::Hyst::from_bits(val as u8) + super::vals::DinDmaSramBusyStatus::from_bits(val as u8) } - #[doc = "Comparator hysteresis"] + #[doc = "DIN RNG SRAM DMA engine status."] #[inline(always)] - pub fn set_hyst(&mut self, val: super::vals::Hyst) { + pub fn set_status(&mut self, val: super::vals::DinDmaSramBusyStatus) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); } } - impl Default for Hyst { + impl Default for DinDmaSramBusy { #[inline(always)] - fn default() -> Hyst { - Hyst(0) + fn default() -> DinDmaSramBusy { + DinDmaSramBusy(0) } } - #[doc = "Enable or disable interrupt"] + #[doc = "Configure the endianness of DIN DMA transactions towards RNG SRAM."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Inten(pub u32); - impl Inten { - #[doc = "Enable or disable interrupt for READY event"] + pub struct DinDmaSramEndianness(pub u32); + impl DinDmaSramEndianness { + #[doc = "Endianness of DIN DMA transactions towards RNG SRAM. The default value is little-endian."] #[inline(always)] - pub const fn ready(&self) -> bool { + pub const fn endian(&self) -> super::vals::Endian { let val = (self.0 >> 0usize) & 0x01; - val != 0 + super::vals::Endian::from_bits(val as u8) } - #[doc = "Enable or disable interrupt for READY event"] + #[doc = "Endianness of DIN DMA transactions towards RNG SRAM. The default value is little-endian."] #[inline(always)] - pub fn set_ready(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + pub fn set_endian(&mut self, val: super::vals::Endian) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); } - #[doc = "Enable or disable interrupt for DOWN event"] + } + impl Default for DinDmaSramEndianness { #[inline(always)] - pub const fn down(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 + fn default() -> DinDmaSramEndianness { + DinDmaSramEndianness(0) } - #[doc = "Enable or disable interrupt for DOWN event"] + } + #[doc = "Register indicating if DIN FIFO is empty and if more data can be accepted."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct DinFifoEmpty(pub u32); + impl DinFifoEmpty { + #[doc = "DIN FIFO status"] #[inline(always)] - pub fn set_down(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + pub const fn status(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 } - #[doc = "Enable or disable interrupt for UP event"] + #[doc = "DIN FIFO status"] #[inline(always)] - pub const fn up(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 + pub fn set_status(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - #[doc = "Enable or disable interrupt for UP event"] + } + impl Default for DinFifoEmpty { #[inline(always)] - pub fn set_up(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + fn default() -> DinFifoEmpty { + DinFifoEmpty(0) } - #[doc = "Enable or disable interrupt for CROSS event"] + } + #[doc = "Reset the DIN FIFO, effectively clearing the FIFO for new data."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct DinFifoReset(pub u32); + impl DinFifoReset { + #[doc = "Writing any value to this address resets the DIN FIFO."] #[inline(always)] - pub const fn cross(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; + pub const fn reset(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for CROSS event"] + #[doc = "Writing any value to this address resets the DIN FIFO."] #[inline(always)] - pub fn set_cross(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + pub fn set_reset(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } } - impl Default for Inten { - #[inline(always)] - fn default() -> Inten { - Inten(0) - } - } - #[doc = "Mode configuration"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Mode(pub u32); - impl Mode { - #[doc = "Speed and power modes"] - #[inline(always)] - pub const fn sp(&self) -> super::vals::Sp { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Sp::from_bits(val as u8) - } - #[doc = "Speed and power modes"] - #[inline(always)] - pub fn set_sp(&mut self, val: super::vals::Sp) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Main operation modes"] - #[inline(always)] - pub const fn main(&self) -> super::vals::Main { - let val = (self.0 >> 8usize) & 0x01; - super::vals::Main::from_bits(val as u8) - } - #[doc = "Main operation modes"] - #[inline(always)] - pub fn set_main(&mut self, val: super::vals::Main) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val.to_bits() as u32) & 0x01) << 8usize); - } - } - impl Default for Mode { - #[inline(always)] - fn default() -> Mode { - Mode(0) - } - } - #[doc = "Pin select"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Psel(pub u32); - impl Psel { - #[doc = "Analog pin select"] - #[inline(always)] - pub const fn psel(&self) -> super::vals::PselPsel { - let val = (self.0 >> 0usize) & 0x07; - super::vals::PselPsel::from_bits(val as u8) - } - #[doc = "Analog pin select"] - #[inline(always)] - pub fn set_psel(&mut self, val: super::vals::PselPsel) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); - } - } - impl Default for Psel { + impl Default for DinFifoReset { #[inline(always)] - fn default() -> Psel { - Psel(0) + fn default() -> DinFifoReset { + DinFifoReset(0) } } - #[doc = "Reference source select for single-ended mode"] + #[doc = "Reset the DIN DMA engine."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Refsel(pub u32); - impl Refsel { - #[doc = "Reference select"] + pub struct DinSwReset(pub u32); + impl DinSwReset { + #[doc = "Writing any value to this address resets the DIN DMA engine. The reset takes 4 CPU clock cycles to complete."] #[inline(always)] - pub const fn refsel(&self) -> super::vals::Refsel { - let val = (self.0 >> 0usize) & 0x07; - super::vals::Refsel::from_bits(val as u8) + pub const fn reset(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 } - #[doc = "Reference select"] + #[doc = "Writing any value to this address resets the DIN DMA engine. The reset takes 4 CPU clock cycles to complete."] #[inline(always)] - pub fn set_refsel(&mut self, val: super::vals::Refsel) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); + pub fn set_reset(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } } - impl Default for Refsel { + impl Default for DinSwReset { #[inline(always)] - fn default() -> Refsel { - Refsel(0) + fn default() -> DinSwReset { + DinSwReset(0) } } - #[doc = "Compare result"] + #[doc = "Indicates that the next CPU write to the DIN_BUFFER is the last in the sequence. This is needed only when the data size is NOT modulo 4 (e.g. HASH padding)."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Result(pub u32); - impl Result { - #[doc = "Result of last compare. Decision point SAMPLE task."] + pub struct DinWriteAlign(pub u32); + impl DinWriteAlign { + #[doc = "Next CPU write to the DIN_BUFFER is the last word."] #[inline(always)] - pub const fn result(&self) -> super::vals::Result { + pub const fn last(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; - super::vals::Result::from_bits(val as u8) + val != 0 } - #[doc = "Result of last compare. Decision point SAMPLE task."] + #[doc = "Next CPU write to the DIN_BUFFER is the last word."] #[inline(always)] - pub fn set_result(&mut self, val: super::vals::Result) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); + pub fn set_last(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } } - impl Default for Result { + impl Default for DinWriteAlign { #[inline(always)] - fn default() -> Result { - Result(0) + fn default() -> DinWriteAlign { + DinWriteAlign(0) } } - #[doc = "Shortcut register"] + #[doc = "The number of bytes to be read from memory. Writing to this register triggers the DMA operation."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Shorts(pub u32); - impl Shorts { - #[doc = "Shortcut between READY event and SAMPLE task"] - #[inline(always)] - pub const fn ready_sample(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Shortcut between READY event and SAMPLE task"] - #[inline(always)] - pub fn set_ready_sample(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Shortcut between READY event and STOP task"] - #[inline(always)] - pub const fn ready_stop(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Shortcut between READY event and STOP task"] - #[inline(always)] - pub fn set_ready_stop(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Shortcut between DOWN event and STOP task"] + pub struct SrcMemSize(pub u32); + impl SrcMemSize { + #[doc = "Total number of bytes to read from memory."] #[inline(always)] - pub const fn down_stop(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 + pub const fn size(&self) -> u32 { + let val = (self.0 >> 0usize) & 0x3fff_ffff; + val as u32 } - #[doc = "Shortcut between DOWN event and STOP task"] + #[doc = "Total number of bytes to read from memory."] #[inline(always)] - pub fn set_down_stop(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + pub fn set_size(&mut self, val: u32) { + self.0 = + (self.0 & !(0x3fff_ffff << 0usize)) | (((val as u32) & 0x3fff_ffff) << 0usize); } - #[doc = "Shortcut between UP event and STOP task"] + #[doc = "This field is reserved"] #[inline(always)] - pub const fn up_stop(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; + pub const fn first(&self) -> bool { + let val = (self.0 >> 30usize) & 0x01; val != 0 } - #[doc = "Shortcut between UP event and STOP task"] + #[doc = "This field is reserved"] #[inline(always)] - pub fn set_up_stop(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + pub fn set_first(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize); } - #[doc = "Shortcut between CROSS event and STOP task"] + #[doc = "This field is reserved"] #[inline(always)] - pub const fn cross_stop(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; + pub const fn last(&self) -> bool { + let val = (self.0 >> 31usize) & 0x01; val != 0 } - #[doc = "Shortcut between CROSS event and STOP task"] - #[inline(always)] - pub fn set_cross_stop(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - } - impl Default for Shorts { - #[inline(always)] - fn default() -> Shorts { - Shorts(0) - } - } - #[doc = "Threshold configuration for hysteresis unit"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Th(pub u32); - impl Th { - #[doc = "VDOWN = (THDOWN+1)/64*VREF"] - #[inline(always)] - pub const fn thdown(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x3f; - val as u8 - } - #[doc = "VDOWN = (THDOWN+1)/64*VREF"] - #[inline(always)] - pub fn set_thdown(&mut self, val: u8) { - self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize); - } - #[doc = "VUP = (THUP+1)/64*VREF"] + #[doc = "This field is reserved"] #[inline(always)] - pub const fn thup(&self) -> u8 { - let val = (self.0 >> 8usize) & 0x3f; - val as u8 - } - #[doc = "VUP = (THUP+1)/64*VREF"] - #[inline(always)] - pub fn set_thup(&mut self, val: u8) { - self.0 = (self.0 & !(0x3f << 8usize)) | (((val as u32) & 0x3f) << 8usize); + pub fn set_last(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); } } - impl Default for Th { + impl Default for SrcMemSize { #[inline(always)] - fn default() -> Th { - Th(0) + fn default() -> SrcMemSize { + SrcMemSize(0) } } } pub mod vals { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub enum Enable { - #[doc = "Disable"] - DISABLED = 0x0, - _RESERVED_1 = 0x01, - #[doc = "Enable"] - ENABLED = 0x02, - _RESERVED_3 = 0x03, + pub enum DinDmaMemBusyStatus { + #[doc = "DIN memory DMA engine is idle"] + IDLE = 0x0, + #[doc = "DIN memory DMA engine is busy"] + BUSY = 0x01, } - impl Enable { + impl DinDmaMemBusyStatus { #[inline(always)] - pub const fn from_bits(val: u8) -> Enable { - unsafe { core::mem::transmute(val & 0x03) } + pub const fn from_bits(val: u8) -> DinDmaMemBusyStatus { + unsafe { core::mem::transmute(val & 0x01) } } #[inline(always)] pub const fn to_bits(self) -> u8 { unsafe { core::mem::transmute(self) } } } - impl From for Enable { + impl From for DinDmaMemBusyStatus { #[inline(always)] - fn from(val: u8) -> Enable { - Enable::from_bits(val) + fn from(val: u8) -> DinDmaMemBusyStatus { + DinDmaMemBusyStatus::from_bits(val) } } - impl From for u8 { + impl From for u8 { #[inline(always)] - fn from(val: Enable) -> u8 { - Enable::to_bits(val) + fn from(val: DinDmaMemBusyStatus) -> u8 { + DinDmaMemBusyStatus::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub enum Extrefsel { - #[doc = "Use AIN0 as external analog reference"] - ANALOG_REFERENCE0 = 0x0, - #[doc = "Use AIN1 as external analog reference"] - ANALOG_REFERENCE1 = 0x01, - #[doc = "Use AIN2 as external analog reference"] - ANALOG_REFERENCE2 = 0x02, - #[doc = "Use AIN3 as external analog reference"] - ANALOG_REFERENCE3 = 0x03, - #[doc = "Use AIN4 as external analog reference"] - ANALOG_REFERENCE4 = 0x04, - #[doc = "Use AIN5 as external analog reference"] - ANALOG_REFERENCE5 = 0x05, - #[doc = "Use AIN6 as external analog reference"] - ANALOG_REFERENCE6 = 0x06, - #[doc = "Use AIN7 as external analog reference"] - ANALOG_REFERENCE7 = 0x07, + pub enum DinDmaSramBusyStatus { + #[doc = "DIN RNG SRAM DMA engine is idle"] + IDLE = 0x0, + #[doc = "DIN RNG SRAM DMA engine is busy"] + BUSY = 0x01, } - impl Extrefsel { + impl DinDmaSramBusyStatus { #[inline(always)] - pub const fn from_bits(val: u8) -> Extrefsel { - unsafe { core::mem::transmute(val & 0x07) } + pub const fn from_bits(val: u8) -> DinDmaSramBusyStatus { + unsafe { core::mem::transmute(val & 0x01) } } #[inline(always)] pub const fn to_bits(self) -> u8 { unsafe { core::mem::transmute(self) } } } - impl From for Extrefsel { + impl From for DinDmaSramBusyStatus { #[inline(always)] - fn from(val: u8) -> Extrefsel { - Extrefsel::from_bits(val) + fn from(val: u8) -> DinDmaSramBusyStatus { + DinDmaSramBusyStatus::from_bits(val) } } - impl From for u8 { + impl From for u8 { #[inline(always)] - fn from(val: Extrefsel) -> u8 { - Extrefsel::to_bits(val) + fn from(val: DinDmaSramBusyStatus) -> u8 { + DinDmaSramBusyStatus::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub enum Hyst { - #[doc = "Comparator hysteresis disabled"] - NO_HYST = 0x0, - #[doc = "Comparator hysteresis enabled"] - HYST50M_V = 0x01, + pub enum Endian { + #[doc = "Use little-endian format for RNG SRAM DMA transactions"] + LITTLE_ENDIAN = 0x0, + #[doc = "Use big-endian format for RNG SRAM DMA transactions"] + BIG_ENDIAN = 0x01, } - impl Hyst { + impl Endian { #[inline(always)] - pub const fn from_bits(val: u8) -> Hyst { + pub const fn from_bits(val: u8) -> Endian { unsafe { core::mem::transmute(val & 0x01) } } #[inline(always)] @@ -2864,140 +2835,333 @@ pub mod comp { unsafe { core::mem::transmute(self) } } } - impl From for Hyst { + impl From for Endian { #[inline(always)] - fn from(val: u8) -> Hyst { - Hyst::from_bits(val) + fn from(val: u8) -> Endian { + Endian::from_bits(val) } } - impl From for u8 { + impl From for u8 { #[inline(always)] - fn from(val: Hyst) -> u8 { - Hyst::to_bits(val) + fn from(val: Endian) -> u8 { + Endian::to_bits(val) } } - #[repr(u8)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub enum Main { - #[doc = "Single-ended mode"] - SE = 0x0, - #[doc = "Differential mode"] - DIFF = 0x01, + } +} +pub mod cc_dout { + #[doc = "CRYPTOCELL Data OUT interface"] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct CcDout { + ptr: *mut u8, + } + unsafe impl Send for CcDout {} + unsafe impl Sync for CcDout {} + impl CcDout { + #[inline(always)] + pub const unsafe fn from_ptr(ptr: *mut ()) -> Self { + Self { ptr: ptr as _ } } - impl Main { - #[inline(always)] - pub const fn from_bits(val: u8) -> Main { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } + #[inline(always)] + pub const fn as_ptr(&self) -> *mut () { + self.ptr as _ + } + #[doc = "Cryptographic results directly accessible by the CPU."] + #[inline(always)] + pub const fn dout_buffer(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0c00usize) as _) } + } + #[doc = "Status register for DOUT DMA engine activity when accessing memory."] + #[inline(always)] + pub const fn dout_dma_mem_busy( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0d20usize) as _) } + } + #[doc = "Data destination address in memory."] + #[inline(always)] + pub const fn dst_mem_addr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0d28usize) as _) } + } + #[doc = "The number of bytes to be written to memory."] + #[inline(always)] + pub const fn dst_mem_size(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0d2cusize) as _) } + } + #[doc = "Data destination address in RNG SRAM."] + #[inline(always)] + pub const fn dst_sram_addr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0d30usize) as _) } + } + #[doc = "The number of bytes to be written to RNG SRAM."] + #[inline(always)] + pub const fn dst_sram_size(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0d34usize) as _) } + } + #[doc = "Status register for DOUT DMA engine activity when accessing RNG SRAM."] + #[inline(always)] + pub const fn dout_dma_sram_busy( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0d38usize) as _) } + } + #[doc = "Configure the endianness of DOUT DMA transactions towards RNG SRAM."] + #[inline(always)] + pub const fn dout_dma_sram_endianness( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0d3cusize) as _) } + } + #[doc = "Indication that the next CPU read from the DOUT_BUFFER is the last in the sequence. This is needed only when the data size is NOT modulo 4 (e.g. HASH padding)."] + #[inline(always)] + pub const fn dout_read_align( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0d44usize) as _) } + } + #[doc = "Register indicating if DOUT FIFO is empty or if more data will come."] + #[inline(always)] + pub const fn dout_fifo_empty( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0d50usize) as _) } + } + #[doc = "Reset the DOUT DMA engine."] + #[inline(always)] + pub const fn dout_sw_reset( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0d58usize) as _) } + } + } + pub mod regs { + #[doc = "Status register for DOUT DMA engine activity when accessing memory."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct DoutDmaMemBusy(pub u32); + impl DoutDmaMemBusy { + #[doc = "DOUT memory DMA engine status."] + #[inline(always)] + pub const fn status(&self) -> super::vals::DoutDmaMemBusyStatus { + let val = (self.0 >> 0usize) & 0x01; + super::vals::DoutDmaMemBusyStatus::from_bits(val as u8) + } + #[doc = "DOUT memory DMA engine status."] + #[inline(always)] + pub fn set_status(&mut self, val: super::vals::DoutDmaMemBusyStatus) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); } } - impl From for Main { + impl Default for DoutDmaMemBusy { #[inline(always)] - fn from(val: u8) -> Main { - Main::from_bits(val) + fn default() -> DoutDmaMemBusy { + DoutDmaMemBusy(0) } } - impl From
for u8 { + #[doc = "Status register for DOUT DMA engine activity when accessing RNG SRAM."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct DoutDmaSramBusy(pub u32); + impl DoutDmaSramBusy { + #[doc = "DOUT RNG SRAM DMA engine status."] #[inline(always)] - fn from(val: Main) -> u8 { - Main::to_bits(val) + pub const fn status(&self) -> super::vals::DoutDmaSramBusyStatus { + let val = (self.0 >> 0usize) & 0x01; + super::vals::DoutDmaSramBusyStatus::from_bits(val as u8) + } + #[doc = "DOUT RNG SRAM DMA engine status."] + #[inline(always)] + pub fn set_status(&mut self, val: super::vals::DoutDmaSramBusyStatus) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); } } - #[repr(u8)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub enum PselPsel { - #[doc = "AIN0 selected as analog input"] - ANALOG_INPUT0 = 0x0, - #[doc = "AIN1 selected as analog input"] - ANALOG_INPUT1 = 0x01, - #[doc = "AIN2 selected as analog input"] - ANALOG_INPUT2 = 0x02, - #[doc = "AIN3 selected as analog input"] - ANALOG_INPUT3 = 0x03, - #[doc = "AIN4 selected as analog input"] - ANALOG_INPUT4 = 0x04, - #[doc = "AIN5 selected as analog input"] - ANALOG_INPUT5 = 0x05, - #[doc = "AIN6 selected as analog input"] - ANALOG_INPUT6 = 0x06, - #[doc = "AIN7 selected as analog input"] - ANALOG_INPUT7 = 0x07, + impl Default for DoutDmaSramBusy { + #[inline(always)] + fn default() -> DoutDmaSramBusy { + DoutDmaSramBusy(0) + } } - impl PselPsel { + #[doc = "Configure the endianness of DOUT DMA transactions towards RNG SRAM."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct DoutDmaSramEndianness(pub u32); + impl DoutDmaSramEndianness { + #[doc = "Endianness of DOUT DMA transactions towards RNG SRAM. The default value is little-endian."] #[inline(always)] - pub const fn from_bits(val: u8) -> PselPsel { - unsafe { core::mem::transmute(val & 0x07) } + pub const fn endian(&self) -> super::vals::Endian { + let val = (self.0 >> 0usize) & 0x01; + super::vals::Endian::from_bits(val as u8) } + #[doc = "Endianness of DOUT DMA transactions towards RNG SRAM. The default value is little-endian."] #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } + pub fn set_endian(&mut self, val: super::vals::Endian) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); } } - impl From for PselPsel { + impl Default for DoutDmaSramEndianness { #[inline(always)] - fn from(val: u8) -> PselPsel { - PselPsel::from_bits(val) + fn default() -> DoutDmaSramEndianness { + DoutDmaSramEndianness(0) } } - impl From for u8 { + #[doc = "Register indicating if DOUT FIFO is empty or if more data will come."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct DoutFifoEmpty(pub u32); + impl DoutFifoEmpty { + #[doc = "DOUT FIFO status"] #[inline(always)] - fn from(val: PselPsel) -> u8 { - PselPsel::to_bits(val) + pub const fn status(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "DOUT FIFO status"] + #[inline(always)] + pub fn set_status(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + } + impl Default for DoutFifoEmpty { + #[inline(always)] + fn default() -> DoutFifoEmpty { + DoutFifoEmpty(0) + } + } + #[doc = "Indication that the next CPU read from the DOUT_BUFFER is the last in the sequence. This is needed only when the data size is NOT modulo 4 (e.g. HASH padding)."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct DoutReadAlign(pub u32); + impl DoutReadAlign { + #[doc = "Next CPU read from the DOUT_BUFFER is the last word, and the remaining read aligned content can be flushed."] + #[inline(always)] + pub const fn last(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Next CPU read from the DOUT_BUFFER is the last word, and the remaining read aligned content can be flushed."] + #[inline(always)] + pub fn set_last(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + } + impl Default for DoutReadAlign { + #[inline(always)] + fn default() -> DoutReadAlign { + DoutReadAlign(0) + } + } + #[doc = "Reset the DOUT DMA engine."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct DoutSwReset(pub u32); + impl DoutSwReset { + #[doc = "Writing any value to this address resets the DOUT DMA engine. The reset takes 4 CPU clock cycles to complete."] + #[inline(always)] + pub const fn reset(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Writing any value to this address resets the DOUT DMA engine. The reset takes 4 CPU clock cycles to complete."] + #[inline(always)] + pub fn set_reset(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } } + impl Default for DoutSwReset { + #[inline(always)] + fn default() -> DoutSwReset { + DoutSwReset(0) + } + } + #[doc = "The number of bytes to be written to memory."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct DstMemSize(pub u32); + impl DstMemSize { + #[doc = "Total number of bytes to write to memory."] + #[inline(always)] + pub const fn size(&self) -> u32 { + let val = (self.0 >> 0usize) & 0x3fff_ffff; + val as u32 + } + #[doc = "Total number of bytes to write to memory."] + #[inline(always)] + pub fn set_size(&mut self, val: u32) { + self.0 = + (self.0 & !(0x3fff_ffff << 0usize)) | (((val as u32) & 0x3fff_ffff) << 0usize); + } + #[doc = "This field is reserved"] + #[inline(always)] + pub const fn first(&self) -> bool { + let val = (self.0 >> 30usize) & 0x01; + val != 0 + } + #[doc = "This field is reserved"] + #[inline(always)] + pub fn set_first(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize); + } + #[doc = "This field is reserved"] + #[inline(always)] + pub const fn last(&self) -> bool { + let val = (self.0 >> 31usize) & 0x01; + val != 0 + } + #[doc = "This field is reserved"] + #[inline(always)] + pub fn set_last(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); + } + } + impl Default for DstMemSize { + #[inline(always)] + fn default() -> DstMemSize { + DstMemSize(0) + } + } + } + pub mod vals { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub enum Refsel { - #[doc = "VREF = internal 1.2 V reference (VDD >= 1.7 V)"] - INT1V2 = 0x0, - #[doc = "VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V)"] - INT1V8 = 0x01, - #[doc = "VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V)"] - INT2V4 = 0x02, - _RESERVED_3 = 0x03, - #[doc = "VREF = VDD"] - VDD = 0x04, - #[doc = "VREF = AREF (VDD >= VREF >= AREFMIN)"] - AREF = 0x05, - _RESERVED_6 = 0x06, - _RESERVED_7 = 0x07, + pub enum DoutDmaMemBusyStatus { + #[doc = "DOUT memory DMA engine is idle"] + IDLE = 0x0, + #[doc = "DOUT memory DMA engine is busy"] + BUSY = 0x01, } - impl Refsel { + impl DoutDmaMemBusyStatus { #[inline(always)] - pub const fn from_bits(val: u8) -> Refsel { - unsafe { core::mem::transmute(val & 0x07) } + pub const fn from_bits(val: u8) -> DoutDmaMemBusyStatus { + unsafe { core::mem::transmute(val & 0x01) } } #[inline(always)] pub const fn to_bits(self) -> u8 { unsafe { core::mem::transmute(self) } } } - impl From for Refsel { + impl From for DoutDmaMemBusyStatus { #[inline(always)] - fn from(val: u8) -> Refsel { - Refsel::from_bits(val) + fn from(val: u8) -> DoutDmaMemBusyStatus { + DoutDmaMemBusyStatus::from_bits(val) } } - impl From for u8 { + impl From for u8 { #[inline(always)] - fn from(val: Refsel) -> u8 { - Refsel::to_bits(val) + fn from(val: DoutDmaMemBusyStatus) -> u8 { + DoutDmaMemBusyStatus::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub enum Result { - #[doc = "Input voltage is below the threshold (VIN+ < VIN-)"] - BELOW = 0x0, - #[doc = "Input voltage is above the threshold (VIN+ > VIN-)"] - ABOVE = 0x01, + pub enum DoutDmaSramBusyStatus { + #[doc = "DOUT RNG SRAM DMA engine is idle"] + IDLE = 0x0, + #[doc = "DOUT RNG SRAM DMA engine is busy"] + BUSY = 0x01, } - impl Result { + impl DoutDmaSramBusyStatus { #[inline(always)] - pub const fn from_bits(val: u8) -> Result { + pub const fn from_bits(val: u8) -> DoutDmaSramBusyStatus { unsafe { core::mem::transmute(val & 0x01) } } #[inline(always)] @@ -3005,62 +3169,59 @@ pub mod comp { unsafe { core::mem::transmute(self) } } } - impl From for Result { + impl From for DoutDmaSramBusyStatus { #[inline(always)] - fn from(val: u8) -> Result { - Result::from_bits(val) + fn from(val: u8) -> DoutDmaSramBusyStatus { + DoutDmaSramBusyStatus::from_bits(val) } } - impl From for u8 { + impl From for u8 { #[inline(always)] - fn from(val: Result) -> u8 { - Result::to_bits(val) + fn from(val: DoutDmaSramBusyStatus) -> u8 { + DoutDmaSramBusyStatus::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub enum Sp { - #[doc = "Low-power mode"] - LOW = 0x0, - #[doc = "Normal mode"] - NORMAL = 0x01, - #[doc = "High-speed mode"] - HIGH = 0x02, - _RESERVED_3 = 0x03, + pub enum Endian { + #[doc = "Use little-endian format for RNG SRAM DMA transactions"] + LITTLE_ENDIAN = 0x0, + #[doc = "Use big-endian format for RNG SRAM DMA transactions"] + BIG_ENDIAN = 0x01, } - impl Sp { + impl Endian { #[inline(always)] - pub const fn from_bits(val: u8) -> Sp { - unsafe { core::mem::transmute(val & 0x03) } + pub const fn from_bits(val: u8) -> Endian { + unsafe { core::mem::transmute(val & 0x01) } } #[inline(always)] pub const fn to_bits(self) -> u8 { unsafe { core::mem::transmute(self) } } } - impl From for Sp { + impl From for Endian { #[inline(always)] - fn from(val: u8) -> Sp { - Sp::from_bits(val) + fn from(val: u8) -> Endian { + Endian::from_bits(val) } } - impl From for u8 { + impl From for u8 { #[inline(always)] - fn from(val: Sp) -> u8 { - Sp::to_bits(val) + fn from(val: Endian) -> u8 { + Endian::to_bits(val) } } } } -pub mod cryptocell { - #[doc = "ARM TrustZone CryptoCell register interface"] +pub mod cc_hash { + #[doc = "CRYPTOCELL HASH engine"] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Cryptocell { + pub struct CcHash { ptr: *mut u8, } - unsafe impl Send for Cryptocell {} - unsafe impl Sync for Cryptocell {} - impl Cryptocell { + unsafe impl Send for CcHash {} + unsafe impl Sync for CcHash {} + impl CcHash { #[inline(always)] pub const unsafe fn from_ptr(ptr: *mut ()) -> Self { Self { ptr: ptr as _ } @@ -3069,35 +3230,6333 @@ pub mod cryptocell { pub const fn as_ptr(&self) -> *mut () { self.ptr as _ } - #[doc = "Enable CRYPTOCELL subsystem"] + #[doc = "Description collection: HASH_H value registers. The initial HASH_H\\[0\\] register holds the least significant bits \\[31:0\\] of the value."] #[inline(always)] - pub const fn enable(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0500usize) as _) } + pub const fn hash_h(self, n: usize) -> crate::common::Reg { + assert!(n < 8usize); + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0640usize + n * 4usize) as _) } } - } - pub mod regs { - #[doc = "Enable CRYPTOCELL subsystem"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Enable(pub u32); - impl Enable { - #[doc = "Enable or disable the CRYPTOCELL subsystem"] - #[inline(always)] - pub const fn enable(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Enable or disable the CRYPTOCELL subsystem"] - #[inline(always)] - pub fn set_enable(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } + #[doc = "Configure the HASH engine to automatically pad data at the end of the DMA transfer to complete the digest operation."] + #[inline(always)] + pub const fn hash_pad_auto( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0684usize) as _) } } - impl Default for Enable { - #[inline(always)] - fn default() -> Enable { - Enable(0) - } + #[doc = "Configure HASH engine initial state registers."] + #[inline(always)] + pub const fn hash_init_state( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0694usize) as _) } + } + #[doc = "HASH engine HW version"] + #[inline(always)] + pub const fn hash_version(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x07b0usize) as _) } + } + #[doc = "Control the HASH engine behavior."] + #[inline(always)] + pub const fn hash_control( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x07c0usize) as _) } + } + #[doc = "Enable the hardware padding feature of the HASH engine."] + #[inline(always)] + pub const fn hash_pad(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x07c4usize) as _) } + } + #[doc = "Force the hardware padding operation to trigger if the input data length is zero bytes."] + #[inline(always)] + pub const fn hash_pad_force( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x07c8usize) as _) } + } + #[doc = "Bits \\[31:0\\] of the number of bytes that have been digested so far."] + #[inline(always)] + pub const fn hash_cur_len_0(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x07ccusize) as _) } + } + #[doc = "Bits \\[63:32\\] of the number of bytes that have been digested so far."] + #[inline(always)] + pub const fn hash_cur_len_1(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x07d0usize) as _) } + } + #[doc = "Hardware configuration of the HASH engine. Reset value holds the supported features."] + #[inline(always)] + pub const fn hash_hw_flags( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x07dcusize) as _) } + } + #[doc = "Reset the HASH engine."] + #[inline(always)] + pub const fn hash_sw_reset( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x07e4usize) as _) } + } + #[doc = "Configure the endianness of HASH data and padding generation."] + #[inline(always)] + pub const fn hash_endianness( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x07e8usize) as _) } + } + } + pub mod regs { + #[doc = "Control the HASH engine behavior."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct HashControl(pub u32); + impl HashControl { + #[doc = "Select HASH mode to execute"] + #[inline(always)] + pub const fn mode(&self) -> super::vals::Mode { + let val = (self.0 >> 0usize) & 0x0f; + super::vals::Mode::from_bits(val as u8) + } + #[doc = "Select HASH mode to execute"] + #[inline(always)] + pub fn set_mode(&mut self, val: super::vals::Mode) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val.to_bits() as u32) & 0x0f) << 0usize); + } + } + impl Default for HashControl { + #[inline(always)] + fn default() -> HashControl { + HashControl(0) + } + } + #[doc = "Configure the endianness of HASH data and padding generation."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct HashEndianness(pub u32); + impl HashEndianness { + #[doc = "Endianness of HASH data and padding generation. The default value is little-endian."] + #[inline(always)] + pub const fn endian(&self) -> super::vals::Endian { + let val = (self.0 >> 0usize) & 0x01; + super::vals::Endian::from_bits(val as u8) + } + #[doc = "Endianness of HASH data and padding generation. The default value is little-endian."] + #[inline(always)] + pub fn set_endian(&mut self, val: super::vals::Endian) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); + } + } + impl Default for HashEndianness { + #[inline(always)] + fn default() -> HashEndianness { + HashEndianness(0) + } + } + #[doc = "Hardware configuration of the HASH engine. Reset value holds the supported features."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct HashHwFlags(pub u32); + impl HashHwFlags { + #[doc = "Indicates the number of concurrent words the hash is using to compute signature."] + #[inline(always)] + pub const fn cw(&self) -> super::vals::Cw { + let val = (self.0 >> 0usize) & 0x0f; + super::vals::Cw::from_bits(val as u8) + } + #[doc = "Indicates the number of concurrent words the hash is using to compute signature."] + #[inline(always)] + pub fn set_cw(&mut self, val: super::vals::Cw) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val.to_bits() as u32) & 0x0f) << 0usize); + } + #[doc = "Indicate if Hi adders are present for each Hi value or 1 adder is shared for all Hi."] + #[inline(always)] + pub const fn ch(&self) -> super::vals::Ch { + let val = (self.0 >> 4usize) & 0x0f; + super::vals::Ch::from_bits(val as u8) + } + #[doc = "Indicate if Hi adders are present for each Hi value or 1 adder is shared for all Hi."] + #[inline(always)] + pub fn set_ch(&mut self, val: super::vals::Ch) { + self.0 = (self.0 & !(0x0f << 4usize)) | (((val.to_bits() as u32) & 0x0f) << 4usize); + } + #[doc = "Determine the granularity of word size."] + #[inline(always)] + pub const fn dw(&self) -> super::vals::Dw { + let val = (self.0 >> 8usize) & 0x0f; + super::vals::Dw::from_bits(val as u8) + } + #[doc = "Determine the granularity of word size."] + #[inline(always)] + pub fn set_dw(&mut self, val: super::vals::Dw) { + self.0 = (self.0 & !(0x0f << 8usize)) | (((val.to_bits() as u32) & 0x0f) << 8usize); + } + #[doc = "If this flag is set, the engine include SHA-512 support."] + #[inline(always)] + pub const fn sha_512_exists(&self) -> bool { + let val = (self.0 >> 12usize) & 0x01; + val != 0 + } + #[doc = "If this flag is set, the engine include SHA-512 support."] + #[inline(always)] + pub fn set_sha_512_exists(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); + } + #[doc = "If this flag is set, the engine include pad block support."] + #[inline(always)] + pub const fn pad_exists(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "If this flag is set, the engine include pad block support."] + #[inline(always)] + pub fn set_pad_exists(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + #[doc = "If this flag is set, the engine include MD5 support."] + #[inline(always)] + pub const fn md5_exists(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "If this flag is set, the engine include MD5 support."] + #[inline(always)] + pub fn set_md5_exists(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } + #[doc = "If this flag is set, the engine include HMAC support."] + #[inline(always)] + pub const fn hmac_exists(&self) -> bool { + let val = (self.0 >> 15usize) & 0x01; + val != 0 + } + #[doc = "If this flag is set, the engine include HMAC support."] + #[inline(always)] + pub fn set_hmac_exists(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); + } + #[doc = "If this flag is set, the engine include SHA-256 support."] + #[inline(always)] + pub const fn sha_256_exists(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "If this flag is set, the engine include SHA-256 support."] + #[inline(always)] + pub fn set_sha_256_exists(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + #[doc = "If this flag is set, the engine include compare digest logic."] + #[inline(always)] + pub const fn hash_compare_exists(&self) -> bool { + let val = (self.0 >> 17usize) & 0x01; + val != 0 + } + #[doc = "If this flag is set, the engine include compare digest logic."] + #[inline(always)] + pub fn set_hash_compare_exists(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); + } + #[doc = "If this flag is set, the engine include HASH to DOUT support."] + #[inline(always)] + pub const fn dump_hash_to_dout_exists(&self) -> bool { + let val = (self.0 >> 18usize) & 0x01; + val != 0 + } + #[doc = "If this flag is set, the engine include HASH to DOUT support."] + #[inline(always)] + pub fn set_dump_hash_to_dout_exists(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); + } + } + impl Default for HashHwFlags { + #[inline(always)] + fn default() -> HashHwFlags { + HashHwFlags(0) + } + } + #[doc = "Configure HASH engine initial state registers."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct HashInitState(pub u32); + impl HashInitState { + #[doc = "Enable loading of data to initial state registers. Digest/IV for HASH/AES_MAC."] + #[inline(always)] + pub const fn load(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Enable loading of data to initial state registers. Digest/IV for HASH/AES_MAC."] + #[inline(always)] + pub fn set_load(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + } + impl Default for HashInitState { + #[inline(always)] + fn default() -> HashInitState { + HashInitState(0) + } + } + #[doc = "Enable the hardware padding feature of the HASH engine."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct HashPad(pub u32); + impl HashPad { + #[doc = "Configure hardware padding feature."] + #[inline(always)] + pub const fn enable(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Configure hardware padding feature."] + #[inline(always)] + pub fn set_enable(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + } + impl Default for HashPad { + #[inline(always)] + fn default() -> HashPad { + HashPad(0) + } + } + #[doc = "Configure the HASH engine to automatically pad data at the end of the DMA transfer to complete the digest operation."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct HashPadAuto(pub u32); + impl HashPadAuto { + #[doc = "Enable automatic padding in hardware."] + #[inline(always)] + pub const fn hwpad(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Enable automatic padding in hardware."] + #[inline(always)] + pub fn set_hwpad(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + } + impl Default for HashPadAuto { + #[inline(always)] + fn default() -> HashPadAuto { + HashPadAuto(0) + } + } + #[doc = "Force the hardware padding operation to trigger if the input data length is zero bytes."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct HashPadForce(pub u32); + impl HashPadForce { + #[doc = "Trigger hardware padding operation."] + #[inline(always)] + pub const fn enable(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Trigger hardware padding operation."] + #[inline(always)] + pub fn set_enable(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + } + impl Default for HashPadForce { + #[inline(always)] + fn default() -> HashPadForce { + HashPadForce(0) + } + } + #[doc = "Reset the HASH engine."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct HashSwReset(pub u32); + impl HashSwReset { + #[doc = "Writing any value to this address resets the HASH engine. The reset takes 4 CPU clock cycles to complete."] + #[inline(always)] + pub const fn reset(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Writing any value to this address resets the HASH engine. The reset takes 4 CPU clock cycles to complete."] + #[inline(always)] + pub fn set_reset(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + } + impl Default for HashSwReset { + #[inline(always)] + fn default() -> HashSwReset { + HashSwReset(0) + } + } + #[doc = "HASH engine HW version"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct HashVersion(pub u32); + impl HashVersion { + #[inline(always)] + pub const fn patch(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 + } + #[inline(always)] + pub fn set_patch(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); + } + #[doc = "Minor version number"] + #[inline(always)] + pub const fn minor_version_number(&self) -> u8 { + let val = (self.0 >> 8usize) & 0x0f; + val as u8 + } + #[doc = "Minor version number"] + #[inline(always)] + pub fn set_minor_version_number(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 8usize)) | (((val as u32) & 0x0f) << 8usize); + } + #[doc = "Major version number"] + #[inline(always)] + pub const fn major_version_number(&self) -> u8 { + let val = (self.0 >> 12usize) & 0x0f; + val as u8 + } + #[doc = "Major version number"] + #[inline(always)] + pub fn set_major_version_number(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 12usize)) | (((val as u32) & 0x0f) << 12usize); + } + } + impl Default for HashVersion { + #[inline(always)] + fn default() -> HashVersion { + HashVersion(0) + } + } + } + pub mod vals { + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum Ch { + #[doc = "One Hi value is updated at a time."] + ONE = 0x0, + #[doc = "All Hi values are updated at the same time."] + ALL = 0x01, + _RESERVED_2 = 0x02, + _RESERVED_3 = 0x03, + _RESERVED_4 = 0x04, + _RESERVED_5 = 0x05, + _RESERVED_6 = 0x06, + _RESERVED_7 = 0x07, + _RESERVED_8 = 0x08, + _RESERVED_9 = 0x09, + _RESERVED_a = 0x0a, + _RESERVED_b = 0x0b, + _RESERVED_c = 0x0c, + _RESERVED_d = 0x0d, + _RESERVED_e = 0x0e, + _RESERVED_f = 0x0f, + } + impl Ch { + #[inline(always)] + pub const fn from_bits(val: u8) -> Ch { + unsafe { core::mem::transmute(val & 0x0f) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for Ch { + #[inline(always)] + fn from(val: u8) -> Ch { + Ch::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: Ch) -> u8 { + Ch::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum Cw { + _RESERVED_0 = 0x0, + #[doc = "One concurrent word used by hash during signature generation"] + ONE = 0x01, + #[doc = "Two concurrent words used by hash during signature generation"] + TWO = 0x02, + _RESERVED_3 = 0x03, + _RESERVED_4 = 0x04, + _RESERVED_5 = 0x05, + _RESERVED_6 = 0x06, + _RESERVED_7 = 0x07, + _RESERVED_8 = 0x08, + _RESERVED_9 = 0x09, + _RESERVED_a = 0x0a, + _RESERVED_b = 0x0b, + _RESERVED_c = 0x0c, + _RESERVED_d = 0x0d, + _RESERVED_e = 0x0e, + _RESERVED_f = 0x0f, + } + impl Cw { + #[inline(always)] + pub const fn from_bits(val: u8) -> Cw { + unsafe { core::mem::transmute(val & 0x0f) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for Cw { + #[inline(always)] + fn from(val: u8) -> Cw { + Cw::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: Cw) -> u8 { + Cw::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum Dw { + #[doc = "32 bits word data."] + _32BITS = 0x0, + #[doc = "64 bits word data."] + _64BITS = 0x01, + _RESERVED_2 = 0x02, + _RESERVED_3 = 0x03, + _RESERVED_4 = 0x04, + _RESERVED_5 = 0x05, + _RESERVED_6 = 0x06, + _RESERVED_7 = 0x07, + _RESERVED_8 = 0x08, + _RESERVED_9 = 0x09, + _RESERVED_a = 0x0a, + _RESERVED_b = 0x0b, + _RESERVED_c = 0x0c, + _RESERVED_d = 0x0d, + _RESERVED_e = 0x0e, + _RESERVED_f = 0x0f, + } + impl Dw { + #[inline(always)] + pub const fn from_bits(val: u8) -> Dw { + unsafe { core::mem::transmute(val & 0x0f) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for Dw { + #[inline(always)] + fn from(val: u8) -> Dw { + Dw::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: Dw) -> u8 { + Dw::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum Endian { + #[doc = "Use little-endian format for data and padding"] + LITTLE_ENDIAN = 0x0, + #[doc = "Use big-endian format for data and padding"] + BIG_ENDIAN = 0x01, + } + impl Endian { + #[inline(always)] + pub const fn from_bits(val: u8) -> Endian { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for Endian { + #[inline(always)] + fn from(val: u8) -> Endian { + Endian::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: Endian) -> u8 { + Endian::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum Mode { + _RESERVED_0 = 0x0, + #[doc = "Select SHA1 mode"] + SHA1 = 0x01, + #[doc = "Select SHA256 mode"] + SHA256 = 0x02, + _RESERVED_3 = 0x03, + _RESERVED_4 = 0x04, + _RESERVED_5 = 0x05, + _RESERVED_6 = 0x06, + _RESERVED_7 = 0x07, + _RESERVED_8 = 0x08, + _RESERVED_9 = 0x09, + #[doc = "Select SHA224 mode"] + SHA224 = 0x0a, + _RESERVED_b = 0x0b, + _RESERVED_c = 0x0c, + _RESERVED_d = 0x0d, + _RESERVED_e = 0x0e, + _RESERVED_f = 0x0f, + } + impl Mode { + #[inline(always)] + pub const fn from_bits(val: u8) -> Mode { + unsafe { core::mem::transmute(val & 0x0f) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for Mode { + #[inline(always)] + fn from(val: u8) -> Mode { + Mode::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: Mode) -> u8 { + Mode::to_bits(val) + } + } + } +} +pub mod cc_host_rgf { + #[doc = "CRYPTOCELL HOST register interface"] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct CcHostRgf { + ptr: *mut u8, + } + unsafe impl Send for CcHostRgf {} + unsafe impl Sync for CcHostRgf {} + impl CcHostRgf { + #[inline(always)] + pub const unsafe fn from_ptr(ptr: *mut ()) -> Self { + Self { ptr: ptr as _ } + } + #[inline(always)] + pub const fn as_ptr(&self) -> *mut () { + self.ptr as _ + } + #[doc = "Interrupt request register. Each bit of this register holds the interrupt status of a single interrupt source. If corresponding IMR bit is unmasked, an interrupt is generated."] + #[inline(always)] + pub const fn irr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0a00usize) as _) } + } + #[doc = "Interrupt mask register. Each bit of this register holds the mask of a single interrupt source."] + #[inline(always)] + pub const fn imr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0a04usize) as _) } + } + #[doc = "Interrupt clear register. Writing a 1 bit into a field in this register will clear the corresponding bit in IRR."] + #[inline(always)] + pub const fn icr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0a08usize) as _) } + } + #[doc = "This register defines the endianness of the Host-accessible registers, and can only be written once."] + #[inline(always)] + pub const fn endianness(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0a0cusize) as _) } + } + #[doc = "This register holds the CRYPTOCELL subsystem signature. See reset value."] + #[inline(always)] + pub const fn host_signature(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0a24usize) as _) } + } + #[doc = "Hardware configuration of the CRYPTOCELL subsystem. Reset value holds the supported features."] + #[inline(always)] + pub const fn host_boot(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0a28usize) as _) } + } + #[doc = "AES hardware key select."] + #[inline(always)] + pub const fn host_cryptokey_sel( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0a38usize) as _) } + } + #[doc = "This write-once register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain."] + #[inline(always)] + pub const fn host_iot_kprtl_lock( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0a4cusize) as _) } + } + #[doc = "This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained."] + #[inline(always)] + pub const fn host_iot_kdr0( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0a50usize) as _) } + } + #[doc = "This register holds bits 63:32 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain."] + #[inline(always)] + pub const fn host_iot_kdr1(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0a54usize) as _) } + } + #[doc = "This register holds bits 95:64 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain."] + #[inline(always)] + pub const fn host_iot_kdr2(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0a58usize) as _) } + } + #[doc = "This register holds bits 127:96 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain."] + #[inline(always)] + pub const fn host_iot_kdr3(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0a5cusize) as _) } + } + #[doc = "Controls life-cycle state (LCS) for CRYPTOCELL subsystem"] + #[inline(always)] + pub const fn host_iot_lcs(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0a60usize) as _) } + } + } + pub mod regs { + #[doc = "This register defines the endianness of the Host-accessible registers, and can only be written once."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Endianness(pub u32); + impl Endianness { + #[doc = "DOUT write endianness."] + #[inline(always)] + pub const fn dout_wr_bg(&self) -> super::vals::DoutWrBg { + let val = (self.0 >> 3usize) & 0x01; + super::vals::DoutWrBg::from_bits(val as u8) + } + #[doc = "DOUT write endianness."] + #[inline(always)] + pub fn set_dout_wr_bg(&mut self, val: super::vals::DoutWrBg) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val.to_bits() as u32) & 0x01) << 3usize); + } + #[doc = "DIN read endianness."] + #[inline(always)] + pub const fn din_rd_bg(&self) -> super::vals::DinRdBg { + let val = (self.0 >> 7usize) & 0x01; + super::vals::DinRdBg::from_bits(val as u8) + } + #[doc = "DIN read endianness."] + #[inline(always)] + pub fn set_din_rd_bg(&mut self, val: super::vals::DinRdBg) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.to_bits() as u32) & 0x01) << 7usize); + } + #[doc = "DOUT write word endianness."] + #[inline(always)] + pub const fn dout_wr_wbg(&self) -> super::vals::DoutWrWbg { + let val = (self.0 >> 11usize) & 0x01; + super::vals::DoutWrWbg::from_bits(val as u8) + } + #[doc = "DOUT write word endianness."] + #[inline(always)] + pub fn set_dout_wr_wbg(&mut self, val: super::vals::DoutWrWbg) { + self.0 = + (self.0 & !(0x01 << 11usize)) | (((val.to_bits() as u32) & 0x01) << 11usize); + } + #[doc = "DIN read word endianness."] + #[inline(always)] + pub const fn din_rd_wbg(&self) -> super::vals::DinRdWbg { + let val = (self.0 >> 15usize) & 0x01; + super::vals::DinRdWbg::from_bits(val as u8) + } + #[doc = "DIN read word endianness."] + #[inline(always)] + pub fn set_din_rd_wbg(&mut self, val: super::vals::DinRdWbg) { + self.0 = + (self.0 & !(0x01 << 15usize)) | (((val.to_bits() as u32) & 0x01) << 15usize); + } + } + impl Default for Endianness { + #[inline(always)] + fn default() -> Endianness { + Endianness(0) + } + } + #[doc = "Hardware configuration of the CRYPTOCELL subsystem. Reset value holds the supported features."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct HostBoot(pub u32); + impl HostBoot { + #[doc = "If this flag is set, full power gating is implemented"] + #[inline(always)] + pub const fn power_gating_exists_local(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "If this flag is set, full power gating is implemented"] + #[inline(always)] + pub fn set_power_gating_exists_local(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "If this flag is set, large RKEK is supported"] + #[inline(always)] + pub const fn large_rkek_local(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "If this flag is set, large RKEK is supported"] + #[inline(always)] + pub fn set_large_rkek_local(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "If this flag is set, HASH in fuses is supported"] + #[inline(always)] + pub const fn hash_in_fuses_local(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "If this flag is set, HASH in fuses is supported"] + #[inline(always)] + pub fn set_hash_in_fuses_local(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "If this flag is set, external secure memory is supported"] + #[inline(always)] + pub const fn ext_mem_secured_local(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "If this flag is set, external secure memory is supported"] + #[inline(always)] + pub fn set_ext_mem_secured_local(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "If this flag is set, RKEK ECC is supported"] + #[inline(always)] + pub const fn rkek_ecc_exists_local_n(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "If this flag is set, RKEK ECC is supported"] + #[inline(always)] + pub fn set_rkek_ecc_exists_local_n(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "SRAM size"] + #[inline(always)] + pub const fn sram_size_local(&self) -> u8 { + let val = (self.0 >> 6usize) & 0x07; + val as u8 + } + #[doc = "SRAM size"] + #[inline(always)] + pub fn set_sram_size_local(&mut self, val: u8) { + self.0 = (self.0 & !(0x07 << 6usize)) | (((val as u32) & 0x07) << 6usize); + } + #[doc = "If this flag is set, Descriptors are supported"] + #[inline(always)] + pub const fn dscrptr_exists_local(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "If this flag is set, Descriptors are supported"] + #[inline(always)] + pub fn set_dscrptr_exists_local(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "If this flag is set, PAU is supported"] + #[inline(always)] + pub const fn pau_exists_local(&self) -> bool { + let val = (self.0 >> 10usize) & 0x01; + val != 0 + } + #[doc = "If this flag is set, PAU is supported"] + #[inline(always)] + pub fn set_pau_exists_local(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); + } + #[doc = "If this flag is set, the RNG engine is present"] + #[inline(always)] + pub const fn rng_exists_local(&self) -> bool { + let val = (self.0 >> 11usize) & 0x01; + val != 0 + } + #[doc = "If this flag is set, the RNG engine is present"] + #[inline(always)] + pub fn set_rng_exists_local(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); + } + #[doc = "If this flag is set, the PKA engine is present"] + #[inline(always)] + pub const fn pka_exists_local(&self) -> bool { + let val = (self.0 >> 12usize) & 0x01; + val != 0 + } + #[doc = "If this flag is set, the PKA engine is present"] + #[inline(always)] + pub fn set_pka_exists_local(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); + } + #[doc = "If this flag is set, the RC4 engine is present"] + #[inline(always)] + pub const fn rc4_exists_local(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "If this flag is set, the RC4 engine is present"] + #[inline(always)] + pub fn set_rc4_exists_local(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + #[doc = "If this flag is set, the HASH engine supports SHA512"] + #[inline(always)] + pub const fn sha_512_prsnt_local(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "If this flag is set, the HASH engine supports SHA512"] + #[inline(always)] + pub fn set_sha_512_prsnt_local(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } + #[doc = "If this flag is set, the HASH engine supports SHA256"] + #[inline(always)] + pub const fn sha_256_prsnt_local(&self) -> bool { + let val = (self.0 >> 15usize) & 0x01; + val != 0 + } + #[doc = "If this flag is set, the HASH engine supports SHA256"] + #[inline(always)] + pub fn set_sha_256_prsnt_local(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); + } + #[doc = "If this flag is set, the HASH engine supports MD5"] + #[inline(always)] + pub const fn md5_prsnt_local(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "If this flag is set, the HASH engine supports MD5"] + #[inline(always)] + pub fn set_md5_prsnt_local(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + #[doc = "If this flag is set, the HASH engine is present"] + #[inline(always)] + pub const fn hash_exists_local(&self) -> bool { + let val = (self.0 >> 17usize) & 0x01; + val != 0 + } + #[doc = "If this flag is set, the HASH engine is present"] + #[inline(always)] + pub fn set_hash_exists_local(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); + } + #[doc = "If this flag is set, the C2 engine is present"] + #[inline(always)] + pub const fn c2_exists_local(&self) -> bool { + let val = (self.0 >> 18usize) & 0x01; + val != 0 + } + #[doc = "If this flag is set, the C2 engine is present"] + #[inline(always)] + pub fn set_c2_exists_local(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); + } + #[doc = "If this flag is set, the DES engine is present"] + #[inline(always)] + pub const fn des_exists_local(&self) -> bool { + let val = (self.0 >> 19usize) & 0x01; + val != 0 + } + #[doc = "If this flag is set, the DES engine is present"] + #[inline(always)] + pub fn set_des_exists_local(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize); + } + #[doc = "If this flag is set, AES XCBC-MAC mode is supported"] + #[inline(always)] + pub const fn aes_xcbc_mac_exists_local(&self) -> bool { + let val = (self.0 >> 20usize) & 0x01; + val != 0 + } + #[doc = "If this flag is set, AES XCBC-MAC mode is supported"] + #[inline(always)] + pub fn set_aes_xcbc_mac_exists_local(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize); + } + #[doc = "If this flag is set, AES CMAC mode is supported"] + #[inline(always)] + pub const fn aes_cmac_exists_local(&self) -> bool { + let val = (self.0 >> 21usize) & 0x01; + val != 0 + } + #[doc = "If this flag is set, AES CMAC mode is supported"] + #[inline(always)] + pub fn set_aes_cmac_exists_local(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize); + } + #[doc = "If this flag is set, AES CCM mode is supported"] + #[inline(always)] + pub const fn aes_ccm_exists_local(&self) -> bool { + let val = (self.0 >> 22usize) & 0x01; + val != 0 + } + #[doc = "If this flag is set, AES CCM mode is supported"] + #[inline(always)] + pub fn set_aes_ccm_exists_local(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize); + } + #[doc = "If this flag is set, AES XEX mode T-value calculation in HW is supported"] + #[inline(always)] + pub const fn aes_xex_hw_t_calc_local(&self) -> bool { + let val = (self.0 >> 23usize) & 0x01; + val != 0 + } + #[doc = "If this flag is set, AES XEX mode T-value calculation in HW is supported"] + #[inline(always)] + pub fn set_aes_xex_hw_t_calc_local(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); + } + #[doc = "If this flag is set, AES XEX mode is supported"] + #[inline(always)] + pub const fn aes_xex_exists_local(&self) -> bool { + let val = (self.0 >> 24usize) & 0x01; + val != 0 + } + #[doc = "If this flag is set, AES XEX mode is supported"] + #[inline(always)] + pub fn set_aes_xex_exists_local(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); + } + #[doc = "If this flag is set, AES CTR mode is supported"] + #[inline(always)] + pub const fn ctr_exists_local(&self) -> bool { + let val = (self.0 >> 25usize) & 0x01; + val != 0 + } + #[doc = "If this flag is set, AES CTR mode is supported"] + #[inline(always)] + pub fn set_ctr_exists_local(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); + } + #[doc = "If this flag is set, the AES engine data input support byte size resolution"] + #[inline(always)] + pub const fn aes_din_byte_resolution_local(&self) -> bool { + let val = (self.0 >> 26usize) & 0x01; + val != 0 + } + #[doc = "If this flag is set, the AES engine data input support byte size resolution"] + #[inline(always)] + pub fn set_aes_din_byte_resolution_local(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); + } + #[doc = "If this flag is set, the AES engine supports tunneling operations"] + #[inline(always)] + pub const fn tunneling_enb_local(&self) -> bool { + let val = (self.0 >> 27usize) & 0x01; + val != 0 + } + #[doc = "If this flag is set, the AES engine supports tunneling operations"] + #[inline(always)] + pub fn set_tunneling_enb_local(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize); + } + #[doc = "If this flag is set, the AES engine supports 192/256 bits key sizes"] + #[inline(always)] + pub const fn support_256_192_key_local(&self) -> bool { + let val = (self.0 >> 28usize) & 0x01; + val != 0 + } + #[doc = "If this flag is set, the AES engine supports 192/256 bits key sizes"] + #[inline(always)] + pub fn set_support_256_192_key_local(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize); + } + #[doc = "If this flag is set, the AES engine only support encryption"] + #[inline(always)] + pub const fn only_encrypt_local(&self) -> bool { + let val = (self.0 >> 29usize) & 0x01; + val != 0 + } + #[doc = "If this flag is set, the AES engine only support encryption"] + #[inline(always)] + pub fn set_only_encrypt_local(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize); + } + #[doc = "If this flag is set, the AES engine is present"] + #[inline(always)] + pub const fn aes_exists_local(&self) -> bool { + let val = (self.0 >> 30usize) & 0x01; + val != 0 + } + #[doc = "If this flag is set, the AES engine is present"] + #[inline(always)] + pub fn set_aes_exists_local(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize); + } + } + impl Default for HostBoot { + #[inline(always)] + fn default() -> HostBoot { + HostBoot(0) + } + } + #[doc = "AES hardware key select."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct HostCryptokeySel(pub u32); + impl HostCryptokeySel { + #[doc = "Select the source of the HW key that is used by the AES engine"] + #[inline(always)] + pub const fn host_cryptokey_sel(&self) -> super::vals::HostCryptokeySel { + let val = (self.0 >> 0usize) & 0x03; + super::vals::HostCryptokeySel::from_bits(val as u8) + } + #[doc = "Select the source of the HW key that is used by the AES engine"] + #[inline(always)] + pub fn set_host_cryptokey_sel(&mut self, val: super::vals::HostCryptokeySel) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); + } + } + impl Default for HostCryptokeySel { + #[inline(always)] + fn default() -> HostCryptokeySel { + HostCryptokeySel(0) + } + } + #[doc = "This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct HostIotKdr0(pub u32); + impl HostIotKdr0 { + #[doc = "This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained. Write: K_DR bits 31:0."] + #[inline(always)] + pub const fn host_iot_kdr0(&self) -> super::vals::HostIotKdr0 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + super::vals::HostIotKdr0::from_bits(val as u32) + } + #[doc = "This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained. Write: K_DR bits 31:0."] + #[inline(always)] + pub fn set_host_iot_kdr0(&mut self, val: super::vals::HostIotKdr0) { + self.0 = (self.0 & !(0xffff_ffff << 0usize)) + | (((val.to_bits() as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for HostIotKdr0 { + #[inline(always)] + fn default() -> HostIotKdr0 { + HostIotKdr0(0) + } + } + #[doc = "This write-once register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct HostIotKprtlLock(pub u32); + impl HostIotKprtlLock { + #[doc = "This register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain."] + #[inline(always)] + pub const fn host_iot_kprtl_lock(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "This register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain."] + #[inline(always)] + pub fn set_host_iot_kprtl_lock(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + } + impl Default for HostIotKprtlLock { + #[inline(always)] + fn default() -> HostIotKprtlLock { + HostIotKprtlLock(0) + } + } + #[doc = "Controls life-cycle state (LCS) for CRYPTOCELL subsystem"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct HostIotLcs(pub u32); + impl HostIotLcs { + #[doc = "Life-cycle state value. This field is write-once per reset."] + #[inline(always)] + pub const fn lcs(&self) -> super::vals::Lcs { + let val = (self.0 >> 0usize) & 0x07; + super::vals::Lcs::from_bits(val as u8) + } + #[doc = "Life-cycle state value. This field is write-once per reset."] + #[inline(always)] + pub fn set_lcs(&mut self, val: super::vals::Lcs) { + self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); + } + #[doc = "Read-only field. Indicates if CRYPTOCELL LCS has been successfully configured since last reset."] + #[inline(always)] + pub const fn lcs_is_valid(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Read-only field. Indicates if CRYPTOCELL LCS has been successfully configured since last reset."] + #[inline(always)] + pub fn set_lcs_is_valid(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + } + impl Default for HostIotLcs { + #[inline(always)] + fn default() -> HostIotLcs { + HostIotLcs(0) + } + } + #[doc = "Interrupt clear register. Writing a 1 bit into a field in this register will clear the corresponding bit in IRR."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Icr(pub u32); + impl Icr { + #[doc = "The RNG SRAM to DIN DMA done interrupt clear."] + #[inline(always)] + pub const fn sram_to_din_clear(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "The RNG SRAM to DIN DMA done interrupt clear."] + #[inline(always)] + pub fn set_sram_to_din_clear(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "The DOUT to RNG SRAM DMA done interrupt clear."] + #[inline(always)] + pub const fn dout_to_sram_clear(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "The DOUT to RNG SRAM DMA done interrupt clear."] + #[inline(always)] + pub fn set_dout_to_sram_clear(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "The memory to DIN DMA done interrupt clear."] + #[inline(always)] + pub const fn mem_to_din_clear(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "The memory to DIN DMA done interrupt clear."] + #[inline(always)] + pub fn set_mem_to_din_clear(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "The DOUT to memory DMA done interrupt clear."] + #[inline(always)] + pub const fn dout_to_mem_clear(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "The DOUT to memory DMA done interrupt clear."] + #[inline(always)] + pub fn set_dout_to_mem_clear(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "The AHB error interrupt clear."] + #[inline(always)] + pub const fn ahb_err_clear(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "The AHB error interrupt clear."] + #[inline(always)] + pub fn set_ahb_err_clear(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "The PKA end of operation interrupt clear."] + #[inline(always)] + pub const fn pka_clear(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "The PKA end of operation interrupt clear."] + #[inline(always)] + pub fn set_pka_clear(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "The RNG interrupt clear. Register RNG_ISR in the RNG engine must be cleared before this interrupt can be cleared."] + #[inline(always)] + pub const fn rng_clear(&self) -> bool { + let val = (self.0 >> 10usize) & 0x01; + val != 0 + } + #[doc = "The RNG interrupt clear. Register RNG_ISR in the RNG engine must be cleared before this interrupt can be cleared."] + #[inline(always)] + pub fn set_rng_clear(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); + } + } + impl Default for Icr { + #[inline(always)] + fn default() -> Icr { + Icr(0) + } + } + #[doc = "Interrupt mask register. Each bit of this register holds the mask of a single interrupt source."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Imr(pub u32); + impl Imr { + #[doc = "The RNG SRAM to DIN DMA done interrupt mask."] + #[inline(always)] + pub const fn sram_to_din_mask(&self) -> super::vals::SramToDinMask { + let val = (self.0 >> 4usize) & 0x01; + super::vals::SramToDinMask::from_bits(val as u8) + } + #[doc = "The RNG SRAM to DIN DMA done interrupt mask."] + #[inline(always)] + pub fn set_sram_to_din_mask(&mut self, val: super::vals::SramToDinMask) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val.to_bits() as u32) & 0x01) << 4usize); + } + #[doc = "The DOUT to RNG SRAM DMA done interrupt mask."] + #[inline(always)] + pub const fn dout_to_sram_mask(&self) -> super::vals::DoutToSramMask { + let val = (self.0 >> 5usize) & 0x01; + super::vals::DoutToSramMask::from_bits(val as u8) + } + #[doc = "The DOUT to RNG SRAM DMA done interrupt mask."] + #[inline(always)] + pub fn set_dout_to_sram_mask(&mut self, val: super::vals::DoutToSramMask) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val.to_bits() as u32) & 0x01) << 5usize); + } + #[doc = "The memory to DIN DMA done interrupt mask."] + #[inline(always)] + pub const fn mem_to_din_mask(&self) -> super::vals::MemToDinMask { + let val = (self.0 >> 6usize) & 0x01; + super::vals::MemToDinMask::from_bits(val as u8) + } + #[doc = "The memory to DIN DMA done interrupt mask."] + #[inline(always)] + pub fn set_mem_to_din_mask(&mut self, val: super::vals::MemToDinMask) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); + } + #[doc = "The DOUT to memory DMA done interrupt mask."] + #[inline(always)] + pub const fn dout_to_mem_mask(&self) -> super::vals::DoutToMemMask { + let val = (self.0 >> 7usize) & 0x01; + super::vals::DoutToMemMask::from_bits(val as u8) + } + #[doc = "The DOUT to memory DMA done interrupt mask."] + #[inline(always)] + pub fn set_dout_to_mem_mask(&mut self, val: super::vals::DoutToMemMask) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.to_bits() as u32) & 0x01) << 7usize); + } + #[doc = "The AHB error interrupt mask."] + #[inline(always)] + pub const fn ahb_err_mask(&self) -> super::vals::AhbErrMask { + let val = (self.0 >> 8usize) & 0x01; + super::vals::AhbErrMask::from_bits(val as u8) + } + #[doc = "The AHB error interrupt mask."] + #[inline(always)] + pub fn set_ahb_err_mask(&mut self, val: super::vals::AhbErrMask) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val.to_bits() as u32) & 0x01) << 8usize); + } + #[doc = "The PKA end of operation interrupt mask."] + #[inline(always)] + pub const fn pka_mask(&self) -> super::vals::PkaMask { + let val = (self.0 >> 9usize) & 0x01; + super::vals::PkaMask::from_bits(val as u8) + } + #[doc = "The PKA end of operation interrupt mask."] + #[inline(always)] + pub fn set_pka_mask(&mut self, val: super::vals::PkaMask) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val.to_bits() as u32) & 0x01) << 9usize); + } + #[doc = "The RNG interrupt mask."] + #[inline(always)] + pub const fn rng_mask(&self) -> super::vals::RngMask { + let val = (self.0 >> 10usize) & 0x01; + super::vals::RngMask::from_bits(val as u8) + } + #[doc = "The RNG interrupt mask."] + #[inline(always)] + pub fn set_rng_mask(&mut self, val: super::vals::RngMask) { + self.0 = + (self.0 & !(0x01 << 10usize)) | (((val.to_bits() as u32) & 0x01) << 10usize); + } + } + impl Default for Imr { + #[inline(always)] + fn default() -> Imr { + Imr(0) + } + } + #[doc = "Interrupt request register. Each bit of this register holds the interrupt status of a single interrupt source. If corresponding IMR bit is unmasked, an interrupt is generated."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Irr(pub u32); + impl Irr { + #[doc = "The RNG SRAM to DIN DMA done interrupt status. This interrupt is asserted when all data was delivered from RNG SRAM to DIN buffer."] + #[inline(always)] + pub const fn sram_to_din_int(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "The RNG SRAM to DIN DMA done interrupt status. This interrupt is asserted when all data was delivered from RNG SRAM to DIN buffer."] + #[inline(always)] + pub fn set_sram_to_din_int(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "The DOUT to RNG SRAM DMA done interrupt status. This interrupt is asserted when all data was delivered from DOUT buffer to RNG SRAM."] + #[inline(always)] + pub const fn dout_to_sram_int(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "The DOUT to RNG SRAM DMA done interrupt status. This interrupt is asserted when all data was delivered from DOUT buffer to RNG SRAM."] + #[inline(always)] + pub fn set_dout_to_sram_int(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "The memory to DIN DMA done interrupt status. This interrupt is asserted when all data was delivered from memory to DIN buffer."] + #[inline(always)] + pub const fn mem_to_din_int(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "The memory to DIN DMA done interrupt status. This interrupt is asserted when all data was delivered from memory to DIN buffer."] + #[inline(always)] + pub fn set_mem_to_din_int(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "The DOUT to memory DMA done interrupt status. This interrupt is asserted when all data was delivered from DOUT buffer to memory."] + #[inline(always)] + pub const fn dout_to_mem_int(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "The DOUT to memory DMA done interrupt status. This interrupt is asserted when all data was delivered from DOUT buffer to memory."] + #[inline(always)] + pub fn set_dout_to_mem_int(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "The AHB error interrupt status."] + #[inline(always)] + pub const fn ahb_err_int(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "The AHB error interrupt status."] + #[inline(always)] + pub fn set_ahb_err_int(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "The PKA end of operation interrupt status."] + #[inline(always)] + pub const fn pka_int(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "The PKA end of operation interrupt status."] + #[inline(always)] + pub fn set_pka_int(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "The RNG interrupt status."] + #[inline(always)] + pub const fn rng_int(&self) -> bool { + let val = (self.0 >> 10usize) & 0x01; + val != 0 + } + #[doc = "The RNG interrupt status."] + #[inline(always)] + pub fn set_rng_int(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); + } + } + impl Default for Irr { + #[inline(always)] + fn default() -> Irr { + Irr(0) + } + } + } + pub mod vals { + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum AhbErrMask { + #[doc = "Do not mask AHB error interrupt i.e. interrupt is generated"] + IRQENABLE = 0x0, + #[doc = "Mask AHB error interrupt i.e. no interrupt is generated"] + IRQDISABLE = 0x01, + } + impl AhbErrMask { + #[inline(always)] + pub const fn from_bits(val: u8) -> AhbErrMask { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for AhbErrMask { + #[inline(always)] + fn from(val: u8) -> AhbErrMask { + AhbErrMask::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: AhbErrMask) -> u8 { + AhbErrMask::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum DinRdBg { + #[doc = "Configure DIN read as little-endian"] + LITTLE_ENDIAN = 0x0, + #[doc = "Configure DIN read as big-endian"] + BIG_ENDIAN = 0x01, + } + impl DinRdBg { + #[inline(always)] + pub const fn from_bits(val: u8) -> DinRdBg { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for DinRdBg { + #[inline(always)] + fn from(val: u8) -> DinRdBg { + DinRdBg::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: DinRdBg) -> u8 { + DinRdBg::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum DinRdWbg { + #[doc = "Configure DIN read word as little-endian"] + LITTLE_ENDIAN = 0x0, + #[doc = "Configure DIN read word as big-endian"] + BIG_ENDIAN = 0x01, + } + impl DinRdWbg { + #[inline(always)] + pub const fn from_bits(val: u8) -> DinRdWbg { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for DinRdWbg { + #[inline(always)] + fn from(val: u8) -> DinRdWbg { + DinRdWbg::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: DinRdWbg) -> u8 { + DinRdWbg::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum DoutToMemMask { + #[doc = "Do not mask DOUT to memory DMA done interrupt i.e. interrupt is generated"] + IRQENABLE = 0x0, + #[doc = "Mask DOUT to memory DMA done interrupt i.e. no interrupt is generated"] + IRQDISABLE = 0x01, + } + impl DoutToMemMask { + #[inline(always)] + pub const fn from_bits(val: u8) -> DoutToMemMask { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for DoutToMemMask { + #[inline(always)] + fn from(val: u8) -> DoutToMemMask { + DoutToMemMask::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: DoutToMemMask) -> u8 { + DoutToMemMask::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum DoutToSramMask { + #[doc = "Do not mask DOUT to RNG SRAM DMA done interrupt i.e. interrupt is generated"] + IRQENABLE = 0x0, + #[doc = "Mask DOUT to RNG SRAM DMA done interrupt i.e. no interrupt is generated"] + IRQDISABLE = 0x01, + } + impl DoutToSramMask { + #[inline(always)] + pub const fn from_bits(val: u8) -> DoutToSramMask { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for DoutToSramMask { + #[inline(always)] + fn from(val: u8) -> DoutToSramMask { + DoutToSramMask::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: DoutToSramMask) -> u8 { + DoutToSramMask::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum DoutWrBg { + #[doc = "Configure DOUT write as little-endian"] + LITTLE_ENDIAN = 0x0, + #[doc = "Configure DOUT write as big-endian"] + BIG_ENDIAN = 0x01, + } + impl DoutWrBg { + #[inline(always)] + pub const fn from_bits(val: u8) -> DoutWrBg { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for DoutWrBg { + #[inline(always)] + fn from(val: u8) -> DoutWrBg { + DoutWrBg::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: DoutWrBg) -> u8 { + DoutWrBg::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum DoutWrWbg { + #[doc = "Configure DOUT write word as little-endian"] + LITTLE_ENDIAN = 0x0, + #[doc = "Configure DOUT write word as big-endian"] + BIG_ENDIAN = 0x01, + } + impl DoutWrWbg { + #[inline(always)] + pub const fn from_bits(val: u8) -> DoutWrWbg { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for DoutWrWbg { + #[inline(always)] + fn from(val: u8) -> DoutWrWbg { + DoutWrWbg::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: DoutWrWbg) -> u8 { + DoutWrWbg::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum HostCryptokeySel { + #[doc = "Use device root key K_DR from CRYPTOCELL AO power domain"] + K_DR = 0x0, + #[doc = "Use hard-coded RTL key K_PRTL"] + K_PRTL = 0x01, + #[doc = "Use provided session key"] + SESSION = 0x02, + _RESERVED_3 = 0x03, + } + impl HostCryptokeySel { + #[inline(always)] + pub const fn from_bits(val: u8) -> HostCryptokeySel { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for HostCryptokeySel { + #[inline(always)] + fn from(val: u8) -> HostCryptokeySel { + HostCryptokeySel::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: HostCryptokeySel) -> u8 { + HostCryptokeySel::to_bits(val) + } + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct HostIotKdr0(pub u32); + impl HostIotKdr0 { + #[doc = "Read: 128 bits K_DR key value is not yet retained in the CRYPTOCELL AO power domain."] + pub const NOT_RETAINED: Self = Self(0x0); + #[doc = "Read: 128 bits K_DR key value is successfully retained in the CRYPTOCELL AO power domain."] + pub const RETAINED: Self = Self(0x01); + } + impl HostIotKdr0 { + pub const fn from_bits(val: u32) -> HostIotKdr0 { + Self(val & 0xffff_ffff) + } + pub const fn to_bits(self) -> u32 { + self.0 + } + } + impl From for HostIotKdr0 { + #[inline(always)] + fn from(val: u32) -> HostIotKdr0 { + HostIotKdr0::from_bits(val) + } + } + impl From for u32 { + #[inline(always)] + fn from(val: HostIotKdr0) -> u32 { + HostIotKdr0::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum Lcs { + #[doc = "CC310 operates in debug mode"] + DEBUG_ENABLE = 0x0, + _RESERVED_1 = 0x01, + #[doc = "CC310 operates in secure mode"] + SECURE = 0x02, + _RESERVED_3 = 0x03, + _RESERVED_4 = 0x04, + _RESERVED_5 = 0x05, + _RESERVED_6 = 0x06, + _RESERVED_7 = 0x07, + } + impl Lcs { + #[inline(always)] + pub const fn from_bits(val: u8) -> Lcs { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for Lcs { + #[inline(always)] + fn from(val: u8) -> Lcs { + Lcs::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: Lcs) -> u8 { + Lcs::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum MemToDinMask { + #[doc = "Do not mask memory to DIN DMA done interrupt i.e. interrupt is generated"] + IRQENABLE = 0x0, + #[doc = "Mask memory to DIN DMA done interrupt i.e. no interrupt is generated"] + IRQDISABLE = 0x01, + } + impl MemToDinMask { + #[inline(always)] + pub const fn from_bits(val: u8) -> MemToDinMask { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for MemToDinMask { + #[inline(always)] + fn from(val: u8) -> MemToDinMask { + MemToDinMask::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: MemToDinMask) -> u8 { + MemToDinMask::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum PkaMask { + #[doc = "Do not mask PKA end of operation interrupt i.e. interrupt is generated"] + IRQENABLE = 0x0, + #[doc = "Mask PKA end of operation interrupt i.e. no interrupt is generated"] + IRQDISABLE = 0x01, + } + impl PkaMask { + #[inline(always)] + pub const fn from_bits(val: u8) -> PkaMask { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for PkaMask { + #[inline(always)] + fn from(val: u8) -> PkaMask { + PkaMask::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: PkaMask) -> u8 { + PkaMask::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum RngMask { + #[doc = "Do not mask RNG interrupt i.e. interrupt is generated"] + IRQENABLE = 0x0, + #[doc = "Mask RNG interrupt i.e. no interrupt is generated"] + IRQDISABLE = 0x01, + } + impl RngMask { + #[inline(always)] + pub const fn from_bits(val: u8) -> RngMask { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for RngMask { + #[inline(always)] + fn from(val: u8) -> RngMask { + RngMask::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: RngMask) -> u8 { + RngMask::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum SramToDinMask { + #[doc = "Do not mask RNG SRAM to DIN DMA done interrupt i.e. interrupt is generated"] + IRQENABLE = 0x0, + #[doc = "Mask RNG SRAM to DIN DMA done interrupt i.e. no interrupt is generated"] + IRQDISABLE = 0x01, + } + impl SramToDinMask { + #[inline(always)] + pub const fn from_bits(val: u8) -> SramToDinMask { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for SramToDinMask { + #[inline(always)] + fn from(val: u8) -> SramToDinMask { + SramToDinMask::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: SramToDinMask) -> u8 { + SramToDinMask::to_bits(val) + } + } + } +} +pub mod cc_misc { + #[doc = "CRYPTOCELL MISC interface"] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct CcMisc { + ptr: *mut u8, + } + unsafe impl Send for CcMisc {} + unsafe impl Sync for CcMisc {} + impl CcMisc { + #[inline(always)] + pub const unsafe fn from_ptr(ptr: *mut ()) -> Self { + Self { ptr: ptr as _ } + } + #[inline(always)] + pub const fn as_ptr(&self) -> *mut () { + self.ptr as _ + } + #[doc = "Clock control for the AES engine."] + #[inline(always)] + pub const fn aes_clk(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0810usize) as _) } + } + #[doc = "Clock control for the HASH engine."] + #[inline(always)] + pub const fn hash_clk(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0818usize) as _) } + } + #[doc = "Clock control for the PKA engine."] + #[inline(always)] + pub const fn pka_clk(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x081cusize) as _) } + } + #[doc = "Clock control for the DMA engines."] + #[inline(always)] + pub const fn dma_clk(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0820usize) as _) } + } + #[doc = "CRYPTOCELL clocks status register."] + #[inline(always)] + pub const fn clk_status(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0824usize) as _) } + } + #[doc = "Clock control for the CHACHA engine."] + #[inline(always)] + pub const fn chacha_clk(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0858usize) as _) } + } + } + pub mod regs { + #[doc = "Clock control for the AES engine."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct AesClk(pub u32); + impl AesClk { + #[doc = "Enables clock for the AES engine."] + #[inline(always)] + pub const fn enable(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Enables clock for the AES engine."] + #[inline(always)] + pub fn set_enable(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + } + impl Default for AesClk { + #[inline(always)] + fn default() -> AesClk { + AesClk(0) + } + } + #[doc = "Clock control for the CHACHA engine."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct ChachaClk(pub u32); + impl ChachaClk { + #[doc = "Enables clock for the CHACHA engine."] + #[inline(always)] + pub const fn enable(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Enables clock for the CHACHA engine."] + #[inline(always)] + pub fn set_enable(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + } + impl Default for ChachaClk { + #[inline(always)] + fn default() -> ChachaClk { + ChachaClk(0) + } + } + #[doc = "CRYPTOCELL clocks status register."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct ClkStatus(pub u32); + impl ClkStatus { + #[doc = "Status of AES engine clock."] + #[inline(always)] + pub const fn aes_clk(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Status of AES engine clock."] + #[inline(always)] + pub fn set_aes_clk(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Status of HASH engine clock."] + #[inline(always)] + pub const fn hash_clk(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Status of HASH engine clock."] + #[inline(always)] + pub fn set_hash_clk(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Status of PKA engine clock."] + #[inline(always)] + pub const fn pka_clk(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Status of PKA engine clock."] + #[inline(always)] + pub fn set_pka_clk(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "Status of CHACHA engine clock."] + #[inline(always)] + pub const fn chacha_clk(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Status of CHACHA engine clock."] + #[inline(always)] + pub fn set_chacha_clk(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "Status of DMA engines clock."] + #[inline(always)] + pub const fn dma_clk(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Status of DMA engines clock."] + #[inline(always)] + pub fn set_dma_clk(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + } + impl Default for ClkStatus { + #[inline(always)] + fn default() -> ClkStatus { + ClkStatus(0) + } + } + #[doc = "Clock control for the DMA engines."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct DmaClk(pub u32); + impl DmaClk { + #[doc = "Enables clock for the DMA engines."] + #[inline(always)] + pub const fn enable(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Enables clock for the DMA engines."] + #[inline(always)] + pub fn set_enable(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + } + impl Default for DmaClk { + #[inline(always)] + fn default() -> DmaClk { + DmaClk(0) + } + } + #[doc = "Clock control for the HASH engine."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct HashClk(pub u32); + impl HashClk { + #[doc = "Enables clock for the HASH engine."] + #[inline(always)] + pub const fn enable(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Enables clock for the HASH engine."] + #[inline(always)] + pub fn set_enable(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + } + impl Default for HashClk { + #[inline(always)] + fn default() -> HashClk { + HashClk(0) + } + } + #[doc = "Clock control for the PKA engine."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct PkaClk(pub u32); + impl PkaClk { + #[doc = "Enables clock for the PKA engine."] + #[inline(always)] + pub const fn enable(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Enables clock for the PKA engine."] + #[inline(always)] + pub fn set_enable(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + } + impl Default for PkaClk { + #[inline(always)] + fn default() -> PkaClk { + PkaClk(0) + } + } + } +} +pub mod cc_pka { + #[doc = "CRYPTOCELL PKA engine"] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct CcPka { + ptr: *mut u8, + } + unsafe impl Send for CcPka {} + unsafe impl Sync for CcPka {} + impl CcPka { + #[inline(always)] + pub const unsafe fn from_ptr(ptr: *mut ()) -> Self { + Self { ptr: ptr as _ } + } + #[inline(always)] + pub const fn as_ptr(&self) -> *mut () { + self.ptr as _ + } + #[doc = "Description collection: Register for mapping the virtual register R\\[n\\] to a physical address in the PKA SRAM."] + #[inline(always)] + pub const fn memory_map( + self, + n: usize, + ) -> crate::common::Reg { + assert!(n < 32usize); + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize + n * 4usize) as _) } + } + #[doc = "Operation code to be executed by the PKA engine. Writing to this register triggers the PKA operation."] + #[inline(always)] + pub const fn opcode(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x80usize) as _) } + } + #[doc = "This register defines the N, Np, T0, and T1 virtual register index."] + #[inline(always)] + pub const fn n_np_t0_t1_addr( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x84usize) as _) } + } + #[doc = "This register holds the status for the PKA pipeline."] + #[inline(always)] + pub const fn pka_status(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x88usize) as _) } + } + #[doc = "Reset the PKA engine."] + #[inline(always)] + pub const fn pka_sw_reset(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x8cusize) as _) } + } + #[doc = "Description collection: This register holds the operands bit size."] + #[inline(always)] + pub const fn pka_l(self, n: usize) -> crate::common::Reg { + assert!(n < 8usize); + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x90usize + n * 4usize) as _) } + } + #[doc = "Status register indicating if the PKA pipeline is ready to receive a new OPCODE."] + #[inline(always)] + pub const fn pka_pipe(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xb0usize) as _) } + } + #[doc = "Status register indicating if the PKA operation has been completed."] + #[inline(always)] + pub const fn pka_done(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xb4usize) as _) } + } + #[doc = "PKA engine HW version. Reset value holds the version."] + #[inline(always)] + pub const fn pka_version(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xc4usize) as _) } + } + #[doc = "Start address in PKA SRAM for subsequent write transactions."] + #[inline(always)] + pub const fn pka_sram_waddr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xd4usize) as _) } + } + #[doc = "Write data to PKA SRAM. Writing to this register triggers a DMA transaction writing data into PKA SRAM. The DMA address offset is automatically incremented during write."] + #[inline(always)] + pub const fn pka_sram_wdata(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xd8usize) as _) } + } + #[doc = "Read data from PKA SRAM. Reading from this register triggers a DMA transaction read data from PKA SRAM. The DMA address offset is automatically incremented during read."] + #[inline(always)] + pub const fn pka_sram_rdata(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xdcusize) as _) } + } + #[doc = "Register for clearing PKA SRAM write buffer."] + #[inline(always)] + pub const fn pka_sram_wclear(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xe0usize) as _) } + } + #[doc = "Start address in PKA SRAM for subsequent read transactions."] + #[inline(always)] + pub const fn pka_sram_raddr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xe4usize) as _) } + } + } + pub mod regs { + #[doc = "Description collection: Register for mapping the virtual register R\\[n\\] to a physical address in the PKA SRAM."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct MemoryMap(pub u32); + impl MemoryMap { + #[doc = "The physical word address used for the virtual register."] + #[inline(always)] + pub const fn addr(&self) -> u16 { + let val = (self.0 >> 1usize) & 0x01ff; + val as u16 + } + #[doc = "The physical word address used for the virtual register."] + #[inline(always)] + pub fn set_addr(&mut self, val: u16) { + self.0 = (self.0 & !(0x01ff << 1usize)) | (((val as u32) & 0x01ff) << 1usize); + } + } + impl Default for MemoryMap { + #[inline(always)] + fn default() -> MemoryMap { + MemoryMap(0) + } + } + #[doc = "This register defines the N, Np, T0, and T1 virtual register index."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct NNpT0T1Addr(pub u32); + impl NNpT0T1Addr { + #[doc = "Register N virtual register index. Default is R0."] + #[inline(always)] + pub const fn n_virtual_addr(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x1f; + val as u8 + } + #[doc = "Register N virtual register index. Default is R0."] + #[inline(always)] + pub fn set_n_virtual_addr(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize); + } + #[doc = "Register Np virtual register index. Default is R1."] + #[inline(always)] + pub const fn np_virtual_addr(&self) -> u8 { + let val = (self.0 >> 5usize) & 0x1f; + val as u8 + } + #[doc = "Register Np virtual register index. Default is R1."] + #[inline(always)] + pub fn set_np_virtual_addr(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 5usize)) | (((val as u32) & 0x1f) << 5usize); + } + #[doc = "Temporary register 0 virtual register index. Default is R30."] + #[inline(always)] + pub const fn t0_virtual_addr(&self) -> u8 { + let val = (self.0 >> 10usize) & 0x1f; + val as u8 + } + #[doc = "Temporary register 0 virtual register index. Default is R30."] + #[inline(always)] + pub fn set_t0_virtual_addr(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 10usize)) | (((val as u32) & 0x1f) << 10usize); + } + #[doc = "Temporary register 1 virtual register index. Default is R31."] + #[inline(always)] + pub const fn t1_virtual_addr(&self) -> u8 { + let val = (self.0 >> 15usize) & 0x1f; + val as u8 + } + #[doc = "Temporary register 1 virtual register index. Default is R31."] + #[inline(always)] + pub fn set_t1_virtual_addr(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 15usize)) | (((val as u32) & 0x1f) << 15usize); + } + } + impl Default for NNpT0T1Addr { + #[inline(always)] + fn default() -> NNpT0T1Addr { + NNpT0T1Addr(0) + } + } + #[doc = "Operation code to be executed by the PKA engine. Writing to this register triggers the PKA operation."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Opcode(pub u32); + impl Opcode { + #[doc = "Holds the operation tag or the operand C virtual register index."] + #[inline(always)] + pub const fn tag(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x3f; + val as u8 + } + #[doc = "Holds the operation tag or the operand C virtual register index."] + #[inline(always)] + pub fn set_tag(&mut self, val: u8) { + self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize); + } + #[doc = "Result register virtual register index."] + #[inline(always)] + pub const fn reg_r(&self) -> u8 { + let val = (self.0 >> 6usize) & 0x1f; + val as u8 + } + #[doc = "Result register virtual register index."] + #[inline(always)] + pub fn set_reg_r(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 6usize)) | (((val as u32) & 0x1f) << 6usize); + } + #[doc = "This field controls the interpretation of REG_R."] + #[inline(always)] + pub const fn discard_r(&self) -> super::vals::DiscardR { + let val = (self.0 >> 11usize) & 0x01; + super::vals::DiscardR::from_bits(val as u8) + } + #[doc = "This field controls the interpretation of REG_R."] + #[inline(always)] + pub fn set_discard_r(&mut self, val: super::vals::DiscardR) { + self.0 = + (self.0 & !(0x01 << 11usize)) | (((val.to_bits() as u32) & 0x01) << 11usize); + } + #[doc = "Operand B virtual register index."] + #[inline(always)] + pub const fn reg_b(&self) -> u8 { + let val = (self.0 >> 12usize) & 0x1f; + val as u8 + } + #[doc = "Operand B virtual register index."] + #[inline(always)] + pub fn set_reg_b(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 12usize)) | (((val as u32) & 0x1f) << 12usize); + } + #[doc = "This field controls the interpretation of REG_B."] + #[inline(always)] + pub const fn const_b(&self) -> super::vals::ConstB { + let val = (self.0 >> 17usize) & 0x01; + super::vals::ConstB::from_bits(val as u8) + } + #[doc = "This field controls the interpretation of REG_B."] + #[inline(always)] + pub fn set_const_b(&mut self, val: super::vals::ConstB) { + self.0 = + (self.0 & !(0x01 << 17usize)) | (((val.to_bits() as u32) & 0x01) << 17usize); + } + #[doc = "Operand A virtual register index."] + #[inline(always)] + pub const fn reg_a(&self) -> u8 { + let val = (self.0 >> 18usize) & 0x1f; + val as u8 + } + #[doc = "Operand A virtual register index."] + #[inline(always)] + pub fn set_reg_a(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 18usize)) | (((val as u32) & 0x1f) << 18usize); + } + #[doc = "This field controls the interpretation of REG_A."] + #[inline(always)] + pub const fn const_a(&self) -> super::vals::ConstA { + let val = (self.0 >> 23usize) & 0x01; + super::vals::ConstA::from_bits(val as u8) + } + #[doc = "This field controls the interpretation of REG_A."] + #[inline(always)] + pub fn set_const_a(&mut self, val: super::vals::ConstA) { + self.0 = + (self.0 & !(0x01 << 23usize)) | (((val.to_bits() as u32) & 0x01) << 23usize); + } + #[doc = "The length of the operands. This value serves as an PKA length register index. E.g.: if LEN field value is set to 0, PKA_L\\[0\\] holds the size of the operands."] + #[inline(always)] + pub const fn len(&self) -> u8 { + let val = (self.0 >> 24usize) & 0x07; + val as u8 + } + #[doc = "The length of the operands. This value serves as an PKA length register index. E.g.: if LEN field value is set to 0, PKA_L\\[0\\] holds the size of the operands."] + #[inline(always)] + pub fn set_len(&mut self, val: u8) { + self.0 = (self.0 & !(0x07 << 24usize)) | (((val as u32) & 0x07) << 24usize); + } + #[doc = "Operation code to be executed by the PKA engine"] + #[inline(always)] + pub const fn opcode(&self) -> super::vals::Opcode { + let val = (self.0 >> 27usize) & 0x1f; + super::vals::Opcode::from_bits(val as u8) + } + #[doc = "Operation code to be executed by the PKA engine"] + #[inline(always)] + pub fn set_opcode(&mut self, val: super::vals::Opcode) { + self.0 = + (self.0 & !(0x1f << 27usize)) | (((val.to_bits() as u32) & 0x1f) << 27usize); + } + } + impl Default for Opcode { + #[inline(always)] + fn default() -> Opcode { + Opcode(0) + } + } + #[doc = "Status register indicating if the PKA operation has been completed."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct PkaDone(pub u32); + impl PkaDone { + #[doc = "PKA operation status."] + #[inline(always)] + pub const fn status(&self) -> super::vals::PkaDoneStatus { + let val = (self.0 >> 0usize) & 0x01; + super::vals::PkaDoneStatus::from_bits(val as u8) + } + #[doc = "PKA operation status."] + #[inline(always)] + pub fn set_status(&mut self, val: super::vals::PkaDoneStatus) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); + } + } + impl Default for PkaDone { + #[inline(always)] + fn default() -> PkaDone { + PkaDone(0) + } + } + #[doc = "Description collection: This register holds the operands bit size."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct PkaL(pub u32); + impl PkaL { + #[doc = "Operand bit size."] + #[inline(always)] + pub const fn op_size(&self) -> u16 { + let val = (self.0 >> 0usize) & 0x1fff; + val as u16 + } + #[doc = "Operand bit size."] + #[inline(always)] + pub fn set_op_size(&mut self, val: u16) { + self.0 = (self.0 & !(0x1fff << 0usize)) | (((val as u32) & 0x1fff) << 0usize); + } + } + impl Default for PkaL { + #[inline(always)] + fn default() -> PkaL { + PkaL(0) + } + } + #[doc = "Status register indicating if the PKA pipeline is ready to receive a new OPCODE."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct PkaPipe(pub u32); + impl PkaPipe { + #[doc = "PKA pipeline status."] + #[inline(always)] + pub const fn status(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "PKA pipeline status."] + #[inline(always)] + pub fn set_status(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + } + impl Default for PkaPipe { + #[inline(always)] + fn default() -> PkaPipe { + PkaPipe(0) + } + } + #[doc = "This register holds the status for the PKA pipeline."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct PkaStatus(pub u32); + impl PkaStatus { + #[doc = "The most significant 4-bits of the operand updated in shift operation."] + #[inline(always)] + pub const fn alu_msb_4bits(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x0f; + val as u8 + } + #[doc = "The most significant 4-bits of the operand updated in shift operation."] + #[inline(always)] + pub fn set_alu_msb_4bits(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + } + #[doc = "The least significant 4-bits of the operand updated in shift operation."] + #[inline(always)] + pub const fn alu_lsb_4bits(&self) -> u8 { + let val = (self.0 >> 4usize) & 0x0f; + val as u8 + } + #[doc = "The least significant 4-bits of the operand updated in shift operation."] + #[inline(always)] + pub fn set_alu_lsb_4bits(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize); + } + #[doc = "Indicates the MSB sign of the last operation."] + #[inline(always)] + pub const fn alu_sign_out(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Indicates the MSB sign of the last operation."] + #[inline(always)] + pub fn set_alu_sign_out(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Holds the carry of the last ALU operation."] + #[inline(always)] + pub const fn alu_carry(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "Holds the carry of the last ALU operation."] + #[inline(always)] + pub fn set_alu_carry(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "Holds the carry of the last modular operation."] + #[inline(always)] + pub const fn alu_carry_mod(&self) -> bool { + let val = (self.0 >> 10usize) & 0x01; + val != 0 + } + #[doc = "Holds the carry of the last modular operation."] + #[inline(always)] + pub fn set_alu_carry_mod(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); + } + #[doc = "Indicates the last subtraction operation sign."] + #[inline(always)] + pub const fn alu_sub_is_zero(&self) -> bool { + let val = (self.0 >> 11usize) & 0x01; + val != 0 + } + #[doc = "Indicates the last subtraction operation sign."] + #[inline(always)] + pub fn set_alu_sub_is_zero(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); + } + #[doc = "Indicates if the result of ALU OUT is zero."] + #[inline(always)] + pub const fn alu_out_zero(&self) -> bool { + let val = (self.0 >> 12usize) & 0x01; + val != 0 + } + #[doc = "Indicates if the result of ALU OUT is zero."] + #[inline(always)] + pub fn set_alu_out_zero(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); + } + #[doc = "Modular overflow flag."] + #[inline(always)] + pub const fn alu_modovrflw(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "Modular overflow flag."] + #[inline(always)] + pub fn set_alu_modovrflw(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + #[doc = "Indication if the division is done by zero."] + #[inline(always)] + pub const fn div_by_zero(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "Indication if the division is done by zero."] + #[inline(always)] + pub fn set_div_by_zero(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } + #[doc = "Indicates the modular inverse of zero."] + #[inline(always)] + pub const fn modinv_of_zero(&self) -> bool { + let val = (self.0 >> 15usize) & 0x01; + val != 0 + } + #[doc = "Indicates the modular inverse of zero."] + #[inline(always)] + pub fn set_modinv_of_zero(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); + } + #[doc = "Opcode of the last operation"] + #[inline(always)] + pub const fn opcode(&self) -> u8 { + let val = (self.0 >> 16usize) & 0x1f; + val as u8 + } + #[doc = "Opcode of the last operation"] + #[inline(always)] + pub fn set_opcode(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 16usize)) | (((val as u32) & 0x1f) << 16usize); + } + } + impl Default for PkaStatus { + #[inline(always)] + fn default() -> PkaStatus { + PkaStatus(0) + } + } + #[doc = "Reset the PKA engine."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct PkaSwReset(pub u32); + impl PkaSwReset { + #[doc = "Writing any value to this address resets the PKA engine. The reset takes 4 CPU clock cycles to complete."] + #[inline(always)] + pub const fn reset(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Writing any value to this address resets the PKA engine. The reset takes 4 CPU clock cycles to complete."] + #[inline(always)] + pub fn set_reset(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + } + impl Default for PkaSwReset { + #[inline(always)] + fn default() -> PkaSwReset { + PkaSwReset(0) + } + } + } + pub mod vals { + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum ConstA { + #[doc = "REG_A is intepreted as a register index."] + REGISTER = 0x0, + #[doc = "REG_A is intepreted as a constant."] + CONSTANT = 0x01, + } + impl ConstA { + #[inline(always)] + pub const fn from_bits(val: u8) -> ConstA { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for ConstA { + #[inline(always)] + fn from(val: u8) -> ConstA { + ConstA::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: ConstA) -> u8 { + ConstA::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum ConstB { + #[doc = "REG_B is intepreted as a register index."] + REGISTER = 0x0, + #[doc = "REG_B is intepreted as a constant."] + CONSTANT = 0x01, + } + impl ConstB { + #[inline(always)] + pub const fn from_bits(val: u8) -> ConstB { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for ConstB { + #[inline(always)] + fn from(val: u8) -> ConstB { + ConstB::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: ConstB) -> u8 { + ConstB::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum DiscardR { + #[doc = "REG_R is intepreted as a register index."] + REGISTER = 0x0, + #[doc = "Result is discarded."] + DISCARD = 0x01, + } + impl DiscardR { + #[inline(always)] + pub const fn from_bits(val: u8) -> DiscardR { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for DiscardR { + #[inline(always)] + fn from(val: u8) -> DiscardR { + DiscardR::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: DiscardR) -> u8 { + DiscardR::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum Opcode { + #[doc = "Terminate operation"] + TERMINATE = 0x0, + _RESERVED_1 = 0x01, + _RESERVED_2 = 0x02, + _RESERVED_3 = 0x03, + #[doc = "Add or Increment"] + ADD_INC = 0x04, + #[doc = "Subtract, Decrement, or Negate"] + SUB_DEC_NEG = 0x05, + #[doc = "Modular Add or Modular Increment"] + MOD_ADD_INC = 0x06, + #[doc = "Modular Subtract, Modular Decrement, or Modular Negate"] + MOD_SUB_DEC_NEG = 0x07, + #[doc = "Perform AND, test, or clear"] + ANDTST0CLR0 = 0x08, + #[doc = "Perform OR, copy, or set bits"] + ORCOPYSET0 = 0x09, + #[doc = "Perform XOR, flip bits, invert, or compare"] + XORFLP0INVCMP = 0x0a, + _RESERVED_b = 0x0b, + #[doc = "Shift right 0 operation"] + SHR0 = 0x0c, + #[doc = "Shift right 1 operation"] + SHR1 = 0x0d, + #[doc = "Shift left 0 operation"] + SHL0 = 0x0e, + #[doc = "Shift left 1 operation"] + SHL1 = 0x0f, + #[doc = "Multiply low operation"] + MUL_LOW = 0x10, + #[doc = "Modular multiply operation"] + MOD_MUL = 0x11, + #[doc = "Modular multiply N operation"] + MOD_MUL_N = 0x12, + #[doc = "Modular exponentiation operation"] + MOD_EXP = 0x13, + #[doc = "Division operation"] + DIVISION = 0x14, + #[doc = "Modular inversion operation"] + MOD_INV = 0x15, + #[doc = "Modular division operation"] + MOD_DIV = 0x16, + #[doc = "Multiply high operation"] + MUL_HIGH = 0x17, + #[doc = "Modular multiplication acceleration"] + MOD_MLAC = 0x18, + #[doc = "Modular multiplication acceleration where final reduction is omitted"] + MOD_MLACNR = 0x19, + _RESERVED_1a = 0x1a, + #[doc = "Reduction operation"] + REDUCTION = 0x1b, + _RESERVED_1c = 0x1c, + _RESERVED_1d = 0x1d, + _RESERVED_1e = 0x1e, + _RESERVED_1f = 0x1f, + } + impl Opcode { + #[inline(always)] + pub const fn from_bits(val: u8) -> Opcode { + unsafe { core::mem::transmute(val & 0x1f) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for Opcode { + #[inline(always)] + fn from(val: u8) -> Opcode { + Opcode::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: Opcode) -> u8 { + Opcode::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum PkaDoneStatus { + #[doc = "PKA operation is processing"] + PROCESSING = 0x0, + #[doc = "PKA operation is completed and pipeline is empty"] + COMPLETED = 0x01, + } + impl PkaDoneStatus { + #[inline(always)] + pub const fn from_bits(val: u8) -> PkaDoneStatus { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for PkaDoneStatus { + #[inline(always)] + fn from(val: u8) -> PkaDoneStatus { + PkaDoneStatus::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: PkaDoneStatus) -> u8 { + PkaDoneStatus::to_bits(val) + } + } + } +} +pub mod cc_rng { + #[doc = "CRYPTOCELL RNG engine"] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct CcRng { + ptr: *mut u8, + } + unsafe impl Send for CcRng {} + unsafe impl Sync for CcRng {} + impl CcRng { + #[inline(always)] + pub const unsafe fn from_ptr(ptr: *mut ()) -> Self { + Self { ptr: ptr as _ } + } + #[inline(always)] + pub const fn as_ptr(&self) -> *mut () { + self.ptr as _ + } + #[doc = "Interrupt mask register. Each bit of this register holds the mask of a single interrupt source."] + #[inline(always)] + pub const fn rng_imr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0100usize) as _) } + } + #[doc = "Interrupt status register. Each bit of this register holds the interrupt status of a single interrupt source. If corresponding RNG_IMR bit is unmasked, an interrupt is generated."] + #[inline(always)] + pub const fn rng_isr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0104usize) as _) } + } + #[doc = "Interrupt clear register. Writing a 1 bit into a field in this register will clear the corresponding bit in RNG_ISR."] + #[inline(always)] + pub const fn rng_icr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0108usize) as _) } + } + #[doc = "TRNG ring oscillator length configuration"] + #[inline(always)] + pub const fn trng_config(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x010cusize) as _) } + } + #[doc = "This register indicates if TRNG entropy collection is valid."] + #[inline(always)] + pub const fn trng_valid(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0110usize) as _) } + } + #[doc = "Description collection: The entropy holding registers (EHR) hold 192-bits random data collected by the TRNG. The initial EHR_DATA\\[0\\] register holds the least significant bits \\[31:0\\] of the random data value."] + #[inline(always)] + pub const fn ehr_data(self, n: usize) -> crate::common::Reg { + assert!(n < 6usize); + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0114usize + n * 4usize) as _) } + } + #[doc = "This register controls the ring oscillator circuit used as a noise source."] + #[inline(always)] + pub const fn noise_source( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x012cusize) as _) } + } + #[doc = "Sample count defining the number of CPU clock cycles between two consecutive noise source samples."] + #[inline(always)] + pub const fn sample_cnt(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0130usize) as _) } + } + #[doc = "Statistics counter for autocorrelation test activations. Statistics collection is stopped if one of the counters reach its limit of all ones."] + #[inline(always)] + pub const fn autocorr_statistic( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0134usize) as _) } + } + #[doc = "Debug register for the TRNG. This register is used to bypass TRNG tests in hardware."] + #[inline(always)] + pub const fn trng_debug(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0138usize) as _) } + } + #[doc = "Reset the RNG engine."] + #[inline(always)] + pub const fn rng_sw_reset(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0140usize) as _) } + } + #[doc = "Status register for RNG engine activity."] + #[inline(always)] + pub const fn rng_busy(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x01b8usize) as _) } + } + #[doc = "Reset the TRNG, including internal counter of collected bits and registers EHR_DATA and TRNG_VALID."] + #[inline(always)] + pub const fn trng_reset(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x01bcusize) as _) } + } + #[doc = "Hardware configuration of RNG engine. Reset value holds the supported features."] + #[inline(always)] + pub const fn rng_hw_flags(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x01c0usize) as _) } + } + #[doc = "Control clock for the RNG engine."] + #[inline(always)] + pub const fn rng_clk(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x01c4usize) as _) } + } + #[doc = "Writing to this register enables the RNG DMA engine."] + #[inline(always)] + pub const fn rng_dma(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x01c8usize) as _) } + } + #[doc = "This register defines which ring oscillator length configuration should be used when using the RNG DMA engine."] + #[inline(always)] + pub const fn rng_dma_rosc_len( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x01ccusize) as _) } + } + #[doc = "This register defines the start address in TRNG SRAM for the TRNG data to be collected by the RNG DMA engine."] + #[inline(always)] + pub const fn rng_dma_sram_addr( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x01d0usize) as _) } + } + #[doc = "This register defines the number of 192-bits samples that the RNG DMA engine collects per run."] + #[inline(always)] + pub const fn rng_dma_samples_num( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x01d4usize) as _) } + } + #[doc = "This register defines the maximum number of CPU clock cycles per TRNG collection of 192-bits samples. If the number of cycles for a collection exceeds this threshold the WATCHDOG interrupt is triggered."] + #[inline(always)] + pub const fn rng_watchdog_val(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x01d8usize) as _) } + } + #[doc = "Status register for RNG DMA engine activity."] + #[inline(always)] + pub const fn rng_dma_busy(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x01dcusize) as _) } + } + } + pub mod regs { + #[doc = "Statistics counter for autocorrelation test activations. Statistics collection is stopped if one of the counters reach its limit of all ones."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct AutocorrStatistic(pub u32); + impl AutocorrStatistic { + #[doc = "Count each time an autocorrelation test starts. Any write to the field resets the counter."] + #[inline(always)] + pub const fn autocorr_trys(&self) -> u16 { + let val = (self.0 >> 0usize) & 0x3fff; + val as u16 + } + #[doc = "Count each time an autocorrelation test starts. Any write to the field resets the counter."] + #[inline(always)] + pub fn set_autocorr_trys(&mut self, val: u16) { + self.0 = (self.0 & !(0x3fff << 0usize)) | (((val as u32) & 0x3fff) << 0usize); + } + #[doc = "Count each time an autocorrelation test fails. Any write to the field resets the counter."] + #[inline(always)] + pub const fn autocorr_fails(&self) -> u8 { + let val = (self.0 >> 14usize) & 0xff; + val as u8 + } + #[doc = "Count each time an autocorrelation test fails. Any write to the field resets the counter."] + #[inline(always)] + pub fn set_autocorr_fails(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 14usize)) | (((val as u32) & 0xff) << 14usize); + } + } + impl Default for AutocorrStatistic { + #[inline(always)] + fn default() -> AutocorrStatistic { + AutocorrStatistic(0) + } + } + #[doc = "This register controls the ring oscillator circuit used as a noise source."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct NoiseSource(pub u32); + impl NoiseSource { + #[doc = "Enable or disable the noise source."] + #[inline(always)] + pub const fn enable(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Enable or disable the noise source."] + #[inline(always)] + pub fn set_enable(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + } + impl Default for NoiseSource { + #[inline(always)] + fn default() -> NoiseSource { + NoiseSource(0) + } + } + #[doc = "Status register for RNG engine activity."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct RngBusy(pub u32); + impl RngBusy { + #[doc = "RNG engine status."] + #[inline(always)] + pub const fn status(&self) -> super::vals::RngBusyStatus { + let val = (self.0 >> 0usize) & 0x01; + super::vals::RngBusyStatus::from_bits(val as u8) + } + #[doc = "RNG engine status."] + #[inline(always)] + pub fn set_status(&mut self, val: super::vals::RngBusyStatus) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); + } + #[doc = "TRNG status."] + #[inline(always)] + pub const fn trng_status(&self) -> super::vals::TrngStatus { + let val = (self.0 >> 1usize) & 0x01; + super::vals::TrngStatus::from_bits(val as u8) + } + #[doc = "TRNG status."] + #[inline(always)] + pub fn set_trng_status(&mut self, val: super::vals::TrngStatus) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val.to_bits() as u32) & 0x01) << 1usize); + } + } + impl Default for RngBusy { + #[inline(always)] + fn default() -> RngBusy { + RngBusy(0) + } + } + #[doc = "Control clock for the RNG engine."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct RngClk(pub u32); + impl RngClk { + #[doc = "Enables clock for the RNG engine."] + #[inline(always)] + pub const fn enable(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Enables clock for the RNG engine."] + #[inline(always)] + pub fn set_enable(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + } + impl Default for RngClk { + #[inline(always)] + fn default() -> RngClk { + RngClk(0) + } + } + #[doc = "Writing to this register enables the RNG DMA engine."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct RngDma(pub u32); + impl RngDma { + #[inline(always)] + pub const fn enable(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[inline(always)] + pub fn set_enable(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + } + impl Default for RngDma { + #[inline(always)] + fn default() -> RngDma { + RngDma(0) + } + } + #[doc = "Status register for RNG DMA engine activity."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct RngDmaBusy(pub u32); + impl RngDmaBusy { + #[doc = "RNG DMA engine status."] + #[inline(always)] + pub const fn status(&self) -> super::vals::RngDmaBusyStatus { + let val = (self.0 >> 0usize) & 0x01; + super::vals::RngDmaBusyStatus::from_bits(val as u8) + } + #[doc = "RNG DMA engine status."] + #[inline(always)] + pub fn set_status(&mut self, val: super::vals::RngDmaBusyStatus) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); + } + #[doc = "The active ring oscillator length configuration used by the RNG DMA engine."] + #[inline(always)] + pub const fn rosc_len(&self) -> super::vals::RngDmaBusyRoscLen { + let val = (self.0 >> 1usize) & 0x03; + super::vals::RngDmaBusyRoscLen::from_bits(val as u8) + } + #[doc = "The active ring oscillator length configuration used by the RNG DMA engine."] + #[inline(always)] + pub fn set_rosc_len(&mut self, val: super::vals::RngDmaBusyRoscLen) { + self.0 = (self.0 & !(0x03 << 1usize)) | (((val.to_bits() as u32) & 0x03) << 1usize); + } + #[doc = "Number of samples already collected using the current ring oscillator configuration."] + #[inline(always)] + pub const fn num_of_samples(&self) -> u8 { + let val = (self.0 >> 3usize) & 0xff; + val as u8 + } + #[doc = "Number of samples already collected using the current ring oscillator configuration."] + #[inline(always)] + pub fn set_num_of_samples(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 3usize)) | (((val as u32) & 0xff) << 3usize); + } + } + impl Default for RngDmaBusy { + #[inline(always)] + fn default() -> RngDmaBusy { + RngDmaBusy(0) + } + } + #[doc = "This register defines which ring oscillator length configuration should be used when using the RNG DMA engine."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct RngDmaRoscLen(pub u32); + impl RngDmaRoscLen { + #[doc = "Use shortest ROSC1 ring oscillator configuration."] + #[inline(always)] + pub const fn rosc1(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Use shortest ROSC1 ring oscillator configuration."] + #[inline(always)] + pub fn set_rosc1(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Use ROSC2 ring oscillator configuration."] + #[inline(always)] + pub const fn rosc2(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Use ROSC2 ring oscillator configuration."] + #[inline(always)] + pub fn set_rosc2(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Use ROSC3 ring oscillator configuration."] + #[inline(always)] + pub const fn rosc3(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Use ROSC3 ring oscillator configuration."] + #[inline(always)] + pub fn set_rosc3(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Use longest ROSC4 ring oscillator configuration."] + #[inline(always)] + pub const fn rosc4(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Use longest ROSC4 ring oscillator configuration."] + #[inline(always)] + pub fn set_rosc4(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + } + impl Default for RngDmaRoscLen { + #[inline(always)] + fn default() -> RngDmaRoscLen { + RngDmaRoscLen(0) + } + } + #[doc = "This register defines the number of 192-bits samples that the RNG DMA engine collects per run."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct RngDmaSamplesNum(pub u32); + impl RngDmaSamplesNum { + #[doc = "Defines the number of 192-bits samples that the DMA engine collects per run."] + #[inline(always)] + pub const fn rng_samples_num(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 + } + #[doc = "Defines the number of 192-bits samples that the DMA engine collects per run."] + #[inline(always)] + pub fn set_rng_samples_num(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); + } + } + impl Default for RngDmaSamplesNum { + #[inline(always)] + fn default() -> RngDmaSamplesNum { + RngDmaSamplesNum(0) + } + } + #[doc = "This register defines the start address in TRNG SRAM for the TRNG data to be collected by the RNG DMA engine."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct RngDmaSramAddr(pub u32); + impl RngDmaSramAddr { + #[doc = "Start address of the TRNG data in TRNG SRAM."] + #[inline(always)] + pub const fn rng_sram_dma_addr(&self) -> u16 { + let val = (self.0 >> 0usize) & 0x07ff; + val as u16 + } + #[doc = "Start address of the TRNG data in TRNG SRAM."] + #[inline(always)] + pub fn set_rng_sram_dma_addr(&mut self, val: u16) { + self.0 = (self.0 & !(0x07ff << 0usize)) | (((val as u32) & 0x07ff) << 0usize); + } + } + impl Default for RngDmaSramAddr { + #[inline(always)] + fn default() -> RngDmaSramAddr { + RngDmaSramAddr(0) + } + } + #[doc = "Hardware configuration of RNG engine. Reset value holds the supported features."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct RngHwFlags(pub u32); + impl RngHwFlags { + #[doc = "Data width supported by the entropy collector"] + #[inline(always)] + pub const fn ehr_width(&self) -> super::vals::EhrWidth { + let val = (self.0 >> 0usize) & 0x01; + super::vals::EhrWidth::from_bits(val as u8) + } + #[doc = "Data width supported by the entropy collector"] + #[inline(always)] + pub fn set_ehr_width(&mut self, val: super::vals::EhrWidth) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); + } + #[doc = "If this flag is set, the engine include support for continuous random number generator test."] + #[inline(always)] + pub const fn crngt_exists(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "If this flag is set, the engine include support for continuous random number generator test."] + #[inline(always)] + pub fn set_crngt_exists(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "If this flag is set, the engine include support for autocorrelation test."] + #[inline(always)] + pub const fn autocorr_exists(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "If this flag is set, the engine include support for autocorrelation test."] + #[inline(always)] + pub fn set_autocorr_exists(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "If this flag is set, the engine include support for bypassing TRNG tests."] + #[inline(always)] + pub const fn bypass_exists(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "If this flag is set, the engine include support for bypassing TRNG tests."] + #[inline(always)] + pub fn set_bypass_exists(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "If this flag is set, the engine include a pseudo-random number generator."] + #[inline(always)] + pub const fn prng_exists(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "If this flag is set, the engine include a pseudo-random number generator."] + #[inline(always)] + pub fn set_prng_exists(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "If this flag is set, the engine include support for known answer tests."] + #[inline(always)] + pub const fn kat_exists(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "If this flag is set, the engine include support for known answer tests."] + #[inline(always)] + pub fn set_kat_exists(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "If this flag is set, the engine include support for automatic reseeding."] + #[inline(always)] + pub const fn reseeding_exists(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "If this flag is set, the engine include support for automatic reseeding."] + #[inline(always)] + pub fn set_reseeding_exists(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[inline(always)] + pub const fn rng_use_5_sboxes(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[inline(always)] + pub fn set_rng_use_5_sboxes(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + } + impl Default for RngHwFlags { + #[inline(always)] + fn default() -> RngHwFlags { + RngHwFlags(0) + } + } + #[doc = "Interrupt clear register. Writing a 1 bit into a field in this register will clear the corresponding bit in RNG_ISR."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct RngIcr(pub u32); + impl RngIcr { + #[doc = "Writing value '1' clears corresponding bit in RNG_ISR"] + #[inline(always)] + pub const fn ehr_valid_clear(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Writing value '1' clears corresponding bit in RNG_ISR"] + #[inline(always)] + pub fn set_ehr_valid_clear(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Cannot be cleared by software! Only RNG reset clears this bit."] + #[inline(always)] + pub const fn autocorr_err_clear(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Cannot be cleared by software! Only RNG reset clears this bit."] + #[inline(always)] + pub fn set_autocorr_err_clear(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Writing value '1' clears corresponding bit in RNG_ISR"] + #[inline(always)] + pub const fn crngt_err_clear(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Writing value '1' clears corresponding bit in RNG_ISR"] + #[inline(always)] + pub fn set_crngt_err_clear(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Writing value '1' clears corresponding bit in RNG_ISR"] + #[inline(always)] + pub const fn vnc_err_clear(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Writing value '1' clears corresponding bit in RNG_ISR"] + #[inline(always)] + pub fn set_vnc_err_clear(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "Writing value '1' clears corresponding bit in RNG_ISR"] + #[inline(always)] + pub const fn watchdog_clear(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "Writing value '1' clears corresponding bit in RNG_ISR"] + #[inline(always)] + pub fn set_watchdog_clear(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "Writing value '1' clears corresponding bit in RNG_ISR"] + #[inline(always)] + pub const fn dma_done_clear(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Writing value '1' clears corresponding bit in RNG_ISR"] + #[inline(always)] + pub fn set_dma_done_clear(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + } + impl Default for RngIcr { + #[inline(always)] + fn default() -> RngIcr { + RngIcr(0) + } + } + #[doc = "Interrupt mask register. Each bit of this register holds the mask of a single interrupt source."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct RngImr(pub u32); + impl RngImr { + #[doc = "See RNG_ISR for explanation on this interrupt."] + #[inline(always)] + pub const fn ehr_valid_mask(&self) -> super::vals::EhrValidMask { + let val = (self.0 >> 0usize) & 0x01; + super::vals::EhrValidMask::from_bits(val as u8) + } + #[doc = "See RNG_ISR for explanation on this interrupt."] + #[inline(always)] + pub fn set_ehr_valid_mask(&mut self, val: super::vals::EhrValidMask) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); + } + #[doc = "See RNG_ISR for explanation on this interrupt."] + #[inline(always)] + pub const fn autocorr_err_mask(&self) -> super::vals::AutocorrErrMask { + let val = (self.0 >> 1usize) & 0x01; + super::vals::AutocorrErrMask::from_bits(val as u8) + } + #[doc = "See RNG_ISR for explanation on this interrupt."] + #[inline(always)] + pub fn set_autocorr_err_mask(&mut self, val: super::vals::AutocorrErrMask) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val.to_bits() as u32) & 0x01) << 1usize); + } + #[doc = "See RNG_ISR for explanation on this interrupt."] + #[inline(always)] + pub const fn crngt_err_mask(&self) -> super::vals::CrngtErrMask { + let val = (self.0 >> 2usize) & 0x01; + super::vals::CrngtErrMask::from_bits(val as u8) + } + #[doc = "See RNG_ISR for explanation on this interrupt."] + #[inline(always)] + pub fn set_crngt_err_mask(&mut self, val: super::vals::CrngtErrMask) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val.to_bits() as u32) & 0x01) << 2usize); + } + #[doc = "See RNG_ISR for explanation on this interrupt."] + #[inline(always)] + pub const fn vnc_err_mask(&self) -> super::vals::VncErrMask { + let val = (self.0 >> 3usize) & 0x01; + super::vals::VncErrMask::from_bits(val as u8) + } + #[doc = "See RNG_ISR for explanation on this interrupt."] + #[inline(always)] + pub fn set_vnc_err_mask(&mut self, val: super::vals::VncErrMask) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val.to_bits() as u32) & 0x01) << 3usize); + } + #[doc = "See RNG_ISR for explanation on this interrupt."] + #[inline(always)] + pub const fn watchdog_mask(&self) -> super::vals::WatchdogMask { + let val = (self.0 >> 4usize) & 0x01; + super::vals::WatchdogMask::from_bits(val as u8) + } + #[doc = "See RNG_ISR for explanation on this interrupt."] + #[inline(always)] + pub fn set_watchdog_mask(&mut self, val: super::vals::WatchdogMask) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val.to_bits() as u32) & 0x01) << 4usize); + } + #[doc = "See RNG_ISR for explanation on this interrupt."] + #[inline(always)] + pub const fn dma_done_mask(&self) -> super::vals::DmaDoneMask { + let val = (self.0 >> 5usize) & 0x01; + super::vals::DmaDoneMask::from_bits(val as u8) + } + #[doc = "See RNG_ISR for explanation on this interrupt."] + #[inline(always)] + pub fn set_dma_done_mask(&mut self, val: super::vals::DmaDoneMask) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val.to_bits() as u32) & 0x01) << 5usize); + } + } + impl Default for RngImr { + #[inline(always)] + fn default() -> RngImr { + RngImr(0) + } + } + #[doc = "Interrupt status register. Each bit of this register holds the interrupt status of a single interrupt source. If corresponding RNG_IMR bit is unmasked, an interrupt is generated."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct RngIsr(pub u32); + impl RngIsr { + #[doc = "192-bits have been collected and are ready to be read."] + #[inline(always)] + pub const fn ehr_valid_int(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "192-bits have been collected and are ready to be read."] + #[inline(always)] + pub fn set_ehr_valid_int(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Autocorrelation error. Failure occurs when autocorrelation test has failed four times in a row. Once set, the TRNG ceases to function until next reset."] + #[inline(always)] + pub const fn autocorr_err_int(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Autocorrelation error. Failure occurs when autocorrelation test has failed four times in a row. Once set, the TRNG ceases to function until next reset."] + #[inline(always)] + pub fn set_autocorr_err_int(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Continuous random number generator test error. Failure occurs when two consecutive blocks of 16 collected bits are equal."] + #[inline(always)] + pub const fn crngt_err_int(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Continuous random number generator test error. Failure occurs when two consecutive blocks of 16 collected bits are equal."] + #[inline(always)] + pub fn set_crngt_err_int(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "von Neumann corrector error. Failure occurs if 32 consecutive collected bits are identical, ZERO, or ONE."] + #[inline(always)] + pub const fn vnc_err_int(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "von Neumann corrector error. Failure occurs if 32 consecutive collected bits are identical, ZERO, or ONE."] + #[inline(always)] + pub fn set_vnc_err_int(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "Maximum number of CPU clock cycles per sample have been exceeded. See RNG_WATCHDOG_VAL for more information."] + #[inline(always)] + pub const fn watchdog_int(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "Maximum number of CPU clock cycles per sample have been exceeded. See RNG_WATCHDOG_VAL for more information."] + #[inline(always)] + pub fn set_watchdog_int(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "RNG DMA to SRAM is completed."] + #[inline(always)] + pub const fn dma_done_int(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "RNG DMA to SRAM is completed."] + #[inline(always)] + pub fn set_dma_done_int(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + } + impl Default for RngIsr { + #[inline(always)] + fn default() -> RngIsr { + RngIsr(0) + } + } + #[doc = "Reset the RNG engine."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct RngSwReset(pub u32); + impl RngSwReset { + #[doc = "Writing any value to this address resets the RNG engine. The reset takes 4 CPU clock cycles to complete."] + #[inline(always)] + pub const fn reset(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Writing any value to this address resets the RNG engine. The reset takes 4 CPU clock cycles to complete."] + #[inline(always)] + pub fn set_reset(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + } + impl Default for RngSwReset { + #[inline(always)] + fn default() -> RngSwReset { + RngSwReset(0) + } + } + #[doc = "TRNG ring oscillator length configuration"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct TrngConfig(pub u32); + impl TrngConfig { + #[doc = "Set the length of the oscillator ring (= the number of inverters) out of four possible configurations."] + #[inline(always)] + pub const fn rosc_len(&self) -> super::vals::TrngConfigRoscLen { + let val = (self.0 >> 0usize) & 0x03; + super::vals::TrngConfigRoscLen::from_bits(val as u8) + } + #[doc = "Set the length of the oscillator ring (= the number of inverters) out of four possible configurations."] + #[inline(always)] + pub fn set_rosc_len(&mut self, val: super::vals::TrngConfigRoscLen) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); + } + } + impl Default for TrngConfig { + #[inline(always)] + fn default() -> TrngConfig { + TrngConfig(0) + } + } + #[doc = "Debug register for the TRNG. This register is used to bypass TRNG tests in hardware."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct TrngDebug(pub u32); + impl TrngDebug { + #[doc = "Bypass the von Neumann corrector post-processing test, including the 32 consecutive bits test."] + #[inline(always)] + pub const fn vnc_bypass(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Bypass the von Neumann corrector post-processing test, including the 32 consecutive bits test."] + #[inline(always)] + pub fn set_vnc_bypass(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Bypass the Continuous Random Number Generator Test (CRNGT)."] + #[inline(always)] + pub const fn crngt_bypass(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Bypass the Continuous Random Number Generator Test (CRNGT)."] + #[inline(always)] + pub fn set_crngt_bypass(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Bypass the autocorrelation test."] + #[inline(always)] + pub const fn autocorr_bypass(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Bypass the autocorrelation test."] + #[inline(always)] + pub fn set_autocorr_bypass(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + } + impl Default for TrngDebug { + #[inline(always)] + fn default() -> TrngDebug { + TrngDebug(0) + } + } + #[doc = "Reset the TRNG, including internal counter of collected bits and registers EHR_DATA and TRNG_VALID."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct TrngReset(pub u32); + impl TrngReset { + #[doc = "Writing any value to this address resets the internal bits counter and registers EHR_DATA and TRNG_VALID. Register NOISE_SOURCE must be disabled in order for the reset to take place."] + #[inline(always)] + pub const fn reset(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Writing any value to this address resets the internal bits counter and registers EHR_DATA and TRNG_VALID. Register NOISE_SOURCE must be disabled in order for the reset to take place."] + #[inline(always)] + pub fn set_reset(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + } + impl Default for TrngReset { + #[inline(always)] + fn default() -> TrngReset { + TrngReset(0) + } + } + #[doc = "This register indicates if TRNG entropy collection is valid."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct TrngValid(pub u32); + impl TrngValid { + #[doc = "A value of 1 indicates that collection of bits in the TRNG is completed, and data can be read from EHR_DATA registers."] + #[inline(always)] + pub const fn ehr_data(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "A value of 1 indicates that collection of bits in the TRNG is completed, and data can be read from EHR_DATA registers."] + #[inline(always)] + pub fn set_ehr_data(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + } + impl Default for TrngValid { + #[inline(always)] + fn default() -> TrngValid { + TrngValid(0) + } + } + } + pub mod vals { + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum AutocorrErrMask { + #[doc = "Do not mask autocorrelation interrupt i.e. interrupt is generated"] + IRQENABLE = 0x0, + #[doc = "Mask autocorrelation interrupt i.e. no interrupt is generated"] + IRQDISABLE = 0x01, + } + impl AutocorrErrMask { + #[inline(always)] + pub const fn from_bits(val: u8) -> AutocorrErrMask { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for AutocorrErrMask { + #[inline(always)] + fn from(val: u8) -> AutocorrErrMask { + AutocorrErrMask::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: AutocorrErrMask) -> u8 { + AutocorrErrMask::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum CrngtErrMask { + #[doc = "Do not mask the CRNGT error interrupt i.e. interrupt is generated"] + IRQENABLE = 0x0, + #[doc = "Mask the CRNGT error interrupt i.e. no interrupt is generated"] + IRQDISABLE = 0x01, + } + impl CrngtErrMask { + #[inline(always)] + pub const fn from_bits(val: u8) -> CrngtErrMask { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for CrngtErrMask { + #[inline(always)] + fn from(val: u8) -> CrngtErrMask { + CrngtErrMask::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: CrngtErrMask) -> u8 { + CrngtErrMask::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum DmaDoneMask { + #[doc = "Do not mask the RNG DMA completion interrupt i.e. interrupt is generated"] + IRQENABLE = 0x0, + #[doc = "Mask the RNG DMA completion interrupt i.e. no interrupt is generated"] + IRQDISABLE = 0x01, + } + impl DmaDoneMask { + #[inline(always)] + pub const fn from_bits(val: u8) -> DmaDoneMask { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for DmaDoneMask { + #[inline(always)] + fn from(val: u8) -> DmaDoneMask { + DmaDoneMask::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: DmaDoneMask) -> u8 { + DmaDoneMask::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum EhrValidMask { + #[doc = "Do not mask EHR interrupt i.e. interrupt is generated"] + IRQENABLE = 0x0, + #[doc = "Mask EHR interrupt i.e. no interrupt is generated"] + IRQDISABLE = 0x01, + } + impl EhrValidMask { + #[inline(always)] + pub const fn from_bits(val: u8) -> EhrValidMask { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for EhrValidMask { + #[inline(always)] + fn from(val: u8) -> EhrValidMask { + EhrValidMask::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: EhrValidMask) -> u8 { + EhrValidMask::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum EhrWidth { + #[doc = "128 bits EHR width"] + _128BITS = 0x0, + #[doc = "192 bits EHR width"] + _192BITS = 0x01, + } + impl EhrWidth { + #[inline(always)] + pub const fn from_bits(val: u8) -> EhrWidth { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for EhrWidth { + #[inline(always)] + fn from(val: u8) -> EhrWidth { + EhrWidth::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: EhrWidth) -> u8 { + EhrWidth::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum RngBusyStatus { + #[doc = "RNG engine is idle"] + IDLE = 0x0, + #[doc = "RNG engine is busy"] + BUSY = 0x01, + } + impl RngBusyStatus { + #[inline(always)] + pub const fn from_bits(val: u8) -> RngBusyStatus { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for RngBusyStatus { + #[inline(always)] + fn from(val: u8) -> RngBusyStatus { + RngBusyStatus::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: RngBusyStatus) -> u8 { + RngBusyStatus::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum RngDmaBusyRoscLen { + #[doc = "Shortest ROSC1 ring oscillator configuration used."] + ROSC1 = 0x0, + #[doc = "ROSC2 ring oscillator configuration used."] + ROSC2 = 0x01, + #[doc = "ROSC3 ring oscillator configuration used."] + ROSC3 = 0x02, + #[doc = "Longest ROSC4 ring oscillator configuration used."] + ROSC4 = 0x03, + } + impl RngDmaBusyRoscLen { + #[inline(always)] + pub const fn from_bits(val: u8) -> RngDmaBusyRoscLen { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for RngDmaBusyRoscLen { + #[inline(always)] + fn from(val: u8) -> RngDmaBusyRoscLen { + RngDmaBusyRoscLen::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: RngDmaBusyRoscLen) -> u8 { + RngDmaBusyRoscLen::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum RngDmaBusyStatus { + #[doc = "RNG DMA engine is idle"] + IDLE = 0x0, + #[doc = "RNG DMA engine is busy"] + BUSY = 0x01, + } + impl RngDmaBusyStatus { + #[inline(always)] + pub const fn from_bits(val: u8) -> RngDmaBusyStatus { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for RngDmaBusyStatus { + #[inline(always)] + fn from(val: u8) -> RngDmaBusyStatus { + RngDmaBusyStatus::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: RngDmaBusyStatus) -> u8 { + RngDmaBusyStatus::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum TrngConfigRoscLen { + #[doc = "Use shortest ROSC1 ring oscillator configuration."] + ROSC1 = 0x0, + #[doc = "Use ROSC2 ring oscillator configuration."] + ROSC2 = 0x01, + #[doc = "Use ROSC3 ring oscillator configuration."] + ROSC3 = 0x02, + #[doc = "Use longest ROSC4 ring oscillator configuration."] + ROSC4 = 0x03, + } + impl TrngConfigRoscLen { + #[inline(always)] + pub const fn from_bits(val: u8) -> TrngConfigRoscLen { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for TrngConfigRoscLen { + #[inline(always)] + fn from(val: u8) -> TrngConfigRoscLen { + TrngConfigRoscLen::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: TrngConfigRoscLen) -> u8 { + TrngConfigRoscLen::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum TrngStatus { + #[doc = "TRNG is idle"] + IDLE = 0x0, + #[doc = "TRNG is busy"] + BUSY = 0x01, + } + impl TrngStatus { + #[inline(always)] + pub const fn from_bits(val: u8) -> TrngStatus { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for TrngStatus { + #[inline(always)] + fn from(val: u8) -> TrngStatus { + TrngStatus::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: TrngStatus) -> u8 { + TrngStatus::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum VncErrMask { + #[doc = "Do not mask the von Neumann corrector error interrupt i.e. interrupt is generated"] + IRQENABLE = 0x0, + #[doc = "Mask the von Neumann corrector error interrupt i.e. no interrupt is generated"] + IRQDISABLE = 0x01, + } + impl VncErrMask { + #[inline(always)] + pub const fn from_bits(val: u8) -> VncErrMask { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for VncErrMask { + #[inline(always)] + fn from(val: u8) -> VncErrMask { + VncErrMask::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: VncErrMask) -> u8 { + VncErrMask::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum WatchdogMask { + #[doc = "Do not mask the watchdog interrupt i.e. interrupt is generated"] + IRQENABLE = 0x0, + #[doc = "Mask the watchdog interrupt i.e. no interrupt is generated"] + IRQDISABLE = 0x01, + } + impl WatchdogMask { + #[inline(always)] + pub const fn from_bits(val: u8) -> WatchdogMask { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for WatchdogMask { + #[inline(always)] + fn from(val: u8) -> WatchdogMask { + WatchdogMask::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: WatchdogMask) -> u8 { + WatchdogMask::to_bits(val) + } + } + } +} +pub mod cc_rng_sram { + #[doc = "CRYPTOCELL RNG SRAM interface"] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct CcRngSram { + ptr: *mut u8, + } + unsafe impl Send for CcRngSram {} + unsafe impl Sync for CcRngSram {} + impl CcRngSram { + #[inline(always)] + pub const unsafe fn from_ptr(ptr: *mut ()) -> Self { + Self { ptr: ptr as _ } + } + #[inline(always)] + pub const fn as_ptr(&self) -> *mut () { + self.ptr as _ + } + #[doc = "Read/Write data from RNG SRAM"] + #[inline(always)] + pub const fn sram_data(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0f00usize) as _) } + } + #[doc = "First address given to RNG SRAM DMA for read/write transactions from/to RNG SRAM."] + #[inline(always)] + pub const fn sram_addr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0f04usize) as _) } + } + #[doc = "RNG SRAM DMA engine is ready to read/write from/to RNG SRAM."] + #[inline(always)] + pub const fn sram_data_ready( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0f08usize) as _) } + } + } + pub mod regs { + #[doc = "First address given to RNG SRAM DMA for read/write transactions from/to RNG SRAM."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct SramAddr(pub u32); + impl SramAddr { + #[doc = "RNG SRAM starting address"] + #[inline(always)] + pub const fn sram_addr(&self) -> u16 { + let val = (self.0 >> 0usize) & 0x7fff; + val as u16 + } + #[doc = "RNG SRAM starting address"] + #[inline(always)] + pub fn set_sram_addr(&mut self, val: u16) { + self.0 = (self.0 & !(0x7fff << 0usize)) | (((val as u32) & 0x7fff) << 0usize); + } + } + impl Default for SramAddr { + #[inline(always)] + fn default() -> SramAddr { + SramAddr(0) + } + } + #[doc = "RNG SRAM DMA engine is ready to read/write from/to RNG SRAM."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct SramDataReady(pub u32); + impl SramDataReady { + #[doc = "RNG SRAM DMA status."] + #[inline(always)] + pub const fn sram_ready(&self) -> super::vals::SramReady { + let val = (self.0 >> 0usize) & 0x01; + super::vals::SramReady::from_bits(val as u8) + } + #[doc = "RNG SRAM DMA status."] + #[inline(always)] + pub fn set_sram_ready(&mut self, val: super::vals::SramReady) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); + } + } + impl Default for SramDataReady { + #[inline(always)] + fn default() -> SramDataReady { + SramDataReady(0) + } + } + } + pub mod vals { + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum SramReady { + #[doc = "DMA is busy"] + BUSY = 0x0, + #[doc = "DMA is idle"] + IDLE = 0x01, + } + impl SramReady { + #[inline(always)] + pub const fn from_bits(val: u8) -> SramReady { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for SramReady { + #[inline(always)] + fn from(val: u8) -> SramReady { + SramReady::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: SramReady) -> u8 { + SramReady::to_bits(val) + } + } + } +} +pub mod ccm { + #[doc = "AES CCM mode encryption"] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ccm { + ptr: *mut u8, + } + unsafe impl Send for Ccm {} + unsafe impl Sync for Ccm {} + impl Ccm { + #[inline(always)] + pub const unsafe fn from_ptr(ptr: *mut ()) -> Self { + Self { ptr: ptr as _ } + } + #[inline(always)] + pub const fn as_ptr(&self) -> *mut () { + self.ptr as _ + } + #[doc = "Start generation of keystream. This operation will stop by itself when completed."] + #[inline(always)] + pub const fn tasks_ksgen(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } + } + #[doc = "Start encryption/decryption. This operation will stop by itself when completed."] + #[inline(always)] + pub const fn tasks_crypt(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } + } + #[doc = "Stop encryption/decryption"] + #[inline(always)] + pub const fn tasks_stop(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } + } + #[doc = "Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption"] + #[inline(always)] + pub const fn tasks_rateoverride(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } + } + #[doc = "Keystream generation complete"] + #[inline(always)] + pub const fn events_endksgen(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0100usize) as _) } + } + #[doc = "Encrypt/decrypt complete"] + #[inline(always)] + pub const fn events_endcrypt(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0104usize) as _) } + } + #[doc = "Deprecated register - CCM error event"] + #[inline(always)] + pub const fn events_error(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0108usize) as _) } + } + #[doc = "Shortcuts between local events and tasks"] + #[inline(always)] + pub const fn shorts(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0200usize) as _) } + } + #[doc = "Enable interrupt"] + #[inline(always)] + pub const fn intenset(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0304usize) as _) } + } + #[doc = "Disable interrupt"] + #[inline(always)] + pub const fn intenclr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0308usize) as _) } + } + #[doc = "MIC check result"] + #[inline(always)] + pub const fn micstatus(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0400usize) as _) } + } + #[doc = "Enable"] + #[inline(always)] + pub const fn enable(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0500usize) as _) } + } + #[doc = "Operation mode"] + #[inline(always)] + pub const fn mode(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0504usize) as _) } + } + #[doc = "Pointer to data structure holding the AES key and the NONCE vector"] + #[inline(always)] + pub const fn cnfptr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0508usize) as _) } + } + #[doc = "Input pointer"] + #[inline(always)] + pub const fn inptr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x050cusize) as _) } + } + #[doc = "Output pointer"] + #[inline(always)] + pub const fn outptr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0510usize) as _) } + } + #[doc = "Pointer to data area used for temporary storage"] + #[inline(always)] + pub const fn scratchptr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0514usize) as _) } + } + #[doc = "Length of keystream generated when MODE.LENGTH = Extended"] + #[inline(always)] + pub const fn maxpacketsize( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0518usize) as _) } + } + #[doc = "Data rate override setting."] + #[inline(always)] + pub const fn rateoverride( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x051cusize) as _) } + } + } + pub mod regs { + #[doc = "Enable"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Enable(pub u32); + impl Enable { + #[doc = "Enable or disable CCM"] + #[inline(always)] + pub const fn enable(&self) -> super::vals::Enable { + let val = (self.0 >> 0usize) & 0x03; + super::vals::Enable::from_bits(val as u8) + } + #[doc = "Enable or disable CCM"] + #[inline(always)] + pub fn set_enable(&mut self, val: super::vals::Enable) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); + } + } + impl Default for Enable { + #[inline(always)] + fn default() -> Enable { + Enable(0) + } + } + #[doc = "Disable interrupt"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Inten(pub u32); + impl Inten { + #[doc = "Write '1' to disable interrupt for event ENDKSGEN"] + #[inline(always)] + pub const fn endksgen(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Write '1' to disable interrupt for event ENDKSGEN"] + #[inline(always)] + pub fn set_endksgen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Write '1' to disable interrupt for event ENDCRYPT"] + #[inline(always)] + pub const fn endcrypt(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Write '1' to disable interrupt for event ENDCRYPT"] + #[inline(always)] + pub fn set_endcrypt(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Deprecated intclrfield - Write '1' to disable interrupt for event ERROR"] + #[inline(always)] + pub const fn error(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Deprecated intclrfield - Write '1' to disable interrupt for event ERROR"] + #[inline(always)] + pub fn set_error(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + } + impl Default for Inten { + #[inline(always)] + fn default() -> Inten { + Inten(0) + } + } + #[doc = "Length of keystream generated when MODE.LENGTH = Extended"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Maxpacketsize(pub u32); + impl Maxpacketsize { + #[doc = "Length of keystream generated when MODE.LENGTH = Extended. This value must be greater than or equal to the subsequent packet payload to be encrypted/decrypted."] + #[inline(always)] + pub const fn maxpacketsize(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 + } + #[doc = "Length of keystream generated when MODE.LENGTH = Extended. This value must be greater than or equal to the subsequent packet payload to be encrypted/decrypted."] + #[inline(always)] + pub fn set_maxpacketsize(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); + } + } + impl Default for Maxpacketsize { + #[inline(always)] + fn default() -> Maxpacketsize { + Maxpacketsize(0) + } + } + #[doc = "MIC check result"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Micstatus(pub u32); + impl Micstatus { + #[doc = "The result of the MIC check performed during the previous decryption operation"] + #[inline(always)] + pub const fn micstatus(&self) -> super::vals::Micstatus { + let val = (self.0 >> 0usize) & 0x01; + super::vals::Micstatus::from_bits(val as u8) + } + #[doc = "The result of the MIC check performed during the previous decryption operation"] + #[inline(always)] + pub fn set_micstatus(&mut self, val: super::vals::Micstatus) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); + } + } + impl Default for Micstatus { + #[inline(always)] + fn default() -> Micstatus { + Micstatus(0) + } + } + #[doc = "Operation mode"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Mode(pub u32); + impl Mode { + #[doc = "The mode of operation to be used. Settings in this register apply whenever either the KSGEN task or the CRYPT task is triggered."] + #[inline(always)] + pub const fn mode(&self) -> super::vals::Mode { + let val = (self.0 >> 0usize) & 0x01; + super::vals::Mode::from_bits(val as u8) + } + #[doc = "The mode of operation to be used. Settings in this register apply whenever either the KSGEN task or the CRYPT task is triggered."] + #[inline(always)] + pub fn set_mode(&mut self, val: super::vals::Mode) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); + } + #[doc = "Radio data rate that the CCM shall run synchronous with"] + #[inline(always)] + pub const fn datarate(&self) -> super::vals::Datarate { + let val = (self.0 >> 16usize) & 0x03; + super::vals::Datarate::from_bits(val as u8) + } + #[doc = "Radio data rate that the CCM shall run synchronous with"] + #[inline(always)] + pub fn set_datarate(&mut self, val: super::vals::Datarate) { + self.0 = + (self.0 & !(0x03 << 16usize)) | (((val.to_bits() as u32) & 0x03) << 16usize); + } + #[doc = "Packet length configuration"] + #[inline(always)] + pub const fn length(&self) -> super::vals::Length { + let val = (self.0 >> 24usize) & 0x01; + super::vals::Length::from_bits(val as u8) + } + #[doc = "Packet length configuration"] + #[inline(always)] + pub fn set_length(&mut self, val: super::vals::Length) { + self.0 = + (self.0 & !(0x01 << 24usize)) | (((val.to_bits() as u32) & 0x01) << 24usize); + } + } + impl Default for Mode { + #[inline(always)] + fn default() -> Mode { + Mode(0) + } + } + #[doc = "Data rate override setting."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Rateoverride(pub u32); + impl Rateoverride { + #[doc = "Data rate override setting"] + #[inline(always)] + pub const fn rateoverride(&self) -> super::vals::Rateoverride { + let val = (self.0 >> 0usize) & 0x03; + super::vals::Rateoverride::from_bits(val as u8) + } + #[doc = "Data rate override setting"] + #[inline(always)] + pub fn set_rateoverride(&mut self, val: super::vals::Rateoverride) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); + } + } + impl Default for Rateoverride { + #[inline(always)] + fn default() -> Rateoverride { + Rateoverride(0) + } + } + #[doc = "Shortcuts between local events and tasks"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Shorts(pub u32); + impl Shorts { + #[doc = "Shortcut between event ENDKSGEN and task CRYPT"] + #[inline(always)] + pub const fn endksgen_crypt(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Shortcut between event ENDKSGEN and task CRYPT"] + #[inline(always)] + pub fn set_endksgen_crypt(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + } + impl Default for Shorts { + #[inline(always)] + fn default() -> Shorts { + Shorts(0) + } + } + } + pub mod vals { + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum Datarate { + #[doc = "1 Mbps"] + _1MBIT = 0x0, + #[doc = "2 Mbps"] + _2MBIT = 0x01, + #[doc = "125 kbps"] + _125KBPS = 0x02, + #[doc = "500 kbps"] + _500KBPS = 0x03, + } + impl Datarate { + #[inline(always)] + pub const fn from_bits(val: u8) -> Datarate { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for Datarate { + #[inline(always)] + fn from(val: u8) -> Datarate { + Datarate::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: Datarate) -> u8 { + Datarate::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum Enable { + #[doc = "Disable"] + DISABLED = 0x0, + _RESERVED_1 = 0x01, + #[doc = "Enable"] + ENABLED = 0x02, + _RESERVED_3 = 0x03, + } + impl Enable { + #[inline(always)] + pub const fn from_bits(val: u8) -> Enable { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for Enable { + #[inline(always)] + fn from(val: u8) -> Enable { + Enable::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: Enable) -> u8 { + Enable::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum Length { + #[doc = "Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A keystream for packet payloads up to 27 bytes will be generated."] + DEFAULT = 0x0, + #[doc = "Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A keystream for packet payloads up to MAXPACKETSIZE bytes will be generated."] + EXTENDED = 0x01, + } + impl Length { + #[inline(always)] + pub const fn from_bits(val: u8) -> Length { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for Length { + #[inline(always)] + fn from(val: u8) -> Length { + Length::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: Length) -> u8 { + Length::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum Micstatus { + #[doc = "MIC check failed"] + CHECK_FAILED = 0x0, + #[doc = "MIC check passed"] + CHECK_PASSED = 0x01, + } + impl Micstatus { + #[inline(always)] + pub const fn from_bits(val: u8) -> Micstatus { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for Micstatus { + #[inline(always)] + fn from(val: u8) -> Micstatus { + Micstatus::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: Micstatus) -> u8 { + Micstatus::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum Mode { + #[doc = "AES CCM packet encryption mode"] + ENCRYPTION = 0x0, + #[doc = "AES CCM packet decryption mode"] + DECRYPTION = 0x01, + } + impl Mode { + #[inline(always)] + pub const fn from_bits(val: u8) -> Mode { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for Mode { + #[inline(always)] + fn from(val: u8) -> Mode { + Mode::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: Mode) -> u8 { + Mode::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum Rateoverride { + #[doc = "1 Mbps"] + _1MBIT = 0x0, + #[doc = "2 Mbps"] + _2MBIT = 0x01, + #[doc = "125 kbps"] + _125KBPS = 0x02, + #[doc = "500 kbps"] + _500KBPS = 0x03, + } + impl Rateoverride { + #[inline(always)] + pub const fn from_bits(val: u8) -> Rateoverride { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for Rateoverride { + #[inline(always)] + fn from(val: u8) -> Rateoverride { + Rateoverride::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: Rateoverride) -> u8 { + Rateoverride::to_bits(val) + } + } + } +} +pub mod clock { + #[doc = "Clock control"] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Clock { + ptr: *mut u8, + } + unsafe impl Send for Clock {} + unsafe impl Sync for Clock {} + impl Clock { + #[inline(always)] + pub const unsafe fn from_ptr(ptr: *mut ()) -> Self { + Self { ptr: ptr as _ } + } + #[inline(always)] + pub const fn as_ptr(&self) -> *mut () { + self.ptr as _ + } + #[doc = "Start HFXO crystal oscillator"] + #[inline(always)] + pub const fn tasks_hfclkstart(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } + } + #[doc = "Stop HFXO crystal oscillator"] + #[inline(always)] + pub const fn tasks_hfclkstop(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } + } + #[doc = "Start LFCLK"] + #[inline(always)] + pub const fn tasks_lfclkstart(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } + } + #[doc = "Stop LFCLK"] + #[inline(always)] + pub const fn tasks_lfclkstop(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } + } + #[doc = "Start calibration of LFRC"] + #[inline(always)] + pub const fn tasks_cal(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } + } + #[doc = "Start calibration timer"] + #[inline(always)] + pub const fn tasks_ctstart(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) } + } + #[doc = "Stop calibration timer"] + #[inline(always)] + pub const fn tasks_ctstop(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) } + } + #[doc = "HFXO crystal oscillator started"] + #[inline(always)] + pub const fn events_hfclkstarted(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0100usize) as _) } + } + #[doc = "LFCLK started"] + #[inline(always)] + pub const fn events_lfclkstarted(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0104usize) as _) } + } + #[doc = "Calibration of LFRC completed"] + #[inline(always)] + pub const fn events_done(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x010cusize) as _) } + } + #[doc = "Calibration timer timeout"] + #[inline(always)] + pub const fn events_ctto(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0110usize) as _) } + } + #[doc = "Calibration timer has been started and is ready to process new tasks"] + #[inline(always)] + pub const fn events_ctstarted(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0128usize) as _) } + } + #[doc = "Calibration timer has been stopped and is ready to process new tasks"] + #[inline(always)] + pub const fn events_ctstopped(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x012cusize) as _) } + } + #[doc = "Enable interrupt"] + #[inline(always)] + pub const fn intenset(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0304usize) as _) } + } + #[doc = "Disable interrupt"] + #[inline(always)] + pub const fn intenclr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0308usize) as _) } + } + #[doc = "Status indicating that HFCLKSTART task has been triggered"] + #[inline(always)] + pub const fn hfclkrun(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0408usize) as _) } + } + #[doc = "HFCLK status"] + #[inline(always)] + pub const fn hfclkstat(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x040cusize) as _) } + } + #[doc = "Status indicating that LFCLKSTART task has been triggered"] + #[inline(always)] + pub const fn lfclkrun(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0414usize) as _) } + } + #[doc = "LFCLK status"] + #[inline(always)] + pub const fn lfclkstat(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0418usize) as _) } + } + #[doc = "Copy of LFCLKSRC register, set when LFCLKSTART task was triggered"] + #[inline(always)] + pub const fn lfclksrccopy( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x041cusize) as _) } + } + #[doc = "Clock source for the LFCLK"] + #[inline(always)] + pub const fn lfclksrc(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0518usize) as _) } + } + #[doc = "HFXO debounce time. The HFXO is started by triggering the TASKS_HFCLKSTART task."] + #[inline(always)] + pub const fn hfxodebounce( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0528usize) as _) } + } + #[doc = "Calibration timer interval"] + #[inline(always)] + pub const fn ctiv(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0538usize) as _) } + } + #[doc = "Clocking options for the trace port debug interface"] + #[inline(always)] + pub const fn traceconfig(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x055cusize) as _) } + } + #[doc = "LFRC mode configuration"] + #[inline(always)] + pub const fn lfrcmode(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x05b4usize) as _) } + } + } + pub mod regs { + #[doc = "Calibration timer interval"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ctiv(pub u32); + impl Ctiv { + #[doc = "Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds."] + #[inline(always)] + pub const fn ctiv(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x7f; + val as u8 + } + #[doc = "Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds."] + #[inline(always)] + pub fn set_ctiv(&mut self, val: u8) { + self.0 = (self.0 & !(0x7f << 0usize)) | (((val as u32) & 0x7f) << 0usize); + } + } + impl Default for Ctiv { + #[inline(always)] + fn default() -> Ctiv { + Ctiv(0) + } + } + #[doc = "Status indicating that HFCLKSTART task has been triggered"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Hfclkrun(pub u32); + impl Hfclkrun { + #[doc = "HFCLKSTART task triggered or not"] + #[inline(always)] + pub const fn status(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "HFCLKSTART task triggered or not"] + #[inline(always)] + pub fn set_status(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + } + impl Default for Hfclkrun { + #[inline(always)] + fn default() -> Hfclkrun { + Hfclkrun(0) + } + } + #[doc = "HFCLK status"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Hfclkstat(pub u32); + impl Hfclkstat { + #[doc = "Source of HFCLK"] + #[inline(always)] + pub const fn src(&self) -> super::vals::HfclkstatSrc { + let val = (self.0 >> 0usize) & 0x01; + super::vals::HfclkstatSrc::from_bits(val as u8) + } + #[doc = "Source of HFCLK"] + #[inline(always)] + pub fn set_src(&mut self, val: super::vals::HfclkstatSrc) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); + } + #[doc = "HFCLK state"] + #[inline(always)] + pub const fn state(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "HFCLK state"] + #[inline(always)] + pub fn set_state(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + } + impl Default for Hfclkstat { + #[inline(always)] + fn default() -> Hfclkstat { + Hfclkstat(0) + } + } + #[doc = "HFXO debounce time. The HFXO is started by triggering the TASKS_HFCLKSTART task."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Hfxodebounce(pub u32); + impl Hfxodebounce { + #[doc = "HFXO debounce time. Debounce time = HFXODEBOUNCE * 16 us."] + #[inline(always)] + pub const fn hfxodebounce(&self) -> super::vals::Hfxodebounce { + let val = (self.0 >> 0usize) & 0xff; + super::vals::Hfxodebounce::from_bits(val as u8) + } + #[doc = "HFXO debounce time. Debounce time = HFXODEBOUNCE * 16 us."] + #[inline(always)] + pub fn set_hfxodebounce(&mut self, val: super::vals::Hfxodebounce) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val.to_bits() as u32) & 0xff) << 0usize); + } + } + impl Default for Hfxodebounce { + #[inline(always)] + fn default() -> Hfxodebounce { + Hfxodebounce(0) + } + } + #[doc = "Disable interrupt"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Inten(pub u32); + impl Inten { + #[doc = "Write '1' to disable interrupt for event HFCLKSTARTED"] + #[inline(always)] + pub const fn hfclkstarted(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Write '1' to disable interrupt for event HFCLKSTARTED"] + #[inline(always)] + pub fn set_hfclkstarted(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Write '1' to disable interrupt for event LFCLKSTARTED"] + #[inline(always)] + pub const fn lfclkstarted(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Write '1' to disable interrupt for event LFCLKSTARTED"] + #[inline(always)] + pub fn set_lfclkstarted(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Write '1' to disable interrupt for event DONE"] + #[inline(always)] + pub const fn done(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Write '1' to disable interrupt for event DONE"] + #[inline(always)] + pub fn set_done(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "Write '1' to disable interrupt for event CTTO"] + #[inline(always)] + pub const fn ctto(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "Write '1' to disable interrupt for event CTTO"] + #[inline(always)] + pub fn set_ctto(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "Write '1' to disable interrupt for event CTSTARTED"] + #[inline(always)] + pub const fn ctstarted(&self) -> bool { + let val = (self.0 >> 10usize) & 0x01; + val != 0 + } + #[doc = "Write '1' to disable interrupt for event CTSTARTED"] + #[inline(always)] + pub fn set_ctstarted(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); + } + #[doc = "Write '1' to disable interrupt for event CTSTOPPED"] + #[inline(always)] + pub const fn ctstopped(&self) -> bool { + let val = (self.0 >> 11usize) & 0x01; + val != 0 + } + #[doc = "Write '1' to disable interrupt for event CTSTOPPED"] + #[inline(always)] + pub fn set_ctstopped(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); + } + } + impl Default for Inten { + #[inline(always)] + fn default() -> Inten { + Inten(0) + } + } + #[doc = "Status indicating that LFCLKSTART task has been triggered"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Lfclkrun(pub u32); + impl Lfclkrun { + #[doc = "LFCLKSTART task triggered or not"] + #[inline(always)] + pub const fn status(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "LFCLKSTART task triggered or not"] + #[inline(always)] + pub fn set_status(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + } + impl Default for Lfclkrun { + #[inline(always)] + fn default() -> Lfclkrun { + Lfclkrun(0) + } + } + #[doc = "Clock source for the LFCLK"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Lfclksrc(pub u32); + impl Lfclksrc { + #[doc = "Clock source"] + #[inline(always)] + pub const fn src(&self) -> super::vals::Lfclksrc { + let val = (self.0 >> 0usize) & 0x03; + super::vals::Lfclksrc::from_bits(val as u8) + } + #[doc = "Clock source"] + #[inline(always)] + pub fn set_src(&mut self, val: super::vals::Lfclksrc) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); + } + #[doc = "Enable or disable bypass of LFCLK crystal oscillator with external clock source"] + #[inline(always)] + pub const fn bypass(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "Enable or disable bypass of LFCLK crystal oscillator with external clock source"] + #[inline(always)] + pub fn set_bypass(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + #[doc = "Enable or disable external source for LFCLK"] + #[inline(always)] + pub const fn external(&self) -> bool { + let val = (self.0 >> 17usize) & 0x01; + val != 0 + } + #[doc = "Enable or disable external source for LFCLK"] + #[inline(always)] + pub fn set_external(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); + } + } + impl Default for Lfclksrc { + #[inline(always)] + fn default() -> Lfclksrc { + Lfclksrc(0) + } + } + #[doc = "Copy of LFCLKSRC register, set when LFCLKSTART task was triggered"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Lfclksrccopy(pub u32); + impl Lfclksrccopy { + #[doc = "Clock source"] + #[inline(always)] + pub const fn src(&self) -> super::vals::Lfclksrc { + let val = (self.0 >> 0usize) & 0x03; + super::vals::Lfclksrc::from_bits(val as u8) + } + #[doc = "Clock source"] + #[inline(always)] + pub fn set_src(&mut self, val: super::vals::Lfclksrc) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); + } + } + impl Default for Lfclksrccopy { + #[inline(always)] + fn default() -> Lfclksrccopy { + Lfclksrccopy(0) + } + } + #[doc = "LFCLK status"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Lfclkstat(pub u32); + impl Lfclkstat { + #[doc = "Source of LFCLK"] + #[inline(always)] + pub const fn src(&self) -> super::vals::Lfclksrc { + let val = (self.0 >> 0usize) & 0x03; + super::vals::Lfclksrc::from_bits(val as u8) + } + #[doc = "Source of LFCLK"] + #[inline(always)] + pub fn set_src(&mut self, val: super::vals::Lfclksrc) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); + } + #[doc = "LFCLK state"] + #[inline(always)] + pub const fn state(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "LFCLK state"] + #[inline(always)] + pub fn set_state(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + } + impl Default for Lfclkstat { + #[inline(always)] + fn default() -> Lfclkstat { + Lfclkstat(0) + } + } + #[doc = "LFRC mode configuration"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Lfrcmode(pub u32); + impl Lfrcmode { + #[doc = "Set LFRC mode"] + #[inline(always)] + pub const fn mode(&self) -> super::vals::Mode { + let val = (self.0 >> 0usize) & 0x01; + super::vals::Mode::from_bits(val as u8) + } + #[doc = "Set LFRC mode"] + #[inline(always)] + pub fn set_mode(&mut self, val: super::vals::Mode) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); + } + #[doc = "Active LFRC mode. This field is read only."] + #[inline(always)] + pub const fn status(&self) -> super::vals::LfrcmodeStatus { + let val = (self.0 >> 16usize) & 0x01; + super::vals::LfrcmodeStatus::from_bits(val as u8) + } + #[doc = "Active LFRC mode. This field is read only."] + #[inline(always)] + pub fn set_status(&mut self, val: super::vals::LfrcmodeStatus) { + self.0 = + (self.0 & !(0x01 << 16usize)) | (((val.to_bits() as u32) & 0x01) << 16usize); + } + } + impl Default for Lfrcmode { + #[inline(always)] + fn default() -> Lfrcmode { + Lfrcmode(0) + } + } + #[doc = "Clocking options for the trace port debug interface"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Traceconfig(pub u32); + impl Traceconfig { + #[doc = "Speed of trace port clock. Note that the TRACECLK pin will output this clock divided by two."] + #[inline(always)] + pub const fn traceportspeed(&self) -> super::vals::Traceportspeed { + let val = (self.0 >> 0usize) & 0x03; + super::vals::Traceportspeed::from_bits(val as u8) + } + #[doc = "Speed of trace port clock. Note that the TRACECLK pin will output this clock divided by two."] + #[inline(always)] + pub fn set_traceportspeed(&mut self, val: super::vals::Traceportspeed) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); + } + #[doc = "Pin multiplexing of trace signals. See pin assignment chapter for more details."] + #[inline(always)] + pub const fn tracemux(&self) -> super::vals::Tracemux { + let val = (self.0 >> 16usize) & 0x03; + super::vals::Tracemux::from_bits(val as u8) + } + #[doc = "Pin multiplexing of trace signals. See pin assignment chapter for more details."] + #[inline(always)] + pub fn set_tracemux(&mut self, val: super::vals::Tracemux) { + self.0 = + (self.0 & !(0x03 << 16usize)) | (((val.to_bits() as u32) & 0x03) << 16usize); + } + } + impl Default for Traceconfig { + #[inline(always)] + fn default() -> Traceconfig { + Traceconfig(0) + } + } + } + pub mod vals { + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum HfclkstatSrc { + #[doc = "64 MHz internal oscillator (HFINT)"] + RC = 0x0, + #[doc = "64 MHz crystal oscillator (HFXO)"] + XTAL = 0x01, + } + impl HfclkstatSrc { + #[inline(always)] + pub const fn from_bits(val: u8) -> HfclkstatSrc { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for HfclkstatSrc { + #[inline(always)] + fn from(val: u8) -> HfclkstatSrc { + HfclkstatSrc::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: HfclkstatSrc) -> u8 { + HfclkstatSrc::to_bits(val) + } + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Hfxodebounce(pub u8); + impl Hfxodebounce { + #[doc = "256 us debounce time. Recommended for TSX-3225, FA-20H and FA-128 crystals."] + pub const DB256US: Self = Self(0x10); + #[doc = "1024 us debounce time. Recommended for NX1612AA and NX1210AB crystals."] + pub const DB1024US: Self = Self(0x40); + } + impl Hfxodebounce { + pub const fn from_bits(val: u8) -> Hfxodebounce { + Self(val & 0xff) + } + pub const fn to_bits(self) -> u8 { + self.0 + } + } + impl From for Hfxodebounce { + #[inline(always)] + fn from(val: u8) -> Hfxodebounce { + Hfxodebounce::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: Hfxodebounce) -> u8 { + Hfxodebounce::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum Lfclksrc { + #[doc = "32.768 kHz RC oscillator (LFRC)"] + RC = 0x0, + #[doc = "32.768 kHz crystal oscillator (LFXO)"] + XTAL = 0x01, + #[doc = "32.768 kHz synthesized from HFCLK (LFSYNT)"] + SYNTH = 0x02, + _RESERVED_3 = 0x03, + } + impl Lfclksrc { + #[inline(always)] + pub const fn from_bits(val: u8) -> Lfclksrc { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for Lfclksrc { + #[inline(always)] + fn from(val: u8) -> Lfclksrc { + Lfclksrc::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: Lfclksrc) -> u8 { + Lfclksrc::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum LfrcmodeStatus { + #[doc = "Normal mode"] + NORMAL = 0x0, + #[doc = "Ultra-low power mode (ULP)"] + ULP = 0x01, + } + impl LfrcmodeStatus { + #[inline(always)] + pub const fn from_bits(val: u8) -> LfrcmodeStatus { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for LfrcmodeStatus { + #[inline(always)] + fn from(val: u8) -> LfrcmodeStatus { + LfrcmodeStatus::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: LfrcmodeStatus) -> u8 { + LfrcmodeStatus::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum Mode { + #[doc = "Normal mode"] + NORMAL = 0x0, + #[doc = "Ultra-low power mode (ULP)"] + ULP = 0x01, + } + impl Mode { + #[inline(always)] + pub const fn from_bits(val: u8) -> Mode { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for Mode { + #[inline(always)] + fn from(val: u8) -> Mode { + Mode::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: Mode) -> u8 { + Mode::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum Tracemux { + #[doc = "No trace signals routed to pins. All pins can be used as regular GPIOs."] + GPIO = 0x0, + #[doc = "SWO trace signal routed to pin. Remaining pins can be used as regular GPIOs."] + SERIAL = 0x01, + #[doc = "All trace signals (TRACECLK and TRACEDATA\\[n\\]) routed to pins."] + PARALLEL = 0x02, + _RESERVED_3 = 0x03, + } + impl Tracemux { + #[inline(always)] + pub const fn from_bits(val: u8) -> Tracemux { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for Tracemux { + #[inline(always)] + fn from(val: u8) -> Tracemux { + Tracemux::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: Tracemux) -> u8 { + Tracemux::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum Traceportspeed { + #[doc = "32 MHz trace port clock (TRACECLK = 16 MHz)"] + _32MHZ = 0x0, + #[doc = "16 MHz trace port clock (TRACECLK = 8 MHz)"] + _16MHZ = 0x01, + #[doc = "8 MHz trace port clock (TRACECLK = 4 MHz)"] + _8MHZ = 0x02, + #[doc = "4 MHz trace port clock (TRACECLK = 2 MHz)"] + _4MHZ = 0x03, + } + impl Traceportspeed { + #[inline(always)] + pub const fn from_bits(val: u8) -> Traceportspeed { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for Traceportspeed { + #[inline(always)] + fn from(val: u8) -> Traceportspeed { + Traceportspeed::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: Traceportspeed) -> u8 { + Traceportspeed::to_bits(val) + } + } + } +} +pub mod common { + use core::marker::PhantomData; + #[derive(Copy, Clone, PartialEq, Eq)] + pub struct RW; + #[derive(Copy, Clone, PartialEq, Eq)] + pub struct R; + #[derive(Copy, Clone, PartialEq, Eq)] + pub struct W; + mod sealed { + use super::*; + pub trait Access {} + impl Access for R {} + impl Access for W {} + impl Access for RW {} + } + pub trait Access: sealed::Access + Copy {} + impl Access for R {} + impl Access for W {} + impl Access for RW {} + pub trait Read: Access {} + impl Read for RW {} + impl Read for R {} + pub trait Write: Access {} + impl Write for RW {} + impl Write for W {} + #[derive(Copy, Clone, PartialEq, Eq)] + pub struct Reg { + ptr: *mut u8, + phantom: PhantomData<*mut (T, A)>, + } + unsafe impl Send for Reg {} + unsafe impl Sync for Reg {} + impl Reg { + #[allow(clippy::missing_safety_doc)] + #[inline(always)] + pub const unsafe fn from_ptr(ptr: *mut T) -> Self { + Self { + ptr: ptr as _, + phantom: PhantomData, + } + } + #[inline(always)] + pub const fn as_ptr(&self) -> *mut T { + self.ptr as _ + } + } + impl Reg { + #[inline(always)] + pub fn read(&self) -> T { + unsafe { (self.ptr as *mut T).read_volatile() } + } + } + impl Reg { + #[inline(always)] + pub fn write_value(&self, val: T) { + unsafe { (self.ptr as *mut T).write_volatile(val) } + } + } + impl Reg { + #[inline(always)] + pub fn write(&self, f: impl FnOnce(&mut T) -> R) -> R { + let mut val = Default::default(); + let res = f(&mut val); + self.write_value(val); + res + } + } + impl Reg { + #[inline(always)] + pub fn modify(&self, f: impl FnOnce(&mut T) -> R) -> R { + let mut val = self.read(); + let res = f(&mut val); + self.write_value(val); + res + } + } +} +pub mod comp { + #[doc = "Comparator"] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Comp { + ptr: *mut u8, + } + unsafe impl Send for Comp {} + unsafe impl Sync for Comp {} + impl Comp { + #[inline(always)] + pub const unsafe fn from_ptr(ptr: *mut ()) -> Self { + Self { ptr: ptr as _ } + } + #[inline(always)] + pub const fn as_ptr(&self) -> *mut () { + self.ptr as _ + } + #[doc = "Start comparator"] + #[inline(always)] + pub const fn tasks_start(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } + } + #[doc = "Stop comparator"] + #[inline(always)] + pub const fn tasks_stop(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } + } + #[doc = "Sample comparator value"] + #[inline(always)] + pub const fn tasks_sample(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } + } + #[doc = "COMP is ready and output is valid"] + #[inline(always)] + pub const fn events_ready(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0100usize) as _) } + } + #[doc = "Downward crossing"] + #[inline(always)] + pub const fn events_down(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0104usize) as _) } + } + #[doc = "Upward crossing"] + #[inline(always)] + pub const fn events_up(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0108usize) as _) } + } + #[doc = "Downward or upward crossing"] + #[inline(always)] + pub const fn events_cross(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x010cusize) as _) } + } + #[doc = "Shortcuts between local events and tasks"] + #[inline(always)] + pub const fn shorts(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0200usize) as _) } + } + #[doc = "Enable or disable interrupt"] + #[inline(always)] + pub const fn inten(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0300usize) as _) } + } + #[doc = "Enable interrupt"] + #[inline(always)] + pub const fn intenset(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0304usize) as _) } + } + #[doc = "Disable interrupt"] + #[inline(always)] + pub const fn intenclr(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0308usize) as _) } + } + #[doc = "Compare result"] + #[inline(always)] + pub const fn result(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0400usize) as _) } + } + #[doc = "COMP enable"] + #[inline(always)] + pub const fn enable(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0500usize) as _) } + } + #[doc = "Pin select"] + #[inline(always)] + pub const fn psel(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0504usize) as _) } + } + #[doc = "Reference source select for single-ended mode"] + #[inline(always)] + pub const fn refsel(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0508usize) as _) } + } + #[doc = "External reference select"] + #[inline(always)] + pub const fn extrefsel(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x050cusize) as _) } + } + #[doc = "Threshold configuration for hysteresis unit"] + #[inline(always)] + pub const fn th(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0530usize) as _) } + } + #[doc = "Mode configuration"] + #[inline(always)] + pub const fn mode(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0534usize) as _) } + } + #[doc = "Comparator hysteresis enable"] + #[inline(always)] + pub const fn hyst(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0538usize) as _) } + } + } + pub mod regs { + #[doc = "COMP enable"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Enable(pub u32); + impl Enable { + #[doc = "Enable or disable COMP"] + #[inline(always)] + pub const fn enable(&self) -> super::vals::Enable { + let val = (self.0 >> 0usize) & 0x03; + super::vals::Enable::from_bits(val as u8) + } + #[doc = "Enable or disable COMP"] + #[inline(always)] + pub fn set_enable(&mut self, val: super::vals::Enable) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); + } + } + impl Default for Enable { + #[inline(always)] + fn default() -> Enable { + Enable(0) + } + } + #[doc = "External reference select"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Extrefsel(pub u32); + impl Extrefsel { + #[doc = "External analog reference select"] + #[inline(always)] + pub const fn extrefsel(&self) -> super::vals::Extrefsel { + let val = (self.0 >> 0usize) & 0x07; + super::vals::Extrefsel::from_bits(val as u8) + } + #[doc = "External analog reference select"] + #[inline(always)] + pub fn set_extrefsel(&mut self, val: super::vals::Extrefsel) { + self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); + } + } + impl Default for Extrefsel { + #[inline(always)] + fn default() -> Extrefsel { + Extrefsel(0) + } + } + #[doc = "Comparator hysteresis enable"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Hyst(pub u32); + impl Hyst { + #[doc = "Comparator hysteresis"] + #[inline(always)] + pub const fn hyst(&self) -> super::vals::Hyst { + let val = (self.0 >> 0usize) & 0x01; + super::vals::Hyst::from_bits(val as u8) + } + #[doc = "Comparator hysteresis"] + #[inline(always)] + pub fn set_hyst(&mut self, val: super::vals::Hyst) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); + } + } + impl Default for Hyst { + #[inline(always)] + fn default() -> Hyst { + Hyst(0) + } + } + #[doc = "Enable or disable interrupt"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Inten(pub u32); + impl Inten { + #[doc = "Enable or disable interrupt for event READY"] + #[inline(always)] + pub const fn ready(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Enable or disable interrupt for event READY"] + #[inline(always)] + pub fn set_ready(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Enable or disable interrupt for event DOWN"] + #[inline(always)] + pub const fn down(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Enable or disable interrupt for event DOWN"] + #[inline(always)] + pub fn set_down(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Enable or disable interrupt for event UP"] + #[inline(always)] + pub const fn up(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Enable or disable interrupt for event UP"] + #[inline(always)] + pub fn set_up(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Enable or disable interrupt for event CROSS"] + #[inline(always)] + pub const fn cross(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Enable or disable interrupt for event CROSS"] + #[inline(always)] + pub fn set_cross(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + } + impl Default for Inten { + #[inline(always)] + fn default() -> Inten { + Inten(0) + } + } + #[doc = "Mode configuration"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Mode(pub u32); + impl Mode { + #[doc = "Speed and power modes"] + #[inline(always)] + pub const fn sp(&self) -> super::vals::Sp { + let val = (self.0 >> 0usize) & 0x03; + super::vals::Sp::from_bits(val as u8) + } + #[doc = "Speed and power modes"] + #[inline(always)] + pub fn set_sp(&mut self, val: super::vals::Sp) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); + } + #[doc = "Main operation modes"] + #[inline(always)] + pub const fn main(&self) -> super::vals::Main { + let val = (self.0 >> 8usize) & 0x01; + super::vals::Main::from_bits(val as u8) + } + #[doc = "Main operation modes"] + #[inline(always)] + pub fn set_main(&mut self, val: super::vals::Main) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val.to_bits() as u32) & 0x01) << 8usize); + } + } + impl Default for Mode { + #[inline(always)] + fn default() -> Mode { + Mode(0) + } + } + #[doc = "Pin select"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Psel(pub u32); + impl Psel { + #[doc = "Analog pin select"] + #[inline(always)] + pub const fn psel(&self) -> super::vals::PselPsel { + let val = (self.0 >> 0usize) & 0x07; + super::vals::PselPsel::from_bits(val as u8) + } + #[doc = "Analog pin select"] + #[inline(always)] + pub fn set_psel(&mut self, val: super::vals::PselPsel) { + self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); + } + } + impl Default for Psel { + #[inline(always)] + fn default() -> Psel { + Psel(0) + } + } + #[doc = "Reference source select for single-ended mode"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Refsel(pub u32); + impl Refsel { + #[doc = "Reference select"] + #[inline(always)] + pub const fn refsel(&self) -> super::vals::Refsel { + let val = (self.0 >> 0usize) & 0x07; + super::vals::Refsel::from_bits(val as u8) + } + #[doc = "Reference select"] + #[inline(always)] + pub fn set_refsel(&mut self, val: super::vals::Refsel) { + self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); + } + } + impl Default for Refsel { + #[inline(always)] + fn default() -> Refsel { + Refsel(0) + } + } + #[doc = "Compare result"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Result(pub u32); + impl Result { + #[doc = "Result of last compare. Decision point SAMPLE task."] + #[inline(always)] + pub const fn result(&self) -> super::vals::Result { + let val = (self.0 >> 0usize) & 0x01; + super::vals::Result::from_bits(val as u8) + } + #[doc = "Result of last compare. Decision point SAMPLE task."] + #[inline(always)] + pub fn set_result(&mut self, val: super::vals::Result) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); + } + } + impl Default for Result { + #[inline(always)] + fn default() -> Result { + Result(0) + } + } + #[doc = "Shortcuts between local events and tasks"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Shorts(pub u32); + impl Shorts { + #[doc = "Shortcut between event READY and task SAMPLE"] + #[inline(always)] + pub const fn ready_sample(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Shortcut between event READY and task SAMPLE"] + #[inline(always)] + pub fn set_ready_sample(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Shortcut between event READY and task STOP"] + #[inline(always)] + pub const fn ready_stop(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Shortcut between event READY and task STOP"] + #[inline(always)] + pub fn set_ready_stop(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Shortcut between event DOWN and task STOP"] + #[inline(always)] + pub const fn down_stop(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Shortcut between event DOWN and task STOP"] + #[inline(always)] + pub fn set_down_stop(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Shortcut between event UP and task STOP"] + #[inline(always)] + pub const fn up_stop(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Shortcut between event UP and task STOP"] + #[inline(always)] + pub fn set_up_stop(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "Shortcut between event CROSS and task STOP"] + #[inline(always)] + pub const fn cross_stop(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "Shortcut between event CROSS and task STOP"] + #[inline(always)] + pub fn set_cross_stop(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + } + impl Default for Shorts { + #[inline(always)] + fn default() -> Shorts { + Shorts(0) + } + } + #[doc = "Threshold configuration for hysteresis unit"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Th(pub u32); + impl Th { + #[doc = "VDOWN = (THDOWN+1)/64*VREF"] + #[inline(always)] + pub const fn thdown(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x3f; + val as u8 + } + #[doc = "VDOWN = (THDOWN+1)/64*VREF"] + #[inline(always)] + pub fn set_thdown(&mut self, val: u8) { + self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize); + } + #[doc = "VUP = (THUP+1)/64*VREF"] + #[inline(always)] + pub const fn thup(&self) -> u8 { + let val = (self.0 >> 8usize) & 0x3f; + val as u8 + } + #[doc = "VUP = (THUP+1)/64*VREF"] + #[inline(always)] + pub fn set_thup(&mut self, val: u8) { + self.0 = (self.0 & !(0x3f << 8usize)) | (((val as u32) & 0x3f) << 8usize); + } + } + impl Default for Th { + #[inline(always)] + fn default() -> Th { + Th(0) + } + } + } + pub mod vals { + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum Enable { + #[doc = "Disable"] + DISABLED = 0x0, + _RESERVED_1 = 0x01, + #[doc = "Enable"] + ENABLED = 0x02, + _RESERVED_3 = 0x03, + } + impl Enable { + #[inline(always)] + pub const fn from_bits(val: u8) -> Enable { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for Enable { + #[inline(always)] + fn from(val: u8) -> Enable { + Enable::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: Enable) -> u8 { + Enable::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum Extrefsel { + #[doc = "Use AIN0 as external analog reference"] + ANALOG_REFERENCE0 = 0x0, + #[doc = "Use AIN1 as external analog reference"] + ANALOG_REFERENCE1 = 0x01, + #[doc = "Use AIN2 as external analog reference"] + ANALOG_REFERENCE2 = 0x02, + #[doc = "Use AIN3 as external analog reference"] + ANALOG_REFERENCE3 = 0x03, + #[doc = "Use AIN4 as external analog reference"] + ANALOG_REFERENCE4 = 0x04, + #[doc = "Use AIN5 as external analog reference"] + ANALOG_REFERENCE5 = 0x05, + #[doc = "Use AIN6 as external analog reference"] + ANALOG_REFERENCE6 = 0x06, + #[doc = "Use AIN7 as external analog reference"] + ANALOG_REFERENCE7 = 0x07, + } + impl Extrefsel { + #[inline(always)] + pub const fn from_bits(val: u8) -> Extrefsel { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for Extrefsel { + #[inline(always)] + fn from(val: u8) -> Extrefsel { + Extrefsel::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: Extrefsel) -> u8 { + Extrefsel::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum Hyst { + #[doc = "Comparator hysteresis disabled"] + NO_HYST = 0x0, + #[doc = "Comparator hysteresis enabled"] + HYST50M_V = 0x01, + } + impl Hyst { + #[inline(always)] + pub const fn from_bits(val: u8) -> Hyst { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for Hyst { + #[inline(always)] + fn from(val: u8) -> Hyst { + Hyst::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: Hyst) -> u8 { + Hyst::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum Main { + #[doc = "Single-ended mode"] + SE = 0x0, + #[doc = "Differential mode"] + DIFF = 0x01, + } + impl Main { + #[inline(always)] + pub const fn from_bits(val: u8) -> Main { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for Main { + #[inline(always)] + fn from(val: u8) -> Main { + Main::from_bits(val) + } + } + impl From
for u8 { + #[inline(always)] + fn from(val: Main) -> u8 { + Main::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum PselPsel { + #[doc = "AIN0 selected as analog input"] + ANALOG_INPUT0 = 0x0, + #[doc = "AIN1 selected as analog input"] + ANALOG_INPUT1 = 0x01, + #[doc = "AIN2 selected as analog input"] + ANALOG_INPUT2 = 0x02, + #[doc = "AIN3 selected as analog input"] + ANALOG_INPUT3 = 0x03, + #[doc = "AIN4 selected as analog input"] + ANALOG_INPUT4 = 0x04, + #[doc = "AIN5 selected as analog input"] + ANALOG_INPUT5 = 0x05, + #[doc = "AIN6 selected as analog input"] + ANALOG_INPUT6 = 0x06, + #[doc = "AIN7 selected as analog input"] + ANALOG_INPUT7 = 0x07, + } + impl PselPsel { + #[inline(always)] + pub const fn from_bits(val: u8) -> PselPsel { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for PselPsel { + #[inline(always)] + fn from(val: u8) -> PselPsel { + PselPsel::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: PselPsel) -> u8 { + PselPsel::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum Refsel { + #[doc = "VREF = internal 1.2 V reference (VDD >= 1.7 V)"] + INT1V2 = 0x0, + #[doc = "VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V)"] + INT1V8 = 0x01, + #[doc = "VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V)"] + INT2V4 = 0x02, + _RESERVED_3 = 0x03, + #[doc = "VREF = VDD"] + VDD = 0x04, + #[doc = "VREF = AREF"] + AREF = 0x05, + _RESERVED_6 = 0x06, + _RESERVED_7 = 0x07, + } + impl Refsel { + #[inline(always)] + pub const fn from_bits(val: u8) -> Refsel { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for Refsel { + #[inline(always)] + fn from(val: u8) -> Refsel { + Refsel::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: Refsel) -> u8 { + Refsel::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum Result { + #[doc = "Input voltage is below the threshold (VIN+ < VIN-)"] + BELOW = 0x0, + #[doc = "Input voltage is above the threshold (VIN+ > VIN-)"] + ABOVE = 0x01, + } + impl Result { + #[inline(always)] + pub const fn from_bits(val: u8) -> Result { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for Result { + #[inline(always)] + fn from(val: u8) -> Result { + Result::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: Result) -> u8 { + Result::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum Sp { + #[doc = "Low-power mode"] + LOW = 0x0, + #[doc = "Normal mode"] + NORMAL = 0x01, + #[doc = "High-speed mode"] + HIGH = 0x02, + _RESERVED_3 = 0x03, + } + impl Sp { + #[inline(always)] + pub const fn from_bits(val: u8) -> Sp { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for Sp { + #[inline(always)] + fn from(val: u8) -> Sp { + Sp::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: Sp) -> u8 { + Sp::to_bits(val) + } + } + } +} +pub mod cryptocell { + #[doc = "CRYPTOCELL register interface"] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cryptocell { + ptr: *mut u8, + } + unsafe impl Send for Cryptocell {} + unsafe impl Sync for Cryptocell {} + impl Cryptocell { + #[inline(always)] + pub const unsafe fn from_ptr(ptr: *mut ()) -> Self { + Self { ptr: ptr as _ } + } + #[inline(always)] + pub const fn as_ptr(&self) -> *mut () { + self.ptr as _ + } + #[doc = "Enable CRYPTOCELL subsystem."] + #[inline(always)] + pub const fn enable(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0500usize) as _) } + } + } + pub mod regs { + #[doc = "Enable CRYPTOCELL subsystem."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Enable(pub u32); + impl Enable { + #[doc = "Enable or disable the CRYPTOCELL subsystem."] + #[inline(always)] + pub const fn enable(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Enable or disable the CRYPTOCELL subsystem."] + #[inline(always)] + pub fn set_enable(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + } + impl Default for Enable { + #[inline(always)] + fn default() -> Enable { + Enable(0) + } } } } @@ -3160,24 +9619,24 @@ pub mod ecb { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Inten(pub u32); impl Inten { - #[doc = "Write '1' to disable interrupt for ENDECB event"] + #[doc = "Write '1' to disable interrupt for event ENDECB"] #[inline(always)] pub const fn endecb(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for ENDECB event"] + #[doc = "Write '1' to disable interrupt for event ENDECB"] #[inline(always)] pub fn set_endecb(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - #[doc = "Write '1' to disable interrupt for ERRORECB event"] + #[doc = "Write '1' to disable interrupt for event ERRORECB"] #[inline(always)] pub const fn errorecb(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for ERRORECB event"] + #[doc = "Write '1' to disable interrupt for event ERRORECB"] #[inline(always)] pub fn set_errorecb(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); @@ -3192,7 +9651,7 @@ pub mod ecb { } } pub mod egu { - #[doc = "Event Generator Unit 0"] + #[doc = "Event generator unit 0"] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Egu { ptr: *mut u8, @@ -3208,13 +9667,13 @@ pub mod egu { pub const fn as_ptr(&self) -> *mut () { self.ptr as _ } - #[doc = "Description collection\\[n\\]: Trigger n for triggering the corresponding TRIGGERED\\[n\\] event"] + #[doc = "Description collection: Trigger n for triggering the corresponding TRIGGERED\\[n\\] event"] #[inline(always)] pub const fn tasks_trigger(self, n: usize) -> crate::common::Reg { assert!(n < 16usize); unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize + n * 4usize) as _) } } - #[doc = "Description collection\\[n\\]: Event number n generated by triggering the corresponding TRIGGER\\[n\\] task"] + #[doc = "Description collection: Event number n generated by triggering the corresponding TRIGGER\\[n\\] task"] #[inline(always)] pub const fn events_triggered( self, @@ -3245,7 +9704,7 @@ pub mod egu { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Inten(pub u32); impl Inten { - #[doc = "Enable or disable interrupt for TRIGGERED\\[0\\] event"] + #[doc = "Enable or disable interrupt for event TRIGGERED\\[0\\]"] #[inline(always)] pub const fn triggered(&self, n: usize) -> bool { assert!(n < 16usize); @@ -3253,7 +9712,7 @@ pub mod egu { let val = (self.0 >> offs) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for TRIGGERED\\[0\\] event"] + #[doc = "Enable or disable interrupt for event TRIGGERED\\[0\\]"] #[inline(always)] pub fn set_triggered(&mut self, n: usize, val: bool) { assert!(n < 16usize); @@ -3296,19 +9755,19 @@ pub mod ficr { pub const fn codesize(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) } } - #[doc = "Description collection\\[n\\]: Device identifier"] + #[doc = "Description collection: Device identifier"] #[inline(always)] pub const fn deviceid(self, n: usize) -> crate::common::Reg { assert!(n < 2usize); unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x60usize + n * 4usize) as _) } } - #[doc = "Description collection\\[n\\]: Encryption root, word n"] + #[doc = "Description collection: Encryption root, word n"] #[inline(always)] pub const fn er(self, n: usize) -> crate::common::Reg { assert!(n < 4usize); unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x80usize + n * 4usize) as _) } } - #[doc = "Description collection\\[n\\]: Identity Root, word n"] + #[doc = "Description collection: Identity Root, word n"] #[inline(always)] pub const fn ir(self, n: usize) -> crate::common::Reg { assert!(n < 4usize); @@ -3321,7 +9780,7 @@ pub mod ficr { ) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xa0usize) as _) } } - #[doc = "Description collection\\[n\\]: Device address n"] + #[doc = "Description collection: Device address n"] #[inline(always)] pub const fn deviceaddr(self, n: usize) -> crate::common::Reg { assert!(n < 2usize); @@ -3332,7 +9791,7 @@ pub mod ficr { pub const fn info(self) -> Info { unsafe { Info::from_ptr(self.ptr.add(0x0100usize) as _) } } - #[doc = "Description collection\\[n\\]: Production test signature n"] + #[doc = "Description collection: Production test signature n"] #[inline(always)] pub const fn prodtest( self, @@ -3378,9 +9837,9 @@ pub mod ficr { pub const fn part(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } - #[doc = "Build code (hardware version and production configuration)"] + #[doc = "Build code, last two letters of Package Variant and first two characters of Build Code, encoded in ASCII."] #[inline(always)] - pub const fn variant(self) -> crate::common::Reg { + pub const fn variant(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "Package option"] @@ -3398,12 +9857,6 @@ pub mod ficr { pub const fn flash(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } } - #[doc = "Unspecified"] - #[inline(always)] - pub const fn unused8(self, n: usize) -> crate::common::Reg { - assert!(n < 3usize); - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize + n * 4usize) as _) } - } } #[doc = "Unspecified"] #[derive(Copy, Clone, Eq, PartialEq)] @@ -3421,22 +9874,22 @@ pub mod ficr { pub const fn as_ptr(&self) -> *mut () { self.ptr as _ } - #[doc = "Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST."] + #[doc = "Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST."] #[inline(always)] pub const fn tagheader0(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } - #[doc = "Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST."] + #[doc = "Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST."] #[inline(always)] pub const fn tagheader1(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } - #[doc = "Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST."] + #[doc = "Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST."] #[inline(always)] pub const fn tagheader2(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } - #[doc = "Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST."] + #[doc = "Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST."] #[inline(always)] pub const fn tagheader3(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } @@ -3973,7 +10426,7 @@ pub mod ficr { Part(0) } } - #[doc = "Description collection\\[n\\]: Production test signature n"] + #[doc = "Description collection: Production test signature n"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Prodtest(pub u32); @@ -4136,7 +10589,7 @@ pub mod ficr { T4(0) } } - #[doc = "Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST."] + #[doc = "Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Tagheader0(pub u32); @@ -4192,7 +10645,7 @@ pub mod ficr { Tagheader0(0) } } - #[doc = "Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST."] + #[doc = "Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Tagheader1(pub u32); @@ -4248,7 +10701,7 @@ pub mod ficr { Tagheader1(0) } } - #[doc = "Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST."] + #[doc = "Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Tagheader2(pub u32); @@ -4304,7 +10757,7 @@ pub mod ficr { Tagheader2(0) } } - #[doc = "Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST."] + #[doc = "Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Tagheader3(pub u32); @@ -4360,30 +10813,6 @@ pub mod ficr { Tagheader3(0) } } - #[doc = "Build code (hardware version and production configuration)"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Variant(pub u32); - impl Variant { - #[doc = "Build code (hardware version and production configuration). Encoded as ASCII."] - #[inline(always)] - pub const fn variant(&self) -> super::vals::Variant { - let val = (self.0 >> 0usize) & 0xffff_ffff; - super::vals::Variant::from_bits(val as u32) - } - #[doc = "Build code (hardware version and production configuration). Encoded as ASCII."] - #[inline(always)] - pub fn set_variant(&mut self, val: super::vals::Variant) { - self.0 = (self.0 & !(0xffff_ffff << 0usize)) - | (((val.to_bits() as u32) & 0xffff_ffff) << 0usize); - } - } - impl Default for Variant { - #[inline(always)] - fn default() -> Variant { - Variant(0) - } - } } pub mod vals { #[repr(u8)] @@ -4420,15 +10849,15 @@ pub mod ficr { #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub struct Flash(pub u32); impl Flash { - #[doc = "128 kByte FLASH"] + #[doc = "128 kB FLASH"] pub const K128: Self = Self(0x80); - #[doc = "256 kByte FLASH"] + #[doc = "256 kB FLASH"] pub const K256: Self = Self(0x0100); - #[doc = "512 kByte FLASH"] + #[doc = "512 kB FLASH"] pub const K512: Self = Self(0x0200); - #[doc = "1 MByte FLASH"] + #[doc = "1 MB FLASH"] pub const K1024: Self = Self(0x0400); - #[doc = "2 MByte FLASH"] + #[doc = "2 MB FLASH"] pub const K2048: Self = Self(0x0800); #[doc = "Unspecified"] pub const UNSPECIFIED: Self = Self(0xffff_ffff); @@ -4457,8 +10886,12 @@ pub mod ficr { #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub struct Package(pub u32); impl Package { - #[doc = "QIxx - 73-pin aQFN"] + #[doc = "QFxx - 6x6 48-pin QFN"] + pub const QF: Self = Self(0x2000); + #[doc = "QIxx - 7x7 73-pin aQFN"] pub const QI: Self = Self(0x2004); + #[doc = "CKxx - 3.544 x 3.607 WLCSP"] + pub const CK: Self = Self(0x2005); #[doc = "Unspecified"] pub const UNSPECIFIED: Self = Self(0xffff_ffff); } @@ -4544,15 +10977,15 @@ pub mod ficr { #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub struct Ram(pub u32); impl Ram { - #[doc = "16 kByte RAM"] + #[doc = "16 kB RAM"] pub const K16: Self = Self(0x10); - #[doc = "32 kByte RAM"] + #[doc = "32 kB RAM"] pub const K32: Self = Self(0x20); - #[doc = "64 kByte RAM"] + #[doc = "64 kB RAM"] pub const K64: Self = Self(0x40); - #[doc = "128 kByte RAM"] + #[doc = "128 kB RAM"] pub const K128: Self = Self(0x80); - #[doc = "256 kByte RAM"] + #[doc = "256 kB RAM"] pub const K256: Self = Self(0x0100); #[doc = "Unspecified"] pub const UNSPECIFIED: Self = Self(0xffff_ffff); @@ -4577,47 +11010,6 @@ pub mod ficr { Ram::to_bits(val) } } - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub struct Variant(pub u32); - impl Variant { - #[doc = "AAAA"] - pub const AAAA: Self = Self(0x4141_4141); - #[doc = "AAAB"] - pub const AAAB: Self = Self(0x4141_4142); - #[doc = "AABA"] - pub const AABA: Self = Self(0x4141_4241); - #[doc = "AABB"] - pub const AABB: Self = Self(0x4141_4242); - #[doc = "AACA"] - pub const AACA: Self = Self(0x4141_4341); - #[doc = "BAAA"] - pub const BAAA: Self = Self(0x4241_4141); - #[doc = "CAAA"] - pub const CAAA: Self = Self(0x4341_4141); - #[doc = "Unspecified"] - pub const UNSPECIFIED: Self = Self(0xffff_ffff); - } - impl Variant { - pub const fn from_bits(val: u32) -> Variant { - Self(val & 0xffff_ffff) - } - pub const fn to_bits(self) -> u32 { - self.0 - } - } - impl From for Variant { - #[inline(always)] - fn from(val: u32) -> Variant { - Variant::from_bits(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: Variant) -> u32 { - Variant::to_bits(val) - } - } } } pub mod fpu { @@ -4645,7 +11037,7 @@ pub mod fpu { } } pub mod gpio { - #[doc = "GPIO Port 1"] + #[doc = "GPIO Port 0"] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Gpio { ptr: *mut u8, @@ -4701,12 +11093,12 @@ pub mod gpio { pub const fn latch(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0520usize) as _) } } - #[doc = "Select between default DETECT signal behaviour and LDETECT mode"] + #[doc = "Select between default DETECT signal behavior and LDETECT mode"] #[inline(always)] pub const fn detectmode(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0524usize) as _) } } - #[doc = "Description collection\\[n\\]: Configuration of GPIO pins"] + #[doc = "Description collection: Configuration of GPIO pins"] #[inline(always)] pub const fn pin_cnf( self, @@ -4717,18 +11109,18 @@ pub mod gpio { } } pub mod regs { - #[doc = "Select between default DETECT signal behaviour and LDETECT mode"] + #[doc = "Select between default DETECT signal behavior and LDETECT mode"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Detectmode(pub u32); impl Detectmode { - #[doc = "Select between default DETECT signal behaviour and LDETECT mode"] + #[doc = "Select between default DETECT signal behavior and LDETECT mode"] #[inline(always)] pub const fn detectmode(&self) -> super::vals::Detectmode { let val = (self.0 >> 0usize) & 0x01; super::vals::Detectmode::from_bits(val as u8) } - #[doc = "Select between default DETECT signal behaviour and LDETECT mode"] + #[doc = "Select between default DETECT signal behavior and LDETECT mode"] #[inline(always)] pub fn set_detectmode(&mut self, val: super::vals::Detectmode) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); @@ -4956,7 +11348,7 @@ pub mod gpio { Outset(0) } } - #[doc = "Description collection\\[n\\]: Configuration of GPIO pins"] + #[doc = "Description collection: Configuration of GPIO pins"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct PinCnf(pub u32); @@ -5031,7 +11423,7 @@ pub mod gpio { pub enum Detectmode { #[doc = "DETECT directly connected to PIN DETECT signals"] DEFAULT = 0x0, - #[doc = "Use the latched LDETECT behaviour"] + #[doc = "Use the latched LDETECT behavior"] LDETECT = 0x01, } impl Detectmode { @@ -5243,25 +11635,25 @@ pub mod gpiote { pub const fn as_ptr(&self) -> *mut () { self.ptr as _ } - #[doc = "Description collection\\[n\\]: Task for writing to pin specified in CONFIG\\[n\\].PSEL. Action on pin is configured in CONFIG\\[n\\].POLARITY."] + #[doc = "Description collection: Task for writing to pin specified in CONFIG\\[n\\].PSEL. Action on pin is configured in CONFIG\\[n\\].POLARITY."] #[inline(always)] pub const fn tasks_out(self, n: usize) -> crate::common::Reg { assert!(n < 8usize); unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize + n * 4usize) as _) } } - #[doc = "Description collection\\[n\\]: Task for writing to pin specified in CONFIG\\[n\\].PSEL. Action on pin is to set it high."] + #[doc = "Description collection: Task for writing to pin specified in CONFIG\\[n\\].PSEL. Action on pin is to set it high."] #[inline(always)] pub const fn tasks_set(self, n: usize) -> crate::common::Reg { assert!(n < 8usize); unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x30usize + n * 4usize) as _) } } - #[doc = "Description collection\\[n\\]: Task for writing to pin specified in CONFIG\\[n\\].PSEL. Action on pin is to set it low."] + #[doc = "Description collection: Task for writing to pin specified in CONFIG\\[n\\].PSEL. Action on pin is to set it low."] #[inline(always)] pub const fn tasks_clr(self, n: usize) -> crate::common::Reg { assert!(n < 8usize); unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x60usize + n * 4usize) as _) } } - #[doc = "Description collection\\[n\\]: Event generated from pin specified in CONFIG\\[n\\].PSEL"] + #[doc = "Description collection: Event generated from pin specified in CONFIG\\[n\\].PSEL"] #[inline(always)] pub const fn events_in(self, n: usize) -> crate::common::Reg { assert!(n < 8usize); @@ -5282,7 +11674,7 @@ pub mod gpiote { pub const fn intenclr(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0308usize) as _) } } - #[doc = "Description collection\\[n\\]: Configuration for OUT\\[n\\], SET\\[n\\] and CLR\\[n\\] tasks and IN\\[n\\] event"] + #[doc = "Description collection: Configuration for OUT\\[n\\], SET\\[n\\], and CLR\\[n\\] tasks and IN\\[n\\] event"] #[inline(always)] pub const fn config(self, n: usize) -> crate::common::Reg { assert!(n < 8usize); @@ -5290,7 +11682,7 @@ pub mod gpiote { } } pub mod regs { - #[doc = "Description collection\\[n\\]: Configuration for OUT\\[n\\], SET\\[n\\] and CLR\\[n\\] tasks and IN\\[n\\] event"] + #[doc = "Description collection: Configuration for OUT\\[n\\], SET\\[n\\], and CLR\\[n\\] tasks and IN\\[n\\] event"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Config(pub u32); @@ -5306,13 +11698,13 @@ pub mod gpiote { pub fn set_mode(&mut self, val: super::vals::Mode) { self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); } - #[doc = "GPIO number associated with SET\\[n\\], CLR\\[n\\] and OUT\\[n\\] tasks and IN\\[n\\] event"] + #[doc = "GPIO number associated with SET\\[n\\], CLR\\[n\\], and OUT\\[n\\] tasks and IN\\[n\\] event"] #[inline(always)] pub const fn psel(&self) -> u8 { let val = (self.0 >> 8usize) & 0x1f; val as u8 } - #[doc = "GPIO number associated with SET\\[n\\], CLR\\[n\\] and OUT\\[n\\] tasks and IN\\[n\\] event"] + #[doc = "GPIO number associated with SET\\[n\\], CLR\\[n\\], and OUT\\[n\\] tasks and IN\\[n\\] event"] #[inline(always)] pub fn set_psel(&mut self, val: u8) { self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize); @@ -5364,101 +11756,101 @@ pub mod gpiote { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Inten(pub u32); impl Inten { - #[doc = "Write '1' to disable interrupt for IN\\[0\\] event"] + #[doc = "Write '1' to disable interrupt for event IN\\[0\\]"] #[inline(always)] pub const fn in0(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for IN\\[0\\] event"] + #[doc = "Write '1' to disable interrupt for event IN\\[0\\]"] #[inline(always)] pub fn set_in0(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - #[doc = "Write '1' to disable interrupt for IN\\[1\\] event"] + #[doc = "Write '1' to disable interrupt for event IN\\[1\\]"] #[inline(always)] pub const fn in1(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for IN\\[1\\] event"] + #[doc = "Write '1' to disable interrupt for event IN\\[1\\]"] #[inline(always)] pub fn set_in1(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } - #[doc = "Write '1' to disable interrupt for IN\\[2\\] event"] + #[doc = "Write '1' to disable interrupt for event IN\\[2\\]"] #[inline(always)] pub const fn in2(&self) -> bool { let val = (self.0 >> 2usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for IN\\[2\\] event"] + #[doc = "Write '1' to disable interrupt for event IN\\[2\\]"] #[inline(always)] pub fn set_in2(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); } - #[doc = "Write '1' to disable interrupt for IN\\[3\\] event"] + #[doc = "Write '1' to disable interrupt for event IN\\[3\\]"] #[inline(always)] pub const fn in3(&self) -> bool { let val = (self.0 >> 3usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for IN\\[3\\] event"] + #[doc = "Write '1' to disable interrupt for event IN\\[3\\]"] #[inline(always)] pub fn set_in3(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); } - #[doc = "Write '1' to disable interrupt for IN\\[4\\] event"] + #[doc = "Write '1' to disable interrupt for event IN\\[4\\]"] #[inline(always)] pub const fn in4(&self) -> bool { let val = (self.0 >> 4usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for IN\\[4\\] event"] + #[doc = "Write '1' to disable interrupt for event IN\\[4\\]"] #[inline(always)] pub fn set_in4(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); } - #[doc = "Write '1' to disable interrupt for IN\\[5\\] event"] + #[doc = "Write '1' to disable interrupt for event IN\\[5\\]"] #[inline(always)] pub const fn in5(&self) -> bool { let val = (self.0 >> 5usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for IN\\[5\\] event"] + #[doc = "Write '1' to disable interrupt for event IN\\[5\\]"] #[inline(always)] pub fn set_in5(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); } - #[doc = "Write '1' to disable interrupt for IN\\[6\\] event"] + #[doc = "Write '1' to disable interrupt for event IN\\[6\\]"] #[inline(always)] pub const fn in6(&self) -> bool { let val = (self.0 >> 6usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for IN\\[6\\] event"] + #[doc = "Write '1' to disable interrupt for event IN\\[6\\]"] #[inline(always)] pub fn set_in6(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); } - #[doc = "Write '1' to disable interrupt for IN\\[7\\] event"] + #[doc = "Write '1' to disable interrupt for event IN\\[7\\]"] #[inline(always)] pub const fn in7(&self) -> bool { let val = (self.0 >> 7usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for IN\\[7\\] event"] + #[doc = "Write '1' to disable interrupt for event IN\\[7\\]"] #[inline(always)] pub fn set_in7(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); } - #[doc = "Write '1' to disable interrupt for PORT event"] + #[doc = "Write '1' to disable interrupt for event PORT"] #[inline(always)] pub const fn port(&self) -> bool { let val = (self.0 >> 31usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for PORT event"] + #[doc = "Write '1' to disable interrupt for event PORT"] #[inline(always)] pub fn set_port(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); @@ -5660,7 +12052,7 @@ pub mod i2s { pub const fn tasks_start(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } - #[doc = "Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the {event:STOPPED} event to be generated."] + #[doc = "Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated."] #[inline(always)] pub const fn tasks_stop(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } @@ -5938,35 +12330,35 @@ pub mod i2s { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Inten(pub u32); impl Inten { - #[doc = "Enable or disable interrupt for RXPTRUPD event"] + #[doc = "Enable or disable interrupt for event RXPTRUPD"] #[inline(always)] pub const fn rxptrupd(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for RXPTRUPD event"] + #[doc = "Enable or disable interrupt for event RXPTRUPD"] #[inline(always)] pub fn set_rxptrupd(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } - #[doc = "Enable or disable interrupt for STOPPED event"] + #[doc = "Enable or disable interrupt for event STOPPED"] #[inline(always)] pub const fn stopped(&self) -> bool { let val = (self.0 >> 2usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for STOPPED event"] + #[doc = "Enable or disable interrupt for event STOPPED"] #[inline(always)] pub fn set_stopped(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); } - #[doc = "Enable or disable interrupt for TXPTRUPD event"] + #[doc = "Enable or disable interrupt for event TXPTRUPD"] #[inline(always)] pub const fn txptrupd(&self) -> bool { let val = (self.0 >> 5usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for TXPTRUPD event"] + #[doc = "Enable or disable interrupt for event TXPTRUPD"] #[inline(always)] pub fn set_txptrupd(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); @@ -6288,16 +12680,6 @@ pub mod i2s { pub const _32MDIV10: Self = Self(0x1800_0000); #[doc = "32 MHz / 8 = 4.0 MHz"] pub const _32MDIV8: Self = Self(0x2000_0000); - #[doc = "32 MHz / 6 = 5.3333333 MHz"] - pub const _32MDIV6: Self = Self(0x2800_0000); - #[doc = "32 MHz / 5 = 6.4 MHz"] - pub const _32MDIV5: Self = Self(0x3000_0000); - #[doc = "32 MHz / 4 = 8.0 MHz"] - pub const _32MDIV4: Self = Self(0x4000_0000); - #[doc = "32 MHz / 3 = 10.6666667 MHz"] - pub const _32MDIV3: Self = Self(0x5000_0000); - #[doc = "32 MHz / 2 = 16.0 MHz"] - pub const _32MDIV2: Self = Self(0x8000_0000); } impl Mckfreq { pub const fn from_bits(val: u32) -> Mckfreq { @@ -6436,7 +12818,7 @@ pub mod i2s { } } pub mod lpcomp { - #[doc = "Low Power Comparator"] + #[doc = "Low-power comparator"] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Lpcomp { ptr: *mut u8, @@ -6487,7 +12869,7 @@ pub mod lpcomp { pub const fn events_cross(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x010cusize) as _) } } - #[doc = "Shortcut register"] + #[doc = "Shortcuts between local events and tasks"] #[inline(always)] pub const fn shorts(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0200usize) as _) } @@ -6636,46 +13018,46 @@ pub mod lpcomp { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Inten(pub u32); impl Inten { - #[doc = "Write '1' to disable interrupt for READY event"] + #[doc = "Write '1' to disable interrupt for event READY"] #[inline(always)] pub const fn ready(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for READY event"] + #[doc = "Write '1' to disable interrupt for event READY"] #[inline(always)] pub fn set_ready(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - #[doc = "Write '1' to disable interrupt for DOWN event"] + #[doc = "Write '1' to disable interrupt for event DOWN"] #[inline(always)] pub const fn down(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for DOWN event"] + #[doc = "Write '1' to disable interrupt for event DOWN"] #[inline(always)] pub fn set_down(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } - #[doc = "Write '1' to disable interrupt for UP event"] + #[doc = "Write '1' to disable interrupt for event UP"] #[inline(always)] pub const fn up(&self) -> bool { let val = (self.0 >> 2usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for UP event"] + #[doc = "Write '1' to disable interrupt for event UP"] #[inline(always)] pub fn set_up(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); } - #[doc = "Write '1' to disable interrupt for CROSS event"] + #[doc = "Write '1' to disable interrupt for event CROSS"] #[inline(always)] pub const fn cross(&self) -> bool { let val = (self.0 >> 3usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for CROSS event"] + #[doc = "Write '1' to disable interrupt for event CROSS"] #[inline(always)] pub fn set_cross(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); @@ -6756,62 +13138,62 @@ pub mod lpcomp { Result(0) } } - #[doc = "Shortcut register"] + #[doc = "Shortcuts between local events and tasks"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Shorts(pub u32); impl Shorts { - #[doc = "Shortcut between READY event and SAMPLE task"] + #[doc = "Shortcut between event READY and task SAMPLE"] #[inline(always)] pub const fn ready_sample(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Shortcut between READY event and SAMPLE task"] + #[doc = "Shortcut between event READY and task SAMPLE"] #[inline(always)] pub fn set_ready_sample(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - #[doc = "Shortcut between READY event and STOP task"] + #[doc = "Shortcut between event READY and task STOP"] #[inline(always)] pub const fn ready_stop(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; val != 0 } - #[doc = "Shortcut between READY event and STOP task"] + #[doc = "Shortcut between event READY and task STOP"] #[inline(always)] pub fn set_ready_stop(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } - #[doc = "Shortcut between DOWN event and STOP task"] + #[doc = "Shortcut between event DOWN and task STOP"] #[inline(always)] pub const fn down_stop(&self) -> bool { let val = (self.0 >> 2usize) & 0x01; val != 0 } - #[doc = "Shortcut between DOWN event and STOP task"] + #[doc = "Shortcut between event DOWN and task STOP"] #[inline(always)] pub fn set_down_stop(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); } - #[doc = "Shortcut between UP event and STOP task"] + #[doc = "Shortcut between event UP and task STOP"] #[inline(always)] pub const fn up_stop(&self) -> bool { let val = (self.0 >> 3usize) & 0x01; val != 0 } - #[doc = "Shortcut between UP event and STOP task"] + #[doc = "Shortcut between event UP and task STOP"] #[inline(always)] pub fn set_up_stop(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); } - #[doc = "Shortcut between CROSS event and STOP task"] + #[doc = "Shortcut between event CROSS and task STOP"] #[inline(always)] pub const fn cross_stop(&self) -> bool { let val = (self.0 >> 4usize) & 0x01; val != 0 } - #[doc = "Shortcut between CROSS event and STOP task"] + #[doc = "Shortcut between event CROSS and task STOP"] #[inline(always)] pub fn set_cross_stop(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); @@ -7023,9 +13405,9 @@ pub mod lpcomp { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Result { - #[doc = "Input voltage is below the reference threshold (VIN+ < VIN-)."] + #[doc = "Input voltage is below the reference threshold (VIN+ < VIN-)"] BELOW = 0x0, - #[doc = "Input voltage is above the reference threshold (VIN+ > VIN-)."] + #[doc = "Input voltage is above the reference threshold (VIN+ > VIN-)"] ABOVE = 0x01, } impl Result { @@ -7053,7 +13435,7 @@ pub mod lpcomp { } } pub mod mwu { - #[doc = "Unspecified"] + #[doc = "Peripheral events."] #[derive(Copy, Clone, Eq, PartialEq)] pub struct EventsPregion { ptr: *mut u8, @@ -7069,18 +13451,18 @@ pub mod mwu { pub const fn as_ptr(&self) -> *mut () { self.ptr as _ } - #[doc = "Description cluster\\[n\\]: Write access to peripheral region n detected"] + #[doc = "Description cluster: Write access to peripheral region n detected"] #[inline(always)] pub const fn wa(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } - #[doc = "Description cluster\\[n\\]: Read access to peripheral region n detected"] + #[doc = "Description cluster: Read access to peripheral region n detected"] #[inline(always)] pub const fn ra(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } } - #[doc = "Unspecified"] + #[doc = "Peripheral events."] #[derive(Copy, Clone, Eq, PartialEq)] pub struct EventsRegion { ptr: *mut u8, @@ -7096,12 +13478,12 @@ pub mod mwu { pub const fn as_ptr(&self) -> *mut () { self.ptr as _ } - #[doc = "Description cluster\\[n\\]: Write access to region n detected"] + #[doc = "Description cluster: Write access to region n detected"] #[inline(always)] pub const fn wa(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } - #[doc = "Description cluster\\[n\\]: Read access to region n detected"] + #[doc = "Description cluster: Read access to region n detected"] #[inline(always)] pub const fn ra(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } @@ -7123,13 +13505,13 @@ pub mod mwu { pub const fn as_ptr(&self) -> *mut () { self.ptr as _ } - #[doc = "Unspecified"] + #[doc = "Peripheral events."] #[inline(always)] pub const fn events_region(self, n: usize) -> EventsRegion { assert!(n < 4usize); unsafe { EventsRegion::from_ptr(self.ptr.add(0x0100usize + n * 8usize) as _) } } - #[doc = "Unspecified"] + #[doc = "Peripheral events."] #[inline(always)] pub const fn events_pregion(self, n: usize) -> EventsPregion { assert!(n < 2usize); @@ -7150,17 +13532,17 @@ pub mod mwu { pub const fn intenclr(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0308usize) as _) } } - #[doc = "Enable or disable non-maskable interrupt"] + #[doc = "Enable or disable interrupt"] #[inline(always)] pub const fn nmien(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0320usize) as _) } } - #[doc = "Enable non-maskable interrupt"] + #[doc = "Enable interrupt"] #[inline(always)] pub const fn nmienset(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0324usize) as _) } } - #[doc = "Disable non-maskable interrupt"] + #[doc = "Disable interrupt"] #[inline(always)] pub const fn nmienclr(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0328usize) as _) } @@ -7215,12 +13597,12 @@ pub mod mwu { pub const fn as_ptr(&self) -> *mut () { self.ptr as _ } - #[doc = "Description cluster\\[n\\]: Source of event/interrupt in region n, write access detected while corresponding subregion was enabled for watching"] + #[doc = "Description cluster: Source of event/interrupt in region n, write access detected while corresponding subregion was enabled for watching"] #[inline(always)] pub const fn substatwa(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } - #[doc = "Description cluster\\[n\\]: Source of event/interrupt in region n, read access detected while corresponding subregion was enabled for watching"] + #[doc = "Description cluster: Source of event/interrupt in region n, read access detected while corresponding subregion was enabled for watching"] #[inline(always)] pub const fn substatra(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } @@ -7242,17 +13624,17 @@ pub mod mwu { pub const fn as_ptr(&self) -> *mut () { self.ptr as _ } - #[doc = "Description cluster\\[n\\]: Reserved for future use"] + #[doc = "Description cluster: Reserved for future use"] #[inline(always)] pub const fn start(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } - #[doc = "Description cluster\\[n\\]: Reserved for future use"] + #[doc = "Description cluster: Reserved for future use"] #[inline(always)] pub const fn end(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } - #[doc = "Description cluster\\[n\\]: Subregions of region n"] + #[doc = "Description cluster: Subregions of region n"] #[inline(always)] pub const fn subs(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } @@ -7274,12 +13656,12 @@ pub mod mwu { pub const fn as_ptr(&self) -> *mut () { self.ptr as _ } - #[doc = "Description cluster\\[n\\]: Start address for region n"] + #[doc = "Description cluster: Start address for region n"] #[inline(always)] pub const fn start(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } - #[doc = "Description cluster\\[n\\]: End address of region n"] + #[doc = "Description cluster: End address of region n"] #[inline(always)] pub const fn end(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } @@ -7291,134 +13673,134 @@ pub mod mwu { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Inten(pub u32); impl Inten { - #[doc = "Enable or disable interrupt for REGION\\[0\\].WA event"] + #[doc = "Enable or disable interrupt for event REGION0WA"] #[inline(always)] pub const fn region0wa(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for REGION\\[0\\].WA event"] + #[doc = "Enable or disable interrupt for event REGION0WA"] #[inline(always)] pub fn set_region0wa(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - #[doc = "Enable or disable interrupt for REGION\\[0\\].RA event"] + #[doc = "Enable or disable interrupt for event REGION0RA"] #[inline(always)] pub const fn region0ra(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for REGION\\[0\\].RA event"] + #[doc = "Enable or disable interrupt for event REGION0RA"] #[inline(always)] pub fn set_region0ra(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } - #[doc = "Enable or disable interrupt for REGION\\[1\\].WA event"] + #[doc = "Enable or disable interrupt for event REGION1WA"] #[inline(always)] pub const fn region1wa(&self) -> bool { let val = (self.0 >> 2usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for REGION\\[1\\].WA event"] + #[doc = "Enable or disable interrupt for event REGION1WA"] #[inline(always)] pub fn set_region1wa(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); } - #[doc = "Enable or disable interrupt for REGION\\[1\\].RA event"] + #[doc = "Enable or disable interrupt for event REGION1RA"] #[inline(always)] pub const fn region1ra(&self) -> bool { let val = (self.0 >> 3usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for REGION\\[1\\].RA event"] + #[doc = "Enable or disable interrupt for event REGION1RA"] #[inline(always)] pub fn set_region1ra(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); } - #[doc = "Enable or disable interrupt for REGION\\[2\\].WA event"] + #[doc = "Enable or disable interrupt for event REGION2WA"] #[inline(always)] pub const fn region2wa(&self) -> bool { let val = (self.0 >> 4usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for REGION\\[2\\].WA event"] + #[doc = "Enable or disable interrupt for event REGION2WA"] #[inline(always)] pub fn set_region2wa(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); } - #[doc = "Enable or disable interrupt for REGION\\[2\\].RA event"] + #[doc = "Enable or disable interrupt for event REGION2RA"] #[inline(always)] pub const fn region2ra(&self) -> bool { let val = (self.0 >> 5usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for REGION\\[2\\].RA event"] + #[doc = "Enable or disable interrupt for event REGION2RA"] #[inline(always)] pub fn set_region2ra(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); } - #[doc = "Enable or disable interrupt for REGION\\[3\\].WA event"] + #[doc = "Enable or disable interrupt for event REGION3WA"] #[inline(always)] pub const fn region3wa(&self) -> bool { let val = (self.0 >> 6usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for REGION\\[3\\].WA event"] + #[doc = "Enable or disable interrupt for event REGION3WA"] #[inline(always)] pub fn set_region3wa(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); } - #[doc = "Enable or disable interrupt for REGION\\[3\\].RA event"] + #[doc = "Enable or disable interrupt for event REGION3RA"] #[inline(always)] pub const fn region3ra(&self) -> bool { let val = (self.0 >> 7usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for REGION\\[3\\].RA event"] + #[doc = "Enable or disable interrupt for event REGION3RA"] #[inline(always)] pub fn set_region3ra(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); } - #[doc = "Enable or disable interrupt for PREGION\\[0\\].WA event"] + #[doc = "Enable or disable interrupt for event PREGION0WA"] #[inline(always)] pub const fn pregion0wa(&self) -> bool { let val = (self.0 >> 24usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for PREGION\\[0\\].WA event"] + #[doc = "Enable or disable interrupt for event PREGION0WA"] #[inline(always)] pub fn set_pregion0wa(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); } - #[doc = "Enable or disable interrupt for PREGION\\[0\\].RA event"] + #[doc = "Enable or disable interrupt for event PREGION0RA"] #[inline(always)] pub const fn pregion0ra(&self) -> bool { let val = (self.0 >> 25usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for PREGION\\[0\\].RA event"] + #[doc = "Enable or disable interrupt for event PREGION0RA"] #[inline(always)] pub fn set_pregion0ra(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); } - #[doc = "Enable or disable interrupt for PREGION\\[1\\].WA event"] + #[doc = "Enable or disable interrupt for event PREGION1WA"] #[inline(always)] pub const fn pregion1wa(&self) -> bool { let val = (self.0 >> 26usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for PREGION\\[1\\].WA event"] + #[doc = "Enable or disable interrupt for event PREGION1WA"] #[inline(always)] pub fn set_pregion1wa(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); } - #[doc = "Enable or disable interrupt for PREGION\\[1\\].RA event"] + #[doc = "Enable or disable interrupt for event PREGION1RA"] #[inline(always)] pub const fn pregion1ra(&self) -> bool { let val = (self.0 >> 27usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for PREGION\\[1\\].RA event"] + #[doc = "Enable or disable interrupt for event PREGION1RA"] #[inline(always)] pub fn set_pregion1ra(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize); @@ -7430,139 +13812,139 @@ pub mod mwu { Inten(0) } } - #[doc = "Enable or disable non-maskable interrupt"] + #[doc = "Enable or disable interrupt"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Nmien(pub u32); impl Nmien { - #[doc = "Enable or disable non-maskable interrupt for REGION\\[0\\].WA event"] + #[doc = "Enable or disable interrupt for event REGION0WA"] #[inline(always)] pub const fn region0wa(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Enable or disable non-maskable interrupt for REGION\\[0\\].WA event"] + #[doc = "Enable or disable interrupt for event REGION0WA"] #[inline(always)] pub fn set_region0wa(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - #[doc = "Enable or disable non-maskable interrupt for REGION\\[0\\].RA event"] + #[doc = "Enable or disable interrupt for event REGION0RA"] #[inline(always)] pub const fn region0ra(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; val != 0 } - #[doc = "Enable or disable non-maskable interrupt for REGION\\[0\\].RA event"] + #[doc = "Enable or disable interrupt for event REGION0RA"] #[inline(always)] pub fn set_region0ra(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } - #[doc = "Enable or disable non-maskable interrupt for REGION\\[1\\].WA event"] + #[doc = "Enable or disable interrupt for event REGION1WA"] #[inline(always)] pub const fn region1wa(&self) -> bool { let val = (self.0 >> 2usize) & 0x01; val != 0 } - #[doc = "Enable or disable non-maskable interrupt for REGION\\[1\\].WA event"] + #[doc = "Enable or disable interrupt for event REGION1WA"] #[inline(always)] pub fn set_region1wa(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); } - #[doc = "Enable or disable non-maskable interrupt for REGION\\[1\\].RA event"] + #[doc = "Enable or disable interrupt for event REGION1RA"] #[inline(always)] pub const fn region1ra(&self) -> bool { let val = (self.0 >> 3usize) & 0x01; val != 0 } - #[doc = "Enable or disable non-maskable interrupt for REGION\\[1\\].RA event"] + #[doc = "Enable or disable interrupt for event REGION1RA"] #[inline(always)] pub fn set_region1ra(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); } - #[doc = "Enable or disable non-maskable interrupt for REGION\\[2\\].WA event"] + #[doc = "Enable or disable interrupt for event REGION2WA"] #[inline(always)] pub const fn region2wa(&self) -> bool { let val = (self.0 >> 4usize) & 0x01; val != 0 } - #[doc = "Enable or disable non-maskable interrupt for REGION\\[2\\].WA event"] + #[doc = "Enable or disable interrupt for event REGION2WA"] #[inline(always)] pub fn set_region2wa(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); } - #[doc = "Enable or disable non-maskable interrupt for REGION\\[2\\].RA event"] + #[doc = "Enable or disable interrupt for event REGION2RA"] #[inline(always)] pub const fn region2ra(&self) -> bool { let val = (self.0 >> 5usize) & 0x01; val != 0 } - #[doc = "Enable or disable non-maskable interrupt for REGION\\[2\\].RA event"] + #[doc = "Enable or disable interrupt for event REGION2RA"] #[inline(always)] pub fn set_region2ra(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); } - #[doc = "Enable or disable non-maskable interrupt for REGION\\[3\\].WA event"] + #[doc = "Enable or disable interrupt for event REGION3WA"] #[inline(always)] pub const fn region3wa(&self) -> bool { let val = (self.0 >> 6usize) & 0x01; val != 0 } - #[doc = "Enable or disable non-maskable interrupt for REGION\\[3\\].WA event"] + #[doc = "Enable or disable interrupt for event REGION3WA"] #[inline(always)] pub fn set_region3wa(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); } - #[doc = "Enable or disable non-maskable interrupt for REGION\\[3\\].RA event"] + #[doc = "Enable or disable interrupt for event REGION3RA"] #[inline(always)] pub const fn region3ra(&self) -> bool { let val = (self.0 >> 7usize) & 0x01; val != 0 } - #[doc = "Enable or disable non-maskable interrupt for REGION\\[3\\].RA event"] + #[doc = "Enable or disable interrupt for event REGION3RA"] #[inline(always)] pub fn set_region3ra(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); } - #[doc = "Enable or disable non-maskable interrupt for PREGION\\[0\\].WA event"] + #[doc = "Enable or disable interrupt for event PREGION0WA"] #[inline(always)] pub const fn pregion0wa(&self) -> bool { let val = (self.0 >> 24usize) & 0x01; val != 0 } - #[doc = "Enable or disable non-maskable interrupt for PREGION\\[0\\].WA event"] + #[doc = "Enable or disable interrupt for event PREGION0WA"] #[inline(always)] pub fn set_pregion0wa(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); } - #[doc = "Enable or disable non-maskable interrupt for PREGION\\[0\\].RA event"] + #[doc = "Enable or disable interrupt for event PREGION0RA"] #[inline(always)] pub const fn pregion0ra(&self) -> bool { let val = (self.0 >> 25usize) & 0x01; val != 0 } - #[doc = "Enable or disable non-maskable interrupt for PREGION\\[0\\].RA event"] + #[doc = "Enable or disable interrupt for event PREGION0RA"] #[inline(always)] pub fn set_pregion0ra(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); } - #[doc = "Enable or disable non-maskable interrupt for PREGION\\[1\\].WA event"] + #[doc = "Enable or disable interrupt for event PREGION1WA"] #[inline(always)] pub const fn pregion1wa(&self) -> bool { let val = (self.0 >> 26usize) & 0x01; val != 0 } - #[doc = "Enable or disable non-maskable interrupt for PREGION\\[1\\].WA event"] + #[doc = "Enable or disable interrupt for event PREGION1WA"] #[inline(always)] pub fn set_pregion1wa(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); } - #[doc = "Enable or disable non-maskable interrupt for PREGION\\[1\\].RA event"] + #[doc = "Enable or disable interrupt for event PREGION1RA"] #[inline(always)] pub const fn pregion1ra(&self) -> bool { let val = (self.0 >> 27usize) & 0x01; val != 0 } - #[doc = "Enable or disable non-maskable interrupt for PREGION\\[1\\].RA event"] + #[doc = "Enable or disable interrupt for event PREGION1RA"] #[inline(always)] pub fn set_pregion1ra(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize); @@ -7646,7 +14028,7 @@ pub mod mwu { Regionen(0) } } - #[doc = "Description cluster\\[n\\]: Subregions of region n"] + #[doc = "Description cluster: Subregions of region n"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Subs(pub u32); @@ -7673,7 +14055,7 @@ pub mod mwu { Subs(0) } } - #[doc = "Description cluster\\[n\\]: Source of event/interrupt in region n, read access detected while corresponding subregion was enabled for watching"] + #[doc = "Description cluster: Source of event/interrupt in region n, read access detected while corresponding subregion was enabled for watching"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Substatra(pub u32); @@ -7700,7 +14082,7 @@ pub mod mwu { Substatra(0) } } - #[doc = "Description cluster\\[n\\]: Source of event/interrupt in region n, write access detected while corresponding subregion was enabled for watching"] + #[doc = "Description cluster: Source of event/interrupt in region n, write access detected while corresponding subregion was enabled for watching"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Substatwa(pub u32); @@ -7878,7 +14260,7 @@ pub mod nfct { pub const fn events_started(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0150usize) as _) } } - #[doc = "Shortcut register"] + #[doc = "Shortcuts between local events and tasks"] #[inline(always)] pub const fn shorts(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0200usize) as _) } @@ -7985,7 +14367,7 @@ pub mod nfct { ) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0598usize) as _) } } - #[doc = "Controls the auto collision resolution function. This setting must be done before the NFCT peripheral is enabled."] + #[doc = "Controls the auto collision resolution function. This setting must be done before the NFCT peripheral is activated."] #[inline(always)] pub const fn autocolresconfig( self, @@ -8062,7 +14444,7 @@ pub mod nfct { } } pub mod regs { - #[doc = "Controls the auto collision resolution function. This setting must be done before the NFCT peripheral is enabled."] + #[doc = "Controls the auto collision resolution function. This setting must be done before the NFCT peripheral is activated."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Autocolresconfig(pub u32); @@ -8217,167 +14599,167 @@ pub mod nfct { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Inten(pub u32); impl Inten { - #[doc = "Enable or disable interrupt for READY event"] + #[doc = "Enable or disable interrupt for event READY"] #[inline(always)] pub const fn ready(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for READY event"] + #[doc = "Enable or disable interrupt for event READY"] #[inline(always)] pub fn set_ready(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - #[doc = "Enable or disable interrupt for FIELDDETECTED event"] + #[doc = "Enable or disable interrupt for event FIELDDETECTED"] #[inline(always)] pub const fn fielddetected(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for FIELDDETECTED event"] + #[doc = "Enable or disable interrupt for event FIELDDETECTED"] #[inline(always)] pub fn set_fielddetected(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } - #[doc = "Enable or disable interrupt for FIELDLOST event"] + #[doc = "Enable or disable interrupt for event FIELDLOST"] #[inline(always)] pub const fn fieldlost(&self) -> bool { let val = (self.0 >> 2usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for FIELDLOST event"] + #[doc = "Enable or disable interrupt for event FIELDLOST"] #[inline(always)] pub fn set_fieldlost(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); } - #[doc = "Enable or disable interrupt for TXFRAMESTART event"] + #[doc = "Enable or disable interrupt for event TXFRAMESTART"] #[inline(always)] pub const fn txframestart(&self) -> bool { let val = (self.0 >> 3usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for TXFRAMESTART event"] + #[doc = "Enable or disable interrupt for event TXFRAMESTART"] #[inline(always)] pub fn set_txframestart(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); } - #[doc = "Enable or disable interrupt for TXFRAMEEND event"] + #[doc = "Enable or disable interrupt for event TXFRAMEEND"] #[inline(always)] pub const fn txframeend(&self) -> bool { let val = (self.0 >> 4usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for TXFRAMEEND event"] + #[doc = "Enable or disable interrupt for event TXFRAMEEND"] #[inline(always)] pub fn set_txframeend(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); } - #[doc = "Enable or disable interrupt for RXFRAMESTART event"] + #[doc = "Enable or disable interrupt for event RXFRAMESTART"] #[inline(always)] pub const fn rxframestart(&self) -> bool { let val = (self.0 >> 5usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for RXFRAMESTART event"] + #[doc = "Enable or disable interrupt for event RXFRAMESTART"] #[inline(always)] pub fn set_rxframestart(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); } - #[doc = "Enable or disable interrupt for RXFRAMEEND event"] + #[doc = "Enable or disable interrupt for event RXFRAMEEND"] #[inline(always)] pub const fn rxframeend(&self) -> bool { let val = (self.0 >> 6usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for RXFRAMEEND event"] + #[doc = "Enable or disable interrupt for event RXFRAMEEND"] #[inline(always)] pub fn set_rxframeend(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); } - #[doc = "Enable or disable interrupt for ERROR event"] + #[doc = "Enable or disable interrupt for event ERROR"] #[inline(always)] pub const fn error(&self) -> bool { let val = (self.0 >> 7usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for ERROR event"] + #[doc = "Enable or disable interrupt for event ERROR"] #[inline(always)] pub fn set_error(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); } - #[doc = "Enable or disable interrupt for RXERROR event"] + #[doc = "Enable or disable interrupt for event RXERROR"] #[inline(always)] pub const fn rxerror(&self) -> bool { let val = (self.0 >> 10usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for RXERROR event"] + #[doc = "Enable or disable interrupt for event RXERROR"] #[inline(always)] pub fn set_rxerror(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); } - #[doc = "Enable or disable interrupt for ENDRX event"] + #[doc = "Enable or disable interrupt for event ENDRX"] #[inline(always)] pub const fn endrx(&self) -> bool { let val = (self.0 >> 11usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for ENDRX event"] + #[doc = "Enable or disable interrupt for event ENDRX"] #[inline(always)] pub fn set_endrx(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); } - #[doc = "Enable or disable interrupt for ENDTX event"] + #[doc = "Enable or disable interrupt for event ENDTX"] #[inline(always)] pub const fn endtx(&self) -> bool { let val = (self.0 >> 12usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for ENDTX event"] + #[doc = "Enable or disable interrupt for event ENDTX"] #[inline(always)] pub fn set_endtx(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); } - #[doc = "Enable or disable interrupt for AUTOCOLRESSTARTED event"] + #[doc = "Enable or disable interrupt for event AUTOCOLRESSTARTED"] #[inline(always)] pub const fn autocolresstarted(&self) -> bool { let val = (self.0 >> 14usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for AUTOCOLRESSTARTED event"] + #[doc = "Enable or disable interrupt for event AUTOCOLRESSTARTED"] #[inline(always)] pub fn set_autocolresstarted(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); } - #[doc = "Enable or disable interrupt for COLLISION event"] + #[doc = "Enable or disable interrupt for event COLLISION"] #[inline(always)] pub const fn collision(&self) -> bool { let val = (self.0 >> 18usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for COLLISION event"] + #[doc = "Enable or disable interrupt for event COLLISION"] #[inline(always)] pub fn set_collision(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); } - #[doc = "Enable or disable interrupt for SELECTED event"] + #[doc = "Enable or disable interrupt for event SELECTED"] #[inline(always)] pub const fn selected(&self) -> bool { let val = (self.0 >> 19usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for SELECTED event"] + #[doc = "Enable or disable interrupt for event SELECTED"] #[inline(always)] pub fn set_selected(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize); } - #[doc = "Enable or disable interrupt for STARTED event"] + #[doc = "Enable or disable interrupt for event STARTED"] #[inline(always)] pub const fn started(&self) -> bool { let val = (self.0 >> 20usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for STARTED event"] + #[doc = "Enable or disable interrupt for event STARTED"] #[inline(always)] pub fn set_started(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize); @@ -8839,40 +15221,40 @@ pub mod nfct { Sensres(0) } } - #[doc = "Shortcut register"] + #[doc = "Shortcuts between local events and tasks"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Shorts(pub u32); impl Shorts { - #[doc = "Shortcut between FIELDDETECTED event and ACTIVATE task"] + #[doc = "Shortcut between event FIELDDETECTED and task ACTIVATE"] #[inline(always)] pub const fn fielddetected_activate(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Shortcut between FIELDDETECTED event and ACTIVATE task"] + #[doc = "Shortcut between event FIELDDETECTED and task ACTIVATE"] #[inline(always)] pub fn set_fielddetected_activate(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - #[doc = "Shortcut between FIELDLOST event and SENSE task"] + #[doc = "Shortcut between event FIELDLOST and task SENSE"] #[inline(always)] pub const fn fieldlost_sense(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; val != 0 } - #[doc = "Shortcut between FIELDLOST event and SENSE task"] + #[doc = "Shortcut between event FIELDLOST and task SENSE"] #[inline(always)] pub fn set_fieldlost_sense(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } - #[doc = "Shortcut between TXFRAMEEND event and ENABLERXDATA task"] + #[doc = "Shortcut between event TXFRAMEEND and task ENABLERXDATA"] #[inline(always)] pub const fn txframeend_enablerxdata(&self) -> bool { let val = (self.0 >> 5usize) & 0x01; val != 0 } - #[doc = "Shortcut between TXFRAMEEND event and ENABLERXDATA task"] + #[doc = "Shortcut between event TXFRAMEEND and task ENABLERXDATA"] #[inline(always)] pub fn set_txframeend_enablerxdata(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); @@ -9296,32 +15678,22 @@ pub mod nvmc { } #[doc = "Register for erasing a page in code area"] #[inline(always)] - pub const fn erasepage(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0508usize) as _) } - } - #[doc = "Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE."] - #[inline(always)] - pub const fn erasepcr1(self) -> crate::common::Reg { + pub const fn erasepage(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0508usize) as _) } } #[doc = "Register for erasing all non-volatile user memory"] #[inline(always)] - pub const fn eraseall(self) -> crate::common::Reg { + pub const fn eraseall(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x050cusize) as _) } } - #[doc = "Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE."] - #[inline(always)] - pub const fn erasepcr0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0510usize) as _) } - } #[doc = "Register for erasing user information configuration registers"] #[inline(always)] - pub const fn eraseuicr(self) -> crate::common::Reg { + pub const fn eraseuicr(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0514usize) as _) } } #[doc = "Register for partial erase of a page in code area"] #[inline(always)] - pub const fn erasepagepartial(self) -> crate::common::Reg { + pub const fn erasepagepartial(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0518usize) as _) } } #[doc = "Register for partial erase configuration"] @@ -9331,17 +15703,17 @@ pub mod nvmc { ) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x051cusize) as _) } } - #[doc = "I-code cache configuration register."] + #[doc = "I-code cache configuration register"] #[inline(always)] pub const fn icachecnf(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0540usize) as _) } } - #[doc = "I-code cache hit counter."] + #[doc = "I-code cache hit counter"] #[inline(always)] pub const fn ihit(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0548usize) as _) } } - #[doc = "I-code cache miss counter."] + #[doc = "I-code cache miss counter"] #[inline(always)] pub const fn imiss(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x054cusize) as _) } @@ -9376,13 +15748,13 @@ pub mod nvmc { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Eraseall(pub u32); impl Eraseall { - #[doc = "Erase all non-volatile memory including UICR registers. Note that the erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased."] + #[doc = "Erase all non-volatile memory including UICR registers. The erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased."] #[inline(always)] pub const fn eraseall(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Erase all non-volatile memory including UICR registers. Note that the erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased."] + #[doc = "Erase all non-volatile memory including UICR registers. The erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased."] #[inline(always)] pub fn set_eraseall(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); @@ -9422,13 +15794,13 @@ pub mod nvmc { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Eraseuicr(pub u32); impl Eraseuicr { - #[doc = "Register starting erase of all user information configuration registers. Note that the erase must be enabled using CONFIG.WEN before the UICR can be erased."] + #[doc = "Register starting erase of all user information configuration registers. The erase must be enabled using CONFIG.WEN before the UICR can be erased."] #[inline(always)] pub const fn eraseuicr(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Register starting erase of all user information configuration registers. Note that the erase must be enabled using CONFIG.WEN before the UICR can be erased."] + #[doc = "Register starting erase of all user information configuration registers. The erase must be enabled using CONFIG.WEN before the UICR can be erased."] #[inline(always)] pub fn set_eraseuicr(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); @@ -9440,7 +15812,7 @@ pub mod nvmc { Eraseuicr(0) } } - #[doc = "I-code cache configuration register."] + #[doc = "I-code cache configuration register"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Icachecnf(pub u32); @@ -9784,35 +16156,35 @@ pub mod pdm { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Inten(pub u32); impl Inten { - #[doc = "Enable or disable interrupt for STARTED event"] + #[doc = "Enable or disable interrupt for event STARTED"] #[inline(always)] pub const fn started(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for STARTED event"] + #[doc = "Enable or disable interrupt for event STARTED"] #[inline(always)] pub fn set_started(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - #[doc = "Enable or disable interrupt for STOPPED event"] + #[doc = "Enable or disable interrupt for event STOPPED"] #[inline(always)] pub const fn stopped(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for STOPPED event"] + #[doc = "Enable or disable interrupt for event STOPPED"] #[inline(always)] pub fn set_stopped(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } - #[doc = "Enable or disable interrupt for END event"] + #[doc = "Enable or disable interrupt for event END"] #[inline(always)] pub const fn end(&self) -> bool { let val = (self.0 >> 2usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for END event"] + #[doc = "Enable or disable interrupt for event END"] #[inline(always)] pub fn set_end(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); @@ -9863,13 +16235,13 @@ pub mod pdm { pub fn set_operation(&mut self, val: super::vals::Operation) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); } - #[doc = "Defines on which PDM_CLK edge Left (or mono) is sampled"] + #[doc = "Defines on which PDM_CLK edge left (or mono) is sampled"] #[inline(always)] pub const fn edge(&self) -> super::vals::Edge { let val = (self.0 >> 1usize) & 0x01; super::vals::Edge::from_bits(val as u8) } - #[doc = "Defines on which PDM_CLK edge Left (or mono) is sampled"] + #[doc = "Defines on which PDM_CLK edge left (or mono) is sampled"] #[inline(always)] pub fn set_edge(&mut self, val: super::vals::Edge) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val.to_bits() as u32) & 0x01) << 1usize); @@ -9886,13 +16258,13 @@ pub mod pdm { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Pdmclkctrl(pub u32); impl Pdmclkctrl { - #[doc = "PDM_CLK frequency"] + #[doc = "PDM_CLK frequency configuration"] #[inline(always)] pub const fn freq(&self) -> super::vals::Freq { let val = (self.0 >> 0usize) & 0xffff_ffff; super::vals::Freq::from_bits(val as u32) } - #[doc = "PDM_CLK frequency"] + #[doc = "PDM_CLK frequency configuration"] #[inline(always)] pub fn set_freq(&mut self, val: super::vals::Freq) { self.0 = (self.0 & !(0xffff_ffff << 0usize)) @@ -10001,11 +16373,11 @@ pub mod pdm { #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub struct Gain(pub u8); impl Gain { - #[doc = "-20dB gain adjustment (minimum)"] + #[doc = "-20 dB gain adjustment (minimum)"] pub const MIN_GAIN: Self = Self(0x0); - #[doc = "0dB gain adjustment"] + #[doc = "0 dB gain adjustment"] pub const DEFAULT_GAIN: Self = Self(0x28); - #[doc = "+20dB gain adjustment (maximum)"] + #[doc = "+20 dB gain adjustment (maximum)"] pub const MAX_GAIN: Self = Self(0x50); } impl Gain { @@ -10031,9 +16403,9 @@ pub mod pdm { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Operation { - #[doc = "Sample and store one pair (Left + Right) of 16bit samples per RAM word R=\\[31:16\\]; L=\\[15:0\\]"] + #[doc = "Sample and store one pair (left + right) of 16-bit samples per RAM word R=\\[31:16\\]; L=\\[15:0\\]"] STEREO = 0x0, - #[doc = "Sample and store two successive Left samples (16 bit each) per RAM word L1=\\[31:16\\]; L0=\\[15:0\\]"] + #[doc = "Sample and store two successive left samples (16 bits each) per RAM word L1=\\[31:16\\]; L0=\\[15:0\\]"] MONO = 0x01, } impl Operation { @@ -10107,12 +16479,12 @@ pub mod power { pub const fn as_ptr(&self) -> *mut () { self.ptr as _ } - #[doc = "Enable constant latency mode"] + #[doc = "Enable Constant Latency mode"] #[inline(always)] pub const fn tasks_constlat(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x78usize) as _) } } - #[doc = "Enable low power mode (variable latency)"] + #[doc = "Enable Low-power mode (variable latency)"] #[inline(always)] pub const fn tasks_lowpwr(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x7cusize) as _) } @@ -10194,12 +16566,12 @@ pub mod power { pub const fn gpregret2(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0520usize) as _) } } - #[doc = "Enable DC/DC converter for REG1 stage."] + #[doc = "Enable DC/DC converter for REG1 stage"] #[inline(always)] pub const fn dcdcen(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0578usize) as _) } } - #[doc = "Enable DC/DC converter for REG0 stage."] + #[doc = "Enable DC/DC converter for REG0 stage"] #[inline(always)] pub const fn dcdcen0(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0580usize) as _) } @@ -10234,24 +16606,24 @@ pub mod power { pub const fn as_ptr(&self) -> *mut () { self.ptr as _ } - #[doc = "Description cluster\\[n\\]: RAMn power control register"] + #[doc = "Description cluster: RAMn power control register"] #[inline(always)] pub const fn power(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } - #[doc = "Description cluster\\[n\\]: RAMn power control set register"] + #[doc = "Description cluster: RAMn power control set register"] #[inline(always)] pub const fn powerset(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } - #[doc = "Description cluster\\[n\\]: RAMn power control clear register"] + #[doc = "Description cluster: RAMn power control clear register"] #[inline(always)] pub const fn powerclr(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } } pub mod regs { - #[doc = "Enable DC/DC converter for REG1 stage."] + #[doc = "Enable DC/DC converter for REG1 stage"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Dcdcen(pub u32); @@ -10274,7 +16646,7 @@ pub mod power { Dcdcen(0) } } - #[doc = "Enable DC/DC converter for REG0 stage."] + #[doc = "Enable DC/DC converter for REG0 stage"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Dcdcen0(pub u32); @@ -10348,68 +16720,68 @@ pub mod power { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Inten(pub u32); impl Inten { - #[doc = "Write '1' to disable interrupt for POFWARN event"] + #[doc = "Write '1' to disable interrupt for event POFWARN"] #[inline(always)] pub const fn pofwarn(&self) -> bool { let val = (self.0 >> 2usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for POFWARN event"] + #[doc = "Write '1' to disable interrupt for event POFWARN"] #[inline(always)] pub fn set_pofwarn(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); } - #[doc = "Write '1' to disable interrupt for SLEEPENTER event"] + #[doc = "Write '1' to disable interrupt for event SLEEPENTER"] #[inline(always)] pub const fn sleepenter(&self) -> bool { let val = (self.0 >> 5usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for SLEEPENTER event"] + #[doc = "Write '1' to disable interrupt for event SLEEPENTER"] #[inline(always)] pub fn set_sleepenter(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); } - #[doc = "Write '1' to disable interrupt for SLEEPEXIT event"] + #[doc = "Write '1' to disable interrupt for event SLEEPEXIT"] #[inline(always)] pub const fn sleepexit(&self) -> bool { let val = (self.0 >> 6usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for SLEEPEXIT event"] + #[doc = "Write '1' to disable interrupt for event SLEEPEXIT"] #[inline(always)] pub fn set_sleepexit(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); } - #[doc = "Write '1' to disable interrupt for USBDETECTED event"] + #[doc = "Write '1' to disable interrupt for event USBDETECTED"] #[inline(always)] pub const fn usbdetected(&self) -> bool { let val = (self.0 >> 7usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for USBDETECTED event"] + #[doc = "Write '1' to disable interrupt for event USBDETECTED"] #[inline(always)] pub fn set_usbdetected(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); } - #[doc = "Write '1' to disable interrupt for USBREMOVED event"] + #[doc = "Write '1' to disable interrupt for event USBREMOVED"] #[inline(always)] pub const fn usbremoved(&self) -> bool { let val = (self.0 >> 8usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for USBREMOVED event"] + #[doc = "Write '1' to disable interrupt for event USBREMOVED"] #[inline(always)] pub fn set_usbremoved(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); } - #[doc = "Write '1' to disable interrupt for USBPWRRDY event"] + #[doc = "Write '1' to disable interrupt for event USBPWRRDY"] #[inline(always)] pub const fn usbpwrrdy(&self) -> bool { let val = (self.0 >> 9usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for USBPWRRDY event"] + #[doc = "Write '1' to disable interrupt for event USBPWRRDY"] #[inline(always)] pub fn set_usbpwrrdy(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); @@ -10489,7 +16861,7 @@ pub mod power { Pofcon(0) } } - #[doc = "Description cluster\\[n\\]: RAMn power control register"] + #[doc = "Description cluster: RAMn power control register"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Power(pub u32); @@ -10918,12 +17290,12 @@ pub mod ppi { pub const fn as_ptr(&self) -> *mut () { self.ptr as _ } - #[doc = "Description cluster\\[n\\]: Channel n event end-point"] + #[doc = "Description cluster: Channel n event endpoint"] #[inline(always)] pub const fn eep(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } - #[doc = "Description cluster\\[n\\]: Channel n task end-point"] + #[doc = "Description cluster: Channel n task endpoint"] #[inline(always)] pub const fn tep(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } @@ -10945,7 +17317,7 @@ pub mod ppi { pub const fn as_ptr(&self) -> *mut () { self.ptr as _ } - #[doc = "Description cluster\\[n\\]: Channel n task end-point"] + #[doc = "Description cluster: Channel n task endpoint"] #[inline(always)] pub const fn tep(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } @@ -10994,7 +17366,7 @@ pub mod ppi { assert!(n < 20usize); unsafe { Ch::from_ptr(self.ptr.add(0x0510usize + n * 8usize) as _) } } - #[doc = "Description collection\\[n\\]: Channel group n"] + #[doc = "Description collection: Channel group n"] #[inline(always)] pub const fn chg(self, n: usize) -> crate::common::Reg { assert!(n < 6usize); @@ -11023,12 +17395,12 @@ pub mod ppi { pub const fn as_ptr(&self) -> *mut () { self.ptr as _ } - #[doc = "Description cluster\\[n\\]: Enable channel group n"] + #[doc = "Description cluster: Enable channel group n"] #[inline(always)] pub const fn en(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } - #[doc = "Description cluster\\[n\\]: Disable channel group n"] + #[doc = "Description cluster: Disable channel group n"] #[inline(always)] pub const fn dis(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } @@ -11062,7 +17434,7 @@ pub mod ppi { Chen(0) } } - #[doc = "Description collection\\[n\\]: Channel group n"] + #[doc = "Description collection: Channel group n"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Chg(pub u32); @@ -11108,7 +17480,7 @@ pub mod pwm { pub const fn as_ptr(&self) -> *mut () { self.ptr as _ } - #[doc = "Description collection\\[n\\]: Output pin select for PWM channel n"] + #[doc = "Description collection: Output pin select for PWM channel n"] #[inline(always)] pub const fn out( self, @@ -11139,7 +17511,7 @@ pub mod pwm { pub const fn tasks_stop(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } - #[doc = "Description collection\\[n\\]: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ\\[n\\]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running."] + #[doc = "Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ\\[n\\]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running."] #[inline(always)] pub const fn tasks_seqstart(self, n: usize) -> crate::common::Reg { assert!(n < 2usize); @@ -11155,7 +17527,7 @@ pub mod pwm { pub const fn events_stopped(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0104usize) as _) } } - #[doc = "Description collection\\[n\\]: First PWM period started on sequence n"] + #[doc = "Description collection: First PWM period started on sequence n"] #[inline(always)] pub const fn events_seqstarted( self, @@ -11164,7 +17536,7 @@ pub mod pwm { assert!(n < 2usize); unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0108usize + n * 4usize) as _) } } - #[doc = "Description collection\\[n\\]: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter"] + #[doc = "Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter"] #[inline(always)] pub const fn events_seqend(self, n: usize) -> crate::common::Reg { assert!(n < 2usize); @@ -11180,7 +17552,7 @@ pub mod pwm { pub const fn events_loopsdone(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x011cusize) as _) } } - #[doc = "Shortcut register"] + #[doc = "Shortcuts between local events and tasks"] #[inline(always)] pub const fn shorts(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0200usize) as _) } @@ -11258,29 +17630,29 @@ pub mod pwm { pub const fn as_ptr(&self) -> *mut () { self.ptr as _ } - #[doc = "Description cluster\\[n\\]: Beginning address in RAM of this sequence"] + #[doc = "Description cluster: Beginning address in RAM of this sequence"] #[inline(always)] pub const fn ptr(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } - #[doc = "Description cluster\\[n\\]: Number of values (duty cycles) in this sequence"] + #[doc = "Description cluster: Number of values (duty cycles) in this sequence"] #[inline(always)] pub const fn cnt(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } - #[doc = "Description cluster\\[n\\]: Number of additional PWM periods between samples loaded into compare register"] + #[doc = "Description cluster: Number of additional PWM periods between samples loaded into compare register"] #[inline(always)] pub const fn refresh(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } - #[doc = "Description cluster\\[n\\]: Time added after the sequence"] + #[doc = "Description cluster: Time added after the sequence"] #[inline(always)] pub const fn enddelay(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } } } pub mod regs { - #[doc = "Description cluster\\[n\\]: Number of values (duty cycles) in this sequence"] + #[doc = "Description cluster: Number of values (duty cycles) in this sequence"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Cnt(pub u32); @@ -11384,7 +17756,7 @@ pub mod pwm { Enable(0) } } - #[doc = "Description cluster\\[n\\]: Time added after the sequence"] + #[doc = "Description cluster: Time added after the sequence"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Enddelay(pub u32); @@ -11413,79 +17785,79 @@ pub mod pwm { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Inten(pub u32); impl Inten { - #[doc = "Enable or disable interrupt for STOPPED event"] + #[doc = "Enable or disable interrupt for event STOPPED"] #[inline(always)] pub const fn stopped(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for STOPPED event"] + #[doc = "Enable or disable interrupt for event STOPPED"] #[inline(always)] pub fn set_stopped(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } - #[doc = "Enable or disable interrupt for SEQSTARTED\\[0\\] event"] + #[doc = "Enable or disable interrupt for event SEQSTARTED\\[0\\]"] #[inline(always)] pub const fn seqstarted0(&self) -> bool { let val = (self.0 >> 2usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for SEQSTARTED\\[0\\] event"] + #[doc = "Enable or disable interrupt for event SEQSTARTED\\[0\\]"] #[inline(always)] pub fn set_seqstarted0(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); } - #[doc = "Enable or disable interrupt for SEQSTARTED\\[1\\] event"] + #[doc = "Enable or disable interrupt for event SEQSTARTED\\[1\\]"] #[inline(always)] pub const fn seqstarted1(&self) -> bool { let val = (self.0 >> 3usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for SEQSTARTED\\[1\\] event"] + #[doc = "Enable or disable interrupt for event SEQSTARTED\\[1\\]"] #[inline(always)] pub fn set_seqstarted1(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); } - #[doc = "Enable or disable interrupt for SEQEND\\[0\\] event"] + #[doc = "Enable or disable interrupt for event SEQEND\\[0\\]"] #[inline(always)] pub const fn seqend0(&self) -> bool { let val = (self.0 >> 4usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for SEQEND\\[0\\] event"] + #[doc = "Enable or disable interrupt for event SEQEND\\[0\\]"] #[inline(always)] pub fn set_seqend0(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); } - #[doc = "Enable or disable interrupt for SEQEND\\[1\\] event"] + #[doc = "Enable or disable interrupt for event SEQEND\\[1\\]"] #[inline(always)] pub const fn seqend1(&self) -> bool { let val = (self.0 >> 5usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for SEQEND\\[1\\] event"] + #[doc = "Enable or disable interrupt for event SEQEND\\[1\\]"] #[inline(always)] pub fn set_seqend1(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); } - #[doc = "Enable or disable interrupt for PWMPERIODEND event"] + #[doc = "Enable or disable interrupt for event PWMPERIODEND"] #[inline(always)] pub const fn pwmperiodend(&self) -> bool { let val = (self.0 >> 6usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for PWMPERIODEND event"] + #[doc = "Enable or disable interrupt for event PWMPERIODEND"] #[inline(always)] pub fn set_pwmperiodend(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); } - #[doc = "Enable or disable interrupt for LOOPSDONE event"] + #[doc = "Enable or disable interrupt for event LOOPSDONE"] #[inline(always)] pub const fn loopsdone(&self) -> bool { let val = (self.0 >> 7usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for LOOPSDONE event"] + #[doc = "Enable or disable interrupt for event LOOPSDONE"] #[inline(always)] pub fn set_loopsdone(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); @@ -11567,7 +17939,7 @@ pub mod pwm { Prescaler(0) } } - #[doc = "Description cluster\\[n\\]: Number of additional PWM periods between samples loaded into compare register"] + #[doc = "Description cluster: Number of additional PWM periods between samples loaded into compare register"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Refresh(pub u32); @@ -11591,62 +17963,62 @@ pub mod pwm { Refresh(0) } } - #[doc = "Shortcut register"] + #[doc = "Shortcuts between local events and tasks"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Shorts(pub u32); impl Shorts { - #[doc = "Shortcut between SEQEND\\[0\\] event and STOP task"] + #[doc = "Shortcut between event SEQEND\\[0\\] and task STOP"] #[inline(always)] pub const fn seqend0_stop(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Shortcut between SEQEND\\[0\\] event and STOP task"] + #[doc = "Shortcut between event SEQEND\\[0\\] and task STOP"] #[inline(always)] pub fn set_seqend0_stop(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - #[doc = "Shortcut between SEQEND\\[1\\] event and STOP task"] + #[doc = "Shortcut between event SEQEND\\[1\\] and task STOP"] #[inline(always)] pub const fn seqend1_stop(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; val != 0 } - #[doc = "Shortcut between SEQEND\\[1\\] event and STOP task"] + #[doc = "Shortcut between event SEQEND\\[1\\] and task STOP"] #[inline(always)] pub fn set_seqend1_stop(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } - #[doc = "Shortcut between LOOPSDONE event and SEQSTART\\[0\\] task"] + #[doc = "Shortcut between event LOOPSDONE and task SEQSTART\\[0\\]"] #[inline(always)] pub const fn loopsdone_seqstart0(&self) -> bool { let val = (self.0 >> 2usize) & 0x01; val != 0 } - #[doc = "Shortcut between LOOPSDONE event and SEQSTART\\[0\\] task"] + #[doc = "Shortcut between event LOOPSDONE and task SEQSTART\\[0\\]"] #[inline(always)] pub fn set_loopsdone_seqstart0(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); } - #[doc = "Shortcut between LOOPSDONE event and SEQSTART\\[1\\] task"] + #[doc = "Shortcut between event LOOPSDONE and task SEQSTART\\[1\\]"] #[inline(always)] pub const fn loopsdone_seqstart1(&self) -> bool { let val = (self.0 >> 3usize) & 0x01; val != 0 } - #[doc = "Shortcut between LOOPSDONE event and SEQSTART\\[1\\] task"] + #[doc = "Shortcut between event LOOPSDONE and task SEQSTART\\[1\\]"] #[inline(always)] pub fn set_loopsdone_seqstart1(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); } - #[doc = "Shortcut between LOOPSDONE event and STOP task"] + #[doc = "Shortcut between event LOOPSDONE and task STOP"] #[inline(always)] pub const fn loopsdone_stop(&self) -> bool { let val = (self.0 >> 4usize) & 0x01; val != 0 } - #[doc = "Shortcut between LOOPSDONE event and STOP task"] + #[doc = "Shortcut between event LOOPSDONE and task STOP"] #[inline(always)] pub fn set_loopsdone_stop(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); @@ -11978,7 +18350,7 @@ pub mod qdec { pub const fn events_stopped(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0110usize) as _) } } - #[doc = "Shortcut register"] + #[doc = "Shortcuts between local events and tasks"] #[inline(always)] pub const fn shorts(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0200usize) as _) } @@ -12152,57 +18524,57 @@ pub mod qdec { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Inten(pub u32); impl Inten { - #[doc = "Write '1' to disable interrupt for SAMPLERDY event"] + #[doc = "Write '1' to disable interrupt for event SAMPLERDY"] #[inline(always)] pub const fn samplerdy(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for SAMPLERDY event"] + #[doc = "Write '1' to disable interrupt for event SAMPLERDY"] #[inline(always)] pub fn set_samplerdy(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - #[doc = "Write '1' to disable interrupt for REPORTRDY event"] + #[doc = "Write '1' to disable interrupt for event REPORTRDY"] #[inline(always)] pub const fn reportrdy(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for REPORTRDY event"] + #[doc = "Write '1' to disable interrupt for event REPORTRDY"] #[inline(always)] pub fn set_reportrdy(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } - #[doc = "Write '1' to disable interrupt for ACCOF event"] + #[doc = "Write '1' to disable interrupt for event ACCOF"] #[inline(always)] pub const fn accof(&self) -> bool { let val = (self.0 >> 2usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for ACCOF event"] + #[doc = "Write '1' to disable interrupt for event ACCOF"] #[inline(always)] pub fn set_accof(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); } - #[doc = "Write '1' to disable interrupt for DBLRDY event"] + #[doc = "Write '1' to disable interrupt for event DBLRDY"] #[inline(always)] pub const fn dblrdy(&self) -> bool { let val = (self.0 >> 3usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for DBLRDY event"] + #[doc = "Write '1' to disable interrupt for event DBLRDY"] #[inline(always)] pub fn set_dblrdy(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); } - #[doc = "Write '1' to disable interrupt for STOPPED event"] + #[doc = "Write '1' to disable interrupt for event STOPPED"] #[inline(always)] pub const fn stopped(&self) -> bool { let val = (self.0 >> 4usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for STOPPED event"] + #[doc = "Write '1' to disable interrupt for event STOPPED"] #[inline(always)] pub fn set_stopped(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); @@ -12265,13 +18637,13 @@ pub mod qdec { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Reportper(pub u32); impl Reportper { - #[doc = "Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated"] + #[doc = "Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated."] #[inline(always)] pub const fn reportper(&self) -> super::vals::Reportper { let val = (self.0 >> 0usize) & 0x0f; super::vals::Reportper::from_bits(val as u8) } - #[doc = "Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated"] + #[doc = "Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated."] #[inline(always)] pub fn set_reportper(&mut self, val: super::vals::Reportper) { self.0 = (self.0 & !(0x0f << 0usize)) | (((val.to_bits() as u32) & 0x0f) << 0usize); @@ -12306,84 +18678,84 @@ pub mod qdec { Sampleper(0) } } - #[doc = "Shortcut register"] + #[doc = "Shortcuts between local events and tasks"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Shorts(pub u32); impl Shorts { - #[doc = "Shortcut between REPORTRDY event and READCLRACC task"] + #[doc = "Shortcut between event REPORTRDY and task READCLRACC"] #[inline(always)] pub const fn reportrdy_readclracc(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Shortcut between REPORTRDY event and READCLRACC task"] + #[doc = "Shortcut between event REPORTRDY and task READCLRACC"] #[inline(always)] pub fn set_reportrdy_readclracc(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - #[doc = "Shortcut between SAMPLERDY event and STOP task"] + #[doc = "Shortcut between event SAMPLERDY and task STOP"] #[inline(always)] pub const fn samplerdy_stop(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; val != 0 } - #[doc = "Shortcut between SAMPLERDY event and STOP task"] + #[doc = "Shortcut between event SAMPLERDY and task STOP"] #[inline(always)] pub fn set_samplerdy_stop(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } - #[doc = "Shortcut between REPORTRDY event and RDCLRACC task"] + #[doc = "Shortcut between event REPORTRDY and task RDCLRACC"] #[inline(always)] pub const fn reportrdy_rdclracc(&self) -> bool { let val = (self.0 >> 2usize) & 0x01; val != 0 } - #[doc = "Shortcut between REPORTRDY event and RDCLRACC task"] + #[doc = "Shortcut between event REPORTRDY and task RDCLRACC"] #[inline(always)] pub fn set_reportrdy_rdclracc(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); } - #[doc = "Shortcut between REPORTRDY event and STOP task"] + #[doc = "Shortcut between event REPORTRDY and task STOP"] #[inline(always)] pub const fn reportrdy_stop(&self) -> bool { let val = (self.0 >> 3usize) & 0x01; val != 0 } - #[doc = "Shortcut between REPORTRDY event and STOP task"] + #[doc = "Shortcut between event REPORTRDY and task STOP"] #[inline(always)] pub fn set_reportrdy_stop(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); } - #[doc = "Shortcut between DBLRDY event and RDCLRDBL task"] + #[doc = "Shortcut between event DBLRDY and task RDCLRDBL"] #[inline(always)] pub const fn dblrdy_rdclrdbl(&self) -> bool { let val = (self.0 >> 4usize) & 0x01; val != 0 } - #[doc = "Shortcut between DBLRDY event and RDCLRDBL task"] + #[doc = "Shortcut between event DBLRDY and task RDCLRDBL"] #[inline(always)] pub fn set_dblrdy_rdclrdbl(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); } - #[doc = "Shortcut between DBLRDY event and STOP task"] + #[doc = "Shortcut between event DBLRDY and task STOP"] #[inline(always)] pub const fn dblrdy_stop(&self) -> bool { let val = (self.0 >> 5usize) & 0x01; val != 0 } - #[doc = "Shortcut between DBLRDY event and STOP task"] + #[doc = "Shortcut between event DBLRDY and task STOP"] #[inline(always)] pub fn set_dblrdy_stop(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); } - #[doc = "Shortcut between SAMPLERDY event and READCLRACC task"] + #[doc = "Shortcut between event SAMPLERDY and task READCLRACC"] #[inline(always)] pub const fn samplerdy_readclracc(&self) -> bool { let val = (self.0 >> 6usize) & 0x01; val != 0 } - #[doc = "Shortcut between SAMPLERDY event and READCLRACC task"] + #[doc = "Shortcut between event SAMPLERDY and task READCLRACC"] #[inline(always)] pub fn set_samplerdy_readclracc(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); @@ -12430,23 +18802,23 @@ pub mod qdec { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Reportper { - #[doc = "10 samples / report"] + #[doc = "10 samples/report"] _10SMPL = 0x0, - #[doc = "40 samples / report"] + #[doc = "40 samples/report"] _40SMPL = 0x01, - #[doc = "80 samples / report"] + #[doc = "80 samples/report"] _80SMPL = 0x02, - #[doc = "120 samples / report"] + #[doc = "120 samples/report"] _120SMPL = 0x03, - #[doc = "160 samples / report"] + #[doc = "160 samples/report"] _160SMPL = 0x04, - #[doc = "200 samples / report"] + #[doc = "200 samples/report"] _200SMPL = 0x05, - #[doc = "240 samples / report"] + #[doc = "240 samples/report"] _240SMPL = 0x06, - #[doc = "280 samples / report"] + #[doc = "280 samples/report"] _280SMPL = 0x07, - #[doc = "1 sample / report"] + #[doc = "1 sample/report"] _1SMPL = 0x08, _RESERVED_9 = 0x09, _RESERVED_a = 0x0a, @@ -13311,13 +19683,13 @@ pub mod qspi { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Inten(pub u32); impl Inten { - #[doc = "Enable or disable interrupt for READY event"] + #[doc = "Enable or disable interrupt for event READY"] #[inline(always)] pub const fn ready(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for READY event"] + #[doc = "Enable or disable interrupt for event READY"] #[inline(always)] pub fn set_ready(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); @@ -13360,14 +19732,14 @@ pub mod qspi { #[doc = "Read transfer length in number of bytes. The length must be a multiple of 4 bytes."] #[inline(always)] pub const fn cnt(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x001f_ffff; + let val = (self.0 >> 0usize) & 0x0003_ffff; val as u32 } #[doc = "Read transfer length in number of bytes. The length must be a multiple of 4 bytes."] #[inline(always)] pub fn set_cnt(&mut self, val: u32) { self.0 = - (self.0 & !(0x001f_ffff << 0usize)) | (((val as u32) & 0x001f_ffff) << 0usize); + (self.0 & !(0x0003_ffff << 0usize)) | (((val as u32) & 0x0003_ffff) << 0usize); } } impl Default for ReadCnt { @@ -13429,14 +19801,14 @@ pub mod qspi { #[doc = "Write transfer length in number of bytes. The length must be a multiple of 4 bytes."] #[inline(always)] pub const fn cnt(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x001f_ffff; + let val = (self.0 >> 0usize) & 0x0003_ffff; val as u32 } #[doc = "Write transfer length in number of bytes. The length must be a multiple of 4 bytes."] #[inline(always)] pub fn set_cnt(&mut self, val: u32) { self.0 = - (self.0 & !(0x001f_ffff << 0usize)) | (((val as u32) & 0x001f_ffff) << 0usize); + (self.0 & !(0x0003_ffff << 0usize)) | (((val as u32) & 0x0003_ffff) << 0usize); } } impl Default for WriteCnt { @@ -13921,12 +20293,17 @@ pub mod radio { pub const fn events_mhrmatch(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x015cusize) as _) } } - #[doc = "Generated in Ble_LR125Kbit, Ble_LR500Kbit and BleIeee802154_250Kbit modes when last bit is sent on air."] + #[doc = "Preamble indicator."] + #[inline(always)] + pub const fn events_sync(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0168usize) as _) } + } + #[doc = "Generated in Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes when last bit is sent on air."] #[inline(always)] pub const fn events_phyend(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x016cusize) as _) } } - #[doc = "Shortcut register"] + #[doc = "Shortcuts between local events and tasks"] #[inline(always)] pub const fn shorts(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0200usize) as _) } @@ -14066,13 +20443,13 @@ pub mod radio { pub const fn bcc(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0560usize) as _) } } - #[doc = "Description collection\\[n\\]: Device address base segment n"] + #[doc = "Description collection: Device address base segment n"] #[inline(always)] pub const fn dab(self, n: usize) -> crate::common::Reg { assert!(n < 8usize); unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0600usize + n * 4usize) as _) } } - #[doc = "Description collection\\[n\\]: Device address prefix n"] + #[doc = "Description collection: Device address prefix n"] #[inline(always)] pub const fn dap(self, n: usize) -> crate::common::Reg { assert!(n < 8usize); @@ -14497,7 +20874,7 @@ pub mod radio { Dai(0) } } - #[doc = "Description collection\\[n\\]: Device address prefix n"] + #[doc = "Description collection: Device address prefix n"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Dap(pub u32); @@ -14629,244 +21006,255 @@ pub mod radio { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Inten(pub u32); impl Inten { - #[doc = "Write '1' to disable interrupt for READY event"] + #[doc = "Write '1' to disable interrupt for event READY"] #[inline(always)] pub const fn ready(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for READY event"] + #[doc = "Write '1' to disable interrupt for event READY"] #[inline(always)] pub fn set_ready(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - #[doc = "Write '1' to disable interrupt for ADDRESS event"] + #[doc = "Write '1' to disable interrupt for event ADDRESS"] #[inline(always)] pub const fn address(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for ADDRESS event"] + #[doc = "Write '1' to disable interrupt for event ADDRESS"] #[inline(always)] pub fn set_address(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } - #[doc = "Write '1' to disable interrupt for PAYLOAD event"] + #[doc = "Write '1' to disable interrupt for event PAYLOAD"] #[inline(always)] pub const fn payload(&self) -> bool { let val = (self.0 >> 2usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for PAYLOAD event"] + #[doc = "Write '1' to disable interrupt for event PAYLOAD"] #[inline(always)] pub fn set_payload(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); } - #[doc = "Write '1' to disable interrupt for END event"] + #[doc = "Write '1' to disable interrupt for event END"] #[inline(always)] pub const fn end(&self) -> bool { let val = (self.0 >> 3usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for END event"] + #[doc = "Write '1' to disable interrupt for event END"] #[inline(always)] pub fn set_end(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); } - #[doc = "Write '1' to disable interrupt for DISABLED event"] + #[doc = "Write '1' to disable interrupt for event DISABLED"] #[inline(always)] pub const fn disabled(&self) -> bool { let val = (self.0 >> 4usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for DISABLED event"] + #[doc = "Write '1' to disable interrupt for event DISABLED"] #[inline(always)] pub fn set_disabled(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); } - #[doc = "Write '1' to disable interrupt for DEVMATCH event"] + #[doc = "Write '1' to disable interrupt for event DEVMATCH"] #[inline(always)] pub const fn devmatch(&self) -> bool { let val = (self.0 >> 5usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for DEVMATCH event"] + #[doc = "Write '1' to disable interrupt for event DEVMATCH"] #[inline(always)] pub fn set_devmatch(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); } - #[doc = "Write '1' to disable interrupt for DEVMISS event"] + #[doc = "Write '1' to disable interrupt for event DEVMISS"] #[inline(always)] pub const fn devmiss(&self) -> bool { let val = (self.0 >> 6usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for DEVMISS event"] + #[doc = "Write '1' to disable interrupt for event DEVMISS"] #[inline(always)] pub fn set_devmiss(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); } - #[doc = "Write '1' to disable interrupt for RSSIEND event"] + #[doc = "Write '1' to disable interrupt for event RSSIEND"] #[inline(always)] pub const fn rssiend(&self) -> bool { let val = (self.0 >> 7usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for RSSIEND event"] + #[doc = "Write '1' to disable interrupt for event RSSIEND"] #[inline(always)] pub fn set_rssiend(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); } - #[doc = "Write '1' to disable interrupt for BCMATCH event"] + #[doc = "Write '1' to disable interrupt for event BCMATCH"] #[inline(always)] pub const fn bcmatch(&self) -> bool { let val = (self.0 >> 10usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for BCMATCH event"] + #[doc = "Write '1' to disable interrupt for event BCMATCH"] #[inline(always)] pub fn set_bcmatch(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); } - #[doc = "Write '1' to disable interrupt for CRCOK event"] + #[doc = "Write '1' to disable interrupt for event CRCOK"] #[inline(always)] pub const fn crcok(&self) -> bool { let val = (self.0 >> 12usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for CRCOK event"] + #[doc = "Write '1' to disable interrupt for event CRCOK"] #[inline(always)] pub fn set_crcok(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); } - #[doc = "Write '1' to disable interrupt for CRCERROR event"] + #[doc = "Write '1' to disable interrupt for event CRCERROR"] #[inline(always)] pub const fn crcerror(&self) -> bool { let val = (self.0 >> 13usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for CRCERROR event"] + #[doc = "Write '1' to disable interrupt for event CRCERROR"] #[inline(always)] pub fn set_crcerror(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); } - #[doc = "Write '1' to disable interrupt for FRAMESTART event"] + #[doc = "Write '1' to disable interrupt for event FRAMESTART"] #[inline(always)] pub const fn framestart(&self) -> bool { let val = (self.0 >> 14usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for FRAMESTART event"] + #[doc = "Write '1' to disable interrupt for event FRAMESTART"] #[inline(always)] pub fn set_framestart(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); } - #[doc = "Write '1' to disable interrupt for EDEND event"] + #[doc = "Write '1' to disable interrupt for event EDEND"] #[inline(always)] pub const fn edend(&self) -> bool { let val = (self.0 >> 15usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for EDEND event"] + #[doc = "Write '1' to disable interrupt for event EDEND"] #[inline(always)] pub fn set_edend(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); } - #[doc = "Write '1' to disable interrupt for EDSTOPPED event"] + #[doc = "Write '1' to disable interrupt for event EDSTOPPED"] #[inline(always)] pub const fn edstopped(&self) -> bool { let val = (self.0 >> 16usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for EDSTOPPED event"] + #[doc = "Write '1' to disable interrupt for event EDSTOPPED"] #[inline(always)] pub fn set_edstopped(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); } - #[doc = "Write '1' to disable interrupt for CCAIDLE event"] + #[doc = "Write '1' to disable interrupt for event CCAIDLE"] #[inline(always)] pub const fn ccaidle(&self) -> bool { let val = (self.0 >> 17usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for CCAIDLE event"] + #[doc = "Write '1' to disable interrupt for event CCAIDLE"] #[inline(always)] pub fn set_ccaidle(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); } - #[doc = "Write '1' to disable interrupt for CCABUSY event"] + #[doc = "Write '1' to disable interrupt for event CCABUSY"] #[inline(always)] pub const fn ccabusy(&self) -> bool { let val = (self.0 >> 18usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for CCABUSY event"] + #[doc = "Write '1' to disable interrupt for event CCABUSY"] #[inline(always)] pub fn set_ccabusy(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); } - #[doc = "Write '1' to disable interrupt for CCASTOPPED event"] + #[doc = "Write '1' to disable interrupt for event CCASTOPPED"] #[inline(always)] pub const fn ccastopped(&self) -> bool { let val = (self.0 >> 19usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for CCASTOPPED event"] + #[doc = "Write '1' to disable interrupt for event CCASTOPPED"] #[inline(always)] pub fn set_ccastopped(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize); } - #[doc = "Write '1' to disable interrupt for RATEBOOST event"] + #[doc = "Write '1' to disable interrupt for event RATEBOOST"] #[inline(always)] pub const fn rateboost(&self) -> bool { let val = (self.0 >> 20usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for RATEBOOST event"] + #[doc = "Write '1' to disable interrupt for event RATEBOOST"] #[inline(always)] pub fn set_rateboost(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize); } - #[doc = "Write '1' to disable interrupt for TXREADY event"] + #[doc = "Write '1' to disable interrupt for event TXREADY"] #[inline(always)] pub const fn txready(&self) -> bool { let val = (self.0 >> 21usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for TXREADY event"] + #[doc = "Write '1' to disable interrupt for event TXREADY"] #[inline(always)] pub fn set_txready(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize); } - #[doc = "Write '1' to disable interrupt for RXREADY event"] + #[doc = "Write '1' to disable interrupt for event RXREADY"] #[inline(always)] pub const fn rxready(&self) -> bool { let val = (self.0 >> 22usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for RXREADY event"] + #[doc = "Write '1' to disable interrupt for event RXREADY"] #[inline(always)] pub fn set_rxready(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize); } - #[doc = "Write '1' to disable interrupt for MHRMATCH event"] + #[doc = "Write '1' to disable interrupt for event MHRMATCH"] #[inline(always)] pub const fn mhrmatch(&self) -> bool { let val = (self.0 >> 23usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for MHRMATCH event"] + #[doc = "Write '1' to disable interrupt for event MHRMATCH"] #[inline(always)] pub fn set_mhrmatch(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); } - #[doc = "Write '1' to disable interrupt for PHYEND event"] + #[doc = "Write '1' to disable interrupt for event SYNC"] + #[inline(always)] + pub const fn sync(&self) -> bool { + let val = (self.0 >> 26usize) & 0x01; + val != 0 + } + #[doc = "Write '1' to disable interrupt for event SYNC"] + #[inline(always)] + pub fn set_sync(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); + } + #[doc = "Write '1' to disable interrupt for event PHYEND"] #[inline(always)] pub const fn phyend(&self) -> bool { let val = (self.0 >> 27usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for PHYEND event"] + #[doc = "Write '1' to disable interrupt for event PHYEND"] #[inline(always)] pub fn set_phyend(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize); @@ -15468,216 +21856,216 @@ pub mod radio { Sfd(0) } } - #[doc = "Shortcut register"] + #[doc = "Shortcuts between local events and tasks"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Shorts(pub u32); impl Shorts { - #[doc = "Shortcut between READY event and START task"] + #[doc = "Shortcut between event READY and task START"] #[inline(always)] pub const fn ready_start(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Shortcut between READY event and START task"] + #[doc = "Shortcut between event READY and task START"] #[inline(always)] pub fn set_ready_start(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - #[doc = "Shortcut between END event and DISABLE task"] + #[doc = "Shortcut between event END and task DISABLE"] #[inline(always)] pub const fn end_disable(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; val != 0 } - #[doc = "Shortcut between END event and DISABLE task"] + #[doc = "Shortcut between event END and task DISABLE"] #[inline(always)] pub fn set_end_disable(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } - #[doc = "Shortcut between DISABLED event and TXEN task"] + #[doc = "Shortcut between event DISABLED and task TXEN"] #[inline(always)] pub const fn disabled_txen(&self) -> bool { let val = (self.0 >> 2usize) & 0x01; val != 0 } - #[doc = "Shortcut between DISABLED event and TXEN task"] + #[doc = "Shortcut between event DISABLED and task TXEN"] #[inline(always)] pub fn set_disabled_txen(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); } - #[doc = "Shortcut between DISABLED event and RXEN task"] + #[doc = "Shortcut between event DISABLED and task RXEN"] #[inline(always)] pub const fn disabled_rxen(&self) -> bool { let val = (self.0 >> 3usize) & 0x01; val != 0 } - #[doc = "Shortcut between DISABLED event and RXEN task"] + #[doc = "Shortcut between event DISABLED and task RXEN"] #[inline(always)] pub fn set_disabled_rxen(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); } - #[doc = "Shortcut between ADDRESS event and RSSISTART task"] + #[doc = "Shortcut between event ADDRESS and task RSSISTART"] #[inline(always)] pub const fn address_rssistart(&self) -> bool { let val = (self.0 >> 4usize) & 0x01; val != 0 } - #[doc = "Shortcut between ADDRESS event and RSSISTART task"] + #[doc = "Shortcut between event ADDRESS and task RSSISTART"] #[inline(always)] pub fn set_address_rssistart(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); } - #[doc = "Shortcut between END event and START task"] + #[doc = "Shortcut between event END and task START"] #[inline(always)] pub const fn end_start(&self) -> bool { let val = (self.0 >> 5usize) & 0x01; val != 0 } - #[doc = "Shortcut between END event and START task"] + #[doc = "Shortcut between event END and task START"] #[inline(always)] pub fn set_end_start(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); } - #[doc = "Shortcut between ADDRESS event and BCSTART task"] + #[doc = "Shortcut between event ADDRESS and task BCSTART"] #[inline(always)] pub const fn address_bcstart(&self) -> bool { let val = (self.0 >> 6usize) & 0x01; val != 0 } - #[doc = "Shortcut between ADDRESS event and BCSTART task"] + #[doc = "Shortcut between event ADDRESS and task BCSTART"] #[inline(always)] pub fn set_address_bcstart(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); } - #[doc = "Shortcut between DISABLED event and RSSISTOP task"] + #[doc = "Shortcut between event DISABLED and task RSSISTOP"] #[inline(always)] pub const fn disabled_rssistop(&self) -> bool { let val = (self.0 >> 8usize) & 0x01; val != 0 } - #[doc = "Shortcut between DISABLED event and RSSISTOP task"] + #[doc = "Shortcut between event DISABLED and task RSSISTOP"] #[inline(always)] pub fn set_disabled_rssistop(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); } - #[doc = "Shortcut between RXREADY event and CCASTART task"] + #[doc = "Shortcut between event RXREADY and task CCASTART"] #[inline(always)] pub const fn rxready_ccastart(&self) -> bool { let val = (self.0 >> 11usize) & 0x01; val != 0 } - #[doc = "Shortcut between RXREADY event and CCASTART task"] + #[doc = "Shortcut between event RXREADY and task CCASTART"] #[inline(always)] pub fn set_rxready_ccastart(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); } - #[doc = "Shortcut between CCAIDLE event and TXEN task"] + #[doc = "Shortcut between event CCAIDLE and task TXEN"] #[inline(always)] pub const fn ccaidle_txen(&self) -> bool { let val = (self.0 >> 12usize) & 0x01; val != 0 } - #[doc = "Shortcut between CCAIDLE event and TXEN task"] + #[doc = "Shortcut between event CCAIDLE and task TXEN"] #[inline(always)] pub fn set_ccaidle_txen(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); } - #[doc = "Shortcut between CCABUSY event and DISABLE task"] + #[doc = "Shortcut between event CCABUSY and task DISABLE"] #[inline(always)] pub const fn ccabusy_disable(&self) -> bool { let val = (self.0 >> 13usize) & 0x01; val != 0 } - #[doc = "Shortcut between CCABUSY event and DISABLE task"] + #[doc = "Shortcut between event CCABUSY and task DISABLE"] #[inline(always)] pub fn set_ccabusy_disable(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); } - #[doc = "Shortcut between FRAMESTART event and BCSTART task"] + #[doc = "Shortcut between event FRAMESTART and task BCSTART"] #[inline(always)] pub const fn framestart_bcstart(&self) -> bool { let val = (self.0 >> 14usize) & 0x01; val != 0 } - #[doc = "Shortcut between FRAMESTART event and BCSTART task"] + #[doc = "Shortcut between event FRAMESTART and task BCSTART"] #[inline(always)] pub fn set_framestart_bcstart(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); } - #[doc = "Shortcut between READY event and EDSTART task"] + #[doc = "Shortcut between event READY and task EDSTART"] #[inline(always)] pub const fn ready_edstart(&self) -> bool { let val = (self.0 >> 15usize) & 0x01; val != 0 } - #[doc = "Shortcut between READY event and EDSTART task"] + #[doc = "Shortcut between event READY and task EDSTART"] #[inline(always)] pub fn set_ready_edstart(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); } - #[doc = "Shortcut between EDEND event and DISABLE task"] + #[doc = "Shortcut between event EDEND and task DISABLE"] #[inline(always)] pub const fn edend_disable(&self) -> bool { let val = (self.0 >> 16usize) & 0x01; val != 0 } - #[doc = "Shortcut between EDEND event and DISABLE task"] + #[doc = "Shortcut between event EDEND and task DISABLE"] #[inline(always)] pub fn set_edend_disable(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); } - #[doc = "Shortcut between CCAIDLE event and STOP task"] + #[doc = "Shortcut between event CCAIDLE and task STOP"] #[inline(always)] pub const fn ccaidle_stop(&self) -> bool { let val = (self.0 >> 17usize) & 0x01; val != 0 } - #[doc = "Shortcut between CCAIDLE event and STOP task"] + #[doc = "Shortcut between event CCAIDLE and task STOP"] #[inline(always)] pub fn set_ccaidle_stop(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); } - #[doc = "Shortcut between TXREADY event and START task"] + #[doc = "Shortcut between event TXREADY and task START"] #[inline(always)] pub const fn txready_start(&self) -> bool { let val = (self.0 >> 18usize) & 0x01; val != 0 } - #[doc = "Shortcut between TXREADY event and START task"] + #[doc = "Shortcut between event TXREADY and task START"] #[inline(always)] pub fn set_txready_start(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); } - #[doc = "Shortcut between RXREADY event and START task"] + #[doc = "Shortcut between event RXREADY and task START"] #[inline(always)] pub const fn rxready_start(&self) -> bool { let val = (self.0 >> 19usize) & 0x01; val != 0 } - #[doc = "Shortcut between RXREADY event and START task"] + #[doc = "Shortcut between event RXREADY and task START"] #[inline(always)] pub fn set_rxready_start(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize); } - #[doc = "Shortcut between PHYEND event and DISABLE task"] + #[doc = "Shortcut between event PHYEND and task DISABLE"] #[inline(always)] pub const fn phyend_disable(&self) -> bool { let val = (self.0 >> 20usize) & 0x01; val != 0 } - #[doc = "Shortcut between PHYEND event and DISABLE task"] + #[doc = "Shortcut between event PHYEND and task DISABLE"] #[inline(always)] pub fn set_phyend_disable(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize); } - #[doc = "Shortcut between PHYEND event and START task"] + #[doc = "Shortcut between event PHYEND and task START"] #[inline(always)] pub const fn phyend_start(&self) -> bool { let val = (self.0 >> 21usize) & 0x01; val != 0 } - #[doc = "Shortcut between PHYEND event and START task"] + #[doc = "Shortcut between event PHYEND and task START"] #[inline(always)] pub fn set_phyend_start(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize); @@ -16157,9 +22545,9 @@ pub mod radio { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Ru { - #[doc = "Default ramp-up time (tRXEN), compatible with firmware written for nRF51"] + #[doc = "Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51"] DEFAULT = 0x0, - #[doc = "Fast ramp-up (tRXEN,FAST), see electrical specification for more information"] + #[doc = "Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specification for more information"] FAST = 0x01, } impl Ru { @@ -16536,7 +22924,8 @@ pub mod radio { _RESERVED_df = 0xdf, _RESERVED_e0 = 0xe0, _RESERVED_e1 = 0xe1, - _RESERVED_e2 = 0xe2, + #[doc = "Deprecated enumerator - -40 dBm"] + NEG30_DBM = 0xe2, _RESERVED_e3 = 0xe3, _RESERVED_e4 = 0xe4, _RESERVED_e5 = 0xe5, @@ -16570,8 +22959,7 @@ pub mod radio { NEG4_DBM = 0xfc, _RESERVED_fd = 0xfd, _RESERVED_fe = 0xfe, - #[doc = "Deprecated enumerator - -40 dBm"] - NEG30_DBM = 0xff, + _RESERVED_ff = 0xff, } impl Txpower { #[inline(always)] @@ -16629,7 +23017,7 @@ pub mod rng { pub const fn events_valrdy(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0100usize) as _) } } - #[doc = "Shortcut register"] + #[doc = "Shortcuts between local events and tasks"] #[inline(always)] pub const fn shorts(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0200usize) as _) } @@ -16684,13 +23072,13 @@ pub mod rng { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Inten(pub u32); impl Inten { - #[doc = "Write '1' to disable interrupt for VALRDY event"] + #[doc = "Write '1' to disable interrupt for event VALRDY"] #[inline(always)] pub const fn valrdy(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for VALRDY event"] + #[doc = "Write '1' to disable interrupt for event VALRDY"] #[inline(always)] pub fn set_valrdy(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); @@ -16702,18 +23090,18 @@ pub mod rng { Inten(0) } } - #[doc = "Shortcut register"] + #[doc = "Shortcuts between local events and tasks"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Shorts(pub u32); impl Shorts { - #[doc = "Shortcut between VALRDY event and STOP task"] + #[doc = "Shortcut between event VALRDY and task STOP"] #[inline(always)] pub const fn valrdy_stop(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Shortcut between VALRDY event and STOP task"] + #[doc = "Shortcut between event VALRDY and task STOP"] #[inline(always)] pub fn set_valrdy_stop(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); @@ -16797,7 +23185,7 @@ pub mod rtc { pub const fn events_ovrflw(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0104usize) as _) } } - #[doc = "Description collection\\[n\\]: Compare event on CC\\[n\\] match"] + #[doc = "Description collection: Compare event on CC\\[n\\] match"] #[inline(always)] pub const fn events_compare(self, n: usize) -> crate::common::Reg { assert!(n < 4usize); @@ -16833,12 +23221,12 @@ pub mod rtc { pub const fn counter(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0504usize) as _) } } - #[doc = "12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped"] + #[doc = "12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is stopped."] #[inline(always)] pub const fn prescaler(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0508usize) as _) } } - #[doc = "Description collection\\[n\\]: Compare register n"] + #[doc = "Description collection: Compare register n"] #[inline(always)] pub const fn cc(self, n: usize) -> crate::common::Reg { assert!(n < 4usize); @@ -16846,7 +23234,7 @@ pub mod rtc { } } pub mod regs { - #[doc = "Description collection\\[n\\]: Compare register n"] + #[doc = "Description collection: Compare register n"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Cc(pub u32); @@ -16899,68 +23287,68 @@ pub mod rtc { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Evten(pub u32); impl Evten { - #[doc = "Enable or disable event routing for TICK event"] + #[doc = "Enable or disable event routing for event TICK"] #[inline(always)] pub const fn tick(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Enable or disable event routing for TICK event"] + #[doc = "Enable or disable event routing for event TICK"] #[inline(always)] pub fn set_tick(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - #[doc = "Enable or disable event routing for OVRFLW event"] + #[doc = "Enable or disable event routing for event OVRFLW"] #[inline(always)] pub const fn ovrflw(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; val != 0 } - #[doc = "Enable or disable event routing for OVRFLW event"] + #[doc = "Enable or disable event routing for event OVRFLW"] #[inline(always)] pub fn set_ovrflw(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } - #[doc = "Enable or disable event routing for COMPARE\\[0\\] event"] + #[doc = "Enable or disable event routing for event COMPARE\\[0\\]"] #[inline(always)] pub const fn compare0(&self) -> bool { let val = (self.0 >> 16usize) & 0x01; val != 0 } - #[doc = "Enable or disable event routing for COMPARE\\[0\\] event"] + #[doc = "Enable or disable event routing for event COMPARE\\[0\\]"] #[inline(always)] pub fn set_compare0(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); } - #[doc = "Enable or disable event routing for COMPARE\\[1\\] event"] + #[doc = "Enable or disable event routing for event COMPARE\\[1\\]"] #[inline(always)] pub const fn compare1(&self) -> bool { let val = (self.0 >> 17usize) & 0x01; val != 0 } - #[doc = "Enable or disable event routing for COMPARE\\[1\\] event"] + #[doc = "Enable or disable event routing for event COMPARE\\[1\\]"] #[inline(always)] pub fn set_compare1(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); } - #[doc = "Enable or disable event routing for COMPARE\\[2\\] event"] + #[doc = "Enable or disable event routing for event COMPARE\\[2\\]"] #[inline(always)] pub const fn compare2(&self) -> bool { let val = (self.0 >> 18usize) & 0x01; val != 0 } - #[doc = "Enable or disable event routing for COMPARE\\[2\\] event"] + #[doc = "Enable or disable event routing for event COMPARE\\[2\\]"] #[inline(always)] pub fn set_compare2(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); } - #[doc = "Enable or disable event routing for COMPARE\\[3\\] event"] + #[doc = "Enable or disable event routing for event COMPARE\\[3\\]"] #[inline(always)] pub const fn compare3(&self) -> bool { let val = (self.0 >> 19usize) & 0x01; val != 0 } - #[doc = "Enable or disable event routing for COMPARE\\[3\\] event"] + #[doc = "Enable or disable event routing for event COMPARE\\[3\\]"] #[inline(always)] pub fn set_compare3(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize); @@ -16977,68 +23365,68 @@ pub mod rtc { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Evtenclr(pub u32); impl Evtenclr { - #[doc = "Write '1' to disable event routing for TICK event"] + #[doc = "Write '1' to disable event routing for event TICK"] #[inline(always)] pub const fn tick(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable event routing for TICK event"] + #[doc = "Write '1' to disable event routing for event TICK"] #[inline(always)] pub fn set_tick(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - #[doc = "Write '1' to disable event routing for OVRFLW event"] + #[doc = "Write '1' to disable event routing for event OVRFLW"] #[inline(always)] pub const fn ovrflw(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable event routing for OVRFLW event"] + #[doc = "Write '1' to disable event routing for event OVRFLW"] #[inline(always)] pub fn set_ovrflw(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } - #[doc = "Write '1' to disable event routing for COMPARE\\[0\\] event"] + #[doc = "Write '1' to disable event routing for event COMPARE\\[0\\]"] #[inline(always)] pub const fn compare0(&self) -> bool { let val = (self.0 >> 16usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable event routing for COMPARE\\[0\\] event"] + #[doc = "Write '1' to disable event routing for event COMPARE\\[0\\]"] #[inline(always)] pub fn set_compare0(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); } - #[doc = "Write '1' to disable event routing for COMPARE\\[1\\] event"] + #[doc = "Write '1' to disable event routing for event COMPARE\\[1\\]"] #[inline(always)] pub const fn compare1(&self) -> bool { let val = (self.0 >> 17usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable event routing for COMPARE\\[1\\] event"] + #[doc = "Write '1' to disable event routing for event COMPARE\\[1\\]"] #[inline(always)] pub fn set_compare1(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); } - #[doc = "Write '1' to disable event routing for COMPARE\\[2\\] event"] + #[doc = "Write '1' to disable event routing for event COMPARE\\[2\\]"] #[inline(always)] pub const fn compare2(&self) -> bool { let val = (self.0 >> 18usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable event routing for COMPARE\\[2\\] event"] + #[doc = "Write '1' to disable event routing for event COMPARE\\[2\\]"] #[inline(always)] pub fn set_compare2(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); } - #[doc = "Write '1' to disable event routing for COMPARE\\[3\\] event"] + #[doc = "Write '1' to disable event routing for event COMPARE\\[3\\]"] #[inline(always)] pub const fn compare3(&self) -> bool { let val = (self.0 >> 19usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable event routing for COMPARE\\[3\\] event"] + #[doc = "Write '1' to disable event routing for event COMPARE\\[3\\]"] #[inline(always)] pub fn set_compare3(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize); @@ -17055,68 +23443,68 @@ pub mod rtc { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Evtenset(pub u32); impl Evtenset { - #[doc = "Write '1' to enable event routing for TICK event"] + #[doc = "Write '1' to enable event routing for event TICK"] #[inline(always)] pub const fn tick(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Write '1' to enable event routing for TICK event"] + #[doc = "Write '1' to enable event routing for event TICK"] #[inline(always)] pub fn set_tick(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - #[doc = "Write '1' to enable event routing for OVRFLW event"] + #[doc = "Write '1' to enable event routing for event OVRFLW"] #[inline(always)] pub const fn ovrflw(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; val != 0 } - #[doc = "Write '1' to enable event routing for OVRFLW event"] + #[doc = "Write '1' to enable event routing for event OVRFLW"] #[inline(always)] pub fn set_ovrflw(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } - #[doc = "Write '1' to enable event routing for COMPARE\\[0\\] event"] + #[doc = "Write '1' to enable event routing for event COMPARE\\[0\\]"] #[inline(always)] pub const fn compare0(&self) -> bool { let val = (self.0 >> 16usize) & 0x01; val != 0 } - #[doc = "Write '1' to enable event routing for COMPARE\\[0\\] event"] + #[doc = "Write '1' to enable event routing for event COMPARE\\[0\\]"] #[inline(always)] pub fn set_compare0(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); } - #[doc = "Write '1' to enable event routing for COMPARE\\[1\\] event"] + #[doc = "Write '1' to enable event routing for event COMPARE\\[1\\]"] #[inline(always)] pub const fn compare1(&self) -> bool { let val = (self.0 >> 17usize) & 0x01; val != 0 } - #[doc = "Write '1' to enable event routing for COMPARE\\[1\\] event"] + #[doc = "Write '1' to enable event routing for event COMPARE\\[1\\]"] #[inline(always)] pub fn set_compare1(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); } - #[doc = "Write '1' to enable event routing for COMPARE\\[2\\] event"] + #[doc = "Write '1' to enable event routing for event COMPARE\\[2\\]"] #[inline(always)] pub const fn compare2(&self) -> bool { let val = (self.0 >> 18usize) & 0x01; val != 0 } - #[doc = "Write '1' to enable event routing for COMPARE\\[2\\] event"] + #[doc = "Write '1' to enable event routing for event COMPARE\\[2\\]"] #[inline(always)] pub fn set_compare2(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); } - #[doc = "Write '1' to enable event routing for COMPARE\\[3\\] event"] + #[doc = "Write '1' to enable event routing for event COMPARE\\[3\\]"] #[inline(always)] pub const fn compare3(&self) -> bool { let val = (self.0 >> 19usize) & 0x01; val != 0 } - #[doc = "Write '1' to enable event routing for COMPARE\\[3\\] event"] + #[doc = "Write '1' to enable event routing for event COMPARE\\[3\\]"] #[inline(always)] pub fn set_compare3(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize); @@ -17133,68 +23521,68 @@ pub mod rtc { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Inten(pub u32); impl Inten { - #[doc = "Write '1' to disable interrupt for TICK event"] + #[doc = "Write '1' to disable interrupt for event TICK"] #[inline(always)] pub const fn tick(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for TICK event"] + #[doc = "Write '1' to disable interrupt for event TICK"] #[inline(always)] pub fn set_tick(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - #[doc = "Write '1' to disable interrupt for OVRFLW event"] + #[doc = "Write '1' to disable interrupt for event OVRFLW"] #[inline(always)] pub const fn ovrflw(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for OVRFLW event"] + #[doc = "Write '1' to disable interrupt for event OVRFLW"] #[inline(always)] pub fn set_ovrflw(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } - #[doc = "Write '1' to disable interrupt for COMPARE\\[0\\] event"] + #[doc = "Write '1' to disable interrupt for event COMPARE\\[0\\]"] #[inline(always)] pub const fn compare0(&self) -> bool { let val = (self.0 >> 16usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for COMPARE\\[0\\] event"] + #[doc = "Write '1' to disable interrupt for event COMPARE\\[0\\]"] #[inline(always)] pub fn set_compare0(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); } - #[doc = "Write '1' to disable interrupt for COMPARE\\[1\\] event"] + #[doc = "Write '1' to disable interrupt for event COMPARE\\[1\\]"] #[inline(always)] pub const fn compare1(&self) -> bool { let val = (self.0 >> 17usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for COMPARE\\[1\\] event"] + #[doc = "Write '1' to disable interrupt for event COMPARE\\[1\\]"] #[inline(always)] pub fn set_compare1(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); } - #[doc = "Write '1' to disable interrupt for COMPARE\\[2\\] event"] + #[doc = "Write '1' to disable interrupt for event COMPARE\\[2\\]"] #[inline(always)] pub const fn compare2(&self) -> bool { let val = (self.0 >> 18usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for COMPARE\\[2\\] event"] + #[doc = "Write '1' to disable interrupt for event COMPARE\\[2\\]"] #[inline(always)] pub fn set_compare2(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); } - #[doc = "Write '1' to disable interrupt for COMPARE\\[3\\] event"] + #[doc = "Write '1' to disable interrupt for event COMPARE\\[3\\]"] #[inline(always)] pub const fn compare3(&self) -> bool { let val = (self.0 >> 19usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for COMPARE\\[3\\] event"] + #[doc = "Write '1' to disable interrupt for event COMPARE\\[3\\]"] #[inline(always)] pub fn set_compare3(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize); @@ -17206,7 +23594,7 @@ pub mod rtc { Inten(0) } } - #[doc = "12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped"] + #[doc = "12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is stopped."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Prescaler(pub u32); @@ -17248,28 +23636,28 @@ pub mod saadc { pub const fn as_ptr(&self) -> *mut () { self.ptr as _ } - #[doc = "Description cluster\\[n\\]: Input positive pin selection for CH\\[n\\]"] + #[doc = "Description cluster: Input positive pin selection for CH\\[n\\]"] #[inline(always)] pub const fn pselp(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } - #[doc = "Description cluster\\[n\\]: Input negative pin selection for CH\\[n\\]"] + #[doc = "Description cluster: Input negative pin selection for CH\\[n\\]"] #[inline(always)] pub const fn pseln(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } - #[doc = "Description cluster\\[n\\]: Input configuration for CH\\[n\\]"] + #[doc = "Description cluster: Input configuration for CH\\[n\\]"] #[inline(always)] pub const fn config(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } - #[doc = "Description cluster\\[n\\]: High/low limits for event monitoring of a channel"] + #[doc = "Description cluster: High/low limits for event monitoring of a channel"] #[inline(always)] pub const fn limit(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } } } - #[doc = "Unspecified"] + #[doc = "Peripheral events."] #[derive(Copy, Clone, Eq, PartialEq)] pub struct EventsCh { ptr: *mut u8, @@ -17285,12 +23673,12 @@ pub mod saadc { pub const fn as_ptr(&self) -> *mut () { self.ptr as _ } - #[doc = "Description cluster\\[n\\]: Last result is equal or above CH\\[n\\].LIMIT.HIGH"] + #[doc = "Description cluster: Last result is equal or above CH\\[n\\].LIMIT.HIGH"] #[inline(always)] pub const fn limith(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } - #[doc = "Description cluster\\[n\\]: Last result is equal or below CH\\[n\\].LIMIT.LOW"] + #[doc = "Description cluster: Last result is equal or below CH\\[n\\].LIMIT.LOW"] #[inline(always)] pub const fn limitl(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } @@ -17394,7 +23782,7 @@ pub mod saadc { pub const fn events_stopped(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0114usize) as _) } } - #[doc = "Unspecified"] + #[doc = "Peripheral events."] #[inline(always)] pub const fn events_ch(self, n: usize) -> EventsCh { assert!(n < 8usize); @@ -17476,7 +23864,7 @@ pub mod saadc { Amount(0) } } - #[doc = "Description cluster\\[n\\]: Input configuration for CH\\[n\\]"] + #[doc = "Description cluster: Input configuration for CH\\[n\\]"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Config(pub u32); @@ -17596,244 +23984,244 @@ pub mod saadc { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Inten(pub u32); impl Inten { - #[doc = "Enable or disable interrupt for STARTED event"] + #[doc = "Enable or disable interrupt for event STARTED"] #[inline(always)] pub const fn started(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for STARTED event"] + #[doc = "Enable or disable interrupt for event STARTED"] #[inline(always)] pub fn set_started(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - #[doc = "Enable or disable interrupt for END event"] + #[doc = "Enable or disable interrupt for event END"] #[inline(always)] pub const fn end(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for END event"] + #[doc = "Enable or disable interrupt for event END"] #[inline(always)] pub fn set_end(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } - #[doc = "Enable or disable interrupt for DONE event"] + #[doc = "Enable or disable interrupt for event DONE"] #[inline(always)] pub const fn done(&self) -> bool { let val = (self.0 >> 2usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for DONE event"] + #[doc = "Enable or disable interrupt for event DONE"] #[inline(always)] pub fn set_done(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); } - #[doc = "Enable or disable interrupt for RESULTDONE event"] + #[doc = "Enable or disable interrupt for event RESULTDONE"] #[inline(always)] pub const fn resultdone(&self) -> bool { let val = (self.0 >> 3usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for RESULTDONE event"] + #[doc = "Enable or disable interrupt for event RESULTDONE"] #[inline(always)] pub fn set_resultdone(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); } - #[doc = "Enable or disable interrupt for CALIBRATEDONE event"] + #[doc = "Enable or disable interrupt for event CALIBRATEDONE"] #[inline(always)] pub const fn calibratedone(&self) -> bool { let val = (self.0 >> 4usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for CALIBRATEDONE event"] + #[doc = "Enable or disable interrupt for event CALIBRATEDONE"] #[inline(always)] pub fn set_calibratedone(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); } - #[doc = "Enable or disable interrupt for STOPPED event"] + #[doc = "Enable or disable interrupt for event STOPPED"] #[inline(always)] pub const fn stopped(&self) -> bool { let val = (self.0 >> 5usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for STOPPED event"] + #[doc = "Enable or disable interrupt for event STOPPED"] #[inline(always)] pub fn set_stopped(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); } - #[doc = "Enable or disable interrupt for CH\\[0\\].LIMITH event"] + #[doc = "Enable or disable interrupt for event CH0LIMITH"] #[inline(always)] pub const fn ch0limith(&self) -> bool { let val = (self.0 >> 6usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for CH\\[0\\].LIMITH event"] + #[doc = "Enable or disable interrupt for event CH0LIMITH"] #[inline(always)] pub fn set_ch0limith(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); } - #[doc = "Enable or disable interrupt for CH\\[0\\].LIMITL event"] + #[doc = "Enable or disable interrupt for event CH0LIMITL"] #[inline(always)] pub const fn ch0limitl(&self) -> bool { let val = (self.0 >> 7usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for CH\\[0\\].LIMITL event"] + #[doc = "Enable or disable interrupt for event CH0LIMITL"] #[inline(always)] pub fn set_ch0limitl(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); } - #[doc = "Enable or disable interrupt for CH\\[1\\].LIMITH event"] + #[doc = "Enable or disable interrupt for event CH1LIMITH"] #[inline(always)] pub const fn ch1limith(&self) -> bool { let val = (self.0 >> 8usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for CH\\[1\\].LIMITH event"] + #[doc = "Enable or disable interrupt for event CH1LIMITH"] #[inline(always)] pub fn set_ch1limith(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); } - #[doc = "Enable or disable interrupt for CH\\[1\\].LIMITL event"] + #[doc = "Enable or disable interrupt for event CH1LIMITL"] #[inline(always)] pub const fn ch1limitl(&self) -> bool { let val = (self.0 >> 9usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for CH\\[1\\].LIMITL event"] + #[doc = "Enable or disable interrupt for event CH1LIMITL"] #[inline(always)] pub fn set_ch1limitl(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); } - #[doc = "Enable or disable interrupt for CH\\[2\\].LIMITH event"] + #[doc = "Enable or disable interrupt for event CH2LIMITH"] #[inline(always)] pub const fn ch2limith(&self) -> bool { let val = (self.0 >> 10usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for CH\\[2\\].LIMITH event"] + #[doc = "Enable or disable interrupt for event CH2LIMITH"] #[inline(always)] pub fn set_ch2limith(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); } - #[doc = "Enable or disable interrupt for CH\\[2\\].LIMITL event"] + #[doc = "Enable or disable interrupt for event CH2LIMITL"] #[inline(always)] pub const fn ch2limitl(&self) -> bool { let val = (self.0 >> 11usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for CH\\[2\\].LIMITL event"] + #[doc = "Enable or disable interrupt for event CH2LIMITL"] #[inline(always)] pub fn set_ch2limitl(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); } - #[doc = "Enable or disable interrupt for CH\\[3\\].LIMITH event"] + #[doc = "Enable or disable interrupt for event CH3LIMITH"] #[inline(always)] pub const fn ch3limith(&self) -> bool { let val = (self.0 >> 12usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for CH\\[3\\].LIMITH event"] + #[doc = "Enable or disable interrupt for event CH3LIMITH"] #[inline(always)] pub fn set_ch3limith(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); } - #[doc = "Enable or disable interrupt for CH\\[3\\].LIMITL event"] + #[doc = "Enable or disable interrupt for event CH3LIMITL"] #[inline(always)] pub const fn ch3limitl(&self) -> bool { let val = (self.0 >> 13usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for CH\\[3\\].LIMITL event"] + #[doc = "Enable or disable interrupt for event CH3LIMITL"] #[inline(always)] pub fn set_ch3limitl(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); } - #[doc = "Enable or disable interrupt for CH\\[4\\].LIMITH event"] + #[doc = "Enable or disable interrupt for event CH4LIMITH"] #[inline(always)] pub const fn ch4limith(&self) -> bool { let val = (self.0 >> 14usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for CH\\[4\\].LIMITH event"] + #[doc = "Enable or disable interrupt for event CH4LIMITH"] #[inline(always)] pub fn set_ch4limith(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); } - #[doc = "Enable or disable interrupt for CH\\[4\\].LIMITL event"] + #[doc = "Enable or disable interrupt for event CH4LIMITL"] #[inline(always)] pub const fn ch4limitl(&self) -> bool { let val = (self.0 >> 15usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for CH\\[4\\].LIMITL event"] + #[doc = "Enable or disable interrupt for event CH4LIMITL"] #[inline(always)] pub fn set_ch4limitl(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); } - #[doc = "Enable or disable interrupt for CH\\[5\\].LIMITH event"] + #[doc = "Enable or disable interrupt for event CH5LIMITH"] #[inline(always)] pub const fn ch5limith(&self) -> bool { let val = (self.0 >> 16usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for CH\\[5\\].LIMITH event"] + #[doc = "Enable or disable interrupt for event CH5LIMITH"] #[inline(always)] pub fn set_ch5limith(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); } - #[doc = "Enable or disable interrupt for CH\\[5\\].LIMITL event"] + #[doc = "Enable or disable interrupt for event CH5LIMITL"] #[inline(always)] pub const fn ch5limitl(&self) -> bool { let val = (self.0 >> 17usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for CH\\[5\\].LIMITL event"] + #[doc = "Enable or disable interrupt for event CH5LIMITL"] #[inline(always)] pub fn set_ch5limitl(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); } - #[doc = "Enable or disable interrupt for CH\\[6\\].LIMITH event"] + #[doc = "Enable or disable interrupt for event CH6LIMITH"] #[inline(always)] pub const fn ch6limith(&self) -> bool { let val = (self.0 >> 18usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for CH\\[6\\].LIMITH event"] + #[doc = "Enable or disable interrupt for event CH6LIMITH"] #[inline(always)] pub fn set_ch6limith(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); } - #[doc = "Enable or disable interrupt for CH\\[6\\].LIMITL event"] + #[doc = "Enable or disable interrupt for event CH6LIMITL"] #[inline(always)] pub const fn ch6limitl(&self) -> bool { let val = (self.0 >> 19usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for CH\\[6\\].LIMITL event"] + #[doc = "Enable or disable interrupt for event CH6LIMITL"] #[inline(always)] pub fn set_ch6limitl(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize); } - #[doc = "Enable or disable interrupt for CH\\[7\\].LIMITH event"] + #[doc = "Enable or disable interrupt for event CH7LIMITH"] #[inline(always)] pub const fn ch7limith(&self) -> bool { let val = (self.0 >> 20usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for CH\\[7\\].LIMITH event"] + #[doc = "Enable or disable interrupt for event CH7LIMITH"] #[inline(always)] pub fn set_ch7limith(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize); } - #[doc = "Enable or disable interrupt for CH\\[7\\].LIMITL event"] + #[doc = "Enable or disable interrupt for event CH7LIMITL"] #[inline(always)] pub const fn ch7limitl(&self) -> bool { let val = (self.0 >> 21usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for CH\\[7\\].LIMITL event"] + #[doc = "Enable or disable interrupt for event CH7LIMITL"] #[inline(always)] pub fn set_ch7limitl(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize); @@ -17845,7 +24233,7 @@ pub mod saadc { Inten(0) } } - #[doc = "Description cluster\\[n\\]: High/low limits for event monitoring of a channel"] + #[doc = "Description cluster: High/low limits for event monitoring of a channel"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Limit(pub u32); @@ -17879,16 +24267,18 @@ pub mod saadc { Limit(0) } } - #[doc = "Description cluster\\[n\\]: Last result is equal or above CH\\[n\\].LIMIT.HIGH"] + #[doc = "Description cluster: Last result is equal or above CH\\[n\\].LIMIT.HIGH"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Limith(pub u32); impl Limith { + #[doc = "Last result is equal or above CH\\[n\\].LIMIT.HIGH"] #[inline(always)] pub const fn limith(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } + #[doc = "Last result is equal or above CH\\[n\\].LIMIT.HIGH"] #[inline(always)] pub fn set_limith(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); @@ -17900,16 +24290,18 @@ pub mod saadc { Limith(0) } } - #[doc = "Description cluster\\[n\\]: Last result is equal or below CH\\[n\\].LIMIT.LOW"] + #[doc = "Description cluster: Last result is equal or below CH\\[n\\].LIMIT.LOW"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Limitl(pub u32); impl Limitl { + #[doc = "Last result is equal or below CH\\[n\\].LIMIT.LOW"] #[inline(always)] pub const fn limitl(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } + #[doc = "Last result is equal or below CH\\[n\\].LIMIT.LOW"] #[inline(always)] pub fn set_limitl(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); @@ -17967,7 +24359,7 @@ pub mod saadc { Oversample(0) } } - #[doc = "Description cluster\\[n\\]: Input negative pin selection for CH\\[n\\]"] + #[doc = "Description cluster: Input negative pin selection for CH\\[n\\]"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Pseln(pub u32); @@ -17990,7 +24382,7 @@ pub mod saadc { Pseln(0) } } - #[doc = "Description cluster\\[n\\]: Input positive pin selection for CH\\[n\\]"] + #[doc = "Description cluster: Input positive pin selection for CH\\[n\\]"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Pselp(pub u32); @@ -18686,7 +25078,7 @@ pub mod spi { pub const fn psel(self) -> Psel { unsafe { Psel::from_ptr(self.ptr.add(0x0508usize) as _) } } - #[doc = "RXD register"] + #[doc = "RXD register. Register is cleared on read and the buffer pointer will be modified if read."] #[inline(always)] pub const fn rxd(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0518usize) as _) } @@ -18805,13 +25197,13 @@ pub mod spi { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Inten(pub u32); impl Inten { - #[doc = "Write '1' to disable interrupt for READY event"] + #[doc = "Write '1' to disable interrupt for event READY"] #[inline(always)] pub const fn ready(&self) -> bool { let val = (self.0 >> 2usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for READY event"] + #[doc = "Write '1' to disable interrupt for event READY"] #[inline(always)] pub fn set_ready(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); @@ -18823,7 +25215,7 @@ pub mod spi { Inten(0) } } - #[doc = "RXD register"] + #[doc = "RXD register. Register is cleared on read and the buffer pointer will be modified if read."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Rxd(pub u32); @@ -18851,13 +25243,13 @@ pub mod spi { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Txd(pub u32); impl Txd { - #[doc = "TX data to send. Double buffered"] + #[doc = "TX data to send. Double buffered."] #[inline(always)] pub const fn txd(&self) -> u8 { let val = (self.0 >> 0usize) & 0xff; val as u8 } - #[doc = "TX data to send. Double buffered"] + #[doc = "TX data to send. Double buffered."] #[inline(always)] pub fn set_txd(&mut self, val: u8) { self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); @@ -19068,7 +25460,7 @@ pub mod spim { pub const fn rxdelay(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } - #[doc = "Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions"] + #[doc = "Minimum duration between edge of CSN and edge of SCK at the start and the end of a transaction, and minimum duration CSN will stay high between transactions if END-START shortcut is used"] #[inline(always)] pub const fn csndur(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } @@ -19213,7 +25605,7 @@ pub mod spim { pub const fn events_started(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x014cusize) as _) } } - #[doc = "Shortcut register"] + #[doc = "Shortcuts between local events and tasks"] #[inline(always)] pub const fn shorts(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0200usize) as _) } @@ -19228,7 +25620,7 @@ pub mod spim { pub const fn intenclr(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0308usize) as _) } } - #[doc = "Stall status for EasyDMA RAM accesses. The fields in this register is set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU."] + #[doc = "Stall status for EasyDMA RAM accesses. The fields in this register are set to STALL by hardware whenever a stall occurs and can be cleared (set to NOSTALL) by the CPU."] #[inline(always)] pub const fn stallstat(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0400usize) as _) } @@ -19374,18 +25766,18 @@ pub mod spim { Config(0) } } - #[doc = "Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions"] + #[doc = "Minimum duration between edge of CSN and edge of SCK at the start and the end of a transaction, and minimum duration CSN will stay high between transactions if END-START shortcut is used"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Csndur(pub u32); impl Csndur { - #[doc = "Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns)."] + #[doc = "Minimum duration between edge of CSN and edge of SCK at the start and end of a transaction. If END-START shortcut is used, minimum duration CSN will stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns)."] #[inline(always)] pub const fn csndur(&self) -> u8 { let val = (self.0 >> 0usize) & 0xff; val as u8 } - #[doc = "Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns)."] + #[doc = "Minimum duration between edge of CSN and edge of SCK at the start and end of a transaction. If END-START shortcut is used, minimum duration CSN will stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns)."] #[inline(always)] pub fn set_csndur(&mut self, val: u8) { self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); @@ -19495,57 +25887,57 @@ pub mod spim { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Inten(pub u32); impl Inten { - #[doc = "Write '1' to disable interrupt for STOPPED event"] + #[doc = "Write '1' to disable interrupt for event STOPPED"] #[inline(always)] pub const fn stopped(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for STOPPED event"] + #[doc = "Write '1' to disable interrupt for event STOPPED"] #[inline(always)] pub fn set_stopped(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } - #[doc = "Write '1' to disable interrupt for ENDRX event"] + #[doc = "Write '1' to disable interrupt for event ENDRX"] #[inline(always)] pub const fn endrx(&self) -> bool { let val = (self.0 >> 4usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for ENDRX event"] + #[doc = "Write '1' to disable interrupt for event ENDRX"] #[inline(always)] pub fn set_endrx(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); } - #[doc = "Write '1' to disable interrupt for END event"] + #[doc = "Write '1' to disable interrupt for event END"] #[inline(always)] pub const fn end(&self) -> bool { let val = (self.0 >> 6usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for END event"] + #[doc = "Write '1' to disable interrupt for event END"] #[inline(always)] pub fn set_end(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); } - #[doc = "Write '1' to disable interrupt for ENDTX event"] + #[doc = "Write '1' to disable interrupt for event ENDTX"] #[inline(always)] pub const fn endtx(&self) -> bool { let val = (self.0 >> 8usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for ENDTX event"] + #[doc = "Write '1' to disable interrupt for event ENDTX"] #[inline(always)] pub fn set_endtx(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); } - #[doc = "Write '1' to disable interrupt for STARTED event"] + #[doc = "Write '1' to disable interrupt for event STARTED"] #[inline(always)] pub const fn started(&self) -> bool { let val = (self.0 >> 19usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for STARTED event"] + #[doc = "Write '1' to disable interrupt for event STARTED"] #[inline(always)] pub fn set_started(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize); @@ -19672,18 +26064,18 @@ pub mod spim { Rxdelay(0) } } - #[doc = "Shortcut register"] + #[doc = "Shortcuts between local events and tasks"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Shorts(pub u32); impl Shorts { - #[doc = "Shortcut between END event and START task"] + #[doc = "Shortcut between event END and task START"] #[inline(always)] pub const fn end_start(&self) -> bool { let val = (self.0 >> 17usize) & 0x01; val != 0 } - #[doc = "Shortcut between END event and START task"] + #[doc = "Shortcut between event END and task START"] #[inline(always)] pub fn set_end_start(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); @@ -19695,7 +26087,7 @@ pub mod spim { Shorts(0) } } - #[doc = "Stall status for EasyDMA RAM accesses. The fields in this register is set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU."] + #[doc = "Stall status for EasyDMA RAM accesses. The fields in this register are set to STALL by hardware whenever a stall occurs and can be cleared (set to NOSTALL) by the CPU."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Stallstat(pub u32); @@ -20146,6 +26538,11 @@ pub mod spis { pub const fn amount(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } + #[doc = "EasyDMA list type"] + #[inline(always)] + pub const fn list(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } + } } #[doc = "SPI Slave 0"] #[derive(Copy, Clone, Eq, PartialEq)] @@ -20188,7 +26585,7 @@ pub mod spis { pub const fn events_acquired(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0128usize) as _) } } - #[doc = "Shortcut register"] + #[doc = "Shortcuts between local events and tasks"] #[inline(always)] pub const fn shorts(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0200usize) as _) } @@ -20280,6 +26677,11 @@ pub mod spis { pub const fn amount(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } + #[doc = "EasyDMA list type"] + #[inline(always)] + pub const fn list(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } + } } pub mod regs { #[doc = "Configuration register"] @@ -20378,35 +26780,35 @@ pub mod spis { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Inten(pub u32); impl Inten { - #[doc = "Write '1' to disable interrupt for END event"] + #[doc = "Write '1' to disable interrupt for event END"] #[inline(always)] pub const fn end(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for END event"] + #[doc = "Write '1' to disable interrupt for event END"] #[inline(always)] pub fn set_end(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } - #[doc = "Write '1' to disable interrupt for ENDRX event"] + #[doc = "Write '1' to disable interrupt for event ENDRX"] #[inline(always)] pub const fn endrx(&self) -> bool { let val = (self.0 >> 4usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for ENDRX event"] + #[doc = "Write '1' to disable interrupt for event ENDRX"] #[inline(always)] pub fn set_endrx(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); } - #[doc = "Write '1' to disable interrupt for ACQUIRED event"] + #[doc = "Write '1' to disable interrupt for event ACQUIRED"] #[inline(always)] pub const fn acquired(&self) -> bool { let val = (self.0 >> 10usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for ACQUIRED event"] + #[doc = "Write '1' to disable interrupt for event ACQUIRED"] #[inline(always)] pub fn set_acquired(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); @@ -20464,6 +26866,29 @@ pub mod spis { RxdAmount(0) } } + #[doc = "EasyDMA list type"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct RxdList(pub u32); + impl RxdList { + #[doc = "List type"] + #[inline(always)] + pub const fn list(&self) -> super::vals::RxdListList { + let val = (self.0 >> 0usize) & 0x03; + super::vals::RxdListList::from_bits(val as u8) + } + #[doc = "List type"] + #[inline(always)] + pub fn set_list(&mut self, val: super::vals::RxdListList) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); + } + } + impl Default for RxdList { + #[inline(always)] + fn default() -> RxdList { + RxdList(0) + } + } #[doc = "Maximum number of bytes in receive buffer"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -20510,18 +26935,18 @@ pub mod spis { Semstat(0) } } - #[doc = "Shortcut register"] + #[doc = "Shortcuts between local events and tasks"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Shorts(pub u32); impl Shorts { - #[doc = "Shortcut between END event and ACQUIRE task"] + #[doc = "Shortcut between event END and task ACQUIRE"] #[inline(always)] pub const fn end_acquire(&self) -> bool { let val = (self.0 >> 2usize) & 0x01; val != 0 } - #[doc = "Shortcut between END event and ACQUIRE task"] + #[doc = "Shortcut between event END and task ACQUIRE"] #[inline(always)] pub fn set_end_acquire(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); @@ -20590,6 +27015,29 @@ pub mod spis { TxdAmount(0) } } + #[doc = "EasyDMA list type"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct TxdList(pub u32); + impl TxdList { + #[doc = "List type"] + #[inline(always)] + pub const fn list(&self) -> super::vals::TxdListList { + let val = (self.0 >> 0usize) & 0x03; + super::vals::TxdListList::from_bits(val as u8) + } + #[doc = "List type"] + #[inline(always)] + pub fn set_list(&mut self, val: super::vals::TxdListList) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); + } + } + impl Default for TxdList { + #[inline(always)] + fn default() -> TxdList { + TxdList(0) + } + } #[doc = "Maximum number of bytes in transmit buffer"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -20751,6 +27199,38 @@ pub mod spis { } #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum RxdListList { + #[doc = "Disable EasyDMA list"] + DISABLED = 0x0, + #[doc = "Use array list"] + ARRAY_LIST = 0x01, + _RESERVED_2 = 0x02, + _RESERVED_3 = 0x03, + } + impl RxdListList { + #[inline(always)] + pub const fn from_bits(val: u8) -> RxdListList { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for RxdListList { + #[inline(always)] + fn from(val: u8) -> RxdListList { + RxdListList::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: RxdListList) -> u8 { + RxdListList::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Semstat { #[doc = "Semaphore is free"] FREE = 0x0, @@ -20783,6 +27263,38 @@ pub mod spis { Semstat::to_bits(val) } } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum TxdListList { + #[doc = "Disable EasyDMA list"] + DISABLED = 0x0, + #[doc = "Use array list"] + ARRAY_LIST = 0x01, + _RESERVED_2 = 0x02, + _RESERVED_3 = 0x03, + } + impl TxdListList { + #[inline(always)] + pub const fn from_bits(val: u8) -> TxdListList { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for TxdListList { + #[inline(always)] + fn from(val: u8) -> TxdListList { + TxdListList::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: TxdListList) -> u8 { + TxdListList::to_bits(val) + } + } } } pub mod swi { @@ -20856,105 +27368,105 @@ pub mod temp { pub const fn temp(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0508usize) as _) } } - #[doc = "Slope of 1st piece wise linear function"] + #[doc = "Slope of first piecewise linear function"] #[inline(always)] pub const fn a0(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0520usize) as _) } } - #[doc = "Slope of 2nd piece wise linear function"] + #[doc = "Slope of second piecewise linear function"] #[inline(always)] pub const fn a1(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0524usize) as _) } } - #[doc = "Slope of 3rd piece wise linear function"] + #[doc = "Slope of third piecewise linear function"] #[inline(always)] pub const fn a2(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0528usize) as _) } } - #[doc = "Slope of 4th piece wise linear function"] + #[doc = "Slope of fourth piecewise linear function"] #[inline(always)] pub const fn a3(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x052cusize) as _) } } - #[doc = "Slope of 5th piece wise linear function"] + #[doc = "Slope of fifth piecewise linear function"] #[inline(always)] pub const fn a4(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0530usize) as _) } } - #[doc = "Slope of 6th piece wise linear function"] + #[doc = "Slope of sixth piecewise linear function"] #[inline(always)] pub const fn a5(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0534usize) as _) } } - #[doc = "y-intercept of 1st piece wise linear function"] + #[doc = "y-intercept of first piecewise linear function"] #[inline(always)] pub const fn b0(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0540usize) as _) } } - #[doc = "y-intercept of 2nd piece wise linear function"] + #[doc = "y-intercept of second piecewise linear function"] #[inline(always)] pub const fn b1(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0544usize) as _) } } - #[doc = "y-intercept of 3rd piece wise linear function"] + #[doc = "y-intercept of third piecewise linear function"] #[inline(always)] pub const fn b2(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0548usize) as _) } } - #[doc = "y-intercept of 4th piece wise linear function"] + #[doc = "y-intercept of fourth piecewise linear function"] #[inline(always)] pub const fn b3(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x054cusize) as _) } } - #[doc = "y-intercept of 5th piece wise linear function"] + #[doc = "y-intercept of fifth piecewise linear function"] #[inline(always)] pub const fn b4(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0550usize) as _) } } - #[doc = "y-intercept of 6th piece wise linear function"] + #[doc = "y-intercept of sixth piecewise linear function"] #[inline(always)] pub const fn b5(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0554usize) as _) } } - #[doc = "End point of 1st piece wise linear function"] + #[doc = "End point of first piecewise linear function"] #[inline(always)] pub const fn t0(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0560usize) as _) } } - #[doc = "End point of 2nd piece wise linear function"] + #[doc = "End point of second piecewise linear function"] #[inline(always)] pub const fn t1(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0564usize) as _) } } - #[doc = "End point of 3rd piece wise linear function"] + #[doc = "End point of third piecewise linear function"] #[inline(always)] pub const fn t2(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0568usize) as _) } } - #[doc = "End point of 4th piece wise linear function"] + #[doc = "End point of fourth piecewise linear function"] #[inline(always)] pub const fn t3(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x056cusize) as _) } } - #[doc = "End point of 5th piece wise linear function"] + #[doc = "End point of fifth piecewise linear function"] #[inline(always)] pub const fn t4(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0570usize) as _) } } } pub mod regs { - #[doc = "Slope of 1st piece wise linear function"] + #[doc = "Slope of first piecewise linear function"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct A0(pub u32); impl A0 { - #[doc = "Slope of 1st piece wise linear function"] + #[doc = "Slope of first piecewise linear function"] #[inline(always)] pub const fn a0(&self) -> u16 { let val = (self.0 >> 0usize) & 0x0fff; val as u16 } - #[doc = "Slope of 1st piece wise linear function"] + #[doc = "Slope of first piecewise linear function"] #[inline(always)] pub fn set_a0(&mut self, val: u16) { self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); @@ -20966,18 +27478,18 @@ pub mod temp { A0(0) } } - #[doc = "Slope of 2nd piece wise linear function"] + #[doc = "Slope of second piecewise linear function"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct A1(pub u32); impl A1 { - #[doc = "Slope of 2nd piece wise linear function"] + #[doc = "Slope of second piecewise linear function"] #[inline(always)] pub const fn a1(&self) -> u16 { let val = (self.0 >> 0usize) & 0x0fff; val as u16 } - #[doc = "Slope of 2nd piece wise linear function"] + #[doc = "Slope of second piecewise linear function"] #[inline(always)] pub fn set_a1(&mut self, val: u16) { self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); @@ -20989,18 +27501,18 @@ pub mod temp { A1(0) } } - #[doc = "Slope of 3rd piece wise linear function"] + #[doc = "Slope of third piecewise linear function"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct A2(pub u32); impl A2 { - #[doc = "Slope of 3rd piece wise linear function"] + #[doc = "Slope of third piecewise linear function"] #[inline(always)] pub const fn a2(&self) -> u16 { let val = (self.0 >> 0usize) & 0x0fff; val as u16 } - #[doc = "Slope of 3rd piece wise linear function"] + #[doc = "Slope of third piecewise linear function"] #[inline(always)] pub fn set_a2(&mut self, val: u16) { self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); @@ -21012,18 +27524,18 @@ pub mod temp { A2(0) } } - #[doc = "Slope of 4th piece wise linear function"] + #[doc = "Slope of fourth piecewise linear function"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct A3(pub u32); impl A3 { - #[doc = "Slope of 4th piece wise linear function"] + #[doc = "Slope of fourth piecewise linear function"] #[inline(always)] pub const fn a3(&self) -> u16 { let val = (self.0 >> 0usize) & 0x0fff; val as u16 } - #[doc = "Slope of 4th piece wise linear function"] + #[doc = "Slope of fourth piecewise linear function"] #[inline(always)] pub fn set_a3(&mut self, val: u16) { self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); @@ -21035,18 +27547,18 @@ pub mod temp { A3(0) } } - #[doc = "Slope of 5th piece wise linear function"] + #[doc = "Slope of fifth piecewise linear function"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct A4(pub u32); impl A4 { - #[doc = "Slope of 5th piece wise linear function"] + #[doc = "Slope of fifth piecewise linear function"] #[inline(always)] pub const fn a4(&self) -> u16 { let val = (self.0 >> 0usize) & 0x0fff; val as u16 } - #[doc = "Slope of 5th piece wise linear function"] + #[doc = "Slope of fifth piecewise linear function"] #[inline(always)] pub fn set_a4(&mut self, val: u16) { self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); @@ -21058,18 +27570,18 @@ pub mod temp { A4(0) } } - #[doc = "Slope of 6th piece wise linear function"] + #[doc = "Slope of sixth piecewise linear function"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct A5(pub u32); impl A5 { - #[doc = "Slope of 6th piece wise linear function"] + #[doc = "Slope of sixth piecewise linear function"] #[inline(always)] pub const fn a5(&self) -> u16 { let val = (self.0 >> 0usize) & 0x0fff; val as u16 } - #[doc = "Slope of 6th piece wise linear function"] + #[doc = "Slope of sixth piecewise linear function"] #[inline(always)] pub fn set_a5(&mut self, val: u16) { self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); @@ -21081,18 +27593,18 @@ pub mod temp { A5(0) } } - #[doc = "y-intercept of 1st piece wise linear function"] + #[doc = "y-intercept of first piecewise linear function"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct B0(pub u32); impl B0 { - #[doc = "y-intercept of 1st piece wise linear function"] + #[doc = "y-intercept of first piecewise linear function"] #[inline(always)] pub const fn b0(&self) -> u16 { let val = (self.0 >> 0usize) & 0x3fff; val as u16 } - #[doc = "y-intercept of 1st piece wise linear function"] + #[doc = "y-intercept of first piecewise linear function"] #[inline(always)] pub fn set_b0(&mut self, val: u16) { self.0 = (self.0 & !(0x3fff << 0usize)) | (((val as u32) & 0x3fff) << 0usize); @@ -21104,18 +27616,18 @@ pub mod temp { B0(0) } } - #[doc = "y-intercept of 2nd piece wise linear function"] + #[doc = "y-intercept of second piecewise linear function"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct B1(pub u32); impl B1 { - #[doc = "y-intercept of 2nd piece wise linear function"] + #[doc = "y-intercept of second piecewise linear function"] #[inline(always)] pub const fn b1(&self) -> u16 { let val = (self.0 >> 0usize) & 0x3fff; val as u16 } - #[doc = "y-intercept of 2nd piece wise linear function"] + #[doc = "y-intercept of second piecewise linear function"] #[inline(always)] pub fn set_b1(&mut self, val: u16) { self.0 = (self.0 & !(0x3fff << 0usize)) | (((val as u32) & 0x3fff) << 0usize); @@ -21127,18 +27639,18 @@ pub mod temp { B1(0) } } - #[doc = "y-intercept of 3rd piece wise linear function"] + #[doc = "y-intercept of third piecewise linear function"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct B2(pub u32); impl B2 { - #[doc = "y-intercept of 3rd piece wise linear function"] + #[doc = "y-intercept of third piecewise linear function"] #[inline(always)] pub const fn b2(&self) -> u16 { let val = (self.0 >> 0usize) & 0x3fff; val as u16 } - #[doc = "y-intercept of 3rd piece wise linear function"] + #[doc = "y-intercept of third piecewise linear function"] #[inline(always)] pub fn set_b2(&mut self, val: u16) { self.0 = (self.0 & !(0x3fff << 0usize)) | (((val as u32) & 0x3fff) << 0usize); @@ -21150,328 +27662,73 @@ pub mod temp { B2(0) } } - #[doc = "y-intercept of 4th piece wise linear function"] + #[doc = "y-intercept of fourth piecewise linear function"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct B3(pub u32); impl B3 { - #[doc = "y-intercept of 4th piece wise linear function"] - #[inline(always)] - pub const fn b3(&self) -> u16 { - let val = (self.0 >> 0usize) & 0x3fff; - val as u16 - } - #[doc = "y-intercept of 4th piece wise linear function"] - #[inline(always)] - pub fn set_b3(&mut self, val: u16) { - self.0 = (self.0 & !(0x3fff << 0usize)) | (((val as u32) & 0x3fff) << 0usize); - } - } - impl Default for B3 { - #[inline(always)] - fn default() -> B3 { - B3(0) - } - } - #[doc = "y-intercept of 5th piece wise linear function"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct B4(pub u32); - impl B4 { - #[doc = "y-intercept of 5th piece wise linear function"] - #[inline(always)] - pub const fn b4(&self) -> u16 { - let val = (self.0 >> 0usize) & 0x3fff; - val as u16 - } - #[doc = "y-intercept of 5th piece wise linear function"] - #[inline(always)] - pub fn set_b4(&mut self, val: u16) { - self.0 = (self.0 & !(0x3fff << 0usize)) | (((val as u32) & 0x3fff) << 0usize); - } - } - impl Default for B4 { - #[inline(always)] - fn default() -> B4 { - B4(0) - } - } - #[doc = "y-intercept of 6th piece wise linear function"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct B5(pub u32); - impl B5 { - #[doc = "y-intercept of 6th piece wise linear function"] - #[inline(always)] - pub const fn b5(&self) -> u16 { - let val = (self.0 >> 0usize) & 0x3fff; - val as u16 - } - #[doc = "y-intercept of 6th piece wise linear function"] - #[inline(always)] - pub fn set_b5(&mut self, val: u16) { - self.0 = (self.0 & !(0x3fff << 0usize)) | (((val as u32) & 0x3fff) << 0usize); - } - } - impl Default for B5 { - #[inline(always)] - fn default() -> B5 { - B5(0) - } - } - #[doc = "Disable interrupt"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Inten(pub u32); - impl Inten { - #[doc = "Write '1' to disable interrupt for DATARDY event"] - #[inline(always)] - pub const fn datardy(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "Write '1' to disable interrupt for DATARDY event"] - #[inline(always)] - pub fn set_datardy(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - } - impl Default for Inten { - #[inline(always)] - fn default() -> Inten { - Inten(0) - } - } - #[doc = "End point of 1st piece wise linear function"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct T0(pub u32); - impl T0 { - #[doc = "End point of 1st piece wise linear function"] - #[inline(always)] - pub const fn t0(&self) -> u8 { - let val = (self.0 >> 0usize) & 0xff; - val as u8 - } - #[doc = "End point of 1st piece wise linear function"] - #[inline(always)] - pub fn set_t0(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); - } - } - impl Default for T0 { - #[inline(always)] - fn default() -> T0 { - T0(0) - } - } - #[doc = "End point of 2nd piece wise linear function"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct T1(pub u32); - impl T1 { - #[doc = "End point of 2nd piece wise linear function"] - #[inline(always)] - pub const fn t1(&self) -> u8 { - let val = (self.0 >> 0usize) & 0xff; - val as u8 - } - #[doc = "End point of 2nd piece wise linear function"] - #[inline(always)] - pub fn set_t1(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); - } - } - impl Default for T1 { - #[inline(always)] - fn default() -> T1 { - T1(0) - } - } - #[doc = "End point of 3rd piece wise linear function"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct T2(pub u32); - impl T2 { - #[doc = "End point of 3rd piece wise linear function"] - #[inline(always)] - pub const fn t2(&self) -> u8 { - let val = (self.0 >> 0usize) & 0xff; - val as u8 - } - #[doc = "End point of 3rd piece wise linear function"] - #[inline(always)] - pub fn set_t2(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); - } - } - impl Default for T2 { - #[inline(always)] - fn default() -> T2 { - T2(0) - } - } - #[doc = "End point of 4th piece wise linear function"] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct T3(pub u32); - impl T3 { - #[doc = "End point of 4th piece wise linear function"] + #[doc = "y-intercept of fourth piecewise linear function"] #[inline(always)] - pub const fn t3(&self) -> u8 { - let val = (self.0 >> 0usize) & 0xff; - val as u8 + pub const fn b3(&self) -> u16 { + let val = (self.0 >> 0usize) & 0x3fff; + val as u16 } - #[doc = "End point of 4th piece wise linear function"] + #[doc = "y-intercept of fourth piecewise linear function"] #[inline(always)] - pub fn set_t3(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); + pub fn set_b3(&mut self, val: u16) { + self.0 = (self.0 & !(0x3fff << 0usize)) | (((val as u32) & 0x3fff) << 0usize); } } - impl Default for T3 { + impl Default for B3 { #[inline(always)] - fn default() -> T3 { - T3(0) + fn default() -> B3 { + B3(0) } } - #[doc = "End point of 5th piece wise linear function"] + #[doc = "y-intercept of fifth piecewise linear function"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct T4(pub u32); - impl T4 { - #[doc = "End point of 5th piece wise linear function"] + pub struct B4(pub u32); + impl B4 { + #[doc = "y-intercept of fifth piecewise linear function"] #[inline(always)] - pub const fn t4(&self) -> u8 { - let val = (self.0 >> 0usize) & 0xff; - val as u8 + pub const fn b4(&self) -> u16 { + let val = (self.0 >> 0usize) & 0x3fff; + val as u16 } - #[doc = "End point of 5th piece wise linear function"] + #[doc = "y-intercept of fifth piecewise linear function"] #[inline(always)] - pub fn set_t4(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); + pub fn set_b4(&mut self, val: u16) { + self.0 = (self.0 & !(0x3fff << 0usize)) | (((val as u32) & 0x3fff) << 0usize); } } - impl Default for T4 { + impl Default for B4 { #[inline(always)] - fn default() -> T4 { - T4(0) + fn default() -> B4 { + B4(0) } } - } -} -pub mod timer { - #[doc = "Timer/Counter 0"] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Timer { - ptr: *mut u8, - } - unsafe impl Send for Timer {} - unsafe impl Sync for Timer {} - impl Timer { - #[inline(always)] - pub const unsafe fn from_ptr(ptr: *mut ()) -> Self { - Self { ptr: ptr as _ } - } - #[inline(always)] - pub const fn as_ptr(&self) -> *mut () { - self.ptr as _ - } - #[doc = "Start Timer"] - #[inline(always)] - pub const fn tasks_start(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } - } - #[doc = "Stop Timer"] - #[inline(always)] - pub const fn tasks_stop(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } - } - #[doc = "Increment Timer (Counter mode only)"] - #[inline(always)] - pub const fn tasks_count(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } - } - #[doc = "Clear time"] - #[inline(always)] - pub const fn tasks_clear(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } - } - #[doc = "Deprecated register - Shut down timer"] - #[inline(always)] - pub const fn tasks_shutdown(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } - } - #[doc = "Description collection\\[n\\]: Capture Timer value to CC\\[n\\] register"] - #[inline(always)] - pub const fn tasks_capture(self, n: usize) -> crate::common::Reg { - assert!(n < 4usize); - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x40usize + n * 4usize) as _) } - } - #[doc = "Description collection\\[n\\]: Compare event on CC\\[n\\] match"] - #[inline(always)] - pub const fn events_compare(self, n: usize) -> crate::common::Reg { - assert!(n < 4usize); - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0140usize + n * 4usize) as _) } - } - #[doc = "Shortcut register"] - #[inline(always)] - pub const fn shorts(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0200usize) as _) } - } - #[doc = "Enable interrupt"] - #[inline(always)] - pub const fn intenset(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0304usize) as _) } - } - #[doc = "Disable interrupt"] - #[inline(always)] - pub const fn intenclr(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0308usize) as _) } - } - #[doc = "Timer mode selection"] - #[inline(always)] - pub const fn mode(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0504usize) as _) } - } - #[doc = "Configure the number of bits used by the TIMER"] - #[inline(always)] - pub const fn bitmode(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0508usize) as _) } - } - #[doc = "Timer prescaler register"] - #[inline(always)] - pub const fn prescaler(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0510usize) as _) } - } - #[doc = "Description collection\\[n\\]: Capture/Compare register n"] - #[inline(always)] - pub const fn cc(self, n: usize) -> crate::common::Reg { - assert!(n < 4usize); - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0540usize + n * 4usize) as _) } - } - } - pub mod regs { - #[doc = "Configure the number of bits used by the TIMER"] + #[doc = "y-intercept of sixth piecewise linear function"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Bitmode(pub u32); - impl Bitmode { - #[doc = "Timer bit width"] + pub struct B5(pub u32); + impl B5 { + #[doc = "y-intercept of sixth piecewise linear function"] #[inline(always)] - pub const fn bitmode(&self) -> super::vals::Bitmode { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Bitmode::from_bits(val as u8) + pub const fn b5(&self) -> u16 { + let val = (self.0 >> 0usize) & 0x3fff; + val as u16 } - #[doc = "Timer bit width"] + #[doc = "y-intercept of sixth piecewise linear function"] #[inline(always)] - pub fn set_bitmode(&mut self, val: super::vals::Bitmode) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); + pub fn set_b5(&mut self, val: u16) { + self.0 = (self.0 & !(0x3fff << 0usize)) | (((val as u32) & 0x3fff) << 0usize); } } - impl Default for Bitmode { + impl Default for B5 { #[inline(always)] - fn default() -> Bitmode { - Bitmode(0) + fn default() -> B5 { + B5(0) } } #[doc = "Disable interrupt"] @@ -21479,20 +27736,16 @@ pub mod timer { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Inten(pub u32); impl Inten { - #[doc = "Write '1' to disable interrupt for COMPARE\\[0\\] event"] + #[doc = "Write '1' to disable interrupt for event DATARDY"] #[inline(always)] - pub const fn compare(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 16usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; + pub const fn datardy(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for COMPARE\\[0\\] event"] + #[doc = "Write '1' to disable interrupt for event DATARDY"] #[inline(always)] - pub fn set_compare(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 16usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + pub fn set_datardy(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } } impl Default for Inten { @@ -21501,174 +27754,132 @@ pub mod timer { Inten(0) } } - #[doc = "Timer mode selection"] + #[doc = "End point of first piecewise linear function"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Mode(pub u32); - impl Mode { - #[doc = "Timer mode"] + pub struct T0(pub u32); + impl T0 { + #[doc = "End point of first piecewise linear function"] #[inline(always)] - pub const fn mode(&self) -> super::vals::Mode { - let val = (self.0 >> 0usize) & 0x03; - super::vals::Mode::from_bits(val as u8) + pub const fn t0(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 } - #[doc = "Timer mode"] + #[doc = "End point of first piecewise linear function"] #[inline(always)] - pub fn set_mode(&mut self, val: super::vals::Mode) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); + pub fn set_t0(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); } } - impl Default for Mode { + impl Default for T0 { #[inline(always)] - fn default() -> Mode { - Mode(0) + fn default() -> T0 { + T0(0) } } - #[doc = "Timer prescaler register"] + #[doc = "End point of second piecewise linear function"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Prescaler(pub u32); - impl Prescaler { - #[doc = "Prescaler value"] + pub struct T1(pub u32); + impl T1 { + #[doc = "End point of second piecewise linear function"] #[inline(always)] - pub const fn prescaler(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; + pub const fn t1(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; val as u8 } - #[doc = "Prescaler value"] + #[doc = "End point of second piecewise linear function"] #[inline(always)] - pub fn set_prescaler(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + pub fn set_t1(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); } } - impl Default for Prescaler { + impl Default for T1 { #[inline(always)] - fn default() -> Prescaler { - Prescaler(0) + fn default() -> T1 { + T1(0) } } - #[doc = "Shortcut register"] + #[doc = "End point of third piecewise linear function"] #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Shorts(pub u32); - impl Shorts { - #[doc = "Shortcut between COMPARE\\[0\\] event and CLEAR task"] - #[inline(always)] - pub const fn compare_clear(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 0usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Shortcut between COMPARE\\[0\\] event and CLEAR task"] - #[inline(always)] - pub fn set_compare_clear(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 0usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - #[doc = "Shortcut between COMPARE\\[0\\] event and STOP task"] - #[inline(always)] - pub const fn compare_stop(&self, n: usize) -> bool { - assert!(n < 4usize); - let offs = 8usize + n * 1usize; - let val = (self.0 >> offs) & 0x01; - val != 0 - } - #[doc = "Shortcut between COMPARE\\[0\\] event and STOP task"] - #[inline(always)] - pub fn set_compare_stop(&mut self, n: usize, val: bool) { - assert!(n < 4usize); - let offs = 8usize + n * 1usize; - self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); - } - } - impl Default for Shorts { - #[inline(always)] - fn default() -> Shorts { - Shorts(0) - } - } - } - pub mod vals { - #[repr(u8)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub enum Bitmode { - #[doc = "16 bit timer bit width"] - _16BIT = 0x0, - #[doc = "8 bit timer bit width"] - _08BIT = 0x01, - #[doc = "24 bit timer bit width"] - _24BIT = 0x02, - #[doc = "32 bit timer bit width"] - _32BIT = 0x03, - } - impl Bitmode { + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct T2(pub u32); + impl T2 { + #[doc = "End point of third piecewise linear function"] #[inline(always)] - pub const fn from_bits(val: u8) -> Bitmode { - unsafe { core::mem::transmute(val & 0x03) } + pub const fn t2(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 } + #[doc = "End point of third piecewise linear function"] #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } + pub fn set_t2(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); } } - impl From for Bitmode { + impl Default for T2 { #[inline(always)] - fn from(val: u8) -> Bitmode { - Bitmode::from_bits(val) + fn default() -> T2 { + T2(0) } } - impl From for u8 { + #[doc = "End point of fourth piecewise linear function"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct T3(pub u32); + impl T3 { + #[doc = "End point of fourth piecewise linear function"] #[inline(always)] - fn from(val: Bitmode) -> u8 { - Bitmode::to_bits(val) + pub const fn t3(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 } - } - #[repr(u8)] - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] - pub enum Mode { - #[doc = "Select Timer mode"] - TIMER = 0x0, - #[doc = "Deprecated enumerator - Select Counter mode"] - COUNTER = 0x01, - #[doc = "Select Low Power Counter mode"] - LOW_POWER_COUNTER = 0x02, - _RESERVED_3 = 0x03, - } - impl Mode { + #[doc = "End point of fourth piecewise linear function"] #[inline(always)] - pub const fn from_bits(val: u8) -> Mode { - unsafe { core::mem::transmute(val & 0x03) } + pub fn set_t3(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); } + } + impl Default for T3 { #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } + fn default() -> T3 { + T3(0) } } - impl From for Mode { + #[doc = "End point of fifth piecewise linear function"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct T4(pub u32); + impl T4 { + #[doc = "End point of fifth piecewise linear function"] #[inline(always)] - fn from(val: u8) -> Mode { - Mode::from_bits(val) + pub const fn t4(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 + } + #[doc = "End point of fifth piecewise linear function"] + #[inline(always)] + pub fn set_t4(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); } } - impl From for u8 { + impl Default for T4 { #[inline(always)] - fn from(val: Mode) -> u8 { - Mode::to_bits(val) + fn default() -> T4 { + T4(0) } } } } -pub mod timer3 { - #[doc = "Timer/Counter 3"] +pub mod timer { + #[doc = "Timer/Counter 0"] #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Timer3 { + pub struct Timer { ptr: *mut u8, } - unsafe impl Send for Timer3 {} - unsafe impl Sync for Timer3 {} - impl Timer3 { + unsafe impl Send for Timer {} + unsafe impl Sync for Timer {} + impl Timer { #[inline(always)] pub const unsafe fn from_ptr(ptr: *mut ()) -> Self { Self { ptr: ptr as _ } @@ -21702,19 +27913,19 @@ pub mod timer3 { pub const fn tasks_shutdown(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } } - #[doc = "Description collection\\[n\\]: Capture Timer value to CC\\[n\\] register"] + #[doc = "Description collection: Capture Timer value to CC\\[n\\] register"] #[inline(always)] pub const fn tasks_capture(self, n: usize) -> crate::common::Reg { assert!(n < 6usize); unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x40usize + n * 4usize) as _) } } - #[doc = "Description collection\\[n\\]: Compare event on CC\\[n\\] match"] + #[doc = "Description collection: Compare event on CC\\[n\\] match"] #[inline(always)] pub const fn events_compare(self, n: usize) -> crate::common::Reg { assert!(n < 6usize); unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0140usize + n * 4usize) as _) } } - #[doc = "Shortcut register"] + #[doc = "Shortcuts between local events and tasks"] #[inline(always)] pub const fn shorts(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0200usize) as _) } @@ -21744,7 +27955,7 @@ pub mod timer3 { pub const fn prescaler(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0510usize) as _) } } - #[doc = "Description collection\\[n\\]: Capture/Compare register n"] + #[doc = "Description collection: Capture/Compare register n"] #[inline(always)] pub const fn cc(self, n: usize) -> crate::common::Reg { assert!(n < 6usize); @@ -21780,7 +27991,7 @@ pub mod timer3 { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Inten(pub u32); impl Inten { - #[doc = "Write '1' to disable interrupt for COMPARE\\[0\\] event"] + #[doc = "Write '1' to disable interrupt for event COMPARE\\[0\\]"] #[inline(always)] pub const fn compare(&self, n: usize) -> bool { assert!(n < 6usize); @@ -21788,7 +27999,7 @@ pub mod timer3 { let val = (self.0 >> offs) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for COMPARE\\[0\\] event"] + #[doc = "Write '1' to disable interrupt for event COMPARE\\[0\\]"] #[inline(always)] pub fn set_compare(&mut self, n: usize, val: bool) { assert!(n < 6usize); @@ -21848,12 +28059,12 @@ pub mod timer3 { Prescaler(0) } } - #[doc = "Shortcut register"] + #[doc = "Shortcuts between local events and tasks"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Shorts(pub u32); impl Shorts { - #[doc = "Shortcut between COMPARE\\[0\\] event and CLEAR task"] + #[doc = "Shortcut between event COMPARE\\[0\\] and task CLEAR"] #[inline(always)] pub const fn compare_clear(&self, n: usize) -> bool { assert!(n < 6usize); @@ -21861,14 +28072,14 @@ pub mod timer3 { let val = (self.0 >> offs) & 0x01; val != 0 } - #[doc = "Shortcut between COMPARE\\[0\\] event and CLEAR task"] + #[doc = "Shortcut between event COMPARE\\[0\\] and task CLEAR"] #[inline(always)] pub fn set_compare_clear(&mut self, n: usize, val: bool) { assert!(n < 6usize); let offs = 0usize + n * 1usize; self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); } - #[doc = "Shortcut between COMPARE\\[0\\] event and STOP task"] + #[doc = "Shortcut between event COMPARE\\[0\\] and task STOP"] #[inline(always)] pub const fn compare_stop(&self, n: usize) -> bool { assert!(n < 6usize); @@ -21876,7 +28087,7 @@ pub mod timer3 { let val = (self.0 >> offs) & 0x01; val != 0 } - #[doc = "Shortcut between COMPARE\\[0\\] event and STOP task"] + #[doc = "Shortcut between event COMPARE\\[0\\] and task STOP"] #[inline(always)] pub fn set_compare_stop(&mut self, n: usize, val: bool) { assert!(n < 6usize); @@ -22060,7 +28271,7 @@ pub mod twi { pub const fn events_suspended(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0148usize) as _) } } - #[doc = "Shortcut register"] + #[doc = "Shortcuts between local events and tasks"] #[inline(always)] pub const fn shorts(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0200usize) as _) } @@ -22090,7 +28301,7 @@ pub mod twi { pub const fn psel(self) -> Psel { unsafe { Psel::from_ptr(self.ptr.add(0x0508usize) as _) } } - #[doc = "RXD register"] + #[doc = "RXD register. Register is cleared on read and the buffer pointer will be modified if read."] #[inline(always)] pub const fn rxd(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0518usize) as _) } @@ -22232,68 +28443,68 @@ pub mod twi { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Inten(pub u32); impl Inten { - #[doc = "Write '1' to disable interrupt for STOPPED event"] + #[doc = "Write '1' to disable interrupt for event STOPPED"] #[inline(always)] pub const fn stopped(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for STOPPED event"] + #[doc = "Write '1' to disable interrupt for event STOPPED"] #[inline(always)] pub fn set_stopped(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } - #[doc = "Write '1' to disable interrupt for RXDREADY event"] + #[doc = "Write '1' to disable interrupt for event RXDREADY"] #[inline(always)] pub const fn rxdready(&self) -> bool { let val = (self.0 >> 2usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for RXDREADY event"] + #[doc = "Write '1' to disable interrupt for event RXDREADY"] #[inline(always)] pub fn set_rxdready(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); } - #[doc = "Write '1' to disable interrupt for TXDSENT event"] + #[doc = "Write '1' to disable interrupt for event TXDSENT"] #[inline(always)] pub const fn txdsent(&self) -> bool { let val = (self.0 >> 7usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for TXDSENT event"] + #[doc = "Write '1' to disable interrupt for event TXDSENT"] #[inline(always)] pub fn set_txdsent(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); } - #[doc = "Write '1' to disable interrupt for ERROR event"] + #[doc = "Write '1' to disable interrupt for event ERROR"] #[inline(always)] pub const fn error(&self) -> bool { let val = (self.0 >> 9usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for ERROR event"] + #[doc = "Write '1' to disable interrupt for event ERROR"] #[inline(always)] pub fn set_error(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); } - #[doc = "Write '1' to disable interrupt for BB event"] + #[doc = "Write '1' to disable interrupt for event BB"] #[inline(always)] pub const fn bb(&self) -> bool { let val = (self.0 >> 14usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for BB event"] + #[doc = "Write '1' to disable interrupt for event BB"] #[inline(always)] pub fn set_bb(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); } - #[doc = "Write '1' to disable interrupt for SUSPENDED event"] + #[doc = "Write '1' to disable interrupt for event SUSPENDED"] #[inline(always)] pub const fn suspended(&self) -> bool { let val = (self.0 >> 18usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for SUSPENDED event"] + #[doc = "Write '1' to disable interrupt for event SUSPENDED"] #[inline(always)] pub fn set_suspended(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); @@ -22305,7 +28516,7 @@ pub mod twi { Inten(0) } } - #[doc = "RXD register"] + #[doc = "RXD register. Register is cleared on read and the buffer pointer will be modified if read."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Rxd(pub u32); @@ -22328,29 +28539,29 @@ pub mod twi { Rxd(0) } } - #[doc = "Shortcut register"] + #[doc = "Shortcuts between local events and tasks"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Shorts(pub u32); impl Shorts { - #[doc = "Shortcut between BB event and SUSPEND task"] + #[doc = "Shortcut between event BB and task SUSPEND"] #[inline(always)] pub const fn bb_suspend(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Shortcut between BB event and SUSPEND task"] + #[doc = "Shortcut between event BB and task SUSPEND"] #[inline(always)] pub fn set_bb_suspend(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - #[doc = "Shortcut between BB event and STOP task"] + #[doc = "Shortcut between event BB and task STOP"] #[inline(always)] pub const fn bb_stop(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; val != 0 } - #[doc = "Shortcut between BB event and STOP task"] + #[doc = "Shortcut between event BB and task STOP"] #[inline(always)] pub fn set_bb_stop(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); @@ -22580,7 +28791,7 @@ pub mod twim { pub const fn events_error(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0124usize) as _) } } - #[doc = "Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended."] + #[doc = "SUSPEND task has been issued, TWI traffic is now suspended."] #[inline(always)] pub const fn events_suspended(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0148usize) as _) } @@ -22605,7 +28816,7 @@ pub mod twim { pub const fn events_lasttx(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0160usize) as _) } } - #[doc = "Shortcut register"] + #[doc = "Shortcuts between local events and tasks"] #[inline(always)] pub const fn shorts(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0200usize) as _) } @@ -22819,79 +29030,79 @@ pub mod twim { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Inten(pub u32); impl Inten { - #[doc = "Enable or disable interrupt for STOPPED event"] + #[doc = "Enable or disable interrupt for event STOPPED"] #[inline(always)] pub const fn stopped(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for STOPPED event"] + #[doc = "Enable or disable interrupt for event STOPPED"] #[inline(always)] pub fn set_stopped(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } - #[doc = "Enable or disable interrupt for ERROR event"] + #[doc = "Enable or disable interrupt for event ERROR"] #[inline(always)] pub const fn error(&self) -> bool { let val = (self.0 >> 9usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for ERROR event"] + #[doc = "Enable or disable interrupt for event ERROR"] #[inline(always)] pub fn set_error(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); } - #[doc = "Enable or disable interrupt for SUSPENDED event"] + #[doc = "Enable or disable interrupt for event SUSPENDED"] #[inline(always)] pub const fn suspended(&self) -> bool { let val = (self.0 >> 18usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for SUSPENDED event"] + #[doc = "Enable or disable interrupt for event SUSPENDED"] #[inline(always)] pub fn set_suspended(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); } - #[doc = "Enable or disable interrupt for RXSTARTED event"] + #[doc = "Enable or disable interrupt for event RXSTARTED"] #[inline(always)] pub const fn rxstarted(&self) -> bool { let val = (self.0 >> 19usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for RXSTARTED event"] + #[doc = "Enable or disable interrupt for event RXSTARTED"] #[inline(always)] pub fn set_rxstarted(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize); } - #[doc = "Enable or disable interrupt for TXSTARTED event"] + #[doc = "Enable or disable interrupt for event TXSTARTED"] #[inline(always)] pub const fn txstarted(&self) -> bool { let val = (self.0 >> 20usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for TXSTARTED event"] + #[doc = "Enable or disable interrupt for event TXSTARTED"] #[inline(always)] pub fn set_txstarted(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize); } - #[doc = "Enable or disable interrupt for LASTRX event"] + #[doc = "Enable or disable interrupt for event LASTRX"] #[inline(always)] pub const fn lastrx(&self) -> bool { let val = (self.0 >> 23usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for LASTRX event"] + #[doc = "Enable or disable interrupt for event LASTRX"] #[inline(always)] pub fn set_lastrx(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); } - #[doc = "Enable or disable interrupt for LASTTX event"] + #[doc = "Enable or disable interrupt for event LASTTX"] #[inline(always)] pub const fn lasttx(&self) -> bool { let val = (self.0 >> 24usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for LASTTX event"] + #[doc = "Enable or disable interrupt for event LASTTX"] #[inline(always)] pub fn set_lasttx(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); @@ -22972,73 +29183,73 @@ pub mod twim { RxdMaxcnt(0) } } - #[doc = "Shortcut register"] + #[doc = "Shortcuts between local events and tasks"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Shorts(pub u32); impl Shorts { - #[doc = "Shortcut between LASTTX event and STARTRX task"] + #[doc = "Shortcut between event LASTTX and task STARTRX"] #[inline(always)] pub const fn lasttx_startrx(&self) -> bool { let val = (self.0 >> 7usize) & 0x01; val != 0 } - #[doc = "Shortcut between LASTTX event and STARTRX task"] + #[doc = "Shortcut between event LASTTX and task STARTRX"] #[inline(always)] pub fn set_lasttx_startrx(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); } - #[doc = "Shortcut between LASTTX event and SUSPEND task"] + #[doc = "Shortcut between event LASTTX and task SUSPEND"] #[inline(always)] pub const fn lasttx_suspend(&self) -> bool { let val = (self.0 >> 8usize) & 0x01; val != 0 } - #[doc = "Shortcut between LASTTX event and SUSPEND task"] + #[doc = "Shortcut between event LASTTX and task SUSPEND"] #[inline(always)] pub fn set_lasttx_suspend(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); } - #[doc = "Shortcut between LASTTX event and STOP task"] + #[doc = "Shortcut between event LASTTX and task STOP"] #[inline(always)] pub const fn lasttx_stop(&self) -> bool { let val = (self.0 >> 9usize) & 0x01; val != 0 } - #[doc = "Shortcut between LASTTX event and STOP task"] + #[doc = "Shortcut between event LASTTX and task STOP"] #[inline(always)] pub fn set_lasttx_stop(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); } - #[doc = "Shortcut between LASTRX event and STARTTX task"] + #[doc = "Shortcut between event LASTRX and task STARTTX"] #[inline(always)] pub const fn lastrx_starttx(&self) -> bool { let val = (self.0 >> 10usize) & 0x01; val != 0 } - #[doc = "Shortcut between LASTRX event and STARTTX task"] + #[doc = "Shortcut between event LASTRX and task STARTTX"] #[inline(always)] pub fn set_lastrx_starttx(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); } - #[doc = "Shortcut between LASTRX event and SUSPEND task"] + #[doc = "Shortcut between event LASTRX and task SUSPEND"] #[inline(always)] pub const fn lastrx_suspend(&self) -> bool { let val = (self.0 >> 11usize) & 0x01; val != 0 } - #[doc = "Shortcut between LASTRX event and SUSPEND task"] + #[doc = "Shortcut between event LASTRX and task SUSPEND"] #[inline(always)] pub fn set_lastrx_suspend(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); } - #[doc = "Shortcut between LASTRX event and STOP task"] + #[doc = "Shortcut between event LASTRX and task STOP"] #[inline(always)] pub const fn lastrx_stop(&self) -> bool { let val = (self.0 >> 12usize) & 0x01; val != 0 } - #[doc = "Shortcut between LASTRX event and STOP task"] + #[doc = "Shortcut between event LASTRX and task STOP"] #[inline(always)] pub fn set_lastrx_stop(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); @@ -23329,6 +29540,11 @@ pub mod twis { pub const fn amount(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } + #[doc = "EasyDMA list type"] + #[inline(always)] + pub const fn list(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } + } } #[doc = "I2C compatible Two-Wire Slave Interface with EasyDMA 0"] #[derive(Copy, Clone, Eq, PartialEq)] @@ -23401,7 +29617,7 @@ pub mod twis { pub const fn events_read(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0168usize) as _) } } - #[doc = "Shortcut register"] + #[doc = "Shortcuts between local events and tasks"] #[inline(always)] pub const fn shorts(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0200usize) as _) } @@ -23451,7 +29667,7 @@ pub mod twis { pub const fn txd(self) -> Txd { unsafe { Txd::from_ptr(self.ptr.add(0x0544usize) as _) } } - #[doc = "Description collection\\[n\\]: TWI slave address n"] + #[doc = "Description collection: TWI slave address n"] #[inline(always)] pub const fn address( self, @@ -23502,9 +29718,14 @@ pub mod twis { pub const fn amount(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } + #[doc = "EasyDMA list type"] + #[inline(always)] + pub const fn list(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } + } } pub mod regs { - #[doc = "Description collection\\[n\\]: TWI slave address n"] + #[doc = "Description collection: TWI slave address n"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Address(pub u32); @@ -23634,68 +29855,68 @@ pub mod twis { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Inten(pub u32); impl Inten { - #[doc = "Enable or disable interrupt for STOPPED event"] + #[doc = "Enable or disable interrupt for event STOPPED"] #[inline(always)] pub const fn stopped(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for STOPPED event"] + #[doc = "Enable or disable interrupt for event STOPPED"] #[inline(always)] pub fn set_stopped(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } - #[doc = "Enable or disable interrupt for ERROR event"] + #[doc = "Enable or disable interrupt for event ERROR"] #[inline(always)] pub const fn error(&self) -> bool { let val = (self.0 >> 9usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for ERROR event"] + #[doc = "Enable or disable interrupt for event ERROR"] #[inline(always)] pub fn set_error(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); } - #[doc = "Enable or disable interrupt for RXSTARTED event"] + #[doc = "Enable or disable interrupt for event RXSTARTED"] #[inline(always)] pub const fn rxstarted(&self) -> bool { let val = (self.0 >> 19usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for RXSTARTED event"] + #[doc = "Enable or disable interrupt for event RXSTARTED"] #[inline(always)] pub fn set_rxstarted(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize); } - #[doc = "Enable or disable interrupt for TXSTARTED event"] + #[doc = "Enable or disable interrupt for event TXSTARTED"] #[inline(always)] pub const fn txstarted(&self) -> bool { let val = (self.0 >> 20usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for TXSTARTED event"] + #[doc = "Enable or disable interrupt for event TXSTARTED"] #[inline(always)] pub fn set_txstarted(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize); } - #[doc = "Enable or disable interrupt for WRITE event"] + #[doc = "Enable or disable interrupt for event WRITE"] #[inline(always)] pub const fn write(&self) -> bool { let val = (self.0 >> 25usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for WRITE event"] + #[doc = "Enable or disable interrupt for event WRITE"] #[inline(always)] pub fn set_write(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); } - #[doc = "Enable or disable interrupt for READ event"] + #[doc = "Enable or disable interrupt for event READ"] #[inline(always)] pub const fn read(&self) -> bool { let val = (self.0 >> 26usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for READ event"] + #[doc = "Enable or disable interrupt for event READ"] #[inline(always)] pub fn set_read(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); @@ -23712,13 +29933,13 @@ pub mod twis { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Match(pub u32); impl Match { - #[doc = "Which of the addresses in {ADDRESS} matched the incoming address"] + #[doc = "Indication of which address in ADDRESS that matched the incoming address"] #[inline(always)] pub const fn match_(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Which of the addresses in {ADDRESS} matched the incoming address"] + #[doc = "Indication of which address in ADDRESS that matched the incoming address"] #[inline(always)] pub fn set_match_(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); @@ -23776,6 +29997,29 @@ pub mod twis { RxdAmount(0) } } + #[doc = "EasyDMA list type"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct RxdList(pub u32); + impl RxdList { + #[doc = "List type"] + #[inline(always)] + pub const fn list(&self) -> super::vals::RxdListList { + let val = (self.0 >> 0usize) & 0x03; + super::vals::RxdListList::from_bits(val as u8) + } + #[doc = "List type"] + #[inline(always)] + pub fn set_list(&mut self, val: super::vals::RxdListList) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); + } + } + impl Default for RxdList { + #[inline(always)] + fn default() -> RxdList { + RxdList(0) + } + } #[doc = "Maximum number of bytes in RXD buffer"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -23799,29 +30043,29 @@ pub mod twis { RxdMaxcnt(0) } } - #[doc = "Shortcut register"] + #[doc = "Shortcuts between local events and tasks"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Shorts(pub u32); impl Shorts { - #[doc = "Shortcut between WRITE event and SUSPEND task"] + #[doc = "Shortcut between event WRITE and task SUSPEND"] #[inline(always)] pub const fn write_suspend(&self) -> bool { let val = (self.0 >> 13usize) & 0x01; val != 0 } - #[doc = "Shortcut between WRITE event and SUSPEND task"] + #[doc = "Shortcut between event WRITE and task SUSPEND"] #[inline(always)] pub fn set_write_suspend(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); } - #[doc = "Shortcut between READ event and SUSPEND task"] + #[doc = "Shortcut between event READ and task SUSPEND"] #[inline(always)] pub const fn read_suspend(&self) -> bool { let val = (self.0 >> 14usize) & 0x01; val != 0 } - #[doc = "Shortcut between READ event and SUSPEND task"] + #[doc = "Shortcut between event READ and task SUSPEND"] #[inline(always)] pub fn set_read_suspend(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); @@ -23856,6 +30100,29 @@ pub mod twis { TxdAmount(0) } } + #[doc = "EasyDMA list type"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct TxdList(pub u32); + impl TxdList { + #[doc = "List type"] + #[inline(always)] + pub const fn list(&self) -> super::vals::TxdListList { + let val = (self.0 >> 0usize) & 0x03; + super::vals::TxdListList::from_bits(val as u8) + } + #[doc = "List type"] + #[inline(always)] + pub fn set_list(&mut self, val: super::vals::TxdListList) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); + } + } + impl Default for TxdList { + #[inline(always)] + fn default() -> TxdList { + TxdList(0) + } + } #[doc = "Maximum number of bytes in TXD buffer"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -23925,6 +30192,70 @@ pub mod twis { Enable::to_bits(val) } } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum RxdListList { + #[doc = "Disable EasyDMA list"] + DISABLED = 0x0, + #[doc = "Use array list"] + ARRAY_LIST = 0x01, + _RESERVED_2 = 0x02, + _RESERVED_3 = 0x03, + } + impl RxdListList { + #[inline(always)] + pub const fn from_bits(val: u8) -> RxdListList { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for RxdListList { + #[inline(always)] + fn from(val: u8) -> RxdListList { + RxdListList::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: RxdListList) -> u8 { + RxdListList::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum TxdListList { + #[doc = "Disable EasyDMA list"] + DISABLED = 0x0, + #[doc = "Use array list"] + ARRAY_LIST = 0x01, + _RESERVED_2 = 0x02, + _RESERVED_3 = 0x03, + } + impl TxdListList { + #[inline(always)] + pub const fn from_bits(val: u8) -> TxdListList { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for TxdListList { + #[inline(always)] + fn from(val: u8) -> TxdListList { + TxdListList::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: TxdListList) -> u8 { + TxdListList::to_bits(val) + } + } } } pub mod uart { @@ -24036,7 +30367,7 @@ pub mod uart { pub const fn events_rxto(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0144usize) as _) } } - #[doc = "Shortcut register"] + #[doc = "Shortcuts between local events and tasks"] #[inline(always)] pub const fn shorts(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0200usize) as _) } @@ -24066,7 +30397,7 @@ pub mod uart { pub const fn psel(self) -> Psel { unsafe { Psel::from_ptr(self.ptr.add(0x0508usize) as _) } } - #[doc = "RXD register"] + #[doc = "RXD register. Register is cleared on read and the double buffered byte will be moved to RXD if it exists."] #[inline(always)] pub const fn rxd(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0518usize) as _) } @@ -24139,6 +30470,17 @@ pub mod uart { pub fn set_parity(&mut self, val: super::vals::ConfigParity) { self.0 = (self.0 & !(0x07 << 1usize)) | (((val.to_bits() as u32) & 0x07) << 1usize); } + #[doc = "Stop bits"] + #[inline(always)] + pub const fn stop(&self) -> super::vals::Stop { + let val = (self.0 >> 4usize) & 0x01; + super::vals::Stop::from_bits(val as u8) + } + #[doc = "Stop bits"] + #[inline(always)] + pub fn set_stop(&mut self, val: super::vals::Stop) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val.to_bits() as u32) & 0x01) << 4usize); + } } impl Default for Config { #[inline(always)] @@ -24230,68 +30572,68 @@ pub mod uart { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Inten(pub u32); impl Inten { - #[doc = "Write '1' to disable interrupt for CTS event"] + #[doc = "Write '1' to disable interrupt for event CTS"] #[inline(always)] pub const fn cts(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for CTS event"] + #[doc = "Write '1' to disable interrupt for event CTS"] #[inline(always)] pub fn set_cts(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - #[doc = "Write '1' to disable interrupt for NCTS event"] + #[doc = "Write '1' to disable interrupt for event NCTS"] #[inline(always)] pub const fn ncts(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for NCTS event"] + #[doc = "Write '1' to disable interrupt for event NCTS"] #[inline(always)] pub fn set_ncts(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } - #[doc = "Write '1' to disable interrupt for RXDRDY event"] + #[doc = "Write '1' to disable interrupt for event RXDRDY"] #[inline(always)] pub const fn rxdrdy(&self) -> bool { let val = (self.0 >> 2usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for RXDRDY event"] + #[doc = "Write '1' to disable interrupt for event RXDRDY"] #[inline(always)] pub fn set_rxdrdy(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); } - #[doc = "Write '1' to disable interrupt for TXDRDY event"] + #[doc = "Write '1' to disable interrupt for event TXDRDY"] #[inline(always)] pub const fn txdrdy(&self) -> bool { let val = (self.0 >> 7usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for TXDRDY event"] + #[doc = "Write '1' to disable interrupt for event TXDRDY"] #[inline(always)] pub fn set_txdrdy(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); } - #[doc = "Write '1' to disable interrupt for ERROR event"] + #[doc = "Write '1' to disable interrupt for event ERROR"] #[inline(always)] pub const fn error(&self) -> bool { let val = (self.0 >> 9usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for ERROR event"] + #[doc = "Write '1' to disable interrupt for event ERROR"] #[inline(always)] pub fn set_error(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); } - #[doc = "Write '1' to disable interrupt for RXTO event"] + #[doc = "Write '1' to disable interrupt for event RXTO"] #[inline(always)] pub const fn rxto(&self) -> bool { let val = (self.0 >> 17usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for RXTO event"] + #[doc = "Write '1' to disable interrupt for event RXTO"] #[inline(always)] pub fn set_rxto(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); @@ -24303,7 +30645,7 @@ pub mod uart { Inten(0) } } - #[doc = "RXD register"] + #[doc = "RXD register. Register is cleared on read and the double buffered byte will be moved to RXD if it exists."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Rxd(pub u32); @@ -24326,29 +30668,29 @@ pub mod uart { Rxd(0) } } - #[doc = "Shortcut register"] + #[doc = "Shortcuts between local events and tasks"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Shorts(pub u32); impl Shorts { - #[doc = "Shortcut between CTS event and STARTRX task"] + #[doc = "Shortcut between event CTS and task STARTRX"] #[inline(always)] pub const fn cts_startrx(&self) -> bool { let val = (self.0 >> 3usize) & 0x01; val != 0 } - #[doc = "Shortcut between CTS event and STARTRX task"] + #[doc = "Shortcut between event CTS and task STARTRX"] #[inline(always)] pub fn set_cts_startrx(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); } - #[doc = "Shortcut between NCTS event and STOPRX task"] + #[doc = "Shortcut between event NCTS and task STOPRX"] #[inline(always)] pub const fn ncts_stoprx(&self) -> bool { let val = (self.0 >> 4usize) & 0x01; val != 0 } - #[doc = "Shortcut between NCTS event and STOPRX task"] + #[doc = "Shortcut between event NCTS and task STOPRX"] #[inline(always)] pub fn set_ncts_stoprx(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); @@ -24526,6 +30868,36 @@ pub mod uart { Enable::to_bits(val) } } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum Stop { + #[doc = "One stop bit"] + ONE = 0x0, + #[doc = "Two stop bits"] + TWO = 0x01, + } + impl Stop { + #[inline(always)] + pub const fn from_bits(val: u8) -> Stop { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for Stop { + #[inline(always)] + fn from(val: u8) -> Stop { + Stop::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: Stop) -> u8 { + Stop::to_bits(val) + } + } } } pub mod uarte { @@ -24726,7 +31098,7 @@ pub mod uarte { pub const fn events_txstopped(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0158usize) as _) } } - #[doc = "Shortcut register"] + #[doc = "Shortcuts between local events and tasks"] #[inline(always)] pub const fn shorts(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0200usize) as _) } @@ -24746,7 +31118,7 @@ pub mod uarte { pub const fn intenclr(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0308usize) as _) } } - #[doc = "Error source Note : this register is read / write one to clear."] + #[doc = "Error source This register is read/write one to clear."] #[inline(always)] pub const fn errorsrc(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0480usize) as _) } @@ -24875,7 +31247,7 @@ pub mod uarte { Enable(0) } } - #[doc = "Error source Note : this register is read / write one to clear."] + #[doc = "Error source This register is read/write one to clear."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Errorsrc(pub u32); @@ -24936,123 +31308,123 @@ pub mod uarte { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Inten(pub u32); impl Inten { - #[doc = "Enable or disable interrupt for CTS event"] + #[doc = "Enable or disable interrupt for event CTS"] #[inline(always)] pub const fn cts(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for CTS event"] + #[doc = "Enable or disable interrupt for event CTS"] #[inline(always)] pub fn set_cts(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - #[doc = "Enable or disable interrupt for NCTS event"] + #[doc = "Enable or disable interrupt for event NCTS"] #[inline(always)] pub const fn ncts(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for NCTS event"] + #[doc = "Enable or disable interrupt for event NCTS"] #[inline(always)] pub fn set_ncts(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } - #[doc = "Enable or disable interrupt for RXDRDY event"] + #[doc = "Enable or disable interrupt for event RXDRDY"] #[inline(always)] pub const fn rxdrdy(&self) -> bool { let val = (self.0 >> 2usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for RXDRDY event"] + #[doc = "Enable or disable interrupt for event RXDRDY"] #[inline(always)] pub fn set_rxdrdy(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); } - #[doc = "Enable or disable interrupt for ENDRX event"] + #[doc = "Enable or disable interrupt for event ENDRX"] #[inline(always)] pub const fn endrx(&self) -> bool { let val = (self.0 >> 4usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for ENDRX event"] + #[doc = "Enable or disable interrupt for event ENDRX"] #[inline(always)] pub fn set_endrx(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); } - #[doc = "Enable or disable interrupt for TXDRDY event"] + #[doc = "Enable or disable interrupt for event TXDRDY"] #[inline(always)] pub const fn txdrdy(&self) -> bool { let val = (self.0 >> 7usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for TXDRDY event"] + #[doc = "Enable or disable interrupt for event TXDRDY"] #[inline(always)] pub fn set_txdrdy(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); } - #[doc = "Enable or disable interrupt for ENDTX event"] + #[doc = "Enable or disable interrupt for event ENDTX"] #[inline(always)] pub const fn endtx(&self) -> bool { let val = (self.0 >> 8usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for ENDTX event"] + #[doc = "Enable or disable interrupt for event ENDTX"] #[inline(always)] pub fn set_endtx(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); } - #[doc = "Enable or disable interrupt for ERROR event"] + #[doc = "Enable or disable interrupt for event ERROR"] #[inline(always)] pub const fn error(&self) -> bool { let val = (self.0 >> 9usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for ERROR event"] + #[doc = "Enable or disable interrupt for event ERROR"] #[inline(always)] pub fn set_error(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); } - #[doc = "Enable or disable interrupt for RXTO event"] + #[doc = "Enable or disable interrupt for event RXTO"] #[inline(always)] pub const fn rxto(&self) -> bool { let val = (self.0 >> 17usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for RXTO event"] + #[doc = "Enable or disable interrupt for event RXTO"] #[inline(always)] pub fn set_rxto(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); } - #[doc = "Enable or disable interrupt for RXSTARTED event"] + #[doc = "Enable or disable interrupt for event RXSTARTED"] #[inline(always)] pub const fn rxstarted(&self) -> bool { let val = (self.0 >> 19usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for RXSTARTED event"] + #[doc = "Enable or disable interrupt for event RXSTARTED"] #[inline(always)] pub fn set_rxstarted(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize); } - #[doc = "Enable or disable interrupt for TXSTARTED event"] + #[doc = "Enable or disable interrupt for event TXSTARTED"] #[inline(always)] pub const fn txstarted(&self) -> bool { let val = (self.0 >> 20usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for TXSTARTED event"] + #[doc = "Enable or disable interrupt for event TXSTARTED"] #[inline(always)] pub fn set_txstarted(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize); } - #[doc = "Enable or disable interrupt for TXSTOPPED event"] + #[doc = "Enable or disable interrupt for event TXSTOPPED"] #[inline(always)] pub const fn txstopped(&self) -> bool { let val = (self.0 >> 22usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for TXSTOPPED event"] + #[doc = "Enable or disable interrupt for event TXSTOPPED"] #[inline(always)] pub fn set_txstopped(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize); @@ -25110,29 +31482,29 @@ pub mod uarte { RxdMaxcnt(0) } } - #[doc = "Shortcut register"] + #[doc = "Shortcuts between local events and tasks"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Shorts(pub u32); impl Shorts { - #[doc = "Shortcut between ENDRX event and STARTRX task"] + #[doc = "Shortcut between event ENDRX and task STARTRX"] #[inline(always)] pub const fn endrx_startrx(&self) -> bool { let val = (self.0 >> 5usize) & 0x01; val != 0 } - #[doc = "Shortcut between ENDRX event and STARTRX task"] + #[doc = "Shortcut between event ENDRX and task STARTRX"] #[inline(always)] pub fn set_endrx_startrx(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); } - #[doc = "Shortcut between ENDRX event and STOPRX task"] + #[doc = "Shortcut between event ENDRX and task STOPRX"] #[inline(always)] pub const fn endrx_stoprx(&self) -> bool { let val = (self.0 >> 6usize) & 0x01; val != 0 } - #[doc = "Shortcut between ENDRX event and STOPRX task"] + #[doc = "Shortcut between event ENDRX and task STOPRX"] #[inline(always)] pub fn set_endrx_stoprx(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); @@ -25230,7 +31602,7 @@ pub mod uarte { pub const BAUD460800: Self = Self(0x0740_0000); #[doc = "921600 baud (actual rate: 941176)"] pub const BAUD921600: Self = Self(0x0f00_0000); - #[doc = "1Mega baud"] + #[doc = "1 megabaud"] pub const BAUD1M: Self = Self(0x1000_0000); } impl Baudrate { @@ -25382,45 +31754,25 @@ pub mod uicr { pub const fn as_ptr(&self) -> *mut () { self.ptr as _ } - #[doc = "Unspecified"] - #[inline(always)] - pub const fn unused0(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } - } - #[doc = "Unspecified"] - #[inline(always)] - pub const fn unused1(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } - } - #[doc = "Unspecified"] - #[inline(always)] - pub const fn unused2(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } - } - #[doc = "Unspecified"] - #[inline(always)] - pub const fn unused3(self) -> crate::common::Reg { - unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } - } - #[doc = "Description collection\\[n\\]: Reserved for Nordic firmware design"] + #[doc = "Description collection: Reserved for Nordic firmware design"] #[inline(always)] pub const fn nrffw(self, n: usize) -> crate::common::Reg { - assert!(n < 15usize); + assert!(n < 13usize); unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize + n * 4usize) as _) } } - #[doc = "Description collection\\[n\\]: Reserved for Nordic hardware design"] + #[doc = "Description collection: Reserved for Nordic hardware design"] #[inline(always)] pub const fn nrfhw(self, n: usize) -> crate::common::Reg { assert!(n < 12usize); unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x50usize + n * 4usize) as _) } } - #[doc = "Description collection\\[n\\]: Reserved for customer"] + #[doc = "Description collection: Reserved for customer"] #[inline(always)] pub const fn customer(self, n: usize) -> crate::common::Reg { assert!(n < 32usize); unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x80usize + n * 4usize) as _) } } - #[doc = "Description collection\\[n\\]: Mapping of the nRESET function"] + #[doc = "Description collection: Mapping of the nRESET function (see POWER chapter for details)"] #[inline(always)] pub const fn pselreset( self, @@ -25444,7 +31796,7 @@ pub mod uicr { pub const fn debugctrl(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0210usize) as _) } } - #[doc = "GPIO reference voltage / external output supply voltage in high voltage mode"] + #[doc = "Output voltage from REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - V_VDDH-VDD."] #[inline(always)] pub const fn regout0(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0304usize) as _) } @@ -25531,18 +31883,18 @@ pub mod uicr { Nfcpins(0) } } - #[doc = "GPIO reference voltage / external output supply voltage in high voltage mode"] + #[doc = "Output voltage from REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - V_VDDH-VDD."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Regout0(pub u32); impl Regout0 { - #[doc = "Output voltage from of REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - VEXDIF."] + #[doc = "Output voltage from REG0 regulator stage."] #[inline(always)] pub const fn vout(&self) -> super::vals::Vout { let val = (self.0 >> 0usize) & 0x07; super::vals::Vout::from_bits(val as u8) } - #[doc = "Output voltage from of REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - VEXDIF."] + #[doc = "Output voltage from REG0 regulator stage."] #[inline(always)] pub fn set_vout(&mut self, val: super::vals::Vout) { self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); @@ -25620,7 +31972,9 @@ pub mod uicr { impl Pall { #[doc = "Enable"] pub const ENABLED: Self = Self(0x0); - #[doc = "Disable"] + #[doc = "Hardware disable of access port protection for devices where access port protection is controlled by hardware and software"] + pub const HW_DISABLED: Self = Self(0x5a); + #[doc = "Hardware disable of access port protection for devices where access port protection is controlled by hardware"] pub const DISABLED: Self = Self(0xff); } impl Pall { @@ -25646,9 +32000,9 @@ pub mod uicr { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Protect { - #[doc = "Operation as GPIO pins. Same protection as normal GPIO pins"] + #[doc = "Operation as GPIO pins. Same protection as normal GPIO pins."] DISABLED = 0x0, - #[doc = "Operation as NFC antenna pins. Configures the protection for NFC operation"] + #[doc = "Operation as NFC antenna pins. Configures the protection for NFC operation."] NFC = 0x01, } impl Protect { @@ -25733,17 +32087,17 @@ pub mod usbd { pub const fn as_ptr(&self) -> *mut () { self.ptr as _ } - #[doc = "Description cluster\\[n\\]: Data pointer"] + #[doc = "Description cluster: Data pointer"] #[inline(always)] pub const fn ptr(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } - #[doc = "Description cluster\\[n\\]: Maximum number of bytes to transfer"] + #[doc = "Description cluster: Maximum number of bytes to transfer"] #[inline(always)] pub const fn maxcnt(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } - #[doc = "Description cluster\\[n\\]: Number of bytes transferred in the last transaction"] + #[doc = "Description cluster: Number of bytes transferred in the last transaction"] #[inline(always)] pub const fn amount(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } @@ -25765,17 +32119,17 @@ pub mod usbd { pub const fn as_ptr(&self) -> *mut () { self.ptr as _ } - #[doc = "Description cluster\\[n\\]: Data pointer"] + #[doc = "Description cluster: Data pointer"] #[inline(always)] pub const fn ptr(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } - #[doc = "Description cluster\\[n\\]: Maximum number of bytes to transfer"] + #[doc = "Description cluster: Maximum number of bytes to transfer"] #[inline(always)] pub const fn maxcnt(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } - #[doc = "Description cluster\\[n\\]: Number of bytes transferred in the last transaction"] + #[doc = "Description cluster: Number of bytes transferred in the last transaction"] #[inline(always)] pub const fn amount(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } @@ -25797,13 +32151,13 @@ pub mod usbd { pub const fn as_ptr(&self) -> *mut () { self.ptr as _ } - #[doc = "Description collection\\[n\\]: IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint."] + #[doc = "Description collection: IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint."] #[inline(always)] pub const fn epin(self, n: usize) -> crate::common::Reg { assert!(n < 8usize); unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize + n * 4usize) as _) } } - #[doc = "Description collection\\[n\\]: OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint."] + #[doc = "Description collection: OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint."] #[inline(always)] pub const fn epout( self, @@ -25893,7 +32247,7 @@ pub mod usbd { pub const fn as_ptr(&self) -> *mut () { self.ptr as _ } - #[doc = "Description collection\\[n\\]: Number of bytes received last in the data stage of this OUT endpoint"] + #[doc = "Description collection: Number of bytes received last in the data stage of this OUT endpoint"] #[inline(always)] pub const fn epout( self, @@ -25924,7 +32278,7 @@ pub mod usbd { pub const fn as_ptr(&self) -> *mut () { self.ptr as _ } - #[doc = "Description collection\\[n\\]: Captures the EPIN\\[n\\].PTR and EPIN\\[n\\].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host"] + #[doc = "Description collection: Captures the EPIN\\[n\\].PTR and EPIN\\[n\\].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host"] #[inline(always)] pub const fn tasks_startepin(self, n: usize) -> crate::common::Reg { assert!(n < 8usize); @@ -25935,7 +32289,7 @@ pub mod usbd { pub const fn tasks_startisoin(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) } } - #[doc = "Description collection\\[n\\]: Captures the EPOUT\\[n\\].PTR and EPOUT\\[n\\].MAXCNT registers values, and enables endpoint n to respond to traffic from host"] + #[doc = "Description collection: Captures the EPOUT\\[n\\].PTR and EPOUT\\[n\\].MAXCNT registers values, and enables endpoint n to respond to traffic from host"] #[inline(always)] pub const fn tasks_startepout(self, n: usize) -> crate::common::Reg { assert!(n < 8usize); @@ -25981,7 +32335,7 @@ pub mod usbd { pub const fn events_started(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0104usize) as _) } } - #[doc = "Description collection\\[n\\]: The whole EPIN\\[n\\] buffer has been consumed. The RAM buffer can be accessed safely by software."] + #[doc = "Description collection: The whole EPIN\\[n\\] buffer has been consumed. The buffer can be accessed safely by software."] #[inline(always)] pub const fn events_endepin(self, n: usize) -> crate::common::Reg { assert!(n < 8usize); @@ -25992,18 +32346,18 @@ pub mod usbd { pub const fn events_ep0datadone(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0128usize) as _) } } - #[doc = "The whole ISOIN buffer has been consumed. The RAM buffer can be accessed safely by software."] + #[doc = "The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software."] #[inline(always)] pub const fn events_endisoin(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x012cusize) as _) } } - #[doc = "Description collection\\[n\\]: The whole EPOUT\\[n\\] buffer has been consumed. The RAM buffer can be accessed safely by software."] + #[doc = "Description collection: The whole EPOUT\\[n\\] buffer has been consumed. The buffer can be accessed safely by software."] #[inline(always)] pub const fn events_endepout(self, n: usize) -> crate::common::Reg { assert!(n < 8usize); unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0130usize + n * 4usize) as _) } } - #[doc = "The whole ISOOUT buffer has been consumed. The RAM buffer can be accessed safely by software."] + #[doc = "The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software."] #[inline(always)] pub const fn events_endisoout(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0150usize) as _) } @@ -26028,7 +32382,7 @@ pub mod usbd { pub const fn events_epdata(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0160usize) as _) } } - #[doc = "Shortcut register"] + #[doc = "Shortcuts between local events and tasks"] #[inline(always)] pub const fn shorts(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0200usize) as _) } @@ -26402,7 +32756,7 @@ pub mod usbd { Epdatastatus(0) } } - #[doc = "Description collection\\[n\\]: IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint."] + #[doc = "Description collection: IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Epin(pub u32); @@ -26426,7 +32780,7 @@ pub mod usbd { Epin(0) } } - #[doc = "Description cluster\\[n\\]: Number of bytes transferred in the last transaction"] + #[doc = "Description cluster: Number of bytes transferred in the last transaction"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct EpinAmount(pub u32); @@ -26449,7 +32803,7 @@ pub mod usbd { EpinAmount(0) } } - #[doc = "Description cluster\\[n\\]: Maximum number of bytes to transfer"] + #[doc = "Description cluster: Maximum number of bytes to transfer"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct EpinMaxcnt(pub u32); @@ -26510,7 +32864,7 @@ pub mod usbd { Epinen(0) } } - #[doc = "Description cluster\\[n\\]: Number of bytes transferred in the last transaction"] + #[doc = "Description cluster: Number of bytes transferred in the last transaction"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct EpoutAmount(pub u32); @@ -26533,7 +32887,7 @@ pub mod usbd { EpoutAmount(0) } } - #[doc = "Description cluster\\[n\\]: Maximum number of bytes to transfer"] + #[doc = "Description cluster: Maximum number of bytes to transfer"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct EpoutMaxcnt(pub u32); @@ -26771,7 +33125,7 @@ pub mod usbd { Framecntr(0) } } - #[doc = "Description collection\\[n\\]: OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint."] + #[doc = "Description collection: OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct HaltedEpout(pub u32); @@ -26800,29 +33154,29 @@ pub mod usbd { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Inten(pub u32); impl Inten { - #[doc = "Enable or disable interrupt for USBRESET event"] + #[doc = "Enable or disable interrupt for event USBRESET"] #[inline(always)] pub const fn usbreset(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for USBRESET event"] + #[doc = "Enable or disable interrupt for event USBRESET"] #[inline(always)] pub fn set_usbreset(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - #[doc = "Enable or disable interrupt for STARTED event"] + #[doc = "Enable or disable interrupt for event STARTED"] #[inline(always)] pub const fn started(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for STARTED event"] + #[doc = "Enable or disable interrupt for event STARTED"] #[inline(always)] pub fn set_started(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } - #[doc = "Enable or disable interrupt for ENDEPIN\\[0\\] event"] + #[doc = "Enable or disable interrupt for event ENDEPIN\\[0\\]"] #[inline(always)] pub const fn endepin(&self, n: usize) -> bool { assert!(n < 8usize); @@ -26830,36 +33184,36 @@ pub mod usbd { let val = (self.0 >> offs) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for ENDEPIN\\[0\\] event"] + #[doc = "Enable or disable interrupt for event ENDEPIN\\[0\\]"] #[inline(always)] pub fn set_endepin(&mut self, n: usize, val: bool) { assert!(n < 8usize); let offs = 2usize + n * 1usize; self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); } - #[doc = "Enable or disable interrupt for EP0DATADONE event"] + #[doc = "Enable or disable interrupt for event EP0DATADONE"] #[inline(always)] pub const fn ep0datadone(&self) -> bool { let val = (self.0 >> 10usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for EP0DATADONE event"] + #[doc = "Enable or disable interrupt for event EP0DATADONE"] #[inline(always)] pub fn set_ep0datadone(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); } - #[doc = "Enable or disable interrupt for ENDISOIN event"] + #[doc = "Enable or disable interrupt for event ENDISOIN"] #[inline(always)] pub const fn endisoin(&self) -> bool { let val = (self.0 >> 11usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for ENDISOIN event"] + #[doc = "Enable or disable interrupt for event ENDISOIN"] #[inline(always)] pub fn set_endisoin(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); } - #[doc = "Enable or disable interrupt for ENDEPOUT\\[0\\] event"] + #[doc = "Enable or disable interrupt for event ENDEPOUT\\[0\\]"] #[inline(always)] pub const fn endepout(&self, n: usize) -> bool { assert!(n < 8usize); @@ -26867,64 +33221,64 @@ pub mod usbd { let val = (self.0 >> offs) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for ENDEPOUT\\[0\\] event"] + #[doc = "Enable or disable interrupt for event ENDEPOUT\\[0\\]"] #[inline(always)] pub fn set_endepout(&mut self, n: usize, val: bool) { assert!(n < 8usize); let offs = 12usize + n * 1usize; self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); } - #[doc = "Enable or disable interrupt for ENDISOOUT event"] + #[doc = "Enable or disable interrupt for event ENDISOOUT"] #[inline(always)] pub const fn endisoout(&self) -> bool { let val = (self.0 >> 20usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for ENDISOOUT event"] + #[doc = "Enable or disable interrupt for event ENDISOOUT"] #[inline(always)] pub fn set_endisoout(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize); } - #[doc = "Enable or disable interrupt for SOF event"] + #[doc = "Enable or disable interrupt for event SOF"] #[inline(always)] pub const fn sof(&self) -> bool { let val = (self.0 >> 21usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for SOF event"] + #[doc = "Enable or disable interrupt for event SOF"] #[inline(always)] pub fn set_sof(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize); } - #[doc = "Enable or disable interrupt for USBEVENT event"] + #[doc = "Enable or disable interrupt for event USBEVENT"] #[inline(always)] pub const fn usbevent(&self) -> bool { let val = (self.0 >> 22usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for USBEVENT event"] + #[doc = "Enable or disable interrupt for event USBEVENT"] #[inline(always)] pub fn set_usbevent(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize); } - #[doc = "Enable or disable interrupt for EP0SETUP event"] + #[doc = "Enable or disable interrupt for event EP0SETUP"] #[inline(always)] pub const fn ep0setup(&self) -> bool { let val = (self.0 >> 23usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for EP0SETUP event"] + #[doc = "Enable or disable interrupt for event EP0SETUP"] #[inline(always)] pub fn set_ep0setup(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); } - #[doc = "Enable or disable interrupt for EPDATA event"] + #[doc = "Enable or disable interrupt for event EPDATA"] #[inline(always)] pub const fn epdata(&self) -> bool { let val = (self.0 >> 24usize) & 0x01; val != 0 } - #[doc = "Enable or disable interrupt for EPDATA event"] + #[doc = "Enable or disable interrupt for event EPDATA"] #[inline(always)] pub fn set_epdata(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); @@ -27133,62 +33487,62 @@ pub mod usbd { Lowpower(0) } } - #[doc = "Shortcut register"] + #[doc = "Shortcuts between local events and tasks"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Shorts(pub u32); impl Shorts { - #[doc = "Shortcut between EP0DATADONE event and STARTEPIN\\[0\\] task"] + #[doc = "Shortcut between event EP0DATADONE and task STARTEPIN\\[0\\]"] #[inline(always)] pub const fn ep0datadone_startepin0(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Shortcut between EP0DATADONE event and STARTEPIN\\[0\\] task"] + #[doc = "Shortcut between event EP0DATADONE and task STARTEPIN\\[0\\]"] #[inline(always)] pub fn set_ep0datadone_startepin0(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - #[doc = "Shortcut between EP0DATADONE event and STARTEPOUT\\[0\\] task"] + #[doc = "Shortcut between event EP0DATADONE and task STARTEPOUT\\[0\\]"] #[inline(always)] pub const fn ep0datadone_startepout0(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; val != 0 } - #[doc = "Shortcut between EP0DATADONE event and STARTEPOUT\\[0\\] task"] + #[doc = "Shortcut between event EP0DATADONE and task STARTEPOUT\\[0\\]"] #[inline(always)] pub fn set_ep0datadone_startepout0(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } - #[doc = "Shortcut between EP0DATADONE event and EP0STATUS task"] + #[doc = "Shortcut between event EP0DATADONE and task EP0STATUS"] #[inline(always)] pub const fn ep0datadone_ep0status(&self) -> bool { let val = (self.0 >> 2usize) & 0x01; val != 0 } - #[doc = "Shortcut between EP0DATADONE event and EP0STATUS task"] + #[doc = "Shortcut between event EP0DATADONE and task EP0STATUS"] #[inline(always)] pub fn set_ep0datadone_ep0status(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); } - #[doc = "Shortcut between ENDEPOUT\\[0\\] event and EP0STATUS task"] + #[doc = "Shortcut between event ENDEPOUT\\[0\\] and task EP0STATUS"] #[inline(always)] pub const fn endepout0_ep0status(&self) -> bool { let val = (self.0 >> 3usize) & 0x01; val != 0 } - #[doc = "Shortcut between ENDEPOUT\\[0\\] event and EP0STATUS task"] + #[doc = "Shortcut between event ENDEPOUT\\[0\\] and task EP0STATUS"] #[inline(always)] pub fn set_endepout0_ep0status(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); } - #[doc = "Shortcut between ENDEPOUT\\[0\\] event and EP0RCVOUT task"] + #[doc = "Shortcut between event ENDEPOUT\\[0\\] and task EP0RCVOUT"] #[inline(always)] pub const fn endepout0_ep0rcvout(&self) -> bool { let val = (self.0 >> 4usize) & 0x01; val != 0 } - #[doc = "Shortcut between ENDEPOUT\\[0\\] event and EP0RCVOUT task"] + #[doc = "Shortcut between event ENDEPOUT\\[0\\] and task EP0RCVOUT"] #[inline(always)] pub fn set_endepout0_ep0rcvout(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); @@ -27200,7 +33554,7 @@ pub mod usbd { Shorts(0) } } - #[doc = "Description collection\\[n\\]: Number of bytes received last in the data stage of this OUT endpoint"] + #[doc = "Description collection: Number of bytes received last in the data stage of this OUT endpoint"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct SizeEpout(pub u32); @@ -27858,7 +34212,7 @@ pub mod usbd { #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub struct Split(pub u16); impl Split { - #[doc = "Full buffer dedicated to either iso IN or OUT"] + #[doc = "Full buffer dedicated to either ISO IN or OUT"] pub const ONE_DIR: Self = Self(0x0); #[doc = "Lower half for IN, upper half for OUT"] pub const HALF_IN: Self = Self(0x80); @@ -28074,7 +34428,7 @@ pub mod wdt { pub const fn config(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x050cusize) as _) } } - #[doc = "Description collection\\[n\\]: Reload request n"] + #[doc = "Description collection: Reload request n"] #[inline(always)] pub const fn rr(self, n: usize) -> crate::common::Reg { assert!(n < 8usize); @@ -28121,13 +34475,13 @@ pub mod wdt { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Inten(pub u32); impl Inten { - #[doc = "Write '1' to disable interrupt for TIMEOUT event"] + #[doc = "Write '1' to disable interrupt for event TIMEOUT"] #[inline(always)] pub const fn timeout(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Write '1' to disable interrupt for TIMEOUT event"] + #[doc = "Write '1' to disable interrupt for event TIMEOUT"] #[inline(always)] pub fn set_timeout(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); @@ -28166,7 +34520,7 @@ pub mod wdt { Reqstatus(0) } } - #[doc = "Description collection\\[n\\]: Reload request n"] + #[doc = "Description collection: Reload request n"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Rr(pub u32); diff --git a/src/chips/nrf5340-app/pac.rs b/src/chips/nrf5340-app/pac.rs index 267622b..d336be1 100644 --- a/src/chips/nrf5340-app/pac.rs +++ b/src/chips/nrf5340-app/pac.rs @@ -1,4 +1,4 @@ -#![doc = "Peripheral access API (generated using chiptool v0.1.0 (218daa7 2024-01-15))"] +#![doc = "Peripheral access API (generated using chiptool v0.1.0 (4df74f6 2024-11-11))"] #[derive(Copy, Clone, Debug, PartialEq, Eq)] pub enum Interrupt { #[doc = "0 - FPU"] @@ -6769,7 +6769,7 @@ pub mod ficr_s { } #[doc = "Description cluster: Address of the PAR register which will be written"] #[inline(always)] - pub const fn addr(self) -> crate::common::Reg { + pub const fn addr(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "Description cluster: Data"] @@ -7437,6 +7437,8 @@ pub mod ficr_s { impl Package { #[doc = "QKxx - 94-pin aQFN"] pub const QK: Self = Self(0x2000); + #[doc = "CLxx - WLCSP"] + pub const CL: Self = Self(0x2005); #[doc = "Unspecified"] pub const UNSPECIFIED: Self = Self(0xffff_ffff); } @@ -7532,6 +7534,8 @@ pub mod ficr_s { #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub struct Variant(pub u32); impl Variant { + #[doc = "CLAA"] + pub const CLAA: Self = Self(0x434c_4141); #[doc = "QKAA"] pub const QKAA: Self = Self(0x514b_4141); #[doc = "Unspecified"] @@ -17052,24 +17056,24 @@ pub mod qspi_ns { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Dpmdur(pub u32); impl Dpmdur { - #[doc = "Duration needed by external flash to enter DPM. Duration is given as ENTER * 256 * 62.5 ns."] + #[doc = "Duration needed by external flash to enter DPM. Duration is given as ENTER * 256 * 31.25 ns"] #[inline(always)] pub const fn enter(&self) -> u16 { let val = (self.0 >> 0usize) & 0xffff; val as u16 } - #[doc = "Duration needed by external flash to enter DPM. Duration is given as ENTER * 256 * 62.5 ns."] + #[doc = "Duration needed by external flash to enter DPM. Duration is given as ENTER * 256 * 31.25 ns"] #[inline(always)] pub fn set_enter(&mut self, val: u16) { self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); } - #[doc = "Duration needed by external flash to exit DPM. Duration is given as EXIT * 256 * 62.5 ns."] + #[doc = "Duration needed by external flash to exit DPM. Duration is given as EXIT * 256 * 31.25 ns."] #[inline(always)] pub const fn exit(&self) -> u16 { let val = (self.0 >> 16usize) & 0xffff; val as u16 } - #[doc = "Duration needed by external flash to exit DPM. Duration is given as EXIT * 256 * 62.5 ns."] + #[doc = "Duration needed by external flash to exit DPM. Duration is given as EXIT * 256 * 31.25 ns."] #[inline(always)] pub fn set_exit(&mut self, val: u16) { self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize); @@ -17154,13 +17158,13 @@ pub mod qspi_ns { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Ifconfig1(pub u32); impl Ifconfig1 { - #[doc = "Minimum amount of time that the CSN pin must stay high before it can go low again. Value is specified in number of 16 MHz periods (62.5 ns)."] + #[doc = "Minimum amount of time that the CSN pin must stay high before it can go low again. Value is specified in number of 32 MHz periods (31.25 ns)."] #[inline(always)] pub const fn sckdelay(&self) -> u8 { let val = (self.0 >> 0usize) & 0xff; val as u8 } - #[doc = "Minimum amount of time that the CSN pin must stay high before it can go low again. Value is specified in number of 16 MHz periods (62.5 ns)."] + #[doc = "Minimum amount of time that the CSN pin must stay high before it can go low again. Value is specified in number of 32 MHz periods (31.25 ns)."] #[inline(always)] pub fn set_sckdelay(&mut self, val: u8) { self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); @@ -20494,7 +20498,7 @@ pub mod spim_ns { pub const fn rxdelay(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } - #[doc = "Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions"] + #[doc = "Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, this is also the minimum duration CSN must stay high between transactions."] #[inline(always)] pub const fn csndur(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } @@ -20863,18 +20867,18 @@ pub mod spim_ns { Config(0) } } - #[doc = "Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions"] + #[doc = "Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, this is also the minimum duration CSN must stay high between transactions."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Csndur(pub u32); impl Csndur { - #[doc = "Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns)."] + #[doc = "Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, this is the minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns)."] #[inline(always)] pub const fn csndur(&self) -> u8 { let val = (self.0 >> 0usize) & 0xff; val as u8 } - #[doc = "Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns)."] + #[doc = "Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, this is the minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns)."] #[inline(always)] pub fn set_csndur(&mut self, val: u8) { self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); diff --git a/src/chips/nrf5340-net/pac.rs b/src/chips/nrf5340-net/pac.rs index b9e4fab..3f08053 100644 --- a/src/chips/nrf5340-net/pac.rs +++ b/src/chips/nrf5340-net/pac.rs @@ -1,4 +1,4 @@ -#![doc = "Peripheral access API (generated using chiptool v0.1.0 (218daa7 2024-01-15))"] +#![doc = "Peripheral access API (generated using chiptool v0.1.0 (4df74f6 2024-11-11))"] #[derive(Copy, Clone, Debug, PartialEq, Eq)] pub enum Interrupt { #[doc = "5 - CLOCK_POWER"] @@ -4505,7 +4505,7 @@ pub mod dppic_ns { #[doc = "Enable or disable channel 0"] #[inline(always)] pub const fn ch(&self, n: usize) -> bool { - assert!(n < 16usize); + assert!(n < 32usize); let offs = 0usize + n * 1usize; let val = (self.0 >> offs) & 0x01; val != 0 @@ -4513,7 +4513,7 @@ pub mod dppic_ns { #[doc = "Enable or disable channel 0"] #[inline(always)] pub fn set_ch(&mut self, n: usize, val: bool) { - assert!(n < 16usize); + assert!(n < 32usize); let offs = 0usize + n * 1usize; self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); } @@ -4532,7 +4532,7 @@ pub mod dppic_ns { #[doc = "Include or exclude channel 0"] #[inline(always)] pub const fn ch(&self, n: usize) -> bool { - assert!(n < 16usize); + assert!(n < 32usize); let offs = 0usize + n * 1usize; let val = (self.0 >> offs) & 0x01; val != 0 @@ -4540,7 +4540,7 @@ pub mod dppic_ns { #[doc = "Include or exclude channel 0"] #[inline(always)] pub fn set_ch(&mut self, n: usize, val: bool) { - assert!(n < 16usize); + assert!(n < 32usize); let offs = 0usize + n * 1usize; self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); } @@ -4909,7 +4909,7 @@ pub mod ficr_ns { } #[doc = "Description cluster: Address"] #[inline(always)] - pub const fn addr(self) -> crate::common::Reg { + pub const fn addr(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "Description cluster: Data"] @@ -5315,6 +5315,8 @@ pub mod ficr_ns { impl Package { #[doc = "QKxx - 94-pin aQFN"] pub const QK: Self = Self(0x2000); + #[doc = "CLxx - WLCSP"] + pub const CL: Self = Self(0x2005); #[doc = "Unspecified"] pub const UNSPECIFIED: Self = Self(0xffff_ffff); } @@ -5410,6 +5412,8 @@ pub mod ficr_ns { #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub struct Variant(pub u32); impl Variant { + #[doc = "CLAA"] + pub const CLAA: Self = Self(0x434c_4141); #[doc = "QKAA"] pub const QKAA: Self = Self(0x514b_4141); #[doc = "Unspecified"] @@ -13127,7 +13131,7 @@ pub mod spim_ns { pub const fn rxdelay(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } - #[doc = "Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions"] + #[doc = "Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, this is also the minimum duration CSN must stay high between transactions."] #[inline(always)] pub const fn csndur(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } @@ -13496,18 +13500,18 @@ pub mod spim_ns { Config(0) } } - #[doc = "Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions"] + #[doc = "Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, this is also the minimum duration CSN must stay high between transactions."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Csndur(pub u32); impl Csndur { - #[doc = "Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns)."] + #[doc = "Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, this is the minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns)."] #[inline(always)] pub const fn csndur(&self) -> u8 { let val = (self.0 >> 0usize) & 0xff; val as u8 } - #[doc = "Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns)."] + #[doc = "Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, this is the minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns)."] #[inline(always)] pub fn set_csndur(&mut self, val: u8) { self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); diff --git a/src/chips/nrf9120/pac.rs b/src/chips/nrf9120/pac.rs index edd1e01..38893f8 100644 --- a/src/chips/nrf9120/pac.rs +++ b/src/chips/nrf9120/pac.rs @@ -1,4 +1,4 @@ -#![doc = "Peripheral access API (generated using chiptool v0.1.0 (218daa7 2024-01-15))"] +#![doc = "Peripheral access API (generated using chiptool v0.1.0 (4df74f6 2024-11-11))"] #[derive(Copy, Clone, Debug, PartialEq, Eq)] pub enum Interrupt { #[doc = "3 - SPU"] diff --git a/src/chips/nrf9160/pac.rs b/src/chips/nrf9160/pac.rs index 154f2cd..20f336d 100644 --- a/src/chips/nrf9160/pac.rs +++ b/src/chips/nrf9160/pac.rs @@ -1,18 +1,18 @@ -#![doc = "Peripheral access API (generated using chiptool v0.1.0 (218daa7 2024-01-15))"] +#![doc = "Peripheral access API (generated using chiptool v0.1.0 (4df74f6 2024-11-11))"] #[derive(Copy, Clone, Debug, PartialEq, Eq)] pub enum Interrupt { #[doc = "3 - SPU"] SPU = 3, #[doc = "5 - CLOCK_POWER"] CLOCK_POWER = 5, - #[doc = "8 - UARTE0_SPIM0_SPIS0_TWIM0_TWIS0"] - UARTE0_SPIM0_SPIS0_TWIM0_TWIS0 = 8, - #[doc = "9 - UARTE1_SPIM1_SPIS1_TWIM1_TWIS1"] - UARTE1_SPIM1_SPIS1_TWIM1_TWIS1 = 9, - #[doc = "10 - UARTE2_SPIM2_SPIS2_TWIM2_TWIS2"] - UARTE2_SPIM2_SPIS2_TWIM2_TWIS2 = 10, - #[doc = "11 - UARTE3_SPIM3_SPIS3_TWIM3_TWIS3"] - UARTE3_SPIM3_SPIS3_TWIM3_TWIS3 = 11, + #[doc = "8 - SPIM0_SPIS0_TWIM0_TWIS0_UARTE0"] + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 = 8, + #[doc = "9 - SPIM1_SPIS1_TWIM1_TWIS1_UARTE1"] + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 = 9, + #[doc = "10 - SPIM2_SPIS2_TWIM2_TWIS2_UARTE2"] + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 = 10, + #[doc = "11 - SPIM3_SPIS3_TWIM3_TWIS3_UARTE3"] + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 = 11, #[doc = "13 - GPIOTE0"] GPIOTE0 = 13, #[doc = "14 - SAADC"] @@ -75,10 +75,10 @@ mod _vectors { extern "C" { fn SPU(); fn CLOCK_POWER(); - fn UARTE0_SPIM0_SPIS0_TWIM0_TWIS0(); - fn UARTE1_SPIM1_SPIS1_TWIM1_TWIS1(); - fn UARTE2_SPIM2_SPIS2_TWIM2_TWIS2(); - fn UARTE3_SPIM3_SPIS3_TWIM3_TWIS3(); + fn SPIM0_SPIS0_TWIM0_TWIS0_UARTE0(); + fn SPIM1_SPIS1_TWIM1_TWIS1_UARTE1(); + fn SPIM2_SPIS2_TWIM2_TWIS2_UARTE2(); + fn SPIM3_SPIS3_TWIM3_TWIS3_UARTE3(); fn GPIOTE0(); fn SAADC(); fn TIMER0(); @@ -123,16 +123,16 @@ mod _vectors { Vector { _reserved: 0 }, Vector { _reserved: 0 }, Vector { - _handler: UARTE0_SPIM0_SPIS0_TWIM0_TWIS0, + _handler: SPIM0_SPIS0_TWIM0_TWIS0_UARTE0, }, Vector { - _handler: UARTE1_SPIM1_SPIS1_TWIM1_TWIS1, + _handler: SPIM1_SPIS1_TWIM1_TWIS1_UARTE1, }, Vector { - _handler: UARTE2_SPIM2_SPIS2_TWIM2_TWIS2, + _handler: SPIM2_SPIS2_TWIM2_TWIS2_UARTE2, }, Vector { - _handler: UARTE3_SPIM3_SPIS3_TWIM3_TWIS3, + _handler: SPIM3_SPIS3_TWIM3_TWIS3_UARTE3, }, Vector { _reserved: 0 }, Vector { _handler: GPIOTE0 }, @@ -254,7 +254,7 @@ pub const TIMER2_NS: timer_ns::Timer = unsafe { timer_ns::Timer::from_ptr(0x4001 pub const RTC0_NS: rtc_ns::Rtc = unsafe { rtc_ns::Rtc::from_ptr(0x4001_4000usize as _) }; #[doc = "Real-time counter 2"] pub const RTC1_NS: rtc_ns::Rtc = unsafe { rtc_ns::Rtc::from_ptr(0x4001_5000usize as _) }; -#[doc = "Distributed Programmable Peripheral Interconnect Controller 0"] +#[doc = "Distributed programmable peripheral interconnect controller 0"] pub const DPPIC_NS: dppic_ns::Dppic = unsafe { dppic_ns::Dppic::from_ptr(0x4001_7000usize as _) }; #[doc = "Watchdog Timer 0"] pub const WDT_NS: wdt_ns::Wdt = unsafe { wdt_ns::Wdt::from_ptr(0x4001_8000usize as _) }; @@ -282,7 +282,7 @@ pub const PWM3_NS: pwm_ns::Pwm = unsafe { pwm_ns::Pwm::from_ptr(0x4002_4000usize pub const PDM_NS: pdm_ns::Pdm = unsafe { pdm_ns::Pdm::from_ptr(0x4002_6000usize as _) }; #[doc = "Inter-IC Sound 0"] pub const I2S_NS: i2s_ns::I2s = unsafe { i2s_ns::I2s::from_ptr(0x4002_8000usize as _) }; -#[doc = "Inter Processor Communication 0"] +#[doc = "Interprocessor communication 0"] pub const IPC_NS: ipc_ns::Ipc = unsafe { ipc_ns::Ipc::from_ptr(0x4002_a000usize as _) }; #[doc = "FPU 0"] pub const FPU_NS: fpu_ns::Fpu = unsafe { fpu_ns::Fpu::from_ptr(0x4002_c000usize as _) }; @@ -364,7 +364,7 @@ pub const TIMER2_S: timer_ns::Timer = unsafe { timer_ns::Timer::from_ptr(0x5001_ pub const RTC0_S: rtc_ns::Rtc = unsafe { rtc_ns::Rtc::from_ptr(0x5001_4000usize as _) }; #[doc = "Real-time counter 3"] pub const RTC1_S: rtc_ns::Rtc = unsafe { rtc_ns::Rtc::from_ptr(0x5001_5000usize as _) }; -#[doc = "Distributed Programmable Peripheral Interconnect Controller 1"] +#[doc = "Distributed programmable peripheral interconnect controller 1"] pub const DPPIC_S: dppic_ns::Dppic = unsafe { dppic_ns::Dppic::from_ptr(0x5001_7000usize as _) }; #[doc = "Watchdog Timer 1"] pub const WDT_S: wdt_ns::Wdt = unsafe { wdt_ns::Wdt::from_ptr(0x5001_8000usize as _) }; @@ -392,7 +392,7 @@ pub const PWM3_S: pwm_ns::Pwm = unsafe { pwm_ns::Pwm::from_ptr(0x5002_4000usize pub const PDM_S: pdm_ns::Pdm = unsafe { pdm_ns::Pdm::from_ptr(0x5002_6000usize as _) }; #[doc = "Inter-IC Sound 1"] pub const I2S_S: i2s_ns::I2s = unsafe { i2s_ns::I2s::from_ptr(0x5002_8000usize as _) }; -#[doc = "Inter Processor Communication 1"] +#[doc = "Interprocessor communication 1"] pub const IPC_S: ipc_ns::Ipc = unsafe { ipc_ns::Ipc::from_ptr(0x5002_a000usize as _) }; #[doc = "FPU 1"] pub const FPU_S: fpu_ns::Fpu = unsafe { fpu_ns::Fpu::from_ptr(0x5002_c000usize as _) }; @@ -803,14 +803,14 @@ pub mod clock_ns { impl Hfclkstat { #[doc = "Active clock source"] #[inline(always)] - pub const fn src(&self) -> bool { + pub const fn src(&self) -> super::vals::HfclkstatSrc { let val = (self.0 >> 0usize) & 0x01; - val != 0 + super::vals::HfclkstatSrc::from_bits(val as u8) } #[doc = "Active clock source"] #[inline(always)] - pub fn set_src(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + pub fn set_src(&mut self, val: super::vals::HfclkstatSrc) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); } #[doc = "HFCLK state"] #[inline(always)] @@ -1003,6 +1003,36 @@ pub mod clock_ns { } } pub mod vals { + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum HfclkstatSrc { + #[doc = "HFINT - 64 MHz on-chip oscillator"] + HFINT = 0x0, + #[doc = "HFXO - 64 MHz clock derived from external 32 MHz crystal oscillator"] + HFXO = 0x01, + } + impl HfclkstatSrc { + #[inline(always)] + pub const fn from_bits(val: u8) -> HfclkstatSrc { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for HfclkstatSrc { + #[inline(always)] + fn from(val: u8) -> HfclkstatSrc { + HfclkstatSrc::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: HfclkstatSrc) -> u8 { + HfclkstatSrc::to_bits(val) + } + } #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Lfclksrc { @@ -1208,12 +1238,12 @@ pub mod ctrl_ap_peri_s { pub const fn as_ptr(&self) -> *mut () { self.ptr as _ } - #[doc = "Lock register ERASEPROTECT.DISABLE from being written until next reset"] + #[doc = "This register locks the ERASEPROTECT.DISABLE register from being written until next reset."] #[inline(always)] pub const fn lock(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } - #[doc = "Disable ERASEPROTECT and perform ERASEALL"] + #[doc = "This register disables the ERASEPROTECT register and performs an ERASEALL operation."] #[inline(always)] pub const fn disable(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } @@ -1235,40 +1265,40 @@ pub mod ctrl_ap_peri_s { pub const fn as_ptr(&self) -> *mut () { self.ptr as _ } - #[doc = "Data sent from the debugger to the CPU"] + #[doc = "Data sent from the debugger to the CPU."] #[inline(always)] pub const fn rxdata(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } - #[doc = "Status to indicate if data sent from the debugger to the CPU has been read"] + #[doc = "This register shows a status that indicates if data sent from the debugger to the CPU has been read."] #[inline(always)] pub const fn rxstatus(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } - #[doc = "Data sent from the CPU to the debugger"] + #[doc = "Data sent from the CPU to the debugger."] #[inline(always)] pub const fn txdata(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x80usize) as _) } } - #[doc = "Status to indicate if data sent from the CPU to the debugger has been read"] + #[doc = "This register shows a status that indicates if the data sent from the CPU to the debugger has been read."] #[inline(always)] pub const fn txstatus(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x84usize) as _) } } } pub mod regs { - #[doc = "Lock register ERASEPROTECT.DISABLE from being written until next reset"] + #[doc = "This register locks the ERASEPROTECT.DISABLE register from being written until next reset."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Lock(pub u32); impl Lock { - #[doc = "Lock register ERASEPROTECT.DISABLE from being written until next reset"] + #[doc = "Lock ERASEPROTECT.DISABLE register from being written until next reset"] #[inline(always)] pub const fn lock(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Lock register ERASEPROTECT.DISABLE from being written until next reset"] + #[doc = "Lock ERASEPROTECT.DISABLE register from being written until next reset"] #[inline(always)] pub fn set_lock(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); @@ -1280,7 +1310,7 @@ pub mod ctrl_ap_peri_s { Lock(0) } } - #[doc = "Status to indicate if data sent from the debugger to the CPU has been read"] + #[doc = "This register shows a status that indicates if data sent from the debugger to the CPU has been read."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Rxstatus(pub u32); @@ -1303,7 +1333,7 @@ pub mod ctrl_ap_peri_s { Rxstatus(0) } } - #[doc = "Status to indicate if data sent from the CPU to the debugger has been read"] + #[doc = "This register shows a status that indicates if the data sent from the CPU to the debugger has been read."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Txstatus(pub u32); @@ -1329,7 +1359,7 @@ pub mod ctrl_ap_peri_s { } } pub mod dppic_ns { - #[doc = "Distributed Programmable Peripheral Interconnect Controller 0"] + #[doc = "Distributed programmable peripheral interconnect controller 0"] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Dppic { ptr: *mut u8, @@ -1372,7 +1402,7 @@ pub mod dppic_ns { pub const fn chenclr(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0508usize) as _) } } - #[doc = "Description collection: Channel group n Note: Writes to this register is ignored if either SUBSCRIBE_CHG\\[n\\].EN/DIS are enabled."] + #[doc = "Description collection: Channel group n Note: Writes to this register are ignored if either SUBSCRIBE_CHG\\[n\\].EN or SUBSCRIBE_CHG\\[n\\].DIS is enabled"] #[inline(always)] pub const fn chg(self, n: usize) -> crate::common::Reg { assert!(n < 6usize); @@ -1465,7 +1495,7 @@ pub mod dppic_ns { Chen(0) } } - #[doc = "Description collection: Channel group n Note: Writes to this register is ignored if either SUBSCRIBE_CHG\\[n\\].EN/DIS are enabled."] + #[doc = "Description collection: Channel group n Note: Writes to this register are ignored if either SUBSCRIBE_CHG\\[n\\].EN or SUBSCRIBE_CHG\\[n\\].DIS is enabled"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Chg(pub u32); @@ -1607,6 +1637,11 @@ pub mod ficr_s { pub const fn as_ptr(&self) -> *mut () { self.ptr as _ } + #[doc = "SIP-specific device info"] + #[inline(always)] + pub const fn sipinfo(self) -> Sipinfo { + unsafe { Sipinfo::from_ptr(self.ptr.add(0x0140usize) as _) } + } #[doc = "Device info"] #[inline(always)] pub const fn info(self) -> Info { @@ -1653,7 +1688,7 @@ pub mod ficr_s { } #[doc = "Part Variant, Hardware version and Production configuration"] #[inline(always)] - pub const fn variant(self) -> crate::common::Reg { + pub const fn variant(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) } } #[doc = "Package option"] @@ -1673,12 +1708,14 @@ pub mod ficr_s { } #[doc = "Code memory page size"] #[inline(always)] - pub const fn codepagesize(self) -> crate::common::Reg { + pub const fn codepagesize( + self, + ) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) } } #[doc = "Code memory size"] #[inline(always)] - pub const fn codesize(self) -> crate::common::Reg { + pub const fn codesize(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) } } #[doc = "Device type"] @@ -1687,6 +1724,40 @@ pub mod ficr_s { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) } } } + #[doc = "SIP-specific device info"] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Sipinfo { + ptr: *mut u8, + } + unsafe impl Send for Sipinfo {} + unsafe impl Sync for Sipinfo {} + impl Sipinfo { + #[inline(always)] + pub const unsafe fn from_ptr(ptr: *mut ()) -> Self { + Self { ptr: ptr as _ } + } + #[inline(always)] + pub const fn as_ptr(&self) -> *mut () { + self.ptr as _ + } + #[doc = "SIP part number"] + #[inline(always)] + pub const fn partno(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } + } + #[doc = "Description collection: SIP hardware revision, encoded in ASCII, ex B0A or B1A"] + #[inline(always)] + pub const fn hwrevision(self, n: usize) -> crate::common::Reg { + assert!(n < 4usize); + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize + n * 1usize) as _) } + } + #[doc = "Description collection: SIP VARIANT, encoded in ASCII, ex SIAA, SIBA or SICA"] + #[inline(always)] + pub const fn variant(self, n: usize) -> crate::common::Reg { + assert!(n < 4usize); + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize + n * 1usize) as _) } + } + } #[doc = "Unspecified"] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Trimcnf { @@ -1772,6 +1843,54 @@ pub mod ficr_s { } } pub mod regs { + #[doc = "Code memory page size"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Codepagesize(pub u32); + impl Codepagesize { + #[doc = "Code memory page size"] + #[inline(always)] + pub const fn codepagesize(&self) -> super::vals::Codepagesize { + let val = (self.0 >> 0usize) & 0xffff_ffff; + super::vals::Codepagesize::from_bits(val as u32) + } + #[doc = "Code memory page size"] + #[inline(always)] + pub fn set_codepagesize(&mut self, val: super::vals::Codepagesize) { + self.0 = (self.0 & !(0xffff_ffff << 0usize)) + | (((val.to_bits() as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Codepagesize { + #[inline(always)] + fn default() -> Codepagesize { + Codepagesize(0) + } + } + #[doc = "Code memory size"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Codesize(pub u32); + impl Codesize { + #[doc = "Code memory size in number of pages Total code space is: CODEPAGESIZE * CODESIZE"] + #[inline(always)] + pub const fn codesize(&self) -> super::vals::Codesize { + let val = (self.0 >> 0usize) & 0xffff_ffff; + super::vals::Codesize::from_bits(val as u32) + } + #[doc = "Code memory size in number of pages Total code space is: CODEPAGESIZE * CODESIZE"] + #[inline(always)] + pub fn set_codesize(&mut self, val: super::vals::Codesize) { + self.0 = (self.0 & !(0xffff_ffff << 0usize)) + | (((val.to_bits() as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Codesize { + #[inline(always)] + fn default() -> Codesize { + Codesize(0) + } + } #[doc = "Device type"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -1820,6 +1939,30 @@ pub mod ficr_s { Flash(0) } } + #[doc = "Part Variant, Hardware version and Production configuration"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct InfoVariant(pub u32); + impl InfoVariant { + #[doc = "Part Variant, Hardware version and Production configuration, encoded as ASCII"] + #[inline(always)] + pub const fn variant(&self) -> super::vals::Variant { + let val = (self.0 >> 0usize) & 0xffff_ffff; + super::vals::Variant::from_bits(val as u32) + } + #[doc = "Part Variant, Hardware version and Production configuration, encoded as ASCII"] + #[inline(always)] + pub fn set_variant(&mut self, val: super::vals::Variant) { + self.0 = (self.0 & !(0xffff_ffff << 0usize)) + | (((val.to_bits() as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for InfoVariant { + #[inline(always)] + fn default() -> InfoVariant { + InfoVariant(0) + } + } #[doc = "Package option"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -1868,6 +2011,28 @@ pub mod ficr_s { Part(0) } } + #[doc = "SIP part number"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Partno(pub u32); + impl Partno { + #[inline(always)] + pub const fn partno(&self) -> super::vals::Partno { + let val = (self.0 >> 0usize) & 0xffff_ffff; + super::vals::Partno::from_bits(val as u32) + } + #[inline(always)] + pub fn set_partno(&mut self, val: super::vals::Partno) { + self.0 = (self.0 & !(0xffff_ffff << 0usize)) + | (((val.to_bits() as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Partno { + #[inline(always)] + fn default() -> Partno { + Partno(0) + } + } #[doc = "RAM variant"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -1892,32 +2057,62 @@ pub mod ficr_s { Ram(0) } } - #[doc = "Part Variant, Hardware version and Production configuration"] + } + pub mod vals { #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Variant(pub u32); - impl Variant { - #[doc = "Part Variant, Hardware version and Production configuration, encoded as ASCII"] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Codepagesize(pub u32); + impl Codepagesize { + #[doc = "4 kByte"] + pub const K4096: Self = Self(0x1000); + } + impl Codepagesize { + pub const fn from_bits(val: u32) -> Codepagesize { + Self(val & 0xffff_ffff) + } + pub const fn to_bits(self) -> u32 { + self.0 + } + } + impl From for Codepagesize { #[inline(always)] - pub const fn variant(&self) -> super::vals::Variant { - let val = (self.0 >> 0usize) & 0xffff_ffff; - super::vals::Variant::from_bits(val as u32) + fn from(val: u32) -> Codepagesize { + Codepagesize::from_bits(val) } - #[doc = "Part Variant, Hardware version and Production configuration, encoded as ASCII"] + } + impl From for u32 { #[inline(always)] - pub fn set_variant(&mut self, val: super::vals::Variant) { - self.0 = (self.0 & !(0xffff_ffff << 0usize)) - | (((val.to_bits() as u32) & 0xffff_ffff) << 0usize); + fn from(val: Codepagesize) -> u32 { + Codepagesize::to_bits(val) + } + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Codesize(pub u32); + impl Codesize { + #[doc = "256 pages"] + pub const P256: Self = Self(0x0100); + } + impl Codesize { + pub const fn from_bits(val: u32) -> Codesize { + Self(val & 0xffff_ffff) + } + pub const fn to_bits(self) -> u32 { + self.0 } } - impl Default for Variant { + impl From for Codesize { #[inline(always)] - fn default() -> Variant { - Variant(0) + fn from(val: u32) -> Codesize { + Codesize::from_bits(val) + } + } + impl From for u32 { + #[inline(always)] + fn from(val: Codesize) -> u32 { + Codesize::to_bits(val) } } - } - pub mod vals { #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub struct Devicetype(pub u32); @@ -1978,8 +2173,8 @@ pub mod ficr_s { #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub struct Package(pub u32); impl Package { - #[doc = "CCxx - 236 ball wlCSP"] - pub const CC: Self = Self(0x2000); + #[doc = "CFxx - 236 ball wlCSP"] + pub const CF: Self = Self(0x2002); } impl Package { pub const fn from_bits(val: u32) -> Package { @@ -2005,6 +2200,8 @@ pub mod ficr_s { #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub struct Part(pub u32); impl Part { + #[doc = "nRF9120"] + pub const N9120: Self = Self(0x9120); #[doc = "nRF9160"] pub const N9160: Self = Self(0x9160); } @@ -2030,6 +2227,33 @@ pub mod ficr_s { } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Partno(pub u32); + impl Partno { + #[doc = "Device is an nRF9160 sip"] + pub const _9160: Self = Self(0x9160); + } + impl Partno { + pub const fn from_bits(val: u32) -> Partno { + Self(val & 0xffff_ffff) + } + pub const fn to_bits(self) -> u32 { + self.0 + } + } + impl From for Partno { + #[inline(always)] + fn from(val: u32) -> Partno { + Partno::from_bits(val) + } + } + impl From for u32 { + #[inline(always)] + fn from(val: Partno) -> u32 { + Partno::to_bits(val) + } + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub struct Ram(pub u32); impl Ram { #[doc = "256 kByte RAM"] @@ -2065,6 +2289,10 @@ pub mod ficr_s { pub const AAA0: Self = Self(0x4141_4130); #[doc = "AAAA"] pub const AAAA: Self = Self(0x4141_4141); + #[doc = "AAB0"] + pub const AAB0: Self = Self(0x4141_4230); + #[doc = "AAC0"] + pub const AAC0: Self = Self(0x4141_4330); } impl Variant { pub const fn from_bits(val: u32) -> Variant { @@ -2351,7 +2579,7 @@ pub mod gpio_ns { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Latch(pub u32); impl Latch { - #[doc = "Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear."] + #[doc = "Status on whether PIN\\[0\\] has met criteria set in PIN_CNF\\[0\\].SENSE register. Write '1' to clear."] #[inline(always)] pub const fn pin(&self, n: usize) -> bool { assert!(n < 32usize); @@ -2359,7 +2587,7 @@ pub mod gpio_ns { let val = (self.0 >> offs) & 0x01; val != 0 } - #[doc = "Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear."] + #[doc = "Status on whether PIN\\[0\\] has met criteria set in PIN_CNF\\[0\\].SENSE register. Write '1' to clear."] #[inline(always)] pub fn set_pin(&mut self, n: usize, val: bool) { assert!(n < 32usize); @@ -2823,7 +3051,7 @@ pub mod gpiote_s { pub const fn intenclr(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0308usize) as _) } } - #[doc = "Description collection: Configuration for OUT\\[n\\], SET\\[n\\] and CLR\\[n\\] tasks and IN\\[n\\] event"] + #[doc = "Description collection: Configuration for OUT\\[n\\], SET\\[n\\], and CLR\\[n\\] tasks and IN\\[n\\] event"] #[inline(always)] pub const fn config(self, n: usize) -> crate::common::Reg { assert!(n < 8usize); @@ -2831,7 +3059,7 @@ pub mod gpiote_s { } } pub mod regs { - #[doc = "Description collection: Configuration for OUT\\[n\\], SET\\[n\\] and CLR\\[n\\] tasks and IN\\[n\\] event"] + #[doc = "Description collection: Configuration for OUT\\[n\\], SET\\[n\\], and CLR\\[n\\] tasks and IN\\[n\\] event"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Config(pub u32); @@ -2847,13 +3075,13 @@ pub mod gpiote_s { pub fn set_mode(&mut self, val: super::vals::Mode) { self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); } - #[doc = "GPIO number associated with SET\\[n\\], CLR\\[n\\] and OUT\\[n\\] tasks and IN\\[n\\] event"] + #[doc = "GPIO number associated with SET\\[n\\], CLR\\[n\\], and OUT\\[n\\] tasks and IN\\[n\\] event"] #[inline(always)] pub const fn psel(&self) -> u8 { let val = (self.0 >> 8usize) & 0x1f; val as u8 } - #[doc = "GPIO number associated with SET\\[n\\], CLR\\[n\\] and OUT\\[n\\] tasks and IN\\[n\\] event"] + #[doc = "GPIO number associated with SET\\[n\\], CLR\\[n\\], and OUT\\[n\\] tasks and IN\\[n\\] event"] #[inline(always)] pub fn set_psel(&mut self, val: u8) { self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize); @@ -3991,7 +4219,7 @@ pub mod i2s_ns { } } pub mod ipc_ns { - #[doc = "Inter Processor Communication 0"] + #[doc = "Interprocessor communication 0"] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Ipc { ptr: *mut u8, @@ -4007,7 +4235,7 @@ pub mod ipc_ns { pub const fn as_ptr(&self) -> *mut () { self.ptr as _ } - #[doc = "Description collection: Trigger events on channel enabled in SEND_CNF\\[n\\]."] + #[doc = "Description collection: Trigger events on IPC channel enabled in SEND_CNF\\[n\\]"] #[inline(always)] pub const fn tasks_send(self, n: usize) -> crate::common::Reg { assert!(n < 8usize); @@ -4022,7 +4250,7 @@ pub mod ipc_ns { assert!(n < 8usize); unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x80usize + n * 4usize) as _) } } - #[doc = "Description collection: Event received on one or more of the enabled channels in RECEIVE_CNF\\[n\\]."] + #[doc = "Description collection: Event received on one or more of the enabled IPC channels in RECEIVE_CNF\\[n\\]"] #[inline(always)] pub const fn events_receive(self, n: usize) -> crate::common::Reg { assert!(n < 8usize); @@ -4057,7 +4285,7 @@ pub mod ipc_ns { pub const fn intpend(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x030cusize) as _) } } - #[doc = "Description collection: Send event configuration for TASKS_SEND\\[n\\]."] + #[doc = "Description collection: Send event configuration for TASKS_SEND\\[n\\]"] #[inline(always)] pub const fn send_cnf( self, @@ -4066,7 +4294,7 @@ pub mod ipc_ns { assert!(n < 8usize); unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0510usize + n * 4usize) as _) } } - #[doc = "Description collection: Receive event configuration for EVENTS_RECEIVE\\[n\\]."] + #[doc = "Description collection: Receive event configuration for EVENTS_RECEIVE\\[n\\]"] #[inline(always)] pub const fn receive_cnf( self, @@ -4075,7 +4303,7 @@ pub mod ipc_ns { assert!(n < 8usize); unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0590usize + n * 4usize) as _) } } - #[doc = "Description collection: General purpose memory."] + #[doc = "Description collection: General purpose memory"] #[inline(always)] pub const fn gpmem(self, n: usize) -> crate::common::Reg { assert!(n < 4usize); @@ -4283,95 +4511,95 @@ pub mod ipc_ns { Intpend(0) } } - #[doc = "Description collection: Receive event configuration for EVENTS_RECEIVE\\[n\\]."] + #[doc = "Description collection: Receive event configuration for EVENTS_RECEIVE\\[n\\]"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct ReceiveCnf(pub u32); impl ReceiveCnf { - #[doc = "Enable subscription to channel 0."] + #[doc = "Enable subscription to IPC channel 0"] #[inline(always)] pub const fn chen0(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Enable subscription to channel 0."] + #[doc = "Enable subscription to IPC channel 0"] #[inline(always)] pub fn set_chen0(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - #[doc = "Enable subscription to channel 1."] + #[doc = "Enable subscription to IPC channel 1"] #[inline(always)] pub const fn chen1(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; val != 0 } - #[doc = "Enable subscription to channel 1."] + #[doc = "Enable subscription to IPC channel 1"] #[inline(always)] pub fn set_chen1(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } - #[doc = "Enable subscription to channel 2."] + #[doc = "Enable subscription to IPC channel 2"] #[inline(always)] pub const fn chen2(&self) -> bool { let val = (self.0 >> 2usize) & 0x01; val != 0 } - #[doc = "Enable subscription to channel 2."] + #[doc = "Enable subscription to IPC channel 2"] #[inline(always)] pub fn set_chen2(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); } - #[doc = "Enable subscription to channel 3."] + #[doc = "Enable subscription to IPC channel 3"] #[inline(always)] pub const fn chen3(&self) -> bool { let val = (self.0 >> 3usize) & 0x01; val != 0 } - #[doc = "Enable subscription to channel 3."] + #[doc = "Enable subscription to IPC channel 3"] #[inline(always)] pub fn set_chen3(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); } - #[doc = "Enable subscription to channel 4."] + #[doc = "Enable subscription to IPC channel 4"] #[inline(always)] pub const fn chen4(&self) -> bool { let val = (self.0 >> 4usize) & 0x01; val != 0 } - #[doc = "Enable subscription to channel 4."] + #[doc = "Enable subscription to IPC channel 4"] #[inline(always)] pub fn set_chen4(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); } - #[doc = "Enable subscription to channel 5."] + #[doc = "Enable subscription to IPC channel 5"] #[inline(always)] pub const fn chen5(&self) -> bool { let val = (self.0 >> 5usize) & 0x01; val != 0 } - #[doc = "Enable subscription to channel 5."] + #[doc = "Enable subscription to IPC channel 5"] #[inline(always)] pub fn set_chen5(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); } - #[doc = "Enable subscription to channel 6."] + #[doc = "Enable subscription to IPC channel 6"] #[inline(always)] pub const fn chen6(&self) -> bool { let val = (self.0 >> 6usize) & 0x01; val != 0 } - #[doc = "Enable subscription to channel 6."] + #[doc = "Enable subscription to IPC channel 6"] #[inline(always)] pub fn set_chen6(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); } - #[doc = "Enable subscription to channel 7."] + #[doc = "Enable subscription to IPC channel 7"] #[inline(always)] pub const fn chen7(&self) -> bool { let val = (self.0 >> 7usize) & 0x01; val != 0 } - #[doc = "Enable subscription to channel 7."] + #[doc = "Enable subscription to IPC channel 7"] #[inline(always)] pub fn set_chen7(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); @@ -4383,95 +4611,95 @@ pub mod ipc_ns { ReceiveCnf(0) } } - #[doc = "Description collection: Send event configuration for TASKS_SEND\\[n\\]."] + #[doc = "Description collection: Send event configuration for TASKS_SEND\\[n\\]"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct SendCnf(pub u32); impl SendCnf { - #[doc = "Enable broadcasting on channel 0."] + #[doc = "Enable broadcasting on IPC channel 0"] #[inline(always)] pub const fn chen0(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Enable broadcasting on channel 0."] + #[doc = "Enable broadcasting on IPC channel 0"] #[inline(always)] pub fn set_chen0(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - #[doc = "Enable broadcasting on channel 1."] + #[doc = "Enable broadcasting on IPC channel 1"] #[inline(always)] pub const fn chen1(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; val != 0 } - #[doc = "Enable broadcasting on channel 1."] + #[doc = "Enable broadcasting on IPC channel 1"] #[inline(always)] pub fn set_chen1(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } - #[doc = "Enable broadcasting on channel 2."] + #[doc = "Enable broadcasting on IPC channel 2"] #[inline(always)] pub const fn chen2(&self) -> bool { let val = (self.0 >> 2usize) & 0x01; val != 0 } - #[doc = "Enable broadcasting on channel 2."] + #[doc = "Enable broadcasting on IPC channel 2"] #[inline(always)] pub fn set_chen2(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); } - #[doc = "Enable broadcasting on channel 3."] + #[doc = "Enable broadcasting on IPC channel 3"] #[inline(always)] pub const fn chen3(&self) -> bool { let val = (self.0 >> 3usize) & 0x01; val != 0 } - #[doc = "Enable broadcasting on channel 3."] + #[doc = "Enable broadcasting on IPC channel 3"] #[inline(always)] pub fn set_chen3(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); } - #[doc = "Enable broadcasting on channel 4."] + #[doc = "Enable broadcasting on IPC channel 4"] #[inline(always)] pub const fn chen4(&self) -> bool { let val = (self.0 >> 4usize) & 0x01; val != 0 } - #[doc = "Enable broadcasting on channel 4."] + #[doc = "Enable broadcasting on IPC channel 4"] #[inline(always)] pub fn set_chen4(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); } - #[doc = "Enable broadcasting on channel 5."] + #[doc = "Enable broadcasting on IPC channel 5"] #[inline(always)] pub const fn chen5(&self) -> bool { let val = (self.0 >> 5usize) & 0x01; val != 0 } - #[doc = "Enable broadcasting on channel 5."] + #[doc = "Enable broadcasting on IPC channel 5"] #[inline(always)] pub fn set_chen5(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); } - #[doc = "Enable broadcasting on channel 6."] + #[doc = "Enable broadcasting on IPC channel 6"] #[inline(always)] pub const fn chen6(&self) -> bool { let val = (self.0 >> 6usize) & 0x01; val != 0 } - #[doc = "Enable broadcasting on channel 6."] + #[doc = "Enable broadcasting on IPC channel 6"] #[inline(always)] pub fn set_chen6(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); } - #[doc = "Enable broadcasting on channel 7."] + #[doc = "Enable broadcasting on IPC channel 7"] #[inline(always)] pub const fn chen7(&self) -> bool { let val = (self.0 >> 7usize) & 0x01; val != 0 } - #[doc = "Enable broadcasting on channel 7."] + #[doc = "Enable broadcasting on IPC channel 7"] #[inline(always)] pub fn set_chen7(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); @@ -4651,13 +4879,13 @@ pub mod kmu_ns { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Selectkeyslot(pub u32); impl Selectkeyslot { - #[doc = "Select key slot ID to be read over AHB, or pushed over secure APB, when TASKS_PUSH_KEYSLOT is started NOTE: ID=0 is not a valid key slot ID. The 0 ID should be used when the KMU is idle or not in use NOTE: Index N in UICR->KEYSLOT.KEY\\[N\\] and UICR->KEYSLOT.CONFIG\\[N\\] corresponds to KMU key slot ID=N+1"] + #[doc = "Select key slot ID to be read over AHB, or pushed over secure APB, when TASKS_PUSH_KEYSLOT is started. NOTE: ID=0 is not a valid key slot ID. The 0 ID should be used when the KMU is idle or not in use. NOTE: Index N in UICR->KEYSLOT.KEY\\[N\\] and UICR->KEYSLOT.CONFIG\\[N\\] corresponds to KMU key slot ID=N+1."] #[inline(always)] pub const fn id(&self) -> u8 { let val = (self.0 >> 0usize) & 0xff; val as u8 } - #[doc = "Select key slot ID to be read over AHB, or pushed over secure APB, when TASKS_PUSH_KEYSLOT is started NOTE: ID=0 is not a valid key slot ID. The 0 ID should be used when the KMU is idle or not in use NOTE: Index N in UICR->KEYSLOT.KEY\\[N\\] and UICR->KEYSLOT.CONFIG\\[N\\] corresponds to KMU key slot ID=N+1"] + #[doc = "Select key slot ID to be read over AHB, or pushed over secure APB, when TASKS_PUSH_KEYSLOT is started. NOTE: ID=0 is not a valid key slot ID. The 0 ID should be used when the KMU is idle or not in use. NOTE: Index N in UICR->KEYSLOT.KEY\\[N\\] and UICR->KEYSLOT.CONFIG\\[N\\] corresponds to KMU key slot ID=N+1."] #[inline(always)] pub fn set_id(&mut self, val: u8) { self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); @@ -5426,13 +5654,13 @@ pub mod pdm_ns { pub fn set_operation(&mut self, val: super::vals::Operation) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); } - #[doc = "Defines on which PDM_CLK edge Left (or mono) is sampled"] + #[doc = "Defines on which PDM_CLK edge left (or mono) is sampled"] #[inline(always)] pub const fn edge(&self) -> super::vals::Edge { let val = (self.0 >> 1usize) & 0x01; super::vals::Edge::from_bits(val as u8) } - #[doc = "Defines on which PDM_CLK edge Left (or mono) is sampled"] + #[doc = "Defines on which PDM_CLK edge left (or mono) is sampled"] #[inline(always)] pub fn set_edge(&mut self, val: super::vals::Edge) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val.to_bits() as u32) & 0x01) << 1usize); @@ -5449,13 +5677,13 @@ pub mod pdm_ns { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Pdmclkctrl(pub u32); impl Pdmclkctrl { - #[doc = "PDM_CLK frequency"] + #[doc = "PDM_CLK frequency configuration."] #[inline(always)] pub const fn freq(&self) -> super::vals::Freq { let val = (self.0 >> 0usize) & 0xffff_ffff; super::vals::Freq::from_bits(val as u32) } - #[doc = "PDM_CLK frequency"] + #[doc = "PDM_CLK frequency configuration."] #[inline(always)] pub fn set_freq(&mut self, val: super::vals::Freq) { self.0 = (self.0 & !(0xffff_ffff << 0usize)) @@ -5564,11 +5792,11 @@ pub mod pdm_ns { #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub struct Gain(pub u8); impl Gain { - #[doc = "-20dB gain adjustment (minimum)"] + #[doc = "-20 dB gain adjustment (minimum)"] pub const MIN_GAIN: Self = Self(0x0); - #[doc = "0dB gain adjustment"] + #[doc = "0 dB gain adjustment"] pub const DEFAULT_GAIN: Self = Self(0x28); - #[doc = "+20dB gain adjustment (maximum)"] + #[doc = "+20 dB gain adjustment (maximum)"] pub const MAX_GAIN: Self = Self(0x50); } impl Gain { @@ -5594,9 +5822,9 @@ pub mod pdm_ns { #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Operation { - #[doc = "Sample and store one pair (Left + Right) of 16bit samples per RAM word R=\\[31:16\\]; L=\\[15:0\\]"] + #[doc = "Sample and store one pair (left + right) of 16-bit samples per RAM word R=\\[31:16\\]; L=\\[15:0\\]"] STEREO = 0x0, - #[doc = "Sample and store two successive Left samples (16 bit each) per RAM word L1=\\[31:16\\]; L0=\\[15:0\\]"] + #[doc = "Sample and store two successive left samples (16 bits each) per RAM word L1=\\[31:16\\]; L0=\\[15:0\\]"] MONO = 0x01, } impl Operation { @@ -5654,6 +5882,33 @@ pub mod pdm_ns { } } pub mod power_ns { + #[doc = "LTE Modem"] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ltemodem { + ptr: *mut u8, + } + unsafe impl Send for Ltemodem {} + unsafe impl Sync for Ltemodem {} + impl Ltemodem { + #[inline(always)] + pub const unsafe fn from_ptr(ptr: *mut ()) -> Self { + Self { ptr: ptr as _ } + } + #[inline(always)] + pub const fn as_ptr(&self) -> *mut () { + self.ptr as _ + } + #[doc = "Start LTE modem"] + #[inline(always)] + pub const fn startn(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } + } + #[doc = "Force off LTE modem"] + #[inline(always)] + pub const fn forceoff(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } + } + } #[doc = "Power control 0"] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Power { @@ -5764,8 +6019,36 @@ pub mod power_ns { assert!(n < 2usize); unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x051cusize + n * 4usize) as _) } } + #[doc = "LTE Modem"] + #[inline(always)] + pub const fn ltemodem(self) -> Ltemodem { + unsafe { Ltemodem::from_ptr(self.ptr.add(0x0610usize) as _) } + } } pub mod regs { + #[doc = "Force off LTE modem"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Forceoff(pub u32); + impl Forceoff { + #[doc = "Force off LTE modem"] + #[inline(always)] + pub const fn forceoff(&self) -> super::vals::Forceoff { + let val = (self.0 >> 0usize) & 0x01; + super::vals::Forceoff::from_bits(val as u8) + } + #[doc = "Force off LTE modem"] + #[inline(always)] + pub fn set_forceoff(&mut self, val: super::vals::Forceoff) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); + } + } + impl Default for Forceoff { + #[inline(always)] + fn default() -> Forceoff { + Forceoff(0) + } + } #[doc = "Description collection: General purpose retention register"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -5946,6 +6229,91 @@ pub mod power_ns { Resetreas(0) } } + #[doc = "Start LTE modem"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Startn(pub u32); + impl Startn { + #[doc = "Start LTE modem"] + #[inline(always)] + pub const fn startn(&self) -> super::vals::Startn { + let val = (self.0 >> 0usize) & 0x01; + super::vals::Startn::from_bits(val as u8) + } + #[doc = "Start LTE modem"] + #[inline(always)] + pub fn set_startn(&mut self, val: super::vals::Startn) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); + } + } + impl Default for Startn { + #[inline(always)] + fn default() -> Startn { + Startn(0) + } + } + } + pub mod vals { + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum Forceoff { + #[doc = "Release force off"] + RELEASE = 0x0, + #[doc = "Hold force off active"] + HOLD = 0x01, + } + impl Forceoff { + #[inline(always)] + pub const fn from_bits(val: u8) -> Forceoff { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for Forceoff { + #[inline(always)] + fn from(val: u8) -> Forceoff { + Forceoff::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: Forceoff) -> u8 { + Forceoff::to_bits(val) + } + } + #[repr(u8)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub enum Startn { + #[doc = "Start LTE modem"] + START = 0x0, + #[doc = "Hold LTE modem disabled"] + HOLD = 0x01, + } + impl Startn { + #[inline(always)] + pub const fn from_bits(val: u8) -> Startn { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } + } + impl From for Startn { + #[inline(always)] + fn from(val: u8) -> Startn { + Startn::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: Startn) -> u8 { + Startn::to_bits(val) + } + } } } pub mod pwm_ns { @@ -6820,6 +7188,11 @@ pub mod regulators_ns { pub const fn systemoff(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0500usize) as _) } } + #[doc = "External power failure warning configuration"] + #[inline(always)] + pub const fn extpofcon(self) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0514usize) as _) } + } #[doc = "Enable DC/DC mode of the main voltage regulator."] #[inline(always)] pub const fn dcdcen(self) -> crate::common::Reg { @@ -6850,6 +7223,29 @@ pub mod regulators_ns { Dcdcen(0) } } + #[doc = "External power failure warning configuration"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Extpofcon(pub u32); + impl Extpofcon { + #[doc = "Enable or disable external power failure warning"] + #[inline(always)] + pub const fn pof(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Enable or disable external power failure warning"] + #[inline(always)] + pub fn set_pof(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + } + impl Default for Extpofcon { + #[inline(always)] + fn default() -> Extpofcon { + Extpofcon(0) + } + } #[doc = "System OFF register"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -8808,16 +9204,16 @@ pub mod shared { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Publish(pub u32); impl Publish { - #[doc = "Channel that event HFCLKSTARTED will publish to."] + #[doc = "DPPI channel that event HFCLKSTARTED will publish to"] #[inline(always)] pub const fn chidx(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; + let val = (self.0 >> 0usize) & 0xff; val as u8 } - #[doc = "Channel that event HFCLKSTARTED will publish to."] + #[doc = "DPPI channel that event HFCLKSTARTED will publish to"] #[inline(always)] pub fn set_chidx(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); } #[inline(always)] pub const fn en(&self) -> bool { @@ -8840,16 +9236,16 @@ pub mod shared { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Subscribe(pub u32); impl Subscribe { - #[doc = "Channel that task HFCLKSTART will subscribe to"] + #[doc = "DPPI channel that task HFCLKSTART will subscribe to"] #[inline(always)] pub const fn chidx(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; + let val = (self.0 >> 0usize) & 0xff; val as u8 } - #[doc = "Channel that task HFCLKSTART will subscribe to"] + #[doc = "DPPI channel that task HFCLKSTART will subscribe to"] #[inline(always)] pub fn set_chidx(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); } #[inline(always)] pub const fn en(&self) -> bool { @@ -11877,13 +12273,13 @@ pub mod spu_s { #[doc = "Region number"] #[inline(always)] pub const fn region(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; + let val = (self.0 >> 0usize) & 0x1f; val as u8 } #[doc = "Region number"] #[inline(always)] pub fn set_region(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize); } #[inline(always)] pub const fn lock(&self) -> bool { @@ -12281,35 +12677,35 @@ pub mod tad_s { pub const fn as_ptr(&self) -> *mut () { self.ptr as _ } - #[doc = "Pin number configuration for TRACECLK"] + #[doc = "Pin configuration for TRACECLK"] #[inline(always)] pub const fn traceclk( self, ) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } - #[doc = "Pin number configuration for TRACEDATA\\[0\\]"] + #[doc = "Pin configuration for TRACEDATA\\[0\\]"] #[inline(always)] pub const fn tracedata0( self, ) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } - #[doc = "Pin number configuration for TRACEDATA\\[1\\]"] + #[doc = "Pin configuration for TRACEDATA\\[1\\]"] #[inline(always)] pub const fn tracedata1( self, ) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) } } - #[doc = "Pin number configuration for TRACEDATA\\[2\\]"] + #[doc = "Pin configuration for TRACEDATA\\[2\\]"] #[inline(always)] pub const fn tracedata2( self, ) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) } } - #[doc = "Pin number configuration for TRACEDATA\\[3\\]"] + #[doc = "Pin configuration for TRACEDATA\\[3\\]"] #[inline(always)] pub const fn tracedata3( self, @@ -12335,12 +12731,12 @@ pub mod tad_s { } #[doc = "Start all trace and debug clocks."] #[inline(always)] - pub const fn clockstart(self) -> crate::common::Reg { + pub const fn tasks_clockstart(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } } #[doc = "Stop all trace and debug clocks."] #[inline(always)] - pub const fn clockstop(self) -> crate::common::Reg { + pub const fn tasks_clockstop(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) } } #[doc = "Enable debug domain and aquire selected GPIOs"] @@ -12353,7 +12749,7 @@ pub mod tad_s { pub const fn psel(self) -> Psel { unsafe { Psel::from_ptr(self.ptr.add(0x0504usize) as _) } } - #[doc = "Clocking options for the Trace Port debug interface"] + #[doc = "Clocking options for the Trace Port debug interface Reset behavior is the same as debug components"] #[inline(always)] pub const fn traceportspeed( self, @@ -12362,48 +12758,6 @@ pub mod tad_s { } } pub mod regs { - #[doc = "Start all trace and debug clocks."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Clockstart(pub u32); - impl Clockstart { - #[inline(always)] - pub const fn start(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_start(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - } - impl Default for Clockstart { - #[inline(always)] - fn default() -> Clockstart { - Clockstart(0) - } - } - #[doc = "Stop all trace and debug clocks."] - #[repr(transparent)] - #[derive(Copy, Clone, Eq, PartialEq)] - pub struct Clockstop(pub u32); - impl Clockstop { - #[inline(always)] - pub const fn stop(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[inline(always)] - pub fn set_stop(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - } - impl Default for Clockstop { - #[inline(always)] - fn default() -> Clockstop { - Clockstop(0) - } - } #[doc = "Enable debug domain and aquire selected GPIOs"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -12425,18 +12779,18 @@ pub mod tad_s { Enable(0) } } - #[doc = "Clocking options for the Trace Port debug interface"] + #[doc = "Clocking options for the Trace Port debug interface Reset behavior is the same as debug components"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Traceportspeed(pub u32); impl Traceportspeed { - #[doc = "Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two."] + #[doc = "Speed of Trace Port clock. Note that the TRACECLK pin output will be divided again by two from the Trace Port clock."] #[inline(always)] pub const fn traceportspeed(&self) -> super::vals::Traceportspeed { let val = (self.0 >> 0usize) & 0x03; super::vals::Traceportspeed::from_bits(val as u8) } - #[doc = "Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two."] + #[doc = "Speed of Trace Port clock. Note that the TRACECLK pin output will be divided again by two from the Trace Port clock."] #[inline(always)] pub fn set_traceportspeed(&mut self, val: super::vals::Traceportspeed) { self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); @@ -12450,16 +12804,151 @@ pub mod tad_s { } } pub mod vals { + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct PselTraceclkPin(pub u8); + impl PselTraceclkPin { + #[doc = "TRACECLK pin"] + pub const TRACECLK: Self = Self(0x15); + } + impl PselTraceclkPin { + pub const fn from_bits(val: u8) -> PselTraceclkPin { + Self(val & 0x1f) + } + pub const fn to_bits(self) -> u8 { + self.0 + } + } + impl From for PselTraceclkPin { + #[inline(always)] + fn from(val: u8) -> PselTraceclkPin { + PselTraceclkPin::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: PselTraceclkPin) -> u8 { + PselTraceclkPin::to_bits(val) + } + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct PselTracedata0Pin(pub u8); + impl PselTracedata0Pin { + #[doc = "TRACEDATA0 pin"] + pub const TRACEDATA0: Self = Self(0x16); + } + impl PselTracedata0Pin { + pub const fn from_bits(val: u8) -> PselTracedata0Pin { + Self(val & 0x1f) + } + pub const fn to_bits(self) -> u8 { + self.0 + } + } + impl From for PselTracedata0Pin { + #[inline(always)] + fn from(val: u8) -> PselTracedata0Pin { + PselTracedata0Pin::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: PselTracedata0Pin) -> u8 { + PselTracedata0Pin::to_bits(val) + } + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct PselTracedata1Pin(pub u8); + impl PselTracedata1Pin { + #[doc = "TRACEDATA1 pin"] + pub const TRACEDATA1: Self = Self(0x17); + } + impl PselTracedata1Pin { + pub const fn from_bits(val: u8) -> PselTracedata1Pin { + Self(val & 0x1f) + } + pub const fn to_bits(self) -> u8 { + self.0 + } + } + impl From for PselTracedata1Pin { + #[inline(always)] + fn from(val: u8) -> PselTracedata1Pin { + PselTracedata1Pin::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: PselTracedata1Pin) -> u8 { + PselTracedata1Pin::to_bits(val) + } + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct PselTracedata2Pin(pub u8); + impl PselTracedata2Pin { + #[doc = "TRACEDATA2 pin"] + pub const TRACEDATA2: Self = Self(0x18); + } + impl PselTracedata2Pin { + pub const fn from_bits(val: u8) -> PselTracedata2Pin { + Self(val & 0x1f) + } + pub const fn to_bits(self) -> u8 { + self.0 + } + } + impl From for PselTracedata2Pin { + #[inline(always)] + fn from(val: u8) -> PselTracedata2Pin { + PselTracedata2Pin::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: PselTracedata2Pin) -> u8 { + PselTracedata2Pin::to_bits(val) + } + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct PselTracedata3Pin(pub u8); + impl PselTracedata3Pin { + #[doc = "TRACEDATA3 pin"] + pub const TRACEDATA3: Self = Self(0x19); + } + impl PselTracedata3Pin { + pub const fn from_bits(val: u8) -> PselTracedata3Pin { + Self(val & 0x1f) + } + pub const fn to_bits(self) -> u8 { + self.0 + } + } + impl From for PselTracedata3Pin { + #[inline(always)] + fn from(val: u8) -> PselTracedata3Pin { + PselTracedata3Pin::from_bits(val) + } + } + impl From for u8 { + #[inline(always)] + fn from(val: PselTracedata3Pin) -> u8 { + PselTracedata3Pin::to_bits(val) + } + } #[repr(u8)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub enum Traceportspeed { - #[doc = "32 MHz Trace Port clock (TRACECLK = 16 MHz)"] + #[doc = "Trace Port clock is: 32MHz"] _32MHZ = 0x0, - #[doc = "16 MHz Trace Port clock (TRACECLK = 8 MHz)"] + #[doc = "Trace Port clock is: 16MHz"] _16MHZ = 0x01, - #[doc = "8 MHz Trace Port clock (TRACECLK = 4 MHz)"] + #[doc = "Trace Port clock is: 8MHz"] _8MHZ = 0x02, - #[doc = "4 MHz Trace Port clock (TRACECLK = 2 MHz)"] + #[doc = "Trace Port clock is: 4MHz"] _4MHZ = 0x03, } impl Traceportspeed { @@ -14283,13 +14772,13 @@ pub mod twis_ns { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Match(pub u32); impl Match { - #[doc = "Which of the addresses in {ADDRESS} matched the incoming address"] + #[doc = "Indication of which address in {ADDRESS} that matched the incoming address"] #[inline(always)] pub const fn match_(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Which of the addresses in {ADDRESS} matched the incoming address"] + #[doc = "Indication of which address in {ADDRESS} that matched the incoming address"] #[inline(always)] pub fn set_match_(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); @@ -14938,7 +15427,7 @@ pub mod uarte_ns { pub const fn intenclr(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0308usize) as _) } } - #[doc = "Error source Note : this register is read / write one to clear."] + #[doc = "Error source This register is read/write one to clear."] #[inline(always)] pub const fn errorsrc(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0480usize) as _) } @@ -15067,7 +15556,7 @@ pub mod uarte_ns { Enable(0) } } - #[doc = "Error source Note : this register is read / write one to clear."] + #[doc = "Error source This register is read/write one to clear."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Errorsrc(pub u32); @@ -15422,7 +15911,7 @@ pub mod uarte_ns { pub const BAUD460800: Self = Self(0x0740_0000); #[doc = "921600 baud (actual rate: 941176)"] pub const BAUD921600: Self = Self(0x0f00_0000); - #[doc = "1Mega baud"] + #[doc = "1 megabaud"] pub const BAUD1M: Self = Self(0x1000_0000); } impl Baudrate { @@ -15574,7 +16063,7 @@ pub mod uicr_s { pub const fn as_ptr(&self) -> *mut () { self.ptr as _ } - #[doc = "Description cluster: Destination address where content of the key value registers (KEYSLOT.KEYn.VALUE\\[0-3\\]) will be pushed by KMU. Note that this address MUST match that of a peripherals APB mapped write-only key registers, else the KMU can push this key value into an address range which the CPU can potentially read!"] + #[doc = "Description cluster: Destination address where content of the key value registers (KEYSLOT.KEYn.VALUE\\[0-3\\]) will be pushed by KMU. Note that this address must match that of a peripherals APB mapped write-only key registers, else the KMU can push this key value into an address range which the CPU can potentially read."] #[inline(always)] pub const fn dest(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) } @@ -15673,6 +16162,13 @@ pub mod uicr_s { pub const fn hfxocnt(self) -> crate::common::Reg { unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) } } + #[doc = "Enable blocking NVM WRITE and aborting NVM ERASE for Application NVM in POFWARN condition ."] + #[inline(always)] + pub const fn appnvmcpofguard( + self, + ) -> crate::common::Reg { + unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) } + } #[doc = "Secure access port protection"] #[inline(always)] pub const fn secureapprotect( @@ -15700,6 +16196,29 @@ pub mod uicr_s { } } pub mod regs { + #[doc = "Enable blocking NVM WRITE and aborting NVM ERASE for Application NVM in POFWARN condition ."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Appnvmcpofguard(pub u32); + impl Appnvmcpofguard { + #[doc = "Enable blocking NVM WRITE and aborting NVM ERASE in POFWARN condition"] + #[inline(always)] + pub const fn nvmcpofguarden(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Enable blocking NVM WRITE and aborting NVM ERASE in POFWARN condition"] + #[inline(always)] + pub fn set_nvmcpofguarden(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + } + impl Default for Appnvmcpofguard { + #[inline(always)] + fn default() -> Appnvmcpofguard { + Appnvmcpofguard(0) + } + } #[doc = "Access port protection"] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] diff --git a/svd/nrf51.svd b/svd/nrf51.svd index 27686a2..7d5cb6d 100644 --- a/svd/nrf51.svd +++ b/svd/nrf51.svd @@ -8,42 +8,35 @@ 522 nRF51 reference description for radio MCU with ARM 32-bit Cortex-M0 Microcontroller at 16MHz CPU clock -Copyright (c) 2010 - 2017, Nordic Semiconductor ASA\n +Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved.\n \n -All rights reserved.\n +SPDX-License-Identifier: BSD-3-Clause\n \n -Redistribution and use in source and binary forms, with or without modification,\n -are permitted provided that the following conditions are met:\n +Redistribution and use in source and binary forms, with or without\n +modification, are permitted provided that the following conditions are met:\n \n 1. Redistributions of source code must retain the above copyright notice, this\n list of conditions and the following disclaimer.\n \n -2. Redistributions in binary form, except as embedded into a Nordic\n - Semiconductor ASA integrated circuit in a product or a software update for\n - such product, must reproduce the above copyright notice, this list of\n - conditions and the following disclaimer in the documentation and/or other\n - materials provided with the distribution.\n +2. Redistributions in binary form must reproduce the above copyright\n + notice, this list of conditions and the following disclaimer in the\n + documentation and/or other materials provided with the distribution.\n \n 3. Neither the name of Nordic Semiconductor ASA nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n \n -4. This software, with or without modification, must only be used with a\n - Nordic Semiconductor ASA integrated circuit.\n -\n -5. Any software provided in binary form under this license must not be reverse\n - engineered, decompiled, modified and/or disassembled.\n -\n -THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS\n -OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES\n -OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE\n -DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\n +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\n +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE\n +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\n LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\n -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT\n -OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n +POSSIBILITY OF SUCH DAMAGE.\n @@ -6948,8 +6941,6 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ 522 SPI master 1. 0x40004000 - SPI - 32 read-write SPI1_TWI1 @@ -6962,8 +6953,6 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ 522 Two-wire interface master 1. 0x40004000 - TWI - 32 read-write SPI1 @@ -8883,8 +8872,6 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ 522 Timer 1. 0x40009000 - TIMER - 32 read-write TIMER1 @@ -8897,8 +8884,6 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ 522 Timer 2. 0x4000A000 - TIMER - 32 read-write TIMER2 @@ -11566,8 +11551,6 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ 522 Real time counter 1. 0x40011000 - RTC - 32 read-write RTC1 diff --git a/svd/nrf52805.svd b/svd/nrf52805.svd index e3e805d..30477b5 100644 --- a/svd/nrf52805.svd +++ b/svd/nrf52805.svd @@ -8,7 +8,7 @@ 1 nRF52805 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller -Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.\n +Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved.\n \n SPDX-License-Identifier: BSD-3-Clause\n \n @@ -52,7 +52,7 @@ POSSIBILITY OF SUCH DAMAGE.\n 3 0 - system_nrf52805 + system_nrf52 NRF_ 2048 @@ -716,6 +716,23 @@ POSSIBILITY OF SUCH DAMAGE.\n + + 0x8 + 0x4 + NRFMDK[%s] + Description collection: Reserved for Nordic MDK + 0x100 + read-write + 0xFFFFFFFF + + + NRFMDK + Reserved for Nordic MDK + 0 + 31 + + + 0x2 0x4 @@ -766,9 +783,14 @@ POSSIBILITY OF SUCH DAMAGE.\n Disabled - Disable + Hardware disable of access port protection for devices where access port protection is controlled by hardware 0xFF + + HwDisabled + Hardware disable of access port protection for devices where access port protection is controlled by hardware and software + 0x5A + Enabled Enable @@ -32919,4 +32941,4 @@ POSSIBILITY OF SUCH DAMAGE.\n - \ No newline at end of file + diff --git a/svd/nrf52810.svd b/svd/nrf52810.svd index 073438a..2412d53 100644 --- a/svd/nrf52810.svd +++ b/svd/nrf52810.svd @@ -8,7 +8,9 @@ 1 nRF52810 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller -Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.\n +Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved.\n +\n +SPDX-License-Identifier: BSD-3-Clause\n \n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions are met:\n @@ -50,7 +52,7 @@ POSSIBILITY OF SUCH DAMAGE.\n 3 0 - system_nrf52810 + system_nrf52 NRF_ 2048 @@ -101,7 +103,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - 2 + 0x2 0x4 DEVICEID[%s] Description collection: Device identifier @@ -118,7 +120,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - 4 + 0x4 0x4 ER[%s] Description collection: Encryption root, word n @@ -135,7 +137,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - 4 + 0x4 0x4 IR[%s] Description collection: Identity root, word n @@ -179,7 +181,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - 2 + 0x2 0x4 DEVICEADDR[%s] Description collection: Device address n @@ -219,6 +221,16 @@ POSSIBILITY OF SUCH DAMAGE.\n nRF52810 0x52810 + + N52811 + nRF52811 + 0x52811 + + + N52832 + nRF52832 + 0x52832 + Unspecified Unspecified @@ -313,6 +325,11 @@ POSSIBILITY OF SUCH DAMAGE.\n QCxx - 32-pin QFN 0x2003 + + CA + CAxx - WLCSP + 0x2004 + Unspecified Unspecified @@ -654,7 +671,7 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x20 - 15 + 0xD 0x4 NRFFW[%s] Description collection: Reserved for Nordic firmware design @@ -671,7 +688,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - 12 + 0xC 0x4 NRFHW[%s] Description collection: Reserved for Nordic hardware design @@ -688,7 +705,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - 32 + 0x20 0x4 CUSTOMER[%s] Description collection: Reserved for customer @@ -705,7 +722,24 @@ POSSIBILITY OF SUCH DAMAGE.\n - 2 + 0x8 + 0x4 + NRFMDK[%s] + Description collection: Reserved for Nordic MDK + 0x100 + read-write + 0xFFFFFFFF + + + NRFMDK + Reserved for Nordic MDK + 0 + 31 + + + + + 0x2 0x4 PSELRESET[%s] Description collection: Mapping of the nRESET function (see POWER chapter for details) @@ -754,9 +788,14 @@ POSSIBILITY OF SUCH DAMAGE.\n Disabled - Disable + Hardware disable of access port protection for devices where access port protection is controlled by hardware 0xFF + + HwDisabled + Hardware disable of access port protection for devices where access port protection is controlled by hardware and software + 0x5A + Enabled Enable @@ -1689,6 +1728,66 @@ POSSIBILITY OF SUCH DAMAGE.\n + + APPROTECT + Only for emulation on devices that support hardened AP-PROTECT. + 0x40000000 + BPROT + + 0 + 0x1000 + registers + + APPROTECT + 0x20 + + + FORCEPROTECT + Software force enable APPROTECT mechanism until next reset. + 0x550 + read-writeOnce + 0xFFFFFFFF + + + FORCEPROTECT + Write 0x0 to force enable APPROTECT mechanism + 0 + 7 + + write + + Force + Software force enable APPROTECT mechanism + 0x0 + + + + + + + DISABLE + Software disable APPROTECT mechanism + 0x558 + read-write + 0x00000000 + + + DISABLE + Software disable APPROTECT mechanism + 0 + 7 + + + SwDisable + Software disable APPROTECT mechanism + 0x5A + + + + + + + CLOCK Clock control @@ -2467,13 +2566,13 @@ POSSIBILITY OF SUCH DAMAGE.\n TASKS_CONSTLAT - Enable constant latency mode + Enable Constant Latency mode 0x078 write-only TASKS_CONSTLAT - Enable constant latency mode + Enable Constant Latency mode 0 0 @@ -2488,13 +2587,13 @@ POSSIBILITY OF SUCH DAMAGE.\n TASKS_LOWPWR - Enable low power mode (variable latency) + Enable Low-power mode (variable latency) 0x07C write-only TASKS_LOWPWR - Enable low power mode (variable latency) + Enable Low-power mode (variable latency) 0 0 @@ -9130,7 +9229,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - 32 + 0x20 0x4 PIN_CNF[%s] Description collection: Configuration of GPIO pins @@ -11326,7 +11425,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - 8 + 0x8 0x4 DAB[%s] Description collection: Device address base segment n @@ -11342,7 +11441,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - 8 + 0x8 0x4 DAP[%s] Description collection: Device address prefix n @@ -17855,7 +17954,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - 2 + 0x2 0x4 ADDRESS[%s] Description collection: TWI slave address n @@ -20142,7 +20241,7 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x20 - 8 + 0x8 0x4 TASKS_OUT[%s] Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. @@ -20165,7 +20264,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - 8 + 0x8 0x4 TASKS_SET[%s] Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. @@ -20188,7 +20287,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - 8 + 0x8 0x4 TASKS_CLR[%s] Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. @@ -20211,7 +20310,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - 8 + 0x8 0x4 EVENTS_IN[%s] Description collection: Event generated from pin specified in CONFIG[n].PSEL @@ -20767,7 +20866,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - 8 + 0x8 0x4 CONFIG[%s] Description collection: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event @@ -23503,7 +23602,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - 4 + 0x6 0x4 TASKS_CAPTURE[%s] Description collection: Capture Timer value to CC[n] register @@ -23526,7 +23625,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - 4 + 0x6 0x4 EVENTS_COMPARE[%s] Description collection: Compare event on CC[n] match @@ -23631,6 +23730,42 @@ POSSIBILITY OF SUCH DAMAGE.\n + + COMPARE4_CLEAR + Shortcut between event COMPARE[4] and task CLEAR + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE5_CLEAR + Shortcut between event COMPARE[5] and task CLEAR + 5 + 5 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + COMPARE0_STOP Shortcut between event COMPARE[0] and task STOP @@ -23703,6 +23838,42 @@ POSSIBILITY OF SUCH DAMAGE.\n + + COMPARE4_STOP + Shortcut between event COMPARE[4] and task STOP + 12 + 12 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE5_STOP + Shortcut between event COMPARE[5] and task STOP + 13 + 13 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + @@ -23989,6 +24160,60 @@ POSSIBILITY OF SUCH DAMAGE.\n + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + @@ -24074,7 +24299,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - 4 + 0x6 0x4 CC[%s] Description collection: Capture/Compare register n @@ -24263,7 +24488,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - 4 + 0x4 0x4 EVENTS_COMPARE[%s] Description collection: Compare event on CC[n] match @@ -25115,7 +25340,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - 4 + 0x4 0x4 CC[%s] Description collection: Compare register n @@ -27588,7 +27813,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - 8 + 0x8 0x4 RR[%s] Description collection: Reload request n @@ -29613,7 +29838,7 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x20 - 16 + 0x10 0x4 TASKS_TRIGGER[%s] Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event @@ -29636,7 +29861,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - 16 + 0x10 0x4 EVENTS_TRIGGERED[%s] Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task @@ -30962,7 +31187,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - 2 + 0x2 0x4 TASKS_SEQSTART[%s] Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. @@ -31032,7 +31257,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - 2 + 0x2 0x4 EVENTS_SEQSTARTED[%s] Description collection: First PWM period started on sequence n @@ -31060,7 +31285,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - 2 + 0x2 0x4 EVENTS_SEQEND[%s] Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter @@ -32058,7 +32283,7 @@ POSSIBILITY OF SUCH DAMAGE.\n read-write 0x560 - 4 + 0x4 0x4 OUT[%s] Description collection: Output pin select for PWM channel n @@ -35376,7 +35601,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - 6 + 0x6 0x4 CHG[%s] Description collection: Channel group n diff --git a/svd/nrf52811.svd b/svd/nrf52811.svd index e17f4c6..daec52e 100644 --- a/svd/nrf52811.svd +++ b/svd/nrf52811.svd @@ -1,38250 +1,38414 @@ - - - - Nordic Semiconductor - Nordic - nrf52811 - nrf52 - 1 - nRF52811 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller - -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved.\n -\n -Redistribution and use in source and binary forms, with or without\n -modification, are permitted provided that the following conditions are met:\n -\n -1. Redistributions of source code must retain the above copyright notice, this\n - list of conditions and the following disclaimer.\n -\n -2. Redistributions in binary form must reproduce the above copyright\n - notice, this list of conditions and the following disclaimer in the\n - documentation and/or other materials provided with the distribution.\n -\n -3. Neither the name of Nordic Semiconductor ASA nor the names of its\n - contributors may be used to endorse or promote products derived from this\n - software without specific prior written permission.\n -\n -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\n -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n -IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE\n -ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\n -LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n -SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n -INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n -CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n -POSSIBILITY OF SUCH DAMAGE.\n - - 8 - 32 - 32 - 0x00000000 - 0xFFFFFFFF - - CM4 - r0p1 - little - 1 - 0 - 3 - 0 - - system_nrf52811 - NRF_ - - 2048 - 2048 - 112 - - - - FICR - Factory information configuration registers - 0x10000000 - - 0 - 0x1000 - registers - - FICR - 0x20 - - - CODEPAGESIZE - Code memory page size - 0x010 - read-only - 0x00001000 - - - CODEPAGESIZE - Code memory page size - 0 - 31 - - - - - CODESIZE - Code memory size - 0x014 - read-only - 0x00000030 - - - CODESIZE - Code memory size in number of pages - 0 - 31 - - - - - 0x2 - 0x4 - DEVICEID[%s] - Description collection: Device identifier - 0x060 - read-only - 0xFFFFFFFF - - - DEVICEID - 64 bit unique device identifier - 0 - 31 - - - - - 0x4 - 0x4 - ER[%s] - Description collection: Encryption root, word n - 0x080 - read-only - 0xFFFFFFFF - - - ER - Encryption root, word n - 0 - 31 - - - - - 0x4 - 0x4 - IR[%s] - Description collection: Identity root, word n - 0x090 - read-only - 0xFFFFFFFF - - - IR - Identity root, word n - 0 - 31 - - - - - DEVICEADDRTYPE - Device address type - 0x0A0 - read-only - 0xFFFFFFFF - - - DEVICEADDRTYPE - Device address type - 0 - 0 - - - Public - Public address - 0 - - - Random - Random address - 1 - - - - - - - 0x2 - 0x4 - DEVICEADDR[%s] - Description collection: Device address n - 0x0A4 - read-only - 0xFFFFFFFF - - - DEVICEADDR - 48 bit device address - 0 - 31 - - - - - INFO - Device info - FICR_INFO - read-only - 0x100 - - PART - Part code - 0x000 - read-only - 0x00052811 - - - PART - Part code - 0 - 31 - - - N52810 - nRF52810 - 0x52810 - - - N52811 - nRF52811 - 0x52811 - - - N52832 - nRF52832 - 0x52832 - - - Unspecified - Unspecified - 0xFFFFFFFF - - - - - - - VARIANT - Part variant, hardware version and production configuration - 0x004 - read-only - 0xFFFFFFFF - - - VARIANT - Part variant, hardware version and production configuration, encoded as ASCII - 0 - 31 - - - AAAA - AAAA - 0x41414141 - - - AAA0 - AAA0 - 0x41414130 - - - AABA - AABA - 0x41414241 - - - AABB - AABB - 0x41414242 - - - AAB0 - AAB0 - 0x41414230 - - - AACA - AACA - 0x41414341 - - - AACB - AACB - 0x41414342 - - - AAC0 - AAC0 - 0x41414330 - - - Unspecified - Unspecified - 0xFFFFFFFF - - - - - - - PACKAGE - Package option - 0x008 - read-only - 0xFFFFFFFF - - - PACKAGE - Package option - 0 - 31 - - - QF - QFxx - 48-pin QFN - 0x2000 - - - QC - QCxx - 32-pin QFN - 0x2003 - - - CA - CAxx - WLCSP - 0x2004 - - - Unspecified - Unspecified - 0xFFFFFFFF - - - - - - - RAM - RAM variant - 0x00C - read-only - 0x00000018 - - - RAM - RAM variant - 0 - 31 - - - K24 - 24 kByte RAM - 0x18 - - - Unspecified - Unspecified - 0xFFFFFFFF - - - - - - - FLASH - Flash variant - 0x010 - read-only - 0x000000C0 - - - FLASH - Flash variant - 0 - 31 - - - K192 - 192 kByte flash - 0xC0 - - - Unspecified - Unspecified - 0xFFFFFFFF - - - - - - - - TEMP - Registers storing factory TEMP module linearization coefficients - FICR_TEMP - read-only - 0x404 - - A0 - Slope definition A0 - 0x000 - read-only - 0x00000320 - - - A - A (slope definition) register - 0 - 11 - - - - - A1 - Slope definition A1 - 0x004 - read-only - 0x00000343 - - - A - A (slope definition) register - 0 - 11 - - - - - A2 - Slope definition A2 - 0x008 - read-only - 0x0000035D - - - A - A (slope definition) register - 0 - 11 - - - - - A3 - Slope definition A3 - 0x00C - read-only - 0x00000400 - - - A - A (slope definition) register - 0 - 11 - - - - - A4 - Slope definition A4 - 0x010 - read-only - 0x00000452 - - - A - A (slope definition) register - 0 - 11 - - - - - A5 - Slope definition A5 - 0x014 - read-only - 0x0000037B - - - A - A (slope definition) register - 0 - 11 - - - - - B0 - Y-intercept B0 - 0x018 - read-only - 0x00003FCC - - - B - B (y-intercept) - 0 - 13 - - - - - B1 - Y-intercept B1 - 0x01C - read-only - 0x00003F98 - - - B - B (y-intercept) - 0 - 13 - - - - - B2 - Y-intercept B2 - 0x020 - read-only - 0x00003F98 - - - B - B (y-intercept) - 0 - 13 - - - - - B3 - Y-intercept B3 - 0x024 - read-only - 0x00000012 - - - B - B (y-intercept) - 0 - 13 - - - - - B4 - Y-intercept B4 - 0x028 - read-only - 0x0000004D - - - B - B (y-intercept) - 0 - 13 - - - - - B5 - Y-intercept B5 - 0x02C - read-only - 0x00003E10 - - - B - B (y-intercept) - 0 - 13 - - - - - T0 - Segment end T0 - 0x030 - read-only - 0x000000E2 - - - T - T (segment end) register - 0 - 7 - - - - - T1 - Segment end T1 - 0x034 - read-only - 0x00000000 - - - T - T (segment end) register - 0 - 7 - - - - - T2 - Segment end T2 - 0x038 - read-only - 0x00000014 - - - T - T (segment end) register - 0 - 7 - - - - - T3 - Segment end T3 - 0x03C - read-only - 0x00000019 - - - T - T (segment end) register - 0 - 7 - - - - - T4 - Segment end T4 - 0x040 - read-only - 0x00000050 - - - T - T (segment end) register - 0 - 7 - - - - - - - - UICR - User information configuration registers - 0x10001000 - - 0 - 0x1000 - registers - - UICR - 0x20 - - - 0xD - 0x4 - NRFFW[%s] - Description collection: Reserved for Nordic firmware design - 0x014 - read-write - 0xFFFFFFFF - - - NRFFW - Reserved for Nordic firmware design - 0 - 31 - - - - - 0xC - 0x4 - NRFHW[%s] - Description collection: Reserved for Nordic hardware design - 0x050 - read-write - 0xFFFFFFFF - - - NRFHW - Reserved for Nordic hardware design - 0 - 31 - - - - - 0x20 - 0x4 - CUSTOMER[%s] - Description collection: Reserved for customer - 0x080 - read-write - 0xFFFFFFFF - - - CUSTOMER - Reserved for customer - 0 - 31 - - - - - 0x2 - 0x4 - PSELRESET[%s] - Description collection: Mapping of the nRESET function (see POWER chapter for details) - 0x200 - read-write - 0xFFFFFFFF - - - PIN - GPIO pin number onto which nRESET is exposed - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - APPROTECT - Access port protection - 0x208 - read-write - 0xFFFFFFFF - - - PALL - Enable or disable access port protection. - 0 - 7 - - - Disabled - Disable - 0xFF - - - Enabled - Enable - 0x00 - - - - - - - - - BPROT - Block Protect - 0x40000000 - - 0 - 0x1000 - registers - - BPROT - 0x20 - - - CONFIG0 - Block protect configuration register 0 - 0x600 - read-write - - - REGION0 - Enable protection for region 0. Write '0' has no effect. - 0 - 0 - - - Disabled - Protection disabled - 0 - - - Enabled - Protection enabled - 1 - - - - - REGION1 - Enable protection for region 1. Write '0' has no effect. - 1 - 1 - - - Disabled - Protection disabled - 0 - - - Enabled - Protection enabled - 1 - - - - - REGION2 - Enable protection for region 2. Write '0' has no effect. - 2 - 2 - - - Disabled - Protection disabled - 0 - - - Enabled - Protection enabled - 1 - - - - - REGION3 - Enable protection for region 3. Write '0' has no effect. - 3 - 3 - - - Disabled - Protection disabled - 0 - - - Enabled - Protection enabled - 1 - - - - - REGION4 - Enable protection for region 4. Write '0' has no effect. - 4 - 4 - - - Disabled - Protection disabled - 0 - - - Enabled - Protection enabled - 1 - - - - - REGION5 - Enable protection for region 5. Write '0' has no effect. - 5 - 5 - - - Disabled - Protection disabled - 0 - - - Enabled - Protection enabled - 1 - - - - - REGION6 - Enable protection for region 6. Write '0' has no effect. - 6 - 6 - - - Disabled - Protection disabled - 0 - - - Enabled - Protection enabled - 1 - - - - - REGION7 - Enable protection for region 7. Write '0' has no effect. - 7 - 7 - - - Disabled - Protection disabled - 0 - - - Enabled - Protection enabled - 1 - - - - - REGION8 - Enable protection for region 8. Write '0' has no effect. - 8 - 8 - - - Disabled - Protection disabled - 0 - - - Enabled - Protection enabled - 1 - - - - - REGION9 - Enable protection for region 9. Write '0' has no effect. - 9 - 9 - - - Disabled - Protection disabled - 0 - - - Enabled - Protection enabled - 1 - - - - - REGION10 - Enable protection for region 10. Write '0' has no effect. - 10 - 10 - - - Disabled - Protection disabled - 0 - - - Enabled - Protection enabled - 1 - - - - - REGION11 - Enable protection for region 11. Write '0' has no effect. - 11 - 11 - - - Disabled - Protection disabled - 0 - - - Enabled - Protection enabled - 1 - - - - - REGION12 - Enable protection for region 12. Write '0' has no effect. - 12 - 12 - - - Disabled - Protection disabled - 0 - - - Enabled - Protection enabled - 1 - - - - - REGION13 - Enable protection for region 13. Write '0' has no effect. - 13 - 13 - - - Disabled - Protection disabled - 0 - - - Enabled - Protection enabled - 1 - - - - - REGION14 - Enable protection for region 14. Write '0' has no effect. - 14 - 14 - - - Disabled - Protection disabled - 0 - - - Enabled - Protection enabled - 1 - - - - - REGION15 - Enable protection for region 15. Write '0' has no effect. - 15 - 15 - - - Disabled - Protection disabled - 0 - - - Enabled - Protection enabled - 1 - - - - - REGION16 - Enable protection for region 16. Write '0' has no effect. - 16 - 16 - - - Disabled - Protection disabled - 0 - - - Enabled - Protection enabled - 1 - - - - - REGION17 - Enable protection for region 17. Write '0' has no effect. - 17 - 17 - - - Disabled - Protection disabled - 0 - - - Enabled - Protection enabled - 1 - - - - - REGION18 - Enable protection for region 18. Write '0' has no effect. - 18 - 18 - - - Disabled - Protection disabled - 0 - - - Enabled - Protection enabled - 1 - - - - - REGION19 - Enable protection for region 19. Write '0' has no effect. - 19 - 19 - - - Disabled - Protection disabled - 0 - - - Enabled - Protection enabled - 1 - - - - - REGION20 - Enable protection for region 20. Write '0' has no effect. - 20 - 20 - - - Disabled - Protection disabled - 0 - - - Enabled - Protection enabled - 1 - - - - - REGION21 - Enable protection for region 21. Write '0' has no effect. - 21 - 21 - - - Disabled - Protection disabled - 0 - - - Enabled - Protection enabled - 1 - - - - - REGION22 - Enable protection for region 22. Write '0' has no effect. - 22 - 22 - - - Disabled - Protection disabled - 0 - - - Enabled - Protection enabled - 1 - - - - - REGION23 - Enable protection for region 23. Write '0' has no effect. - 23 - 23 - - - Disabled - Protection disabled - 0 - - - Enabled - Protection enabled - 1 - - - - - REGION24 - Enable protection for region 24. Write '0' has no effect. - 24 - 24 - - - Disabled - Protection disabled - 0 - - - Enabled - Protection enabled - 1 - - - - - REGION25 - Enable protection for region 25. Write '0' has no effect. - 25 - 25 - - - Disabled - Protection disabled - 0 - - - Enabled - Protection enabled - 1 - - - - - REGION26 - Enable protection for region 26. Write '0' has no effect. - 26 - 26 - - - Disabled - Protection disabled - 0 - - - Enabled - Protection enabled - 1 - - - - - REGION27 - Enable protection for region 27. Write '0' has no effect. - 27 - 27 - - - Disabled - Protection disabled - 0 - - - Enabled - Protection enabled - 1 - - - - - REGION28 - Enable protection for region 28. Write '0' has no effect. - 28 - 28 - - - Disabled - Protection disabled - 0 - - - Enabled - Protection enabled - 1 - - - - - REGION29 - Enable protection for region 29. Write '0' has no effect. - 29 - 29 - - - Disabled - Protection disabled - 0 - - - Enabled - Protection enabled - 1 - - - - - REGION30 - Enable protection for region 30. Write '0' has no effect. - 30 - 30 - - - Disabled - Protection disabled - 0 - - - Enabled - Protection enabled - 1 - - - - - REGION31 - Enable protection for region 31. Write '0' has no effect. - 31 - 31 - - - Disabled - Protection disabled - 0 - - - Enabled - Protection enabled - 1 - - - - - - - CONFIG1 - Block protect configuration register 1 - 0x604 - read-write - - - REGION32 - Enable protection for region 32. Write '0' has no effect. - 0 - 0 - - - Disabled - Protection disabled - 0 - - - Enabled - Protection enabled - 1 - - - - - REGION33 - Enable protection for region 33. Write '0' has no effect. - 1 - 1 - - - Disabled - Protection disabled - 0 - - - Enabled - Protection enabled - 1 - - - - - REGION34 - Enable protection for region 34. Write '0' has no effect. - 2 - 2 - - - Disabled - Protection disabled - 0 - - - Enabled - Protection enabled - 1 - - - - - REGION35 - Enable protection for region 35. Write '0' has no effect. - 3 - 3 - - - Disabled - Protection disabled - 0 - - - Enabled - Protection enabled - 1 - - - - - REGION36 - Enable protection for region 36. Write '0' has no effect. - 4 - 4 - - - Disabled - Protection disabled - 0 - - - Enabled - Protection enabled - 1 - - - - - REGION37 - Enable protection for region 37. Write '0' has no effect. - 5 - 5 - - - Disabled - Protection disabled - 0 - - - Enabled - Protection enabled - 1 - - - - - REGION38 - Enable protection for region 38. Write '0' has no effect. - 6 - 6 - - - Disabled - Protection disabled - 0 - - - Enabled - Protection enabled - 1 - - - - - REGION39 - Enable protection for region 39. Write '0' has no effect. - 7 - 7 - - - Disabled - Protection disabled - 0 - - - Enabled - Protection enabled - 1 - - - - - REGION40 - Enable protection for region 40. Write '0' has no effect. - 8 - 8 - - - Disabled - Protection disabled - 0 - - - Enabled - Protection enabled - 1 - - - - - REGION41 - Enable protection for region 41. Write '0' has no effect. - 9 - 9 - - - Disabled - Protection disabled - 0 - - - Enabled - Protection enabled - 1 - - - - - REGION42 - Enable protection for region 42. Write '0' has no effect. - 10 - 10 - - - Disabled - Protection disabled - 0 - - - Enabled - Protection enabled - 1 - - - - - REGION43 - Enable protection for region 43. Write '0' has no effect. - 11 - 11 - - - Disabled - Protection disabled - 0 - - - Enabled - Protection enabled - 1 - - - - - REGION44 - Enable protection for region 44. Write '0' has no effect. - 12 - 12 - - - Disabled - Protection disabled - 0 - - - Enabled - Protection enabled - 1 - - - - - REGION45 - Enable protection for region 45. Write '0' has no effect. - 13 - 13 - - - Disabled - Protection disabled - 0 - - - Enabled - Protection enabled - 1 - - - - - REGION46 - Enable protection for region 46. Write '0' has no effect. - 14 - 14 - - - Disabled - Protection disabled - 0 - - - Enabled - Protection enabled - 1 - - - - - REGION47 - Enable protection for region 47. Write '0' has no effect. - 15 - 15 - - - Disabled - Protection disabled - 0 - - - Enabled - Protection enabled - 1 - - - - - - - DISABLEINDEBUG - Disable protection mechanism in debug mode - 0x608 - read-write - 0x00000001 - - - DISABLEINDEBUG - Disable the protection mechanism for NVM regions while in debug mode. This register will only disable the protection mechanism if the device is in debug mode. - 0 - 0 - - - Disabled - Disabled in debug - 1 - - - Enabled - Enabled in debug - 0 - - - - - - - - - CLOCK - Clock control - 0x40000000 - BPROT - - 0 - 0x1000 - registers - - - POWER_CLOCK - 0 - - CLOCK - 0x20 - - - TASKS_HFCLKSTART - Start HFCLK crystal oscillator - 0x000 - write-only - - - TASKS_HFCLKSTART - Start HFCLK crystal oscillator - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_HFCLKSTOP - Stop HFCLK crystal oscillator - 0x004 - write-only - - - TASKS_HFCLKSTOP - Stop HFCLK crystal oscillator - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_LFCLKSTART - Start LFCLK source - 0x008 - write-only - - - TASKS_LFCLKSTART - Start LFCLK source - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_LFCLKSTOP - Stop LFCLK source - 0x00C - write-only - - - TASKS_LFCLKSTOP - Stop LFCLK source - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_CAL - Start calibration of LFRC oscillator - 0x010 - write-only - - - TASKS_CAL - Start calibration of LFRC oscillator - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_CTSTART - Start calibration timer - 0x014 - write-only - - - TASKS_CTSTART - Start calibration timer - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_CTSTOP - Stop calibration timer - 0x018 - write-only - - - TASKS_CTSTOP - Stop calibration timer - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - EVENTS_HFCLKSTARTED - HFCLK oscillator started - 0x100 - read-write - - - EVENTS_HFCLKSTARTED - HFCLK oscillator started - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_LFCLKSTARTED - LFCLK started - 0x104 - read-write - - - EVENTS_LFCLKSTARTED - LFCLK started - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_DONE - Calibration of LFCLK RC oscillator complete event - 0x10C - read-write - - - EVENTS_DONE - Calibration of LFCLK RC oscillator complete event - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_CTTO - Calibration timer timeout - 0x110 - read-write - - - EVENTS_CTTO - Calibration timer timeout - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - HFCLKSTARTED - Write '1' to enable interrupt for event HFCLKSTARTED - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - LFCLKSTARTED - Write '1' to enable interrupt for event LFCLKSTARTED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - DONE - Write '1' to enable interrupt for event DONE - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CTTO - Write '1' to enable interrupt for event CTTO - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - HFCLKSTARTED - Write '1' to disable interrupt for event HFCLKSTARTED - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - LFCLKSTARTED - Write '1' to disable interrupt for event LFCLKSTARTED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - DONE - Write '1' to disable interrupt for event DONE - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CTTO - Write '1' to disable interrupt for event CTTO - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - HFCLKRUN - Status indicating that HFCLKSTART task has been triggered - 0x408 - read-only - - - STATUS - HFCLKSTART task triggered or not - 0 - 0 - - - NotTriggered - Task not triggered - 0 - - - Triggered - Task triggered - 1 - - - - - - - HFCLKSTAT - HFCLK status - 0x40C - read-only - - - SRC - Source of HFCLK - 0 - 0 - - - RC - 64 MHz internal oscillator (HFINT) - 0 - - - Xtal - 64 MHz crystal oscillator (HFXO) - 1 - - - - - STATE - HFCLK state - 16 - 16 - - - NotRunning - HFCLK not running - 0 - - - Running - HFCLK running - 1 - - - - - - - LFCLKRUN - Status indicating that LFCLKSTART task has been triggered - 0x414 - read-only - - - STATUS - LFCLKSTART task triggered or not - 0 - 0 - - - NotTriggered - Task not triggered - 0 - - - Triggered - Task triggered - 1 - - - - - - - LFCLKSTAT - LFCLK status - 0x418 - read-only - - - SRC - Source of LFCLK - 0 - 1 - - - RC - 32.768 kHz RC oscillator - 0 - - - Xtal - 32.768 kHz crystal oscillator - 1 - - - Synth - 32.768 kHz synthesized from HFCLK - 2 - - - - - STATE - LFCLK state - 16 - 16 - - - NotRunning - LFCLK not running - 0 - - - Running - LFCLK running - 1 - - - - - - - LFCLKSRCCOPY - Copy of LFCLKSRC register, set when LFCLKSTART task was triggered - 0x41C - read-only - - - SRC - Clock source - 0 - 1 - - - RC - 32.768 kHz RC oscillator - 0 - - - Xtal - 32.768 kHz crystal oscillator - 1 - - - Synth - 32.768 kHz synthesized from HFCLK - 2 - - - - - - - LFCLKSRC - Clock source for the LFCLK - 0x518 - read-write - - - SRC - Clock source - 0 - 1 - - - RC - 32.768 kHz RC oscillator - 0 - - - Xtal - 32.768 kHz crystal oscillator - 1 - - - Synth - 32.768 kHz synthesized from HFCLK - 2 - - - - - BYPASS - Enable or disable bypass of LFCLK crystal oscillator with external clock source - 16 - 16 - - - Disabled - Disable (use with Xtal or low-swing external source) - 0 - - - Enabled - Enable (use with rail-to-rail external source) - 1 - - - - - EXTERNAL - Enable or disable external source for LFCLK - 17 - 17 - - - Disabled - Disable external source (use with Xtal) - 0 - - - Enabled - Enable use of external source instead of Xtal (SRC needs to be set to Xtal) - 1 - - - - - - - CTIV - Calibration timer interval - 0x538 - read-write - - - CTIV - Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. - 0 - 6 - - - - - - - POWER - Power control - 0x40000000 - BPROT - - 0 - 0x1000 - registers - - - POWER_CLOCK - 0 - - POWER - 0x20 - - - TASKS_CONSTLAT - Enable Constant Latency mode - 0x078 - write-only - - - TASKS_CONSTLAT - Enable Constant Latency mode - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_LOWPWR - Enable Low-power mode (variable latency) - 0x07C - write-only - - - TASKS_LOWPWR - Enable Low-power mode (variable latency) - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - EVENTS_POFWARN - Power failure warning - 0x108 - read-write - - - EVENTS_POFWARN - Power failure warning - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_SLEEPENTER - CPU entered WFI/WFE sleep - 0x114 - read-write - - - EVENTS_SLEEPENTER - CPU entered WFI/WFE sleep - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_SLEEPEXIT - CPU exited WFI/WFE sleep - 0x118 - read-write - - - EVENTS_SLEEPEXIT - CPU exited WFI/WFE sleep - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - POFWARN - Write '1' to enable interrupt for event POFWARN - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - SLEEPENTER - Write '1' to enable interrupt for event SLEEPENTER - 5 - 5 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - SLEEPEXIT - Write '1' to enable interrupt for event SLEEPEXIT - 6 - 6 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - POFWARN - Write '1' to disable interrupt for event POFWARN - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - SLEEPENTER - Write '1' to disable interrupt for event SLEEPENTER - 5 - 5 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - SLEEPEXIT - Write '1' to disable interrupt for event SLEEPEXIT - 6 - 6 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - RESETREAS - Reset reason - 0x400 - read-write - - - RESETPIN - Reset from pin-reset detected - 0 - 0 - - - NotDetected - Not detected - 0 - - - Detected - Detected - 1 - - - - - DOG - Reset from watchdog detected - 1 - 1 - - - NotDetected - Not detected - 0 - - - Detected - Detected - 1 - - - - - SREQ - Reset from soft reset detected - 2 - 2 - - - NotDetected - Not detected - 0 - - - Detected - Detected - 1 - - - - - LOCKUP - Reset from CPU lock-up detected - 3 - 3 - - - NotDetected - Not detected - 0 - - - Detected - Detected - 1 - - - - - OFF - Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO - 16 - 16 - - - NotDetected - Not detected - 0 - - - Detected - Detected - 1 - - - - - DIF - Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode - 18 - 18 - - - NotDetected - Not detected - 0 - - - Detected - Detected - 1 - - - - - - - SYSTEMOFF - System OFF register - 0x500 - write-only - - - SYSTEMOFF - Enable System OFF mode - 0 - 0 - - - Enter - Enable System OFF mode - 1 - - - - - - - POFCON - Power failure comparator configuration - 0x510 - read-write - - - POF - Enable or disable power failure comparator - 0 - 0 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - THRESHOLD - Power failure comparator threshold setting - 1 - 4 - - - V17 - Set threshold to 1.7 V - 4 - - - V18 - Set threshold to 1.8 V - 5 - - - V19 - Set threshold to 1.9 V - 6 - - - V20 - Set threshold to 2.0 V - 7 - - - V21 - Set threshold to 2.1 V - 8 - - - V22 - Set threshold to 2.2 V - 9 - - - V23 - Set threshold to 2.3 V - 10 - - - V24 - Set threshold to 2.4 V - 11 - - - V25 - Set threshold to 2.5 V - 12 - - - V26 - Set threshold to 2.6 V - 13 - - - V27 - Set threshold to 2.7 V - 14 - - - V28 - Set threshold to 2.8 V - 15 - - - - - - - GPREGRET - General purpose retention register - 0x51C - read-write - - - GPREGRET - General purpose retention register - 0 - 7 - - - - - GPREGRET2 - General purpose retention register - 0x520 - read-write - - - GPREGRET - General purpose retention register - 0 - 7 - - - - - DCDCEN - DC/DC enable register - 0x578 - read-write - - - DCDCEN - Enable or disable DC/DC converter - 0 - 0 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - 8 - 0x010 - RAM[%s] - Unspecified - POWER_RAM - read-write - 0x900 - - POWER - Description cluster: RAMn power control register. The RAM size will vary depending on product variant, and the RAMn register will only be present if the corresponding RAM AHB slave is present on the device. - 0x000 - read-write - 0x0000FFFF - - - S0POWER - Keep RAM section S0 ON or OFF in System ON mode. - 0 - 0 - - - Off - Off - 0 - - - On - On - 1 - - - - - S1POWER - Keep RAM section S1 ON or OFF in System ON mode. - 1 - 1 - - - Off - Off - 0 - - - On - On - 1 - - - - - S0RETENTION - Keep retention on RAM section S0 when RAM section is in OFF - 16 - 16 - - - Off - Off - 0 - - - On - On - 1 - - - - - S1RETENTION - Keep retention on RAM section S1 when RAM section is in OFF - 17 - 17 - - - Off - Off - 0 - - - On - On - 1 - - - - - - - POWERSET - Description cluster: RAMn power control set register - 0x004 - write-only - 0x0000FFFF - - - S0POWER - Keep RAM section S0 of RAMn on or off in System ON mode - 0 - 0 - - - On - On - 1 - - - - - S1POWER - Keep RAM section S1 of RAMn on or off in System ON mode - 1 - 1 - - - On - On - 1 - - - - - S0RETENTION - Keep retention on RAM section S0 when RAM section is switched off - 16 - 16 - - - On - On - 1 - - - - - S1RETENTION - Keep retention on RAM section S1 when RAM section is switched off - 17 - 17 - - - On - On - 1 - - - - - - - POWERCLR - Description cluster: RAMn power control clear register - 0x008 - write-only - 0x0000FFFF - - - S0POWER - Keep RAM section S0 of RAMn on or off in System ON mode - 0 - 0 - - - Off - Off - 1 - - - - - S1POWER - Keep RAM section S1 of RAMn on or off in System ON mode - 1 - 1 - - - Off - Off - 1 - - - - - S0RETENTION - Keep retention on RAM section S0 when RAM section is switched off - 16 - 16 - - - Off - Off - 1 - - - - - S1RETENTION - Keep retention on RAM section S1 when RAM section is switched off - 17 - 17 - - - Off - Off - 1 - - - - - - - - - - P0 - GPIO Port - 0x50000000 - GPIO - - 0 - 0x1000 - registers - - GPIO - 0x20 - - - OUT - Write GPIO port - 0x504 - read-write - - - PIN0 - Pin 0 - 0 - 0 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN1 - Pin 1 - 1 - 1 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN2 - Pin 2 - 2 - 2 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN3 - Pin 3 - 3 - 3 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN4 - Pin 4 - 4 - 4 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN5 - Pin 5 - 5 - 5 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN6 - Pin 6 - 6 - 6 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN7 - Pin 7 - 7 - 7 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN8 - Pin 8 - 8 - 8 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN9 - Pin 9 - 9 - 9 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN10 - Pin 10 - 10 - 10 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN11 - Pin 11 - 11 - 11 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN12 - Pin 12 - 12 - 12 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN13 - Pin 13 - 13 - 13 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN14 - Pin 14 - 14 - 14 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN15 - Pin 15 - 15 - 15 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN16 - Pin 16 - 16 - 16 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN17 - Pin 17 - 17 - 17 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN18 - Pin 18 - 18 - 18 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN19 - Pin 19 - 19 - 19 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN20 - Pin 20 - 20 - 20 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN21 - Pin 21 - 21 - 21 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN22 - Pin 22 - 22 - 22 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN23 - Pin 23 - 23 - 23 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN24 - Pin 24 - 24 - 24 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN25 - Pin 25 - 25 - 25 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN26 - Pin 26 - 26 - 26 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN27 - Pin 27 - 27 - 27 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN28 - Pin 28 - 28 - 28 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN29 - Pin 29 - 29 - 29 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN30 - Pin 30 - 30 - 30 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN31 - Pin 31 - 31 - 31 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - - - OUTSET - Set individual bits in GPIO port - 0x508 - read-write - oneToSet - - - PIN0 - Pin 0 - 0 - 0 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN1 - Pin 1 - 1 - 1 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN2 - Pin 2 - 2 - 2 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN3 - Pin 3 - 3 - 3 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN4 - Pin 4 - 4 - 4 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN5 - Pin 5 - 5 - 5 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN6 - Pin 6 - 6 - 6 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN7 - Pin 7 - 7 - 7 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN8 - Pin 8 - 8 - 8 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN9 - Pin 9 - 9 - 9 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN10 - Pin 10 - 10 - 10 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN11 - Pin 11 - 11 - 11 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN12 - Pin 12 - 12 - 12 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN13 - Pin 13 - 13 - 13 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN14 - Pin 14 - 14 - 14 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN15 - Pin 15 - 15 - 15 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN16 - Pin 16 - 16 - 16 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN17 - Pin 17 - 17 - 17 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN18 - Pin 18 - 18 - 18 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN19 - Pin 19 - 19 - 19 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN20 - Pin 20 - 20 - 20 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN21 - Pin 21 - 21 - 21 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN22 - Pin 22 - 22 - 22 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN23 - Pin 23 - 23 - 23 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN24 - Pin 24 - 24 - 24 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN25 - Pin 25 - 25 - 25 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN26 - Pin 26 - 26 - 26 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN27 - Pin 27 - 27 - 27 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN28 - Pin 28 - 28 - 28 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN29 - Pin 29 - 29 - 29 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN30 - Pin 30 - 30 - 30 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN31 - Pin 31 - 31 - 31 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - - - OUTCLR - Clear individual bits in GPIO port - 0x50C - read-write - oneToClear - - - PIN0 - Pin 0 - 0 - 0 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN1 - Pin 1 - 1 - 1 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN2 - Pin 2 - 2 - 2 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN3 - Pin 3 - 3 - 3 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN4 - Pin 4 - 4 - 4 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN5 - Pin 5 - 5 - 5 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN6 - Pin 6 - 6 - 6 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN7 - Pin 7 - 7 - 7 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN8 - Pin 8 - 8 - 8 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN9 - Pin 9 - 9 - 9 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN10 - Pin 10 - 10 - 10 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN11 - Pin 11 - 11 - 11 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN12 - Pin 12 - 12 - 12 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN13 - Pin 13 - 13 - 13 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN14 - Pin 14 - 14 - 14 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN15 - Pin 15 - 15 - 15 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN16 - Pin 16 - 16 - 16 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN17 - Pin 17 - 17 - 17 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN18 - Pin 18 - 18 - 18 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN19 - Pin 19 - 19 - 19 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN20 - Pin 20 - 20 - 20 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN21 - Pin 21 - 21 - 21 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN22 - Pin 22 - 22 - 22 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN23 - Pin 23 - 23 - 23 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN24 - Pin 24 - 24 - 24 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN25 - Pin 25 - 25 - 25 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN26 - Pin 26 - 26 - 26 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN27 - Pin 27 - 27 - 27 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN28 - Pin 28 - 28 - 28 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN29 - Pin 29 - 29 - 29 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN30 - Pin 30 - 30 - 30 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN31 - Pin 31 - 31 - 31 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - - - IN - Read GPIO port - 0x510 - read-only - - - PIN0 - Pin 0 - 0 - 0 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN1 - Pin 1 - 1 - 1 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN2 - Pin 2 - 2 - 2 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN3 - Pin 3 - 3 - 3 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN4 - Pin 4 - 4 - 4 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN5 - Pin 5 - 5 - 5 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN6 - Pin 6 - 6 - 6 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN7 - Pin 7 - 7 - 7 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN8 - Pin 8 - 8 - 8 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN9 - Pin 9 - 9 - 9 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN10 - Pin 10 - 10 - 10 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN11 - Pin 11 - 11 - 11 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN12 - Pin 12 - 12 - 12 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN13 - Pin 13 - 13 - 13 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN14 - Pin 14 - 14 - 14 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN15 - Pin 15 - 15 - 15 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN16 - Pin 16 - 16 - 16 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN17 - Pin 17 - 17 - 17 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN18 - Pin 18 - 18 - 18 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN19 - Pin 19 - 19 - 19 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN20 - Pin 20 - 20 - 20 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN21 - Pin 21 - 21 - 21 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN22 - Pin 22 - 22 - 22 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN23 - Pin 23 - 23 - 23 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN24 - Pin 24 - 24 - 24 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN25 - Pin 25 - 25 - 25 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN26 - Pin 26 - 26 - 26 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN27 - Pin 27 - 27 - 27 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN28 - Pin 28 - 28 - 28 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN29 - Pin 29 - 29 - 29 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN30 - Pin 30 - 30 - 30 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN31 - Pin 31 - 31 - 31 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - - - DIR - Direction of GPIO pins - 0x514 - read-write - - - PIN0 - Pin 0 - 0 - 0 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN1 - Pin 1 - 1 - 1 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN2 - Pin 2 - 2 - 2 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN3 - Pin 3 - 3 - 3 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN4 - Pin 4 - 4 - 4 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN5 - Pin 5 - 5 - 5 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN6 - Pin 6 - 6 - 6 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN7 - Pin 7 - 7 - 7 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN8 - Pin 8 - 8 - 8 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN9 - Pin 9 - 9 - 9 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN10 - Pin 10 - 10 - 10 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN11 - Pin 11 - 11 - 11 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN12 - Pin 12 - 12 - 12 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN13 - Pin 13 - 13 - 13 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN14 - Pin 14 - 14 - 14 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN15 - Pin 15 - 15 - 15 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN16 - Pin 16 - 16 - 16 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN17 - Pin 17 - 17 - 17 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN18 - Pin 18 - 18 - 18 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN19 - Pin 19 - 19 - 19 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN20 - Pin 20 - 20 - 20 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN21 - Pin 21 - 21 - 21 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN22 - Pin 22 - 22 - 22 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN23 - Pin 23 - 23 - 23 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN24 - Pin 24 - 24 - 24 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN25 - Pin 25 - 25 - 25 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN26 - Pin 26 - 26 - 26 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN27 - Pin 27 - 27 - 27 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN28 - Pin 28 - 28 - 28 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN29 - Pin 29 - 29 - 29 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN30 - Pin 30 - 30 - 30 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN31 - Pin 31 - 31 - 31 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - - - DIRSET - DIR set register - 0x518 - read-write - oneToSet - - - PIN0 - Set as output pin 0 - 0 - 0 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN1 - Set as output pin 1 - 1 - 1 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN2 - Set as output pin 2 - 2 - 2 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN3 - Set as output pin 3 - 3 - 3 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN4 - Set as output pin 4 - 4 - 4 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN5 - Set as output pin 5 - 5 - 5 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN6 - Set as output pin 6 - 6 - 6 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN7 - Set as output pin 7 - 7 - 7 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN8 - Set as output pin 8 - 8 - 8 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN9 - Set as output pin 9 - 9 - 9 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN10 - Set as output pin 10 - 10 - 10 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN11 - Set as output pin 11 - 11 - 11 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN12 - Set as output pin 12 - 12 - 12 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN13 - Set as output pin 13 - 13 - 13 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN14 - Set as output pin 14 - 14 - 14 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN15 - Set as output pin 15 - 15 - 15 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN16 - Set as output pin 16 - 16 - 16 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN17 - Set as output pin 17 - 17 - 17 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN18 - Set as output pin 18 - 18 - 18 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN19 - Set as output pin 19 - 19 - 19 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN20 - Set as output pin 20 - 20 - 20 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN21 - Set as output pin 21 - 21 - 21 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN22 - Set as output pin 22 - 22 - 22 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN23 - Set as output pin 23 - 23 - 23 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN24 - Set as output pin 24 - 24 - 24 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN25 - Set as output pin 25 - 25 - 25 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN26 - Set as output pin 26 - 26 - 26 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN27 - Set as output pin 27 - 27 - 27 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN28 - Set as output pin 28 - 28 - 28 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN29 - Set as output pin 29 - 29 - 29 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN30 - Set as output pin 30 - 30 - 30 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN31 - Set as output pin 31 - 31 - 31 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - - - DIRCLR - DIR clear register - 0x51C - read-write - oneToClear - - - PIN0 - Set as input pin 0 - 0 - 0 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN1 - Set as input pin 1 - 1 - 1 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN2 - Set as input pin 2 - 2 - 2 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN3 - Set as input pin 3 - 3 - 3 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN4 - Set as input pin 4 - 4 - 4 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN5 - Set as input pin 5 - 5 - 5 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN6 - Set as input pin 6 - 6 - 6 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN7 - Set as input pin 7 - 7 - 7 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN8 - Set as input pin 8 - 8 - 8 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN9 - Set as input pin 9 - 9 - 9 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN10 - Set as input pin 10 - 10 - 10 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN11 - Set as input pin 11 - 11 - 11 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN12 - Set as input pin 12 - 12 - 12 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN13 - Set as input pin 13 - 13 - 13 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN14 - Set as input pin 14 - 14 - 14 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN15 - Set as input pin 15 - 15 - 15 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN16 - Set as input pin 16 - 16 - 16 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN17 - Set as input pin 17 - 17 - 17 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN18 - Set as input pin 18 - 18 - 18 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN19 - Set as input pin 19 - 19 - 19 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN20 - Set as input pin 20 - 20 - 20 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN21 - Set as input pin 21 - 21 - 21 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN22 - Set as input pin 22 - 22 - 22 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN23 - Set as input pin 23 - 23 - 23 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN24 - Set as input pin 24 - 24 - 24 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN25 - Set as input pin 25 - 25 - 25 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN26 - Set as input pin 26 - 26 - 26 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN27 - Set as input pin 27 - 27 - 27 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN28 - Set as input pin 28 - 28 - 28 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN29 - Set as input pin 29 - 29 - 29 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN30 - Set as input pin 30 - 30 - 30 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN31 - Set as input pin 31 - 31 - 31 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - - - LATCH - Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers - 0x520 - read-write - - - PIN0 - Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. - 0 - 0 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN1 - Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. - 1 - 1 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN2 - Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. - 2 - 2 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN3 - Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. - 3 - 3 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN4 - Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. - 4 - 4 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN5 - Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. - 5 - 5 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN6 - Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. - 6 - 6 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN7 - Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. - 7 - 7 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN8 - Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. - 8 - 8 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN9 - Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. - 9 - 9 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN10 - Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. - 10 - 10 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN11 - Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. - 11 - 11 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN12 - Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. - 12 - 12 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN13 - Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. - 13 - 13 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN14 - Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. - 14 - 14 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN15 - Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. - 15 - 15 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN16 - Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. - 16 - 16 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN17 - Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. - 17 - 17 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN18 - Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. - 18 - 18 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN19 - Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. - 19 - 19 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN20 - Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. - 20 - 20 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN21 - Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. - 21 - 21 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN22 - Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. - 22 - 22 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN23 - Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. - 23 - 23 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN24 - Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. - 24 - 24 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN25 - Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. - 25 - 25 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN26 - Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. - 26 - 26 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN27 - Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. - 27 - 27 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN28 - Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. - 28 - 28 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN29 - Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. - 29 - 29 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN30 - Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. - 30 - 30 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN31 - Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. - 31 - 31 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - - - DETECTMODE - Select between default DETECT signal behaviour and LDETECT mode - 0x524 - read-write - - - DETECTMODE - Select between default DETECT signal behaviour and LDETECT mode - 0 - 0 - - - Default - DETECT directly connected to PIN DETECT signals - 0 - - - LDETECT - Use the latched LDETECT behaviour - 1 - - - - - - - 0x20 - 0x4 - PIN_CNF[%s] - Description collection: Configuration of GPIO pins - 0x700 - read-write - 0x00000002 - - - DIR - Pin direction. Same physical register as DIR register - 0 - 0 - - - Input - Configure pin as an input pin - 0 - - - Output - Configure pin as an output pin - 1 - - - - - INPUT - Connect or disconnect input buffer - 1 - 1 - - - Connect - Connect input buffer - 0 - - - Disconnect - Disconnect input buffer - 1 - - - - - PULL - Pull configuration - 2 - 3 - - - Disabled - No pull - 0 - - - Pulldown - Pull down on pin - 1 - - - Pullup - Pull up on pin - 3 - - - - - DRIVE - Drive configuration - 8 - 10 - - - S0S1 - Standard '0', standard '1' - 0 - - - H0S1 - High drive '0', standard '1' - 1 - - - S0H1 - Standard '0', high drive '1' - 2 - - - H0H1 - High drive '0', high 'drive '1'' - 3 - - - D0S1 - Disconnect '0' standard '1' (normally used for wired-or connections) - 4 - - - D0H1 - Disconnect '0', high drive '1' (normally used for wired-or connections) - 5 - - - S0D1 - Standard '0'. disconnect '1' (normally used for wired-and connections) - 6 - - - H0D1 - High drive '0', disconnect '1' (normally used for wired-and connections) - 7 - - - - - SENSE - Pin sensing mechanism - 16 - 17 - - - Disabled - Disabled - 0 - - - High - Sense for high level - 2 - - - Low - Sense for low level - 3 - - - - - - - - - RADIO - 2.4 GHz radio - 0x40001000 - - 0 - 0x1000 - registers - - - RADIO - 1 - - RADIO - 0x20 - - - TASKS_TXEN - Enable RADIO in TX mode - 0x000 - write-only - - - TASKS_TXEN - Enable RADIO in TX mode - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_RXEN - Enable RADIO in RX mode - 0x004 - write-only - - - TASKS_RXEN - Enable RADIO in RX mode - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_START - Start RADIO - 0x008 - write-only - - - TASKS_START - Start RADIO - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STOP - Stop RADIO - 0x00C - write-only - - - TASKS_STOP - Stop RADIO - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_DISABLE - Disable RADIO - 0x010 - write-only - - - TASKS_DISABLE - Disable RADIO - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_RSSISTART - Start the RSSI and take one single sample of the receive signal strength - 0x014 - write-only - - - TASKS_RSSISTART - Start the RSSI and take one single sample of the receive signal strength - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_RSSISTOP - Stop the RSSI measurement - 0x018 - write-only - - - TASKS_RSSISTOP - Stop the RSSI measurement - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_BCSTART - Start the bit counter - 0x01C - write-only - - - TASKS_BCSTART - Start the bit counter - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_BCSTOP - Stop the bit counter - 0x020 - write-only - - - TASKS_BCSTOP - Stop the bit counter - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_EDSTART - Start the energy detect measurement used in IEEE 802.15.4 mode - 0x024 - write-only - - - TASKS_EDSTART - Start the energy detect measurement used in IEEE 802.15.4 mode - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_EDSTOP - Stop the energy detect measurement - 0x028 - write-only - - - TASKS_EDSTOP - Stop the energy detect measurement - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_CCASTART - Start the clear channel assessment used in IEEE 802.15.4 mode - 0x02C - write-only - - - TASKS_CCASTART - Start the clear channel assessment used in IEEE 802.15.4 mode - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_CCASTOP - Stop the clear channel assessment - 0x030 - write-only - - - TASKS_CCASTOP - Stop the clear channel assessment - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - EVENTS_READY - RADIO has ramped up and is ready to be started - 0x100 - read-write - - - EVENTS_READY - RADIO has ramped up and is ready to be started - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_ADDRESS - Address sent or received - 0x104 - read-write - - - EVENTS_ADDRESS - Address sent or received - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_PAYLOAD - Packet payload sent or received - 0x108 - read-write - - - EVENTS_PAYLOAD - Packet payload sent or received - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_END - Packet sent or received - 0x10C - read-write - - - EVENTS_END - Packet sent or received - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_DISABLED - RADIO has been disabled - 0x110 - read-write - - - EVENTS_DISABLED - RADIO has been disabled - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_DEVMATCH - A device address match occurred on the last received packet - 0x114 - read-write - - - EVENTS_DEVMATCH - A device address match occurred on the last received packet - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_DEVMISS - No device address match occurred on the last received packet - 0x118 - read-write - - - EVENTS_DEVMISS - No device address match occurred on the last received packet - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_RSSIEND - Sampling of receive signal strength complete - 0x11C - read-write - - - EVENTS_RSSIEND - Sampling of receive signal strength complete - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_BCMATCH - Bit counter reached bit count value - 0x128 - read-write - - - EVENTS_BCMATCH - Bit counter reached bit count value - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_CRCOK - Packet received with CRC ok - 0x130 - read-write - - - EVENTS_CRCOK - Packet received with CRC ok - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_CRCERROR - Packet received with CRC error - 0x134 - read-write - - - EVENTS_CRCERROR - Packet received with CRC error - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_FRAMESTART - IEEE 802.15.4 length field received - 0x138 - read-write - - - EVENTS_FRAMESTART - IEEE 802.15.4 length field received - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_EDEND - Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register - 0x13C - read-write - - - EVENTS_EDEND - Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_EDSTOPPED - The sampling of energy detection has stopped - 0x140 - read-write - - - EVENTS_EDSTOPPED - The sampling of energy detection has stopped - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_CCAIDLE - Wireless medium in idle - clear to send - 0x144 - read-write - - - EVENTS_CCAIDLE - Wireless medium in idle - clear to send - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_CCABUSY - Wireless medium busy - do not send - 0x148 - read-write - - - EVENTS_CCABUSY - Wireless medium busy - do not send - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_CCASTOPPED - The CCA has stopped - 0x14C - read-write - - - EVENTS_CCASTOPPED - The CCA has stopped - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_RATEBOOST - Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. - 0x150 - read-write - - - EVENTS_RATEBOOST - Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_TXREADY - RADIO has ramped up and is ready to be started TX path - 0x154 - read-write - - - EVENTS_TXREADY - RADIO has ramped up and is ready to be started TX path - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_RXREADY - RADIO has ramped up and is ready to be started RX path - 0x158 - read-write - - - EVENTS_RXREADY - RADIO has ramped up and is ready to be started RX path - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_MHRMATCH - MAC header match found - 0x15C - read-write - - - EVENTS_MHRMATCH - MAC header match found - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_PHYEND - Generated when last bit is sent on air - 0x16C - read-write - - - EVENTS_PHYEND - Generated when last bit is sent on air - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_CTEPRESENT - CTE is present (early warning right after receiving CTEInfo byte) - 0x170 - read-write - - - EVENTS_CTEPRESENT - CTE is present (early warning right after receiving CTEInfo byte) - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - SHORTS - Shortcuts between local events and tasks - 0x200 - read-write - - - READY_START - Shortcut between event READY and task START - 0 - 0 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - END_DISABLE - Shortcut between event END and task DISABLE - 1 - 1 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - DISABLED_TXEN - Shortcut between event DISABLED and task TXEN - 2 - 2 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - DISABLED_RXEN - Shortcut between event DISABLED and task RXEN - 3 - 3 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - ADDRESS_RSSISTART - Shortcut between event ADDRESS and task RSSISTART - 4 - 4 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - END_START - Shortcut between event END and task START - 5 - 5 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - ADDRESS_BCSTART - Shortcut between event ADDRESS and task BCSTART - 6 - 6 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - DISABLED_RSSISTOP - Shortcut between event DISABLED and task RSSISTOP - 8 - 8 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - RXREADY_CCASTART - Shortcut between event RXREADY and task CCASTART - 11 - 11 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - CCAIDLE_TXEN - Shortcut between event CCAIDLE and task TXEN - 12 - 12 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - CCABUSY_DISABLE - Shortcut between event CCABUSY and task DISABLE - 13 - 13 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - FRAMESTART_BCSTART - Shortcut between event FRAMESTART and task BCSTART - 14 - 14 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - READY_EDSTART - Shortcut between event READY and task EDSTART - 15 - 15 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - EDEND_DISABLE - Shortcut between event EDEND and task DISABLE - 16 - 16 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - CCAIDLE_STOP - Shortcut between event CCAIDLE and task STOP - 17 - 17 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - TXREADY_START - Shortcut between event TXREADY and task START - 18 - 18 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - RXREADY_START - Shortcut between event RXREADY and task START - 19 - 19 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - PHYEND_DISABLE - Shortcut between event PHYEND and task DISABLE - 20 - 20 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - PHYEND_START - Shortcut between event PHYEND and task START - 21 - 21 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - READY - Write '1' to enable interrupt for event READY - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ADDRESS - Write '1' to enable interrupt for event ADDRESS - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - PAYLOAD - Write '1' to enable interrupt for event PAYLOAD - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - END - Write '1' to enable interrupt for event END - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - DISABLED - Write '1' to enable interrupt for event DISABLED - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - DEVMATCH - Write '1' to enable interrupt for event DEVMATCH - 5 - 5 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - DEVMISS - Write '1' to enable interrupt for event DEVMISS - 6 - 6 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RSSIEND - Write '1' to enable interrupt for event RSSIEND - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - BCMATCH - Write '1' to enable interrupt for event BCMATCH - 10 - 10 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CRCOK - Write '1' to enable interrupt for event CRCOK - 12 - 12 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CRCERROR - Write '1' to enable interrupt for event CRCERROR - 13 - 13 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - FRAMESTART - Write '1' to enable interrupt for event FRAMESTART - 14 - 14 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - EDEND - Write '1' to enable interrupt for event EDEND - 15 - 15 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - EDSTOPPED - Write '1' to enable interrupt for event EDSTOPPED - 16 - 16 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CCAIDLE - Write '1' to enable interrupt for event CCAIDLE - 17 - 17 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CCABUSY - Write '1' to enable interrupt for event CCABUSY - 18 - 18 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CCASTOPPED - Write '1' to enable interrupt for event CCASTOPPED - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RATEBOOST - Write '1' to enable interrupt for event RATEBOOST - 20 - 20 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TXREADY - Write '1' to enable interrupt for event TXREADY - 21 - 21 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RXREADY - Write '1' to enable interrupt for event RXREADY - 22 - 22 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - MHRMATCH - Write '1' to enable interrupt for event MHRMATCH - 23 - 23 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - PHYEND - Write '1' to enable interrupt for event PHYEND - 27 - 27 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CTEPRESENT - Write '1' to enable interrupt for event CTEPRESENT - 28 - 28 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - READY - Write '1' to disable interrupt for event READY - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ADDRESS - Write '1' to disable interrupt for event ADDRESS - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - PAYLOAD - Write '1' to disable interrupt for event PAYLOAD - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - END - Write '1' to disable interrupt for event END - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - DISABLED - Write '1' to disable interrupt for event DISABLED - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - DEVMATCH - Write '1' to disable interrupt for event DEVMATCH - 5 - 5 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - DEVMISS - Write '1' to disable interrupt for event DEVMISS - 6 - 6 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RSSIEND - Write '1' to disable interrupt for event RSSIEND - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - BCMATCH - Write '1' to disable interrupt for event BCMATCH - 10 - 10 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CRCOK - Write '1' to disable interrupt for event CRCOK - 12 - 12 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CRCERROR - Write '1' to disable interrupt for event CRCERROR - 13 - 13 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - FRAMESTART - Write '1' to disable interrupt for event FRAMESTART - 14 - 14 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - EDEND - Write '1' to disable interrupt for event EDEND - 15 - 15 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - EDSTOPPED - Write '1' to disable interrupt for event EDSTOPPED - 16 - 16 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CCAIDLE - Write '1' to disable interrupt for event CCAIDLE - 17 - 17 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CCABUSY - Write '1' to disable interrupt for event CCABUSY - 18 - 18 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CCASTOPPED - Write '1' to disable interrupt for event CCASTOPPED - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RATEBOOST - Write '1' to disable interrupt for event RATEBOOST - 20 - 20 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TXREADY - Write '1' to disable interrupt for event TXREADY - 21 - 21 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RXREADY - Write '1' to disable interrupt for event RXREADY - 22 - 22 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - MHRMATCH - Write '1' to disable interrupt for event MHRMATCH - 23 - 23 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - PHYEND - Write '1' to disable interrupt for event PHYEND - 27 - 27 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CTEPRESENT - Write '1' to disable interrupt for event CTEPRESENT - 28 - 28 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - CRCSTATUS - CRC status - 0x400 - read-only - - - CRCSTATUS - CRC status of packet received - 0 - 0 - - - CRCError - Packet received with CRC error - 0 - - - CRCOk - Packet received with CRC ok - 1 - - - - - - - RXMATCH - Received address - 0x408 - read-only - - - RXMATCH - Received address - 0 - 2 - - - - - RXCRC - CRC field of previously received packet - 0x40C - read-only - - - RXCRC - CRC field of previously received packet - 0 - 23 - - - - - DAI - Device address match index - 0x410 - read-only - - - DAI - Device address match index - 0 - 2 - - - - - PDUSTAT - Payload status - 0x414 - read-only - - - PDUSTAT - Status on payload length vs. PCNF1.MAXLEN - 0 - 0 - - - LessThan - Payload less than PCNF1.MAXLEN - 0 - - - GreaterThan - Payload greater than PCNF1.MAXLEN - 1 - - - - - CISTAT - Status on what rate packet is received with in Long Range - 1 - 2 - - - LR125kbit - Frame is received at 125kbps - 0 - - - LR500kbit - Frame is received at 500kbps - 1 - - - - - - - CTESTATUS - CTEInfo parsed from received packet - 0x44C - read-only - - - CTETIME - CTETime parsed from packet - 0 - 4 - - - RFU - RFU parsed from packet - 5 - 5 - - - CTETYPE - CTEType parsed from packet - 6 - 7 - - - - - DFESTATUS - DFE status information - 0x458 - read-only - - - SWITCHINGSTATE - Internal state of switching state machine - 0 - 2 - - - Idle - Switching state Idle - 0 - - - Offset - Switching state Offset - 1 - - - Guard - Switching state Guard - 2 - - - Ref - Switching state Ref - 3 - - - Switching - Switching state Switching - 4 - - - Ending - Switching state Ending - 5 - - - - - SAMPLINGSTATE - Internal state of sampling state machine - 4 - 4 - - - Idle - Sampling state Idle - 0 - - - Sampling - Sampling state Sampling - 1 - - - - - - - PACKETPTR - Packet pointer - 0x504 - read-write - 0x00000000 - - - PACKETPTR - Packet pointer - 0 - 31 - - - - - FREQUENCY - Frequency - 0x508 - read-write - 0x00000002 - - - FREQUENCY - Radio channel frequency - 0 - 6 - - - MAP - Channel map selection. - 8 - 8 - - - Default - Channel map between 2400 MHZ .. 2500 MHz - 0 - - - Low - Channel map between 2360 MHZ .. 2460 MHz - 1 - - - - - - - TXPOWER - Output power - 0x50C - read-write - - - TXPOWER - RADIO output power - 0 - 7 - - - Pos4dBm - +4 dBm - 0x4 - - - Pos3dBm - +3 dBm - 0x3 - - - 0dBm - 0 dBm - 0x0 - - - Neg4dBm - -4 dBm - 0xFC - - - Neg8dBm - -8 dBm - 0xF8 - - - Neg12dBm - -12 dBm - 0xF4 - - - Neg16dBm - -16 dBm - 0xF0 - - - Neg20dBm - -20 dBm - 0xEC - - - Neg30dBm - Deprecated enumerator - -40 dBm - 0xE2 - - - Neg40dBm - -40 dBm - 0xD8 - - - - - - - MODE - Data rate and modulation - 0x510 - read-write - - - MODE - Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation. - 0 - 3 - - - Nrf_1Mbit - 1 Mbps Nordic proprietary radio mode - 0 - - - Nrf_2Mbit - 2 Mbps Nordic proprietary radio mode - 1 - - - Ble_1Mbit - 1 Mbps BLE - 3 - - - Ble_2Mbit - 2 Mbps BLE - 4 - - - Ble_LR125Kbit - Long range 125 kbps TX, 125 kbps and 500 kbps RX - 5 - - - Ble_LR500Kbit - Long range 500 kbps TX, 125 kbps and 500 kbps RX - 6 - - - Ieee802154_250Kbit - IEEE 802.15.4-2006 250 kbps - 15 - - - - - - - PCNF0 - Packet configuration register 0 - 0x514 - read-write - - - LFLEN - Length on air of LENGTH field in number of bits. - 0 - 3 - - - S0LEN - Length on air of S0 field in number of bytes. - 8 - 8 - - - S1LEN - Length on air of S1 field in number of bits. - 16 - 19 - - - S1INCL - Include or exclude S1 field in RAM - 20 - 20 - - - Automatic - Include S1 field in RAM only if S1LEN &gt; 0 - 0 - - - Include - Always include S1 field in RAM independent of S1LEN - 1 - - - - - CILEN - Length of code indicator - long range - 22 - 23 - - - PLEN - Length of preamble on air. Decision point: TASKS_START task - 24 - 25 - - - 8bit - 8-bit preamble - 0 - - - 16bit - 16-bit preamble - 1 - - - 32bitZero - 32-bit zero preamble - used for IEEE 802.15.4 - 2 - - - LongRange - Preamble - used for BLE long range - 3 - - - - - CRCINC - Indicates if LENGTH field contains CRC or not - 26 - 26 - - - Exclude - LENGTH does not contain CRC - 0 - - - Include - LENGTH includes CRC - 1 - - - - - TERMLEN - Length of TERM field in Long Range operation - 29 - 30 - - - - - PCNF1 - Packet configuration register 1 - 0x518 - read-write - - - MAXLEN - Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. - 0 - 7 - - - STATLEN - Static length in number of bytes - 8 - 15 - - - BALEN - Base address length in number of bytes - 16 - 18 - - - ENDIAN - On-air endianness of packet, this applies to the S0, LENGTH, S1, and the PAYLOAD fields. - 24 - 24 - - - Little - Least significant bit on air first - 0 - - - Big - Most significant bit on air first - 1 - - - - - WHITEEN - Enable or disable packet whitening - 25 - 25 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - BASE0 - Base address 0 - 0x51C - read-write - - - BASE0 - Base address 0 - 0 - 31 - - - - - BASE1 - Base address 1 - 0x520 - read-write - - - BASE1 - Base address 1 - 0 - 31 - - - - - PREFIX0 - Prefixes bytes for logical addresses 0-3 - 0x524 - read-write - - - AP0 - Address prefix 0. - 0 - 7 - - - AP1 - Address prefix 1. - 8 - 15 - - - AP2 - Address prefix 2. - 16 - 23 - - - AP3 - Address prefix 3. - 24 - 31 - - - - - PREFIX1 - Prefixes bytes for logical addresses 4-7 - 0x528 - read-write - - - AP4 - Address prefix 4. - 0 - 7 - - - AP5 - Address prefix 5. - 8 - 15 - - - AP6 - Address prefix 6. - 16 - 23 - - - AP7 - Address prefix 7. - 24 - 31 - - - - - TXADDRESS - Transmit address select - 0x52C - read-write - - - TXADDRESS - Transmit address select - 0 - 2 - - - - - RXADDRESSES - Receive address select - 0x530 - read-write - - - ADDR0 - Enable or disable reception on logical address 0. - 0 - 0 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ADDR1 - Enable or disable reception on logical address 1. - 1 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ADDR2 - Enable or disable reception on logical address 2. - 2 - 2 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ADDR3 - Enable or disable reception on logical address 3. - 3 - 3 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ADDR4 - Enable or disable reception on logical address 4. - 4 - 4 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ADDR5 - Enable or disable reception on logical address 5. - 5 - 5 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ADDR6 - Enable or disable reception on logical address 6. - 6 - 6 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ADDR7 - Enable or disable reception on logical address 7. - 7 - 7 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - CRCCNF - CRC configuration - 0x534 - read-write - - - LEN - CRC length in number of bytes. - 0 - 1 - - - Disabled - CRC length is zero and CRC calculation is disabled - 0 - - - One - CRC length is one byte and CRC calculation is enabled - 1 - - - Two - CRC length is two bytes and CRC calculation is enabled - 2 - - - Three - CRC length is three bytes and CRC calculation is enabled - 3 - - - - - SKIPADDR - Include or exclude packet address field out of CRC calculation. - 8 - 9 - - - Include - CRC calculation includes address field - 0 - - - Skip - CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. - 1 - - - Ieee802154 - CRC calculation as per 802.15.4 standard. Starting at first byte after length field. - 2 - - - - - - - CRCPOLY - CRC polynomial - 0x538 - read-write - 0x00000000 - - - CRCPOLY - CRC polynomial - 0 - 23 - - - - - CRCINIT - CRC initial value - 0x53C - read-write - - - CRCINIT - CRC initial value - 0 - 23 - - - - - TIFS - Interframe spacing in us - 0x544 - read-write - - - TIFS - Interframe spacing in us - 0 - 9 - - - - - RSSISAMPLE - RSSI sample - 0x548 - read-only - - - RSSISAMPLE - RSSI sample - 0 - 6 - - - - - STATE - Current radio state - 0x550 - read-only - - - STATE - Current radio state - 0 - 3 - - - Disabled - RADIO is in the Disabled state - 0 - - - RxRu - RADIO is in the RXRU state - 1 - - - RxIdle - RADIO is in the RXIDLE state - 2 - - - Rx - RADIO is in the RX state - 3 - - - RxDisable - RADIO is in the RXDISABLED state - 4 - - - TxRu - RADIO is in the TXRU state - 9 - - - TxIdle - RADIO is in the TXIDLE state - 10 - - - Tx - RADIO is in the TX state - 11 - - - TxDisable - RADIO is in the TXDISABLED state - 12 - - - - - - - DATAWHITEIV - Data whitening initial value - 0x554 - read-write - 0x00000040 - - - DATAWHITEIV - Data whitening initial value. Bit 6 is hardwired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. - 0 - 6 - - - - - BCC - Bit counter compare - 0x560 - read-write - - - BCC - Bit counter compare - 0 - 31 - - - - - 0x8 - 0x4 - DAB[%s] - Description collection: Device address base segment n - 0x600 - read-write - - - DAB - Device address base segment n - 0 - 31 - - - - - 0x8 - 0x4 - DAP[%s] - Description collection: Device address prefix n - 0x620 - read-write - - - DAP - Device address prefix n - 0 - 15 - - - - - DACNF - Device address match configuration - 0x640 - read-write - - - ENA0 - Enable or disable device address matching using device address 0 - 0 - 0 - - - Disabled - Disabled - 0 - - - Enabled - Enabled - 1 - - - - - ENA1 - Enable or disable device address matching using device address 1 - 1 - 1 - - - Disabled - Disabled - 0 - - - Enabled - Enabled - 1 - - - - - ENA2 - Enable or disable device address matching using device address 2 - 2 - 2 - - - Disabled - Disabled - 0 - - - Enabled - Enabled - 1 - - - - - ENA3 - Enable or disable device address matching using device address 3 - 3 - 3 - - - Disabled - Disabled - 0 - - - Enabled - Enabled - 1 - - - - - ENA4 - Enable or disable device address matching using device address 4 - 4 - 4 - - - Disabled - Disabled - 0 - - - Enabled - Enabled - 1 - - - - - ENA5 - Enable or disable device address matching using device address 5 - 5 - 5 - - - Disabled - Disabled - 0 - - - Enabled - Enabled - 1 - - - - - ENA6 - Enable or disable device address matching using device address 6 - 6 - 6 - - - Disabled - Disabled - 0 - - - Enabled - Enabled - 1 - - - - - ENA7 - Enable or disable device address matching using device address 7 - 7 - 7 - - - Disabled - Disabled - 0 - - - Enabled - Enabled - 1 - - - - - TXADD0 - TxAdd for device address 0 - 8 - 8 - - - TXADD1 - TxAdd for device address 1 - 9 - 9 - - - TXADD2 - TxAdd for device address 2 - 10 - 10 - - - TXADD3 - TxAdd for device address 3 - 11 - 11 - - - TXADD4 - TxAdd for device address 4 - 12 - 12 - - - TXADD5 - TxAdd for device address 5 - 13 - 13 - - - TXADD6 - TxAdd for device address 6 - 14 - 14 - - - TXADD7 - TxAdd for device address 7 - 15 - 15 - - - - - MHRMATCHCONF - Search pattern configuration - 0x644 - read-write - - - MHRMATCHCONF - Search pattern configuration - 0 - 31 - - - - - MHRMATCHMAS - Pattern mask - 0x648 - read-write - - - MHRMATCHMAS - Pattern mask - 0 - 31 - - - - - MODECNF0 - Radio mode configuration register 0 - 0x650 - read-write - 0x00000200 - - - RU - Radio ramp-up time - 0 - 0 - - - Default - Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51 - 0 - - - Fast - Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specification for more information - 1 - - - - - DTX - Default TX value - 8 - 9 - - - B1 - Transmit '1' - 0 - - - B0 - Transmit '0' - 1 - - - Center - Transmit center frequency - 2 - - - - - - - SFD - IEEE 802.15.4 start of frame delimiter - 0x660 - read-write - 0x000000A7 - - - SFD - IEEE 802.15.4 start of frame delimiter - 0 - 7 - - - - - EDCNT - IEEE 802.15.4 energy detect loop count - 0x664 - read-write - 0x00000000 - - - EDCNT - IEEE 802.15.4 energy detect loop count - 0 - 20 - - - - - EDSAMPLE - IEEE 802.15.4 energy detect level - 0x668 - read-write - 0x00000000 - - - EDLVL - IEEE 802.15.4 energy detect level - 0 - 7 - - - - - CCACTRL - IEEE 802.15.4 clear channel assessment control - 0x66C - read-write - 0x052D0000 - - - CCAMODE - CCA mode of operation - 0 - 2 - - - EdMode - Energy above threshold - 0 - - - CarrierMode - Carrier seen - 1 - - - CarrierAndEdMode - Energy above threshold AND carrier seen - 2 - - - CarrierOrEdMode - Energy above threshold OR carrier seen - 3 - - - EdModeTest1 - Energy above threshold test mode that will abort when first ED measurement over threshold is seen. No averaging. - 4 - - - - - CCAEDTHRES - CCA energy busy threshold. Used in all the CCA modes except CarrierMode. - 8 - 15 - - - CCACORRTHRES - CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode, and CarrierOrEdMode. - 16 - 23 - - - CCACORRCNT - Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect is enabled. - 24 - 31 - - - - - DFEMODE - Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure (AOD) - 0x900 - read-write - 0x00000000 - - - DFEOPMODE - Direction finding operation mode - 0 - 1 - - - Disabled - Direction finding mode disabled - 0 - - - AoD - Direction finding mode set to AoD - 2 - - - AoA - Direction finding mode set to AoA - 3 - - - - - - - CTEINLINECONF - Configuration for CTE inline mode - 0x904 - read-write - 0x00002800 - - - CTEINLINECTRLEN - Enable parsing of CTEInfo from received packet in BLE modes - 0 - 0 - - - Enabled - Parsing of CTEInfo is enabled - 1 - - - Disabled - Parsing of CTEInfo is disabled - 0 - - - - - CTEINFOINS1 - CTEInfo is S1 byte or not - 3 - 3 - - - InS1 - CTEInfo is in S1 byte (data PDU) - 1 - - - NotInS1 - CTEInfo is NOT in S1 byte (advertising PDU) - 0 - - - - - CTEERRORHANDLING - Sampling/switching if CRC is not OK - 4 - 4 - - - Yes - Sampling and antenna switching also when CRC is not OK - 1 - - - No - No sampling and antenna switching when CRC is not OK - 0 - - - - - CTETIMEVALIDRANGE - Max range of CTETime - 6 - 7 - - - 20 - 20 in 8us unit (default) Set to 20 if parsed CTETime is larger han 20 - 0 - - - 31 - 31 in 8us unit - 1 - - - 63 - 63 in 8us unit - 2 - - - - - CTEINLINERXMODE1US - Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set - 10 - 12 - - - 4us - 4us - 1 - - - 2us - 2us - 2 - - - 1us - 1us - 3 - - - 500ns - 0.5us - 4 - - - 250ns - 0.25us - 5 - - - 125ns - 0.125us - 6 - - - - - CTEINLINERXMODE2US - Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set - 13 - 15 - - - 4us - 4us - 1 - - - 2us - 2us - 2 - - - 1us - 1us - 3 - - - 500ns - 0.5us - 4 - - - 250ns - 0.25us - 5 - - - 125ns - 0.125us - 6 - - - - - S0CONF - S0 bit pattern to match - 16 - 23 - - - S0MASK - S0 bit mask to set which bit to match - 24 - 31 - - - - - DFECTRL1 - Various configuration for Direction finding - 0x910 - read-write - 0x00023282 - - - NUMBEROF8US - Length of the AoA/AoD procedure in number of 8 us units - 0 - 5 - - - DFEINEXTENSION - Add CTE extension and do antenna switching/sampling in this extension - 7 - 7 - - - CRC - AoA/AoD procedure triggered at end of CRC - 1 - - - Payload - Antenna switching/sampling is done in the packet payload - 0 - - - - - TSWITCHSPACING - Interval between every time the antenna is changed in the SWITCHING state - 8 - 10 - - - 4us - 4us - 1 - - - 2us - 2us - 2 - - - 1us - 1us - 3 - - - - - TSAMPLESPACINGREF - Interval between samples in the REFERENCE period - 12 - 14 - - - 4us - 4us - 1 - - - 2us - 2us - 2 - - - 1us - 1us - 3 - - - 500ns - 0.5us - 4 - - - 250ns - 0.25us - 5 - - - 125ns - 0.125us - 6 - - - - - SAMPLETYPE - Whether to sample I/Q or magnitude/phase - 15 - 15 - - - IQ - Complex samples in I and Q - 0 - - - MagPhase - Complex samples as magnitude and phase - 1 - - - - - TSAMPLESPACING - Interval between samples in the SWITCHING period when CTEINLINECTRLEN is 0 - 16 - 18 - - - 4us - 4us - 1 - - - 2us - 2us - 2 - - - 1us - 1us - 3 - - - 500ns - 0.5us - 4 - - - 250ns - 0.25us - 5 - - - 125ns - 0.125us - 6 - - - - - AGCBACKOFFGAIN - Gain will be lowered by the specified number of gain steps at the start of CTE - 24 - 27 - - - - - DFECTRL2 - Start offset for Direction finding - 0x914 - read-write - 0x00000000 - - - TSWITCHOFFSET - Signed value offset after the end of the CRC before starting switching in number of 16M cycles - 0 - 12 - - - TSAMPLEOFFSET - Signed value offset before starting sampling in number of 16M cycles relative to the beginning of the REFERENCE state - 12 us after switching start - 16 - 27 - - - - - SWITCHPATTERN - GPIO patterns to be used for each antenna - 0x928 - read-write - 0x00000000 - - - SWITCHPATTERN - Fill array of GPIO patterns for antenna control - 0 - 7 - - - - - CLEARPATTERN - Clear the GPIO pattern array for antenna control - 0x92C - read-write - - - CLEARPATTERN - Clears GPIO pattern array for antenna control - 0 - 0 - oneToClear - - - Clear - Clear the GPIO pattern - 1 - - - - - - - PSEL - Unspecified - RADIO_PSEL - read-write - 0x930 - - 0x8 - 0x4 - DFEGPIO[%s] - Description collection: Pin select for DFE pin n - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - DFEPACKET - DFE packet EasyDMA channel - RADIO_DFEPACKET - read-write - 0x950 - - PTR - Data pointer - 0x000 - read-write - 0x00000000 - - - PTR - Data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of buffer words to transfer - 0x004 - read-write - 0x00001000 - - - MAXCNT - Maximum number of buffer words to transfer - 0 - 12 - - - - - AMOUNT - Number of samples transferred in the last transaction - 0x008 - read-only - - - AMOUNT - Number of samples transferred in the last transaction - 0 - 15 - - - - - - POWER - Peripheral power control - 0xFFC - read-write - 0x00000001 - - - POWER - Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. - 0 - 0 - - - Disabled - Peripheral is powered off - 0 - - - Enabled - Peripheral is powered on - 1 - - - - - - - - - UART0 - Universal Asynchronous Receiver/Transmitter - 0x40002000 - UART - - 0 - 0x1000 - registers - - - UARTE0_UART0 - 2 - - UART - 0x20 - - - TASKS_STARTRX - Start UART receiver - 0x000 - write-only - - - TASKS_STARTRX - Start UART receiver - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STOPRX - Stop UART receiver - 0x004 - write-only - - - TASKS_STOPRX - Stop UART receiver - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STARTTX - Start UART transmitter - 0x008 - write-only - - - TASKS_STARTTX - Start UART transmitter - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STOPTX - Stop UART transmitter - 0x00C - write-only - - - TASKS_STOPTX - Stop UART transmitter - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_SUSPEND - Suspend UART - 0x01C - write-only - - - TASKS_SUSPEND - Suspend UART - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - EVENTS_CTS - CTS is activated (set low). Clear To Send. - 0x100 - read-write - - - EVENTS_CTS - CTS is activated (set low). Clear To Send. - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_NCTS - CTS is deactivated (set high). Not Clear To Send. - 0x104 - read-write - - - EVENTS_NCTS - CTS is deactivated (set high). Not Clear To Send. - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_RXDRDY - Data received in RXD - 0x108 - read-write - - - EVENTS_RXDRDY - Data received in RXD - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_TXDRDY - Data sent from TXD - 0x11C - read-write - - - EVENTS_TXDRDY - Data sent from TXD - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_ERROR - Error detected - 0x124 - read-write - - - EVENTS_ERROR - Error detected - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_RXTO - Receiver timeout - 0x144 - read-write - - - EVENTS_RXTO - Receiver timeout - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - SHORTS - Shortcuts between local events and tasks - 0x200 - read-write - - - CTS_STARTRX - Shortcut between event CTS and task STARTRX - 3 - 3 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - NCTS_STOPRX - Shortcut between event NCTS and task STOPRX - 4 - 4 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - CTS - Write '1' to enable interrupt for event CTS - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - NCTS - Write '1' to enable interrupt for event NCTS - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RXDRDY - Write '1' to enable interrupt for event RXDRDY - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TXDRDY - Write '1' to enable interrupt for event TXDRDY - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ERROR - Write '1' to enable interrupt for event ERROR - 9 - 9 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RXTO - Write '1' to enable interrupt for event RXTO - 17 - 17 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - CTS - Write '1' to disable interrupt for event CTS - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - NCTS - Write '1' to disable interrupt for event NCTS - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RXDRDY - Write '1' to disable interrupt for event RXDRDY - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TXDRDY - Write '1' to disable interrupt for event TXDRDY - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ERROR - Write '1' to disable interrupt for event ERROR - 9 - 9 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RXTO - Write '1' to disable interrupt for event RXTO - 17 - 17 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - ERRORSRC - Error source - 0x480 - read-write - oneToClear - - - OVERRUN - Overrun error - 0 - 0 - - read - - NotPresent - Read: error not present - 0 - - - Present - Read: error present - 1 - - - - - PARITY - Parity error - 1 - 1 - - read - - NotPresent - Read: error not present - 0 - - - Present - Read: error present - 1 - - - - - FRAMING - Framing error occurred - 2 - 2 - - read - - NotPresent - Read: error not present - 0 - - - Present - Read: error present - 1 - - - - - BREAK - Break condition - 3 - 3 - - read - - NotPresent - Read: error not present - 0 - - - Present - Read: error present - 1 - - - - - - - ENABLE - Enable UART - 0x500 - read-write - - - ENABLE - Enable or disable UART - 0 - 3 - - - Disabled - Disable UART - 0 - - - Enabled - Enable UART - 4 - - - - - - - PSEL - Unspecified - UART_PSEL - read-write - 0x508 - - RTS - Pin select for RTS - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - TXD - Pin select for TXD - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - CTS - Pin select for CTS - 0x008 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - RXD - Pin select for RXD - 0x00C - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - RXD - RXD register - 0x518 - read-only - modifyExternal - - - RXD - RX data received in previous transfers, double buffered - 0 - 7 - - - - - TXD - TXD register - 0x51C - write-only - - - TXD - TX data to be transferred - 0 - 7 - - - - - BAUDRATE - Baud rate. Accuracy depends on the HFCLK source selected. - 0x524 - read-write - 0x04000000 - - - BAUDRATE - Baud rate - 0 - 31 - - - Baud1200 - 1200 baud (actual rate: 1205) - 0x0004F000 - - - Baud2400 - 2400 baud (actual rate: 2396) - 0x0009D000 - - - Baud4800 - 4800 baud (actual rate: 4808) - 0x0013B000 - - - Baud9600 - 9600 baud (actual rate: 9598) - 0x00275000 - - - Baud14400 - 14400 baud (actual rate: 14414) - 0x003B0000 - - - Baud19200 - 19200 baud (actual rate: 19208) - 0x004EA000 - - - Baud28800 - 28800 baud (actual rate: 28829) - 0x0075F000 - - - Baud31250 - 31250 baud - 0x00800000 - - - Baud38400 - 38400 baud (actual rate: 38462) - 0x009D5000 - - - Baud56000 - 56000 baud (actual rate: 55944) - 0x00E50000 - - - Baud57600 - 57600 baud (actual rate: 57762) - 0x00EBF000 - - - Baud76800 - 76800 baud (actual rate: 76923) - 0x013A9000 - - - Baud115200 - 115200 baud (actual rate: 115942) - 0x01D7E000 - - - Baud230400 - 230400 baud (actual rate: 231884) - 0x03AFB000 - - - Baud250000 - 250000 baud - 0x04000000 - - - Baud460800 - 460800 baud (actual rate: 470588) - 0x075F7000 - - - Baud921600 - 921600 baud (actual rate: 941176) - 0x0EBED000 - - - Baud1M - 1Mega baud - 0x10000000 - - - - - - - CONFIG - Configuration of parity and hardware flow control - 0x56C - read-write - - - HWFC - Hardware flow control - 0 - 0 - - - Disabled - Disabled - 0 - - - Enabled - Enabled - 1 - - - - - PARITY - Parity - 1 - 3 - - - Excluded - Exclude parity bit - 0x0 - - - Included - Include parity bit - 0x7 - - - - - STOP - Stop bits - 4 - 4 - - - One - One stop bit - 0 - - - Two - Two stop bits - 1 - - - - - - - - - UARTE0 - UART with EasyDMA - 0x40002000 - UART0 - UARTE - - 0 - 0x1000 - registers - - - UARTE0_UART0 - 2 - - UARTE - 0x20 - - - TASKS_STARTRX - Start UART receiver - 0x000 - write-only - - - TASKS_STARTRX - Start UART receiver - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STOPRX - Stop UART receiver - 0x004 - write-only - - - TASKS_STOPRX - Stop UART receiver - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STARTTX - Start UART transmitter - 0x008 - write-only - - - TASKS_STARTTX - Start UART transmitter - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STOPTX - Stop UART transmitter - 0x00C - write-only - - - TASKS_STOPTX - Stop UART transmitter - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_FLUSHRX - Flush RX FIFO into RX buffer - 0x02C - write-only - - - TASKS_FLUSHRX - Flush RX FIFO into RX buffer - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - EVENTS_CTS - CTS is activated (set low). Clear To Send. - 0x100 - read-write - - - EVENTS_CTS - CTS is activated (set low). Clear To Send. - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_NCTS - CTS is deactivated (set high). Not Clear To Send. - 0x104 - read-write - - - EVENTS_NCTS - CTS is deactivated (set high). Not Clear To Send. - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_RXDRDY - Data received in RXD (but potentially not yet transferred to Data RAM) - 0x108 - read-write - - - EVENTS_RXDRDY - Data received in RXD (but potentially not yet transferred to Data RAM) - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_ENDRX - Receive buffer is filled up - 0x110 - read-write - - - EVENTS_ENDRX - Receive buffer is filled up - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_TXDRDY - Data sent from TXD - 0x11C - read-write - - - EVENTS_TXDRDY - Data sent from TXD - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_ENDTX - Last TX byte transmitted - 0x120 - read-write - - - EVENTS_ENDTX - Last TX byte transmitted - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_ERROR - Error detected - 0x124 - read-write - - - EVENTS_ERROR - Error detected - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_RXTO - Receiver timeout - 0x144 - read-write - - - EVENTS_RXTO - Receiver timeout - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_RXSTARTED - UART receiver has started - 0x14C - read-write - - - EVENTS_RXSTARTED - UART receiver has started - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_TXSTARTED - UART transmitter has started - 0x150 - read-write - - - EVENTS_TXSTARTED - UART transmitter has started - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_TXSTOPPED - Transmitter stopped - 0x158 - read-write - - - EVENTS_TXSTOPPED - Transmitter stopped - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - SHORTS - Shortcuts between local events and tasks - 0x200 - read-write - - - ENDRX_STARTRX - Shortcut between event ENDRX and task STARTRX - 5 - 5 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - ENDRX_STOPRX - Shortcut between event ENDRX and task STOPRX - 6 - 6 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - - CTS - Enable or disable interrupt for event CTS - 0 - 0 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - NCTS - Enable or disable interrupt for event NCTS - 1 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RXDRDY - Enable or disable interrupt for event RXDRDY - 2 - 2 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ENDRX - Enable or disable interrupt for event ENDRX - 4 - 4 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TXDRDY - Enable or disable interrupt for event TXDRDY - 7 - 7 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ENDTX - Enable or disable interrupt for event ENDTX - 8 - 8 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ERROR - Enable or disable interrupt for event ERROR - 9 - 9 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RXTO - Enable or disable interrupt for event RXTO - 17 - 17 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RXSTARTED - Enable or disable interrupt for event RXSTARTED - 19 - 19 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TXSTARTED - Enable or disable interrupt for event TXSTARTED - 20 - 20 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TXSTOPPED - Enable or disable interrupt for event TXSTOPPED - 22 - 22 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - CTS - Write '1' to enable interrupt for event CTS - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - NCTS - Write '1' to enable interrupt for event NCTS - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RXDRDY - Write '1' to enable interrupt for event RXDRDY - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ENDRX - Write '1' to enable interrupt for event ENDRX - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TXDRDY - Write '1' to enable interrupt for event TXDRDY - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ENDTX - Write '1' to enable interrupt for event ENDTX - 8 - 8 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ERROR - Write '1' to enable interrupt for event ERROR - 9 - 9 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RXTO - Write '1' to enable interrupt for event RXTO - 17 - 17 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RXSTARTED - Write '1' to enable interrupt for event RXSTARTED - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TXSTARTED - Write '1' to enable interrupt for event TXSTARTED - 20 - 20 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TXSTOPPED - Write '1' to enable interrupt for event TXSTOPPED - 22 - 22 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - CTS - Write '1' to disable interrupt for event CTS - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - NCTS - Write '1' to disable interrupt for event NCTS - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RXDRDY - Write '1' to disable interrupt for event RXDRDY - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ENDRX - Write '1' to disable interrupt for event ENDRX - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TXDRDY - Write '1' to disable interrupt for event TXDRDY - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ENDTX - Write '1' to disable interrupt for event ENDTX - 8 - 8 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ERROR - Write '1' to disable interrupt for event ERROR - 9 - 9 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RXTO - Write '1' to disable interrupt for event RXTO - 17 - 17 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RXSTARTED - Write '1' to disable interrupt for event RXSTARTED - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TXSTARTED - Write '1' to disable interrupt for event TXSTARTED - 20 - 20 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TXSTOPPED - Write '1' to disable interrupt for event TXSTOPPED - 22 - 22 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - ERRORSRC - Error source Note : this register is read / write one to clear. - 0x480 - read-write - oneToClear - - - OVERRUN - Overrun error - 0 - 0 - - read - - NotPresent - Read: error not present - 0 - - - Present - Read: error present - 1 - - - - - PARITY - Parity error - 1 - 1 - - read - - NotPresent - Read: error not present - 0 - - - Present - Read: error present - 1 - - - - - FRAMING - Framing error occurred - 2 - 2 - - read - - NotPresent - Read: error not present - 0 - - - Present - Read: error present - 1 - - - - - BREAK - Break condition - 3 - 3 - - read - - NotPresent - Read: error not present - 0 - - - Present - Read: error present - 1 - - - - - - - ENABLE - Enable UART - 0x500 - read-write - - - ENABLE - Enable or disable UARTE - 0 - 3 - - - Disabled - Disable UARTE - 0 - - - Enabled - Enable UARTE - 8 - - - - - - - PSEL - Unspecified - UARTE_PSEL - read-write - 0x508 - - RTS - Pin select for RTS signal - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - TXD - Pin select for TXD signal - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - CTS - Pin select for CTS signal - 0x008 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - RXD - Pin select for RXD signal - 0x00C - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - BAUDRATE - Baud rate. Accuracy depends on the HFCLK source selected. - 0x524 - read-write - 0x04000000 - - - BAUDRATE - Baud rate - 0 - 31 - - - Baud1200 - 1200 baud (actual rate: 1205) - 0x0004F000 - - - Baud2400 - 2400 baud (actual rate: 2396) - 0x0009D000 - - - Baud4800 - 4800 baud (actual rate: 4808) - 0x0013B000 - - - Baud9600 - 9600 baud (actual rate: 9598) - 0x00275000 - - - Baud14400 - 14400 baud (actual rate: 14401) - 0x003AF000 - - - Baud19200 - 19200 baud (actual rate: 19208) - 0x004EA000 - - - Baud28800 - 28800 baud (actual rate: 28777) - 0x0075C000 - - - Baud31250 - 31250 baud - 0x00800000 - - - Baud38400 - 38400 baud (actual rate: 38369) - 0x009D0000 - - - Baud56000 - 56000 baud (actual rate: 55944) - 0x00E50000 - - - Baud57600 - 57600 baud (actual rate: 57554) - 0x00EB0000 - - - Baud76800 - 76800 baud (actual rate: 76923) - 0x013A9000 - - - Baud115200 - 115200 baud (actual rate: 115108) - 0x01D60000 - - - Baud230400 - 230400 baud (actual rate: 231884) - 0x03B00000 - - - Baud250000 - 250000 baud - 0x04000000 - - - Baud460800 - 460800 baud (actual rate: 457143) - 0x07400000 - - - Baud921600 - 921600 baud (actual rate: 941176) - 0x0F000000 - - - Baud1M - 1Mega baud - 0x10000000 - - - - - - - RXD - RXD EasyDMA channel - UARTE_RXD - read-write - 0x534 - - PTR - Data pointer - 0x000 - read-write - - - PTR - Data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in receive buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in receive buffer - 0 - 9 - - - - - AMOUNT - Number of bytes transferred in the last transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last transaction - 0 - 9 - - - - - - TXD - TXD EasyDMA channel - UARTE_TXD - read-write - 0x544 - - PTR - Data pointer - 0x000 - read-write - - - PTR - Data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in transmit buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in transmit buffer - 0 - 9 - - - - - AMOUNT - Number of bytes transferred in the last transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last transaction - 0 - 9 - - - - - - CONFIG - Configuration of parity and hardware flow control - 0x56C - read-write - - - HWFC - Hardware flow control - 0 - 0 - - - Disabled - Disabled - 0 - - - Enabled - Enabled - 1 - - - - - PARITY - Parity - 1 - 3 - - - Excluded - Exclude parity bit - 0x0 - - - Included - Include even parity bit - 0x7 - - - - - STOP - Stop bits - 4 - 4 - - - One - One stop bit - 0 - - - Two - Two stop bits - 1 - - - - - - - - - SPI0 - Serial Peripheral Interface 0 - 0x40003000 - SPI - - 0 - 0x1000 - registers - - - TWIM0_TWIS0_TWI0_SPIM0_SPIS0_SPI0 - 3 - - SPI - 0x20 - - - EVENTS_READY - TXD byte sent and RXD byte received - 0x108 - read-write - - - EVENTS_READY - TXD byte sent and RXD byte received - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - READY - Write '1' to enable interrupt for event READY - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - READY - Write '1' to disable interrupt for event READY - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - ENABLE - Enable SPI - 0x500 - read-write - - - ENABLE - Enable or disable SPI - 0 - 3 - - - Disabled - Disable SPI - 0 - - - Enabled - Enable SPI - 1 - - - - - - - PSEL - Unspecified - SPI_PSEL - read-write - 0x508 - - SCK - Pin select for SCK - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - MOSI - Pin select for MOSI signal - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - MISO - Pin select for MISO signal - 0x008 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - RXD - RXD register - 0x518 - read-only - modifyExternal - - - RXD - RX data received. Double buffered - 0 - 7 - - - - - TXD - TXD register - 0x51C - read-write - - - TXD - TX data to send. Double buffered - 0 - 7 - - - - - FREQUENCY - SPI frequency. Accuracy depends on the HFCLK source selected. - 0x524 - read-write - 0x04000000 - - - FREQUENCY - SPI master data rate - 0 - 31 - - - K125 - 125 kbps - 0x02000000 - - - K250 - 250 kbps - 0x04000000 - - - K500 - 500 kbps - 0x08000000 - - - M1 - 1 Mbps - 0x10000000 - - - M2 - 2 Mbps - 0x20000000 - - - M4 - 4 Mbps - 0x40000000 - - - M8 - 8 Mbps - 0x80000000 - - - - - - - CONFIG - Configuration register - 0x554 - read-write - - - ORDER - Bit order - 0 - 0 - - - MsbFirst - Most significant bit shifted out first - 0 - - - LsbFirst - Least significant bit shifted out first - 1 - - - - - CPHA - Serial clock (SCK) phase - 1 - 1 - - - Leading - Sample on leading edge of clock, shift serial data on trailing edge - 0 - - - Trailing - Sample on trailing edge of clock, shift serial data on leading edge - 1 - - - - - CPOL - Serial clock (SCK) polarity - 2 - 2 - - - ActiveHigh - Active high - 0 - - - ActiveLow - Active low - 1 - - - - - - - - - SPIM0 - Serial Peripheral Interface Master with EasyDMA 0 - 0x40003000 - SPI0 - SPIM - - 0 - 0x1000 - registers - - - TWIM0_TWIS0_TWI0_SPIM0_SPIS0_SPI0 - 3 - - SPIM - 0x20 - - - TASKS_START - Start SPI transaction - 0x010 - write-only - - - TASKS_START - Start SPI transaction - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STOP - Stop SPI transaction - 0x014 - write-only - - - TASKS_STOP - Stop SPI transaction - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_SUSPEND - Suspend SPI transaction - 0x01C - write-only - - - TASKS_SUSPEND - Suspend SPI transaction - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_RESUME - Resume SPI transaction - 0x020 - write-only - - - TASKS_RESUME - Resume SPI transaction - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - EVENTS_STOPPED - SPI transaction has stopped - 0x104 - read-write - - - EVENTS_STOPPED - SPI transaction has stopped - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_ENDRX - End of RXD buffer reached - 0x110 - read-write - - - EVENTS_ENDRX - End of RXD buffer reached - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_END - End of RXD buffer and TXD buffer reached - 0x118 - read-write - - - EVENTS_END - End of RXD buffer and TXD buffer reached - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_ENDTX - End of TXD buffer reached - 0x120 - read-write - - - EVENTS_ENDTX - End of TXD buffer reached - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_STARTED - Transaction started - 0x14C - read-write - - - EVENTS_STARTED - Transaction started - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - SHORTS - Shortcuts between local events and tasks - 0x200 - read-write - - - END_START - Shortcut between event END and task START - 17 - 17 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - STOPPED - Write '1' to enable interrupt for event STOPPED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ENDRX - Write '1' to enable interrupt for event ENDRX - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - END - Write '1' to enable interrupt for event END - 6 - 6 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ENDTX - Write '1' to enable interrupt for event ENDTX - 8 - 8 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - STARTED - Write '1' to enable interrupt for event STARTED - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - STOPPED - Write '1' to disable interrupt for event STOPPED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ENDRX - Write '1' to disable interrupt for event ENDRX - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - END - Write '1' to disable interrupt for event END - 6 - 6 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ENDTX - Write '1' to disable interrupt for event ENDTX - 8 - 8 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - STARTED - Write '1' to disable interrupt for event STARTED - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - ENABLE - Enable SPIM - 0x500 - read-write - - - ENABLE - Enable or disable SPIM - 0 - 3 - - - Disabled - Disable SPIM - 0 - - - Enabled - Enable SPIM - 7 - - - - - - - PSEL - Unspecified - SPIM_PSEL - read-write - 0x508 - - SCK - Pin select for SCK - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - MOSI - Pin select for MOSI signal - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - MISO - Pin select for MISO signal - 0x008 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - FREQUENCY - SPI frequency. Accuracy depends on the HFCLK source selected. - 0x524 - read-write - 0x04000000 - - - FREQUENCY - SPI master data rate - 0 - 31 - - - K125 - 125 kbps - 0x02000000 - - - K250 - 250 kbps - 0x04000000 - - - K500 - 500 kbps - 0x08000000 - - - M1 - 1 Mbps - 0x10000000 - - - M2 - 2 Mbps - 0x20000000 - - - M4 - 4 Mbps - 0x40000000 - - - M8 - 8 Mbps - 0x80000000 - - - - - - - RXD - RXD EasyDMA channel - SPIM_RXD - read-write - 0x534 - - PTR - Data pointer - 0x000 - read-write - - - PTR - Data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in receive buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in receive buffer - 0 - 13 - - - - - AMOUNT - Number of bytes transferred in the last transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last transaction - 0 - 13 - - - - - LIST - EasyDMA list type - 0x00C - read-write - - - LIST - List type - 0 - 1 - - - Disabled - Disable EasyDMA list - 0 - - - ArrayList - Use array list - 1 - - - - - - - - TXD - TXD EasyDMA channel - SPIM_TXD - read-write - 0x544 - - PTR - Data pointer - 0x000 - read-write - - - PTR - Data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in transmit buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in transmit buffer - 0 - 13 - - - - - AMOUNT - Number of bytes transferred in the last transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last transaction - 0 - 13 - - - - - LIST - EasyDMA list type - 0x00C - read-write - - - LIST - List type - 0 - 1 - - - Disabled - Disable EasyDMA list - 0 - - - ArrayList - Use array list - 1 - - - - - - - - CONFIG - Configuration register - 0x554 - read-write - - - ORDER - Bit order - 0 - 0 - - - MsbFirst - Most significant bit shifted out first - 0 - - - LsbFirst - Least significant bit shifted out first - 1 - - - - - CPHA - Serial clock (SCK) phase - 1 - 1 - - - Leading - Sample on leading edge of clock, shift serial data on trailing edge - 0 - - - Trailing - Sample on trailing edge of clock, shift serial data on leading edge - 1 - - - - - CPOL - Serial clock (SCK) polarity - 2 - 2 - - - ActiveHigh - Active high - 0 - - - ActiveLow - Active low - 1 - - - - - - - ORC - Over-read character. Character clocked out in case and over-read of the TXD buffer. - 0x5C0 - read-write - - - ORC - Over-read character. Character clocked out in case and over-read of the TXD buffer. - 0 - 7 - - - - - - - SPIS0 - SPI Slave 0 - 0x40003000 - SPI0 - SPIS - - 0 - 0x1000 - registers - - - TWIM0_TWIS0_TWI0_SPIM0_SPIS0_SPI0 - 3 - - SPIS - 0x20 - - - TASKS_ACQUIRE - Acquire SPI semaphore - 0x024 - write-only - - - TASKS_ACQUIRE - Acquire SPI semaphore - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_RELEASE - Release SPI semaphore, enabling the SPI slave to acquire it - 0x028 - write-only - - - TASKS_RELEASE - Release SPI semaphore, enabling the SPI slave to acquire it - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - EVENTS_END - Granted transaction completed - 0x104 - read-write - - - EVENTS_END - Granted transaction completed - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_ENDRX - End of RXD buffer reached - 0x110 - read-write - - - EVENTS_ENDRX - End of RXD buffer reached - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_ACQUIRED - Semaphore acquired - 0x128 - read-write - - - EVENTS_ACQUIRED - Semaphore acquired - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - SHORTS - Shortcuts between local events and tasks - 0x200 - read-write - - - END_ACQUIRE - Shortcut between event END and task ACQUIRE - 2 - 2 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - END - Write '1' to enable interrupt for event END - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ENDRX - Write '1' to enable interrupt for event ENDRX - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ACQUIRED - Write '1' to enable interrupt for event ACQUIRED - 10 - 10 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - END - Write '1' to disable interrupt for event END - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ENDRX - Write '1' to disable interrupt for event ENDRX - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ACQUIRED - Write '1' to disable interrupt for event ACQUIRED - 10 - 10 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - SEMSTAT - Semaphore status register - 0x400 - read-only - 0x00000001 - - - SEMSTAT - Semaphore status - 0 - 1 - - - Free - Semaphore is free - 0 - - - CPU - Semaphore is assigned to CPU - 1 - - - SPIS - Semaphore is assigned to SPI slave - 2 - - - CPUPending - Semaphore is assigned to SPI but a handover to the CPU is pending - 3 - - - - - - - STATUS - Status from last transaction - 0x440 - read-write - - - OVERREAD - TX buffer over-read detected, and prevented - 0 - 0 - - read - - NotPresent - Read: error not present - 0 - - - Present - Read: error present - 1 - - - - write - - Clear - Write: clear error on writing '1' - 1 - - - - - OVERFLOW - RX buffer overflow detected, and prevented - 1 - 1 - - read - - NotPresent - Read: error not present - 0 - - - Present - Read: error present - 1 - - - - write - - Clear - Write: clear error on writing '1' - 1 - - - - - - - ENABLE - Enable SPI slave - 0x500 - read-write - - - ENABLE - Enable or disable SPI slave - 0 - 3 - - - Disabled - Disable SPI slave - 0 - - - Enabled - Enable SPI slave - 2 - - - - - - - PSEL - Unspecified - SPIS_PSEL - read-write - 0x508 - - SCK - Pin select for SCK - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - MISO - Pin select for MISO signal - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - MOSI - Pin select for MOSI signal - 0x008 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - CSN - Pin select for CSN signal - 0x00C - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - RXD - Unspecified - SPIS_RXD - read-write - 0x534 - - PTR - RXD data pointer - 0x000 - read-write - - - PTR - RXD data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in receive buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in receive buffer - 0 - 13 - - - - - AMOUNT - Number of bytes received in last granted transaction - 0x008 - read-only - - - AMOUNT - Number of bytes received in the last granted transaction - 0 - 13 - - - - - LIST - EasyDMA list type - 0x00C - read-write - - - LIST - List type - 0 - 1 - - - Disabled - Disable EasyDMA list - 0 - - - ArrayList - Use array list - 1 - - - - - - - - TXD - Unspecified - SPIS_TXD - read-write - 0x544 - - PTR - TXD data pointer - 0x000 - read-write - - - PTR - TXD data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in transmit buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in transmit buffer - 0 - 13 - - - - - AMOUNT - Number of bytes transmitted in last granted transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transmitted in last granted transaction - 0 - 13 - - - - - LIST - EasyDMA list type - 0x00C - read-write - - - LIST - List type - 0 - 1 - - - Disabled - Disable EasyDMA list - 0 - - - ArrayList - Use array list - 1 - - - - - - - - CONFIG - Configuration register - 0x554 - read-write - - - ORDER - Bit order - 0 - 0 - - - MsbFirst - Most significant bit shifted out first - 0 - - - LsbFirst - Least significant bit shifted out first - 1 - - - - - CPHA - Serial clock (SCK) phase - 1 - 1 - - - Leading - Sample on leading edge of clock, shift serial data on trailing edge - 0 - - - Trailing - Sample on trailing edge of clock, shift serial data on leading edge - 1 - - - - - CPOL - Serial clock (SCK) polarity - 2 - 2 - - - ActiveHigh - Active high - 0 - - - ActiveLow - Active low - 1 - - - - - - - DEF - Default character. Character clocked out in case of an ignored transaction. - 0x55C - read-write - - - DEF - Default character. Character clocked out in case of an ignored transaction. - 0 - 7 - - - - - ORC - Over-read character - 0x5C0 - read-write - - - ORC - Over-read character. Character clocked out after an over-read of the transmit buffer. - 0 - 7 - - - - - - - TWI0 - I2C compatible Two-Wire Interface - 0x40003000 - SPI0 - TWI - - 0 - 0x1000 - registers - - - TWIM0_TWIS0_TWI0_SPIM0_SPIS0_SPI0 - 3 - - TWI - 0x20 - - - TASKS_STARTRX - Start TWI receive sequence - 0x000 - write-only - - - TASKS_STARTRX - Start TWI receive sequence - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STARTTX - Start TWI transmit sequence - 0x008 - write-only - - - TASKS_STARTTX - Start TWI transmit sequence - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STOP - Stop TWI transaction - 0x014 - write-only - - - TASKS_STOP - Stop TWI transaction - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_SUSPEND - Suspend TWI transaction - 0x01C - write-only - - - TASKS_SUSPEND - Suspend TWI transaction - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_RESUME - Resume TWI transaction - 0x020 - write-only - - - TASKS_RESUME - Resume TWI transaction - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - EVENTS_STOPPED - TWI stopped - 0x104 - read-write - - - EVENTS_STOPPED - TWI stopped - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_RXDREADY - TWI RXD byte received - 0x108 - read-write - - - EVENTS_RXDREADY - TWI RXD byte received - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_TXDSENT - TWI TXD byte sent - 0x11C - read-write - - - EVENTS_TXDSENT - TWI TXD byte sent - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_ERROR - TWI error - 0x124 - read-write - - - EVENTS_ERROR - TWI error - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_BB - TWI byte boundary, generated before each byte that is sent or received - 0x138 - read-write - - - EVENTS_BB - TWI byte boundary, generated before each byte that is sent or received - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_SUSPENDED - TWI entered the suspended state - 0x148 - read-write - - - EVENTS_SUSPENDED - TWI entered the suspended state - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - SHORTS - Shortcuts between local events and tasks - 0x200 - read-write - - - BB_SUSPEND - Shortcut between event BB and task SUSPEND - 0 - 0 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - BB_STOP - Shortcut between event BB and task STOP - 1 - 1 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - STOPPED - Write '1' to enable interrupt for event STOPPED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RXDREADY - Write '1' to enable interrupt for event RXDREADY - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TXDSENT - Write '1' to enable interrupt for event TXDSENT - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ERROR - Write '1' to enable interrupt for event ERROR - 9 - 9 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - BB - Write '1' to enable interrupt for event BB - 14 - 14 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - SUSPENDED - Write '1' to enable interrupt for event SUSPENDED - 18 - 18 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - STOPPED - Write '1' to disable interrupt for event STOPPED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RXDREADY - Write '1' to disable interrupt for event RXDREADY - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TXDSENT - Write '1' to disable interrupt for event TXDSENT - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ERROR - Write '1' to disable interrupt for event ERROR - 9 - 9 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - BB - Write '1' to disable interrupt for event BB - 14 - 14 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - SUSPENDED - Write '1' to disable interrupt for event SUSPENDED - 18 - 18 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - ERRORSRC - Error source - 0x4C4 - read-write - oneToClear - - - OVERRUN - Overrun error - 0 - 0 - - read - - NotPresent - Read: no overrun occured - 0 - - - Present - Read: overrun occured - 1 - - - - - ANACK - NACK received after sending the address (write '1' to clear) - 1 - 1 - - read - - NotPresent - Read: error not present - 0 - - - Present - Read: error present - 1 - - - - - DNACK - NACK received after sending a data byte (write '1' to clear) - 2 - 2 - - read - - NotPresent - Read: error not present - 0 - - - Present - Read: error present - 1 - - - - - - - ENABLE - Enable TWI - 0x500 - read-write - - - ENABLE - Enable or disable TWI - 0 - 3 - - - Disabled - Disable TWI - 0 - - - Enabled - Enable TWI - 5 - - - - - - - PSEL - Unspecified - TWI_PSEL - read-write - 0x508 - - SCL - Pin select for SCL - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - SDA - Pin select for SDA - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - RXD - RXD register - 0x518 - read-only - modifyExternal - - - RXD - RXD register - 0 - 7 - - - - - TXD - TXD register - 0x51C - read-write - - - TXD - TXD register - 0 - 7 - - - - - FREQUENCY - TWI frequency. Accuracy depends on the HFCLK source selected. - 0x524 - read-write - 0x04000000 - - - FREQUENCY - TWI master clock frequency - 0 - 31 - - - K100 - 100 kbps - 0x01980000 - - - K250 - 250 kbps - 0x04000000 - - - K400 - 400 kbps (actual rate 410.256 kbps) - 0x06680000 - - - - - - - ADDRESS - Address used in the TWI transfer - 0x588 - read-write - - - ADDRESS - Address used in the TWI transfer - 0 - 6 - - - - - - - TWIM0 - I2C compatible Two-Wire Master Interface with EasyDMA - 0x40003000 - SPI0 - TWIM - - 0 - 0x1000 - registers - - - TWIM0_TWIS0_TWI0_SPIM0_SPIS0_SPI0 - 3 - - TWIM - 0x20 - - - TASKS_STARTRX - Start TWI receive sequence - 0x000 - write-only - - - TASKS_STARTRX - Start TWI receive sequence - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STARTTX - Start TWI transmit sequence - 0x008 - write-only - - - TASKS_STARTTX - Start TWI transmit sequence - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STOP - Stop TWI transaction. Must be issued while the TWI master is not suspended. - 0x014 - write-only - - - TASKS_STOP - Stop TWI transaction. Must be issued while the TWI master is not suspended. - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_SUSPEND - Suspend TWI transaction - 0x01C - write-only - - - TASKS_SUSPEND - Suspend TWI transaction - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_RESUME - Resume TWI transaction - 0x020 - write-only - - - TASKS_RESUME - Resume TWI transaction - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - EVENTS_STOPPED - TWI stopped - 0x104 - read-write - - - EVENTS_STOPPED - TWI stopped - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_ERROR - TWI error - 0x124 - read-write - - - EVENTS_ERROR - TWI error - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_SUSPENDED - Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. - 0x148 - read-write - - - EVENTS_SUSPENDED - Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_RXSTARTED - Receive sequence started - 0x14C - read-write - - - EVENTS_RXSTARTED - Receive sequence started - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_TXSTARTED - Transmit sequence started - 0x150 - read-write - - - EVENTS_TXSTARTED - Transmit sequence started - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_LASTRX - Byte boundary, starting to receive the last byte - 0x15C - read-write - - - EVENTS_LASTRX - Byte boundary, starting to receive the last byte - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_LASTTX - Byte boundary, starting to transmit the last byte - 0x160 - read-write - - - EVENTS_LASTTX - Byte boundary, starting to transmit the last byte - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - SHORTS - Shortcuts between local events and tasks - 0x200 - read-write - - - LASTTX_STARTRX - Shortcut between event LASTTX and task STARTRX - 7 - 7 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - LASTTX_SUSPEND - Shortcut between event LASTTX and task SUSPEND - 8 - 8 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - LASTTX_STOP - Shortcut between event LASTTX and task STOP - 9 - 9 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - LASTRX_STARTTX - Shortcut between event LASTRX and task STARTTX - 10 - 10 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - LASTRX_SUSPEND - Shortcut between event LASTRX and task SUSPEND - 11 - 11 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - LASTRX_STOP - Shortcut between event LASTRX and task STOP - 12 - 12 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - - STOPPED - Enable or disable interrupt for event STOPPED - 1 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ERROR - Enable or disable interrupt for event ERROR - 9 - 9 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - SUSPENDED - Enable or disable interrupt for event SUSPENDED - 18 - 18 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RXSTARTED - Enable or disable interrupt for event RXSTARTED - 19 - 19 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TXSTARTED - Enable or disable interrupt for event TXSTARTED - 20 - 20 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - LASTRX - Enable or disable interrupt for event LASTRX - 23 - 23 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - LASTTX - Enable or disable interrupt for event LASTTX - 24 - 24 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - STOPPED - Write '1' to enable interrupt for event STOPPED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ERROR - Write '1' to enable interrupt for event ERROR - 9 - 9 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - SUSPENDED - Write '1' to enable interrupt for event SUSPENDED - 18 - 18 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RXSTARTED - Write '1' to enable interrupt for event RXSTARTED - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TXSTARTED - Write '1' to enable interrupt for event TXSTARTED - 20 - 20 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - LASTRX - Write '1' to enable interrupt for event LASTRX - 23 - 23 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - LASTTX - Write '1' to enable interrupt for event LASTTX - 24 - 24 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - STOPPED - Write '1' to disable interrupt for event STOPPED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ERROR - Write '1' to disable interrupt for event ERROR - 9 - 9 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - SUSPENDED - Write '1' to disable interrupt for event SUSPENDED - 18 - 18 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RXSTARTED - Write '1' to disable interrupt for event RXSTARTED - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TXSTARTED - Write '1' to disable interrupt for event TXSTARTED - 20 - 20 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - LASTRX - Write '1' to disable interrupt for event LASTRX - 23 - 23 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - LASTTX - Write '1' to disable interrupt for event LASTTX - 24 - 24 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - ERRORSRC - Error source - 0x4C4 - read-write - oneToClear - - - OVERRUN - Overrun error - 0 - 0 - - - NotReceived - Error did not occur - 0 - - - Received - Error occurred - 1 - - - - - ANACK - NACK received after sending the address (write '1' to clear) - 1 - 1 - - - NotReceived - Error did not occur - 0 - - - Received - Error occurred - 1 - - - - - DNACK - NACK received after sending a data byte (write '1' to clear) - 2 - 2 - - - NotReceived - Error did not occur - 0 - - - Received - Error occurred - 1 - - - - - - - ENABLE - Enable TWIM - 0x500 - read-write - - - ENABLE - Enable or disable TWIM - 0 - 3 - - - Disabled - Disable TWIM - 0 - - - Enabled - Enable TWIM - 6 - - - - - - - PSEL - Unspecified - TWIM_PSEL - read-write - 0x508 - - SCL - Pin select for SCL signal - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - SDA - Pin select for SDA signal - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - FREQUENCY - TWI frequency. Accuracy depends on the HFCLK source selected. - 0x524 - read-write - 0x04000000 - - - FREQUENCY - TWI master clock frequency - 0 - 31 - - - K100 - 100 kbps - 0x01980000 - - - K250 - 250 kbps - 0x04000000 - - - K400 - 400 kbps - 0x06400000 - - - - - - - RXD - RXD EasyDMA channel - TWIM_RXD - read-write - 0x534 - - PTR - Data pointer - 0x000 - read-write - - - PTR - Data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in receive buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in receive buffer - 0 - 13 - - - - - AMOUNT - Number of bytes transferred in the last transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. - 0 - 13 - - - - - LIST - EasyDMA list type - 0x00C - read-write - - - LIST - List type - 0 - 2 - - - Disabled - Disable EasyDMA list - 0 - - - ArrayList - Use array list - 1 - - - - - - - - TXD - TXD EasyDMA channel - TWIM_TXD - read-write - 0x544 - - PTR - Data pointer - 0x000 - read-write - - - PTR - Data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in transmit buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in transmit buffer - 0 - 13 - - - - - AMOUNT - Number of bytes transferred in the last transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. - 0 - 13 - - - - - LIST - EasyDMA list type - 0x00C - read-write - - - LIST - List type - 0 - 2 - - - Disabled - Disable EasyDMA list - 0 - - - ArrayList - Use array list - 1 - - - - - - - - ADDRESS - Address used in the TWI transfer - 0x588 - read-write - - - ADDRESS - Address used in the TWI transfer - 0 - 6 - - - - - - - TWIS0 - I2C compatible Two-Wire Slave Interface with EasyDMA - 0x40003000 - SPI0 - TWIS - - 0 - 0x1000 - registers - - - TWIM0_TWIS0_TWI0_SPIM0_SPIS0_SPI0 - 3 - - TWIS - 0x20 - - - TASKS_STOP - Stop TWI transaction - 0x014 - write-only - - - TASKS_STOP - Stop TWI transaction - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_SUSPEND - Suspend TWI transaction - 0x01C - write-only - - - TASKS_SUSPEND - Suspend TWI transaction - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_RESUME - Resume TWI transaction - 0x020 - write-only - - - TASKS_RESUME - Resume TWI transaction - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_PREPARERX - Prepare the TWI slave to respond to a write command - 0x030 - write-only - - - TASKS_PREPARERX - Prepare the TWI slave to respond to a write command - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_PREPARETX - Prepare the TWI slave to respond to a read command - 0x034 - write-only - - - TASKS_PREPARETX - Prepare the TWI slave to respond to a read command - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - EVENTS_STOPPED - TWI stopped - 0x104 - read-write - - - EVENTS_STOPPED - TWI stopped - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_ERROR - TWI error - 0x124 - read-write - - - EVENTS_ERROR - TWI error - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_RXSTARTED - Receive sequence started - 0x14C - read-write - - - EVENTS_RXSTARTED - Receive sequence started - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_TXSTARTED - Transmit sequence started - 0x150 - read-write - - - EVENTS_TXSTARTED - Transmit sequence started - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_WRITE - Write command received - 0x164 - read-write - - - EVENTS_WRITE - Write command received - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_READ - Read command received - 0x168 - read-write - - - EVENTS_READ - Read command received - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - SHORTS - Shortcuts between local events and tasks - 0x200 - read-write - - - WRITE_SUSPEND - Shortcut between event WRITE and task SUSPEND - 13 - 13 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - READ_SUSPEND - Shortcut between event READ and task SUSPEND - 14 - 14 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - - STOPPED - Enable or disable interrupt for event STOPPED - 1 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ERROR - Enable or disable interrupt for event ERROR - 9 - 9 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RXSTARTED - Enable or disable interrupt for event RXSTARTED - 19 - 19 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TXSTARTED - Enable or disable interrupt for event TXSTARTED - 20 - 20 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - WRITE - Enable or disable interrupt for event WRITE - 25 - 25 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - READ - Enable or disable interrupt for event READ - 26 - 26 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - STOPPED - Write '1' to enable interrupt for event STOPPED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ERROR - Write '1' to enable interrupt for event ERROR - 9 - 9 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RXSTARTED - Write '1' to enable interrupt for event RXSTARTED - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TXSTARTED - Write '1' to enable interrupt for event TXSTARTED - 20 - 20 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - WRITE - Write '1' to enable interrupt for event WRITE - 25 - 25 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - READ - Write '1' to enable interrupt for event READ - 26 - 26 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - STOPPED - Write '1' to disable interrupt for event STOPPED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ERROR - Write '1' to disable interrupt for event ERROR - 9 - 9 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RXSTARTED - Write '1' to disable interrupt for event RXSTARTED - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TXSTARTED - Write '1' to disable interrupt for event TXSTARTED - 20 - 20 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - WRITE - Write '1' to disable interrupt for event WRITE - 25 - 25 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - READ - Write '1' to disable interrupt for event READ - 26 - 26 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - ERRORSRC - Error source - 0x4D0 - read-write - oneToClear - - - OVERFLOW - RX buffer overflow detected, and prevented - 0 - 0 - - - NotDetected - Error did not occur - 0 - - - Detected - Error occurred - 1 - - - - - DNACK - NACK sent after receiving a data byte - 2 - 2 - - - NotReceived - Error did not occur - 0 - - - Received - Error occurred - 1 - - - - - OVERREAD - TX buffer over-read detected, and prevented - 3 - 3 - - - NotDetected - Error did not occur - 0 - - - Detected - Error occurred - 1 - - - - - - - MATCH - Status register indicating which address had a match - 0x4D4 - read-only - - - MATCH - Which of the addresses in {ADDRESS} matched the incoming address - 0 - 0 - - - - - ENABLE - Enable TWIS - 0x500 - read-write - - - ENABLE - Enable or disable TWIS - 0 - 3 - - - Disabled - Disable TWIS - 0 - - - Enabled - Enable TWIS - 9 - - - - - - - PSEL - Unspecified - TWIS_PSEL - read-write - 0x508 - - SCL - Pin select for SCL signal - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - SDA - Pin select for SDA signal - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - RXD - RXD EasyDMA channel - TWIS_RXD - read-write - 0x534 - - PTR - RXD Data pointer - 0x000 - read-write - - - PTR - RXD Data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in RXD buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in RXD buffer - 0 - 13 - - - - - AMOUNT - Number of bytes transferred in the last RXD transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last RXD transaction - 0 - 13 - - - - - LIST - EasyDMA list type - 0x00C - read-write - - - LIST - List type - 0 - 1 - - - Disabled - Disable EasyDMA list - 0 - - - ArrayList - Use array list - 1 - - - - - - - - TXD - TXD EasyDMA channel - TWIS_TXD - read-write - 0x544 - - PTR - TXD Data pointer - 0x000 - read-write - - - PTR - TXD Data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in TXD buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in TXD buffer - 0 - 13 - - - - - AMOUNT - Number of bytes transferred in the last TXD transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last TXD transaction - 0 - 13 - - - - - LIST - EasyDMA list type - 0x00C - read-write - - - LIST - List type - 0 - 1 - - - Disabled - Disable EasyDMA list - 0 - - - ArrayList - Use array list - 1 - - - - - - - - 0x2 - 0x4 - ADDRESS[%s] - Description collection: TWI slave address n - 0x588 - read-write - - - ADDRESS - TWI slave address - 0 - 6 - - - - - CONFIG - Configuration register for the address match mechanism - 0x594 - read-write - 0x00000001 - - - ADDRESS0 - Enable or disable address matching on ADDRESS[0] - 0 - 0 - - - Disabled - Disabled - 0 - - - Enabled - Enabled - 1 - - - - - ADDRESS1 - Enable or disable address matching on ADDRESS[1] - 1 - 1 - - - Disabled - Disabled - 0 - - - Enabled - Enabled - 1 - - - - - - - ORC - Over-read character. Character sent out in case of an over-read of the transmit buffer. - 0x5C0 - read-write - - - ORC - Over-read character. Character sent out in case of an over-read of the transmit buffer. - 0 - 7 - - - - - - - SPI1 - Serial Peripheral Interface 1 - 0x40004000 - - SPIM1_SPIS1_SPI1 - 4 - - - - SPIM1 - Serial Peripheral Interface Master with EasyDMA 1 - 0x40004000 - SPI1 - - SPIM1_SPIS1_SPI1 - 4 - - - - SPIS1 - SPI Slave 1 - 0x40004000 - SPI1 - - SPIM1_SPIS1_SPI1 - 4 - - - - GPIOTE - GPIO Tasks and Events - 0x40006000 - - 0 - 0x1000 - registers - - - GPIOTE - 6 - - GPIOTE - 0x20 - - - 0x8 - 0x4 - TASKS_OUT[%s] - Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. - 0x000 - write-only - - - TASKS_OUT - Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - 0x8 - 0x4 - TASKS_SET[%s] - Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. - 0x030 - write-only - - - TASKS_SET - Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - 0x8 - 0x4 - TASKS_CLR[%s] - Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. - 0x060 - write-only - - - TASKS_CLR - Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - 0x8 - 0x4 - EVENTS_IN[%s] - Description collection: Event generated from pin specified in CONFIG[n].PSEL - 0x100 - read-write - - - EVENTS_IN - Event generated from pin specified in CONFIG[n].PSEL - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_PORT - Event generated from multiple input GPIO pins with SENSE mechanism enabled - 0x17C - read-write - - - EVENTS_PORT - Event generated from multiple input GPIO pins with SENSE mechanism enabled - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - IN0 - Write '1' to enable interrupt for event IN[0] - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - IN1 - Write '1' to enable interrupt for event IN[1] - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - IN2 - Write '1' to enable interrupt for event IN[2] - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - IN3 - Write '1' to enable interrupt for event IN[3] - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - IN4 - Write '1' to enable interrupt for event IN[4] - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - IN5 - Write '1' to enable interrupt for event IN[5] - 5 - 5 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - IN6 - Write '1' to enable interrupt for event IN[6] - 6 - 6 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - IN7 - Write '1' to enable interrupt for event IN[7] - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - PORT - Write '1' to enable interrupt for event PORT - 31 - 31 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - IN0 - Write '1' to disable interrupt for event IN[0] - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - IN1 - Write '1' to disable interrupt for event IN[1] - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - IN2 - Write '1' to disable interrupt for event IN[2] - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - IN3 - Write '1' to disable interrupt for event IN[3] - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - IN4 - Write '1' to disable interrupt for event IN[4] - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - IN5 - Write '1' to disable interrupt for event IN[5] - 5 - 5 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - IN6 - Write '1' to disable interrupt for event IN[6] - 6 - 6 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - IN7 - Write '1' to disable interrupt for event IN[7] - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - PORT - Write '1' to disable interrupt for event PORT - 31 - 31 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - 0x8 - 0x4 - CONFIG[%s] - Description collection: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event - 0x510 - read-write - - - MODE - Mode - 0 - 1 - - - Disabled - Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. - 0 - - - Event - Event mode - 1 - - - Task - Task mode - 3 - - - - - PSEL - GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event - 8 - 12 - - - POLARITY - When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. - 16 - 17 - - - None - Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. - 0 - - - LoToHi - Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. - 1 - - - HiToLo - Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. - 2 - - - Toggle - Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. - 3 - - - - - OUTINIT - When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. - 20 - 20 - - - Low - Task mode: Initial value of pin before task triggering is low - 0 - - - High - Task mode: Initial value of pin before task triggering is high - 1 - - - - - - - - - SAADC - Analog to Digital Converter - 0x40007000 - - 0 - 0x1000 - registers - - - SAADC - 7 - - SAADC - 0x20 - - - TASKS_START - Start the ADC and prepare the result buffer in RAM - 0x000 - write-only - - - TASKS_START - Start the ADC and prepare the result buffer in RAM - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_SAMPLE - Take one ADC sample, if scan is enabled all channels are sampled - 0x004 - write-only - - - TASKS_SAMPLE - Take one ADC sample, if scan is enabled all channels are sampled - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STOP - Stop the ADC and terminate any on-going conversion - 0x008 - write-only - - - TASKS_STOP - Stop the ADC and terminate any on-going conversion - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_CALIBRATEOFFSET - Starts offset auto-calibration - 0x00C - write-only - - - TASKS_CALIBRATEOFFSET - Starts offset auto-calibration - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - EVENTS_STARTED - The ADC has started - 0x100 - read-write - - - EVENTS_STARTED - The ADC has started - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_END - The ADC has filled up the Result buffer - 0x104 - read-write - - - EVENTS_END - The ADC has filled up the Result buffer - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_DONE - A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. - 0x108 - read-write - - - EVENTS_DONE - A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_RESULTDONE - A result is ready to get transferred to RAM. - 0x10C - read-write - - - EVENTS_RESULTDONE - A result is ready to get transferred to RAM. - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_CALIBRATEDONE - Calibration is complete - 0x110 - read-write - - - EVENTS_CALIBRATEDONE - Calibration is complete - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_STOPPED - The ADC has stopped - 0x114 - read-write - - - EVENTS_STOPPED - The ADC has stopped - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - 8 - 0x008 - EVENTS_CH[%s] - Peripheral events. - SAADC_EVENTS_CH - read-write - 0x118 - - LIMITH - Description cluster: Last results is equal or above CH[n].LIMIT.HIGH - 0x000 - read-write - - - LIMITH - Last results is equal or above CH[n].LIMIT.HIGH - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - LIMITL - Description cluster: Last results is equal or below CH[n].LIMIT.LOW - 0x004 - read-write - - - LIMITL - Last results is equal or below CH[n].LIMIT.LOW - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - - STARTED - Enable or disable interrupt for event STARTED - 0 - 0 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - END - Enable or disable interrupt for event END - 1 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - DONE - Enable or disable interrupt for event DONE - 2 - 2 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RESULTDONE - Enable or disable interrupt for event RESULTDONE - 3 - 3 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - CALIBRATEDONE - Enable or disable interrupt for event CALIBRATEDONE - 4 - 4 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - STOPPED - Enable or disable interrupt for event STOPPED - 5 - 5 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - CH0LIMITH - Enable or disable interrupt for event CH0LIMITH - 6 - 6 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - CH0LIMITL - Enable or disable interrupt for event CH0LIMITL - 7 - 7 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - CH1LIMITH - Enable or disable interrupt for event CH1LIMITH - 8 - 8 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - CH1LIMITL - Enable or disable interrupt for event CH1LIMITL - 9 - 9 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - CH2LIMITH - Enable or disable interrupt for event CH2LIMITH - 10 - 10 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - CH2LIMITL - Enable or disable interrupt for event CH2LIMITL - 11 - 11 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - CH3LIMITH - Enable or disable interrupt for event CH3LIMITH - 12 - 12 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - CH3LIMITL - Enable or disable interrupt for event CH3LIMITL - 13 - 13 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - CH4LIMITH - Enable or disable interrupt for event CH4LIMITH - 14 - 14 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - CH4LIMITL - Enable or disable interrupt for event CH4LIMITL - 15 - 15 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - CH5LIMITH - Enable or disable interrupt for event CH5LIMITH - 16 - 16 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - CH5LIMITL - Enable or disable interrupt for event CH5LIMITL - 17 - 17 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - CH6LIMITH - Enable or disable interrupt for event CH6LIMITH - 18 - 18 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - CH6LIMITL - Enable or disable interrupt for event CH6LIMITL - 19 - 19 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - CH7LIMITH - Enable or disable interrupt for event CH7LIMITH - 20 - 20 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - CH7LIMITL - Enable or disable interrupt for event CH7LIMITL - 21 - 21 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - STARTED - Write '1' to enable interrupt for event STARTED - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - END - Write '1' to enable interrupt for event END - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - DONE - Write '1' to enable interrupt for event DONE - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RESULTDONE - Write '1' to enable interrupt for event RESULTDONE - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CALIBRATEDONE - Write '1' to enable interrupt for event CALIBRATEDONE - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - STOPPED - Write '1' to enable interrupt for event STOPPED - 5 - 5 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CH0LIMITH - Write '1' to enable interrupt for event CH0LIMITH - 6 - 6 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CH0LIMITL - Write '1' to enable interrupt for event CH0LIMITL - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CH1LIMITH - Write '1' to enable interrupt for event CH1LIMITH - 8 - 8 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CH1LIMITL - Write '1' to enable interrupt for event CH1LIMITL - 9 - 9 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CH2LIMITH - Write '1' to enable interrupt for event CH2LIMITH - 10 - 10 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CH2LIMITL - Write '1' to enable interrupt for event CH2LIMITL - 11 - 11 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CH3LIMITH - Write '1' to enable interrupt for event CH3LIMITH - 12 - 12 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CH3LIMITL - Write '1' to enable interrupt for event CH3LIMITL - 13 - 13 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CH4LIMITH - Write '1' to enable interrupt for event CH4LIMITH - 14 - 14 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CH4LIMITL - Write '1' to enable interrupt for event CH4LIMITL - 15 - 15 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CH5LIMITH - Write '1' to enable interrupt for event CH5LIMITH - 16 - 16 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CH5LIMITL - Write '1' to enable interrupt for event CH5LIMITL - 17 - 17 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CH6LIMITH - Write '1' to enable interrupt for event CH6LIMITH - 18 - 18 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CH6LIMITL - Write '1' to enable interrupt for event CH6LIMITL - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CH7LIMITH - Write '1' to enable interrupt for event CH7LIMITH - 20 - 20 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CH7LIMITL - Write '1' to enable interrupt for event CH7LIMITL - 21 - 21 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - STARTED - Write '1' to disable interrupt for event STARTED - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - END - Write '1' to disable interrupt for event END - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - DONE - Write '1' to disable interrupt for event DONE - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RESULTDONE - Write '1' to disable interrupt for event RESULTDONE - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CALIBRATEDONE - Write '1' to disable interrupt for event CALIBRATEDONE - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - STOPPED - Write '1' to disable interrupt for event STOPPED - 5 - 5 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CH0LIMITH - Write '1' to disable interrupt for event CH0LIMITH - 6 - 6 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CH0LIMITL - Write '1' to disable interrupt for event CH0LIMITL - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CH1LIMITH - Write '1' to disable interrupt for event CH1LIMITH - 8 - 8 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CH1LIMITL - Write '1' to disable interrupt for event CH1LIMITL - 9 - 9 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CH2LIMITH - Write '1' to disable interrupt for event CH2LIMITH - 10 - 10 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CH2LIMITL - Write '1' to disable interrupt for event CH2LIMITL - 11 - 11 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CH3LIMITH - Write '1' to disable interrupt for event CH3LIMITH - 12 - 12 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CH3LIMITL - Write '1' to disable interrupt for event CH3LIMITL - 13 - 13 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CH4LIMITH - Write '1' to disable interrupt for event CH4LIMITH - 14 - 14 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CH4LIMITL - Write '1' to disable interrupt for event CH4LIMITL - 15 - 15 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CH5LIMITH - Write '1' to disable interrupt for event CH5LIMITH - 16 - 16 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CH5LIMITL - Write '1' to disable interrupt for event CH5LIMITL - 17 - 17 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CH6LIMITH - Write '1' to disable interrupt for event CH6LIMITH - 18 - 18 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CH6LIMITL - Write '1' to disable interrupt for event CH6LIMITL - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CH7LIMITH - Write '1' to disable interrupt for event CH7LIMITH - 20 - 20 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CH7LIMITL - Write '1' to disable interrupt for event CH7LIMITL - 21 - 21 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - STATUS - Status - 0x400 - read-only - - - STATUS - Status - 0 - 0 - - - Ready - ADC is ready. No on-going conversion. - 0 - - - Busy - ADC is busy. Conversion in progress. - 1 - - - - - - - ENABLE - Enable or disable ADC - 0x500 - read-write - - - ENABLE - Enable or disable ADC - 0 - 0 - - - Disabled - Disable ADC - 0 - - - Enabled - Enable ADC - 1 - - - - - - - 8 - 0x010 - CH[%s] - Unspecified - SAADC_CH - read-write - 0x510 - - PSELP - Description cluster: Input positive pin selection for CH[n] - 0x000 - read-write - 0x00000000 - - - PSELP - Analog positive input channel - 0 - 4 - - - NC - Not connected - 0 - - - AnalogInput0 - AIN0 - 1 - - - AnalogInput1 - AIN1 - 2 - - - AnalogInput2 - AIN2 - 3 - - - AnalogInput3 - AIN3 - 4 - - - AnalogInput4 - AIN4 - 5 - - - AnalogInput5 - AIN5 - 6 - - - AnalogInput6 - AIN6 - 7 - - - AnalogInput7 - AIN7 - 8 - - - VDD - VDD - 9 - - - - - - - PSELN - Description cluster: Input negative pin selection for CH[n] - 0x004 - read-write - 0x00000000 - - - PSELN - Analog negative input, enables differential channel - 0 - 4 - - - NC - Not connected - 0 - - - AnalogInput0 - AIN0 - 1 - - - AnalogInput1 - AIN1 - 2 - - - AnalogInput2 - AIN2 - 3 - - - AnalogInput3 - AIN3 - 4 - - - AnalogInput4 - AIN4 - 5 - - - AnalogInput5 - AIN5 - 6 - - - AnalogInput6 - AIN6 - 7 - - - AnalogInput7 - AIN7 - 8 - - - VDD - VDD - 9 - - - - - - - CONFIG - Description cluster: Input configuration for CH[n] - 0x008 - read-write - 0x00020000 - - - RESP - Positive channel resistor control - 0 - 1 - - - Bypass - Bypass resistor ladder - 0 - - - Pulldown - Pull-down to GND - 1 - - - Pullup - Pull-up to VDD - 2 - - - VDD1_2 - Set input at VDD/2 - 3 - - - - - RESN - Negative channel resistor control - 4 - 5 - - - Bypass - Bypass resistor ladder - 0 - - - Pulldown - Pull-down to GND - 1 - - - Pullup - Pull-up to VDD - 2 - - - VDD1_2 - Set input at VDD/2 - 3 - - - - - GAIN - Gain control - 8 - 10 - - - Gain1_6 - 1/6 - 0 - - - Gain1_5 - 1/5 - 1 - - - Gain1_4 - 1/4 - 2 - - - Gain1_3 - 1/3 - 3 - - - Gain1_2 - 1/2 - 4 - - - Gain1 - 1 - 5 - - - Gain2 - 2 - 6 - - - Gain4 - 4 - 7 - - - - - REFSEL - Reference control - 12 - 12 - - - Internal - Internal reference (0.6 V) - 0 - - - VDD1_4 - VDD/4 as reference - 1 - - - - - TACQ - Acquisition time, the time the ADC uses to sample the input voltage - 16 - 18 - - - 3us - 3 us - 0 - - - 5us - 5 us - 1 - - - 10us - 10 us - 2 - - - 15us - 15 us - 3 - - - 20us - 20 us - 4 - - - 40us - 40 us - 5 - - - - - MODE - Enable differential mode - 20 - 20 - - - SE - Single ended, PSELN will be ignored, negative input to ADC shorted to GND - 0 - - - Diff - Differential - 1 - - - - - BURST - Enable burst mode - 24 - 24 - - - Disabled - Burst mode is disabled (normal operation) - 0 - - - Enabled - Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. - 1 - - - - - - - LIMIT - Description cluster: High/low limits for event monitoring a channel - 0x00C - read-write - 0x7FFF8000 - - - LOW - Low level limit - 0 - 15 - - - HIGH - High level limit - 16 - 31 - - - - - - RESOLUTION - Resolution configuration - 0x5F0 - read-write - 0x00000001 - - - VAL - Set the resolution - 0 - 2 - - - 8bit - 8 bit - 0 - - - 10bit - 10 bit - 1 - - - 12bit - 12 bit - 2 - - - 14bit - 14 bit - 3 - - - - - - - OVERSAMPLE - Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. - 0x5F4 - read-write - - - OVERSAMPLE - Oversample control - 0 - 3 - - - Bypass - Bypass oversampling - 0 - - - Over2x - Oversample 2x - 1 - - - Over4x - Oversample 4x - 2 - - - Over8x - Oversample 8x - 3 - - - Over16x - Oversample 16x - 4 - - - Over32x - Oversample 32x - 5 - - - Over64x - Oversample 64x - 6 - - - Over128x - Oversample 128x - 7 - - - Over256x - Oversample 256x - 8 - - - - - - - SAMPLERATE - Controls normal or continuous sample rate - 0x5F8 - read-write - - - CC - Capture and compare value. Sample rate is 16 MHz/CC - 0 - 10 - - - MODE - Select mode for sample rate control - 12 - 12 - - - Task - Rate is controlled from SAMPLE task - 0 - - - Timers - Rate is controlled from local timer (use CC to control the rate) - 1 - - - - - - - RESULT - RESULT EasyDMA channel - SAADC_RESULT - read-write - 0x62C - - PTR - Data pointer - 0x000 - read-write - - - PTR - Data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of buffer words to transfer - 0x004 - read-write - - - MAXCNT - Maximum number of buffer words to transfer - 0 - 14 - - - - - AMOUNT - Number of buffer words transferred since last START - 0x008 - read-only - - - AMOUNT - Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. - 0 - 14 - - - - - - - - TIMER0 - Timer/Counter 0 - 0x40008000 - TIMER - - 0 - 0x1000 - registers - - - TIMER0 - 8 - - TIMER - 0x20 - - - TASKS_START - Start Timer - 0x000 - write-only - - - TASKS_START - Start Timer - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STOP - Stop Timer - 0x004 - write-only - - - TASKS_STOP - Stop Timer - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_COUNT - Increment Timer (Counter mode only) - 0x008 - write-only - - - TASKS_COUNT - Increment Timer (Counter mode only) - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_CLEAR - Clear time - 0x00C - write-only - - - TASKS_CLEAR - Clear time - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_SHUTDOWN - Deprecated register - Shut down timer - 0x010 - write-only - - - TASKS_SHUTDOWN - Deprecated field - Shut down timer - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - 0x6 - 0x4 - TASKS_CAPTURE[%s] - Description collection: Capture Timer value to CC[n] register - 0x040 - write-only - - - TASKS_CAPTURE - Capture Timer value to CC[n] register - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - 0x6 - 0x4 - EVENTS_COMPARE[%s] - Description collection: Compare event on CC[n] match - 0x140 - read-write - - - EVENTS_COMPARE - Compare event on CC[n] match - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - SHORTS - Shortcuts between local events and tasks - 0x200 - read-write - - - COMPARE0_CLEAR - Shortcut between event COMPARE[0] and task CLEAR - 0 - 0 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - COMPARE1_CLEAR - Shortcut between event COMPARE[1] and task CLEAR - 1 - 1 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - COMPARE2_CLEAR - Shortcut between event COMPARE[2] and task CLEAR - 2 - 2 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - COMPARE3_CLEAR - Shortcut between event COMPARE[3] and task CLEAR - 3 - 3 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - COMPARE4_CLEAR - Shortcut between event COMPARE[4] and task CLEAR - 4 - 4 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - COMPARE5_CLEAR - Shortcut between event COMPARE[5] and task CLEAR - 5 - 5 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - COMPARE0_STOP - Shortcut between event COMPARE[0] and task STOP - 8 - 8 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - COMPARE1_STOP - Shortcut between event COMPARE[1] and task STOP - 9 - 9 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - COMPARE2_STOP - Shortcut between event COMPARE[2] and task STOP - 10 - 10 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - COMPARE3_STOP - Shortcut between event COMPARE[3] and task STOP - 11 - 11 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - COMPARE4_STOP - Shortcut between event COMPARE[4] and task STOP - 12 - 12 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - COMPARE5_STOP - Shortcut between event COMPARE[5] and task STOP - 13 - 13 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - COMPARE0 - Write '1' to enable interrupt for event COMPARE[0] - 16 - 16 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - COMPARE1 - Write '1' to enable interrupt for event COMPARE[1] - 17 - 17 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - COMPARE2 - Write '1' to enable interrupt for event COMPARE[2] - 18 - 18 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - COMPARE3 - Write '1' to enable interrupt for event COMPARE[3] - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - COMPARE4 - Write '1' to enable interrupt for event COMPARE[4] - 20 - 20 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - COMPARE5 - Write '1' to enable interrupt for event COMPARE[5] - 21 - 21 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - COMPARE0 - Write '1' to disable interrupt for event COMPARE[0] - 16 - 16 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - COMPARE1 - Write '1' to disable interrupt for event COMPARE[1] - 17 - 17 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - COMPARE2 - Write '1' to disable interrupt for event COMPARE[2] - 18 - 18 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - COMPARE3 - Write '1' to disable interrupt for event COMPARE[3] - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - COMPARE4 - Write '1' to disable interrupt for event COMPARE[4] - 20 - 20 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - COMPARE5 - Write '1' to disable interrupt for event COMPARE[5] - 21 - 21 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - MODE - Timer mode selection - 0x504 - read-write - - - MODE - Timer mode - 0 - 1 - - - Timer - Select Timer mode - 0 - - - Counter - Deprecated enumerator - Select Counter mode - 1 - - - LowPowerCounter - Select Low Power Counter mode - 2 - - - - - - - BITMODE - Configure the number of bits used by the TIMER - 0x508 - read-write - - - BITMODE - Timer bit width - 0 - 1 - - - 16Bit - 16 bit timer bit width - 0 - - - 08Bit - 8 bit timer bit width - 1 - - - 24Bit - 24 bit timer bit width - 2 - - - 32Bit - 32 bit timer bit width - 3 - - - - - - - PRESCALER - Timer prescaler register - 0x510 - read-write - 0x00000004 - - - PRESCALER - Prescaler value - 0 - 3 - - - - - 0x6 - 0x4 - CC[%s] - Description collection: Capture/Compare register n - 0x540 - read-write - - - CC - Capture/Compare value - 0 - 31 - - - - - - - TIMER1 - Timer/Counter 1 - 0x40009000 - - TIMER1 - 9 - - - - TIMER2 - Timer/Counter 2 - 0x4000A000 - - TIMER2 - 10 - - - - RTC0 - Real time counter 0 - 0x4000B000 - RTC - - 0 - 0x1000 - registers - - - RTC0 - 11 - - RTC - 0x20 - - - TASKS_START - Start RTC COUNTER - 0x000 - write-only - - - TASKS_START - Start RTC COUNTER - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STOP - Stop RTC COUNTER - 0x004 - write-only - - - TASKS_STOP - Stop RTC COUNTER - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_CLEAR - Clear RTC COUNTER - 0x008 - write-only - - - TASKS_CLEAR - Clear RTC COUNTER - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_TRIGOVRFLW - Set COUNTER to 0xFFFFF0 - 0x00C - write-only - - - TASKS_TRIGOVRFLW - Set COUNTER to 0xFFFFF0 - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - EVENTS_TICK - Event on COUNTER increment - 0x100 - read-write - - - EVENTS_TICK - Event on COUNTER increment - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_OVRFLW - Event on COUNTER overflow - 0x104 - read-write - - - EVENTS_OVRFLW - Event on COUNTER overflow - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - 0x4 - 0x4 - EVENTS_COMPARE[%s] - Description collection: Compare event on CC[n] match - 0x140 - read-write - - - EVENTS_COMPARE - Compare event on CC[n] match - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - TICK - Write '1' to enable interrupt for event TICK - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - OVRFLW - Write '1' to enable interrupt for event OVRFLW - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - COMPARE0 - Write '1' to enable interrupt for event COMPARE[0] - 16 - 16 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - COMPARE1 - Write '1' to enable interrupt for event COMPARE[1] - 17 - 17 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - COMPARE2 - Write '1' to enable interrupt for event COMPARE[2] - 18 - 18 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - COMPARE3 - Write '1' to enable interrupt for event COMPARE[3] - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - TICK - Write '1' to disable interrupt for event TICK - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - OVRFLW - Write '1' to disable interrupt for event OVRFLW - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - COMPARE0 - Write '1' to disable interrupt for event COMPARE[0] - 16 - 16 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - COMPARE1 - Write '1' to disable interrupt for event COMPARE[1] - 17 - 17 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - COMPARE2 - Write '1' to disable interrupt for event COMPARE[2] - 18 - 18 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - COMPARE3 - Write '1' to disable interrupt for event COMPARE[3] - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - EVTEN - Enable or disable event routing - 0x340 - read-write - - - TICK - Enable or disable event routing for event TICK - 0 - 0 - - - Disabled - Disable - 0 - - - Enabled - Disable - 1 - - - - - OVRFLW - Enable or disable event routing for event OVRFLW - 1 - 1 - - - Disabled - Disable - 0 - - - Enabled - Disable - 1 - - - - - COMPARE0 - Enable or disable event routing for event COMPARE[0] - 16 - 16 - - - Disabled - Disable - 0 - - - Enabled - Disable - 1 - - - - - COMPARE1 - Enable or disable event routing for event COMPARE[1] - 17 - 17 - - - Disabled - Disable - 0 - - - Enabled - Disable - 1 - - - - - COMPARE2 - Enable or disable event routing for event COMPARE[2] - 18 - 18 - - - Disabled - Disable - 0 - - - Enabled - Disable - 1 - - - - - COMPARE3 - Enable or disable event routing for event COMPARE[3] - 19 - 19 - - - Disabled - Disable - 0 - - - Enabled - Disable - 1 - - - - - - - EVTENSET - Enable event routing - 0x344 - read-write - - - TICK - Write '1' to enable event routing for event TICK - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - OVRFLW - Write '1' to enable event routing for event OVRFLW - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - COMPARE0 - Write '1' to enable event routing for event COMPARE[0] - 16 - 16 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - COMPARE1 - Write '1' to enable event routing for event COMPARE[1] - 17 - 17 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - COMPARE2 - Write '1' to enable event routing for event COMPARE[2] - 18 - 18 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - COMPARE3 - Write '1' to enable event routing for event COMPARE[3] - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - EVTENCLR - Disable event routing - 0x348 - read-write - - - TICK - Write '1' to disable event routing for event TICK - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - OVRFLW - Write '1' to disable event routing for event OVRFLW - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - COMPARE0 - Write '1' to disable event routing for event COMPARE[0] - 16 - 16 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - COMPARE1 - Write '1' to disable event routing for event COMPARE[1] - 17 - 17 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - COMPARE2 - Write '1' to disable event routing for event COMPARE[2] - 18 - 18 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - COMPARE3 - Write '1' to disable event routing for event COMPARE[3] - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - COUNTER - Current COUNTER value - 0x504 - read-only - - - COUNTER - Counter value - 0 - 23 - - - - - PRESCALER - 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped - 0x508 - read-write - - - PRESCALER - Prescaler value - 0 - 11 - - - - - 0x4 - 0x4 - CC[%s] - Description collection: Compare register n - 0x540 - read-write - - - COMPARE - Compare value - 0 - 23 - - - - - - - TEMP - Temperature Sensor - 0x4000C000 - - 0 - 0x1000 - registers - - - TEMP - 12 - - TEMP - 0x20 - - - TASKS_START - Start temperature measurement - 0x000 - write-only - - - TASKS_START - Start temperature measurement - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STOP - Stop temperature measurement - 0x004 - write-only - - - TASKS_STOP - Stop temperature measurement - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - EVENTS_DATARDY - Temperature measurement complete, data ready - 0x100 - read-write - - - EVENTS_DATARDY - Temperature measurement complete, data ready - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - DATARDY - Write '1' to enable interrupt for event DATARDY - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - DATARDY - Write '1' to disable interrupt for event DATARDY - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - TEMP - Temperature in degC (0.25deg steps) - 0x508 - read-only - int32_t - - - TEMP - Temperature in degC (0.25deg steps) - 0 - 31 - - - - - A0 - Slope of 1st piece wise linear function - 0x520 - read-write - 0x00000326 - - - A0 - Slope of 1st piece wise linear function - 0 - 11 - - - - - A1 - Slope of 2nd piece wise linear function - 0x524 - read-write - 0x00000348 - - - A1 - Slope of 2nd piece wise linear function - 0 - 11 - - - - - A2 - Slope of 3rd piece wise linear function - 0x528 - read-write - 0x000003AA - - - A2 - Slope of 3rd piece wise linear function - 0 - 11 - - - - - A3 - Slope of 4th piece wise linear function - 0x52C - read-write - 0x0000040E - - - A3 - Slope of 4th piece wise linear function - 0 - 11 - - - - - A4 - Slope of 5th piece wise linear function - 0x530 - read-write - 0x000004BD - - - A4 - Slope of 5th piece wise linear function - 0 - 11 - - - - - A5 - Slope of 6th piece wise linear function - 0x534 - read-write - 0x000005A3 - - - A5 - Slope of 6th piece wise linear function - 0 - 11 - - - - - B0 - y-intercept of 1st piece wise linear function - 0x540 - read-write - 0x00003FEF - - - B0 - y-intercept of 1st piece wise linear function - 0 - 13 - - - - - B1 - y-intercept of 2nd piece wise linear function - 0x544 - read-write - 0x00003FBE - - - B1 - y-intercept of 2nd piece wise linear function - 0 - 13 - - - - - B2 - y-intercept of 3rd piece wise linear function - 0x548 - read-write - 0x00003FBE - - - B2 - y-intercept of 3rd piece wise linear function - 0 - 13 - - - - - B3 - y-intercept of 4th piece wise linear function - 0x54C - read-write - 0x00000012 - - - B3 - y-intercept of 4th piece wise linear function - 0 - 13 - - - - - B4 - y-intercept of 5th piece wise linear function - 0x550 - read-write - 0x00000124 - - - B4 - y-intercept of 5th piece wise linear function - 0 - 13 - - - - - B5 - y-intercept of 6th piece wise linear function - 0x554 - read-write - 0x0000027C - - - B5 - y-intercept of 6th piece wise linear function - 0 - 13 - - - - - T0 - End point of 1st piece wise linear function - 0x560 - read-write - 0x000000E2 - - - T0 - End point of 1st piece wise linear function - 0 - 7 - - - - - T1 - End point of 2nd piece wise linear function - 0x564 - read-write - 0x00000000 - - - T1 - End point of 2nd piece wise linear function - 0 - 7 - - - - - T2 - End point of 3rd piece wise linear function - 0x568 - read-write - 0x00000019 - - - T2 - End point of 3rd piece wise linear function - 0 - 7 - - - - - T3 - End point of 4th piece wise linear function - 0x56C - read-write - 0x0000003C - - - T3 - End point of 4th piece wise linear function - 0 - 7 - - - - - T4 - End point of 5th piece wise linear function - 0x570 - read-write - 0x00000050 - - - T4 - End point of 5th piece wise linear function - 0 - 7 - - - - - - - RNG - Random Number Generator - 0x4000D000 - - 0 - 0x1000 - registers - - - RNG - 13 - - RNG - 0x20 - - - TASKS_START - Task starting the random number generator - 0x000 - write-only - - - TASKS_START - Task starting the random number generator - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STOP - Task stopping the random number generator - 0x004 - write-only - - - TASKS_STOP - Task stopping the random number generator - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - EVENTS_VALRDY - Event being generated for every new random number written to the VALUE register - 0x100 - read-write - - - EVENTS_VALRDY - Event being generated for every new random number written to the VALUE register - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - SHORTS - Shortcuts between local events and tasks - 0x200 - read-write - - - VALRDY_STOP - Shortcut between event VALRDY and task STOP - 0 - 0 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - VALRDY - Write '1' to enable interrupt for event VALRDY - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - VALRDY - Write '1' to disable interrupt for event VALRDY - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - CONFIG - Configuration register - 0x504 - read-write - - - DERCEN - Bias correction - 0 - 0 - - - Disabled - Disabled - 0 - - - Enabled - Enabled - 1 - - - - - - - VALUE - Output random number - 0x508 - read-only - - - VALUE - Generated random number - 0 - 7 - - - - - - - ECB - AES ECB Mode Encryption - 0x4000E000 - - 0 - 0x1000 - registers - - - ECB - 14 - - ECB - 0x20 - - - TASKS_STARTECB - Start ECB block encrypt - 0x000 - write-only - - - TASKS_STARTECB - Start ECB block encrypt - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STOPECB - Abort a possible executing ECB operation - 0x004 - write-only - - - TASKS_STOPECB - Abort a possible executing ECB operation - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - EVENTS_ENDECB - ECB block encrypt complete - 0x100 - read-write - - - EVENTS_ENDECB - ECB block encrypt complete - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_ERRORECB - ECB block encrypt aborted because of a STOPECB task or due to an error - 0x104 - read-write - - - EVENTS_ERRORECB - ECB block encrypt aborted because of a STOPECB task or due to an error - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - ENDECB - Write '1' to enable interrupt for event ENDECB - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ERRORECB - Write '1' to enable interrupt for event ERRORECB - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - ENDECB - Write '1' to disable interrupt for event ENDECB - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ERRORECB - Write '1' to disable interrupt for event ERRORECB - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - ECBDATAPTR - ECB block encrypt memory pointers - 0x504 - read-write - - - ECBDATAPTR - Pointer to the ECB data structure (see Table 1 ECB data structure overview) - 0 - 31 - - - - - - - AAR - Accelerated Address Resolver - 0x4000F000 - - 0 - 0x1000 - registers - - - CCM_AAR - 15 - - AAR - 0x20 - - - TASKS_START - Start resolving addresses based on IRKs specified in the IRK data structure - 0x000 - write-only - - - TASKS_START - Start resolving addresses based on IRKs specified in the IRK data structure - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STOP - Stop resolving addresses - 0x008 - write-only - - - TASKS_STOP - Stop resolving addresses - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - EVENTS_END - Address resolution procedure complete - 0x100 - read-write - - - EVENTS_END - Address resolution procedure complete - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_RESOLVED - Address resolved - 0x104 - read-write - - - EVENTS_RESOLVED - Address resolved - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_NOTRESOLVED - Address not resolved - 0x108 - read-write - - - EVENTS_NOTRESOLVED - Address not resolved - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - END - Write '1' to enable interrupt for event END - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RESOLVED - Write '1' to enable interrupt for event RESOLVED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - NOTRESOLVED - Write '1' to enable interrupt for event NOTRESOLVED - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - END - Write '1' to disable interrupt for event END - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RESOLVED - Write '1' to disable interrupt for event RESOLVED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - NOTRESOLVED - Write '1' to disable interrupt for event NOTRESOLVED - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - STATUS - Resolution status - 0x400 - read-only - - - STATUS - The IRK that was used last time an address was resolved - 0 - 3 - - - - - ENABLE - Enable AAR - 0x500 - read-write - - - ENABLE - Enable or disable AAR - 0 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 3 - - - - - - - NIRK - Number of IRKs - 0x504 - read-write - 0x00000001 - - - NIRK - Number of Identity root keys available in the IRK data structure - 0 - 4 - - - - - IRKPTR - Pointer to IRK data structure - 0x508 - read-write - - - IRKPTR - Pointer to the IRK data structure - 0 - 31 - - - - - ADDRPTR - Pointer to the resolvable address - 0x510 - read-write - - - ADDRPTR - Pointer to the resolvable address (6-bytes) - 0 - 31 - - - - - SCRATCHPTR - Pointer to data area used for temporary storage - 0x514 - read-write - - - SCRATCHPTR - Pointer to a scratch data area used for temporary storage during resolution. A space of minimum 3 bytes must be reserved. - 0 - 31 - - - - - - - CCM - AES CCM Mode Encryption - 0x4000F000 - AAR - - 0 - 0x1000 - registers - - - CCM_AAR - 15 - - CCM - 0x20 - - - TASKS_KSGEN - Start generation of key-stream. This operation will stop by itself when completed. - 0x000 - write-only - - - TASKS_KSGEN - Start generation of key-stream. This operation will stop by itself when completed. - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_CRYPT - Start encryption/decryption. This operation will stop by itself when completed. - 0x004 - write-only - - - TASKS_CRYPT - Start encryption/decryption. This operation will stop by itself when completed. - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STOP - Stop encryption/decryption - 0x008 - write-only - - - TASKS_STOP - Stop encryption/decryption - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_RATEOVERRIDE - Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption - 0x00C - write-only - - - TASKS_RATEOVERRIDE - Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - EVENTS_ENDKSGEN - Key-stream generation complete - 0x100 - read-write - - - EVENTS_ENDKSGEN - Key-stream generation complete - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_ENDCRYPT - Encrypt/decrypt complete - 0x104 - read-write - - - EVENTS_ENDCRYPT - Encrypt/decrypt complete - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_ERROR - Deprecated register - CCM error event - 0x108 - read-write - - - EVENTS_ERROR - Deprecated field - CCM error event - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - SHORTS - Shortcuts between local events and tasks - 0x200 - read-write - - - ENDKSGEN_CRYPT - Shortcut between event ENDKSGEN and task CRYPT - 0 - 0 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - ENDKSGEN - Write '1' to enable interrupt for event ENDKSGEN - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ENDCRYPT - Write '1' to enable interrupt for event ENDCRYPT - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ERROR - Deprecated intsetfield - Write '1' to enable interrupt for event ERROR - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - ENDKSGEN - Write '1' to disable interrupt for event ENDKSGEN - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ENDCRYPT - Write '1' to disable interrupt for event ENDCRYPT - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ERROR - Deprecated intclrfield - Write '1' to disable interrupt for event ERROR - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - MICSTATUS - MIC check result - 0x400 - read-only - - - MICSTATUS - The result of the MIC check performed during the previous decryption operation - 0 - 0 - - - CheckFailed - MIC check failed - 0 - - - CheckPassed - MIC check passed - 1 - - - - - - - ENABLE - Enable - 0x500 - read-write - - - ENABLE - Enable or disable CCM - 0 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 2 - - - - - - - MODE - Operation mode - 0x504 - read-write - 0x00000001 - - - MODE - The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered. - 0 - 0 - - - Encryption - AES CCM packet encryption mode - 0 - - - Decryption - AES CCM packet decryption mode - 1 - - - - - DATARATE - Radio data rate that the CCM shall run synchronous with - 16 - 17 - - - 1Mbit - 1 Mbps - 0 - - - 2Mbit - 2 Mbps - 1 - - - 125Kbps - 125 Kbps - 2 - - - 500Kbps - 500 Kbps - 3 - - - - - LENGTH - Packet length configuration - 24 - 24 - - - Default - Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packet payloads up to 27 bytes will be generated. - 0 - - - Extended - Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packet payloads up to MAXPACKETSIZE bytes will be generated. - 1 - - - - - - - CNFPTR - Pointer to data structure holding AES key and NONCE vector - 0x508 - read-write - - - CNFPTR - Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) - 0 - 31 - - - - - INPTR - Input pointer - 0x50C - read-write - - - INPTR - Input pointer - 0 - 31 - - - - - OUTPTR - Output pointer - 0x510 - read-write - - - OUTPTR - Output pointer - 0 - 31 - - - - - SCRATCHPTR - Pointer to data area used for temporary storage - 0x514 - read-write - - - SCRATCHPTR - Pointer to a scratch data area used for temporary storage during key-stream generation, - MIC generation and encryption/decryption. - 0 - 31 - - - - - MAXPACKETSIZE - Length of key-stream generated when MODE.LENGTH = Extended. - 0x518 - read-write - 0x000000FB - - - MAXPACKETSIZE - Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. - 0 - 7 - - - - - RATEOVERRIDE - Data rate override setting. - 0x51C - read-write - 0x00000000 - - - RATEOVERRIDE - Data rate override setting. - 0 - 1 - - - 1Mbit - 1 Mbps - 0 - - - 2Mbit - 2 Mbps - 1 - - - 125Kbps - 125 Kbps - 2 - - - 500Kbps - 500 Kbps - 3 - - - - - - - - - WDT - Watchdog Timer - 0x40010000 - - 0 - 0x1000 - registers - - - WDT - 16 - - WDT - 0x20 - - - TASKS_START - Start the watchdog - 0x000 - write-only - - - TASKS_START - Start the watchdog - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - EVENTS_TIMEOUT - Watchdog timeout - 0x100 - read-write - - - EVENTS_TIMEOUT - Watchdog timeout - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - TIMEOUT - Write '1' to enable interrupt for event TIMEOUT - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - TIMEOUT - Write '1' to disable interrupt for event TIMEOUT - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - RUNSTATUS - Run status - 0x400 - read-only - - - RUNSTATUS - Indicates whether or not the watchdog is running - 0 - 0 - - - NotRunning - Watchdog not running - 0 - - - Running - Watchdog is running - 1 - - - - - - - REQSTATUS - Request status - 0x404 - read-only - 0x00000001 - - - RR0 - Request status for RR[0] register - 0 - 0 - - - DisabledOrRequested - RR[0] register is not enabled, or are already requesting reload - 0 - - - EnabledAndUnrequested - RR[0] register is enabled, and are not yet requesting reload - 1 - - - - - RR1 - Request status for RR[1] register - 1 - 1 - - - DisabledOrRequested - RR[1] register is not enabled, or are already requesting reload - 0 - - - EnabledAndUnrequested - RR[1] register is enabled, and are not yet requesting reload - 1 - - - - - RR2 - Request status for RR[2] register - 2 - 2 - - - DisabledOrRequested - RR[2] register is not enabled, or are already requesting reload - 0 - - - EnabledAndUnrequested - RR[2] register is enabled, and are not yet requesting reload - 1 - - - - - RR3 - Request status for RR[3] register - 3 - 3 - - - DisabledOrRequested - RR[3] register is not enabled, or are already requesting reload - 0 - - - EnabledAndUnrequested - RR[3] register is enabled, and are not yet requesting reload - 1 - - - - - RR4 - Request status for RR[4] register - 4 - 4 - - - DisabledOrRequested - RR[4] register is not enabled, or are already requesting reload - 0 - - - EnabledAndUnrequested - RR[4] register is enabled, and are not yet requesting reload - 1 - - - - - RR5 - Request status for RR[5] register - 5 - 5 - - - DisabledOrRequested - RR[5] register is not enabled, or are already requesting reload - 0 - - - EnabledAndUnrequested - RR[5] register is enabled, and are not yet requesting reload - 1 - - - - - RR6 - Request status for RR[6] register - 6 - 6 - - - DisabledOrRequested - RR[6] register is not enabled, or are already requesting reload - 0 - - - EnabledAndUnrequested - RR[6] register is enabled, and are not yet requesting reload - 1 - - - - - RR7 - Request status for RR[7] register - 7 - 7 - - - DisabledOrRequested - RR[7] register is not enabled, or are already requesting reload - 0 - - - EnabledAndUnrequested - RR[7] register is enabled, and are not yet requesting reload - 1 - - - - - - - CRV - Counter reload value - 0x504 - read-write - 0xFFFFFFFF - - - CRV - Counter reload value in number of cycles of the 32.768 kHz clock - 0 - 31 - - - - - RREN - Enable register for reload request registers - 0x508 - read-write - 0x00000001 - - - RR0 - Enable or disable RR[0] register - 0 - 0 - - - Disabled - Disable RR[0] register - 0 - - - Enabled - Enable RR[0] register - 1 - - - - - RR1 - Enable or disable RR[1] register - 1 - 1 - - - Disabled - Disable RR[1] register - 0 - - - Enabled - Enable RR[1] register - 1 - - - - - RR2 - Enable or disable RR[2] register - 2 - 2 - - - Disabled - Disable RR[2] register - 0 - - - Enabled - Enable RR[2] register - 1 - - - - - RR3 - Enable or disable RR[3] register - 3 - 3 - - - Disabled - Disable RR[3] register - 0 - - - Enabled - Enable RR[3] register - 1 - - - - - RR4 - Enable or disable RR[4] register - 4 - 4 - - - Disabled - Disable RR[4] register - 0 - - - Enabled - Enable RR[4] register - 1 - - - - - RR5 - Enable or disable RR[5] register - 5 - 5 - - - Disabled - Disable RR[5] register - 0 - - - Enabled - Enable RR[5] register - 1 - - - - - RR6 - Enable or disable RR[6] register - 6 - 6 - - - Disabled - Disable RR[6] register - 0 - - - Enabled - Enable RR[6] register - 1 - - - - - RR7 - Enable or disable RR[7] register - 7 - 7 - - - Disabled - Disable RR[7] register - 0 - - - Enabled - Enable RR[7] register - 1 - - - - - - - CONFIG - Configuration register - 0x50C - read-write - 0x00000001 - - - SLEEP - Configure the watchdog to either be paused, or kept running, while the CPU is sleeping - 0 - 0 - - - Pause - Pause watchdog while the CPU is sleeping - 0 - - - Run - Keep the watchdog running while the CPU is sleeping - 1 - - - - - HALT - Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger - 3 - 3 - - - Pause - Pause watchdog while the CPU is halted by the debugger - 0 - - - Run - Keep the watchdog running while the CPU is halted by the debugger - 1 - - - - - - - 0x8 - 0x4 - RR[%s] - Description collection: Reload request n - 0x600 - write-only - - - RR - Reload request register - 0 - 31 - - - Reload - Value to request a reload of the watchdog timer - 0x6E524635 - - - - - - - - - RTC1 - Real time counter 1 - 0x40011000 - - RTC1 - 17 - - - - QDEC - Quadrature Decoder - 0x40012000 - - 0 - 0x1000 - registers - - - QDEC - 18 - - QDEC - 0x20 - - - TASKS_START - Task starting the quadrature decoder - 0x000 - write-only - - - TASKS_START - Task starting the quadrature decoder - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STOP - Task stopping the quadrature decoder - 0x004 - write-only - - - TASKS_STOP - Task stopping the quadrature decoder - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_READCLRACC - Read and clear ACC and ACCDBL - 0x008 - write-only - - - TASKS_READCLRACC - Read and clear ACC and ACCDBL - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_RDCLRACC - Read and clear ACC - 0x00C - write-only - - - TASKS_RDCLRACC - Read and clear ACC - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_RDCLRDBL - Read and clear ACCDBL - 0x010 - write-only - - - TASKS_RDCLRDBL - Read and clear ACCDBL - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - EVENTS_SAMPLERDY - Event being generated for every new sample value written to the SAMPLE register - 0x100 - read-write - - - EVENTS_SAMPLERDY - Event being generated for every new sample value written to the SAMPLE register - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_REPORTRDY - Non-null report ready - 0x104 - read-write - - - EVENTS_REPORTRDY - Non-null report ready - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_ACCOF - ACC or ACCDBL register overflow - 0x108 - read-write - - - EVENTS_ACCOF - ACC or ACCDBL register overflow - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_DBLRDY - Double displacement(s) detected - 0x10C - read-write - - - EVENTS_DBLRDY - Double displacement(s) detected - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_STOPPED - QDEC has been stopped - 0x110 - read-write - - - EVENTS_STOPPED - QDEC has been stopped - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - SHORTS - Shortcuts between local events and tasks - 0x200 - read-write - - - REPORTRDY_READCLRACC - Shortcut between event REPORTRDY and task READCLRACC - 0 - 0 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - SAMPLERDY_STOP - Shortcut between event SAMPLERDY and task STOP - 1 - 1 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - REPORTRDY_RDCLRACC - Shortcut between event REPORTRDY and task RDCLRACC - 2 - 2 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - REPORTRDY_STOP - Shortcut between event REPORTRDY and task STOP - 3 - 3 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - DBLRDY_RDCLRDBL - Shortcut between event DBLRDY and task RDCLRDBL - 4 - 4 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - DBLRDY_STOP - Shortcut between event DBLRDY and task STOP - 5 - 5 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - SAMPLERDY_READCLRACC - Shortcut between event SAMPLERDY and task READCLRACC - 6 - 6 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - SAMPLERDY - Write '1' to enable interrupt for event SAMPLERDY - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - REPORTRDY - Write '1' to enable interrupt for event REPORTRDY - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ACCOF - Write '1' to enable interrupt for event ACCOF - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - DBLRDY - Write '1' to enable interrupt for event DBLRDY - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - STOPPED - Write '1' to enable interrupt for event STOPPED - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - SAMPLERDY - Write '1' to disable interrupt for event SAMPLERDY - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - REPORTRDY - Write '1' to disable interrupt for event REPORTRDY - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ACCOF - Write '1' to disable interrupt for event ACCOF - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - DBLRDY - Write '1' to disable interrupt for event DBLRDY - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - STOPPED - Write '1' to disable interrupt for event STOPPED - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - ENABLE - Enable the quadrature decoder - 0x500 - read-write - - - ENABLE - Enable or disable the quadrature decoder - 0 - 0 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - LEDPOL - LED output pin polarity - 0x504 - read-write - - - LEDPOL - LED output pin polarity - 0 - 0 - - - ActiveLow - Led active on output pin low - 0 - - - ActiveHigh - Led active on output pin high - 1 - - - - - - - SAMPLEPER - Sample period - 0x508 - read-write - - - SAMPLEPER - Sample period. The SAMPLE register will be updated for every new sample - 0 - 3 - - - 128us - 128 us - 0 - - - 256us - 256 us - 1 - - - 512us - 512 us - 2 - - - 1024us - 1024 us - 3 - - - 2048us - 2048 us - 4 - - - 4096us - 4096 us - 5 - - - 8192us - 8192 us - 6 - - - 16384us - 16384 us - 7 - - - 32ms - 32768 us - 8 - - - 65ms - 65536 us - 9 - - - 131ms - 131072 us - 10 - - - - - - - SAMPLE - Motion sample value - 0x50C - read-only - int32_t - - - SAMPLE - Last motion sample - 0 - 31 - - - - - REPORTPER - Number of samples to be taken before REPORTRDY and DBLRDY events can be generated - 0x510 - read-write - - - REPORTPER - Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated - 0 - 3 - - - 10Smpl - 10 samples / report - 0 - - - 40Smpl - 40 samples / report - 1 - - - 80Smpl - 80 samples / report - 2 - - - 120Smpl - 120 samples / report - 3 - - - 160Smpl - 160 samples / report - 4 - - - 200Smpl - 200 samples / report - 5 - - - 240Smpl - 240 samples / report - 6 - - - 280Smpl - 280 samples / report - 7 - - - 1Smpl - 1 sample / report - 8 - - - - - - - ACC - Register accumulating the valid transitions - 0x514 - read-only - int32_t - - - ACC - Register accumulating all valid samples (not double transition) read from the SAMPLE register - 0 - 31 - - - - - ACCREAD - Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task - 0x518 - read-only - int32_t - - - ACCREAD - Snapshot of the ACC register. - 0 - 31 - - - - - PSEL - Unspecified - QDEC_PSEL - read-write - 0x51C - - LED - Pin select for LED signal - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - A - Pin select for A signal - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - B - Pin select for B signal - 0x008 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - DBFEN - Enable input debounce filters - 0x528 - read-write - - - DBFEN - Enable input debounce filters - 0 - 0 - - - Disabled - Debounce input filters disabled - 0 - - - Enabled - Debounce input filters enabled - 1 - - - - - - - LEDPRE - Time period the LED is switched ON prior to sampling - 0x540 - read-write - 0x00000010 - - - LEDPRE - Period in us the LED is switched on prior to sampling - 0 - 8 - - - - - ACCDBL - Register accumulating the number of detected double transitions - 0x544 - read-only - - - ACCDBL - Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). - 0 - 3 - - - - - ACCDBLREAD - Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task - 0x548 - read-only - - - ACCDBLREAD - Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. - 0 - 3 - - - - - - - COMP - Comparator - 0x40013000 - - 0 - 0x1000 - registers - - - COMP - 19 - - COMP - 0x20 - - - TASKS_START - Start comparator - 0x000 - write-only - - - TASKS_START - Start comparator - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STOP - Stop comparator - 0x004 - write-only - - - TASKS_STOP - Stop comparator - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_SAMPLE - Sample comparator value - 0x008 - write-only - - - TASKS_SAMPLE - Sample comparator value - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - EVENTS_READY - COMP is ready and output is valid - 0x100 - read-write - - - EVENTS_READY - COMP is ready and output is valid - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_DOWN - Downward crossing - 0x104 - read-write - - - EVENTS_DOWN - Downward crossing - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_UP - Upward crossing - 0x108 - read-write - - - EVENTS_UP - Upward crossing - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_CROSS - Downward or upward crossing - 0x10C - read-write - - - EVENTS_CROSS - Downward or upward crossing - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - SHORTS - Shortcuts between local events and tasks - 0x200 - read-write - - - READY_SAMPLE - Shortcut between event READY and task SAMPLE - 0 - 0 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - READY_STOP - Shortcut between event READY and task STOP - 1 - 1 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - DOWN_STOP - Shortcut between event DOWN and task STOP - 2 - 2 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - UP_STOP - Shortcut between event UP and task STOP - 3 - 3 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - CROSS_STOP - Shortcut between event CROSS and task STOP - 4 - 4 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - - READY - Enable or disable interrupt for event READY - 0 - 0 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - DOWN - Enable or disable interrupt for event DOWN - 1 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - UP - Enable or disable interrupt for event UP - 2 - 2 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - CROSS - Enable or disable interrupt for event CROSS - 3 - 3 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - READY - Write '1' to enable interrupt for event READY - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - DOWN - Write '1' to enable interrupt for event DOWN - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - UP - Write '1' to enable interrupt for event UP - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CROSS - Write '1' to enable interrupt for event CROSS - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - READY - Write '1' to disable interrupt for event READY - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - DOWN - Write '1' to disable interrupt for event DOWN - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - UP - Write '1' to disable interrupt for event UP - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CROSS - Write '1' to disable interrupt for event CROSS - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - RESULT - Compare result - 0x400 - read-only - - - RESULT - Result of last compare. Decision point SAMPLE task. - 0 - 0 - - - Below - Input voltage is below the threshold (VIN+ &lt; VIN-) - 0 - - - Above - Input voltage is above the threshold (VIN+ &gt; VIN-) - 1 - - - - - - - ENABLE - COMP enable - 0x500 - read-write - - - ENABLE - Enable or disable COMP - 0 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 2 - - - - - - - PSEL - Pin select - 0x504 - read-write - - - PSEL - Analog pin select - 0 - 2 - - - AnalogInput0 - AIN0 selected as analog input - 0 - - - AnalogInput1 - AIN1 selected as analog input - 1 - - - AnalogInput2 - AIN2 selected as analog input - 2 - - - AnalogInput3 - AIN3 selected as analog input - 3 - - - AnalogInput4 - AIN4 selected as analog input - 4 - - - AnalogInput5 - AIN5 selected as analog input - 5 - - - AnalogInput6 - AIN6 selected as analog input - 6 - - - VddDiv2 - VDD/2 selected as analog input - 7 - - - - - - - REFSEL - Reference source select for single-ended mode - 0x508 - read-write - 0x00000004 - - - REFSEL - Reference select - 0 - 2 - - - Int1V2 - VREF = internal 1.2 V reference (VDD &gt;= 1.7 V) - 0 - - - Int1V8 - VREF = internal 1.8 V reference (VDD &gt;= VREF + 0.2 V) - 1 - - - Int2V4 - VREF = internal 2.4 V reference (VDD &gt;= VREF + 0.2 V) - 2 - - - VDD - VREF = VDD - 4 - - - ARef - VREF = AREF (VDD &gt;= VREF &gt;= AREFMIN) - 5 - - - - - - - EXTREFSEL - External reference select - 0x50C - read-write - - - EXTREFSEL - External analog reference select - 0 - 2 - - - AnalogReference0 - Use AIN0 as external analog reference - 0 - - - AnalogReference1 - Use AIN1 as external analog reference - 1 - - - AnalogReference2 - Use AIN2 as external analog reference - 2 - - - AnalogReference3 - Use AIN3 as external analog reference - 3 - - - AnalogReference4 - Use AIN4 as external analog reference - 4 - - - AnalogReference5 - Use AIN5 as external analog reference - 5 - - - AnalogReference6 - Use AIN6 as external analog reference - 6 - - - AnalogReference7 - Use AIN7 as external analog reference - 7 - - - - - - - TH - Threshold configuration for hysteresis unit - 0x530 - read-write - 0x00000000 - - - THDOWN - VDOWN = (THDOWN+1)/64*VREF - 0 - 5 - - - THUP - VUP = (THUP+1)/64*VREF - 8 - 13 - - - - - MODE - Mode configuration - 0x534 - read-write - - - SP - Speed and power modes - 0 - 1 - - - Low - Low-power mode - 0 - - - Normal - Normal mode - 1 - - - High - High-speed mode - 2 - - - - - MAIN - Main operation modes - 8 - 8 - - - SE - Single-ended mode - 0 - - - Diff - Differential mode - 1 - - - - - - - HYST - Comparator hysteresis enable - 0x538 - read-write - - - HYST - Comparator hysteresis - 0 - 0 - - - NoHyst - Comparator hysteresis disabled - 0 - - - Hyst50mV - Comparator hysteresis enabled - 1 - - - - - - - - - EGU0 - Event Generator Unit 0 - 0x40014000 - EGU - - 0 - 0x1000 - registers - - - SWI0_EGU0 - 20 - - EGU - 0x20 - - - 0x10 - 0x4 - TASKS_TRIGGER[%s] - Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event - 0x000 - write-only - - - TASKS_TRIGGER - Trigger n for triggering the corresponding TRIGGERED[n] event - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - 0x10 - 0x4 - EVENTS_TRIGGERED[%s] - Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task - 0x100 - read-write - - - EVENTS_TRIGGERED - Event number n generated by triggering the corresponding TRIGGER[n] task - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - - TRIGGERED0 - Enable or disable interrupt for event TRIGGERED[0] - 0 - 0 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED1 - Enable or disable interrupt for event TRIGGERED[1] - 1 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED2 - Enable or disable interrupt for event TRIGGERED[2] - 2 - 2 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED3 - Enable or disable interrupt for event TRIGGERED[3] - 3 - 3 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED4 - Enable or disable interrupt for event TRIGGERED[4] - 4 - 4 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED5 - Enable or disable interrupt for event TRIGGERED[5] - 5 - 5 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED6 - Enable or disable interrupt for event TRIGGERED[6] - 6 - 6 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED7 - Enable or disable interrupt for event TRIGGERED[7] - 7 - 7 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED8 - Enable or disable interrupt for event TRIGGERED[8] - 8 - 8 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED9 - Enable or disable interrupt for event TRIGGERED[9] - 9 - 9 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED10 - Enable or disable interrupt for event TRIGGERED[10] - 10 - 10 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED11 - Enable or disable interrupt for event TRIGGERED[11] - 11 - 11 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED12 - Enable or disable interrupt for event TRIGGERED[12] - 12 - 12 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED13 - Enable or disable interrupt for event TRIGGERED[13] - 13 - 13 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED14 - Enable or disable interrupt for event TRIGGERED[14] - 14 - 14 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED15 - Enable or disable interrupt for event TRIGGERED[15] - 15 - 15 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - TRIGGERED0 - Write '1' to enable interrupt for event TRIGGERED[0] - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TRIGGERED1 - Write '1' to enable interrupt for event TRIGGERED[1] - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TRIGGERED2 - Write '1' to enable interrupt for event TRIGGERED[2] - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TRIGGERED3 - Write '1' to enable interrupt for event TRIGGERED[3] - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TRIGGERED4 - Write '1' to enable interrupt for event TRIGGERED[4] - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TRIGGERED5 - Write '1' to enable interrupt for event TRIGGERED[5] - 5 - 5 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TRIGGERED6 - Write '1' to enable interrupt for event TRIGGERED[6] - 6 - 6 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TRIGGERED7 - Write '1' to enable interrupt for event TRIGGERED[7] - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TRIGGERED8 - Write '1' to enable interrupt for event TRIGGERED[8] - 8 - 8 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TRIGGERED9 - Write '1' to enable interrupt for event TRIGGERED[9] - 9 - 9 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TRIGGERED10 - Write '1' to enable interrupt for event TRIGGERED[10] - 10 - 10 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TRIGGERED11 - Write '1' to enable interrupt for event TRIGGERED[11] - 11 - 11 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TRIGGERED12 - Write '1' to enable interrupt for event TRIGGERED[12] - 12 - 12 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TRIGGERED13 - Write '1' to enable interrupt for event TRIGGERED[13] - 13 - 13 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TRIGGERED14 - Write '1' to enable interrupt for event TRIGGERED[14] - 14 - 14 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TRIGGERED15 - Write '1' to enable interrupt for event TRIGGERED[15] - 15 - 15 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - TRIGGERED0 - Write '1' to disable interrupt for event TRIGGERED[0] - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TRIGGERED1 - Write '1' to disable interrupt for event TRIGGERED[1] - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TRIGGERED2 - Write '1' to disable interrupt for event TRIGGERED[2] - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TRIGGERED3 - Write '1' to disable interrupt for event TRIGGERED[3] - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TRIGGERED4 - Write '1' to disable interrupt for event TRIGGERED[4] - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TRIGGERED5 - Write '1' to disable interrupt for event TRIGGERED[5] - 5 - 5 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TRIGGERED6 - Write '1' to disable interrupt for event TRIGGERED[6] - 6 - 6 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TRIGGERED7 - Write '1' to disable interrupt for event TRIGGERED[7] - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TRIGGERED8 - Write '1' to disable interrupt for event TRIGGERED[8] - 8 - 8 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TRIGGERED9 - Write '1' to disable interrupt for event TRIGGERED[9] - 9 - 9 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TRIGGERED10 - Write '1' to disable interrupt for event TRIGGERED[10] - 10 - 10 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TRIGGERED11 - Write '1' to disable interrupt for event TRIGGERED[11] - 11 - 11 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TRIGGERED12 - Write '1' to disable interrupt for event TRIGGERED[12] - 12 - 12 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TRIGGERED13 - Write '1' to disable interrupt for event TRIGGERED[13] - 13 - 13 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TRIGGERED14 - Write '1' to disable interrupt for event TRIGGERED[14] - 14 - 14 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TRIGGERED15 - Write '1' to disable interrupt for event TRIGGERED[15] - 15 - 15 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - - - SWI0 - Software interrupt 0 - 0x40014000 - EGU0 - SWI - - 0 - 0x1000 - registers - - - SWI0_EGU0 - 20 - - SWI - 0x20 - - - UNUSED - Unused. - 0x000 - 0x00000000 - read-only - - - - - EGU1 - Event Generator Unit 1 - 0x40015000 - - SWI1_EGU1 - 21 - - - - SWI1 - Software interrupt 1 - 0x40015000 - EGU1 - - SWI1_EGU1 - 21 - - - - SWI2 - Software interrupt 2 - 0x40016000 - - SWI2 - 22 - - - - SWI3 - Software interrupt 3 - 0x40017000 - - SWI3 - 23 - - - - SWI4 - Software interrupt 4 - 0x40018000 - - SWI4 - 24 - - - - SWI5 - Software interrupt 5 - 0x40019000 - - SWI5 - 25 - - - - PWM0 - Pulse width modulation unit - 0x4001C000 - PWM - - 0 - 0x1000 - registers - - - PWM0 - 28 - - PWM - 0x20 - - - TASKS_STOP - Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback - 0x004 - write-only - - - TASKS_STOP - Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - 0x2 - 0x4 - TASKS_SEQSTART[%s] - Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. - 0x008 - write-only - - - TASKS_SEQSTART - Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_NEXTSTEP - Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. - 0x010 - write-only - - - TASKS_NEXTSTEP - Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - EVENTS_STOPPED - Response to STOP task, emitted when PWM pulses are no longer generated - 0x104 - read-write - - - EVENTS_STOPPED - Response to STOP task, emitted when PWM pulses are no longer generated - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - 0x2 - 0x4 - EVENTS_SEQSTARTED[%s] - Description collection: First PWM period started on sequence n - 0x108 - read-write - - - EVENTS_SEQSTARTED - First PWM period started on sequence n - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - 0x2 - 0x4 - EVENTS_SEQEND[%s] - Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter - 0x110 - read-write - - - EVENTS_SEQEND - Emitted at end of every sequence n, when last value from RAM has been applied to wave counter - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_PWMPERIODEND - Emitted at the end of each PWM period - 0x118 - read-write - - - EVENTS_PWMPERIODEND - Emitted at the end of each PWM period - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_LOOPSDONE - Concatenated sequences have been played the amount of times defined in LOOP.CNT - 0x11C - read-write - - - EVENTS_LOOPSDONE - Concatenated sequences have been played the amount of times defined in LOOP.CNT - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - SHORTS - Shortcuts between local events and tasks - 0x200 - read-write - - - SEQEND0_STOP - Shortcut between event SEQEND[0] and task STOP - 0 - 0 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - SEQEND1_STOP - Shortcut between event SEQEND[1] and task STOP - 1 - 1 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - LOOPSDONE_SEQSTART0 - Shortcut between event LOOPSDONE and task SEQSTART[0] - 2 - 2 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - LOOPSDONE_SEQSTART1 - Shortcut between event LOOPSDONE and task SEQSTART[1] - 3 - 3 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - LOOPSDONE_STOP - Shortcut between event LOOPSDONE and task STOP - 4 - 4 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - - STOPPED - Enable or disable interrupt for event STOPPED - 1 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - SEQSTARTED0 - Enable or disable interrupt for event SEQSTARTED[0] - 2 - 2 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - SEQSTARTED1 - Enable or disable interrupt for event SEQSTARTED[1] - 3 - 3 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - SEQEND0 - Enable or disable interrupt for event SEQEND[0] - 4 - 4 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - SEQEND1 - Enable or disable interrupt for event SEQEND[1] - 5 - 5 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - PWMPERIODEND - Enable or disable interrupt for event PWMPERIODEND - 6 - 6 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - LOOPSDONE - Enable or disable interrupt for event LOOPSDONE - 7 - 7 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - STOPPED - Write '1' to enable interrupt for event STOPPED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - SEQSTARTED0 - Write '1' to enable interrupt for event SEQSTARTED[0] - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - SEQSTARTED1 - Write '1' to enable interrupt for event SEQSTARTED[1] - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - SEQEND0 - Write '1' to enable interrupt for event SEQEND[0] - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - SEQEND1 - Write '1' to enable interrupt for event SEQEND[1] - 5 - 5 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - PWMPERIODEND - Write '1' to enable interrupt for event PWMPERIODEND - 6 - 6 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - LOOPSDONE - Write '1' to enable interrupt for event LOOPSDONE - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - STOPPED - Write '1' to disable interrupt for event STOPPED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - SEQSTARTED0 - Write '1' to disable interrupt for event SEQSTARTED[0] - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - SEQSTARTED1 - Write '1' to disable interrupt for event SEQSTARTED[1] - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - SEQEND0 - Write '1' to disable interrupt for event SEQEND[0] - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - SEQEND1 - Write '1' to disable interrupt for event SEQEND[1] - 5 - 5 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - PWMPERIODEND - Write '1' to disable interrupt for event PWMPERIODEND - 6 - 6 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - LOOPSDONE - Write '1' to disable interrupt for event LOOPSDONE - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - ENABLE - PWM module enable register - 0x500 - read-write - 0x00000000 - - - ENABLE - Enable or disable PWM module - 0 - 0 - - - Disabled - Disabled - 0 - - - Enabled - Enable - 1 - - - - - - - MODE - Selects operating mode of the wave counter - 0x504 - read-write - 0x00000000 - - - UPDOWN - Selects up mode or up-and-down mode for the counter - 0 - 0 - - - Up - Up counter, edge-aligned PWM duty cycle - 0 - - - UpAndDown - Up and down counter, center-aligned PWM duty cycle - 1 - - - - - - - COUNTERTOP - Value up to which the pulse generator counter counts - 0x508 - read-write - 0x000003FF - - - COUNTERTOP - Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. - 0 - 14 - - - - - PRESCALER - Configuration for PWM_CLK - 0x50C - read-write - 0x00000000 - - - PRESCALER - Prescaler of PWM_CLK - 0 - 2 - - - DIV_1 - Divide by 1 (16 MHz) - 0 - - - DIV_2 - Divide by 2 (8 MHz) - 1 - - - DIV_4 - Divide by 4 (4 MHz) - 2 - - - DIV_8 - Divide by 8 (2 MHz) - 3 - - - DIV_16 - Divide by 16 (1 MHz) - 4 - - - DIV_32 - Divide by 32 (500 kHz) - 5 - - - DIV_64 - Divide by 64 (250 kHz) - 6 - - - DIV_128 - Divide by 128 (125 kHz) - 7 - - - - - - - DECODER - Configuration of the decoder - 0x510 - read-write - 0x00000000 - - - LOAD - How a sequence is read from RAM and spread to the compare register - 0 - 1 - - - Common - 1st half word (16-bit) used in all PWM channels 0..3 - 0 - - - Grouped - 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 - 1 - - - Individual - 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 - 2 - - - WaveForm - 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP - 3 - - - - - MODE - Selects source for advancing the active sequence - 8 - 8 - - - RefreshCount - SEQ[n].REFRESH is used to determine loading internal compare registers - 0 - - - NextStep - NEXTSTEP task causes a new value to be loaded to internal compare registers - 1 - - - - - - - LOOP - Number of playbacks of a loop - 0x514 - read-write - 0x00000000 - - - CNT - Number of playbacks of pattern cycles - 0 - 15 - - - Disabled - Looping disabled (stop at the end of the sequence) - 0 - - - - - - - 2 - 0x020 - SEQ[%s] - Unspecified - PWM_SEQ - read-write - 0x520 - - PTR - Description cluster: Beginning address in RAM of this sequence - 0x000 - read-write - 0x00000000 - - - PTR - Beginning address in RAM of this sequence - 0 - 31 - - - - - CNT - Description cluster: Number of values (duty cycles) in this sequence - 0x004 - read-write - 0x00000000 - - - CNT - Number of values (duty cycles) in this sequence - 0 - 14 - - - Disabled - Sequence is disabled, and shall not be started as it is empty - 0 - - - - - - - REFRESH - Description cluster: Number of additional PWM periods between samples loaded into compare register - 0x008 - read-write - 0x00000001 - - - CNT - Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) - 0 - 23 - - - Continuous - Update every PWM period - 0 - - - - - - - ENDDELAY - Description cluster: Time added after the sequence - 0x00C - read-write - 0x00000000 - - - CNT - Time added after the sequence in PWM periods - 0 - 23 - - - - - - PSEL - Unspecified - PWM_PSEL - read-write - 0x560 - - 0x4 - 0x4 - OUT[%s] - Description collection: Output pin select for PWM channel n - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - - - PDM - Pulse Density Modulation (Digital Microphone) Interface - 0x4001D000 - - 0 - 0x1000 - registers - - - PDM - 29 - - PDM - 0x20 - - - TASKS_START - Starts continuous PDM transfer - 0x000 - write-only - - - TASKS_START - Starts continuous PDM transfer - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STOP - Stops PDM transfer - 0x004 - write-only - - - TASKS_STOP - Stops PDM transfer - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - EVENTS_STARTED - PDM transfer has started - 0x100 - read-write - - - EVENTS_STARTED - PDM transfer has started - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_STOPPED - PDM transfer has finished - 0x104 - read-write - - - EVENTS_STOPPED - PDM transfer has finished - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_END - The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM - 0x108 - read-write - - - EVENTS_END - The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - - STARTED - Enable or disable interrupt for event STARTED - 0 - 0 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - STOPPED - Enable or disable interrupt for event STOPPED - 1 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - END - Enable or disable interrupt for event END - 2 - 2 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - STARTED - Write '1' to enable interrupt for event STARTED - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - STOPPED - Write '1' to enable interrupt for event STOPPED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - END - Write '1' to enable interrupt for event END - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - STARTED - Write '1' to disable interrupt for event STARTED - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - STOPPED - Write '1' to disable interrupt for event STOPPED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - END - Write '1' to disable interrupt for event END - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - ENABLE - PDM module enable register - 0x500 - read-write - 0x00000000 - - - ENABLE - Enable or disable PDM module - 0 - 0 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - PDMCLKCTRL - PDM clock generator control - 0x504 - read-write - 0x08400000 - - - FREQ - PDM_CLK frequency - 0 - 31 - - - 1000K - PDM_CLK = 32 MHz / 32 = 1.000 MHz - 0x08000000 - - - Default - PDM_CLK = 32 MHz / 31 = 1.032 MHz - 0x08400000 - - - 1067K - PDM_CLK = 32 MHz / 30 = 1.067 MHz - 0x08800000 - - - - - - - MODE - Defines the routing of the connected PDM microphones' signals - 0x508 - read-write - 0x00000000 - - - OPERATION - Mono or stereo operation - 0 - 0 - - - Stereo - Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] - 0 - - - Mono - Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] - 1 - - - - - EDGE - Defines on which PDM_CLK edge Left (or mono) is sampled - 1 - 1 - - - LeftFalling - Left (or mono) is sampled on falling edge of PDM_CLK - 0 - - - LeftRising - Left (or mono) is sampled on rising edge of PDM_CLK - 1 - - - - - - - GAINL - Left output gain adjustment - 0x518 - read-write - 0x00000028 - - - GAINL - Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust - 0 - 6 - - - MinGain - -20dB gain adjustment (minimum) - 0x00 - - - DefaultGain - 0dB gain adjustment ('2500 RMS' requirement) - 0x28 - - - MaxGain - +20dB gain adjustment (maximum) - 0x50 - - - - - - - GAINR - Right output gain adjustment - 0x51C - read-write - 0x00000028 - - - GAINR - Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) - 0 - 6 - - - MinGain - -20dB gain adjustment (minimum) - 0x00 - - - DefaultGain - 0dB gain adjustment ('2500 RMS' requirement) - 0x28 - - - MaxGain - +20dB gain adjustment (maximum) - 0x50 - - - - - - - PSEL - Unspecified - PDM_PSEL - read-write - 0x540 - - CLK - Pin number configuration for PDM CLK signal - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - DIN - Pin number configuration for PDM DIN signal - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - SAMPLE - Unspecified - PDM_SAMPLE - read-write - 0x560 - - PTR - RAM address pointer to write samples to with EasyDMA - 0x000 - read-write - - - SAMPLEPTR - Address to write PDM samples to over DMA - 0 - 31 - - - - - MAXCNT - Number of samples to allocate memory for in EasyDMA mode - 0x004 - read-write - - - BUFFSIZE - Length of DMA RAM allocation in number of samples - 0 - 14 - - - - - - - - NVMC - Non-volatile memory controller - 0x4001E000 - - 0 - 0x1000 - registers - - NVMC - 0x20 - - - READY - Ready flag - 0x400 - read-only - 0x00000001 - - - READY - NVMC is ready or busy - 0 - 0 - - - Busy - NVMC is busy (ongoing write or erase operation) - 0 - - - Ready - NVMC is ready - 1 - - - - - - - CONFIG - Configuration register - 0x504 - read-write - - - WEN - Program memory access mode. It is strongly recommended to activate erase and write modes only when they are actively used. - 0 - 1 - - - Ren - Read only access - 0 - - - Wen - Write enabled - 1 - - - Een - Erase enabled - 2 - - - - - - - ERASEPAGE - Register for erasing a page in code area - 0x508 - read-write - - - ERASEPAGE - Register for starting erase of a page in code area. - 0 - 31 - - - - - ERASEPCR1 - Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. - 0x508 - read-write - ERASEPAGE - - - ERASEPCR1 - Register for erasing a page in code area. Equivalent to ERASEPAGE. - 0 - 31 - - - - - ERASEALL - Register for erasing all non-volatile user memory - 0x50C - read-write - - - ERASEALL - Erase all non-volatile memory including UICR registers. Note that the erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased. - 0 - 0 - - - NoOperation - No operation - 0 - - - Erase - Start erase of chip - 1 - - - - - - - ERASEPCR0 - Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. - 0x510 - read-write - - - ERASEPCR0 - Register for starting erase of a page in code area. Equivalent to ERASEPAGE. - 0 - 31 - - - - - ERASEUICR - Register for erasing user information configuration registers - 0x514 - read-write - - - ERASEUICR - Register starting erase of all user information configuration registers. Note that the erase must be enabled using CONFIG.WEN before the UICR can be erased. - 0 - 0 - - - NoOperation - No operation - 0 - - - Erase - Start erase of UICR - 1 - - - - - - - ERASEPAGEPARTIAL - Register for partial erase of a page in code area - 0x518 - read-write - - - ERASEPAGEPARTIAL - Register for starting partial erase of a page in code area - 0 - 31 - - - - - ERASEPAGEPARTIALCFG - Register for partial erase configuration - 0x51C - read-write - 0x0000000A - - - DURATION - Duration of the partial erase in milliseconds - 0 - 6 - - - - - - - PPI - Programmable Peripheral Interconnect - 0x4001F000 - - 0 - 0x1000 - registers - - PPI - 0x20 - - - 6 - 0x008 - TASKS_CHG[%s] - Channel group tasks - PPI_TASKS_CHG - write-only - 0x000 - - EN - Description cluster: Enable channel group n - 0x000 - write-only - - - EN - Enable channel group n - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - DIS - Description cluster: Disable channel group n - 0x004 - write-only - - - DIS - Disable channel group n - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - - CHEN - Channel enable register - 0x500 - read-write - - - CH0 - Enable or disable channel 0 - 0 - 0 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH1 - Enable or disable channel 1 - 1 - 1 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH2 - Enable or disable channel 2 - 2 - 2 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH3 - Enable or disable channel 3 - 3 - 3 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH4 - Enable or disable channel 4 - 4 - 4 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH5 - Enable or disable channel 5 - 5 - 5 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH6 - Enable or disable channel 6 - 6 - 6 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH7 - Enable or disable channel 7 - 7 - 7 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH8 - Enable or disable channel 8 - 8 - 8 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH9 - Enable or disable channel 9 - 9 - 9 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH10 - Enable or disable channel 10 - 10 - 10 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH11 - Enable or disable channel 11 - 11 - 11 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH12 - Enable or disable channel 12 - 12 - 12 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH13 - Enable or disable channel 13 - 13 - 13 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH14 - Enable or disable channel 14 - 14 - 14 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH15 - Enable or disable channel 15 - 15 - 15 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH16 - Enable or disable channel 16 - 16 - 16 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH17 - Enable or disable channel 17 - 17 - 17 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH18 - Enable or disable channel 18 - 18 - 18 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH19 - Enable or disable channel 19 - 19 - 19 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH20 - Enable or disable channel 20 - 20 - 20 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH21 - Enable or disable channel 21 - 21 - 21 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH22 - Enable or disable channel 22 - 22 - 22 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH23 - Enable or disable channel 23 - 23 - 23 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH24 - Enable or disable channel 24 - 24 - 24 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH25 - Enable or disable channel 25 - 25 - 25 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH26 - Enable or disable channel 26 - 26 - 26 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH27 - Enable or disable channel 27 - 27 - 27 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH28 - Enable or disable channel 28 - 28 - 28 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH29 - Enable or disable channel 29 - 29 - 29 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH30 - Enable or disable channel 30 - 30 - 30 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH31 - Enable or disable channel 31 - 31 - 31 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - - - CHENSET - Channel enable set register - 0x504 - read-write - oneToSet - - - CH0 - Channel 0 enable set register. Writing '0' has no effect - 0 - 0 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH1 - Channel 1 enable set register. Writing '0' has no effect - 1 - 1 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH2 - Channel 2 enable set register. Writing '0' has no effect - 2 - 2 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH3 - Channel 3 enable set register. Writing '0' has no effect - 3 - 3 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH4 - Channel 4 enable set register. Writing '0' has no effect - 4 - 4 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH5 - Channel 5 enable set register. Writing '0' has no effect - 5 - 5 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH6 - Channel 6 enable set register. Writing '0' has no effect - 6 - 6 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH7 - Channel 7 enable set register. Writing '0' has no effect - 7 - 7 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH8 - Channel 8 enable set register. Writing '0' has no effect - 8 - 8 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH9 - Channel 9 enable set register. Writing '0' has no effect - 9 - 9 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH10 - Channel 10 enable set register. Writing '0' has no effect - 10 - 10 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH11 - Channel 11 enable set register. Writing '0' has no effect - 11 - 11 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH12 - Channel 12 enable set register. Writing '0' has no effect - 12 - 12 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH13 - Channel 13 enable set register. Writing '0' has no effect - 13 - 13 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH14 - Channel 14 enable set register. Writing '0' has no effect - 14 - 14 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH15 - Channel 15 enable set register. Writing '0' has no effect - 15 - 15 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH16 - Channel 16 enable set register. Writing '0' has no effect - 16 - 16 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH17 - Channel 17 enable set register. Writing '0' has no effect - 17 - 17 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH18 - Channel 18 enable set register. Writing '0' has no effect - 18 - 18 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH19 - Channel 19 enable set register. Writing '0' has no effect - 19 - 19 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH20 - Channel 20 enable set register. Writing '0' has no effect - 20 - 20 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH21 - Channel 21 enable set register. Writing '0' has no effect - 21 - 21 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH22 - Channel 22 enable set register. Writing '0' has no effect - 22 - 22 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH23 - Channel 23 enable set register. Writing '0' has no effect - 23 - 23 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH24 - Channel 24 enable set register. Writing '0' has no effect - 24 - 24 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH25 - Channel 25 enable set register. Writing '0' has no effect - 25 - 25 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH26 - Channel 26 enable set register. Writing '0' has no effect - 26 - 26 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH27 - Channel 27 enable set register. Writing '0' has no effect - 27 - 27 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH28 - Channel 28 enable set register. Writing '0' has no effect - 28 - 28 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH29 - Channel 29 enable set register. Writing '0' has no effect - 29 - 29 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH30 - Channel 30 enable set register. Writing '0' has no effect - 30 - 30 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH31 - Channel 31 enable set register. Writing '0' has no effect - 31 - 31 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - - - CHENCLR - Channel enable clear register - 0x508 - read-write - oneToClear - - - CH0 - Channel 0 enable clear register. Writing '0' has no effect - 0 - 0 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel - 1 - - - - - CH1 - Channel 1 enable clear register. Writing '0' has no effect - 1 - 1 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel - 1 - - - - - CH2 - Channel 2 enable clear register. Writing '0' has no effect - 2 - 2 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel - 1 - - - - - CH3 - Channel 3 enable clear register. Writing '0' has no effect - 3 - 3 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel - 1 - - - - - CH4 - Channel 4 enable clear register. Writing '0' has no effect - 4 - 4 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel - 1 - - - - - CH5 - Channel 5 enable clear register. Writing '0' has no effect - 5 - 5 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel - 1 - - - - - CH6 - Channel 6 enable clear register. Writing '0' has no effect - 6 - 6 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel - 1 - - - - - CH7 - Channel 7 enable clear register. Writing '0' has no effect - 7 - 7 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel - 1 - - - - - CH8 - Channel 8 enable clear register. Writing '0' has no effect - 8 - 8 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel - 1 - - - - - CH9 - Channel 9 enable clear register. Writing '0' has no effect - 9 - 9 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel - 1 - - - - - CH10 - Channel 10 enable clear register. Writing '0' has no effect - 10 - 10 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel - 1 - - - - - CH11 - Channel 11 enable clear register. Writing '0' has no effect - 11 - 11 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel - 1 - - - - - CH12 - Channel 12 enable clear register. Writing '0' has no effect - 12 - 12 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel - 1 - - - - - CH13 - Channel 13 enable clear register. Writing '0' has no effect - 13 - 13 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel - 1 - - - - - CH14 - Channel 14 enable clear register. Writing '0' has no effect - 14 - 14 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel - 1 - - - - - CH15 - Channel 15 enable clear register. Writing '0' has no effect - 15 - 15 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel - 1 - - - - - CH16 - Channel 16 enable clear register. Writing '0' has no effect - 16 - 16 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel - 1 - - - - - CH17 - Channel 17 enable clear register. Writing '0' has no effect - 17 - 17 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel - 1 - - - - - CH18 - Channel 18 enable clear register. Writing '0' has no effect - 18 - 18 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel - 1 - - - - - CH19 - Channel 19 enable clear register. Writing '0' has no effect - 19 - 19 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel - 1 - - - - - CH20 - Channel 20 enable clear register. Writing '0' has no effect - 20 - 20 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel - 1 - - - - - CH21 - Channel 21 enable clear register. Writing '0' has no effect - 21 - 21 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel - 1 - - - - - CH22 - Channel 22 enable clear register. Writing '0' has no effect - 22 - 22 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel - 1 - - - - - CH23 - Channel 23 enable clear register. Writing '0' has no effect - 23 - 23 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel - 1 - - - - - CH24 - Channel 24 enable clear register. Writing '0' has no effect - 24 - 24 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel - 1 - - - - - CH25 - Channel 25 enable clear register. Writing '0' has no effect - 25 - 25 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel - 1 - - - - - CH26 - Channel 26 enable clear register. Writing '0' has no effect - 26 - 26 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel - 1 - - - - - CH27 - Channel 27 enable clear register. Writing '0' has no effect - 27 - 27 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel - 1 - - - - - CH28 - Channel 28 enable clear register. Writing '0' has no effect - 28 - 28 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel - 1 - - - - - CH29 - Channel 29 enable clear register. Writing '0' has no effect - 29 - 29 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel - 1 - - - - - CH30 - Channel 30 enable clear register. Writing '0' has no effect - 30 - 30 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel - 1 - - - - - CH31 - Channel 31 enable clear register. Writing '0' has no effect - 31 - 31 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel - 1 - - - - - - - 20 - 0x008 - CH[%s] - PPI Channel - PPI_CH - read-write - 0x510 - - EEP - Description cluster: Channel n event end-point - 0x000 - read-write - - - EEP - Pointer to event register. Accepts only addresses to registers from the Event group. - 0 - 31 - - - - - TEP - Description cluster: Channel n task end-point - 0x004 - read-write - - - TEP - Pointer to task register. Accepts only addresses to registers from the Task group. - 0 - 31 - - - - - - 0x6 - 0x4 - CHG[%s] - Description collection: Channel group n - 0x800 - read-write - - - CH0 - Include or exclude channel 0 - 0 - 0 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH1 - Include or exclude channel 1 - 1 - 1 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH2 - Include or exclude channel 2 - 2 - 2 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH3 - Include or exclude channel 3 - 3 - 3 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH4 - Include or exclude channel 4 - 4 - 4 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH5 - Include or exclude channel 5 - 5 - 5 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH6 - Include or exclude channel 6 - 6 - 6 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH7 - Include or exclude channel 7 - 7 - 7 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH8 - Include or exclude channel 8 - 8 - 8 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH9 - Include or exclude channel 9 - 9 - 9 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH10 - Include or exclude channel 10 - 10 - 10 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH11 - Include or exclude channel 11 - 11 - 11 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH12 - Include or exclude channel 12 - 12 - 12 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH13 - Include or exclude channel 13 - 13 - 13 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH14 - Include or exclude channel 14 - 14 - 14 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH15 - Include or exclude channel 15 - 15 - 15 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH16 - Include or exclude channel 16 - 16 - 16 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH17 - Include or exclude channel 17 - 17 - 17 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH18 - Include or exclude channel 18 - 18 - 18 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH19 - Include or exclude channel 19 - 19 - 19 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH20 - Include or exclude channel 20 - 20 - 20 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH21 - Include or exclude channel 21 - 21 - 21 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH22 - Include or exclude channel 22 - 22 - 22 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH23 - Include or exclude channel 23 - 23 - 23 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH24 - Include or exclude channel 24 - 24 - 24 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH25 - Include or exclude channel 25 - 25 - 25 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH26 - Include or exclude channel 26 - 26 - 26 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH27 - Include or exclude channel 27 - 27 - 27 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH28 - Include or exclude channel 28 - 28 - 28 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH29 - Include or exclude channel 29 - 29 - 29 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH30 - Include or exclude channel 30 - 30 - 30 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH31 - Include or exclude channel 31 - 31 - 31 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - - - 32 - 0x004 - FORK[%s] - Fork - PPI_FORK - read-write - 0x910 - - TEP - Description cluster: Channel n task end-point - 0x000 - read-write - - - TEP - Pointer to task register - 0 - 31 - - - - - - - - + + + + Nordic Semiconductor + Nordic + nrf52811 + nrf52 + 1 + nRF52811 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller + +Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved.\n +\n +SPDX-License-Identifier: BSD-3-Clause\n +\n +Redistribution and use in source and binary forms, with or without\n +modification, are permitted provided that the following conditions are met:\n +\n +1. Redistributions of source code must retain the above copyright notice, this\n + list of conditions and the following disclaimer.\n +\n +2. Redistributions in binary form must reproduce the above copyright\n + notice, this list of conditions and the following disclaimer in the\n + documentation and/or other materials provided with the distribution.\n +\n +3. Neither the name of Nordic Semiconductor ASA nor the names of its\n + contributors may be used to endorse or promote products derived from this\n + software without specific prior written permission.\n +\n +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\n +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE\n +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\n +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n +POSSIBILITY OF SUCH DAMAGE.\n + + 8 + 32 + 32 + 0x00000000 + 0xFFFFFFFF + + CM4 + r0p1 + little + 1 + 0 + 3 + 0 + + system_nrf52 + NRF_ + + 2048 + 2048 + 112 + + + + FICR + Factory information configuration registers + 0x10000000 + + 0 + 0x1000 + registers + + FICR + 0x20 + + + CODEPAGESIZE + Code memory page size + 0x010 + read-only + 0x00001000 + + + CODEPAGESIZE + Code memory page size + 0 + 31 + + + + + CODESIZE + Code memory size + 0x014 + read-only + 0x00000030 + + + CODESIZE + Code memory size in number of pages + 0 + 31 + + + + + 0x2 + 0x4 + DEVICEID[%s] + Description collection: Device identifier + 0x060 + read-only + 0xFFFFFFFF + + + DEVICEID + 64 bit unique device identifier + 0 + 31 + + + + + 0x4 + 0x4 + ER[%s] + Description collection: Encryption root, word n + 0x080 + read-only + 0xFFFFFFFF + + + ER + Encryption root, word n + 0 + 31 + + + + + 0x4 + 0x4 + IR[%s] + Description collection: Identity root, word n + 0x090 + read-only + 0xFFFFFFFF + + + IR + Identity root, word n + 0 + 31 + + + + + DEVICEADDRTYPE + Device address type + 0x0A0 + read-only + 0xFFFFFFFF + + + DEVICEADDRTYPE + Device address type + 0 + 0 + + + Public + Public address + 0 + + + Random + Random address + 1 + + + + + + + 0x2 + 0x4 + DEVICEADDR[%s] + Description collection: Device address n + 0x0A4 + read-only + 0xFFFFFFFF + + + DEVICEADDR + 48 bit device address + 0 + 31 + + + + + INFO + Device info + FICR_INFO + read-only + 0x100 + + PART + Part code + 0x000 + read-only + 0x00052811 + + + PART + Part code + 0 + 31 + + + N52810 + nRF52810 + 0x52810 + + + N52811 + nRF52811 + 0x52811 + + + N52832 + nRF52832 + 0x52832 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + VARIANT + Part variant, hardware version and production configuration + 0x004 + read-only + 0xFFFFFFFF + + + VARIANT + Part variant, hardware version and production configuration, encoded as ASCII + 0 + 31 + + + AAAA + AAAA + 0x41414141 + + + AAA0 + AAA0 + 0x41414130 + + + AABA + AABA + 0x41414241 + + + AABB + AABB + 0x41414242 + + + AAB0 + AAB0 + 0x41414230 + + + AACA + AACA + 0x41414341 + + + AACB + AACB + 0x41414342 + + + AAC0 + AAC0 + 0x41414330 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + PACKAGE + Package option + 0x008 + read-only + 0xFFFFFFFF + + + PACKAGE + Package option + 0 + 31 + + + QF + QFxx - 48-pin QFN + 0x2000 + + + QC + QCxx - 32-pin QFN + 0x2003 + + + CA + CAxx - WLCSP + 0x2004 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + RAM + RAM variant + 0x00C + read-only + 0x00000018 + + + RAM + RAM variant + 0 + 31 + + + K24 + 24 kByte RAM + 0x18 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + FLASH + Flash variant + 0x010 + read-only + 0x000000C0 + + + FLASH + Flash variant + 0 + 31 + + + K192 + 192 kByte flash + 0xC0 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + + TEMP + Registers storing factory TEMP module linearization coefficients + FICR_TEMP + read-only + 0x404 + + A0 + Slope definition A0 + 0x000 + read-only + 0xFFFFFFFF + + + A + A (slope definition) register + 0 + 11 + + + + + A1 + Slope definition A1 + 0x004 + read-only + 0xFFFFFFFF + + + A + A (slope definition) register + 0 + 11 + + + + + A2 + Slope definition A2 + 0x008 + read-only + 0xFFFFFFFF + + + A + A (slope definition) register + 0 + 11 + + + + + A3 + Slope definition A3 + 0x00C + read-only + 0xFFFFFFFF + + + A + A (slope definition) register + 0 + 11 + + + + + A4 + Slope definition A4 + 0x010 + read-only + 0xFFFFFFFF + + + A + A (slope definition) register + 0 + 11 + + + + + A5 + Slope definition A5 + 0x014 + read-only + 0xFFFFFFFF + + + A + A (slope definition) register + 0 + 11 + + + + + B0 + Y-intercept B0 + 0x018 + read-only + 0xFFFFFFFF + + + B + B (y-intercept) + 0 + 13 + + + + + B1 + Y-intercept B1 + 0x01C + read-only + 0xFFFFFFFF + + + B + B (y-intercept) + 0 + 13 + + + + + B2 + Y-intercept B2 + 0x020 + read-only + 0xFFFFFFFF + + + B + B (y-intercept) + 0 + 13 + + + + + B3 + Y-intercept B3 + 0x024 + read-only + 0xFFFFFFFF + + + B + B (y-intercept) + 0 + 13 + + + + + B4 + Y-intercept B4 + 0x028 + read-only + 0xFFFFFFFF + + + B + B (y-intercept) + 0 + 13 + + + + + B5 + Y-intercept B5 + 0x02C + read-only + 0xFFFFFFFF + + + B + B (y-intercept) + 0 + 13 + + + + + T0 + Segment end T0 + 0x030 + read-only + 0xFFFFFFFF + + + T + T (segment end) register + 0 + 7 + + + + + T1 + Segment end T1 + 0x034 + read-only + 0xFFFFFFFF + + + T + T (segment end) register + 0 + 7 + + + + + T2 + Segment end T2 + 0x038 + read-only + 0xFFFFFFFF + + + T + T (segment end) register + 0 + 7 + + + + + T3 + Segment end T3 + 0x03C + read-only + 0xFFFFFFFF + + + T + T (segment end) register + 0 + 7 + + + + + T4 + Segment end T4 + 0x040 + read-only + 0xFFFFFFFF + + + T + T (segment end) register + 0 + 7 + + + + + + + + UICR + User information configuration registers + 0x10001000 + + 0 + 0x1000 + registers + + UICR + 0x20 + + + 0xD + 0x4 + NRFFW[%s] + Description collection: Reserved for Nordic firmware design + 0x014 + read-write + 0xFFFFFFFF + + + NRFFW + Reserved for Nordic firmware design + 0 + 31 + + + + + 0xC + 0x4 + NRFHW[%s] + Description collection: Reserved for Nordic hardware design + 0x050 + read-write + 0xFFFFFFFF + + + NRFHW + Reserved for Nordic hardware design + 0 + 31 + + + + + 0x20 + 0x4 + CUSTOMER[%s] + Description collection: Reserved for customer + 0x080 + read-write + 0xFFFFFFFF + + + CUSTOMER + Reserved for customer + 0 + 31 + + + + + 0x8 + 0x4 + NRFMDK[%s] + Description collection: Reserved for Nordic MDK + 0x100 + read-write + 0xFFFFFFFF + + + NRFMDK + Reserved for Nordic MDK + 0 + 31 + + + + + 0x2 + 0x4 + PSELRESET[%s] + Description collection: Mapping of the nRESET function (see POWER chapter for details) + 0x200 + read-write + 0xFFFFFFFF + + + PIN + GPIO pin number onto which nRESET is exposed + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + APPROTECT + Access port protection + 0x208 + read-write + 0xFFFFFFFF + + + PALL + Enable or disable access port protection. + 0 + 7 + + + Disabled + Hardware disable of access port protection for devices where access port protection is controlled by hardware + 0xFF + + + HwDisabled + Hardware disable of access port protection for devices where access port protection is controlled by hardware and software + 0x5A + + + Enabled + Enable + 0x00 + + + + + + + + + APPROTECT + Access Port Protection + 0x40000000 + + 0 + 0x1000 + registers + + APPROTECT + 0x20 + + + FORCEPROTECT + Software force enable APPROTECT mechanism until next reset. + 0x550 + read-writeOnce + 0xFFFFFFFF + + + FORCEPROTECT + Write 0x0 to force enable APPROTECT mechanism + 0 + 7 + + write + + Force + Software force enable APPROTECT mechanism + 0x0 + + + + + + + DISABLE + Software disable APPROTECT mechanism + 0x558 + read-write + 0x00000000 + + + DISABLE + Software disable APPROTECT mechanism + 0 + 7 + + + SwDisable + Software disable APPROTECT mechanism + 0x5A + + + + + + + + + BPROT + Block Protect + 0x40000000 + APPROTECT + + 0 + 0x1000 + registers + + BPROT + 0x20 + + + CONFIG0 + Block protect configuration register 0 + 0x600 + read-write + + + REGION0 + Enable protection for region 0. Write '0' has no effect. + 0 + 0 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION1 + Enable protection for region 1. Write '0' has no effect. + 1 + 1 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION2 + Enable protection for region 2. Write '0' has no effect. + 2 + 2 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION3 + Enable protection for region 3. Write '0' has no effect. + 3 + 3 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION4 + Enable protection for region 4. Write '0' has no effect. + 4 + 4 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION5 + Enable protection for region 5. Write '0' has no effect. + 5 + 5 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION6 + Enable protection for region 6. Write '0' has no effect. + 6 + 6 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION7 + Enable protection for region 7. Write '0' has no effect. + 7 + 7 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION8 + Enable protection for region 8. Write '0' has no effect. + 8 + 8 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION9 + Enable protection for region 9. Write '0' has no effect. + 9 + 9 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION10 + Enable protection for region 10. Write '0' has no effect. + 10 + 10 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION11 + Enable protection for region 11. Write '0' has no effect. + 11 + 11 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION12 + Enable protection for region 12. Write '0' has no effect. + 12 + 12 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION13 + Enable protection for region 13. Write '0' has no effect. + 13 + 13 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION14 + Enable protection for region 14. Write '0' has no effect. + 14 + 14 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION15 + Enable protection for region 15. Write '0' has no effect. + 15 + 15 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION16 + Enable protection for region 16. Write '0' has no effect. + 16 + 16 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION17 + Enable protection for region 17. Write '0' has no effect. + 17 + 17 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION18 + Enable protection for region 18. Write '0' has no effect. + 18 + 18 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION19 + Enable protection for region 19. Write '0' has no effect. + 19 + 19 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION20 + Enable protection for region 20. Write '0' has no effect. + 20 + 20 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION21 + Enable protection for region 21. Write '0' has no effect. + 21 + 21 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION22 + Enable protection for region 22. Write '0' has no effect. + 22 + 22 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION23 + Enable protection for region 23. Write '0' has no effect. + 23 + 23 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION24 + Enable protection for region 24. Write '0' has no effect. + 24 + 24 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION25 + Enable protection for region 25. Write '0' has no effect. + 25 + 25 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION26 + Enable protection for region 26. Write '0' has no effect. + 26 + 26 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION27 + Enable protection for region 27. Write '0' has no effect. + 27 + 27 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION28 + Enable protection for region 28. Write '0' has no effect. + 28 + 28 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION29 + Enable protection for region 29. Write '0' has no effect. + 29 + 29 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION30 + Enable protection for region 30. Write '0' has no effect. + 30 + 30 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION31 + Enable protection for region 31. Write '0' has no effect. + 31 + 31 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + + + CONFIG1 + Block protect configuration register 1 + 0x604 + read-write + + + REGION32 + Enable protection for region 32. Write '0' has no effect. + 0 + 0 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION33 + Enable protection for region 33. Write '0' has no effect. + 1 + 1 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION34 + Enable protection for region 34. Write '0' has no effect. + 2 + 2 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION35 + Enable protection for region 35. Write '0' has no effect. + 3 + 3 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION36 + Enable protection for region 36. Write '0' has no effect. + 4 + 4 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION37 + Enable protection for region 37. Write '0' has no effect. + 5 + 5 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION38 + Enable protection for region 38. Write '0' has no effect. + 6 + 6 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION39 + Enable protection for region 39. Write '0' has no effect. + 7 + 7 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION40 + Enable protection for region 40. Write '0' has no effect. + 8 + 8 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION41 + Enable protection for region 41. Write '0' has no effect. + 9 + 9 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION42 + Enable protection for region 42. Write '0' has no effect. + 10 + 10 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION43 + Enable protection for region 43. Write '0' has no effect. + 11 + 11 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION44 + Enable protection for region 44. Write '0' has no effect. + 12 + 12 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION45 + Enable protection for region 45. Write '0' has no effect. + 13 + 13 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION46 + Enable protection for region 46. Write '0' has no effect. + 14 + 14 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION47 + Enable protection for region 47. Write '0' has no effect. + 15 + 15 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + + + DISABLEINDEBUG + Disable protection mechanism in debug mode + 0x608 + read-write + 0x00000001 + + + DISABLEINDEBUG + Disable the protection mechanism for NVM regions while in debug mode. This register will only disable the protection mechanism if the device is in debug mode. + 0 + 0 + + + Disabled + Disabled in debug + 1 + + + Enabled + Enabled in debug + 0 + + + + + + + + + CLOCK + Clock control + 0x40000000 + APPROTECT + + 0 + 0x1000 + registers + + + POWER_CLOCK + 0 + + CLOCK + 0x20 + + + TASKS_HFCLKSTART + Start HFCLK crystal oscillator + 0x000 + write-only + + + TASKS_HFCLKSTART + Start HFCLK crystal oscillator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_HFCLKSTOP + Stop HFCLK crystal oscillator + 0x004 + write-only + + + TASKS_HFCLKSTOP + Stop HFCLK crystal oscillator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_LFCLKSTART + Start LFCLK source + 0x008 + write-only + + + TASKS_LFCLKSTART + Start LFCLK source + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_LFCLKSTOP + Stop LFCLK source + 0x00C + write-only + + + TASKS_LFCLKSTOP + Stop LFCLK source + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CAL + Start calibration of LFRC oscillator + 0x010 + write-only + + + TASKS_CAL + Start calibration of LFRC oscillator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CTSTART + Start calibration timer + 0x014 + write-only + + + TASKS_CTSTART + Start calibration timer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CTSTOP + Stop calibration timer + 0x018 + write-only + + + TASKS_CTSTOP + Stop calibration timer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_HFCLKSTARTED + HFCLK oscillator started + 0x100 + read-write + + + EVENTS_HFCLKSTARTED + HFCLK oscillator started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_LFCLKSTARTED + LFCLK started + 0x104 + read-write + + + EVENTS_LFCLKSTARTED + LFCLK started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DONE + Calibration of LFCLK RC oscillator complete event + 0x10C + read-write + + + EVENTS_DONE + Calibration of LFCLK RC oscillator complete event + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CTTO + Calibration timer timeout + 0x110 + read-write + + + EVENTS_CTTO + Calibration timer timeout + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + HFCLKSTARTED + Write '1' to enable interrupt for event HFCLKSTARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + LFCLKSTARTED + Write '1' to enable interrupt for event LFCLKSTARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DONE + Write '1' to enable interrupt for event DONE + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CTTO + Write '1' to enable interrupt for event CTTO + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + HFCLKSTARTED + Write '1' to disable interrupt for event HFCLKSTARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + LFCLKSTARTED + Write '1' to disable interrupt for event LFCLKSTARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DONE + Write '1' to disable interrupt for event DONE + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CTTO + Write '1' to disable interrupt for event CTTO + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + HFCLKRUN + Status indicating that HFCLKSTART task has been triggered + 0x408 + read-only + + + STATUS + HFCLKSTART task triggered or not + 0 + 0 + + + NotTriggered + Task not triggered + 0 + + + Triggered + Task triggered + 1 + + + + + + + HFCLKSTAT + HFCLK status + 0x40C + read-only + + + SRC + Source of HFCLK + 0 + 0 + + + RC + 64 MHz internal oscillator (HFINT) + 0 + + + Xtal + 64 MHz crystal oscillator (HFXO) + 1 + + + + + STATE + HFCLK state + 16 + 16 + + + NotRunning + HFCLK not running + 0 + + + Running + HFCLK running + 1 + + + + + + + LFCLKRUN + Status indicating that LFCLKSTART task has been triggered + 0x414 + read-only + + + STATUS + LFCLKSTART task triggered or not + 0 + 0 + + + NotTriggered + Task not triggered + 0 + + + Triggered + Task triggered + 1 + + + + + + + LFCLKSTAT + LFCLK status + 0x418 + read-only + + + SRC + Source of LFCLK + 0 + 1 + + + RC + 32.768 kHz RC oscillator + 0 + + + Xtal + 32.768 kHz crystal oscillator + 1 + + + Synth + 32.768 kHz synthesized from HFCLK + 2 + + + + + STATE + LFCLK state + 16 + 16 + + + NotRunning + LFCLK not running + 0 + + + Running + LFCLK running + 1 + + + + + + + LFCLKSRCCOPY + Copy of LFCLKSRC register, set when LFCLKSTART task was triggered + 0x41C + read-only + + + SRC + Clock source + 0 + 1 + + + RC + 32.768 kHz RC oscillator + 0 + + + Xtal + 32.768 kHz crystal oscillator + 1 + + + Synth + 32.768 kHz synthesized from HFCLK + 2 + + + + + + + LFCLKSRC + Clock source for the LFCLK + 0x518 + read-write + + + SRC + Clock source + 0 + 1 + + + RC + 32.768 kHz RC oscillator + 0 + + + Xtal + 32.768 kHz crystal oscillator + 1 + + + Synth + 32.768 kHz synthesized from HFCLK + 2 + + + + + BYPASS + Enable or disable bypass of LFCLK crystal oscillator with external clock source + 16 + 16 + + + Disabled + Disable (use with Xtal or low-swing external source) + 0 + + + Enabled + Enable (use with rail-to-rail external source) + 1 + + + + + EXTERNAL + Enable or disable external source for LFCLK + 17 + 17 + + + Disabled + Disable external source (use with Xtal) + 0 + + + Enabled + Enable use of external source instead of Xtal (SRC needs to be set to Xtal) + 1 + + + + + + + CTIV + Calibration timer interval + 0x538 + read-write + + + CTIV + Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. + 0 + 6 + + + + + + + POWER + Power control + 0x40000000 + APPROTECT + + 0 + 0x1000 + registers + + + POWER_CLOCK + 0 + + POWER + 0x20 + + + TASKS_CONSTLAT + Enable Constant Latency mode + 0x078 + write-only + + + TASKS_CONSTLAT + Enable Constant Latency mode + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_LOWPWR + Enable Low-power mode (variable latency) + 0x07C + write-only + + + TASKS_LOWPWR + Enable Low-power mode (variable latency) + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_POFWARN + Power failure warning + 0x108 + read-write + + + EVENTS_POFWARN + Power failure warning + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SLEEPENTER + CPU entered WFI/WFE sleep + 0x114 + read-write + + + EVENTS_SLEEPENTER + CPU entered WFI/WFE sleep + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SLEEPEXIT + CPU exited WFI/WFE sleep + 0x118 + read-write + + + EVENTS_SLEEPEXIT + CPU exited WFI/WFE sleep + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + POFWARN + Write '1' to enable interrupt for event POFWARN + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SLEEPENTER + Write '1' to enable interrupt for event SLEEPENTER + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SLEEPEXIT + Write '1' to enable interrupt for event SLEEPEXIT + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + POFWARN + Write '1' to disable interrupt for event POFWARN + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SLEEPENTER + Write '1' to disable interrupt for event SLEEPENTER + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SLEEPEXIT + Write '1' to disable interrupt for event SLEEPEXIT + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + RESETREAS + Reset reason + 0x400 + read-write + + + RESETPIN + Reset from pin-reset detected + 0 + 0 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + DOG + Reset from watchdog detected + 1 + 1 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + SREQ + Reset from soft reset detected + 2 + 2 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + LOCKUP + Reset from CPU lock-up detected + 3 + 3 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + OFF + Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO + 16 + 16 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + DIF + Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode + 18 + 18 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + + + SYSTEMOFF + System OFF register + 0x500 + write-only + + + SYSTEMOFF + Enable System OFF mode + 0 + 0 + + + Enter + Enable System OFF mode + 1 + + + + + + + POFCON + Power failure comparator configuration + 0x510 + read-write + + + POF + Enable or disable power failure comparator + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + THRESHOLD + Power failure comparator threshold setting + 1 + 4 + + + V17 + Set threshold to 1.7 V + 4 + + + V18 + Set threshold to 1.8 V + 5 + + + V19 + Set threshold to 1.9 V + 6 + + + V20 + Set threshold to 2.0 V + 7 + + + V21 + Set threshold to 2.1 V + 8 + + + V22 + Set threshold to 2.2 V + 9 + + + V23 + Set threshold to 2.3 V + 10 + + + V24 + Set threshold to 2.4 V + 11 + + + V25 + Set threshold to 2.5 V + 12 + + + V26 + Set threshold to 2.6 V + 13 + + + V27 + Set threshold to 2.7 V + 14 + + + V28 + Set threshold to 2.8 V + 15 + + + + + + + GPREGRET + General purpose retention register + 0x51C + read-write + + + GPREGRET + General purpose retention register + 0 + 7 + + + + + GPREGRET2 + General purpose retention register + 0x520 + read-write + + + GPREGRET + General purpose retention register + 0 + 7 + + + + + DCDCEN + DC/DC enable register + 0x578 + read-write + + + DCDCEN + Enable or disable DC/DC converter + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + 8 + 0x010 + RAM[%s] + Unspecified + POWER_RAM + read-write + 0x900 + + POWER + Description cluster: RAMn power control register. The RAM size will vary depending on product variant, and the RAMn register will only be present if the corresponding RAM AHB slave is present on the device. + 0x000 + read-write + 0x0000FFFF + + + S0POWER + Keep RAM section S0 ON or OFF in System ON mode. + 0 + 0 + + + Off + Off + 0 + + + On + On + 1 + + + + + S1POWER + Keep RAM section S1 ON or OFF in System ON mode. + 1 + 1 + + + Off + Off + 0 + + + On + On + 1 + + + + + S0RETENTION + Keep retention on RAM section S0 when RAM section is in OFF + 16 + 16 + + + Off + Off + 0 + + + On + On + 1 + + + + + S1RETENTION + Keep retention on RAM section S1 when RAM section is in OFF + 17 + 17 + + + Off + Off + 0 + + + On + On + 1 + + + + + + + POWERSET + Description cluster: RAMn power control set register + 0x004 + write-only + 0x0000FFFF + + + S0POWER + Keep RAM section S0 of RAMn on or off in System ON mode + 0 + 0 + + + On + On + 1 + + + + + S1POWER + Keep RAM section S1 of RAMn on or off in System ON mode + 1 + 1 + + + On + On + 1 + + + + + S0RETENTION + Keep retention on RAM section S0 when RAM section is switched off + 16 + 16 + + + On + On + 1 + + + + + S1RETENTION + Keep retention on RAM section S1 when RAM section is switched off + 17 + 17 + + + On + On + 1 + + + + + + + POWERCLR + Description cluster: RAMn power control clear register + 0x008 + write-only + 0x0000FFFF + + + S0POWER + Keep RAM section S0 of RAMn on or off in System ON mode + 0 + 0 + + + Off + Off + 1 + + + + + S1POWER + Keep RAM section S1 of RAMn on or off in System ON mode + 1 + 1 + + + Off + Off + 1 + + + + + S0RETENTION + Keep retention on RAM section S0 when RAM section is switched off + 16 + 16 + + + Off + Off + 1 + + + + + S1RETENTION + Keep retention on RAM section S1 when RAM section is switched off + 17 + 17 + + + Off + Off + 1 + + + + + + + + + + P0 + GPIO Port + 0x50000000 + GPIO + + 0 + 0x1000 + registers + + GPIO + 0x20 + + + OUT + Write GPIO port + 0x504 + read-write + + + PIN0 + Pin 0 + 0 + 0 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + + + OUTSET + Set individual bits in GPIO port + 0x508 + read-write + oneToSet + + + PIN0 + Pin 0 + 0 + 0 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + + + OUTCLR + Clear individual bits in GPIO port + 0x50C + read-write + oneToClear + + + PIN0 + Pin 0 + 0 + 0 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + + + IN + Read GPIO port + 0x510 + read-only + + + PIN0 + Pin 0 + 0 + 0 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + + + DIR + Direction of GPIO pins + 0x514 + read-write + + + PIN0 + Pin 0 + 0 + 0 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + + + DIRSET + DIR set register + 0x518 + read-write + oneToSet + + + PIN0 + Set as output pin 0 + 0 + 0 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN1 + Set as output pin 1 + 1 + 1 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN2 + Set as output pin 2 + 2 + 2 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN3 + Set as output pin 3 + 3 + 3 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN4 + Set as output pin 4 + 4 + 4 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN5 + Set as output pin 5 + 5 + 5 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN6 + Set as output pin 6 + 6 + 6 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN7 + Set as output pin 7 + 7 + 7 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN8 + Set as output pin 8 + 8 + 8 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN9 + Set as output pin 9 + 9 + 9 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN10 + Set as output pin 10 + 10 + 10 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN11 + Set as output pin 11 + 11 + 11 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN12 + Set as output pin 12 + 12 + 12 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN13 + Set as output pin 13 + 13 + 13 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN14 + Set as output pin 14 + 14 + 14 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN15 + Set as output pin 15 + 15 + 15 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN16 + Set as output pin 16 + 16 + 16 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN17 + Set as output pin 17 + 17 + 17 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN18 + Set as output pin 18 + 18 + 18 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN19 + Set as output pin 19 + 19 + 19 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN20 + Set as output pin 20 + 20 + 20 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN21 + Set as output pin 21 + 21 + 21 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN22 + Set as output pin 22 + 22 + 22 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN23 + Set as output pin 23 + 23 + 23 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN24 + Set as output pin 24 + 24 + 24 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN25 + Set as output pin 25 + 25 + 25 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN26 + Set as output pin 26 + 26 + 26 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN27 + Set as output pin 27 + 27 + 27 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN28 + Set as output pin 28 + 28 + 28 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN29 + Set as output pin 29 + 29 + 29 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN30 + Set as output pin 30 + 30 + 30 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN31 + Set as output pin 31 + 31 + 31 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + + + DIRCLR + DIR clear register + 0x51C + read-write + oneToClear + + + PIN0 + Set as input pin 0 + 0 + 0 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN1 + Set as input pin 1 + 1 + 1 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN2 + Set as input pin 2 + 2 + 2 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN3 + Set as input pin 3 + 3 + 3 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN4 + Set as input pin 4 + 4 + 4 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN5 + Set as input pin 5 + 5 + 5 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN6 + Set as input pin 6 + 6 + 6 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN7 + Set as input pin 7 + 7 + 7 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN8 + Set as input pin 8 + 8 + 8 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN9 + Set as input pin 9 + 9 + 9 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN10 + Set as input pin 10 + 10 + 10 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN11 + Set as input pin 11 + 11 + 11 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN12 + Set as input pin 12 + 12 + 12 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN13 + Set as input pin 13 + 13 + 13 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN14 + Set as input pin 14 + 14 + 14 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN15 + Set as input pin 15 + 15 + 15 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN16 + Set as input pin 16 + 16 + 16 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN17 + Set as input pin 17 + 17 + 17 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN18 + Set as input pin 18 + 18 + 18 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN19 + Set as input pin 19 + 19 + 19 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN20 + Set as input pin 20 + 20 + 20 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN21 + Set as input pin 21 + 21 + 21 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN22 + Set as input pin 22 + 22 + 22 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN23 + Set as input pin 23 + 23 + 23 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN24 + Set as input pin 24 + 24 + 24 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN25 + Set as input pin 25 + 25 + 25 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN26 + Set as input pin 26 + 26 + 26 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN27 + Set as input pin 27 + 27 + 27 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN28 + Set as input pin 28 + 28 + 28 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN29 + Set as input pin 29 + 29 + 29 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN30 + Set as input pin 30 + 30 + 30 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN31 + Set as input pin 31 + 31 + 31 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + + + LATCH + Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers + 0x520 + read-write + + + PIN0 + Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. + 0 + 0 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN1 + Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. + 1 + 1 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN2 + Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. + 2 + 2 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN3 + Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. + 3 + 3 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN4 + Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. + 4 + 4 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN5 + Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. + 5 + 5 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN6 + Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. + 6 + 6 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN7 + Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. + 7 + 7 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN8 + Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. + 8 + 8 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN9 + Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. + 9 + 9 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN10 + Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. + 10 + 10 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN11 + Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. + 11 + 11 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN12 + Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. + 12 + 12 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN13 + Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. + 13 + 13 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN14 + Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. + 14 + 14 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN15 + Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. + 15 + 15 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN16 + Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. + 16 + 16 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN17 + Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. + 17 + 17 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN18 + Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. + 18 + 18 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN19 + Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. + 19 + 19 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN20 + Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. + 20 + 20 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN21 + Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. + 21 + 21 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN22 + Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. + 22 + 22 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN23 + Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. + 23 + 23 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN24 + Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. + 24 + 24 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN25 + Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. + 25 + 25 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN26 + Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. + 26 + 26 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN27 + Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. + 27 + 27 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN28 + Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. + 28 + 28 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN29 + Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. + 29 + 29 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN30 + Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. + 30 + 30 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN31 + Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. + 31 + 31 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + + + DETECTMODE + Select between default DETECT signal behaviour and LDETECT mode + 0x524 + read-write + + + DETECTMODE + Select between default DETECT signal behaviour and LDETECT mode + 0 + 0 + + + Default + DETECT directly connected to PIN DETECT signals + 0 + + + LDETECT + Use the latched LDETECT behaviour + 1 + + + + + + + 0x20 + 0x4 + PIN_CNF[%s] + Description collection: Configuration of GPIO pins + 0x700 + read-write + 0x00000002 + + + DIR + Pin direction. Same physical register as DIR register + 0 + 0 + + + Input + Configure pin as an input pin + 0 + + + Output + Configure pin as an output pin + 1 + + + + + INPUT + Connect or disconnect input buffer + 1 + 1 + + + Connect + Connect input buffer + 0 + + + Disconnect + Disconnect input buffer + 1 + + + + + PULL + Pull configuration + 2 + 3 + + + Disabled + No pull + 0 + + + Pulldown + Pull down on pin + 1 + + + Pullup + Pull up on pin + 3 + + + + + DRIVE + Drive configuration + 8 + 10 + + + S0S1 + Standard '0', standard '1' + 0 + + + H0S1 + High drive '0', standard '1' + 1 + + + S0H1 + Standard '0', high drive '1' + 2 + + + H0H1 + High drive '0', high 'drive '1'' + 3 + + + D0S1 + Disconnect '0' standard '1' (normally used for wired-or connections) + 4 + + + D0H1 + Disconnect '0', high drive '1' (normally used for wired-or connections) + 5 + + + S0D1 + Standard '0'. disconnect '1' (normally used for wired-and connections) + 6 + + + H0D1 + High drive '0', disconnect '1' (normally used for wired-and connections) + 7 + + + + + SENSE + Pin sensing mechanism + 16 + 17 + + + Disabled + Disabled + 0 + + + High + Sense for high level + 2 + + + Low + Sense for low level + 3 + + + + + + + + + RADIO + 2.4 GHz radio + 0x40001000 + + 0 + 0x1000 + registers + + + RADIO + 1 + + RADIO + 0x20 + + + TASKS_TXEN + Enable RADIO in TX mode + 0x000 + write-only + + + TASKS_TXEN + Enable RADIO in TX mode + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RXEN + Enable RADIO in RX mode + 0x004 + write-only + + + TASKS_RXEN + Enable RADIO in RX mode + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_START + Start RADIO + 0x008 + write-only + + + TASKS_START + Start RADIO + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop RADIO + 0x00C + write-only + + + TASKS_STOP + Stop RADIO + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_DISABLE + Disable RADIO + 0x010 + write-only + + + TASKS_DISABLE + Disable RADIO + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RSSISTART + Start the RSSI and take one single sample of the receive signal strength + 0x014 + write-only + + + TASKS_RSSISTART + Start the RSSI and take one single sample of the receive signal strength + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RSSISTOP + Stop the RSSI measurement + 0x018 + write-only + + + TASKS_RSSISTOP + Stop the RSSI measurement + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_BCSTART + Start the bit counter + 0x01C + write-only + + + TASKS_BCSTART + Start the bit counter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_BCSTOP + Stop the bit counter + 0x020 + write-only + + + TASKS_BCSTOP + Stop the bit counter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_EDSTART + Start the energy detect measurement used in IEEE 802.15.4 mode + 0x024 + write-only + + + TASKS_EDSTART + Start the energy detect measurement used in IEEE 802.15.4 mode + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_EDSTOP + Stop the energy detect measurement + 0x028 + write-only + + + TASKS_EDSTOP + Stop the energy detect measurement + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CCASTART + Start the clear channel assessment used in IEEE 802.15.4 mode + 0x02C + write-only + + + TASKS_CCASTART + Start the clear channel assessment used in IEEE 802.15.4 mode + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CCASTOP + Stop the clear channel assessment + 0x030 + write-only + + + TASKS_CCASTOP + Stop the clear channel assessment + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_READY + RADIO has ramped up and is ready to be started + 0x100 + read-write + + + EVENTS_READY + RADIO has ramped up and is ready to be started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ADDRESS + Address sent or received + 0x104 + read-write + + + EVENTS_ADDRESS + Address sent or received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_PAYLOAD + Packet payload sent or received + 0x108 + read-write + + + EVENTS_PAYLOAD + Packet payload sent or received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_END + Packet sent or received + 0x10C + read-write + + + EVENTS_END + Packet sent or received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DISABLED + RADIO has been disabled + 0x110 + read-write + + + EVENTS_DISABLED + RADIO has been disabled + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DEVMATCH + A device address match occurred on the last received packet + 0x114 + read-write + + + EVENTS_DEVMATCH + A device address match occurred on the last received packet + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DEVMISS + No device address match occurred on the last received packet + 0x118 + read-write + + + EVENTS_DEVMISS + No device address match occurred on the last received packet + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RSSIEND + Sampling of receive signal strength complete + 0x11C + read-write + + + EVENTS_RSSIEND + Sampling of receive signal strength complete + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_BCMATCH + Bit counter reached bit count value + 0x128 + read-write + + + EVENTS_BCMATCH + Bit counter reached bit count value + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CRCOK + Packet received with CRC ok + 0x130 + read-write + + + EVENTS_CRCOK + Packet received with CRC ok + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CRCERROR + Packet received with CRC error + 0x134 + read-write + + + EVENTS_CRCERROR + Packet received with CRC error + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_FRAMESTART + IEEE 802.15.4 length field received + 0x138 + read-write + + + EVENTS_FRAMESTART + IEEE 802.15.4 length field received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_EDEND + Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. + 0x13C + read-write + + + EVENTS_EDEND + Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_EDSTOPPED + The sampling of energy detection has stopped + 0x140 + read-write + + + EVENTS_EDSTOPPED + The sampling of energy detection has stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CCAIDLE + Wireless medium in idle - clear to send + 0x144 + read-write + + + EVENTS_CCAIDLE + Wireless medium in idle - clear to send + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CCABUSY + Wireless medium busy - do not send + 0x148 + read-write + + + EVENTS_CCABUSY + Wireless medium busy - do not send + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CCASTOPPED + The CCA has stopped + 0x14C + read-write + + + EVENTS_CCASTOPPED + The CCA has stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RATEBOOST + Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. + 0x150 + read-write + + + EVENTS_RATEBOOST + Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXREADY + RADIO has ramped up and is ready to be started TX path + 0x154 + read-write + + + EVENTS_TXREADY + RADIO has ramped up and is ready to be started TX path + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXREADY + RADIO has ramped up and is ready to be started RX path + 0x158 + read-write + + + EVENTS_RXREADY + RADIO has ramped up and is ready to be started RX path + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_MHRMATCH + MAC header match found + 0x15C + read-write + + + EVENTS_MHRMATCH + MAC header match found + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SYNC + Preamble indicator + 0x168 + read-write + + + EVENTS_SYNC + Preamble indicator + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_PHYEND + Generated when last bit is sent on air, or received from air + 0x16C + read-write + + + EVENTS_PHYEND + Generated when last bit is sent on air, or received from air + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CTEPRESENT + CTE is present (early warning right after receiving CTEInfo byte) + 0x170 + read-write + + + EVENTS_CTEPRESENT + CTE is present (early warning right after receiving CTEInfo byte) + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + READY_START + Shortcut between event READY and task START + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + END_DISABLE + Shortcut between event END and task DISABLE + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DISABLED_TXEN + Shortcut between event DISABLED and task TXEN + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DISABLED_RXEN + Shortcut between event DISABLED and task RXEN + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + ADDRESS_RSSISTART + Shortcut between event ADDRESS and task RSSISTART + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + END_START + Shortcut between event END and task START + 5 + 5 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + ADDRESS_BCSTART + Shortcut between event ADDRESS and task BCSTART + 6 + 6 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DISABLED_RSSISTOP + Shortcut between event DISABLED and task RSSISTOP + 8 + 8 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + RXREADY_CCASTART + Shortcut between event RXREADY and task CCASTART + 11 + 11 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + CCAIDLE_TXEN + Shortcut between event CCAIDLE and task TXEN + 12 + 12 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + CCABUSY_DISABLE + Shortcut between event CCABUSY and task DISABLE + 13 + 13 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + FRAMESTART_BCSTART + Shortcut between event FRAMESTART and task BCSTART + 14 + 14 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + READY_EDSTART + Shortcut between event READY and task EDSTART + 15 + 15 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + EDEND_DISABLE + Shortcut between event EDEND and task DISABLE + 16 + 16 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + CCAIDLE_STOP + Shortcut between event CCAIDLE and task STOP + 17 + 17 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + TXREADY_START + Shortcut between event TXREADY and task START + 18 + 18 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + RXREADY_START + Shortcut between event RXREADY and task START + 19 + 19 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + PHYEND_DISABLE + Shortcut between event PHYEND and task DISABLE + 20 + 20 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + PHYEND_START + Shortcut between event PHYEND and task START + 21 + 21 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + READY + Write '1' to enable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ADDRESS + Write '1' to enable interrupt for event ADDRESS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PAYLOAD + Write '1' to enable interrupt for event PAYLOAD + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + END + Write '1' to enable interrupt for event END + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DISABLED + Write '1' to enable interrupt for event DISABLED + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DEVMATCH + Write '1' to enable interrupt for event DEVMATCH + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DEVMISS + Write '1' to enable interrupt for event DEVMISS + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RSSIEND + Write '1' to enable interrupt for event RSSIEND + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + BCMATCH + Write '1' to enable interrupt for event BCMATCH + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CRCOK + Write '1' to enable interrupt for event CRCOK + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CRCERROR + Write '1' to enable interrupt for event CRCERROR + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + FRAMESTART + Write '1' to enable interrupt for event FRAMESTART + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + EDEND + Write '1' to enable interrupt for event EDEND + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + EDSTOPPED + Write '1' to enable interrupt for event EDSTOPPED + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CCAIDLE + Write '1' to enable interrupt for event CCAIDLE + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CCABUSY + Write '1' to enable interrupt for event CCABUSY + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CCASTOPPED + Write '1' to enable interrupt for event CCASTOPPED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RATEBOOST + Write '1' to enable interrupt for event RATEBOOST + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXREADY + Write '1' to enable interrupt for event TXREADY + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXREADY + Write '1' to enable interrupt for event RXREADY + 22 + 22 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + MHRMATCH + Write '1' to enable interrupt for event MHRMATCH + 23 + 23 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SYNC + Write '1' to enable interrupt for event SYNC + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PHYEND + Write '1' to enable interrupt for event PHYEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CTEPRESENT + Write '1' to enable interrupt for event CTEPRESENT + 28 + 28 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + READY + Write '1' to disable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ADDRESS + Write '1' to disable interrupt for event ADDRESS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PAYLOAD + Write '1' to disable interrupt for event PAYLOAD + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + END + Write '1' to disable interrupt for event END + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DISABLED + Write '1' to disable interrupt for event DISABLED + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DEVMATCH + Write '1' to disable interrupt for event DEVMATCH + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DEVMISS + Write '1' to disable interrupt for event DEVMISS + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RSSIEND + Write '1' to disable interrupt for event RSSIEND + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + BCMATCH + Write '1' to disable interrupt for event BCMATCH + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CRCOK + Write '1' to disable interrupt for event CRCOK + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CRCERROR + Write '1' to disable interrupt for event CRCERROR + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + FRAMESTART + Write '1' to disable interrupt for event FRAMESTART + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + EDEND + Write '1' to disable interrupt for event EDEND + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + EDSTOPPED + Write '1' to disable interrupt for event EDSTOPPED + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CCAIDLE + Write '1' to disable interrupt for event CCAIDLE + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CCABUSY + Write '1' to disable interrupt for event CCABUSY + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CCASTOPPED + Write '1' to disable interrupt for event CCASTOPPED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RATEBOOST + Write '1' to disable interrupt for event RATEBOOST + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXREADY + Write '1' to disable interrupt for event TXREADY + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXREADY + Write '1' to disable interrupt for event RXREADY + 22 + 22 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + MHRMATCH + Write '1' to disable interrupt for event MHRMATCH + 23 + 23 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SYNC + Write '1' to disable interrupt for event SYNC + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PHYEND + Write '1' to disable interrupt for event PHYEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CTEPRESENT + Write '1' to disable interrupt for event CTEPRESENT + 28 + 28 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + CRCSTATUS + CRC status + 0x400 + read-only + + + CRCSTATUS + CRC status of packet received + 0 + 0 + + + CRCError + Packet received with CRC error + 0 + + + CRCOk + Packet received with CRC ok + 1 + + + + + + + RXMATCH + Received address + 0x408 + read-only + + + RXMATCH + Received address + 0 + 2 + + + + + RXCRC + CRC field of previously received packet + 0x40C + read-only + + + RXCRC + CRC field of previously received packet + 0 + 23 + + + + + DAI + Device address match index + 0x410 + read-only + + + DAI + Device address match index + 0 + 2 + + + + + PDUSTAT + Payload status + 0x414 + read-only + + + PDUSTAT + Status on payload length vs. PCNF1.MAXLEN + 0 + 0 + + + LessThan + Payload less than PCNF1.MAXLEN + 0 + + + GreaterThan + Payload greater than PCNF1.MAXLEN + 1 + + + + + CISTAT + Status on what rate packet is received with in Long Range + 1 + 2 + + + LR125kbit + Frame is received at 125 kbps + 0 + + + LR500kbit + Frame is received at 500 kbps + 1 + + + + + + + CTESTATUS + CTEInfo parsed from received packet + 0x44C + read-only + + + CTETIME + CTETime parsed from packet + 0 + 4 + + + RFU + RFU parsed from packet + 5 + 5 + + + CTETYPE + CTEType parsed from packet + 6 + 7 + + + + + DFESTATUS + DFE status information + 0x458 + read-only + + + SWITCHINGSTATE + Internal state of switching state machine + 0 + 2 + + + Idle + Switching state Idle + 0 + + + Offset + Switching state Offset + 1 + + + Guard + Switching state Guard + 2 + + + Ref + Switching state Ref + 3 + + + Switching + Switching state Switching + 4 + + + Ending + Switching state Ending + 5 + + + + + SAMPLINGSTATE + Internal state of sampling state machine + 4 + 4 + + + Idle + Sampling state Idle + 0 + + + Sampling + Sampling state Sampling + 1 + + + + + + + PACKETPTR + Packet pointer + 0x504 + read-write + 0x00000000 + + + PACKETPTR + Packet pointer + 0 + 31 + + + + + FREQUENCY + Frequency + 0x508 + read-write + 0x00000002 + + + FREQUENCY + Radio channel frequency + 0 + 6 + + + MAP + Channel map selection + 8 + 8 + + + Default + Channel map between 2400 MHZ .. 2500 MHz + 0 + + + Low + Channel map between 2360 MHZ .. 2460 MHz + 1 + + + + + + + TXPOWER + Output power + 0x50C + read-write + + + TXPOWER + RADIO output power + 0 + 7 + + + Pos4dBm + +4 dBm + 0x4 + + + Pos3dBm + +3 dBm + 0x3 + + + 0dBm + 0 dBm + 0x0 + + + Neg4dBm + -4 dBm + 0xFC + + + Neg8dBm + -8 dBm + 0xF8 + + + Neg12dBm + -12 dBm + 0xF4 + + + Neg16dBm + -16 dBm + 0xF0 + + + Neg20dBm + -20 dBm + 0xEC + + + Neg30dBm + Deprecated enumerator - -40 dBm + 0xE2 + + + Neg40dBm + -40 dBm + 0xD8 + + + + + + + MODE + Data rate and modulation + 0x510 + read-write + + + MODE + Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation. + 0 + 3 + + + Nrf_1Mbit + 1 Mbps Nordic proprietary radio mode + 0 + + + Nrf_2Mbit + 2 Mbps Nordic proprietary radio mode + 1 + + + Ble_1Mbit + 1 Mbps BLE + 3 + + + Ble_2Mbit + 2 Mbps BLE + 4 + + + Ble_LR125Kbit + Long range 125 kbps TX, 125 kbps and 500 kbps RX + 5 + + + Ble_LR500Kbit + Long range 500 kbps TX, 125 kbps and 500 kbps RX + 6 + + + Ieee802154_250Kbit + IEEE 802.15.4-2006 250 kbps + 15 + + + + + + + PCNF0 + Packet configuration register 0 + 0x514 + read-write + + + LFLEN + Length on air of LENGTH field in number of bits + 0 + 3 + + + S0LEN + Length on air of S0 field in number of bytes + 8 + 8 + + + S1LEN + Length on air of S1 field in number of bits + 16 + 19 + + + S1INCL + Include or exclude S1 field in RAM + 20 + 20 + + + Automatic + Include S1 field in RAM only if S1LEN &gt; 0 + 0 + + + Include + Always include S1 field in RAM independent of S1LEN + 1 + + + + + CILEN + Length of code indicator - long range + 22 + 23 + + + PLEN + Length of preamble on air. Decision point: TASKS_START task + 24 + 25 + + + 8bit + 8-bit preamble + 0 + + + 16bit + 16-bit preamble + 1 + + + 32bitZero + 32-bit zero preamble - used for IEEE 802.15.4 + 2 + + + LongRange + Preamble - used for BLE long range + 3 + + + + + CRCINC + Indicates if LENGTH field contains CRC or not + 26 + 26 + + + Exclude + LENGTH does not contain CRC + 0 + + + Include + LENGTH includes CRC + 1 + + + + + TERMLEN + Length of TERM field in Long Range operation + 29 + 30 + + + + + PCNF1 + Packet configuration register 1 + 0x518 + read-write + + + MAXLEN + Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. + 0 + 7 + + + STATLEN + Static length in number of bytes + 8 + 15 + + + BALEN + Base address length in number of bytes + 16 + 18 + + + ENDIAN + On-air endianness of packet, this applies to the S0, LENGTH, S1, and the PAYLOAD fields. + 24 + 24 + + + Little + Least significant bit on air first + 0 + + + Big + Most significant bit on air first + 1 + + + + + WHITEEN + Enable or disable packet whitening + 25 + 25 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + BASE0 + Base address 0 + 0x51C + read-write + + + BASE0 + Base address 0 + 0 + 31 + + + + + BASE1 + Base address 1 + 0x520 + read-write + + + BASE1 + Base address 1 + 0 + 31 + + + + + PREFIX0 + Prefixes bytes for logical addresses 0-3 + 0x524 + read-write + + + AP0 + Address prefix 0. + 0 + 7 + + + AP1 + Address prefix 1. + 8 + 15 + + + AP2 + Address prefix 2. + 16 + 23 + + + AP3 + Address prefix 3. + 24 + 31 + + + + + PREFIX1 + Prefixes bytes for logical addresses 4-7 + 0x528 + read-write + + + AP4 + Address prefix 4. + 0 + 7 + + + AP5 + Address prefix 5. + 8 + 15 + + + AP6 + Address prefix 6. + 16 + 23 + + + AP7 + Address prefix 7. + 24 + 31 + + + + + TXADDRESS + Transmit address select + 0x52C + read-write + + + TXADDRESS + Transmit address select + 0 + 2 + + + + + RXADDRESSES + Receive address select + 0x530 + read-write + + + ADDR0 + Enable or disable reception on logical address 0. + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR1 + Enable or disable reception on logical address 1. + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR2 + Enable or disable reception on logical address 2. + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR3 + Enable or disable reception on logical address 3. + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR4 + Enable or disable reception on logical address 4. + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR5 + Enable or disable reception on logical address 5. + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR6 + Enable or disable reception on logical address 6. + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR7 + Enable or disable reception on logical address 7. + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + CRCCNF + CRC configuration + 0x534 + read-write + + + LEN + CRC length in number of bytes For MODE Ble_LR125Kbit and Ble_LR500Kbit, only LEN set to 3 is supported + 0 + 1 + + + Disabled + CRC length is zero and CRC calculation is disabled + 0 + + + One + CRC length is one byte and CRC calculation is enabled + 1 + + + Two + CRC length is two bytes and CRC calculation is enabled + 2 + + + Three + CRC length is three bytes and CRC calculation is enabled + 3 + + + + + SKIPADDR + Include or exclude packet address field out of CRC calculation. + 8 + 9 + + + Include + CRC calculation includes address field + 0 + + + Skip + CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. + 1 + + + Ieee802154 + CRC calculation as per 802.15.4 standard. Starting at first byte after length field. + 2 + + + + + + + CRCPOLY + CRC polynomial + 0x538 + read-write + 0x00000000 + + + CRCPOLY + CRC polynomial + 0 + 23 + + + + + CRCINIT + CRC initial value + 0x53C + read-write + + + CRCINIT + CRC initial value + 0 + 23 + + + + + TIFS + Interframe spacing in us + 0x544 + read-write + + + TIFS + Interframe spacing in us. + 0 + 9 + + + + + RSSISAMPLE + RSSI sample + 0x548 + read-only + + + RSSISAMPLE + RSSI sample. + 0 + 6 + + + + + STATE + Current radio state + 0x550 + read-only + + + STATE + Current radio state + 0 + 3 + + + Disabled + RADIO is in the Disabled state + 0 + + + RxRu + RADIO is in the RXRU state + 1 + + + RxIdle + RADIO is in the RXIDLE state + 2 + + + Rx + RADIO is in the RX state + 3 + + + RxDisable + RADIO is in the RXDISABLED state + 4 + + + TxRu + RADIO is in the TXRU state + 9 + + + TxIdle + RADIO is in the TXIDLE state + 10 + + + Tx + RADIO is in the TX state + 11 + + + TxDisable + RADIO is in the TXDISABLED state + 12 + + + + + + + DATAWHITEIV + Data whitening initial value + 0x554 + read-write + 0x00000040 + + + DATAWHITEIV + Data whitening initial value. Bit 6 is hardwired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. + 0 + 6 + + + + + BCC + Bit counter compare + 0x560 + read-write + + + BCC + Bit counter compare + 0 + 31 + + + + + 0x8 + 0x4 + DAB[%s] + Description collection: Device address base segment n + 0x600 + read-write + + + DAB + Device address base segment n + 0 + 31 + + + + + 0x8 + 0x4 + DAP[%s] + Description collection: Device address prefix n + 0x620 + read-write + + + DAP + Device address prefix n + 0 + 15 + + + + + DACNF + Device address match configuration + 0x640 + read-write + + + ENA0 + Enable or disable device address matching using device address 0 + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA1 + Enable or disable device address matching using device address 1 + 1 + 1 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA2 + Enable or disable device address matching using device address 2 + 2 + 2 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA3 + Enable or disable device address matching using device address 3 + 3 + 3 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA4 + Enable or disable device address matching using device address 4 + 4 + 4 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA5 + Enable or disable device address matching using device address 5 + 5 + 5 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA6 + Enable or disable device address matching using device address 6 + 6 + 6 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA7 + Enable or disable device address matching using device address 7 + 7 + 7 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + TXADD0 + TxAdd for device address 0 + 8 + 8 + + + TXADD1 + TxAdd for device address 1 + 9 + 9 + + + TXADD2 + TxAdd for device address 2 + 10 + 10 + + + TXADD3 + TxAdd for device address 3 + 11 + 11 + + + TXADD4 + TxAdd for device address 4 + 12 + 12 + + + TXADD5 + TxAdd for device address 5 + 13 + 13 + + + TXADD6 + TxAdd for device address 6 + 14 + 14 + + + TXADD7 + TxAdd for device address 7 + 15 + 15 + + + + + MHRMATCHCONF + Search pattern configuration + 0x644 + read-write + + + MHRMATCHCONF + Search pattern configuration + 0 + 31 + + + + + MHRMATCHMAS + Pattern mask + 0x648 + read-write + + + MHRMATCHMAS + Pattern mask + 0 + 31 + + + + + MODECNF0 + Radio mode configuration register 0 + 0x650 + read-write + 0x00000200 + + + RU + Radio ramp-up time + 0 + 0 + + + Default + Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51 + 0 + + + Fast + Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specifications for more information + 1 + + + + + DTX + Default TX value + 8 + 9 + + + B1 + Transmit '1' + 0 + + + B0 + Transmit '0' + 1 + + + Center + Transmit center frequency + 2 + + + + + + + SFD + IEEE 802.15.4 start of frame delimiter + 0x660 + read-write + 0x000000A7 + + + SFD + IEEE 802.15.4 start of frame delimiter + 0 + 7 + + + + + EDCNT + IEEE 802.15.4 energy detect loop count + 0x664 + read-write + 0x00000000 + + + EDCNT + IEEE 802.15.4 energy detect loop count + 0 + 20 + + + + + EDSAMPLE + IEEE 802.15.4 energy detect level + 0x668 + read-only + 0x00000000 + + + EDLVL + IEEE 802.15.4 energy detect level + 0 + 7 + + + + + CCACTRL + IEEE 802.15.4 clear channel assessment control + 0x66C + read-write + 0x052D0000 + + + CCAMODE + CCA mode of operation + 0 + 2 + + + EdMode + Energy above threshold + 0 + + + CarrierMode + Carrier seen + 1 + + + CarrierAndEdMode + Energy above threshold AND carrier seen + 2 + + + CarrierOrEdMode + Energy above threshold OR carrier seen + 3 + + + EdModeTest1 + Energy above threshold test mode that will abort when first ED measurement over threshold is seen. No averaging. + 4 + + + + + CCAEDTHRES + CCA energy busy threshold. Used in all the CCA modes except CarrierMode. + 8 + 15 + + + CCACORRTHRES + CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode, and CarrierOrEdMode. + 16 + 23 + + + CCACORRCNT + Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect is enabled. + 24 + 31 + + + + + DFEMODE + Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure (AOD) + 0x900 + read-write + 0x00000000 + + + DFEOPMODE + Direction finding operation mode + 0 + 1 + + + Disabled + Direction finding mode disabled + 0 + + + AoD + Direction finding mode set to AoD + 2 + + + AoA + Direction finding mode set to AoA + 3 + + + + + + + CTEINLINECONF + Configuration for CTE inline mode + 0x904 + read-write + 0x00002800 + + + CTEINLINECTRLEN + Enable parsing of CTEInfo from received packet in BLE modes + 0 + 0 + + + Enabled + Parsing of CTEInfo is enabled + 1 + + + Disabled + Parsing of CTEInfo is disabled + 0 + + + + + CTEINFOINS1 + CTEInfo is S1 byte or not + 3 + 3 + + + InS1 + CTEInfo is in S1 byte (data PDU) + 1 + + + NotInS1 + CTEInfo is NOT in S1 byte (advertising PDU) + 0 + + + + + CTEERRORHANDLING + Sampling/switching if CRC is not OK + 4 + 4 + + + Yes + Sampling and antenna switching also when CRC is not OK + 1 + + + No + No sampling and antenna switching when CRC is not OK + 0 + + + + + CTETIMEVALIDRANGE + Max range of CTETime + 6 + 7 + + + 20 + 20 in 8 us unit (default) Set to 20 if parsed CTETime is larger than 20 + 0 + + + 31 + 31 in 8 us unit + 1 + + + 63 + 63 in 8 us unit + 2 + + + + + CTEINLINERXMODE1US + Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set. + 10 + 12 + + + 4us + 4 us + 1 + + + 2us + 2 us + 2 + + + 1us + 1 us + 3 + + + 500ns + 0.5 us + 4 + + + 250ns + 0.25 us + 5 + + + 125ns + 0.125 us + 6 + + + + + CTEINLINERXMODE2US + Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set. + 13 + 15 + + + 4us + 4 us + 1 + + + 2us + 2 us + 2 + + + 1us + 1 us + 3 + + + 500ns + 0.5 us + 4 + + + 250ns + 0.25 us + 5 + + + 125ns + 0.125 us + 6 + + + + + S0CONF + S0 bit pattern to match + 16 + 23 + + + S0MASK + S0 bit mask to set which bit to match + 24 + 31 + + + + + DFECTRL1 + Various configuration for Direction finding + 0x910 + read-write + 0x00023282 + + + NUMBEROF8US + Length of the AoA/AoD procedure in number of 8 us units + 0 + 5 + + + DFEINEXTENSION + Add CTE extension and do antenna switching/sampling in this extension + 7 + 7 + + + CRC + AoA/AoD procedure triggered at end of CRC + 1 + + + Payload + Antenna switching/sampling is done in the packet payload + 0 + + + + + TSWITCHSPACING + Interval between every time the antenna is changed in the SWITCHING state + 8 + 10 + + + 4us + 4 us + 1 + + + 2us + 2 us + 2 + + + 1us + 1 us + 3 + + + + + TSAMPLESPACINGREF + Interval between samples in the REFERENCE period + 12 + 14 + + + 4us + 4 us + 1 + + + 2us + 2 us + 2 + + + 1us + 1 us + 3 + + + 500ns + 0.5 us + 4 + + + 250ns + 0.25 us + 5 + + + 125ns + 0.125 us + 6 + + + + + SAMPLETYPE + Whether to sample I/Q or magnitude/phase + 15 + 15 + + + IQ + Complex samples in I and Q + 0 + + + MagPhase + Complex samples as magnitude and phase + 1 + + + + + TSAMPLESPACING + Interval between samples in the SWITCHING period when CTEINLINECTRLEN is 0 + 16 + 18 + + + 4us + 4 us + 1 + + + 2us + 2 us + 2 + + + 1us + 1 us + 3 + + + 500ns + 0.5 us + 4 + + + 250ns + 0.25 us + 5 + + + 125ns + 0.125 us + 6 + + + + + AGCBACKOFFGAIN + Gain will be lowered by the specified number of gain steps at the start of CTE + 24 + 27 + + + + + DFECTRL2 + Start offset for Direction finding + 0x914 + read-write + 0x00000000 + + + TSWITCHOFFSET + Signed value offset after the end of the CRC before starting switching in number of 16M cycles + 0 + 12 + + + TSAMPLEOFFSET + Signed value offset before starting sampling in number of 16M cycles relative to the beginning of the REFERENCE state - 12 us after switching start + 16 + 27 + + + + + SWITCHPATTERN + GPIO patterns to be used for each antenna + 0x928 + read-write + 0x00000000 + + + SWITCHPATTERN + Fill array of GPIO patterns for antenna control. + 0 + 7 + + + + + CLEARPATTERN + Clear the GPIO pattern array for antenna control + 0x92C + read-write + + + CLEARPATTERN + Clears GPIO pattern array for antenna control + 0 + 0 + oneToClear + + + Clear + Clear the GPIO pattern + 1 + + + + + + + PSEL + Unspecified + RADIO_PSEL + read-write + 0x930 + + 0x8 + 0x4 + DFEGPIO[%s] + Description collection: Pin select for DFE pin n + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + DFEPACKET + DFE packet EasyDMA channel + RADIO_DFEPACKET + read-write + 0x950 + + PTR + Data pointer + 0x000 + read-write + 0x00000000 + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of buffer words to transfer + 0x004 + read-write + 0x00001000 + + + MAXCNT + Maximum number of buffer words to transfer + 0 + 12 + + + + + AMOUNT + Number of samples transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of samples transferred in the last transaction + 0 + 15 + + + + + + POWER + Peripheral power control + 0xFFC + read-write + 0x00000001 + + + POWER + Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. + 0 + 0 + + + Disabled + Peripheral is powered off + 0 + + + Enabled + Peripheral is powered on + 1 + + + + + + + + + UART0 + Universal Asynchronous Receiver/Transmitter + 0x40002000 + UART + + 0 + 0x1000 + registers + + + UARTE0_UART0 + 2 + + UART + 0x20 + + + TASKS_STARTRX + Start UART receiver + 0x000 + write-only + + + TASKS_STARTRX + Start UART receiver + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOPRX + Stop UART receiver + 0x004 + write-only + + + TASKS_STOPRX + Stop UART receiver + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTTX + Start UART transmitter + 0x008 + write-only + + + TASKS_STARTTX + Start UART transmitter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOPTX + Stop UART transmitter + 0x00C + write-only + + + TASKS_STOPTX + Stop UART transmitter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SUSPEND + Suspend UART + 0x01C + write-only + + + TASKS_SUSPEND + Suspend UART + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0x100 + read-write + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0x104 + read-write + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXDRDY + Data received in RXD + 0x108 + read-write + + + EVENTS_RXDRDY + Data received in RXD + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXDRDY + Data sent from TXD + 0x11C + read-write + + + EVENTS_TXDRDY + Data sent from TXD + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + Error detected + 0x124 + read-write + + + EVENTS_ERROR + Error detected + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXTO + Receiver timeout + 0x144 + read-write + + + EVENTS_RXTO + Receiver timeout + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + CTS_STARTRX + Shortcut between event CTS and task STARTRX + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + NCTS_STOPRX + Shortcut between event NCTS and task STOPRX + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + CTS + Write '1' to enable interrupt for event CTS + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + NCTS + Write '1' to enable interrupt for event NCTS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXDRDY + Write '1' to enable interrupt for event RXDRDY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXDRDY + Write '1' to enable interrupt for event TXDRDY + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXTO + Write '1' to enable interrupt for event RXTO + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + CTS + Write '1' to disable interrupt for event CTS + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + NCTS + Write '1' to disable interrupt for event NCTS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXDRDY + Write '1' to disable interrupt for event RXDRDY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXDRDY + Write '1' to disable interrupt for event TXDRDY + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXTO + Write '1' to disable interrupt for event RXTO + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source + 0x480 + read-write + oneToClear + + + OVERRUN + Overrun error + 0 + 0 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + PARITY + Parity error + 1 + 1 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + FRAMING + Framing error occurred + 2 + 2 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + BREAK + Break condition + 3 + 3 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + + + ENABLE + Enable UART + 0x500 + read-write + + + ENABLE + Enable or disable UART + 0 + 3 + + + Disabled + Disable UART + 0 + + + Enabled + Enable UART + 4 + + + + + + + PSEL + Unspecified + UART_PSEL + read-write + 0x508 + + RTS + Pin select for RTS + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + TXD + Pin select for TXD + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + CTS + Pin select for CTS + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + RXD + Pin select for RXD + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + RXD + RXD register + 0x518 + read-only + modifyExternal + + + RXD + RX data received in previous transfers, double buffered + 0 + 7 + + + + + TXD + TXD register + 0x51C + write-only + + + TXD + TX data to be transferred + 0 + 7 + + + + + BAUDRATE + Baud rate. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + BAUDRATE + Baud rate + 0 + 31 + + + Baud1200 + 1200 baud (actual rate: 1205) + 0x0004F000 + + + Baud2400 + 2400 baud (actual rate: 2396) + 0x0009D000 + + + Baud4800 + 4800 baud (actual rate: 4808) + 0x0013B000 + + + Baud9600 + 9600 baud (actual rate: 9598) + 0x00275000 + + + Baud14400 + 14400 baud (actual rate: 14414) + 0x003B0000 + + + Baud19200 + 19200 baud (actual rate: 19208) + 0x004EA000 + + + Baud28800 + 28800 baud (actual rate: 28829) + 0x0075F000 + + + Baud31250 + 31250 baud + 0x00800000 + + + Baud38400 + 38400 baud (actual rate: 38462) + 0x009D5000 + + + Baud56000 + 56000 baud (actual rate: 55944) + 0x00E50000 + + + Baud57600 + 57600 baud (actual rate: 57762) + 0x00EBF000 + + + Baud76800 + 76800 baud (actual rate: 76923) + 0x013A9000 + + + Baud115200 + 115200 baud (actual rate: 115942) + 0x01D7E000 + + + Baud230400 + 230400 baud (actual rate: 231884) + 0x03AFB000 + + + Baud250000 + 250000 baud + 0x04000000 + + + Baud460800 + 460800 baud (actual rate: 470588) + 0x075F7000 + + + Baud921600 + 921600 baud (actual rate: 941176) + 0x0EBED000 + + + Baud1M + 1Mega baud + 0x10000000 + + + + + + + CONFIG + Configuration of parity and hardware flow control + 0x56C + read-write + + + HWFC + Hardware flow control + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + PARITY + Parity + 1 + 3 + + + Excluded + Exclude parity bit + 0x0 + + + Included + Include parity bit + 0x7 + + + + + STOP + Stop bits + 4 + 4 + + + One + One stop bit + 0 + + + Two + Two stop bits + 1 + + + + + + + + + UARTE0 + UART with EasyDMA + 0x40002000 + UART0 + UARTE + + 0 + 0x1000 + registers + + + UARTE0_UART0 + 2 + + UARTE + 0x20 + + + TASKS_STARTRX + Start UART receiver + 0x000 + write-only + + + TASKS_STARTRX + Start UART receiver + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOPRX + Stop UART receiver + 0x004 + write-only + + + TASKS_STOPRX + Stop UART receiver + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTTX + Start UART transmitter + 0x008 + write-only + + + TASKS_STARTTX + Start UART transmitter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOPTX + Stop UART transmitter + 0x00C + write-only + + + TASKS_STOPTX + Stop UART transmitter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_FLUSHRX + Flush RX FIFO into RX buffer + 0x02C + write-only + + + TASKS_FLUSHRX + Flush RX FIFO into RX buffer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0x100 + read-write + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0x104 + read-write + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXDRDY + Data received in RXD (but potentially not yet transferred to Data RAM) + 0x108 + read-write + + + EVENTS_RXDRDY + Data received in RXD (but potentially not yet transferred to Data RAM) + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDRX + Receive buffer is filled up + 0x110 + read-write + + + EVENTS_ENDRX + Receive buffer is filled up + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXDRDY + Data sent from TXD + 0x11C + read-write + + + EVENTS_TXDRDY + Data sent from TXD + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDTX + Last TX byte transmitted + 0x120 + read-write + + + EVENTS_ENDTX + Last TX byte transmitted + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + Error detected + 0x124 + read-write + + + EVENTS_ERROR + Error detected + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXTO + Receiver timeout + 0x144 + read-write + + + EVENTS_RXTO + Receiver timeout + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXSTARTED + UART receiver has started + 0x14C + read-write + + + EVENTS_RXSTARTED + UART receiver has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXSTARTED + UART transmitter has started + 0x150 + read-write + + + EVENTS_TXSTARTED + UART transmitter has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXSTOPPED + Transmitter stopped + 0x158 + read-write + + + EVENTS_TXSTOPPED + Transmitter stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + ENDRX_STARTRX + Shortcut between event ENDRX and task STARTRX + 5 + 5 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + ENDRX_STOPRX + Shortcut between event ENDRX and task STOPRX + 6 + 6 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + CTS + Enable or disable interrupt for event CTS + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + NCTS + Enable or disable interrupt for event NCTS + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXDRDY + Enable or disable interrupt for event RXDRDY + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDRX + Enable or disable interrupt for event ENDRX + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXDRDY + Enable or disable interrupt for event TXDRDY + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDTX + Enable or disable interrupt for event ENDTX + 8 + 8 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXTO + Enable or disable interrupt for event RXTO + 17 + 17 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXSTARTED + Enable or disable interrupt for event RXSTARTED + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTARTED + Enable or disable interrupt for event TXSTARTED + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTOPPED + Enable or disable interrupt for event TXSTOPPED + 22 + 22 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + CTS + Write '1' to enable interrupt for event CTS + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + NCTS + Write '1' to enable interrupt for event NCTS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXDRDY + Write '1' to enable interrupt for event RXDRDY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDRX + Write '1' to enable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXDRDY + Write '1' to enable interrupt for event TXDRDY + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDTX + Write '1' to enable interrupt for event ENDTX + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXTO + Write '1' to enable interrupt for event RXTO + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXSTARTED + Write '1' to enable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTARTED + Write '1' to enable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTOPPED + Write '1' to enable interrupt for event TXSTOPPED + 22 + 22 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + CTS + Write '1' to disable interrupt for event CTS + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + NCTS + Write '1' to disable interrupt for event NCTS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXDRDY + Write '1' to disable interrupt for event RXDRDY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDRX + Write '1' to disable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXDRDY + Write '1' to disable interrupt for event TXDRDY + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDTX + Write '1' to disable interrupt for event ENDTX + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXTO + Write '1' to disable interrupt for event RXTO + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXSTARTED + Write '1' to disable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXSTARTED + Write '1' to disable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXSTOPPED + Write '1' to disable interrupt for event TXSTOPPED + 22 + 22 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source Note : this register is read / write one to clear. + 0x480 + read-write + oneToClear + + + OVERRUN + Overrun error + 0 + 0 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + PARITY + Parity error + 1 + 1 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + FRAMING + Framing error occurred + 2 + 2 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + BREAK + Break condition + 3 + 3 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + + + ENABLE + Enable UART + 0x500 + read-write + + + ENABLE + Enable or disable UARTE + 0 + 3 + + + Disabled + Disable UARTE + 0 + + + Enabled + Enable UARTE + 8 + + + + + + + PSEL + Unspecified + UARTE_PSEL + read-write + 0x508 + + RTS + Pin select for RTS signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + TXD + Pin select for TXD signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + CTS + Pin select for CTS signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + RXD + Pin select for RXD signal + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + BAUDRATE + Baud rate. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + BAUDRATE + Baud rate + 0 + 31 + + + Baud1200 + 1200 baud (actual rate: 1205) + 0x0004F000 + + + Baud2400 + 2400 baud (actual rate: 2396) + 0x0009D000 + + + Baud4800 + 4800 baud (actual rate: 4808) + 0x0013B000 + + + Baud9600 + 9600 baud (actual rate: 9598) + 0x00275000 + + + Baud14400 + 14400 baud (actual rate: 14401) + 0x003AF000 + + + Baud19200 + 19200 baud (actual rate: 19208) + 0x004EA000 + + + Baud28800 + 28800 baud (actual rate: 28777) + 0x0075C000 + + + Baud31250 + 31250 baud + 0x00800000 + + + Baud38400 + 38400 baud (actual rate: 38369) + 0x009D0000 + + + Baud56000 + 56000 baud (actual rate: 55944) + 0x00E50000 + + + Baud57600 + 57600 baud (actual rate: 57554) + 0x00EB0000 + + + Baud76800 + 76800 baud (actual rate: 76923) + 0x013A9000 + + + Baud115200 + 115200 baud (actual rate: 115108) + 0x01D60000 + + + Baud230400 + 230400 baud (actual rate: 231884) + 0x03B00000 + + + Baud250000 + 250000 baud + 0x04000000 + + + Baud460800 + 460800 baud (actual rate: 457143) + 0x07400000 + + + Baud921600 + 921600 baud (actual rate: 941176) + 0x0F000000 + + + Baud1M + 1Mega baud + 0x10000000 + + + + + + + RXD + RXD EasyDMA channel + UARTE_RXD + read-write + 0x534 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 9 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 9 + + + + + + TXD + TXD EasyDMA channel + UARTE_TXD + read-write + 0x544 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 9 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 9 + + + + + + CONFIG + Configuration of parity and hardware flow control + 0x56C + read-write + + + HWFC + Hardware flow control + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + PARITY + Parity + 1 + 3 + + + Excluded + Exclude parity bit + 0x0 + + + Included + Include even parity bit + 0x7 + + + + + STOP + Stop bits + 4 + 4 + + + One + One stop bit + 0 + + + Two + Two stop bits + 1 + + + + + + + + + SPI1 + Serial Peripheral Interface 0 + 0x40003000 + SPI + + 0 + 0x1000 + registers + + + TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1 + 3 + + SPI + 0x20 + + + EVENTS_READY + TXD byte sent and RXD byte received + 0x108 + read-write + + + EVENTS_READY + TXD byte sent and RXD byte received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + READY + Write '1' to enable interrupt for event READY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + READY + Write '1' to disable interrupt for event READY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + Enable SPI + 0x500 + read-write + + + ENABLE + Enable or disable SPI + 0 + 3 + + + Disabled + Disable SPI + 0 + + + Enabled + Enable SPI + 1 + + + + + + + PSEL + Unspecified + SPI_PSEL + read-write + 0x508 + + SCK + Pin select for SCK + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MOSI + Pin select for MOSI signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MISO + Pin select for MISO signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + RXD + RXD register + 0x518 + read-only + modifyExternal + + + RXD + RX data received. Double buffered + 0 + 7 + + + + + TXD + TXD register + 0x51C + read-write + + + TXD + TX data to send. Double buffered + 0 + 7 + + + + + FREQUENCY + SPI frequency. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + FREQUENCY + SPI master data rate + 0 + 31 + + + K125 + 125 kbps + 0x02000000 + + + K250 + 250 kbps + 0x04000000 + + + K500 + 500 kbps + 0x08000000 + + + M1 + 1 Mbps + 0x10000000 + + + M2 + 2 Mbps + 0x20000000 + + + M4 + 4 Mbps + 0x40000000 + + + M8 + 8 Mbps + 0x80000000 + + + + + + + CONFIG + Configuration register + 0x554 + read-write + + + ORDER + Bit order + 0 + 0 + + + MsbFirst + Most significant bit shifted out first + 0 + + + LsbFirst + Least significant bit shifted out first + 1 + + + + + CPHA + Serial clock (SCK) phase + 1 + 1 + + + Leading + Sample on leading edge of clock, shift serial data on trailing edge + 0 + + + Trailing + Sample on trailing edge of clock, shift serial data on leading edge + 1 + + + + + CPOL + Serial clock (SCK) polarity + 2 + 2 + + + ActiveHigh + Active high + 0 + + + ActiveLow + Active low + 1 + + + + + + + + + SPIM1 + Serial Peripheral Interface Master with EasyDMA 0 + 0x40003000 + SPI1 + SPIM + + 0 + 0x1000 + registers + + + TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1 + 3 + + SPIM + 0x20 + + + TASKS_START + Start SPI transaction + 0x010 + write-only + + + TASKS_START + Start SPI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop SPI transaction + 0x014 + write-only + + + TASKS_STOP + Stop SPI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SUSPEND + Suspend SPI transaction + 0x01C + write-only + + + TASKS_SUSPEND + Suspend SPI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RESUME + Resume SPI transaction + 0x020 + write-only + + + TASKS_RESUME + Resume SPI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_STOPPED + SPI transaction has stopped + 0x104 + read-write + + + EVENTS_STOPPED + SPI transaction has stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDRX + End of RXD buffer reached + 0x110 + read-write + + + EVENTS_ENDRX + End of RXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_END + End of RXD buffer and TXD buffer reached + 0x118 + read-write + + + EVENTS_END + End of RXD buffer and TXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDTX + End of TXD buffer reached + 0x120 + read-write + + + EVENTS_ENDTX + End of TXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STARTED + Transaction started + 0x14C + read-write + + + EVENTS_STARTED + Transaction started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + END_START + Shortcut between event END and task START + 17 + 17 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDRX + Write '1' to enable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + END + Write '1' to enable interrupt for event END + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDTX + Write '1' to enable interrupt for event ENDTX + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STARTED + Write '1' to enable interrupt for event STARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDRX + Write '1' to disable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + END + Write '1' to disable interrupt for event END + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDTX + Write '1' to disable interrupt for event ENDTX + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STARTED + Write '1' to disable interrupt for event STARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + Enable SPIM + 0x500 + read-write + + + ENABLE + Enable or disable SPIM + 0 + 3 + + + Disabled + Disable SPIM + 0 + + + Enabled + Enable SPIM + 7 + + + + + + + PSEL + Unspecified + SPIM_PSEL + read-write + 0x508 + + SCK + Pin select for SCK + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MOSI + Pin select for MOSI signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MISO + Pin select for MISO signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + FREQUENCY + SPI frequency. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + FREQUENCY + SPI master data rate + 0 + 31 + + + K125 + 125 kbps + 0x02000000 + + + K250 + 250 kbps + 0x04000000 + + + K500 + 500 kbps + 0x08000000 + + + M1 + 1 Mbps + 0x10000000 + + + M2 + 2 Mbps + 0x20000000 + + + M4 + 4 Mbps + 0x40000000 + + + M8 + 8 Mbps + 0x80000000 + + + + + + + RXD + RXD EasyDMA channel + SPIM_RXD + read-write + 0x534 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 13 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 13 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + TXD + TXD EasyDMA channel + SPIM_TXD + read-write + 0x544 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 13 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 13 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + CONFIG + Configuration register + 0x554 + read-write + + + ORDER + Bit order + 0 + 0 + + + MsbFirst + Most significant bit shifted out first + 0 + + + LsbFirst + Least significant bit shifted out first + 1 + + + + + CPHA + Serial clock (SCK) phase + 1 + 1 + + + Leading + Sample on leading edge of clock, shift serial data on trailing edge + 0 + + + Trailing + Sample on trailing edge of clock, shift serial data on leading edge + 1 + + + + + CPOL + Serial clock (SCK) polarity + 2 + 2 + + + ActiveHigh + Active high + 0 + + + ActiveLow + Active low + 1 + + + + + + + ORC + Over-read character. Character clocked out in case and over-read of the TXD buffer. + 0x5C0 + read-write + + + ORC + Over-read character. Character clocked out in case and over-read of the TXD buffer. + 0 + 7 + + + + + + + SPIS1 + SPI Slave 0 + 0x40003000 + SPI1 + SPIS + + 0 + 0x1000 + registers + + + TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1 + 3 + + SPIS + 0x20 + + + TASKS_ACQUIRE + Acquire SPI semaphore + 0x024 + write-only + + + TASKS_ACQUIRE + Acquire SPI semaphore + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RELEASE + Release SPI semaphore, enabling the SPI slave to acquire it + 0x028 + write-only + + + TASKS_RELEASE + Release SPI semaphore, enabling the SPI slave to acquire it + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_END + Granted transaction completed + 0x104 + read-write + + + EVENTS_END + Granted transaction completed + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDRX + End of RXD buffer reached + 0x110 + read-write + + + EVENTS_ENDRX + End of RXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ACQUIRED + Semaphore acquired + 0x128 + read-write + + + EVENTS_ACQUIRED + Semaphore acquired + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + END_ACQUIRE + Shortcut between event END and task ACQUIRE + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + END + Write '1' to enable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDRX + Write '1' to enable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ACQUIRED + Write '1' to enable interrupt for event ACQUIRED + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + END + Write '1' to disable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDRX + Write '1' to disable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ACQUIRED + Write '1' to disable interrupt for event ACQUIRED + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + SEMSTAT + Semaphore status register + 0x400 + read-only + 0x00000001 + + + SEMSTAT + Semaphore status + 0 + 1 + + + Free + Semaphore is free + 0 + + + CPU + Semaphore is assigned to CPU + 1 + + + SPIS + Semaphore is assigned to SPI slave + 2 + + + CPUPending + Semaphore is assigned to SPI but a handover to the CPU is pending + 3 + + + + + + + STATUS + Status from last transaction + 0x440 + read-write + + + OVERREAD + TX buffer over-read detected, and prevented + 0 + 0 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + write + + Clear + Write: clear error on writing '1' + 1 + + + + + OVERFLOW + RX buffer overflow detected, and prevented + 1 + 1 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + write + + Clear + Write: clear error on writing '1' + 1 + + + + + + + ENABLE + Enable SPI slave + 0x500 + read-write + + + ENABLE + Enable or disable SPI slave + 0 + 3 + + + Disabled + Disable SPI slave + 0 + + + Enabled + Enable SPI slave + 2 + + + + + + + PSEL + Unspecified + SPIS_PSEL + read-write + 0x508 + + SCK + Pin select for SCK + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MISO + Pin select for MISO signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MOSI + Pin select for MOSI signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + CSN + Pin select for CSN signal + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + RXD + Unspecified + SPIS_RXD + read-write + 0x534 + + PTR + RXD data pointer + 0x000 + read-write + + + PTR + RXD data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 13 + + + + + AMOUNT + Number of bytes received in last granted transaction + 0x008 + read-only + + + AMOUNT + Number of bytes received in the last granted transaction + 0 + 13 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + TXD + Unspecified + SPIS_TXD + read-write + 0x544 + + PTR + TXD data pointer + 0x000 + read-write + + + PTR + TXD data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 13 + + + + + AMOUNT + Number of bytes transmitted in last granted transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transmitted in last granted transaction + 0 + 13 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + CONFIG + Configuration register + 0x554 + read-write + + + ORDER + Bit order + 0 + 0 + + + MsbFirst + Most significant bit shifted out first + 0 + + + LsbFirst + Least significant bit shifted out first + 1 + + + + + CPHA + Serial clock (SCK) phase + 1 + 1 + + + Leading + Sample on leading edge of clock, shift serial data on trailing edge + 0 + + + Trailing + Sample on trailing edge of clock, shift serial data on leading edge + 1 + + + + + CPOL + Serial clock (SCK) polarity + 2 + 2 + + + ActiveHigh + Active high + 0 + + + ActiveLow + Active low + 1 + + + + + + + DEF + Default character. Character clocked out in case of an ignored transaction. + 0x55C + read-write + + + DEF + Default character. Character clocked out in case of an ignored transaction. + 0 + 7 + + + + + ORC + Over-read character + 0x5C0 + read-write + + + ORC + Over-read character. Character clocked out after an over-read of the transmit buffer. + 0 + 7 + + + + + + + TWI0 + I2C compatible Two-Wire Interface + 0x40003000 + SPI1 + TWI + + 0 + 0x1000 + registers + + + TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1 + 3 + + TWI + 0x20 + + + TASKS_STARTRX + Start TWI receive sequence + 0x000 + write-only + + + TASKS_STARTRX + Start TWI receive sequence + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTTX + Start TWI transmit sequence + 0x008 + write-only + + + TASKS_STARTTX + Start TWI transmit sequence + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop TWI transaction + 0x014 + write-only + + + TASKS_STOP + Stop TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SUSPEND + Suspend TWI transaction + 0x01C + write-only + + + TASKS_SUSPEND + Suspend TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RESUME + Resume TWI transaction + 0x020 + write-only + + + TASKS_RESUME + Resume TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_STOPPED + TWI stopped + 0x104 + read-write + + + EVENTS_STOPPED + TWI stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXDREADY + TWI RXD byte received + 0x108 + read-write + + + EVENTS_RXDREADY + TWI RXD byte received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXDSENT + TWI TXD byte sent + 0x11C + read-write + + + EVENTS_TXDSENT + TWI TXD byte sent + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + TWI error + 0x124 + read-write + + + EVENTS_ERROR + TWI error + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_BB + TWI byte boundary, generated before each byte that is sent or received + 0x138 + read-write + + + EVENTS_BB + TWI byte boundary, generated before each byte that is sent or received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SUSPENDED + TWI entered the suspended state + 0x148 + read-write + + + EVENTS_SUSPENDED + TWI entered the suspended state + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + BB_SUSPEND + Shortcut between event BB and task SUSPEND + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + BB_STOP + Shortcut between event BB and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXDREADY + Write '1' to enable interrupt for event RXDREADY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXDSENT + Write '1' to enable interrupt for event TXDSENT + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + BB + Write '1' to enable interrupt for event BB + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SUSPENDED + Write '1' to enable interrupt for event SUSPENDED + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXDREADY + Write '1' to disable interrupt for event RXDREADY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXDSENT + Write '1' to disable interrupt for event TXDSENT + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + BB + Write '1' to disable interrupt for event BB + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SUSPENDED + Write '1' to disable interrupt for event SUSPENDED + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source + 0x4C4 + read-write + oneToClear + + + OVERRUN + Overrun error + 0 + 0 + + read + + NotPresent + Read: no overrun occured + 0 + + + Present + Read: overrun occured + 1 + + + + + ANACK + NACK received after sending the address (write '1' to clear) + 1 + 1 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + DNACK + NACK received after sending a data byte (write '1' to clear) + 2 + 2 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + + + ENABLE + Enable TWI + 0x500 + read-write + + + ENABLE + Enable or disable TWI + 0 + 3 + + + Disabled + Disable TWI + 0 + + + Enabled + Enable TWI + 5 + + + + + + + PSEL + Unspecified + TWI_PSEL + read-write + 0x508 + + SCL + Pin select for SCL + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDA + Pin select for SDA + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + RXD + RXD register + 0x518 + read-only + modifyExternal + + + RXD + RXD register + 0 + 7 + + + + + TXD + TXD register + 0x51C + read-write + + + TXD + TXD register + 0 + 7 + + + + + FREQUENCY + TWI frequency. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + FREQUENCY + TWI master clock frequency + 0 + 31 + + + K100 + 100 kbps + 0x01980000 + + + K250 + 250 kbps + 0x04000000 + + + K400 + 400 kbps (actual rate 410.256 kbps) + 0x06680000 + + + + + + + ADDRESS + Address used in the TWI transfer + 0x588 + read-write + + + ADDRESS + Address used in the TWI transfer + 0 + 6 + + + + + + + TWIM0 + I2C compatible Two-Wire Master Interface with EasyDMA + 0x40003000 + SPI1 + TWIM + + 0 + 0x1000 + registers + + + TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1 + 3 + + TWIM + 0x20 + + + TASKS_STARTRX + Start TWI receive sequence + 0x000 + write-only + + + TASKS_STARTRX + Start TWI receive sequence + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTTX + Start TWI transmit sequence + 0x008 + write-only + + + TASKS_STARTTX + Start TWI transmit sequence + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop TWI transaction. Must be issued while the TWI master is not suspended. + 0x014 + write-only + + + TASKS_STOP + Stop TWI transaction. Must be issued while the TWI master is not suspended. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SUSPEND + Suspend TWI transaction + 0x01C + write-only + + + TASKS_SUSPEND + Suspend TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RESUME + Resume TWI transaction + 0x020 + write-only + + + TASKS_RESUME + Resume TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_STOPPED + TWI stopped + 0x104 + read-write + + + EVENTS_STOPPED + TWI stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + TWI error + 0x124 + read-write + + + EVENTS_ERROR + TWI error + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SUSPENDED + Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. + 0x148 + read-write + + + EVENTS_SUSPENDED + Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXSTARTED + Receive sequence started + 0x14C + read-write + + + EVENTS_RXSTARTED + Receive sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXSTARTED + Transmit sequence started + 0x150 + read-write + + + EVENTS_TXSTARTED + Transmit sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_LASTRX + Byte boundary, starting to receive the last byte + 0x15C + read-write + + + EVENTS_LASTRX + Byte boundary, starting to receive the last byte + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_LASTTX + Byte boundary, starting to transmit the last byte + 0x160 + read-write + + + EVENTS_LASTTX + Byte boundary, starting to transmit the last byte + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + LASTTX_STARTRX + Shortcut between event LASTTX and task STARTRX + 7 + 7 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTTX_SUSPEND + Shortcut between event LASTTX and task SUSPEND + 8 + 8 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTTX_STOP + Shortcut between event LASTTX and task STOP + 9 + 9 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTRX_STARTTX + Shortcut between event LASTRX and task STARTTX + 10 + 10 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTRX_SUSPEND + Shortcut between event LASTRX and task SUSPEND + 11 + 11 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTRX_STOP + Shortcut between event LASTRX and task STOP + 12 + 12 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SUSPENDED + Enable or disable interrupt for event SUSPENDED + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXSTARTED + Enable or disable interrupt for event RXSTARTED + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTARTED + Enable or disable interrupt for event TXSTARTED + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + LASTRX + Enable or disable interrupt for event LASTRX + 23 + 23 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + LASTTX + Enable or disable interrupt for event LASTTX + 24 + 24 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SUSPENDED + Write '1' to enable interrupt for event SUSPENDED + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXSTARTED + Write '1' to enable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTARTED + Write '1' to enable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + LASTRX + Write '1' to enable interrupt for event LASTRX + 23 + 23 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + LASTTX + Write '1' to enable interrupt for event LASTTX + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SUSPENDED + Write '1' to disable interrupt for event SUSPENDED + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXSTARTED + Write '1' to disable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXSTARTED + Write '1' to disable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + LASTRX + Write '1' to disable interrupt for event LASTRX + 23 + 23 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + LASTTX + Write '1' to disable interrupt for event LASTTX + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source + 0x4C4 + read-write + oneToClear + + + OVERRUN + Overrun error + 0 + 0 + + + NotReceived + Error did not occur + 0 + + + Received + Error occurred + 1 + + + + + ANACK + NACK received after sending the address (write '1' to clear) + 1 + 1 + + + NotReceived + Error did not occur + 0 + + + Received + Error occurred + 1 + + + + + DNACK + NACK received after sending a data byte (write '1' to clear) + 2 + 2 + + + NotReceived + Error did not occur + 0 + + + Received + Error occurred + 1 + + + + + + + ENABLE + Enable TWIM + 0x500 + read-write + + + ENABLE + Enable or disable TWIM + 0 + 3 + + + Disabled + Disable TWIM + 0 + + + Enabled + Enable TWIM + 6 + + + + + + + PSEL + Unspecified + TWIM_PSEL + read-write + 0x508 + + SCL + Pin select for SCL signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDA + Pin select for SDA signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + FREQUENCY + TWI frequency. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + FREQUENCY + TWI master clock frequency + 0 + 31 + + + K100 + 100 kbps + 0x01980000 + + + K250 + 250 kbps + 0x04000000 + + + K400 + 400 kbps + 0x06400000 + + + + + + + RXD + RXD EasyDMA channel + TWIM_RXD + read-write + 0x534 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 13 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 13 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + TXD + TXD EasyDMA channel + TWIM_TXD + read-write + 0x544 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 13 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 13 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + ADDRESS + Address used in the TWI transfer + 0x588 + read-write + + + ADDRESS + Address used in the TWI transfer + 0 + 6 + + + + + + + TWIS0 + I2C compatible Two-Wire Slave Interface with EasyDMA + 0x40003000 + SPI1 + TWIS + + 0 + 0x1000 + registers + + + TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1 + 3 + + TWIS + 0x20 + + + TASKS_STOP + Stop TWI transaction + 0x014 + write-only + + + TASKS_STOP + Stop TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SUSPEND + Suspend TWI transaction + 0x01C + write-only + + + TASKS_SUSPEND + Suspend TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RESUME + Resume TWI transaction + 0x020 + write-only + + + TASKS_RESUME + Resume TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_PREPARERX + Prepare the TWI slave to respond to a write command + 0x030 + write-only + + + TASKS_PREPARERX + Prepare the TWI slave to respond to a write command + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_PREPARETX + Prepare the TWI slave to respond to a read command + 0x034 + write-only + + + TASKS_PREPARETX + Prepare the TWI slave to respond to a read command + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_STOPPED + TWI stopped + 0x104 + read-write + + + EVENTS_STOPPED + TWI stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + TWI error + 0x124 + read-write + + + EVENTS_ERROR + TWI error + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXSTARTED + Receive sequence started + 0x14C + read-write + + + EVENTS_RXSTARTED + Receive sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXSTARTED + Transmit sequence started + 0x150 + read-write + + + EVENTS_TXSTARTED + Transmit sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_WRITE + Write command received + 0x164 + read-write + + + EVENTS_WRITE + Write command received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_READ + Read command received + 0x168 + read-write + + + EVENTS_READ + Read command received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + WRITE_SUSPEND + Shortcut between event WRITE and task SUSPEND + 13 + 13 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + READ_SUSPEND + Shortcut between event READ and task SUSPEND + 14 + 14 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXSTARTED + Enable or disable interrupt for event RXSTARTED + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTARTED + Enable or disable interrupt for event TXSTARTED + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + WRITE + Enable or disable interrupt for event WRITE + 25 + 25 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + READ + Enable or disable interrupt for event READ + 26 + 26 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXSTARTED + Write '1' to enable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTARTED + Write '1' to enable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + WRITE + Write '1' to enable interrupt for event WRITE + 25 + 25 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + READ + Write '1' to enable interrupt for event READ + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXSTARTED + Write '1' to disable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXSTARTED + Write '1' to disable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + WRITE + Write '1' to disable interrupt for event WRITE + 25 + 25 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + READ + Write '1' to disable interrupt for event READ + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source + 0x4D0 + read-write + oneToClear + + + OVERFLOW + RX buffer overflow detected, and prevented + 0 + 0 + + + NotDetected + Error did not occur + 0 + + + Detected + Error occurred + 1 + + + + + DNACK + NACK sent after receiving a data byte + 2 + 2 + + + NotReceived + Error did not occur + 0 + + + Received + Error occurred + 1 + + + + + OVERREAD + TX buffer over-read detected, and prevented + 3 + 3 + + + NotDetected + Error did not occur + 0 + + + Detected + Error occurred + 1 + + + + + + + MATCH + Status register indicating which address had a match + 0x4D4 + read-only + + + MATCH + Which of the addresses in {ADDRESS} matched the incoming address + 0 + 0 + + + + + ENABLE + Enable TWIS + 0x500 + read-write + + + ENABLE + Enable or disable TWIS + 0 + 3 + + + Disabled + Disable TWIS + 0 + + + Enabled + Enable TWIS + 9 + + + + + + + PSEL + Unspecified + TWIS_PSEL + read-write + 0x508 + + SCL + Pin select for SCL signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDA + Pin select for SDA signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + RXD + RXD EasyDMA channel + TWIS_RXD + read-write + 0x534 + + PTR + RXD Data pointer + 0x000 + read-write + + + PTR + RXD Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in RXD buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in RXD buffer + 0 + 13 + + + + + AMOUNT + Number of bytes transferred in the last RXD transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last RXD transaction + 0 + 13 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + TXD + TXD EasyDMA channel + TWIS_TXD + read-write + 0x544 + + PTR + TXD Data pointer + 0x000 + read-write + + + PTR + TXD Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in TXD buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in TXD buffer + 0 + 13 + + + + + AMOUNT + Number of bytes transferred in the last TXD transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last TXD transaction + 0 + 13 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + 0x2 + 0x4 + ADDRESS[%s] + Description collection: TWI slave address n + 0x588 + read-write + + + ADDRESS + TWI slave address + 0 + 6 + + + + + CONFIG + Configuration register for the address match mechanism + 0x594 + read-write + 0x00000001 + + + ADDRESS0 + Enable or disable address matching on ADDRESS[0] + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ADDRESS1 + Enable or disable address matching on ADDRESS[1] + 1 + 1 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + + + ORC + Over-read character. Character sent out in case of an over-read of the transmit buffer. + 0x5C0 + read-write + + + ORC + Over-read character. Character sent out in case of an over-read of the transmit buffer. + 0 + 7 + + + + + + + SPI0 + Serial Peripheral Interface 1 + 0x40004000 + + SPIM0_SPIS0_SPI0 + 4 + + + + SPIM0 + Serial Peripheral Interface Master with EasyDMA 1 + 0x40004000 + SPI0 + + SPIM0_SPIS0_SPI0 + 4 + + + + SPIS0 + SPI Slave 1 + 0x40004000 + SPI0 + + SPIM0_SPIS0_SPI0 + 4 + + + + GPIOTE + GPIO Tasks and Events + 0x40006000 + + 0 + 0x1000 + registers + + + GPIOTE + 6 + + GPIOTE + 0x20 + + + 0x8 + 0x4 + TASKS_OUT[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. + 0x000 + write-only + + + TASKS_OUT + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x8 + 0x4 + TASKS_SET[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. + 0x030 + write-only + + + TASKS_SET + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x8 + 0x4 + TASKS_CLR[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. + 0x060 + write-only + + + TASKS_CLR + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x8 + 0x4 + EVENTS_IN[%s] + Description collection: Event generated from pin specified in CONFIG[n].PSEL + 0x100 + read-write + + + EVENTS_IN + Event generated from pin specified in CONFIG[n].PSEL + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_PORT + Event generated from multiple input GPIO pins with SENSE mechanism enabled + 0x17C + read-write + + + EVENTS_PORT + Event generated from multiple input GPIO pins with SENSE mechanism enabled + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + IN0 + Write '1' to enable interrupt for event IN[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN1 + Write '1' to enable interrupt for event IN[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN2 + Write '1' to enable interrupt for event IN[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN3 + Write '1' to enable interrupt for event IN[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN4 + Write '1' to enable interrupt for event IN[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN5 + Write '1' to enable interrupt for event IN[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN6 + Write '1' to enable interrupt for event IN[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN7 + Write '1' to enable interrupt for event IN[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PORT + Write '1' to enable interrupt for event PORT + 31 + 31 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + IN0 + Write '1' to disable interrupt for event IN[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN1 + Write '1' to disable interrupt for event IN[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN2 + Write '1' to disable interrupt for event IN[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN3 + Write '1' to disable interrupt for event IN[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN4 + Write '1' to disable interrupt for event IN[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN5 + Write '1' to disable interrupt for event IN[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN6 + Write '1' to disable interrupt for event IN[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN7 + Write '1' to disable interrupt for event IN[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PORT + Write '1' to disable interrupt for event PORT + 31 + 31 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + 0x8 + 0x4 + CONFIG[%s] + Description collection: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event + 0x510 + read-write + + + MODE + Mode + 0 + 1 + + + Disabled + Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. + 0 + + + Event + Event mode + 1 + + + Task + Task mode + 3 + + + + + PSEL + GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event + 8 + 12 + + + POLARITY + When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. + 16 + 17 + + + None + Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. + 0 + + + LoToHi + Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. + 1 + + + HiToLo + Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. + 2 + + + Toggle + Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. + 3 + + + + + OUTINIT + When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. + 20 + 20 + + + Low + Task mode: Initial value of pin before task triggering is low + 0 + + + High + Task mode: Initial value of pin before task triggering is high + 1 + + + + + + + + + SAADC + Analog to Digital Converter + 0x40007000 + + 0 + 0x1000 + registers + + + SAADC + 7 + + SAADC + 0x20 + + + TASKS_START + Start the ADC and prepare the result buffer in RAM + 0x000 + write-only + + + TASKS_START + Start the ADC and prepare the result buffer in RAM + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SAMPLE + Take one ADC sample, if scan is enabled all channels are sampled + 0x004 + write-only + + + TASKS_SAMPLE + Take one ADC sample, if scan is enabled all channels are sampled + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop the ADC and terminate any on-going conversion + 0x008 + write-only + + + TASKS_STOP + Stop the ADC and terminate any on-going conversion + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CALIBRATEOFFSET + Starts offset auto-calibration + 0x00C + write-only + + + TASKS_CALIBRATEOFFSET + Starts offset auto-calibration + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_STARTED + The ADC has started + 0x100 + read-write + + + EVENTS_STARTED + The ADC has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_END + The ADC has filled up the Result buffer + 0x104 + read-write + + + EVENTS_END + The ADC has filled up the Result buffer + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DONE + A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. + 0x108 + read-write + + + EVENTS_DONE + A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RESULTDONE + A result is ready to get transferred to RAM. + 0x10C + read-write + + + EVENTS_RESULTDONE + A result is ready to get transferred to RAM. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CALIBRATEDONE + Calibration is complete + 0x110 + read-write + + + EVENTS_CALIBRATEDONE + Calibration is complete + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STOPPED + The ADC has stopped + 0x114 + read-write + + + EVENTS_STOPPED + The ADC has stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 8 + 0x008 + EVENTS_CH[%s] + Peripheral events. + SAADC_EVENTS_CH + read-write + 0x118 + + LIMITH + Description cluster: Last results is equal or above CH[n].LIMIT.HIGH + 0x000 + read-write + + + LIMITH + Last results is equal or above CH[n].LIMIT.HIGH + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + LIMITL + Description cluster: Last results is equal or below CH[n].LIMIT.LOW + 0x004 + read-write + + + LIMITL + Last results is equal or below CH[n].LIMIT.LOW + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STARTED + Enable or disable interrupt for event STARTED + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + END + Enable or disable interrupt for event END + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + DONE + Enable or disable interrupt for event DONE + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RESULTDONE + Enable or disable interrupt for event RESULTDONE + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CALIBRATEDONE + Enable or disable interrupt for event CALIBRATEDONE + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + STOPPED + Enable or disable interrupt for event STOPPED + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH0LIMITH + Enable or disable interrupt for event CH0LIMITH + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH0LIMITL + Enable or disable interrupt for event CH0LIMITL + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH1LIMITH + Enable or disable interrupt for event CH1LIMITH + 8 + 8 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH1LIMITL + Enable or disable interrupt for event CH1LIMITL + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH2LIMITH + Enable or disable interrupt for event CH2LIMITH + 10 + 10 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH2LIMITL + Enable or disable interrupt for event CH2LIMITL + 11 + 11 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH3LIMITH + Enable or disable interrupt for event CH3LIMITH + 12 + 12 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH3LIMITL + Enable or disable interrupt for event CH3LIMITL + 13 + 13 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH4LIMITH + Enable or disable interrupt for event CH4LIMITH + 14 + 14 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH4LIMITL + Enable or disable interrupt for event CH4LIMITL + 15 + 15 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH5LIMITH + Enable or disable interrupt for event CH5LIMITH + 16 + 16 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH5LIMITL + Enable or disable interrupt for event CH5LIMITL + 17 + 17 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH6LIMITH + Enable or disable interrupt for event CH6LIMITH + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH6LIMITL + Enable or disable interrupt for event CH6LIMITL + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH7LIMITH + Enable or disable interrupt for event CH7LIMITH + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH7LIMITL + Enable or disable interrupt for event CH7LIMITL + 21 + 21 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STARTED + Write '1' to enable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + END + Write '1' to enable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DONE + Write '1' to enable interrupt for event DONE + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RESULTDONE + Write '1' to enable interrupt for event RESULTDONE + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CALIBRATEDONE + Write '1' to enable interrupt for event CALIBRATEDONE + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH0LIMITH + Write '1' to enable interrupt for event CH0LIMITH + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH0LIMITL + Write '1' to enable interrupt for event CH0LIMITL + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH1LIMITH + Write '1' to enable interrupt for event CH1LIMITH + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH1LIMITL + Write '1' to enable interrupt for event CH1LIMITL + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH2LIMITH + Write '1' to enable interrupt for event CH2LIMITH + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH2LIMITL + Write '1' to enable interrupt for event CH2LIMITL + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH3LIMITH + Write '1' to enable interrupt for event CH3LIMITH + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH3LIMITL + Write '1' to enable interrupt for event CH3LIMITL + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH4LIMITH + Write '1' to enable interrupt for event CH4LIMITH + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH4LIMITL + Write '1' to enable interrupt for event CH4LIMITL + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH5LIMITH + Write '1' to enable interrupt for event CH5LIMITH + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH5LIMITL + Write '1' to enable interrupt for event CH5LIMITL + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH6LIMITH + Write '1' to enable interrupt for event CH6LIMITH + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH6LIMITL + Write '1' to enable interrupt for event CH6LIMITL + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH7LIMITH + Write '1' to enable interrupt for event CH7LIMITH + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH7LIMITL + Write '1' to enable interrupt for event CH7LIMITL + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STARTED + Write '1' to disable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + END + Write '1' to disable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DONE + Write '1' to disable interrupt for event DONE + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RESULTDONE + Write '1' to disable interrupt for event RESULTDONE + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CALIBRATEDONE + Write '1' to disable interrupt for event CALIBRATEDONE + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH0LIMITH + Write '1' to disable interrupt for event CH0LIMITH + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH0LIMITL + Write '1' to disable interrupt for event CH0LIMITL + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH1LIMITH + Write '1' to disable interrupt for event CH1LIMITH + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH1LIMITL + Write '1' to disable interrupt for event CH1LIMITL + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH2LIMITH + Write '1' to disable interrupt for event CH2LIMITH + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH2LIMITL + Write '1' to disable interrupt for event CH2LIMITL + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH3LIMITH + Write '1' to disable interrupt for event CH3LIMITH + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH3LIMITL + Write '1' to disable interrupt for event CH3LIMITL + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH4LIMITH + Write '1' to disable interrupt for event CH4LIMITH + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH4LIMITL + Write '1' to disable interrupt for event CH4LIMITL + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH5LIMITH + Write '1' to disable interrupt for event CH5LIMITH + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH5LIMITL + Write '1' to disable interrupt for event CH5LIMITL + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH6LIMITH + Write '1' to disable interrupt for event CH6LIMITH + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH6LIMITL + Write '1' to disable interrupt for event CH6LIMITL + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH7LIMITH + Write '1' to disable interrupt for event CH7LIMITH + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH7LIMITL + Write '1' to disable interrupt for event CH7LIMITL + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + STATUS + Status + 0x400 + read-only + + + STATUS + Status + 0 + 0 + + + Ready + ADC is ready. No on-going conversion. + 0 + + + Busy + ADC is busy. Conversion in progress. + 1 + + + + + + + ENABLE + Enable or disable ADC + 0x500 + read-write + + + ENABLE + Enable or disable ADC + 0 + 0 + + + Disabled + Disable ADC + 0 + + + Enabled + Enable ADC + 1 + + + + + + + 8 + 0x010 + CH[%s] + Unspecified + SAADC_CH + read-write + 0x510 + + PSELP + Description cluster: Input positive pin selection for CH[n] + 0x000 + read-write + 0x00000000 + + + PSELP + Analog positive input channel + 0 + 4 + + + NC + Not connected + 0 + + + AnalogInput0 + AIN0 + 1 + + + AnalogInput1 + AIN1 + 2 + + + AnalogInput2 + AIN2 + 3 + + + AnalogInput3 + AIN3 + 4 + + + AnalogInput4 + AIN4 + 5 + + + AnalogInput5 + AIN5 + 6 + + + AnalogInput6 + AIN6 + 7 + + + AnalogInput7 + AIN7 + 8 + + + VDD + VDD + 9 + + + + + + + PSELN + Description cluster: Input negative pin selection for CH[n] + 0x004 + read-write + 0x00000000 + + + PSELN + Analog negative input, enables differential channel + 0 + 4 + + + NC + Not connected + 0 + + + AnalogInput0 + AIN0 + 1 + + + AnalogInput1 + AIN1 + 2 + + + AnalogInput2 + AIN2 + 3 + + + AnalogInput3 + AIN3 + 4 + + + AnalogInput4 + AIN4 + 5 + + + AnalogInput5 + AIN5 + 6 + + + AnalogInput6 + AIN6 + 7 + + + AnalogInput7 + AIN7 + 8 + + + VDD + VDD + 9 + + + + + + + CONFIG + Description cluster: Input configuration for CH[n] + 0x008 + read-write + 0x00020000 + + + RESP + Positive channel resistor control + 0 + 1 + + + Bypass + Bypass resistor ladder + 0 + + + Pulldown + Pull-down to GND + 1 + + + Pullup + Pull-up to VDD + 2 + + + VDD1_2 + Set input at VDD/2 + 3 + + + + + RESN + Negative channel resistor control + 4 + 5 + + + Bypass + Bypass resistor ladder + 0 + + + Pulldown + Pull-down to GND + 1 + + + Pullup + Pull-up to VDD + 2 + + + VDD1_2 + Set input at VDD/2 + 3 + + + + + GAIN + Gain control + 8 + 10 + + + Gain1_6 + 1/6 + 0 + + + Gain1_5 + 1/5 + 1 + + + Gain1_4 + 1/4 + 2 + + + Gain1_3 + 1/3 + 3 + + + Gain1_2 + 1/2 + 4 + + + Gain1 + 1 + 5 + + + Gain2 + 2 + 6 + + + Gain4 + 4 + 7 + + + + + REFSEL + Reference control + 12 + 12 + + + Internal + Internal reference (0.6 V) + 0 + + + VDD1_4 + VDD/4 as reference + 1 + + + + + TACQ + Acquisition time, the time the ADC uses to sample the input voltage + 16 + 18 + + + 3us + 3 us + 0 + + + 5us + 5 us + 1 + + + 10us + 10 us + 2 + + + 15us + 15 us + 3 + + + 20us + 20 us + 4 + + + 40us + 40 us + 5 + + + + + MODE + Enable differential mode + 20 + 20 + + + SE + Single ended, PSELN will be ignored, negative input to ADC shorted to GND + 0 + + + Diff + Differential + 1 + + + + + BURST + Enable burst mode + 24 + 24 + + + Disabled + Burst mode is disabled (normal operation) + 0 + + + Enabled + Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. + 1 + + + + + + + LIMIT + Description cluster: High/low limits for event monitoring a channel + 0x00C + read-write + 0x7FFF8000 + + + LOW + Low level limit + 0 + 15 + + + HIGH + High level limit + 16 + 31 + + + + + + RESOLUTION + Resolution configuration + 0x5F0 + read-write + 0x00000001 + + + VAL + Set the resolution + 0 + 2 + + + 8bit + 8 bit + 0 + + + 10bit + 10 bit + 1 + + + 12bit + 12 bit + 2 + + + 14bit + 14 bit + 3 + + + + + + + OVERSAMPLE + Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. + 0x5F4 + read-write + + + OVERSAMPLE + Oversample control + 0 + 3 + + + Bypass + Bypass oversampling + 0 + + + Over2x + Oversample 2x + 1 + + + Over4x + Oversample 4x + 2 + + + Over8x + Oversample 8x + 3 + + + Over16x + Oversample 16x + 4 + + + Over32x + Oversample 32x + 5 + + + Over64x + Oversample 64x + 6 + + + Over128x + Oversample 128x + 7 + + + Over256x + Oversample 256x + 8 + + + + + + + SAMPLERATE + Controls normal or continuous sample rate + 0x5F8 + read-write + + + CC + Capture and compare value. Sample rate is 16 MHz/CC + 0 + 10 + + + MODE + Select mode for sample rate control + 12 + 12 + + + Task + Rate is controlled from SAMPLE task + 0 + + + Timers + Rate is controlled from local timer (use CC to control the rate) + 1 + + + + + + + RESULT + RESULT EasyDMA channel + SAADC_RESULT + read-write + 0x62C + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of buffer words to transfer + 0x004 + read-write + + + MAXCNT + Maximum number of buffer words to transfer + 0 + 14 + + + + + AMOUNT + Number of buffer words transferred since last START + 0x008 + read-only + + + AMOUNT + Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. + 0 + 14 + + + + + + + + TIMER0 + Timer/Counter 0 + 0x40008000 + TIMER + + 0 + 0x1000 + registers + + + TIMER0 + 8 + + TIMER + 0x20 + + + TASKS_START + Start Timer + 0x000 + write-only + + + TASKS_START + Start Timer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop Timer + 0x004 + write-only + + + TASKS_STOP + Stop Timer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_COUNT + Increment Timer (Counter mode only) + 0x008 + write-only + + + TASKS_COUNT + Increment Timer (Counter mode only) + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CLEAR + Clear time + 0x00C + write-only + + + TASKS_CLEAR + Clear time + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SHUTDOWN + Deprecated register - Shut down timer + 0x010 + write-only + + + TASKS_SHUTDOWN + Deprecated field - Shut down timer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x6 + 0x4 + TASKS_CAPTURE[%s] + Description collection: Capture Timer value to CC[n] register + 0x040 + write-only + + + TASKS_CAPTURE + Capture Timer value to CC[n] register + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x6 + 0x4 + EVENTS_COMPARE[%s] + Description collection: Compare event on CC[n] match + 0x140 + read-write + + + EVENTS_COMPARE + Compare event on CC[n] match + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + COMPARE0_CLEAR + Shortcut between event COMPARE[0] and task CLEAR + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE1_CLEAR + Shortcut between event COMPARE[1] and task CLEAR + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE2_CLEAR + Shortcut between event COMPARE[2] and task CLEAR + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE3_CLEAR + Shortcut between event COMPARE[3] and task CLEAR + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE4_CLEAR + Shortcut between event COMPARE[4] and task CLEAR + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE5_CLEAR + Shortcut between event COMPARE[5] and task CLEAR + 5 + 5 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE0_STOP + Shortcut between event COMPARE[0] and task STOP + 8 + 8 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE1_STOP + Shortcut between event COMPARE[1] and task STOP + 9 + 9 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE2_STOP + Shortcut between event COMPARE[2] and task STOP + 10 + 10 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE3_STOP + Shortcut between event COMPARE[3] and task STOP + 11 + 11 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE4_STOP + Shortcut between event COMPARE[4] and task STOP + 12 + 12 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE5_STOP + Shortcut between event COMPARE[5] and task STOP + 13 + 13 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + MODE + Timer mode selection + 0x504 + read-write + + + MODE + Timer mode + 0 + 1 + + + Timer + Select Timer mode + 0 + + + Counter + Deprecated enumerator - Select Counter mode + 1 + + + LowPowerCounter + Select Low Power Counter mode + 2 + + + + + + + BITMODE + Configure the number of bits used by the TIMER + 0x508 + read-write + + + BITMODE + Timer bit width + 0 + 1 + + + 16Bit + 16 bit timer bit width + 0 + + + 08Bit + 8 bit timer bit width + 1 + + + 24Bit + 24 bit timer bit width + 2 + + + 32Bit + 32 bit timer bit width + 3 + + + + + + + PRESCALER + Timer prescaler register + 0x510 + read-write + 0x00000004 + + + PRESCALER + Prescaler value + 0 + 3 + + + + + 0x6 + 0x4 + CC[%s] + Description collection: Capture/Compare register n + 0x540 + read-write + + + CC + Capture/Compare value + 0 + 31 + + + + + + + TIMER1 + Timer/Counter 1 + 0x40009000 + + TIMER1 + 9 + + + + TIMER2 + Timer/Counter 2 + 0x4000A000 + + TIMER2 + 10 + + + + RTC0 + Real time counter 0 + 0x4000B000 + RTC + + 0 + 0x1000 + registers + + + RTC0 + 11 + + RTC + 0x20 + + + TASKS_START + Start RTC COUNTER + 0x000 + write-only + + + TASKS_START + Start RTC COUNTER + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop RTC COUNTER + 0x004 + write-only + + + TASKS_STOP + Stop RTC COUNTER + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CLEAR + Clear RTC COUNTER + 0x008 + write-only + + + TASKS_CLEAR + Clear RTC COUNTER + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_TRIGOVRFLW + Set COUNTER to 0xFFFFF0 + 0x00C + write-only + + + TASKS_TRIGOVRFLW + Set COUNTER to 0xFFFFF0 + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_TICK + Event on COUNTER increment + 0x100 + read-write + + + EVENTS_TICK + Event on COUNTER increment + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_OVRFLW + Event on COUNTER overflow + 0x104 + read-write + + + EVENTS_OVRFLW + Event on COUNTER overflow + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x4 + 0x4 + EVENTS_COMPARE[%s] + Description collection: Compare event on CC[n] match + 0x140 + read-write + + + EVENTS_COMPARE + Compare event on CC[n] match + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + TICK + Write '1' to enable interrupt for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + OVRFLW + Write '1' to enable interrupt for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + TICK + Write '1' to disable interrupt for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + OVRFLW + Write '1' to disable interrupt for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + EVTEN + Enable or disable event routing + 0x340 + read-write + + + TICK + Enable or disable event routing for event TICK + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Disable + 1 + + + + + OVRFLW + Enable or disable event routing for event OVRFLW + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Disable + 1 + + + + + COMPARE0 + Enable or disable event routing for event COMPARE[0] + 16 + 16 + + + Disabled + Disable + 0 + + + Enabled + Disable + 1 + + + + + COMPARE1 + Enable or disable event routing for event COMPARE[1] + 17 + 17 + + + Disabled + Disable + 0 + + + Enabled + Disable + 1 + + + + + COMPARE2 + Enable or disable event routing for event COMPARE[2] + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Disable + 1 + + + + + COMPARE3 + Enable or disable event routing for event COMPARE[3] + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Disable + 1 + + + + + + + EVTENSET + Enable event routing + 0x344 + read-write + + + TICK + Write '1' to enable event routing for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + OVRFLW + Write '1' to enable event routing for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE0 + Write '1' to enable event routing for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE1 + Write '1' to enable event routing for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE2 + Write '1' to enable event routing for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE3 + Write '1' to enable event routing for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + EVTENCLR + Disable event routing + 0x348 + read-write + + + TICK + Write '1' to disable event routing for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + OVRFLW + Write '1' to disable event routing for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE0 + Write '1' to disable event routing for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE1 + Write '1' to disable event routing for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE2 + Write '1' to disable event routing for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE3 + Write '1' to disable event routing for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + COUNTER + Current COUNTER value + 0x504 + read-only + + + COUNTER + Counter value + 0 + 23 + + + + + PRESCALER + 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped + 0x508 + read-write + + + PRESCALER + Prescaler value + 0 + 11 + + + + + 0x4 + 0x4 + CC[%s] + Description collection: Compare register n + 0x540 + read-write + + + COMPARE + Compare value + 0 + 23 + + + + + + + TEMP + Temperature Sensor + 0x4000C000 + + 0 + 0x1000 + registers + + + TEMP + 12 + + TEMP + 0x20 + + + TASKS_START + Start temperature measurement + 0x000 + write-only + + + TASKS_START + Start temperature measurement + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop temperature measurement + 0x004 + write-only + + + TASKS_STOP + Stop temperature measurement + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_DATARDY + Temperature measurement complete, data ready + 0x100 + read-write + + + EVENTS_DATARDY + Temperature measurement complete, data ready + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + DATARDY + Write '1' to enable interrupt for event DATARDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + DATARDY + Write '1' to disable interrupt for event DATARDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + TEMP + Temperature in degC (0.25deg steps) + 0x508 + read-only + int32_t + + + TEMP + Temperature in degC (0.25deg steps) + 0 + 31 + + + + + A0 + Slope of 1st piece wise linear function + 0x520 + read-write + 0x00000326 + + + A0 + Slope of 1st piece wise linear function + 0 + 11 + + + + + A1 + Slope of 2nd piece wise linear function + 0x524 + read-write + 0x00000348 + + + A1 + Slope of 2nd piece wise linear function + 0 + 11 + + + + + A2 + Slope of 3rd piece wise linear function + 0x528 + read-write + 0x000003AA + + + A2 + Slope of 3rd piece wise linear function + 0 + 11 + + + + + A3 + Slope of 4th piece wise linear function + 0x52C + read-write + 0x0000040E + + + A3 + Slope of 4th piece wise linear function + 0 + 11 + + + + + A4 + Slope of 5th piece wise linear function + 0x530 + read-write + 0x000004BD + + + A4 + Slope of 5th piece wise linear function + 0 + 11 + + + + + A5 + Slope of 6th piece wise linear function + 0x534 + read-write + 0x000005A3 + + + A5 + Slope of 6th piece wise linear function + 0 + 11 + + + + + B0 + y-intercept of 1st piece wise linear function + 0x540 + read-write + 0x00003FEF + + + B0 + y-intercept of 1st piece wise linear function + 0 + 13 + + + + + B1 + y-intercept of 2nd piece wise linear function + 0x544 + read-write + 0x00003FBE + + + B1 + y-intercept of 2nd piece wise linear function + 0 + 13 + + + + + B2 + y-intercept of 3rd piece wise linear function + 0x548 + read-write + 0x00003FBE + + + B2 + y-intercept of 3rd piece wise linear function + 0 + 13 + + + + + B3 + y-intercept of 4th piece wise linear function + 0x54C + read-write + 0x00000012 + + + B3 + y-intercept of 4th piece wise linear function + 0 + 13 + + + + + B4 + y-intercept of 5th piece wise linear function + 0x550 + read-write + 0x00000124 + + + B4 + y-intercept of 5th piece wise linear function + 0 + 13 + + + + + B5 + y-intercept of 6th piece wise linear function + 0x554 + read-write + 0x0000027C + + + B5 + y-intercept of 6th piece wise linear function + 0 + 13 + + + + + T0 + End point of 1st piece wise linear function + 0x560 + read-write + 0x000000E2 + + + T0 + End point of 1st piece wise linear function + 0 + 7 + + + + + T1 + End point of 2nd piece wise linear function + 0x564 + read-write + 0x00000000 + + + T1 + End point of 2nd piece wise linear function + 0 + 7 + + + + + T2 + End point of 3rd piece wise linear function + 0x568 + read-write + 0x00000019 + + + T2 + End point of 3rd piece wise linear function + 0 + 7 + + + + + T3 + End point of 4th piece wise linear function + 0x56C + read-write + 0x0000003C + + + T3 + End point of 4th piece wise linear function + 0 + 7 + + + + + T4 + End point of 5th piece wise linear function + 0x570 + read-write + 0x00000050 + + + T4 + End point of 5th piece wise linear function + 0 + 7 + + + + + + + RNG + Random Number Generator + 0x4000D000 + + 0 + 0x1000 + registers + + + RNG + 13 + + RNG + 0x20 + + + TASKS_START + Task starting the random number generator + 0x000 + write-only + + + TASKS_START + Task starting the random number generator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Task stopping the random number generator + 0x004 + write-only + + + TASKS_STOP + Task stopping the random number generator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_VALRDY + Event being generated for every new random number written to the VALUE register + 0x100 + read-write + + + EVENTS_VALRDY + Event being generated for every new random number written to the VALUE register + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + VALRDY_STOP + Shortcut between event VALRDY and task STOP + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + VALRDY + Write '1' to enable interrupt for event VALRDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + VALRDY + Write '1' to disable interrupt for event VALRDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + CONFIG + Configuration register + 0x504 + read-write + + + DERCEN + Bias correction + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + + + VALUE + Output random number + 0x508 + read-only + + + VALUE + Generated random number + 0 + 7 + + + + + + + ECB + AES ECB Mode Encryption + 0x4000E000 + + 0 + 0x1000 + registers + + + ECB + 14 + + ECB + 0x20 + + + TASKS_STARTECB + Start ECB block encrypt + 0x000 + write-only + + + TASKS_STARTECB + Start ECB block encrypt + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOPECB + Abort a possible executing ECB operation + 0x004 + write-only + + + TASKS_STOPECB + Abort a possible executing ECB operation + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_ENDECB + ECB block encrypt complete + 0x100 + read-write + + + EVENTS_ENDECB + ECB block encrypt complete + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERRORECB + ECB block encrypt aborted because of a STOPECB task or due to an error + 0x104 + read-write + + + EVENTS_ERRORECB + ECB block encrypt aborted because of a STOPECB task or due to an error + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + ENDECB + Write '1' to enable interrupt for event ENDECB + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERRORECB + Write '1' to enable interrupt for event ERRORECB + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + ENDECB + Write '1' to disable interrupt for event ENDECB + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERRORECB + Write '1' to disable interrupt for event ERRORECB + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ECBDATAPTR + ECB block encrypt memory pointers + 0x504 + read-write + + + ECBDATAPTR + Pointer to the ECB data structure (see Table 1 ECB data structure overview) + 0 + 31 + + + + + + + AAR + Accelerated Address Resolver + 0x4000F000 + + 0 + 0x1000 + registers + + + CCM_AAR + 15 + + AAR + 0x20 + + + TASKS_START + Start resolving addresses based on IRKs specified in the IRK data structure + 0x000 + write-only + + + TASKS_START + Start resolving addresses based on IRKs specified in the IRK data structure + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop resolving addresses + 0x008 + write-only + + + TASKS_STOP + Stop resolving addresses + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_END + Address resolution procedure complete + 0x100 + read-write + + + EVENTS_END + Address resolution procedure complete + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RESOLVED + Address resolved + 0x104 + read-write + + + EVENTS_RESOLVED + Address resolved + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_NOTRESOLVED + Address not resolved + 0x108 + read-write + + + EVENTS_NOTRESOLVED + Address not resolved + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + END + Write '1' to enable interrupt for event END + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RESOLVED + Write '1' to enable interrupt for event RESOLVED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + NOTRESOLVED + Write '1' to enable interrupt for event NOTRESOLVED + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + END + Write '1' to disable interrupt for event END + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RESOLVED + Write '1' to disable interrupt for event RESOLVED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + NOTRESOLVED + Write '1' to disable interrupt for event NOTRESOLVED + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + STATUS + Resolution status + 0x400 + read-only + + + STATUS + The IRK that was used last time an address was resolved + 0 + 3 + + + + + ENABLE + Enable AAR + 0x500 + read-write + + + ENABLE + Enable or disable AAR + 0 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 3 + + + + + + + NIRK + Number of IRKs + 0x504 + read-write + 0x00000001 + + + NIRK + Number of Identity root keys available in the IRK data structure + 0 + 4 + + + + + IRKPTR + Pointer to IRK data structure + 0x508 + read-write + + + IRKPTR + Pointer to the IRK data structure + 0 + 31 + + + + + ADDRPTR + Pointer to the resolvable address + 0x510 + read-write + + + ADDRPTR + Pointer to the resolvable address (6-bytes) + 0 + 31 + + + + + SCRATCHPTR + Pointer to data area used for temporary storage + 0x514 + read-write + + + SCRATCHPTR + Pointer to a scratch data area used for temporary storage during resolution. A space of minimum 3 bytes must be reserved. + 0 + 31 + + + + + + + CCM + AES CCM mode encryption + 0x4000F000 + AAR + + 0 + 0x1000 + registers + + + CCM_AAR + 15 + + CCM + 0x20 + + + TASKS_KSGEN + Start generation of keystream. This operation will stop by itself when completed. + 0x000 + write-only + + + TASKS_KSGEN + Start generation of keystream. This operation will stop by itself when completed. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CRYPT + Start encryption/decryption. This operation will stop by itself when completed. + 0x004 + write-only + + + TASKS_CRYPT + Start encryption/decryption. This operation will stop by itself when completed. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop encryption/decryption + 0x008 + write-only + + + TASKS_STOP + Stop encryption/decryption + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RATEOVERRIDE + Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption + 0x00C + write-only + + + TASKS_RATEOVERRIDE + Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_ENDKSGEN + Keystream generation complete + 0x100 + read-write + + + EVENTS_ENDKSGEN + Keystream generation complete + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDCRYPT + Encrypt/decrypt complete + 0x104 + read-write + + + EVENTS_ENDCRYPT + Encrypt/decrypt complete + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + Deprecated register - CCM error event + 0x108 + read-write + + + EVENTS_ERROR + Deprecated field - CCM error event + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + ENDKSGEN_CRYPT + Shortcut between event ENDKSGEN and task CRYPT + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + ENDKSGEN + Write '1' to enable interrupt for event ENDKSGEN + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDCRYPT + Write '1' to enable interrupt for event ENDCRYPT + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Deprecated intsetfield - Write '1' to enable interrupt for event ERROR + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + ENDKSGEN + Write '1' to disable interrupt for event ENDKSGEN + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDCRYPT + Write '1' to disable interrupt for event ENDCRYPT + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Deprecated intclrfield - Write '1' to disable interrupt for event ERROR + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + MICSTATUS + MIC check result + 0x400 + read-only + + + MICSTATUS + The result of the MIC check performed during the previous decryption operation + 0 + 0 + + + CheckFailed + MIC check failed + 0 + + + CheckPassed + MIC check passed + 1 + + + + + + + ENABLE + Enable + 0x500 + read-write + + + ENABLE + Enable or disable CCM + 0 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 2 + + + + + + + MODE + Operation mode + 0x504 + read-write + 0x00000001 + + + MODE + The mode of operation to be used. Settings in this register apply whenever either the KSGEN task or the CRYPT task is triggered. + 0 + 0 + + + Encryption + AES CCM packet encryption mode + 0 + + + Decryption + AES CCM packet decryption mode + 1 + + + + + DATARATE + Radio data rate that the CCM shall run synchronous with + 16 + 17 + + + 1Mbit + 1 Mbps + 0 + + + 2Mbit + 2 Mbps + 1 + + + 125Kbps + 125 kbps + 2 + + + 500Kbps + 500 kbps + 3 + + + + + LENGTH + Packet length configuration + 24 + 24 + + + Default + Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A keystream for packet payloads up to 27 bytes will be generated. + 0 + + + Extended + Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A keystream for packet payloads up to MAXPACKETSIZE bytes will be generated. + 1 + + + + + + + CNFPTR + Pointer to data structure holding the AES key and the NONCE vector + 0x508 + read-write + + + CNFPTR + Pointer to the data structure holding the AES key and the CCM NONCE vector (see table CCM data structure overview) + 0 + 31 + + + + + INPTR + Input pointer + 0x50C + read-write + + + INPTR + Input pointer + 0 + 31 + + + + + OUTPTR + Output pointer + 0x510 + read-write + + + OUTPTR + Output pointer + 0 + 31 + + + + + SCRATCHPTR + Pointer to data area used for temporary storage + 0x514 + read-write + + + SCRATCHPTR + Pointer to a scratch data area used for temporary storage during keystream generation, + MIC generation and encryption/decryption. + 0 + 31 + + + + + MAXPACKETSIZE + Length of keystream generated when MODE.LENGTH = Extended + 0x518 + read-write + 0x000000FB + + + MAXPACKETSIZE + Length of keystream generated when MODE.LENGTH = Extended. This value must be greater than or equal to the subsequent packet payload to be encrypted/decrypted. + 0 + 7 + + + + + RATEOVERRIDE + Data rate override setting. + 0x51C + read-write + 0x00000000 + + + RATEOVERRIDE + Data rate override setting + 0 + 1 + + + 1Mbit + 1 Mbps + 0 + + + 2Mbit + 2 Mbps + 1 + + + 125Kbps + 125 kbps + 2 + + + 500Kbps + 500 kbps + 3 + + + + + + + + + WDT + Watchdog Timer + 0x40010000 + + 0 + 0x1000 + registers + + + WDT + 16 + + WDT + 0x20 + + + TASKS_START + Start the watchdog + 0x000 + write-only + + + TASKS_START + Start the watchdog + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_TIMEOUT + Watchdog timeout + 0x100 + read-write + + + EVENTS_TIMEOUT + Watchdog timeout + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + TIMEOUT + Write '1' to enable interrupt for event TIMEOUT + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + TIMEOUT + Write '1' to disable interrupt for event TIMEOUT + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + RUNSTATUS + Run status + 0x400 + read-only + + + RUNSTATUS + Indicates whether or not the watchdog is running + 0 + 0 + + + NotRunning + Watchdog not running + 0 + + + Running + Watchdog is running + 1 + + + + + + + REQSTATUS + Request status + 0x404 + read-only + 0x00000001 + + + RR0 + Request status for RR[0] register + 0 + 0 + + + DisabledOrRequested + RR[0] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[0] register is enabled, and are not yet requesting reload + 1 + + + + + RR1 + Request status for RR[1] register + 1 + 1 + + + DisabledOrRequested + RR[1] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[1] register is enabled, and are not yet requesting reload + 1 + + + + + RR2 + Request status for RR[2] register + 2 + 2 + + + DisabledOrRequested + RR[2] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[2] register is enabled, and are not yet requesting reload + 1 + + + + + RR3 + Request status for RR[3] register + 3 + 3 + + + DisabledOrRequested + RR[3] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[3] register is enabled, and are not yet requesting reload + 1 + + + + + RR4 + Request status for RR[4] register + 4 + 4 + + + DisabledOrRequested + RR[4] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[4] register is enabled, and are not yet requesting reload + 1 + + + + + RR5 + Request status for RR[5] register + 5 + 5 + + + DisabledOrRequested + RR[5] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[5] register is enabled, and are not yet requesting reload + 1 + + + + + RR6 + Request status for RR[6] register + 6 + 6 + + + DisabledOrRequested + RR[6] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[6] register is enabled, and are not yet requesting reload + 1 + + + + + RR7 + Request status for RR[7] register + 7 + 7 + + + DisabledOrRequested + RR[7] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[7] register is enabled, and are not yet requesting reload + 1 + + + + + + + CRV + Counter reload value + 0x504 + read-write + 0xFFFFFFFF + + + CRV + Counter reload value in number of cycles of the 32.768 kHz clock + 0 + 31 + + + + + RREN + Enable register for reload request registers + 0x508 + read-write + 0x00000001 + + + RR0 + Enable or disable RR[0] register + 0 + 0 + + + Disabled + Disable RR[0] register + 0 + + + Enabled + Enable RR[0] register + 1 + + + + + RR1 + Enable or disable RR[1] register + 1 + 1 + + + Disabled + Disable RR[1] register + 0 + + + Enabled + Enable RR[1] register + 1 + + + + + RR2 + Enable or disable RR[2] register + 2 + 2 + + + Disabled + Disable RR[2] register + 0 + + + Enabled + Enable RR[2] register + 1 + + + + + RR3 + Enable or disable RR[3] register + 3 + 3 + + + Disabled + Disable RR[3] register + 0 + + + Enabled + Enable RR[3] register + 1 + + + + + RR4 + Enable or disable RR[4] register + 4 + 4 + + + Disabled + Disable RR[4] register + 0 + + + Enabled + Enable RR[4] register + 1 + + + + + RR5 + Enable or disable RR[5] register + 5 + 5 + + + Disabled + Disable RR[5] register + 0 + + + Enabled + Enable RR[5] register + 1 + + + + + RR6 + Enable or disable RR[6] register + 6 + 6 + + + Disabled + Disable RR[6] register + 0 + + + Enabled + Enable RR[6] register + 1 + + + + + RR7 + Enable or disable RR[7] register + 7 + 7 + + + Disabled + Disable RR[7] register + 0 + + + Enabled + Enable RR[7] register + 1 + + + + + + + CONFIG + Configuration register + 0x50C + read-write + 0x00000001 + + + SLEEP + Configure the watchdog to either be paused, or kept running, while the CPU is sleeping + 0 + 0 + + + Pause + Pause watchdog while the CPU is sleeping + 0 + + + Run + Keep the watchdog running while the CPU is sleeping + 1 + + + + + HALT + Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger + 3 + 3 + + + Pause + Pause watchdog while the CPU is halted by the debugger + 0 + + + Run + Keep the watchdog running while the CPU is halted by the debugger + 1 + + + + + + + 0x8 + 0x4 + RR[%s] + Description collection: Reload request n + 0x600 + write-only + + + RR + Reload request register + 0 + 31 + + + Reload + Value to request a reload of the watchdog timer + 0x6E524635 + + + + + + + + + RTC1 + Real time counter 1 + 0x40011000 + + RTC1 + 17 + + + + QDEC + Quadrature Decoder + 0x40012000 + + 0 + 0x1000 + registers + + + QDEC + 18 + + QDEC + 0x20 + + + TASKS_START + Task starting the quadrature decoder + 0x000 + write-only + + + TASKS_START + Task starting the quadrature decoder + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Task stopping the quadrature decoder + 0x004 + write-only + + + TASKS_STOP + Task stopping the quadrature decoder + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_READCLRACC + Read and clear ACC and ACCDBL + 0x008 + write-only + + + TASKS_READCLRACC + Read and clear ACC and ACCDBL + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RDCLRACC + Read and clear ACC + 0x00C + write-only + + + TASKS_RDCLRACC + Read and clear ACC + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RDCLRDBL + Read and clear ACCDBL + 0x010 + write-only + + + TASKS_RDCLRDBL + Read and clear ACCDBL + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_SAMPLERDY + Event being generated for every new sample value written to the SAMPLE register + 0x100 + read-write + + + EVENTS_SAMPLERDY + Event being generated for every new sample value written to the SAMPLE register + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_REPORTRDY + Non-null report ready + 0x104 + read-write + + + EVENTS_REPORTRDY + Non-null report ready + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ACCOF + ACC or ACCDBL register overflow + 0x108 + read-write + + + EVENTS_ACCOF + ACC or ACCDBL register overflow + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DBLRDY + Double displacement(s) detected + 0x10C + read-write + + + EVENTS_DBLRDY + Double displacement(s) detected + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STOPPED + QDEC has been stopped + 0x110 + read-write + + + EVENTS_STOPPED + QDEC has been stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + REPORTRDY_READCLRACC + Shortcut between event REPORTRDY and task READCLRACC + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + SAMPLERDY_STOP + Shortcut between event SAMPLERDY and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + REPORTRDY_RDCLRACC + Shortcut between event REPORTRDY and task RDCLRACC + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + REPORTRDY_STOP + Shortcut between event REPORTRDY and task STOP + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DBLRDY_RDCLRDBL + Shortcut between event DBLRDY and task RDCLRDBL + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DBLRDY_STOP + Shortcut between event DBLRDY and task STOP + 5 + 5 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + SAMPLERDY_READCLRACC + Shortcut between event SAMPLERDY and task READCLRACC + 6 + 6 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + SAMPLERDY + Write '1' to enable interrupt for event SAMPLERDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + REPORTRDY + Write '1' to enable interrupt for event REPORTRDY + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ACCOF + Write '1' to enable interrupt for event ACCOF + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DBLRDY + Write '1' to enable interrupt for event DBLRDY + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + SAMPLERDY + Write '1' to disable interrupt for event SAMPLERDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REPORTRDY + Write '1' to disable interrupt for event REPORTRDY + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ACCOF + Write '1' to disable interrupt for event ACCOF + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DBLRDY + Write '1' to disable interrupt for event DBLRDY + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + Enable the quadrature decoder + 0x500 + read-write + + + ENABLE + Enable or disable the quadrature decoder + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + LEDPOL + LED output pin polarity + 0x504 + read-write + + + LEDPOL + LED output pin polarity + 0 + 0 + + + ActiveLow + Led active on output pin low + 0 + + + ActiveHigh + Led active on output pin high + 1 + + + + + + + SAMPLEPER + Sample period + 0x508 + read-write + + + SAMPLEPER + Sample period. The SAMPLE register will be updated for every new sample + 0 + 3 + + + 128us + 128 us + 0 + + + 256us + 256 us + 1 + + + 512us + 512 us + 2 + + + 1024us + 1024 us + 3 + + + 2048us + 2048 us + 4 + + + 4096us + 4096 us + 5 + + + 8192us + 8192 us + 6 + + + 16384us + 16384 us + 7 + + + 32ms + 32768 us + 8 + + + 65ms + 65536 us + 9 + + + 131ms + 131072 us + 10 + + + + + + + SAMPLE + Motion sample value + 0x50C + read-only + int32_t + + + SAMPLE + Last motion sample + 0 + 31 + + + + + REPORTPER + Number of samples to be taken before REPORTRDY and DBLRDY events can be generated + 0x510 + read-write + + + REPORTPER + Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated + 0 + 3 + + + 10Smpl + 10 samples / report + 0 + + + 40Smpl + 40 samples / report + 1 + + + 80Smpl + 80 samples / report + 2 + + + 120Smpl + 120 samples / report + 3 + + + 160Smpl + 160 samples / report + 4 + + + 200Smpl + 200 samples / report + 5 + + + 240Smpl + 240 samples / report + 6 + + + 280Smpl + 280 samples / report + 7 + + + 1Smpl + 1 sample / report + 8 + + + + + + + ACC + Register accumulating the valid transitions + 0x514 + read-only + int32_t + + + ACC + Register accumulating all valid samples (not double transition) read from the SAMPLE register + 0 + 31 + + + + + ACCREAD + Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task + 0x518 + read-only + int32_t + + + ACCREAD + Snapshot of the ACC register. + 0 + 31 + + + + + PSEL + Unspecified + QDEC_PSEL + read-write + 0x51C + + LED + Pin select for LED signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + A + Pin select for A signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + B + Pin select for B signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + DBFEN + Enable input debounce filters + 0x528 + read-write + + + DBFEN + Enable input debounce filters + 0 + 0 + + + Disabled + Debounce input filters disabled + 0 + + + Enabled + Debounce input filters enabled + 1 + + + + + + + LEDPRE + Time period the LED is switched ON prior to sampling + 0x540 + read-write + 0x00000010 + + + LEDPRE + Period in us the LED is switched on prior to sampling + 0 + 8 + + + + + ACCDBL + Register accumulating the number of detected double transitions + 0x544 + read-only + + + ACCDBL + Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). + 0 + 3 + + + + + ACCDBLREAD + Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task + 0x548 + read-only + + + ACCDBLREAD + Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. + 0 + 3 + + + + + + + COMP + Comparator + 0x40013000 + + 0 + 0x1000 + registers + + + COMP + 19 + + COMP + 0x20 + + + TASKS_START + Start comparator + 0x000 + write-only + + + TASKS_START + Start comparator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop comparator + 0x004 + write-only + + + TASKS_STOP + Stop comparator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SAMPLE + Sample comparator value + 0x008 + write-only + + + TASKS_SAMPLE + Sample comparator value + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_READY + COMP is ready and output is valid + 0x100 + read-write + + + EVENTS_READY + COMP is ready and output is valid + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DOWN + Downward crossing + 0x104 + read-write + + + EVENTS_DOWN + Downward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_UP + Upward crossing + 0x108 + read-write + + + EVENTS_UP + Upward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CROSS + Downward or upward crossing + 0x10C + read-write + + + EVENTS_CROSS + Downward or upward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + READY_SAMPLE + Shortcut between event READY and task SAMPLE + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + READY_STOP + Shortcut between event READY and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DOWN_STOP + Shortcut between event DOWN and task STOP + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + UP_STOP + Shortcut between event UP and task STOP + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + CROSS_STOP + Shortcut between event CROSS and task STOP + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + READY + Enable or disable interrupt for event READY + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + DOWN + Enable or disable interrupt for event DOWN + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + UP + Enable or disable interrupt for event UP + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CROSS + Enable or disable interrupt for event CROSS + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + READY + Write '1' to enable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DOWN + Write '1' to enable interrupt for event DOWN + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + UP + Write '1' to enable interrupt for event UP + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CROSS + Write '1' to enable interrupt for event CROSS + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + READY + Write '1' to disable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DOWN + Write '1' to disable interrupt for event DOWN + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + UP + Write '1' to disable interrupt for event UP + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CROSS + Write '1' to disable interrupt for event CROSS + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + RESULT + Compare result + 0x400 + read-only + + + RESULT + Result of last compare. Decision point SAMPLE task. + 0 + 0 + + + Below + Input voltage is below the threshold (VIN+ &lt; VIN-) + 0 + + + Above + Input voltage is above the threshold (VIN+ &gt; VIN-) + 1 + + + + + + + ENABLE + COMP enable + 0x500 + read-write + + + ENABLE + Enable or disable COMP + 0 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 2 + + + + + + + PSEL + Pin select + 0x504 + read-write + + + PSEL + Analog pin select + 0 + 2 + + + AnalogInput0 + AIN0 selected as analog input + 0 + + + AnalogInput1 + AIN1 selected as analog input + 1 + + + AnalogInput2 + AIN2 selected as analog input + 2 + + + AnalogInput3 + AIN3 selected as analog input + 3 + + + AnalogInput4 + AIN4 selected as analog input + 4 + + + AnalogInput5 + AIN5 selected as analog input + 5 + + + AnalogInput6 + AIN6 selected as analog input + 6 + + + VddDiv2 + VDD/2 selected as analog input + 7 + + + + + + + REFSEL + Reference source select for single-ended mode + 0x508 + read-write + 0x00000004 + + + REFSEL + Reference select + 0 + 2 + + + Int1V2 + VREF = internal 1.2 V reference (VDD &gt;= 1.7 V) + 0 + + + Int1V8 + VREF = internal 1.8 V reference (VDD &gt;= VREF + 0.2 V) + 1 + + + Int2V4 + VREF = internal 2.4 V reference (VDD &gt;= VREF + 0.2 V) + 2 + + + VDD + VREF = VDD + 4 + + + ARef + VREF = AREF (VDD &gt;= VREF &gt;= AREFMIN) + 5 + + + + + + + EXTREFSEL + External reference select + 0x50C + read-write + + + EXTREFSEL + External analog reference select + 0 + 2 + + + AnalogReference0 + Use AIN0 as external analog reference + 0 + + + AnalogReference1 + Use AIN1 as external analog reference + 1 + + + AnalogReference2 + Use AIN2 as external analog reference + 2 + + + AnalogReference3 + Use AIN3 as external analog reference + 3 + + + AnalogReference4 + Use AIN4 as external analog reference + 4 + + + AnalogReference5 + Use AIN5 as external analog reference + 5 + + + AnalogReference6 + Use AIN6 as external analog reference + 6 + + + AnalogReference7 + Use AIN7 as external analog reference + 7 + + + + + + + TH + Threshold configuration for hysteresis unit + 0x530 + read-write + 0x00000000 + + + THDOWN + VDOWN = (THDOWN+1)/64*VREF + 0 + 5 + + + THUP + VUP = (THUP+1)/64*VREF + 8 + 13 + + + + + MODE + Mode configuration + 0x534 + read-write + + + SP + Speed and power modes + 0 + 1 + + + Low + Low-power mode + 0 + + + Normal + Normal mode + 1 + + + High + High-speed mode + 2 + + + + + MAIN + Main operation modes + 8 + 8 + + + SE + Single-ended mode + 0 + + + Diff + Differential mode + 1 + + + + + + + HYST + Comparator hysteresis enable + 0x538 + read-write + + + HYST + Comparator hysteresis + 0 + 0 + + + NoHyst + Comparator hysteresis disabled + 0 + + + Hyst50mV + Comparator hysteresis enabled + 1 + + + + + + + + + EGU0 + Event generator unit 0 + 0x40014000 + EGU + + 0 + 0x1000 + registers + + + SWI0_EGU0 + 20 + + EGU + 0x20 + + + 0x10 + 0x4 + TASKS_TRIGGER[%s] + Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event + 0x000 + write-only + + + TASKS_TRIGGER + Trigger n for triggering the corresponding TRIGGERED[n] event + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x10 + 0x4 + EVENTS_TRIGGERED[%s] + Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task + 0x100 + read-write + + + EVENTS_TRIGGERED + Event number n generated by triggering the corresponding TRIGGER[n] task + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + TRIGGERED0 + Enable or disable interrupt for event TRIGGERED[0] + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED1 + Enable or disable interrupt for event TRIGGERED[1] + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED2 + Enable or disable interrupt for event TRIGGERED[2] + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED3 + Enable or disable interrupt for event TRIGGERED[3] + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED4 + Enable or disable interrupt for event TRIGGERED[4] + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED5 + Enable or disable interrupt for event TRIGGERED[5] + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED6 + Enable or disable interrupt for event TRIGGERED[6] + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED7 + Enable or disable interrupt for event TRIGGERED[7] + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED8 + Enable or disable interrupt for event TRIGGERED[8] + 8 + 8 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED9 + Enable or disable interrupt for event TRIGGERED[9] + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED10 + Enable or disable interrupt for event TRIGGERED[10] + 10 + 10 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED11 + Enable or disable interrupt for event TRIGGERED[11] + 11 + 11 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED12 + Enable or disable interrupt for event TRIGGERED[12] + 12 + 12 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED13 + Enable or disable interrupt for event TRIGGERED[13] + 13 + 13 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED14 + Enable or disable interrupt for event TRIGGERED[14] + 14 + 14 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED15 + Enable or disable interrupt for event TRIGGERED[15] + 15 + 15 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + TRIGGERED0 + Write '1' to enable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED1 + Write '1' to enable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED2 + Write '1' to enable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED3 + Write '1' to enable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED4 + Write '1' to enable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED5 + Write '1' to enable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED6 + Write '1' to enable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED7 + Write '1' to enable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED8 + Write '1' to enable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED9 + Write '1' to enable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED10 + Write '1' to enable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED11 + Write '1' to enable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED12 + Write '1' to enable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED13 + Write '1' to enable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED14 + Write '1' to enable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED15 + Write '1' to enable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + TRIGGERED0 + Write '1' to disable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED1 + Write '1' to disable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED2 + Write '1' to disable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED3 + Write '1' to disable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED4 + Write '1' to disable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED5 + Write '1' to disable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED6 + Write '1' to disable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED7 + Write '1' to disable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED8 + Write '1' to disable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED9 + Write '1' to disable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED10 + Write '1' to disable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED11 + Write '1' to disable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED12 + Write '1' to disable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED13 + Write '1' to disable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED14 + Write '1' to disable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED15 + Write '1' to disable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + + + SWI0 + Software interrupt 0 + 0x40014000 + EGU0 + SWI + + 0 + 0x1000 + registers + + + SWI0_EGU0 + 20 + + SWI + 0x20 + + + UNUSED + Unused. + 0x000 + 0x00000000 + read-only + + + + + EGU1 + Event generator unit 1 + 0x40015000 + + SWI1_EGU1 + 21 + + + + SWI1 + Software interrupt 1 + 0x40015000 + EGU1 + + SWI1_EGU1 + 21 + + + + SWI2 + Software interrupt 2 + 0x40016000 + + SWI2 + 22 + + + + SWI3 + Software interrupt 3 + 0x40017000 + + SWI3 + 23 + + + + SWI4 + Software interrupt 4 + 0x40018000 + + SWI4 + 24 + + + + SWI5 + Software interrupt 5 + 0x40019000 + + SWI5 + 25 + + + + PWM0 + Pulse width modulation unit + 0x4001C000 + PWM + + 0 + 0x1000 + registers + + + PWM0 + 28 + + PWM + 0x20 + + + TASKS_STOP + Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback + 0x004 + write-only + + + TASKS_STOP + Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x2 + 0x4 + TASKS_SEQSTART[%s] + Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. + 0x008 + write-only + + + TASKS_SEQSTART + Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_NEXTSTEP + Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. + 0x010 + write-only + + + TASKS_NEXTSTEP + Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_STOPPED + Response to STOP task, emitted when PWM pulses are no longer generated + 0x104 + read-write + + + EVENTS_STOPPED + Response to STOP task, emitted when PWM pulses are no longer generated + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x2 + 0x4 + EVENTS_SEQSTARTED[%s] + Description collection: First PWM period started on sequence n + 0x108 + read-write + + + EVENTS_SEQSTARTED + First PWM period started on sequence n + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x2 + 0x4 + EVENTS_SEQEND[%s] + Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter + 0x110 + read-write + + + EVENTS_SEQEND + Emitted at end of every sequence n, when last value from RAM has been applied to wave counter + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_PWMPERIODEND + Emitted at the end of each PWM period + 0x118 + read-write + + + EVENTS_PWMPERIODEND + Emitted at the end of each PWM period + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_LOOPSDONE + Concatenated sequences have been played the amount of times defined in LOOP.CNT + 0x11C + read-write + + + EVENTS_LOOPSDONE + Concatenated sequences have been played the amount of times defined in LOOP.CNT + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + SEQEND0_STOP + Shortcut between event SEQEND[0] and task STOP + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + SEQEND1_STOP + Shortcut between event SEQEND[1] and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LOOPSDONE_SEQSTART0 + Shortcut between event LOOPSDONE and task SEQSTART[0] + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LOOPSDONE_SEQSTART1 + Shortcut between event LOOPSDONE and task SEQSTART[1] + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LOOPSDONE_STOP + Shortcut between event LOOPSDONE and task STOP + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SEQSTARTED0 + Enable or disable interrupt for event SEQSTARTED[0] + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SEQSTARTED1 + Enable or disable interrupt for event SEQSTARTED[1] + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SEQEND0 + Enable or disable interrupt for event SEQEND[0] + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SEQEND1 + Enable or disable interrupt for event SEQEND[1] + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + LOOPSDONE + Enable or disable interrupt for event LOOPSDONE + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SEQSTARTED0 + Write '1' to enable interrupt for event SEQSTARTED[0] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SEQSTARTED1 + Write '1' to enable interrupt for event SEQSTARTED[1] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SEQEND0 + Write '1' to enable interrupt for event SEQEND[0] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SEQEND1 + Write '1' to enable interrupt for event SEQEND[1] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + LOOPSDONE + Write '1' to enable interrupt for event LOOPSDONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SEQSTARTED0 + Write '1' to disable interrupt for event SEQSTARTED[0] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SEQSTARTED1 + Write '1' to disable interrupt for event SEQSTARTED[1] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SEQEND0 + Write '1' to disable interrupt for event SEQEND[0] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SEQEND1 + Write '1' to disable interrupt for event SEQEND[1] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + LOOPSDONE + Write '1' to disable interrupt for event LOOPSDONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + PWM module enable register + 0x500 + read-write + 0x00000000 + + + ENABLE + Enable or disable PWM module + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enable + 1 + + + + + + + MODE + Selects operating mode of the wave counter + 0x504 + read-write + 0x00000000 + + + UPDOWN + Selects up mode or up-and-down mode for the counter + 0 + 0 + + + Up + Up counter, edge-aligned PWM duty cycle + 0 + + + UpAndDown + Up and down counter, center-aligned PWM duty cycle + 1 + + + + + + + COUNTERTOP + Value up to which the pulse generator counter counts + 0x508 + read-write + 0x000003FF + + + COUNTERTOP + Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. + 0 + 14 + + + + + PRESCALER + Configuration for PWM_CLK + 0x50C + read-write + 0x00000000 + + + PRESCALER + Prescaler of PWM_CLK + 0 + 2 + + + DIV_1 + Divide by 1 (16 MHz) + 0 + + + DIV_2 + Divide by 2 (8 MHz) + 1 + + + DIV_4 + Divide by 4 (4 MHz) + 2 + + + DIV_8 + Divide by 8 (2 MHz) + 3 + + + DIV_16 + Divide by 16 (1 MHz) + 4 + + + DIV_32 + Divide by 32 (500 kHz) + 5 + + + DIV_64 + Divide by 64 (250 kHz) + 6 + + + DIV_128 + Divide by 128 (125 kHz) + 7 + + + + + + + DECODER + Configuration of the decoder + 0x510 + read-write + 0x00000000 + + + LOAD + How a sequence is read from RAM and spread to the compare register + 0 + 1 + + + Common + 1st half word (16-bit) used in all PWM channels 0..3 + 0 + + + Grouped + 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 + 1 + + + Individual + 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 + 2 + + + WaveForm + 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP + 3 + + + + + MODE + Selects source for advancing the active sequence + 8 + 8 + + + RefreshCount + SEQ[n].REFRESH is used to determine loading internal compare registers + 0 + + + NextStep + NEXTSTEP task causes a new value to be loaded to internal compare registers + 1 + + + + + + + LOOP + Number of playbacks of a loop + 0x514 + read-write + 0x00000000 + + + CNT + Number of playbacks of pattern cycles + 0 + 15 + + + Disabled + Looping disabled (stop at the end of the sequence) + 0 + + + + + + + 2 + 0x020 + SEQ[%s] + Unspecified + PWM_SEQ + read-write + 0x520 + + PTR + Description cluster: Beginning address in RAM of this sequence + 0x000 + read-write + 0x00000000 + + + PTR + Beginning address in RAM of this sequence + 0 + 31 + + + + + CNT + Description cluster: Number of values (duty cycles) in this sequence + 0x004 + read-write + 0x00000000 + + + CNT + Number of values (duty cycles) in this sequence + 0 + 14 + + + Disabled + Sequence is disabled, and shall not be started as it is empty + 0 + + + + + + + REFRESH + Description cluster: Number of additional PWM periods between samples loaded into compare register + 0x008 + read-write + 0x00000001 + + + CNT + Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) + 0 + 23 + + + Continuous + Update every PWM period + 0 + + + + + + + ENDDELAY + Description cluster: Time added after the sequence + 0x00C + read-write + 0x00000000 + + + CNT + Time added after the sequence in PWM periods + 0 + 23 + + + + + + PSEL + Unspecified + PWM_PSEL + read-write + 0x560 + + 0x4 + 0x4 + OUT[%s] + Description collection: Output pin select for PWM channel n + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + + + PDM + Pulse Density Modulation (Digital Microphone) Interface + 0x4001D000 + + 0 + 0x1000 + registers + + + PDM + 29 + + PDM + 0x20 + + + TASKS_START + Starts continuous PDM transfer + 0x000 + write-only + + + TASKS_START + Starts continuous PDM transfer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stops PDM transfer + 0x004 + write-only + + + TASKS_STOP + Stops PDM transfer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_STARTED + PDM transfer has started + 0x100 + read-write + + + EVENTS_STARTED + PDM transfer has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STOPPED + PDM transfer has finished + 0x104 + read-write + + + EVENTS_STOPPED + PDM transfer has finished + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_END + The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM + 0x108 + read-write + + + EVENTS_END + The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STARTED + Enable or disable interrupt for event STARTED + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + END + Enable or disable interrupt for event END + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STARTED + Write '1' to enable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + END + Write '1' to enable interrupt for event END + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STARTED + Write '1' to disable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + END + Write '1' to disable interrupt for event END + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + PDM module enable register + 0x500 + read-write + 0x00000000 + + + ENABLE + Enable or disable PDM module + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + PDMCLKCTRL + PDM clock generator control + 0x504 + read-write + 0x08400000 + + + FREQ + PDM_CLK frequency + 0 + 31 + + + 1000K + PDM_CLK = 32 MHz / 32 = 1.000 MHz + 0x08000000 + + + Default + PDM_CLK = 32 MHz / 31 = 1.032 MHz + 0x08400000 + + + 1067K + PDM_CLK = 32 MHz / 30 = 1.067 MHz + 0x08800000 + + + + + + + MODE + Defines the routing of the connected PDM microphones' signals + 0x508 + read-write + 0x00000000 + + + OPERATION + Mono or stereo operation + 0 + 0 + + + Stereo + Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] + 0 + + + Mono + Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] + 1 + + + + + EDGE + Defines on which PDM_CLK edge Left (or mono) is sampled + 1 + 1 + + + LeftFalling + Left (or mono) is sampled on falling edge of PDM_CLK + 0 + + + LeftRising + Left (or mono) is sampled on rising edge of PDM_CLK + 1 + + + + + + + GAINL + Left output gain adjustment + 0x518 + read-write + 0x00000028 + + + GAINL + Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust + 0 + 6 + + + MinGain + -20dB gain adjustment (minimum) + 0x00 + + + DefaultGain + 0dB gain adjustment ('2500 RMS' requirement) + 0x28 + + + MaxGain + +20dB gain adjustment (maximum) + 0x50 + + + + + + + GAINR + Right output gain adjustment + 0x51C + read-write + 0x00000028 + + + GAINR + Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) + 0 + 6 + + + MinGain + -20dB gain adjustment (minimum) + 0x00 + + + DefaultGain + 0dB gain adjustment ('2500 RMS' requirement) + 0x28 + + + MaxGain + +20dB gain adjustment (maximum) + 0x50 + + + + + + + PSEL + Unspecified + PDM_PSEL + read-write + 0x540 + + CLK + Pin number configuration for PDM CLK signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + DIN + Pin number configuration for PDM DIN signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + SAMPLE + Unspecified + PDM_SAMPLE + read-write + 0x560 + + PTR + RAM address pointer to write samples to with EasyDMA + 0x000 + read-write + + + SAMPLEPTR + Address to write PDM samples to over DMA + 0 + 31 + + + + + MAXCNT + Number of samples to allocate memory for in EasyDMA mode + 0x004 + read-write + + + BUFFSIZE + Length of DMA RAM allocation in number of samples + 0 + 14 + + + + + + + + NVMC + Non-volatile memory controller + 0x4001E000 + + 0 + 0x1000 + registers + + NVMC + 0x20 + + + READY + Ready flag + 0x400 + read-only + 0x00000001 + + + READY + NVMC is ready or busy + 0 + 0 + + + Busy + NVMC is busy (ongoing write or erase operation) + 0 + + + Ready + NVMC is ready + 1 + + + + + + + CONFIG + Configuration register + 0x504 + read-write + + + WEN + Program memory access mode. It is strongly recommended to activate erase and write modes only when they are actively used. + 0 + 1 + + + Ren + Read only access + 0 + + + Wen + Write enabled + 1 + + + Een + Erase enabled + 2 + + + + + + + ERASEPAGE + Register for erasing a page in code area + 0x508 + read-write + + + ERASEPAGE + Register for starting erase of a page in code area. + 0 + 31 + + + + + ERASEPCR1 + Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. + 0x508 + read-write + ERASEPAGE + + + ERASEPCR1 + Register for erasing a page in code area. Equivalent to ERASEPAGE. + 0 + 31 + + + + + ERASEALL + Register for erasing all non-volatile user memory + 0x50C + read-write + + + ERASEALL + Erase all non-volatile memory including UICR registers. Note that the erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased. + 0 + 0 + + + NoOperation + No operation + 0 + + + Erase + Start erase of chip + 1 + + + + + + + ERASEPCR0 + Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. + 0x510 + read-write + + + ERASEPCR0 + Register for starting erase of a page in code area. Equivalent to ERASEPAGE. + 0 + 31 + + + + + ERASEUICR + Register for erasing user information configuration registers + 0x514 + read-write + + + ERASEUICR + Register starting erase of all user information configuration registers. Note that the erase must be enabled using CONFIG.WEN before the UICR can be erased. + 0 + 0 + + + NoOperation + No operation + 0 + + + Erase + Start erase of UICR + 1 + + + + + + + ERASEPAGEPARTIAL + Register for partial erase of a page in code area + 0x518 + read-write + + + ERASEPAGEPARTIAL + Register for starting partial erase of a page in code area + 0 + 31 + + + + + ERASEPAGEPARTIALCFG + Register for partial erase configuration + 0x51C + read-write + 0x0000000A + + + DURATION + Duration of the partial erase in milliseconds + 0 + 6 + + + + + + + PPI + Programmable Peripheral Interconnect + 0x4001F000 + + 0 + 0x1000 + registers + + PPI + 0x20 + + + 6 + 0x008 + TASKS_CHG[%s] + Channel group tasks + PPI_TASKS_CHG + write-only + 0x000 + + EN + Description cluster: Enable channel group n + 0x000 + write-only + + + EN + Enable channel group n + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + DIS + Description cluster: Disable channel group n + 0x004 + write-only + + + DIS + Disable channel group n + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + + CHEN + Channel enable register + 0x500 + read-write + + + CH0 + Enable or disable channel 0 + 0 + 0 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH1 + Enable or disable channel 1 + 1 + 1 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH2 + Enable or disable channel 2 + 2 + 2 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH3 + Enable or disable channel 3 + 3 + 3 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH4 + Enable or disable channel 4 + 4 + 4 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH5 + Enable or disable channel 5 + 5 + 5 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH6 + Enable or disable channel 6 + 6 + 6 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH7 + Enable or disable channel 7 + 7 + 7 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH8 + Enable or disable channel 8 + 8 + 8 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH9 + Enable or disable channel 9 + 9 + 9 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH10 + Enable or disable channel 10 + 10 + 10 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH11 + Enable or disable channel 11 + 11 + 11 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH12 + Enable or disable channel 12 + 12 + 12 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH13 + Enable or disable channel 13 + 13 + 13 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH14 + Enable or disable channel 14 + 14 + 14 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH15 + Enable or disable channel 15 + 15 + 15 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH16 + Enable or disable channel 16 + 16 + 16 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH17 + Enable or disable channel 17 + 17 + 17 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH18 + Enable or disable channel 18 + 18 + 18 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH19 + Enable or disable channel 19 + 19 + 19 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH20 + Enable or disable channel 20 + 20 + 20 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH21 + Enable or disable channel 21 + 21 + 21 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH22 + Enable or disable channel 22 + 22 + 22 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH23 + Enable or disable channel 23 + 23 + 23 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH24 + Enable or disable channel 24 + 24 + 24 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH25 + Enable or disable channel 25 + 25 + 25 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH26 + Enable or disable channel 26 + 26 + 26 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH27 + Enable or disable channel 27 + 27 + 27 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH28 + Enable or disable channel 28 + 28 + 28 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH29 + Enable or disable channel 29 + 29 + 29 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH30 + Enable or disable channel 30 + 30 + 30 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH31 + Enable or disable channel 31 + 31 + 31 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + + + CHENSET + Channel enable set register + 0x504 + read-write + oneToSet + + + CH0 + Channel 0 enable set register. Writing '0' has no effect + 0 + 0 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH1 + Channel 1 enable set register. Writing '0' has no effect + 1 + 1 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH2 + Channel 2 enable set register. Writing '0' has no effect + 2 + 2 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH3 + Channel 3 enable set register. Writing '0' has no effect + 3 + 3 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH4 + Channel 4 enable set register. Writing '0' has no effect + 4 + 4 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH5 + Channel 5 enable set register. Writing '0' has no effect + 5 + 5 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH6 + Channel 6 enable set register. Writing '0' has no effect + 6 + 6 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH7 + Channel 7 enable set register. Writing '0' has no effect + 7 + 7 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH8 + Channel 8 enable set register. Writing '0' has no effect + 8 + 8 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH9 + Channel 9 enable set register. Writing '0' has no effect + 9 + 9 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH10 + Channel 10 enable set register. Writing '0' has no effect + 10 + 10 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH11 + Channel 11 enable set register. Writing '0' has no effect + 11 + 11 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH12 + Channel 12 enable set register. Writing '0' has no effect + 12 + 12 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH13 + Channel 13 enable set register. Writing '0' has no effect + 13 + 13 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH14 + Channel 14 enable set register. Writing '0' has no effect + 14 + 14 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH15 + Channel 15 enable set register. Writing '0' has no effect + 15 + 15 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH16 + Channel 16 enable set register. Writing '0' has no effect + 16 + 16 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH17 + Channel 17 enable set register. Writing '0' has no effect + 17 + 17 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH18 + Channel 18 enable set register. Writing '0' has no effect + 18 + 18 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH19 + Channel 19 enable set register. Writing '0' has no effect + 19 + 19 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH20 + Channel 20 enable set register. Writing '0' has no effect + 20 + 20 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH21 + Channel 21 enable set register. Writing '0' has no effect + 21 + 21 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH22 + Channel 22 enable set register. Writing '0' has no effect + 22 + 22 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH23 + Channel 23 enable set register. Writing '0' has no effect + 23 + 23 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH24 + Channel 24 enable set register. Writing '0' has no effect + 24 + 24 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH25 + Channel 25 enable set register. Writing '0' has no effect + 25 + 25 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH26 + Channel 26 enable set register. Writing '0' has no effect + 26 + 26 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH27 + Channel 27 enable set register. Writing '0' has no effect + 27 + 27 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH28 + Channel 28 enable set register. Writing '0' has no effect + 28 + 28 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH29 + Channel 29 enable set register. Writing '0' has no effect + 29 + 29 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH30 + Channel 30 enable set register. Writing '0' has no effect + 30 + 30 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH31 + Channel 31 enable set register. Writing '0' has no effect + 31 + 31 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + + + CHENCLR + Channel enable clear register + 0x508 + read-write + oneToClear + + + CH0 + Channel 0 enable clear register. Writing '0' has no effect + 0 + 0 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH1 + Channel 1 enable clear register. Writing '0' has no effect + 1 + 1 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH2 + Channel 2 enable clear register. Writing '0' has no effect + 2 + 2 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH3 + Channel 3 enable clear register. Writing '0' has no effect + 3 + 3 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH4 + Channel 4 enable clear register. Writing '0' has no effect + 4 + 4 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH5 + Channel 5 enable clear register. Writing '0' has no effect + 5 + 5 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH6 + Channel 6 enable clear register. Writing '0' has no effect + 6 + 6 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH7 + Channel 7 enable clear register. Writing '0' has no effect + 7 + 7 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH8 + Channel 8 enable clear register. Writing '0' has no effect + 8 + 8 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH9 + Channel 9 enable clear register. Writing '0' has no effect + 9 + 9 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH10 + Channel 10 enable clear register. Writing '0' has no effect + 10 + 10 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH11 + Channel 11 enable clear register. Writing '0' has no effect + 11 + 11 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH12 + Channel 12 enable clear register. Writing '0' has no effect + 12 + 12 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH13 + Channel 13 enable clear register. Writing '0' has no effect + 13 + 13 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH14 + Channel 14 enable clear register. Writing '0' has no effect + 14 + 14 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH15 + Channel 15 enable clear register. Writing '0' has no effect + 15 + 15 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH16 + Channel 16 enable clear register. Writing '0' has no effect + 16 + 16 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH17 + Channel 17 enable clear register. Writing '0' has no effect + 17 + 17 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH18 + Channel 18 enable clear register. Writing '0' has no effect + 18 + 18 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH19 + Channel 19 enable clear register. Writing '0' has no effect + 19 + 19 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH20 + Channel 20 enable clear register. Writing '0' has no effect + 20 + 20 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH21 + Channel 21 enable clear register. Writing '0' has no effect + 21 + 21 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH22 + Channel 22 enable clear register. Writing '0' has no effect + 22 + 22 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH23 + Channel 23 enable clear register. Writing '0' has no effect + 23 + 23 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH24 + Channel 24 enable clear register. Writing '0' has no effect + 24 + 24 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH25 + Channel 25 enable clear register. Writing '0' has no effect + 25 + 25 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH26 + Channel 26 enable clear register. Writing '0' has no effect + 26 + 26 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH27 + Channel 27 enable clear register. Writing '0' has no effect + 27 + 27 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH28 + Channel 28 enable clear register. Writing '0' has no effect + 28 + 28 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH29 + Channel 29 enable clear register. Writing '0' has no effect + 29 + 29 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH30 + Channel 30 enable clear register. Writing '0' has no effect + 30 + 30 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH31 + Channel 31 enable clear register. Writing '0' has no effect + 31 + 31 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + + + 20 + 0x008 + CH[%s] + PPI Channel + PPI_CH + read-write + 0x510 + + EEP + Description cluster: Channel n event end-point + 0x000 + read-write + + + EEP + Pointer to event register. Accepts only addresses to registers from the Event group. + 0 + 31 + + + + + TEP + Description cluster: Channel n task end-point + 0x004 + read-write + + + TEP + Pointer to task register. Accepts only addresses to registers from the Task group. + 0 + 31 + + + + + + 0x6 + 0x4 + CHG[%s] + Description collection: Channel group n + 0x800 + read-write + + + CH0 + Include or exclude channel 0 + 0 + 0 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH1 + Include or exclude channel 1 + 1 + 1 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH2 + Include or exclude channel 2 + 2 + 2 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH3 + Include or exclude channel 3 + 3 + 3 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH4 + Include or exclude channel 4 + 4 + 4 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH5 + Include or exclude channel 5 + 5 + 5 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH6 + Include or exclude channel 6 + 6 + 6 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH7 + Include or exclude channel 7 + 7 + 7 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH8 + Include or exclude channel 8 + 8 + 8 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH9 + Include or exclude channel 9 + 9 + 9 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH10 + Include or exclude channel 10 + 10 + 10 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH11 + Include or exclude channel 11 + 11 + 11 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH12 + Include or exclude channel 12 + 12 + 12 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH13 + Include or exclude channel 13 + 13 + 13 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH14 + Include or exclude channel 14 + 14 + 14 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH15 + Include or exclude channel 15 + 15 + 15 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH16 + Include or exclude channel 16 + 16 + 16 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH17 + Include or exclude channel 17 + 17 + 17 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH18 + Include or exclude channel 18 + 18 + 18 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH19 + Include or exclude channel 19 + 19 + 19 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH20 + Include or exclude channel 20 + 20 + 20 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH21 + Include or exclude channel 21 + 21 + 21 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH22 + Include or exclude channel 22 + 22 + 22 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH23 + Include or exclude channel 23 + 23 + 23 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH24 + Include or exclude channel 24 + 24 + 24 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH25 + Include or exclude channel 25 + 25 + 25 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH26 + Include or exclude channel 26 + 26 + 26 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH27 + Include or exclude channel 27 + 27 + 27 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH28 + Include or exclude channel 28 + 28 + 28 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH29 + Include or exclude channel 29 + 29 + 29 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH30 + Include or exclude channel 30 + 30 + 30 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH31 + Include or exclude channel 31 + 31 + 31 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + + + 32 + 0x004 + FORK[%s] + Fork + PPI_FORK + read-write + 0x910 + + TEP + Description cluster: Channel n task end-point + 0x000 + read-write + + + TEP + Pointer to task register + 0 + 31 + + + + + + + + diff --git a/svd/nrf52820.svd b/svd/nrf52820.svd index 3d46f6c..11cc442 100644 --- a/svd/nrf52820.svd +++ b/svd/nrf52820.svd @@ -8,7 +8,7 @@ 1 nRF52820 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller -Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.\n +Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved.\n \n SPDX-License-Identifier: BSD-3-Clause\n \n @@ -52,7 +52,7 @@ POSSIBILITY OF SUCH DAMAGE.\n 3 0 - system_nrf52820 + system_nrf52 NRF_ 2048 @@ -273,6 +273,11 @@ POSSIBILITY OF SUCH DAMAGE.\n AAC1 0x41414331 + + AAD0 + AAD0 + 0x41414430 + Unspecified Unspecified @@ -324,27 +329,27 @@ POSSIBILITY OF SUCH DAMAGE.\n K16 - 16 kByte RAM + 16 kB RAM 0x10 K32 - 32 kByte RAM + 32 kB RAM 0x20 K64 - 64 kByte RAM + 64 kB RAM 0x40 K128 - 128 kByte RAM + 128 kB RAM 0x80 K256 - 256 kByte RAM + 256 kB RAM 0x100 @@ -371,27 +376,27 @@ POSSIBILITY OF SUCH DAMAGE.\n K128 - 128 kByte FLASH + 128 kB FLASH 0x80 K256 - 256 kByte FLASH + 256 kB FLASH 0x100 K512 - 512 kByte FLASH + 512 kB FLASH 0x200 K1024 - 1 MByte FLASH + 1 MB FLASH 0x400 K2048 - 2 MByte FLASH + 2 MB FLASH 0x800 @@ -12040,12 +12045,12 @@ POSSIBILITY OF SUCH DAMAGE.\n Default - Channel map between 2400 MHZ .. 2500 MHz + Channel map between 2400 MHz and 2500 MHz 0 Low - Channel map between 2360 MHZ .. 2460 MHz + Channel map between 2360 MHz and 2460 MHz 1 @@ -12177,12 +12182,12 @@ POSSIBILITY OF SUCH DAMAGE.\n Ble_LR125Kbit - Long range 125 kbps TX, 125 kbps and 500 kbps RX + Long Range 125 kbps TX, 125 kbps and 500 kbps RX 5 Ble_LR500Kbit - Long range 500 kbps TX, 125 kbps and 500 kbps RX + Long Range 500 kbps TX, 125 kbps and 500 kbps RX 6 @@ -12238,7 +12243,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CILEN - Length of code indicator - long range + Length of code indicator - Long Range 22 23 @@ -12265,7 +12270,7 @@ POSSIBILITY OF SUCH DAMAGE.\n LongRange - Preamble - used for BLE long range + Preamble - used for Bluetooth LE Long Range 3 @@ -13621,13 +13626,13 @@ POSSIBILITY OF SUCH DAMAGE.\n TSWITCHOFFSET - Signed value offset after the end of the CRC before starting switching in number of 16M cycles + Signed value offset after the end of the CRC before starting switching in number of 16 MHz clock cycles 0 12 TSAMPLEOFFSET - Signed value offset before starting sampling in number of 16M cycles relative to the beginning of the REFERENCE state - 12 us after switching start + Signed value offset in number of 16 MHz clock cycles for fine tuning of the sampling instant for all IQ samples. With TSAMPLEOFFSET=0 the first sample is taken immediately at the start of the reference period 16 27 @@ -26296,7 +26301,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CCM - AES CCM Mode Encryption + AES CCM mode encryption 0x4000F000 AAR @@ -26738,7 +26743,7 @@ POSSIBILITY OF SUCH DAMAGE.\n MODE - The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered. + The mode of operation to be used. Settings in this register apply whenever either the KSGEN task or the CRYPT task is triggered. 0 0 @@ -26772,12 +26777,12 @@ POSSIBILITY OF SUCH DAMAGE.\n 125Kbps - 125 Kbps + 125 kbps 2 500Kbps - 500 Kbps + 500 kbps 3 @@ -26804,13 +26809,13 @@ POSSIBILITY OF SUCH DAMAGE.\n CNFPTR - Pointer to data structure holding AES key and NONCE vector + Pointer to data structure holding the AES key and the NONCE vector 0x508 read-write CNFPTR - Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) + Pointer to the data structure holding the AES key and the CCM NONCE vector (see table CCM data structure overview) 0 31 @@ -26861,14 +26866,14 @@ POSSIBILITY OF SUCH DAMAGE.\n MAXPACKETSIZE - Length of keystream generated when MODE.LENGTH = Extended. + Length of keystream generated when MODE.LENGTH = Extended 0x518 read-write 0x000000FB MAXPACKETSIZE - Length of keystream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. + Length of keystream generated when MODE.LENGTH = Extended. This value must be greater than or equal to the subsequent packet payload to be encrypted/decrypted. 0 7 @@ -26883,7 +26888,7 @@ POSSIBILITY OF SUCH DAMAGE.\n RATEOVERRIDE - Data rate override setting. + Data rate override setting 0 1 @@ -26899,18 +26904,33 @@ POSSIBILITY OF SUCH DAMAGE.\n 125Kbps - 125 Kbps + 125 kbps 2 500Kbps - 500 Kbps + 500 kbps 3 + + HEADERMASK + Header (S0) mask. + 0x520 + read-write + 0x000000E3 + + + HEADERMASK + Header (S0) mask + 0 + 7 + + + @@ -30825,7 +30845,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SIZE - Description cluster: Size of region to protect counting from address ACL[n].ADDR. Write '0' as no effect. + Description cluster: Size of region to protect counting from address ACL[n].ADDR. Writing a '0' has no effect. 0x004 read-writeOnce 0x00000000 @@ -30847,36 +30867,36 @@ POSSIBILITY OF SUCH DAMAGE.\n WRITE - Configure write and erase permissions for region n. Write '0' has no effect. + Configure write and erase permissions for region n. Writing a '0' has no effect. 1 1 Enable - Allow write and erase instructions to region n + Allow write and erase instructions to region n. 0 Disable - Block write and erase instructions to region n + Block write and erase instructions to region n. 1 READ - Configure read permissions for region n. Write '0' has no effect. + Configure read permissions for region n. Writing a '0' has no effect. 2 2 Enable - Allow read instructions to region n + Allow read instructions to region n. 0 Disable - Block read instructions to region n + Block read instructions to region n. 1 @@ -38467,4 +38487,4 @@ POSSIBILITY OF SUCH DAMAGE.\n - \ No newline at end of file + diff --git a/svd/nrf52833.svd b/svd/nrf52833.svd index 70eb75f..c0f7b2c 100644 --- a/svd/nrf52833.svd +++ b/svd/nrf52833.svd @@ -8,7 +8,9 @@ 1 nRF52833 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved.\n +Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved.\n +\n +SPDX-License-Identifier: BSD-3-Clause\n \n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions are met:\n @@ -50,7 +52,7 @@ POSSIBILITY OF SUCH DAMAGE.\n 3 0 - system_nrf52833 + system_nrf52 NRF_ 2048 @@ -214,6 +216,11 @@ POSSIBILITY OF SUCH DAMAGE.\n 0 31 + + N52820 + nRF52820 + 0x52820 + N52833 nRF52833 @@ -256,6 +263,21 @@ POSSIBILITY OF SUCH DAMAGE.\n AAAB 0x41414142 + + AAA0 + AAA0 + 0x41414130 + + + AAA1 + AAA1 + 0x41414131 + + + AAB0 + AAB0 + 0x41414230 + Unspecified Unspecified @@ -280,17 +302,17 @@ POSSIBILITY OF SUCH DAMAGE.\n QD - QDxx - 40-pin QFN + QDxx - 5x5 40-pin QFN 0x2007 QI - QIxx - 73-pin aQFN + QIxx - 7x7 73-pin aQFN 0x2004 CJ - CJxx - WLCSP + CJxx - 3.175 x 3.175 WLCSP 0x2008 @@ -948,9 +970,14 @@ POSSIBILITY OF SUCH DAMAGE.\n Disabled - Disable + Hardware disable of access port protection for devices where access port protection is controlled by hardware 0xFF + + HwDisabled + Hardware disable of access port protection for devices where access port protection is controlled by hardware and software + 0x5A + Enabled Enable @@ -975,12 +1002,12 @@ POSSIBILITY OF SUCH DAMAGE.\n Disabled - Operation as GPIO pins. Same protection as normal GPIO pins + Operation as GPIO pins. Same protection as normal GPIO pins. 0 NFC - Operation as NFC antenna pins. Configures the protection for NFC operation + Operation as NFC antenna pins. Configures the protection for NFC operation. 1 @@ -1034,7 +1061,7 @@ POSSIBILITY OF SUCH DAMAGE.\n REGOUT0 - Output voltage from REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - VREG0DROP. + Output voltage from REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - V_VDDH-VDD. 0x304 read-write 0xFFFFFFFF @@ -1086,10 +1113,70 @@ POSSIBILITY OF SUCH DAMAGE.\n + + APPROTECT + Access Port Protection + 0x40000000 + + 0 + 0x1000 + registers + + APPROTECT + 0x20 + + + FORCEPROTECT + Software force enable APPROTECT mechanism until next reset. + 0x550 + read-writeOnce + 0xFFFFFFFF + + + FORCEPROTECT + Write 0x0 to force enable APPROTECT mechanism + 0 + 7 + + write + + Force + Software force enable APPROTECT mechanism + 0x0 + + + + + + + DISABLE + Software disable APPROTECT mechanism + 0x558 + read-write + 0x00000000 + + + DISABLE + Software disable APPROTECT mechanism + 0 + 7 + + + SwDisable + Software disable APPROTECT mechanism + 0x5A + + + + + + + CLOCK Clock control 0x40000000 + APPROTECT 0 0x1000 @@ -2122,7 +2209,7 @@ POSSIBILITY OF SUCH DAMAGE.\n POWER Power control 0x40000000 - CLOCK + APPROTECT 0 0x1000 @@ -5325,7 +5412,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5352,7 +5439,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5379,7 +5466,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5406,7 +5493,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5433,7 +5520,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5460,7 +5547,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5487,7 +5574,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5514,7 +5601,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5541,7 +5628,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5568,7 +5655,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5595,7 +5682,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5622,7 +5709,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5649,7 +5736,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5676,7 +5763,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5703,7 +5790,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5730,7 +5817,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5757,7 +5844,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5784,7 +5871,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5811,7 +5898,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5838,7 +5925,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5865,7 +5952,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5892,7 +5979,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5919,7 +6006,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5946,7 +6033,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5973,7 +6060,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -6000,7 +6087,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -6027,7 +6114,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -6054,7 +6141,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -6081,7 +6168,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -6108,7 +6195,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -6135,7 +6222,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -6162,7 +6249,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -6198,7 +6285,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6225,7 +6312,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6252,7 +6339,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6279,7 +6366,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6306,7 +6393,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6333,7 +6420,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6360,7 +6447,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6387,7 +6474,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6414,7 +6501,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6441,7 +6528,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6468,7 +6555,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6495,7 +6582,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6522,7 +6609,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6549,7 +6636,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6576,7 +6663,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6603,7 +6690,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6630,7 +6717,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6657,7 +6744,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6684,7 +6771,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6711,7 +6798,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6738,7 +6825,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6765,7 +6852,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6792,7 +6879,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6819,7 +6906,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6846,7 +6933,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6873,7 +6960,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6900,7 +6987,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6927,7 +7014,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6954,7 +7041,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6981,7 +7068,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -7008,7 +7095,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -7035,7 +7122,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -8239,7 +8326,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8266,7 +8353,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8293,7 +8380,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8320,7 +8407,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8347,7 +8434,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8374,7 +8461,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8401,7 +8488,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8428,7 +8515,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8455,7 +8542,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8482,7 +8569,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8509,7 +8596,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8536,7 +8623,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8563,7 +8650,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8590,7 +8677,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8617,7 +8704,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8644,7 +8731,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8671,7 +8758,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8698,7 +8785,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8725,7 +8812,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8752,7 +8839,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8779,7 +8866,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8806,7 +8893,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8833,7 +8920,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8860,7 +8947,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8887,7 +8974,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8914,7 +9001,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8941,7 +9028,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8968,7 +9055,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8995,7 +9082,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -9022,7 +9109,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -9049,7 +9136,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -9076,7 +9163,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -9112,7 +9199,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9139,7 +9226,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9166,7 +9253,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9193,7 +9280,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9220,7 +9307,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9247,7 +9334,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9274,7 +9361,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9301,7 +9388,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9328,7 +9415,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9355,7 +9442,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9382,7 +9469,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9409,7 +9496,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9436,7 +9523,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9463,7 +9550,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9490,7 +9577,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9517,7 +9604,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9544,7 +9631,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9571,7 +9658,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9598,7 +9685,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9625,7 +9712,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9652,7 +9739,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9679,7 +9766,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9706,7 +9793,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9733,7 +9820,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9760,7 +9847,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9787,7 +9874,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9814,7 +9901,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9841,7 +9928,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9868,7 +9955,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9895,7 +9982,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9922,7 +10009,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9949,7 +10036,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -10542,13 +10629,13 @@ POSSIBILITY OF SUCH DAMAGE.\n DETECTMODE - Select between default DETECT signal behaviour and LDETECT mode + Select between default DETECT signal behavior and LDETECT mode 0x524 read-write DETECTMODE - Select between default DETECT signal behaviour and LDETECT mode + Select between default DETECT signal behavior and LDETECT mode 0 0 @@ -10559,7 +10646,7 @@ POSSIBILITY OF SUCH DAMAGE.\n LDETECT - Use the latched LDETECT behaviour + Use the latched LDETECT behavior 1 @@ -11318,13 +11405,13 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_EDEND - Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register + Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. 0x13C read-write EVENTS_EDEND - Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register + Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. 0 0 @@ -13522,7 +13609,7 @@ POSSIBILITY OF SUCH DAMAGE.\n MAP - Channel map selection. + Channel map selection 8 8 @@ -13690,19 +13777,19 @@ POSSIBILITY OF SUCH DAMAGE.\n LFLEN - Length on air of LENGTH field in number of bits. + Length on air of LENGTH field in number of bits 0 3 S0LEN - Length on air of S0 field in number of bytes. + Length on air of S0 field in number of bytes 8 8 S1LEN - Length on air of S1 field in number of bits. + Length on air of S1 field in number of bits 16 19 @@ -14112,7 +14199,7 @@ POSSIBILITY OF SUCH DAMAGE.\n LEN - CRC length in number of bytes. + CRC length in number of bytes For MODE Ble_LR125Kbit and Ble_LR500Kbit, only LEN set to 3 is supported 0 1 @@ -14200,7 +14287,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TIFS - Interframe spacing in us + Interframe spacing in us. 0 9 @@ -14214,7 +14301,7 @@ POSSIBILITY OF SUCH DAMAGE.\n RSSISAMPLE - RSSI sample + RSSI sample. 0 6 @@ -14590,7 +14677,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Fast - Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specification for more information + Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specifications for more information 1 @@ -14826,93 +14913,93 @@ POSSIBILITY OF SUCH DAMAGE.\n 20 - 20 in 8us unit (default) Set to 20 if parsed CTETime is larger han 20 + 20 in 8 us unit (default) Set to 20 if parsed CTETime is larger than 20 0 31 - 31 in 8us unit + 31 in 8 us unit 1 63 - 63 in 8us unit + 63 in 8 us unit 2 CTEINLINERXMODE1US - Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set + Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set. 10 12 4us - 4us + 4 us 1 2us - 2us + 2 us 2 1us - 1us + 1 us 3 500ns - 0.5us + 0.5 us 4 250ns - 0.25us + 0.25 us 5 125ns - 0.125us + 0.125 us 6 CTEINLINERXMODE2US - Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set + Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set. 13 15 4us - 4us + 4 us 1 2us - 2us + 2 us 2 1us - 1us + 1 us 3 500ns - 0.5us + 0.5 us 4 250ns - 0.25us + 0.25 us 5 125ns - 0.125us + 0.125 us 6 @@ -14970,17 +15057,17 @@ POSSIBILITY OF SUCH DAMAGE.\n 4us - 4us + 4 us 1 2us - 2us + 2 us 2 1us - 1us + 1 us 3 @@ -14993,32 +15080,32 @@ POSSIBILITY OF SUCH DAMAGE.\n 4us - 4us + 4 us 1 2us - 2us + 2 us 2 1us - 1us + 1 us 3 500ns - 0.5us + 0.5 us 4 250ns - 0.25us + 0.25 us 5 125ns - 0.125us + 0.125 us 6 @@ -15049,32 +15136,32 @@ POSSIBILITY OF SUCH DAMAGE.\n 4us - 4us + 4 us 1 2us - 2us + 2 us 2 1us - 1us + 1 us 3 500ns - 0.5us + 0.5 us 4 250ns - 0.25us + 0.25 us 5 125ns - 0.125us + 0.125 us 6 @@ -15130,7 +15217,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SWITCHPATTERN - Fill array of GPIO patterns for antenna control + Fill array of GPIO patterns for antenna control. 0 7 @@ -17711,7 +17798,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ERRORSRC - Error source Note : this register is read / write one to clear. + Error source This register is read/write one to clear. 0x480 read-write oneToClear @@ -18083,7 +18170,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Baud1M - 1Mega baud + 1 megabaud 0x10000000 @@ -18556,7 +18643,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TXD - TX data to send. Double buffered + TX data to send. Double buffered. 0 7 @@ -19224,7 +19311,7 @@ POSSIBILITY OF SUCH DAMAGE.\n STALLSTAT - Stall status for EasyDMA RAM accesses. The fields in this register is set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU. + Stall status for EasyDMA RAM accesses. The fields in this register are set to STALL by hardware whenever a stall occurs and can be cleared (set to NOSTALL) by the CPU. 0x400 read-write 0x00000000 @@ -21829,13 +21916,13 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_SUSPENDED - Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. + SUSPEND task has been issued, TWI traffic is now suspended. 0x148 read-write EVENTS_SUSPENDED - Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. + SUSPEND task has been issued, TWI traffic is now suspended. 0 0 @@ -23823,7 +23910,7 @@ POSSIBILITY OF SUCH DAMAGE.\n MATCH - Which of the addresses in {ADDRESS} matched the incoming address + Indication of which address in {ADDRESS} that matched the incoming address 0 0 @@ -26085,8 +26172,8 @@ POSSIBILITY OF SUCH DAMAGE.\n SLEEPSTATE - Reflects the sleep state during automatic collision resolution. Set to IDLE - by a GOIDLE task. Set to SLEEP_A when a valid SLEEP_REQ frame is received or by a + Reflects the sleep state during automatic collision resolution. Set to IDLE + by a GOIDLE task. Set to SLEEP_A when a valid SLEEP_REQ frame is received or by a GOSLEEP task. 0 0 @@ -31878,7 +31965,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PRESCALER - 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped + 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is stopped. 0x508 read-write @@ -32079,14 +32166,14 @@ POSSIBILITY OF SUCH DAMAGE.\n A0 - Slope of 1st piece wise linear function + Slope of first piecewise linear function 0x520 read-write 0x00000326 A0 - Slope of 1st piece wise linear function + Slope of first piecewise linear function 0 11 @@ -32094,14 +32181,14 @@ POSSIBILITY OF SUCH DAMAGE.\n A1 - Slope of 2nd piece wise linear function + Slope of second piecewise linear function 0x524 read-write 0x00000348 A1 - Slope of 2nd piece wise linear function + Slope of second piecewise linear function 0 11 @@ -32109,14 +32196,14 @@ POSSIBILITY OF SUCH DAMAGE.\n A2 - Slope of 3rd piece wise linear function + Slope of third piecewise linear function 0x528 read-write 0x000003AA A2 - Slope of 3rd piece wise linear function + Slope of third piecewise linear function 0 11 @@ -32124,14 +32211,14 @@ POSSIBILITY OF SUCH DAMAGE.\n A3 - Slope of 4th piece wise linear function + Slope of fourth piecewise linear function 0x52C read-write 0x0000040E A3 - Slope of 4th piece wise linear function + Slope of fourth piecewise linear function 0 11 @@ -32139,14 +32226,14 @@ POSSIBILITY OF SUCH DAMAGE.\n A4 - Slope of 5th piece wise linear function + Slope of fifth piecewise linear function 0x530 read-write 0x000004BD A4 - Slope of 5th piece wise linear function + Slope of fifth piecewise linear function 0 11 @@ -32154,14 +32241,14 @@ POSSIBILITY OF SUCH DAMAGE.\n A5 - Slope of 6th piece wise linear function + Slope of sixth piecewise linear function 0x534 read-write 0x000005A3 A5 - Slope of 6th piece wise linear function + Slope of sixth piecewise linear function 0 11 @@ -32169,14 +32256,14 @@ POSSIBILITY OF SUCH DAMAGE.\n B0 - y-intercept of 1st piece wise linear function + y-intercept of first piecewise linear function 0x540 read-write 0x00003FEF B0 - y-intercept of 1st piece wise linear function + y-intercept of first piecewise linear function 0 13 @@ -32184,14 +32271,14 @@ POSSIBILITY OF SUCH DAMAGE.\n B1 - y-intercept of 2nd piece wise linear function + y-intercept of second piecewise linear function 0x544 read-write 0x00003FBE B1 - y-intercept of 2nd piece wise linear function + y-intercept of second piecewise linear function 0 13 @@ -32199,14 +32286,14 @@ POSSIBILITY OF SUCH DAMAGE.\n B2 - y-intercept of 3rd piece wise linear function + y-intercept of third piecewise linear function 0x548 read-write 0x00003FBE B2 - y-intercept of 3rd piece wise linear function + y-intercept of third piecewise linear function 0 13 @@ -32214,14 +32301,14 @@ POSSIBILITY OF SUCH DAMAGE.\n B3 - y-intercept of 4th piece wise linear function + y-intercept of fourth piecewise linear function 0x54C read-write 0x00000012 B3 - y-intercept of 4th piece wise linear function + y-intercept of fourth piecewise linear function 0 13 @@ -32229,14 +32316,14 @@ POSSIBILITY OF SUCH DAMAGE.\n B4 - y-intercept of 5th piece wise linear function + y-intercept of fifth piecewise linear function 0x550 read-write 0x00000124 B4 - y-intercept of 5th piece wise linear function + y-intercept of fifth piecewise linear function 0 13 @@ -32244,14 +32331,14 @@ POSSIBILITY OF SUCH DAMAGE.\n B5 - y-intercept of 6th piece wise linear function + y-intercept of sixth piecewise linear function 0x554 read-write 0x0000027C B5 - y-intercept of 6th piece wise linear function + y-intercept of sixth piecewise linear function 0 13 @@ -32259,14 +32346,14 @@ POSSIBILITY OF SUCH DAMAGE.\n T0 - End point of 1st piece wise linear function + End point of first piecewise linear function 0x560 read-write 0x000000E2 T0 - End point of 1st piece wise linear function + End point of first piecewise linear function 0 7 @@ -32274,14 +32361,14 @@ POSSIBILITY OF SUCH DAMAGE.\n T1 - End point of 2nd piece wise linear function + End point of second piecewise linear function 0x564 read-write 0x00000000 T1 - End point of 2nd piece wise linear function + End point of second piecewise linear function 0 7 @@ -32289,14 +32376,14 @@ POSSIBILITY OF SUCH DAMAGE.\n T2 - End point of 3rd piece wise linear function + End point of third piecewise linear function 0x568 read-write 0x00000019 T2 - End point of 3rd piece wise linear function + End point of third piecewise linear function 0 7 @@ -32304,14 +32391,14 @@ POSSIBILITY OF SUCH DAMAGE.\n T3 - End point of 4th piece wise linear function + End point of fourth piecewise linear function 0x56C read-write 0x0000003C T3 - End point of 4th piece wise linear function + End point of fourth piecewise linear function 0 7 @@ -32319,14 +32406,14 @@ POSSIBILITY OF SUCH DAMAGE.\n T4 - End point of 5th piece wise linear function + End point of fifth piecewise linear function 0x570 read-write 0x00000050 T4 - End point of 5th piece wise linear function + End point of fifth piecewise linear function 0 7 @@ -33169,7 +33256,7 @@ POSSIBILITY OF SUCH DAMAGE.\n NIRK - Number of Identity root keys available in the IRK data structure + Number of Identity Root Keys available in the IRK data structure 0 4 @@ -33221,7 +33308,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CCM - AES CCM Mode Encryption + AES CCM mode encryption 0x4000F000 AAR @@ -33238,13 +33325,13 @@ POSSIBILITY OF SUCH DAMAGE.\n TASKS_KSGEN - Start generation of key-stream. This operation will stop by itself when completed. + Start generation of keystream. This operation will stop by itself when completed. 0x000 write-only TASKS_KSGEN - Start generation of key-stream. This operation will stop by itself when completed. + Start generation of keystream. This operation will stop by itself when completed. 0 0 @@ -33322,13 +33409,13 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_ENDKSGEN - Key-stream generation complete + Keystream generation complete 0x100 read-write EVENTS_ENDKSGEN - Key-stream generation complete + Keystream generation complete 0 0 @@ -33663,7 +33750,7 @@ POSSIBILITY OF SUCH DAMAGE.\n MODE - The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered. + The mode of operation to be used. Settings in this register apply whenever either the KSGEN task or the CRYPT task is triggered. 0 0 @@ -33697,12 +33784,12 @@ POSSIBILITY OF SUCH DAMAGE.\n 125Kbps - 125 Kbps + 125 kbps 2 500Kbps - 500 Kbps + 500 kbps 3 @@ -33715,12 +33802,12 @@ POSSIBILITY OF SUCH DAMAGE.\n Default - Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packet payloads up to 27 bytes will be generated. + Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A keystream for packet payloads up to 27 bytes will be generated. 0 Extended - Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packet payloads up to MAXPACKETSIZE bytes will be generated. + Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A keystream for packet payloads up to MAXPACKETSIZE bytes will be generated. 1 @@ -33729,13 +33816,13 @@ POSSIBILITY OF SUCH DAMAGE.\n CNFPTR - Pointer to data structure holding AES key and NONCE vector + Pointer to data structure holding the AES key and the NONCE vector 0x508 read-write CNFPTR - Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) + Pointer to the data structure holding the AES key and the CCM NONCE vector (see table CCM data structure overview) 0 31 @@ -33777,7 +33864,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SCRATCHPTR - Pointer to a scratch data area used for temporary storage during key-stream generation, + Pointer to a scratch data area used for temporary storage during keystream generation, MIC generation and encryption/decryption. 0 31 @@ -33786,14 +33873,14 @@ POSSIBILITY OF SUCH DAMAGE.\n MAXPACKETSIZE - Length of key-stream generated when MODE.LENGTH = Extended. + Length of keystream generated when MODE.LENGTH = Extended 0x518 read-write 0x000000FB MAXPACKETSIZE - Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. + Length of keystream generated when MODE.LENGTH = Extended. This value must be greater than or equal to the subsequent packet payload to be encrypted/decrypted. 0 7 @@ -33808,7 +33895,7 @@ POSSIBILITY OF SUCH DAMAGE.\n RATEOVERRIDE - Data rate override setting. + Data rate override setting 0 1 @@ -33824,18 +33911,33 @@ POSSIBILITY OF SUCH DAMAGE.\n 125Kbps - 125 Kbps + 125 kbps 2 500Kbps - 500 Kbps + 500 kbps 3 + + HEADERMASK + Header (S0) mask. + 0x520 + read-write + 0x000000E3 + + + HEADERMASK + Header (S0) mask + 0 + 7 + + + @@ -35214,53 +35316,53 @@ POSSIBILITY OF SUCH DAMAGE.\n REPORTPER - Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated + Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated. 0 3 10Smpl - 10 samples / report + 10 samples/report 0 40Smpl - 40 samples / report + 40 samples/report 1 80Smpl - 80 samples / report + 80 samples/report 2 120Smpl - 120 samples / report + 120 samples/report 3 160Smpl - 160 samples / report + 160 samples/report 4 200Smpl - 200 samples / report + 200 samples/report 5 240Smpl - 240 samples / report + 240 samples/report 6 280Smpl - 280 samples / report + 280 samples/report 7 1Smpl - 1 sample / report + 1 sample/report 8 @@ -35276,7 +35378,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ACC - Register accumulating all valid samples (not double transition) read from the SAMPLE register + Register accumulating all valid samples (not double transition) read from the SAMPLE register. 0 31 @@ -40487,14 +40589,14 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x800 ADDR - Description cluster: Configure the word-aligned start address of region n to protect + Description cluster: Start address of region to protect. The start address must be word-aligned. 0x000 - read-write + read-writeOnce 0x00000000 ADDR - Valid word-aligned start address of region n to protect. Address must point to a flash page boundary. + Start address of flash region n. The start address must point to a flash page boundary. 0 31 @@ -40502,9 +40604,9 @@ POSSIBILITY OF SUCH DAMAGE.\n SIZE - Description cluster: Size of region to protect counting from address ACL[n].ADDR. Write '0' as no effect. + Description cluster: Size of region to protect counting from address ACL[n].ADDR. Writing a '0' has no effect. 0x004 - read-write + read-writeOnce 0x00000000 @@ -40519,41 +40621,41 @@ POSSIBILITY OF SUCH DAMAGE.\n PERM Description cluster: Access permissions for region n as defined by start address ACL[n].ADDR and size ACL[n].SIZE 0x008 - read-write + read-writeOnce 0x00000000 WRITE - Configure write and erase permissions for region n. Write '0' has no effect. + Configure write and erase permissions for region n. Writing a '0' has no effect. 1 1 Enable - Allow write and erase instructions to region n + Allow write and erase instructions to region n. 0 Disable - Block write and erase instructions to region n + Block write and erase instructions to region n. 1 READ - Configure read permissions for region n. Write '0' has no effect. + Configure read permissions for region n. Writing a '0' has no effect. 2 2 Enable - Allow read instructions to region n + Allow read instructions to region n. 0 Disable - Block read instructions to region n + Block read instructions to region n. 1 @@ -41516,7 +41618,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH0 - Channel 0 enable set register. Writing '0' has no effect + Channel 0 enable set register. Writing '0' has no effect. 0 0 @@ -41543,7 +41645,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH1 - Channel 1 enable set register. Writing '0' has no effect + Channel 1 enable set register. Writing '0' has no effect. 1 1 @@ -41570,7 +41672,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH2 - Channel 2 enable set register. Writing '0' has no effect + Channel 2 enable set register. Writing '0' has no effect. 2 2 @@ -41597,7 +41699,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH3 - Channel 3 enable set register. Writing '0' has no effect + Channel 3 enable set register. Writing '0' has no effect. 3 3 @@ -41624,7 +41726,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH4 - Channel 4 enable set register. Writing '0' has no effect + Channel 4 enable set register. Writing '0' has no effect. 4 4 @@ -41651,7 +41753,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH5 - Channel 5 enable set register. Writing '0' has no effect + Channel 5 enable set register. Writing '0' has no effect. 5 5 @@ -41678,7 +41780,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH6 - Channel 6 enable set register. Writing '0' has no effect + Channel 6 enable set register. Writing '0' has no effect. 6 6 @@ -41705,7 +41807,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH7 - Channel 7 enable set register. Writing '0' has no effect + Channel 7 enable set register. Writing '0' has no effect. 7 7 @@ -41732,7 +41834,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH8 - Channel 8 enable set register. Writing '0' has no effect + Channel 8 enable set register. Writing '0' has no effect. 8 8 @@ -41759,7 +41861,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH9 - Channel 9 enable set register. Writing '0' has no effect + Channel 9 enable set register. Writing '0' has no effect. 9 9 @@ -41786,7 +41888,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH10 - Channel 10 enable set register. Writing '0' has no effect + Channel 10 enable set register. Writing '0' has no effect. 10 10 @@ -41813,7 +41915,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH11 - Channel 11 enable set register. Writing '0' has no effect + Channel 11 enable set register. Writing '0' has no effect. 11 11 @@ -41840,7 +41942,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH12 - Channel 12 enable set register. Writing '0' has no effect + Channel 12 enable set register. Writing '0' has no effect. 12 12 @@ -41867,7 +41969,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH13 - Channel 13 enable set register. Writing '0' has no effect + Channel 13 enable set register. Writing '0' has no effect. 13 13 @@ -41894,7 +41996,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH14 - Channel 14 enable set register. Writing '0' has no effect + Channel 14 enable set register. Writing '0' has no effect. 14 14 @@ -41921,7 +42023,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH15 - Channel 15 enable set register. Writing '0' has no effect + Channel 15 enable set register. Writing '0' has no effect. 15 15 @@ -41948,7 +42050,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH16 - Channel 16 enable set register. Writing '0' has no effect + Channel 16 enable set register. Writing '0' has no effect. 16 16 @@ -41975,7 +42077,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH17 - Channel 17 enable set register. Writing '0' has no effect + Channel 17 enable set register. Writing '0' has no effect. 17 17 @@ -42002,7 +42104,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH18 - Channel 18 enable set register. Writing '0' has no effect + Channel 18 enable set register. Writing '0' has no effect. 18 18 @@ -42029,7 +42131,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH19 - Channel 19 enable set register. Writing '0' has no effect + Channel 19 enable set register. Writing '0' has no effect. 19 19 @@ -42056,7 +42158,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH20 - Channel 20 enable set register. Writing '0' has no effect + Channel 20 enable set register. Writing '0' has no effect. 20 20 @@ -42083,7 +42185,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH21 - Channel 21 enable set register. Writing '0' has no effect + Channel 21 enable set register. Writing '0' has no effect. 21 21 @@ -42110,7 +42212,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH22 - Channel 22 enable set register. Writing '0' has no effect + Channel 22 enable set register. Writing '0' has no effect. 22 22 @@ -42137,7 +42239,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH23 - Channel 23 enable set register. Writing '0' has no effect + Channel 23 enable set register. Writing '0' has no effect. 23 23 @@ -42164,7 +42266,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH24 - Channel 24 enable set register. Writing '0' has no effect + Channel 24 enable set register. Writing '0' has no effect. 24 24 @@ -42191,7 +42293,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH25 - Channel 25 enable set register. Writing '0' has no effect + Channel 25 enable set register. Writing '0' has no effect. 25 25 @@ -42218,7 +42320,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH26 - Channel 26 enable set register. Writing '0' has no effect + Channel 26 enable set register. Writing '0' has no effect. 26 26 @@ -42245,7 +42347,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH27 - Channel 27 enable set register. Writing '0' has no effect + Channel 27 enable set register. Writing '0' has no effect. 27 27 @@ -42272,7 +42374,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH28 - Channel 28 enable set register. Writing '0' has no effect + Channel 28 enable set register. Writing '0' has no effect. 28 28 @@ -42299,7 +42401,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH29 - Channel 29 enable set register. Writing '0' has no effect + Channel 29 enable set register. Writing '0' has no effect. 29 29 @@ -42326,7 +42428,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH30 - Channel 30 enable set register. Writing '0' has no effect + Channel 30 enable set register. Writing '0' has no effect. 30 30 @@ -42353,7 +42455,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH31 - Channel 31 enable set register. Writing '0' has no effect + Channel 31 enable set register. Writing '0' has no effect. 31 31 @@ -42389,7 +42491,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH0 - Channel 0 enable clear register. Writing '0' has no effect + Channel 0 enable clear register. Writing '0' has no effect. 0 0 @@ -42416,7 +42518,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH1 - Channel 1 enable clear register. Writing '0' has no effect + Channel 1 enable clear register. Writing '0' has no effect. 1 1 @@ -42443,7 +42545,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH2 - Channel 2 enable clear register. Writing '0' has no effect + Channel 2 enable clear register. Writing '0' has no effect. 2 2 @@ -42470,7 +42572,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH3 - Channel 3 enable clear register. Writing '0' has no effect + Channel 3 enable clear register. Writing '0' has no effect. 3 3 @@ -42497,7 +42599,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH4 - Channel 4 enable clear register. Writing '0' has no effect + Channel 4 enable clear register. Writing '0' has no effect. 4 4 @@ -42524,7 +42626,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH5 - Channel 5 enable clear register. Writing '0' has no effect + Channel 5 enable clear register. Writing '0' has no effect. 5 5 @@ -42551,7 +42653,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH6 - Channel 6 enable clear register. Writing '0' has no effect + Channel 6 enable clear register. Writing '0' has no effect. 6 6 @@ -42578,7 +42680,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH7 - Channel 7 enable clear register. Writing '0' has no effect + Channel 7 enable clear register. Writing '0' has no effect. 7 7 @@ -42605,7 +42707,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH8 - Channel 8 enable clear register. Writing '0' has no effect + Channel 8 enable clear register. Writing '0' has no effect. 8 8 @@ -42632,7 +42734,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH9 - Channel 9 enable clear register. Writing '0' has no effect + Channel 9 enable clear register. Writing '0' has no effect. 9 9 @@ -42659,7 +42761,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH10 - Channel 10 enable clear register. Writing '0' has no effect + Channel 10 enable clear register. Writing '0' has no effect. 10 10 @@ -42686,7 +42788,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH11 - Channel 11 enable clear register. Writing '0' has no effect + Channel 11 enable clear register. Writing '0' has no effect. 11 11 @@ -42713,7 +42815,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH12 - Channel 12 enable clear register. Writing '0' has no effect + Channel 12 enable clear register. Writing '0' has no effect. 12 12 @@ -42740,7 +42842,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH13 - Channel 13 enable clear register. Writing '0' has no effect + Channel 13 enable clear register. Writing '0' has no effect. 13 13 @@ -42767,7 +42869,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH14 - Channel 14 enable clear register. Writing '0' has no effect + Channel 14 enable clear register. Writing '0' has no effect. 14 14 @@ -42794,7 +42896,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH15 - Channel 15 enable clear register. Writing '0' has no effect + Channel 15 enable clear register. Writing '0' has no effect. 15 15 @@ -42821,7 +42923,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH16 - Channel 16 enable clear register. Writing '0' has no effect + Channel 16 enable clear register. Writing '0' has no effect. 16 16 @@ -42848,7 +42950,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH17 - Channel 17 enable clear register. Writing '0' has no effect + Channel 17 enable clear register. Writing '0' has no effect. 17 17 @@ -42875,7 +42977,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH18 - Channel 18 enable clear register. Writing '0' has no effect + Channel 18 enable clear register. Writing '0' has no effect. 18 18 @@ -42902,7 +43004,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH19 - Channel 19 enable clear register. Writing '0' has no effect + Channel 19 enable clear register. Writing '0' has no effect. 19 19 @@ -42929,7 +43031,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH20 - Channel 20 enable clear register. Writing '0' has no effect + Channel 20 enable clear register. Writing '0' has no effect. 20 20 @@ -42956,7 +43058,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH21 - Channel 21 enable clear register. Writing '0' has no effect + Channel 21 enable clear register. Writing '0' has no effect. 21 21 @@ -42983,7 +43085,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH22 - Channel 22 enable clear register. Writing '0' has no effect + Channel 22 enable clear register. Writing '0' has no effect. 22 22 @@ -43010,7 +43112,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH23 - Channel 23 enable clear register. Writing '0' has no effect + Channel 23 enable clear register. Writing '0' has no effect. 23 23 @@ -43037,7 +43139,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH24 - Channel 24 enable clear register. Writing '0' has no effect + Channel 24 enable clear register. Writing '0' has no effect. 24 24 @@ -43064,7 +43166,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH25 - Channel 25 enable clear register. Writing '0' has no effect + Channel 25 enable clear register. Writing '0' has no effect. 25 25 @@ -43091,7 +43193,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH26 - Channel 26 enable clear register. Writing '0' has no effect + Channel 26 enable clear register. Writing '0' has no effect. 26 26 @@ -43118,7 +43220,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH27 - Channel 27 enable clear register. Writing '0' has no effect + Channel 27 enable clear register. Writing '0' has no effect. 27 27 @@ -43145,7 +43247,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH28 - Channel 28 enable clear register. Writing '0' has no effect + Channel 28 enable clear register. Writing '0' has no effect. 28 28 @@ -43172,7 +43274,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH29 - Channel 29 enable clear register. Writing '0' has no effect + Channel 29 enable clear register. Writing '0' has no effect. 29 29 @@ -43199,7 +43301,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH30 - Channel 30 enable clear register. Writing '0' has no effect + Channel 30 enable clear register. Writing '0' has no effect. 30 30 @@ -43226,7 +43328,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH31 - Channel 31 enable clear register. Writing '0' has no effect + Channel 31 enable clear register. Writing '0' has no effect. 31 31 @@ -43263,7 +43365,7 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x510 EEP - Description cluster: Channel n event end-point + Description cluster: Channel n event endpoint 0x000 read-write @@ -43277,7 +43379,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TEP - Description cluster: Channel n task end-point + Description cluster: Channel n task endpoint 0x004 read-write @@ -43886,7 +43988,7 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x910 TEP - Description cluster: Channel n task end-point + Description cluster: Channel n task endpoint 0x000 read-write @@ -53713,7 +53815,7 @@ POSSIBILITY OF SUCH DAMAGE.\n OneDir - Full buffer dedicated to either iso IN or OUT + Full buffer dedicated to either ISO IN or OUT 0x0000 @@ -54022,4 +54124,4 @@ POSSIBILITY OF SUCH DAMAGE.\n - \ No newline at end of file + diff --git a/svd/nrf52840.svd b/svd/nrf52840.svd index e43e718..be41fab 100644 --- a/svd/nrf52840.svd +++ b/svd/nrf52840.svd @@ -6,50 +6,44 @@ nrf52840 nrf52 1 - nRF52840 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller + nRF52840 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller -Copyright (c) 2010 - 2018, Nordic Semiconductor ASA\n -\n -All rights reserved.\n -\n -Redistribution and use in source and binary forms, with or without modification,\n -are permitted provided that the following conditions are met:\n -\n -1. Redistributions of source code must retain the above copyright notice, this\n - list of conditions and the following disclaimer.\n -\n -2. Redistributions in binary form, except as embedded into a Nordic\n - Semiconductor ASA integrated circuit in a product or a software update for\n - such product, must reproduce the above copyright notice, this list of\n - conditions and the following disclaimer in the documentation and/or other\n - materials provided with the distribution.\n -\n -3. Neither the name of Nordic Semiconductor ASA nor the names of its\n - contributors may be used to endorse or promote products derived from this\n - software without specific prior written permission.\n -\n -4. This software, with or without modification, must only be used with a\n - Nordic Semiconductor ASA integrated circuit.\n -\n -5. Any software provided in binary form under this license must not be reverse\n - engineered, decompiled, modified and/or disassembled.\n -\n -THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS\n -OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES\n -OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE\n -DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\n -LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\n -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT\n -OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n - +Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + 8 32 32 0x00000000 0xFFFFFFFF + NRF_ CM4 r0p1 @@ -58,12 +52,11 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ 1 3 0 + 112 + 0 system_nrf52840 - NRF_ - 2048 - 2048 112 @@ -85,6 +78,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ 0x010 read-only 0xFFFFFFFF + 0x20 CODEPAGESIZE @@ -100,6 +94,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ 0x014 read-only 0xFFFFFFFF + 0x20 CODESIZE @@ -110,13 +105,14 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ - 2 + 0x2 0x4 DEVICEID[%s] - Description collection[n]: Device identifier + Description collection: Device identifier 0x060 read-only 0xFFFFFFFF + 0x20 DEVICEID @@ -127,13 +123,14 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ - 4 + 0x4 0x4 ER[%s] - Description collection[n]: Encryption root, word n + Description collection: Encryption root, word n 0x080 read-only 0xFFFFFFFF + 0x20 ER @@ -144,13 +141,14 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ - 4 + 0x4 0x4 IR[%s] - Description collection[n]: Identity Root, word n + Description collection: Identity Root, word n 0x090 read-only 0xFFFFFFFF + 0x20 IR @@ -166,6 +164,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ 0x0A0 read-only 0xFFFFFFFF + 0x20 DEVICEADDRTYPE @@ -176,25 +175,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Public Public address - 0 + 0x0 Random Random address - 1 + 0x1 - 2 + 0x2 0x4 DEVICEADDR[%s] - Description collection[n]: Device address n + Description collection: Device address n 0x0A4 read-only 0xFFFFFFFF + 0x20 DEVICEADDR @@ -208,6 +208,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ INFO Device info FICR_INFO + read-only 0x100 PART @@ -215,6 +216,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ 0x000 read-only 0x00052840 + 0x20 PART @@ -225,7 +227,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ N52840 nRF52840 - 0x52840 + 0x00052840 Unspecified @@ -238,58 +240,17 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ VARIANT - Build code (hardware version and production configuration) + Build code, last two letters of Package Variant and first two characters of Build Code, encoded in ASCII. 0x004 read-only 0xFFFFFFFF + 0x20 VARIANT - Build code (hardware version and production configuration). Encoded as ASCII. + For valid values see SoC revisions and variants. 0 31 - - - AAAA - AAAA - 0x41414141 - - - BAAA - BAAA - 0x42414141 - - - CAAA - CAAA - 0x43414141 - - - AABA - AABA - 0x41414241 - - - AABB - AABB - 0x41414242 - - - AACA - AACA - 0x41414341 - - - AAAB - AAAB - 0x41414142 - - - Unspecified - Unspecified - 0xFFFFFFFF - - @@ -299,6 +260,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ 0x008 read-only 0xFFFFFFFF + 0x20 PACKAGE @@ -308,8 +270,18 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ QI - QIxx - 73-pin aQFN - 0x2004 + QIxx - 7x7 73-pin aQFN + 0x00002004 + + + QF + QFxx - 6x6 48-pin QFN + 0x00002000 + + + CK + CKxx - 3.544 x 3.607 WLCSP + 0x00002005 Unspecified @@ -326,6 +298,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ 0x00C read-only 0xFFFFFFFF + 0x20 RAM @@ -335,28 +308,28 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ K16 - 16 kByte RAM - 0x10 + 16 kB RAM + 0x00000010 K32 - 32 kByte RAM - 0x20 + 32 kB RAM + 0x00000020 K64 - 64 kByte RAM - 0x40 + 64 kB RAM + 0x00000040 K128 - 128 kByte RAM - 0x80 + 128 kB RAM + 0x00000080 K256 - 256 kByte RAM - 0x100 + 256 kB RAM + 0x00000100 Unspecified @@ -373,6 +346,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ 0x010 read-only 0xFFFFFFFF + 0x20 FLASH @@ -382,28 +356,28 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ K128 - 128 kByte FLASH - 0x80 + 128 kB FLASH + 0x00000080 K256 - 256 kByte FLASH - 0x100 + 256 kB FLASH + 0x00000100 K512 - 512 kByte FLASH - 0x200 + 512 kB FLASH + 0x00000200 K1024 - 1 MByte FLASH - 0x400 + 1 MB FLASH + 0x00000400 K2048 - 2 MByte FLASH - 0x800 + 2 MB FLASH + 0x00000800 Unspecified @@ -414,23 +388,16 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ - - 3 - 0x4 - UNUSED8[%s] - Unspecified - 0x014 - read-write - - 3 + 0x3 0x4 PRODTEST[%s] - Description collection[n]: Production test signature n + Description collection: Production test signature n 0x350 read-only 0xFFFFFFFF + 0x20 PRODTEST @@ -456,13 +423,15 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ TEMP Registers storing factory TEMP module linearization coefficients FICR_TEMP + read-only 0x404 A0 Slope definition A0 0x000 read-only - 0xFFFFF320 + 0xFFFFFFFF + 0x20 A @@ -477,7 +446,8 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Slope definition A1 0x004 read-only - 0xFFFFF343 + 0xFFFFFFFF + 0x20 A @@ -492,7 +462,8 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Slope definition A2 0x008 read-only - 0xFFFFF35D + 0xFFFFFFFF + 0x20 A @@ -507,7 +478,8 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Slope definition A3 0x00C read-only - 0xFFFFF400 + 0xFFFFFFFF + 0x20 A @@ -522,7 +494,8 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Slope definition A4 0x010 read-only - 0xFFFFF452 + 0xFFFFFFFF + 0x20 A @@ -537,7 +510,8 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Slope definition A5 0x014 read-only - 0xFFFFF37B + 0xFFFFFFFF + 0x20 A @@ -552,7 +526,8 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Y-intercept B0 0x018 read-only - 0xFFFF3FCC + 0xFFFFFFFF + 0x20 B @@ -567,7 +542,8 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Y-intercept B1 0x01C read-only - 0xFFFF3F98 + 0xFFFFFFFF + 0x20 B @@ -582,7 +558,8 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Y-intercept B2 0x020 read-only - 0xFFFF3F98 + 0xFFFFFFFF + 0x20 B @@ -597,7 +574,8 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Y-intercept B3 0x024 read-only - 0xFFFF0012 + 0xFFFFFFFF + 0x20 B @@ -612,7 +590,8 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Y-intercept B4 0x028 read-only - 0xFFFF004D + 0xFFFFFFFF + 0x20 B @@ -627,7 +606,8 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Y-intercept B5 0x02C read-only - 0xFFFF3E10 + 0xFFFFFFFF + 0x20 B @@ -642,7 +622,8 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Segment end T0 0x030 read-only - 0xFFFFFFE2 + 0xFFFFFFFF + 0x20 T @@ -657,7 +638,8 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Segment end T1 0x034 read-only - 0xFFFFFF00 + 0xFFFFFFFF + 0x20 T @@ -672,7 +654,8 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Segment end T2 0x038 read-only - 0xFFFFFF14 + 0xFFFFFFFF + 0x20 T @@ -687,7 +670,8 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Segment end T3 0x03C read-only - 0xFFFFFF19 + 0xFFFFFFFF + 0x20 T @@ -702,7 +686,8 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Segment end T4 0x040 read-only - 0xFFFFFF50 + 0xFFFFFFFF + 0x20 T @@ -717,13 +702,15 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ NFC Unspecified FICR_NFC + read-write 0x450 TAGHEADER0 - Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. + Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. 0x000 read-only 0xFFFFFF5F + 0x20 MFGID @@ -753,10 +740,11 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ TAGHEADER1 - Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. + Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. 0x004 read-only 0xFFFFFFFF + 0x20 UD4 @@ -786,10 +774,11 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ TAGHEADER2 - Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. + Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. 0x008 read-only 0xFFFFFFFF + 0x20 UD8 @@ -819,10 +808,11 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ TAGHEADER3 - Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. + Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. 0x00C read-only 0xFFFFFFFF + 0x20 UD12 @@ -855,6 +845,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ TRNG90B NIST800-90B RNG calibration data FICR_TRNG90B + read-write 0xC00 BYTES @@ -862,6 +853,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ 0x000 read-only 0xFFFFFFFF + 0x20 BYTES @@ -877,6 +869,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ 0x004 read-only 0xFFFFFFFF + 0x20 RCCUTOFF @@ -892,6 +885,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ 0x008 read-only 0xFFFFFFFF + 0x20 APCUTOFF @@ -906,7 +900,8 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Amount of bytes for the startup tests 0x00C read-only - 0x00000210 + 0xFFFFFFFF + 0x20 STARTUP @@ -922,6 +917,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ 0x010 read-only 0xFFFFFFFF + 0x20 ROSC1 @@ -937,6 +933,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ 0x014 read-only 0xFFFFFFFF + 0x20 ROSC2 @@ -952,6 +949,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ 0x018 read-only 0xFFFFFFFF + 0x20 ROSC3 @@ -967,6 +965,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ 0x01C read-only 0xFFFFFFFF + 0x20 ROSC4 @@ -992,37 +991,14 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ 0x20 - UNUSED0 - Unspecified - 0x000 - read-write - - - UNUSED1 - Unspecified - 0x004 - read-write - - - UNUSED2 - Unspecified - 0x008 - read-write - - - UNUSED3 - Unspecified - 0x010 - read-write - - - 15 + 0xD 0x4 NRFFW[%s] - Description collection[n]: Reserved for Nordic firmware design + Description collection: Reserved for Nordic firmware design 0x014 read-write 0xFFFFFFFF + 0x20 NRFFW @@ -1033,13 +1009,14 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ - 12 + 0xC 0x4 NRFHW[%s] - Description collection[n]: Reserved for Nordic hardware design + Description collection: Reserved for Nordic hardware design 0x050 read-write 0xFFFFFFFF + 0x20 NRFHW @@ -1050,13 +1027,14 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ - 32 + 0x20 0x4 CUSTOMER[%s] - Description collection[n]: Reserved for customer + Description collection: Reserved for customer 0x080 read-write 0xFFFFFFFF + 0x20 CUSTOMER @@ -1067,17 +1045,18 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ - 2 + 0x2 0x4 PSELRESET[%s] - Description collection[n]: Mapping of the nRESET function + Description collection: Mapping of the nRESET function (see POWER chapter for details) 0x200 read-write 0xFFFFFFFF + 0x20 PIN - Pin number of PORT onto which nRESET is exposed + GPIO pin number onto which nRESET is exposed 0 4 @@ -1096,12 +1075,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disconnected Disconnect - 1 + 0x1 Connected Connect - 0 + 0x0 @@ -1113,6 +1092,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ 0x208 read-write 0xFFFFFFFF + 0x20 PALL @@ -1122,9 +1102,14 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled - Disable + Hardware disable of access port protection for devices where access port protection is controlled by hardware 0xFF + + HwDisabled + Hardware disable of access port protection for devices where access port protection is controlled by hardware and software + 0x5A + Enabled Enable @@ -1140,6 +1125,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ 0x20C read-write 0xFFFFFFFF + 0x20 PROTECT @@ -1149,13 +1135,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled - Operation as GPIO pins. Same protection as normal GPIO pins - 0 + Operation as GPIO pins. Same protection as normal GPIO pins. + 0x0 NFC - Operation as NFC antenna pins. Configures the protection for NFC operation - 1 + Operation as NFC antenna pins. Configures the protection for NFC operation. + 0x1 @@ -1167,6 +1153,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ 0x210 read-write 0xFFFFFFFF + 0x20 CPUNIDEN @@ -1208,51 +1195,113 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ REGOUT0 - GPIO reference voltage / external output supply voltage in high voltage mode + Output voltage from REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - V_VDDH-VDD. 0x304 read-write 0xFFFFFFFF + 0x20 VOUT - Output voltage from of REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - VEXDIF. + Output voltage from REG0 regulator stage. 0 2 1V8 1.8 V - 0 + 0x0 2V1 2.1 V - 1 + 0x1 2V4 2.4 V - 2 + 0x2 2V7 2.7 V - 3 + 0x3 3V0 3.0 V - 4 + 0x4 3V3 3.3 V - 5 + 0x5 DEFAULT Default voltage: 1.8 V - 7 + 0x7 + + + + + + + + + APPROTECT + Access Port Protection + 0x40000000 + + 0 + 0x1000 + registers + + APPROTECT + 0x20 + + + FORCEPROTECT + Software force enable APPROTECT mechanism until next reset. + 0x550 + read-writeOnce + 0xFFFFFFFF + 0x20 + + + FORCEPROTECT + Write 0x0 to force enable APPROTECT mechanism + 0 + 7 + + write + + Force + Software force enable APPROTECT mechanism + 0x00 + + + + + + + DISABLE + Software disable APPROTECT mechanism + 0x558 + read-write + 0x00000000 + 0x20 + + + DISABLE + Software disable APPROTECT mechanism + 0 + 7 + + + SwDisable + Software disable APPROTECT mechanism + 0x5A @@ -1264,13 +1313,14 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ CLOCK Clock control 0x40000000 + APPROTECT 0 0x1000 registers - POWER_CLOCK + CLOCK_POWER 0 CLOCK @@ -1281,11 +1331,21 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Start HFXO crystal oscillator 0x000 write-only + 0x00000000 + 0x20 TASKS_HFCLKSTART + Start HFXO crystal oscillator 0 0 + + + Trigger + Trigger task + 0x1 + + @@ -1294,11 +1354,21 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Stop HFXO crystal oscillator 0x004 write-only + 0x00000000 + 0x20 TASKS_HFCLKSTOP + Stop HFXO crystal oscillator 0 0 + + + Trigger + Trigger task + 0x1 + + @@ -1307,11 +1377,21 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Start LFCLK 0x008 write-only + 0x00000000 + 0x20 TASKS_LFCLKSTART + Start LFCLK 0 0 + + + Trigger + Trigger task + 0x1 + + @@ -1320,11 +1400,21 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Stop LFCLK 0x00C write-only + 0x00000000 + 0x20 TASKS_LFCLKSTOP + Stop LFCLK 0 0 + + + Trigger + Trigger task + 0x1 + + @@ -1333,11 +1423,21 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Start calibration of LFRC 0x010 write-only + 0x00000000 + 0x20 TASKS_CAL + Start calibration of LFRC 0 0 + + + Trigger + Trigger task + 0x1 + + @@ -1346,11 +1446,21 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Start calibration timer 0x014 write-only + 0x00000000 + 0x20 TASKS_CTSTART + Start calibration timer 0 0 + + + Trigger + Trigger task + 0x1 + + @@ -1359,11 +1469,21 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Stop calibration timer 0x018 write-only + 0x00000000 + 0x20 TASKS_CTSTOP + Stop calibration timer 0 0 + + + Trigger + Trigger task + 0x1 + + @@ -1372,11 +1492,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ HFXO crystal oscillator started 0x100 read-write + 0x00000000 + 0x20 EVENTS_HFCLKSTARTED + HFXO crystal oscillator started 0 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + @@ -1385,11 +1520,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ LFCLK started 0x104 read-write + 0x00000000 + 0x20 EVENTS_LFCLKSTARTED + LFCLK started 0 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + @@ -1398,11 +1548,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Calibration of LFRC completed 0x10C read-write + 0x00000000 + 0x20 EVENTS_DONE + Calibration of LFRC completed 0 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + @@ -1411,11 +1576,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Calibration timer timeout 0x110 read-write + 0x00000000 + 0x20 EVENTS_CTTO + Calibration timer timeout 0 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + @@ -1424,11 +1604,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Calibration timer has been started and is ready to process new tasks 0x128 read-write + 0x00000000 + 0x20 EVENTS_CTSTARTED + Calibration timer has been started and is ready to process new tasks 0 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + @@ -1437,11 +1632,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Calibration timer has been stopped and is ready to process new tasks 0x12C read-write + 0x00000000 + 0x20 EVENTS_CTSTOPPED + Calibration timer has been stopped and is ready to process new tasks 0 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + @@ -1450,10 +1660,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Enable interrupt 0x304 read-write + 0x00000000 + 0x20 HFCLKSTARTED - Write '1' to enable interrupt for HFCLKSTARTED event + Write '1' to enable interrupt for event HFCLKSTARTED 0 0 @@ -1461,12 +1673,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -1474,13 +1686,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 LFCLKSTARTED - Write '1' to enable interrupt for LFCLKSTARTED event + Write '1' to enable interrupt for event LFCLKSTARTED 1 1 @@ -1488,12 +1700,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -1501,13 +1713,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 DONE - Write '1' to enable interrupt for DONE event + Write '1' to enable interrupt for event DONE 3 3 @@ -1515,12 +1727,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -1528,13 +1740,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 CTTO - Write '1' to enable interrupt for CTTO event + Write '1' to enable interrupt for event CTTO 4 4 @@ -1542,12 +1754,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -1555,13 +1767,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 CTSTARTED - Write '1' to enable interrupt for CTSTARTED event + Write '1' to enable interrupt for event CTSTARTED 10 10 @@ -1569,12 +1781,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -1582,13 +1794,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 CTSTOPPED - Write '1' to enable interrupt for CTSTOPPED event + Write '1' to enable interrupt for event CTSTOPPED 11 11 @@ -1596,12 +1808,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -1609,7 +1821,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 @@ -1620,10 +1832,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disable interrupt 0x308 read-write + 0x00000000 + 0x20 HFCLKSTARTED - Write '1' to disable interrupt for HFCLKSTARTED event + Write '1' to disable interrupt for event HFCLKSTARTED 0 0 @@ -1631,12 +1845,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -1644,13 +1858,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 LFCLKSTARTED - Write '1' to disable interrupt for LFCLKSTARTED event + Write '1' to disable interrupt for event LFCLKSTARTED 1 1 @@ -1658,12 +1872,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -1671,13 +1885,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 DONE - Write '1' to disable interrupt for DONE event + Write '1' to disable interrupt for event DONE 3 3 @@ -1685,12 +1899,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -1698,13 +1912,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 CTTO - Write '1' to disable interrupt for CTTO event + Write '1' to disable interrupt for event CTTO 4 4 @@ -1712,12 +1926,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -1725,13 +1939,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 CTSTARTED - Write '1' to disable interrupt for CTSTARTED event + Write '1' to disable interrupt for event CTSTARTED 10 10 @@ -1739,12 +1953,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -1752,13 +1966,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 CTSTOPPED - Write '1' to disable interrupt for CTSTOPPED event + Write '1' to disable interrupt for event CTSTOPPED 11 11 @@ -1766,12 +1980,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -1779,7 +1993,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 @@ -1790,6 +2004,8 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Status indicating that HFCLKSTART task has been triggered 0x408 read-only + 0x00000000 + 0x20 STATUS @@ -1800,12 +2016,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ NotTriggered Task not triggered - 0 + 0x0 Triggered Task triggered - 1 + 0x1 @@ -1816,6 +2032,8 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ HFCLK status 0x40C read-only + 0x00000000 + 0x20 SRC @@ -1826,12 +2044,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ RC 64 MHz internal oscillator (HFINT) - 0 + 0x0 Xtal 64 MHz crystal oscillator (HFXO) - 1 + 0x1 @@ -1844,12 +2062,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ NotRunning HFCLK not running - 0 + 0x0 Running HFCLK running - 1 + 0x1 @@ -1860,6 +2078,8 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Status indicating that LFCLKSTART task has been triggered 0x414 read-only + 0x00000000 + 0x20 STATUS @@ -1870,12 +2090,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ NotTriggered Task not triggered - 0 + 0x0 Triggered Task triggered - 1 + 0x1 @@ -1886,6 +2106,8 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ LFCLK status 0x418 read-only + 0x00000000 + 0x20 SRC @@ -1896,17 +2118,17 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ RC 32.768 kHz RC oscillator (LFRC) - 0 + 0x0 Xtal 32.768 kHz crystal oscillator (LFXO) - 1 + 0x1 Synth 32.768 kHz synthesized from HFCLK (LFSYNT) - 2 + 0x2 @@ -1919,12 +2141,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ NotRunning LFCLK not running - 0 + 0x0 Running LFCLK running - 1 + 0x1 @@ -1935,6 +2157,8 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Copy of LFCLKSRC register, set when LFCLKSTART task was triggered 0x41C read-only + 0x00000000 + 0x20 SRC @@ -1945,17 +2169,17 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ RC 32.768 kHz RC oscillator (LFRC) - 0 + 0x0 Xtal 32.768 kHz crystal oscillator (LFXO) - 1 + 0x1 Synth 32.768 kHz synthesized from HFCLK (LFSYNT) - 2 + 0x2 @@ -1966,6 +2190,8 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clock source for the LFCLK 0x518 read-write + 0x00000000 + 0x20 SRC @@ -1976,17 +2202,17 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ RC 32.768 kHz RC oscillator (LFRC) - 0 + 0x0 Xtal 32.768 kHz crystal oscillator (LFXO) - 1 + 0x1 Synth 32.768 kHz synthesized from HFCLK (LFSYNT) - 2 + 0x2 @@ -1999,12 +2225,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Disable (use with Xtal or low-swing external source) - 0 + 0x0 Enabled Enable (use with rail-to-rail external source) - 1 + 0x1 @@ -2017,12 +2243,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Disable external source (use with Xtal) - 0 + 0x0 Enabled Enable use of external source instead of Xtal (SRC needs to be set to Xtal) - 1 + 0x1 @@ -2034,6 +2260,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ 0x528 read-write 0x00000010 + 0x20 HFXODEBOUNCE @@ -2060,6 +2287,8 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Calibration timer interval 0x538 read-write + 0x00000000 + 0x20 CTIV @@ -2075,6 +2304,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ 0x55C read-write 0x00000000 + 0x20 TRACEPORTSPEED @@ -2085,22 +2315,22 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ 32MHz 32 MHz trace port clock (TRACECLK = 16 MHz) - 0 + 0x0 16MHz 16 MHz trace port clock (TRACECLK = 8 MHz) - 1 + 0x1 8MHz 8 MHz trace port clock (TRACECLK = 4 MHz) - 2 + 0x2 4MHz 4 MHz trace port clock (TRACECLK = 2 MHz) - 3 + 0x3 @@ -2113,17 +2343,17 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ GPIO No trace signals routed to pins. All pins can be used as regular GPIOs. - 0 + 0x0 Serial SWO trace signal routed to pin. Remaining pins can be used as regular GPIOs. - 1 + 0x1 Parallel All trace signals (TRACECLK and TRACEDATA[n]) routed to pins. - 2 + 0x2 @@ -2135,6 +2365,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ 0x5B4 read-write 0x00000000 + 0x20 MODE @@ -2145,12 +2376,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Normal Normal mode - 0 + 0x0 ULP Ultra-low power mode (ULP) - 1 + 0x1 @@ -2163,12 +2394,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Normal Normal mode - 0 + 0x0 ULP Ultra-low power mode (ULP) - 1 + 0x1 @@ -2180,14 +2411,14 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ POWER Power control 0x40000000 - CLOCK + APPROTECT 0 0x1000 registers - POWER_CLOCK + CLOCK_POWER 0 POWER @@ -2195,27 +2426,47 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ TASKS_CONSTLAT - Enable constant latency mode + Enable Constant Latency mode 0x78 write-only + 0x00000000 + 0x20 TASKS_CONSTLAT + Enable Constant Latency mode 0 0 + + + Trigger + Trigger task + 0x1 + + TASKS_LOWPWR - Enable low power mode (variable latency) + Enable Low-power mode (variable latency) 0x7C write-only + 0x00000000 + 0x20 TASKS_LOWPWR + Enable Low-power mode (variable latency) 0 0 + + + Trigger + Trigger task + 0x1 + + @@ -2224,11 +2475,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Power failure warning 0x108 read-write + 0x00000000 + 0x20 EVENTS_POFWARN + Power failure warning 0 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + @@ -2237,11 +2503,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ CPU entered WFI/WFE sleep 0x114 read-write + 0x00000000 + 0x20 EVENTS_SLEEPENTER + CPU entered WFI/WFE sleep 0 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + @@ -2250,11 +2531,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ CPU exited WFI/WFE sleep 0x118 read-write + 0x00000000 + 0x20 EVENTS_SLEEPEXIT + CPU exited WFI/WFE sleep 0 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + @@ -2263,11 +2559,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Voltage supply detected on VBUS 0x11C read-write + 0x00000000 + 0x20 EVENTS_USBDETECTED + Voltage supply detected on VBUS 0 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + @@ -2276,11 +2587,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Voltage supply removed from VBUS 0x120 read-write + 0x00000000 + 0x20 EVENTS_USBREMOVED + Voltage supply removed from VBUS 0 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + @@ -2289,11 +2615,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ USB 3.3 V supply ready 0x124 read-write + 0x00000000 + 0x20 EVENTS_USBPWRRDY + USB 3.3 V supply ready 0 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + @@ -2302,10 +2643,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Enable interrupt 0x304 read-write + 0x00000000 + 0x20 POFWARN - Write '1' to enable interrupt for POFWARN event + Write '1' to enable interrupt for event POFWARN 2 2 @@ -2313,12 +2656,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -2326,13 +2669,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 SLEEPENTER - Write '1' to enable interrupt for SLEEPENTER event + Write '1' to enable interrupt for event SLEEPENTER 5 5 @@ -2340,12 +2683,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -2353,13 +2696,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 SLEEPEXIT - Write '1' to enable interrupt for SLEEPEXIT event + Write '1' to enable interrupt for event SLEEPEXIT 6 6 @@ -2367,12 +2710,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -2380,13 +2723,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 USBDETECTED - Write '1' to enable interrupt for USBDETECTED event + Write '1' to enable interrupt for event USBDETECTED 7 7 @@ -2394,12 +2737,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -2407,13 +2750,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 USBREMOVED - Write '1' to enable interrupt for USBREMOVED event + Write '1' to enable interrupt for event USBREMOVED 8 8 @@ -2421,12 +2764,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -2434,13 +2777,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 USBPWRRDY - Write '1' to enable interrupt for USBPWRRDY event + Write '1' to enable interrupt for event USBPWRRDY 9 9 @@ -2448,12 +2791,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -2461,7 +2804,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 @@ -2472,10 +2815,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disable interrupt 0x308 read-write + 0x00000000 + 0x20 POFWARN - Write '1' to disable interrupt for POFWARN event + Write '1' to disable interrupt for event POFWARN 2 2 @@ -2483,12 +2828,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -2496,13 +2841,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 SLEEPENTER - Write '1' to disable interrupt for SLEEPENTER event + Write '1' to disable interrupt for event SLEEPENTER 5 5 @@ -2510,12 +2855,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -2523,13 +2868,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 SLEEPEXIT - Write '1' to disable interrupt for SLEEPEXIT event + Write '1' to disable interrupt for event SLEEPEXIT 6 6 @@ -2537,12 +2882,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -2550,13 +2895,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 USBDETECTED - Write '1' to disable interrupt for USBDETECTED event + Write '1' to disable interrupt for event USBDETECTED 7 7 @@ -2564,12 +2909,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -2577,13 +2922,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 USBREMOVED - Write '1' to disable interrupt for USBREMOVED event + Write '1' to disable interrupt for event USBREMOVED 8 8 @@ -2591,12 +2936,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -2604,13 +2949,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 USBPWRRDY - Write '1' to disable interrupt for USBPWRRDY event + Write '1' to disable interrupt for event USBPWRRDY 9 9 @@ -2618,12 +2963,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -2631,7 +2976,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 @@ -2642,6 +2987,8 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Reset reason 0x400 read-write + 0x00000000 + 0x20 RESETPIN @@ -2652,12 +2999,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ NotDetected Not detected - 0 + 0x0 Detected Detected - 1 + 0x1 @@ -2670,12 +3017,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ NotDetected Not detected - 0 + 0x0 Detected Detected - 1 + 0x1 @@ -2688,12 +3035,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ NotDetected Not detected - 0 + 0x0 Detected Detected - 1 + 0x1 @@ -2706,12 +3053,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ NotDetected Not detected - 0 + 0x0 Detected Detected - 1 + 0x1 @@ -2724,12 +3071,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ NotDetected Not detected - 0 + 0x0 Detected Detected - 1 + 0x1 @@ -2742,12 +3089,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ NotDetected Not detected - 0 + 0x0 Detected Detected - 1 + 0x1 @@ -2760,12 +3107,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ NotDetected Not detected - 0 + 0x0 Detected Detected - 1 + 0x1 @@ -2778,12 +3125,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ NotDetected Not detected - 0 + 0x0 Detected Detected - 1 + 0x1 @@ -2796,12 +3143,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ NotDetected Not detected - 0 + 0x0 Detected Detected - 1 + 0x1 @@ -2813,6 +3160,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ 0x428 read-only 0x00000000 + 0x20 RAMBLOCK0 @@ -2823,12 +3171,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 0 + 0x0 On On - 1 + 0x1 @@ -2841,12 +3189,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 0 + 0x0 On On - 1 + 0x1 @@ -2859,12 +3207,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 0 + 0x0 On On - 1 + 0x1 @@ -2877,12 +3225,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 0 + 0x0 On On - 1 + 0x1 @@ -2894,6 +3242,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ 0x438 read-only 0x00000000 + 0x20 VBUSDETECT @@ -2904,12 +3253,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ NoVbus VBUS voltage below valid threshold - 0 + 0x0 VbusPresent VBUS voltage above valid threshold - 1 + 0x1 @@ -2922,12 +3271,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ NotReady USBREG output settling time not elapsed - 0 + 0x0 Ready USBREG output settling time elapsed (same information as USBPWRRDY event) - 1 + 0x1 @@ -2938,6 +3287,8 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ System OFF register 0x500 write-only + 0x00000000 + 0x20 SYSTEMOFF @@ -2948,7 +3299,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Enter Enable System OFF mode - 1 + 0x1 @@ -2959,6 +3310,8 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Power-fail comparator configuration 0x510 read-write + 0x00000000 + 0x20 POF @@ -2969,12 +3322,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -2987,62 +3340,62 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ V17 Set threshold to 1.7 V - 4 + 0x4 V18 Set threshold to 1.8 V - 5 + 0x5 V19 Set threshold to 1.9 V - 6 + 0x6 V20 Set threshold to 2.0 V - 7 + 0x7 V21 Set threshold to 2.1 V - 8 + 0x8 V22 Set threshold to 2.2 V - 9 + 0x9 V23 Set threshold to 2.3 V - 10 + 0xA V24 Set threshold to 2.4 V - 11 + 0xB V25 Set threshold to 2.5 V - 12 + 0xC V26 Set threshold to 2.6 V - 13 + 0xD V27 Set threshold to 2.7 V - 14 + 0xE V28 Set threshold to 2.8 V - 15 + 0xF @@ -3055,82 +3408,82 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ V27 Set threshold to 2.7 V - 0 + 0x0 V28 Set threshold to 2.8 V - 1 + 0x1 V29 Set threshold to 2.9 V - 2 + 0x2 V30 Set threshold to 3.0 V - 3 + 0x3 V31 Set threshold to 3.1 V - 4 + 0x4 V32 Set threshold to 3.2 V - 5 + 0x5 V33 Set threshold to 3.3 V - 6 + 0x6 V34 Set threshold to 3.4 V - 7 + 0x7 V35 Set threshold to 3.5 V - 8 + 0x8 V36 Set threshold to 3.6 V - 9 + 0x9 V37 Set threshold to 3.7 V - 10 + 0xA V38 Set threshold to 3.8 V - 11 + 0xB V39 Set threshold to 3.9 V - 12 + 0xC V40 Set threshold to 4.0 V - 13 + 0xD V41 Set threshold to 4.1 V - 14 + 0xE V42 Set threshold to 4.2 V - 15 + 0xF @@ -3141,6 +3494,8 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ General purpose retention register 0x51C read-write + 0x00000000 + 0x20 GPREGRET @@ -3155,6 +3510,8 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ General purpose retention register 0x520 read-write + 0x00000000 + 0x20 GPREGRET @@ -3166,9 +3523,11 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ DCDCEN - Enable DC/DC converter for REG1 stage. + Enable DC/DC converter for REG1 stage 0x578 read-write + 0x00000000 + 0x20 DCDCEN @@ -3179,12 +3538,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -3192,9 +3551,11 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ DCDCEN0 - Enable DC/DC converter for REG0 stage. + Enable DC/DC converter for REG0 stage 0x580 read-write + 0x00000000 + 0x20 DCDCEN @@ -3205,12 +3566,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -3222,6 +3583,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ 0x640 read-only 0x00000000 + 0x20 MAINREGSTATUS @@ -3232,12 +3594,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Normal Normal voltage mode. Voltage supplied on VDD. - 0 + 0x0 High High voltage mode. Voltage supplied on VDDH. - 1 + 0x1 @@ -3249,13 +3611,15 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ RAM[%s] Unspecified POWER_RAM + read-write 0x900 POWER - Description cluster[n]: RAMn power control register + Description cluster: RAMn power control register 0x000 read-write 0x0000FFFF + 0x20 S0POWER @@ -3266,12 +3630,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 0 + 0x0 On On - 1 + 0x1 @@ -3284,12 +3648,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 0 + 0x0 On On - 1 + 0x1 @@ -3302,12 +3666,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 0 + 0x0 On On - 1 + 0x1 @@ -3320,12 +3684,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 0 + 0x0 On On - 1 + 0x1 @@ -3338,12 +3702,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 0 + 0x0 On On - 1 + 0x1 @@ -3356,12 +3720,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 0 + 0x0 On On - 1 + 0x1 @@ -3374,12 +3738,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 0 + 0x0 On On - 1 + 0x1 @@ -3392,12 +3756,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 0 + 0x0 On On - 1 + 0x1 @@ -3410,12 +3774,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 0 + 0x0 On On - 1 + 0x1 @@ -3428,12 +3792,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 0 + 0x0 On On - 1 + 0x1 @@ -3446,12 +3810,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 0 + 0x0 On On - 1 + 0x1 @@ -3464,12 +3828,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 0 + 0x0 On On - 1 + 0x1 @@ -3482,12 +3846,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 0 + 0x0 On On - 1 + 0x1 @@ -3500,12 +3864,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 0 + 0x0 On On - 1 + 0x1 @@ -3518,12 +3882,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 0 + 0x0 On On - 1 + 0x1 @@ -3536,12 +3900,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 0 + 0x0 On On - 1 + 0x1 @@ -3554,12 +3918,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 0 + 0x0 On On - 1 + 0x1 @@ -3572,12 +3936,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 0 + 0x0 On On - 1 + 0x1 @@ -3590,12 +3954,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 0 + 0x0 On On - 1 + 0x1 @@ -3608,12 +3972,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 0 + 0x0 On On - 1 + 0x1 @@ -3626,12 +3990,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 0 + 0x0 On On - 1 + 0x1 @@ -3644,12 +4008,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 0 + 0x0 On On - 1 + 0x1 @@ -3662,12 +4026,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 0 + 0x0 On On - 1 + 0x1 @@ -3680,12 +4044,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 0 + 0x0 On On - 1 + 0x1 @@ -3698,12 +4062,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 0 + 0x0 On On - 1 + 0x1 @@ -3716,12 +4080,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 0 + 0x0 On On - 1 + 0x1 @@ -3734,12 +4098,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 0 + 0x0 On On - 1 + 0x1 @@ -3752,12 +4116,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 0 + 0x0 On On - 1 + 0x1 @@ -3770,12 +4134,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 0 + 0x0 On On - 1 + 0x1 @@ -3788,12 +4152,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 0 + 0x0 On On - 1 + 0x1 @@ -3806,12 +4170,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 0 + 0x0 On On - 1 + 0x1 @@ -3824,12 +4188,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 0 + 0x0 On On - 1 + 0x1 @@ -3837,10 +4201,11 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ POWERSET - Description cluster[n]: RAMn power control set register + Description cluster: RAMn power control set register 0x004 write-only 0x0000FFFF + 0x20 S0POWER @@ -3851,7 +4216,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ On On - 1 + 0x1 @@ -3864,7 +4229,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ On On - 1 + 0x1 @@ -3877,7 +4242,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ On On - 1 + 0x1 @@ -3890,7 +4255,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ On On - 1 + 0x1 @@ -3903,7 +4268,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ On On - 1 + 0x1 @@ -3916,7 +4281,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ On On - 1 + 0x1 @@ -3929,7 +4294,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ On On - 1 + 0x1 @@ -3942,7 +4307,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ On On - 1 + 0x1 @@ -3955,7 +4320,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ On On - 1 + 0x1 @@ -3968,7 +4333,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ On On - 1 + 0x1 @@ -3981,7 +4346,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ On On - 1 + 0x1 @@ -3994,7 +4359,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ On On - 1 + 0x1 @@ -4007,7 +4372,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ On On - 1 + 0x1 @@ -4020,7 +4385,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ On On - 1 + 0x1 @@ -4033,7 +4398,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ On On - 1 + 0x1 @@ -4046,7 +4411,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ On On - 1 + 0x1 @@ -4059,7 +4424,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ On On - 1 + 0x1 @@ -4072,7 +4437,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ On On - 1 + 0x1 @@ -4085,7 +4450,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ On On - 1 + 0x1 @@ -4098,7 +4463,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ On On - 1 + 0x1 @@ -4111,7 +4476,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ On On - 1 + 0x1 @@ -4124,7 +4489,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ On On - 1 + 0x1 @@ -4137,7 +4502,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ On On - 1 + 0x1 @@ -4150,7 +4515,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ On On - 1 + 0x1 @@ -4163,7 +4528,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ On On - 1 + 0x1 @@ -4176,7 +4541,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ On On - 1 + 0x1 @@ -4189,7 +4554,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ On On - 1 + 0x1 @@ -4202,7 +4567,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ On On - 1 + 0x1 @@ -4215,7 +4580,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ On On - 1 + 0x1 @@ -4228,7 +4593,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ On On - 1 + 0x1 @@ -4241,7 +4606,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ On On - 1 + 0x1 @@ -4254,7 +4619,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ On On - 1 + 0x1 @@ -4262,10 +4627,11 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ POWERCLR - Description cluster[n]: RAMn power control clear register + Description cluster: RAMn power control clear register 0x008 write-only 0x0000FFFF + 0x20 S0POWER @@ -4276,7 +4642,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 1 + 0x1 @@ -4289,7 +4655,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 1 + 0x1 @@ -4302,7 +4668,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 1 + 0x1 @@ -4315,7 +4681,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 1 + 0x1 @@ -4328,7 +4694,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 1 + 0x1 @@ -4341,7 +4707,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 1 + 0x1 @@ -4354,7 +4720,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 1 + 0x1 @@ -4367,7 +4733,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 1 + 0x1 @@ -4380,7 +4746,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 1 + 0x1 @@ -4393,7 +4759,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 1 + 0x1 @@ -4406,7 +4772,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 1 + 0x1 @@ -4419,7 +4785,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 1 + 0x1 @@ -4432,7 +4798,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 1 + 0x1 @@ -4445,7 +4811,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 1 + 0x1 @@ -4458,7 +4824,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 1 + 0x1 @@ -4471,7 +4837,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 1 + 0x1 @@ -4484,7 +4850,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 1 + 0x1 @@ -4497,7 +4863,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 1 + 0x1 @@ -4510,7 +4876,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 1 + 0x1 @@ -4523,7 +4889,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 1 + 0x1 @@ -4536,7 +4902,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 1 + 0x1 @@ -4549,7 +4915,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 1 + 0x1 @@ -4562,7 +4928,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 1 + 0x1 @@ -4575,7 +4941,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 1 + 0x1 @@ -4588,7 +4954,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 1 + 0x1 @@ -4601,7 +4967,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 1 + 0x1 @@ -4614,7 +4980,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 1 + 0x1 @@ -4627,7 +4993,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 1 + 0x1 @@ -4640,7 +5006,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 1 + 0x1 @@ -4653,7 +5019,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 1 + 0x1 @@ -4666,7 +5032,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 1 + 0x1 @@ -4679,7 +5045,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Off Off - 1 + 0x1 @@ -4689,8466 +5055,7389 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ - RADIO - 2.4 GHz radio - 0x40001000 + P0 + GPIO Port 0 + 0x50000000 + GPIO 0 0x1000 registers - - RADIO - 1 - - RADIO + GPIO 0x20 - TASKS_TXEN - Enable RADIO in TX mode - 0x000 - write-only + OUT + Write GPIO port + 0x504 + read-write + 0x00000000 + 0x20 - TASKS_TXEN + PIN0 + Pin 0 0 0 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + - - - - TASKS_RXEN - Enable RADIO in RX mode - 0x004 - write-only - - TASKS_RXEN - 0 - 0 + PIN1 + Pin 1 + 1 + 1 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + - - - - TASKS_START - Start RADIO - 0x008 - write-only - - TASKS_START - 0 - 0 + PIN2 + Pin 2 + 2 + 2 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + - - - - TASKS_STOP - Stop RADIO - 0x00C - write-only - - TASKS_STOP - 0 - 0 + PIN3 + Pin 3 + 3 + 3 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + - - - - TASKS_DISABLE - Disable RADIO - 0x010 - write-only - - TASKS_DISABLE - 0 - 0 + PIN4 + Pin 4 + 4 + 4 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + - - - - TASKS_RSSISTART - Start the RSSI and take one single sample of the receive signal strength - 0x014 - write-only - - TASKS_RSSISTART - 0 - 0 + PIN5 + Pin 5 + 5 + 5 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + - - - - TASKS_RSSISTOP - Stop the RSSI measurement - 0x018 - write-only - - TASKS_RSSISTOP - 0 - 0 + PIN6 + Pin 6 + 6 + 6 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + - - - - TASKS_BCSTART - Start the bit counter - 0x01C - write-only - - TASKS_BCSTART - 0 - 0 + PIN7 + Pin 7 + 7 + 7 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + - - - - TASKS_BCSTOP - Stop the bit counter - 0x020 - write-only - - TASKS_BCSTOP - 0 - 0 + PIN8 + Pin 8 + 8 + 8 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + - - - - TASKS_EDSTART - Start the energy detect measurement used in IEEE 802.15.4 mode - 0x024 - write-only - - TASKS_EDSTART - 0 - 0 + PIN9 + Pin 9 + 9 + 9 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + - - - - TASKS_EDSTOP - Stop the energy detect measurement - 0x028 - write-only - - TASKS_EDSTOP - 0 - 0 + PIN10 + Pin 10 + 10 + 10 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + - - - - TASKS_CCASTART - Start the clear channel assessment used in IEEE 802.15.4 mode - 0x02C - write-only - - TASKS_CCASTART - 0 - 0 + PIN11 + Pin 11 + 11 + 11 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + - - - - TASKS_CCASTOP - Stop the clear channel assessment - 0x030 - write-only - - TASKS_CCASTOP - 0 - 0 + PIN12 + Pin 12 + 12 + 12 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + - - - - EVENTS_READY - RADIO has ramped up and is ready to be started - 0x100 - read-write - - EVENTS_READY - 0 - 0 + PIN13 + Pin 13 + 13 + 13 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + - - - - EVENTS_ADDRESS - Address sent or received - 0x104 - read-write - - EVENTS_ADDRESS - 0 - 0 + PIN14 + Pin 14 + 14 + 14 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + - - - - EVENTS_PAYLOAD - Packet payload sent or received - 0x108 - read-write - - - EVENTS_PAYLOAD - 0 - 0 - - - - - EVENTS_END - Packet sent or received - 0x10C - read-write - - - EVENTS_END - 0 - 0 - - - - - EVENTS_DISABLED - RADIO has been disabled - 0x110 - read-write - - - EVENTS_DISABLED - 0 - 0 - - - - - EVENTS_DEVMATCH - A device address match occurred on the last received packet - 0x114 - read-write - - - EVENTS_DEVMATCH - 0 - 0 - - - - - EVENTS_DEVMISS - No device address match occurred on the last received packet - 0x118 - read-write - - - EVENTS_DEVMISS - 0 - 0 - - - - - EVENTS_RSSIEND - Sampling of receive signal strength complete - 0x11C - read-write - - - EVENTS_RSSIEND - 0 - 0 - - - - - EVENTS_BCMATCH - Bit counter reached bit count value - 0x128 - read-write - - - EVENTS_BCMATCH - 0 - 0 - - - - - EVENTS_CRCOK - Packet received with CRC ok - 0x130 - read-write - - - EVENTS_CRCOK - 0 - 0 - - - - - EVENTS_CRCERROR - Packet received with CRC error - 0x134 - read-write - - - EVENTS_CRCERROR - 0 - 0 - - - - - EVENTS_FRAMESTART - IEEE 802.15.4 length field received - 0x138 - read-write - - - EVENTS_FRAMESTART - 0 - 0 - - - - - EVENTS_EDEND - Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. - 0x13C - read-write - - - EVENTS_EDEND - 0 - 0 - - - - - EVENTS_EDSTOPPED - The sampling of energy detection has stopped - 0x140 - read-write - - - EVENTS_EDSTOPPED - 0 - 0 - - - - - EVENTS_CCAIDLE - Wireless medium in idle - clear to send - 0x144 - read-write - - - EVENTS_CCAIDLE - 0 - 0 - - - - - EVENTS_CCABUSY - Wireless medium busy - do not send - 0x148 - read-write - - - EVENTS_CCABUSY - 0 - 0 - - - - - EVENTS_CCASTOPPED - The CCA has stopped - 0x14C - read-write - - - EVENTS_CCASTOPPED - 0 - 0 - - - - - EVENTS_RATEBOOST - Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. - 0x150 - read-write - - - EVENTS_RATEBOOST - 0 - 0 - - - - - EVENTS_TXREADY - RADIO has ramped up and is ready to be started TX path - 0x154 - read-write - - - EVENTS_TXREADY - 0 - 0 - - - - - EVENTS_RXREADY - RADIO has ramped up and is ready to be started RX path - 0x158 - read-write - - - EVENTS_RXREADY - 0 - 0 - - - - - EVENTS_MHRMATCH - MAC header match found - 0x15C - read-write - - - EVENTS_MHRMATCH - 0 - 0 - - - - - EVENTS_PHYEND - Generated in Ble_LR125Kbit, Ble_LR500Kbit and BleIeee802154_250Kbit modes when last bit is sent on air. - 0x16C - read-write - - - EVENTS_PHYEND - 0 - 0 - - - - - SHORTS - Shortcut register - 0x200 - read-write - - READY_START - Shortcut between READY event and START task - 0 - 0 + PIN15 + Pin 15 + 15 + 15 - Disabled - Disable shortcut - 0 + Low + Pin driver is low + 0x0 - Enabled - Enable shortcut - 1 + High + Pin driver is high + 0x1 - END_DISABLE - Shortcut between END event and DISABLE task - 1 - 1 + PIN16 + Pin 16 + 16 + 16 - Disabled - Disable shortcut - 0 + Low + Pin driver is low + 0x0 - Enabled - Enable shortcut - 1 + High + Pin driver is high + 0x1 - DISABLED_TXEN - Shortcut between DISABLED event and TXEN task - 2 - 2 + PIN17 + Pin 17 + 17 + 17 - Disabled - Disable shortcut - 0 + Low + Pin driver is low + 0x0 - Enabled - Enable shortcut - 1 + High + Pin driver is high + 0x1 - DISABLED_RXEN - Shortcut between DISABLED event and RXEN task - 3 - 3 + PIN18 + Pin 18 + 18 + 18 - Disabled - Disable shortcut - 0 + Low + Pin driver is low + 0x0 - Enabled - Enable shortcut - 1 + High + Pin driver is high + 0x1 - ADDRESS_RSSISTART - Shortcut between ADDRESS event and RSSISTART task - 4 - 4 + PIN19 + Pin 19 + 19 + 19 - Disabled - Disable shortcut - 0 + Low + Pin driver is low + 0x0 - Enabled - Enable shortcut - 1 + High + Pin driver is high + 0x1 - END_START - Shortcut between END event and START task - 5 - 5 + PIN20 + Pin 20 + 20 + 20 - Disabled - Disable shortcut - 0 + Low + Pin driver is low + 0x0 - Enabled - Enable shortcut - 1 + High + Pin driver is high + 0x1 - ADDRESS_BCSTART - Shortcut between ADDRESS event and BCSTART task - 6 - 6 + PIN21 + Pin 21 + 21 + 21 - Disabled - Disable shortcut - 0 + Low + Pin driver is low + 0x0 - Enabled - Enable shortcut - 1 + High + Pin driver is high + 0x1 - DISABLED_RSSISTOP - Shortcut between DISABLED event and RSSISTOP task - 8 - 8 + PIN22 + Pin 22 + 22 + 22 - Disabled - Disable shortcut - 0 + Low + Pin driver is low + 0x0 - Enabled - Enable shortcut - 1 + High + Pin driver is high + 0x1 - RXREADY_CCASTART - Shortcut between RXREADY event and CCASTART task - 11 - 11 + PIN23 + Pin 23 + 23 + 23 - Disabled - Disable shortcut - 0 + Low + Pin driver is low + 0x0 - Enabled - Enable shortcut - 1 + High + Pin driver is high + 0x1 - CCAIDLE_TXEN - Shortcut between CCAIDLE event and TXEN task - 12 - 12 + PIN24 + Pin 24 + 24 + 24 - Disabled - Disable shortcut - 0 + Low + Pin driver is low + 0x0 - Enabled - Enable shortcut - 1 + High + Pin driver is high + 0x1 - CCABUSY_DISABLE - Shortcut between CCABUSY event and DISABLE task - 13 - 13 + PIN25 + Pin 25 + 25 + 25 - Disabled - Disable shortcut - 0 + Low + Pin driver is low + 0x0 - Enabled - Enable shortcut - 1 + High + Pin driver is high + 0x1 - FRAMESTART_BCSTART - Shortcut between FRAMESTART event and BCSTART task - 14 - 14 + PIN26 + Pin 26 + 26 + 26 - Disabled - Disable shortcut - 0 + Low + Pin driver is low + 0x0 - Enabled - Enable shortcut - 1 + High + Pin driver is high + 0x1 - READY_EDSTART - Shortcut between READY event and EDSTART task - 15 - 15 + PIN27 + Pin 27 + 27 + 27 - Disabled - Disable shortcut - 0 + Low + Pin driver is low + 0x0 - Enabled - Enable shortcut - 1 + High + Pin driver is high + 0x1 - EDEND_DISABLE - Shortcut between EDEND event and DISABLE task - 16 - 16 + PIN28 + Pin 28 + 28 + 28 - Disabled - Disable shortcut - 0 + Low + Pin driver is low + 0x0 - Enabled - Enable shortcut - 1 + High + Pin driver is high + 0x1 - CCAIDLE_STOP - Shortcut between CCAIDLE event and STOP task - 17 - 17 + PIN29 + Pin 29 + 29 + 29 - Disabled - Disable shortcut - 0 + Low + Pin driver is low + 0x0 - Enabled - Enable shortcut - 1 + High + Pin driver is high + 0x1 - TXREADY_START - Shortcut between TXREADY event and START task - 18 - 18 + PIN30 + Pin 30 + 30 + 30 - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - RXREADY_START - Shortcut between RXREADY event and START task - 19 - 19 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - PHYEND_DISABLE - Shortcut between PHYEND event and DISABLE task - 20 - 20 - - - Disabled - Disable shortcut - 0 + Low + Pin driver is low + 0x0 - Enabled - Enable shortcut - 1 + High + Pin driver is high + 0x1 - PHYEND_START - Shortcut between PHYEND event and START task - 21 - 21 + PIN31 + Pin 31 + 31 + 31 - Disabled - Disable shortcut - 0 + Low + Pin driver is low + 0x0 - Enabled - Enable shortcut - 1 + High + Pin driver is high + 0x1 - INTENSET - Enable interrupt - 0x304 + OUTSET + Set individual bits in GPIO port + 0x508 read-write + 0x00000000 + oneToSet + 0x20 - READY - Write '1' to enable interrupt for READY event + PIN0 + Pin 0 0 0 read - Disabled - Read: Disabled - 0 + Low + Read: pin driver is low + 0x0 - Enabled - Read: Enabled - 1 + High + Read: pin driver is high + 0x1 write Set - Enable - 1 + Write: a '1' sets the pin high; a '0' has no effect + 0x1 - ADDRESS - Write '1' to enable interrupt for ADDRESS event + PIN1 + Pin 1 1 1 read - Disabled - Read: Disabled - 0 + Low + Read: pin driver is low + 0x0 - Enabled - Read: Enabled - 1 + High + Read: pin driver is high + 0x1 write Set - Enable - 1 + Write: a '1' sets the pin high; a '0' has no effect + 0x1 - PAYLOAD - Write '1' to enable interrupt for PAYLOAD event + PIN2 + Pin 2 2 2 read - Disabled - Read: Disabled - 0 + Low + Read: pin driver is low + 0x0 - Enabled - Read: Enabled - 1 + High + Read: pin driver is high + 0x1 write Set - Enable - 1 + Write: a '1' sets the pin high; a '0' has no effect + 0x1 - END - Write '1' to enable interrupt for END event + PIN3 + Pin 3 3 3 read - Disabled - Read: Disabled - 0 + Low + Read: pin driver is low + 0x0 - Enabled - Read: Enabled - 1 + High + Read: pin driver is high + 0x1 write Set - Enable - 1 + Write: a '1' sets the pin high; a '0' has no effect + 0x1 - DISABLED - Write '1' to enable interrupt for DISABLED event + PIN4 + Pin 4 4 4 read - Disabled - Read: Disabled - 0 + Low + Read: pin driver is low + 0x0 - Enabled - Read: Enabled - 1 + High + Read: pin driver is high + 0x1 write Set - Enable - 1 + Write: a '1' sets the pin high; a '0' has no effect + 0x1 - DEVMATCH - Write '1' to enable interrupt for DEVMATCH event + PIN5 + Pin 5 5 5 read - Disabled - Read: Disabled - 0 + Low + Read: pin driver is low + 0x0 - Enabled - Read: Enabled - 1 + High + Read: pin driver is high + 0x1 write Set - Enable - 1 + Write: a '1' sets the pin high; a '0' has no effect + 0x1 - DEVMISS - Write '1' to enable interrupt for DEVMISS event + PIN6 + Pin 6 6 6 read - Disabled - Read: Disabled - 0 + Low + Read: pin driver is low + 0x0 - Enabled - Read: Enabled - 1 + High + Read: pin driver is high + 0x1 write Set - Enable - 1 + Write: a '1' sets the pin high; a '0' has no effect + 0x1 - RSSIEND - Write '1' to enable interrupt for RSSIEND event + PIN7 + Pin 7 7 7 read - Disabled - Read: Disabled - 0 + Low + Read: pin driver is low + 0x0 - Enabled - Read: Enabled - 1 + High + Read: pin driver is high + 0x1 write Set - Enable - 1 + Write: a '1' sets the pin high; a '0' has no effect + 0x1 - BCMATCH - Write '1' to enable interrupt for BCMATCH event + PIN8 + Pin 8 + 8 + 8 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 0x1 + + + + + PIN9 + Pin 9 + 9 + 9 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 0x1 + + + + + PIN10 + Pin 10 10 10 read - Disabled - Read: Disabled - 0 + Low + Read: pin driver is low + 0x0 - Enabled - Read: Enabled - 1 + High + Read: pin driver is high + 0x1 write Set - Enable - 1 + Write: a '1' sets the pin high; a '0' has no effect + 0x1 - CRCOK - Write '1' to enable interrupt for CRCOK event + PIN11 + Pin 11 + 11 + 11 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 0x1 + + + + + PIN12 + Pin 12 12 12 read - Disabled - Read: Disabled - 0 + Low + Read: pin driver is low + 0x0 - Enabled - Read: Enabled - 1 + High + Read: pin driver is high + 0x1 write Set - Enable - 1 + Write: a '1' sets the pin high; a '0' has no effect + 0x1 - CRCERROR - Write '1' to enable interrupt for CRCERROR event + PIN13 + Pin 13 13 13 read - Disabled - Read: Disabled - 0 + Low + Read: pin driver is low + 0x0 - Enabled - Read: Enabled - 1 + High + Read: pin driver is high + 0x1 write Set - Enable - 1 + Write: a '1' sets the pin high; a '0' has no effect + 0x1 - FRAMESTART - Write '1' to enable interrupt for FRAMESTART event + PIN14 + Pin 14 14 14 read - Disabled - Read: Disabled - 0 + Low + Read: pin driver is low + 0x0 - Enabled - Read: Enabled - 1 + High + Read: pin driver is high + 0x1 write Set - Enable - 1 + Write: a '1' sets the pin high; a '0' has no effect + 0x1 - EDEND - Write '1' to enable interrupt for EDEND event + PIN15 + Pin 15 15 15 read - Disabled - Read: Disabled - 0 + Low + Read: pin driver is low + 0x0 - Enabled - Read: Enabled - 1 + High + Read: pin driver is high + 0x1 write Set - Enable - 1 + Write: a '1' sets the pin high; a '0' has no effect + 0x1 - EDSTOPPED - Write '1' to enable interrupt for EDSTOPPED event + PIN16 + Pin 16 16 16 read - Disabled - Read: Disabled - 0 + Low + Read: pin driver is low + 0x0 - Enabled - Read: Enabled - 1 + High + Read: pin driver is high + 0x1 write Set - Enable - 1 + Write: a '1' sets the pin high; a '0' has no effect + 0x1 - CCAIDLE - Write '1' to enable interrupt for CCAIDLE event + PIN17 + Pin 17 17 17 read - Disabled - Read: Disabled - 0 + Low + Read: pin driver is low + 0x0 - Enabled - Read: Enabled - 1 + High + Read: pin driver is high + 0x1 write Set - Enable - 1 + Write: a '1' sets the pin high; a '0' has no effect + 0x1 - CCABUSY - Write '1' to enable interrupt for CCABUSY event + PIN18 + Pin 18 18 18 read - Disabled - Read: Disabled - 0 + Low + Read: pin driver is low + 0x0 - Enabled - Read: Enabled - 1 + High + Read: pin driver is high + 0x1 write Set - Enable - 1 + Write: a '1' sets the pin high; a '0' has no effect + 0x1 - CCASTOPPED - Write '1' to enable interrupt for CCASTOPPED event + PIN19 + Pin 19 19 19 read - Disabled - Read: Disabled - 0 + Low + Read: pin driver is low + 0x0 - Enabled - Read: Enabled - 1 + High + Read: pin driver is high + 0x1 write Set - Enable - 1 + Write: a '1' sets the pin high; a '0' has no effect + 0x1 - RATEBOOST - Write '1' to enable interrupt for RATEBOOST event + PIN20 + Pin 20 20 20 read - Disabled - Read: Disabled - 0 + Low + Read: pin driver is low + 0x0 - Enabled - Read: Enabled - 1 + High + Read: pin driver is high + 0x1 write Set - Enable - 1 + Write: a '1' sets the pin high; a '0' has no effect + 0x1 - TXREADY - Write '1' to enable interrupt for TXREADY event + PIN21 + Pin 21 21 21 read - Disabled - Read: Disabled - 0 + Low + Read: pin driver is low + 0x0 - Enabled - Read: Enabled - 1 + High + Read: pin driver is high + 0x1 write Set - Enable - 1 + Write: a '1' sets the pin high; a '0' has no effect + 0x1 - RXREADY - Write '1' to enable interrupt for RXREADY event + PIN22 + Pin 22 22 22 read - Disabled - Read: Disabled - 0 + Low + Read: pin driver is low + 0x0 - Enabled - Read: Enabled - 1 + High + Read: pin driver is high + 0x1 write Set - Enable - 1 + Write: a '1' sets the pin high; a '0' has no effect + 0x1 - MHRMATCH - Write '1' to enable interrupt for MHRMATCH event + PIN23 + Pin 23 23 23 read - Disabled - Read: Disabled - 0 + Low + Read: pin driver is low + 0x0 - Enabled - Read: Enabled - 1 + High + Read: pin driver is high + 0x1 write Set - Enable - 1 + Write: a '1' sets the pin high; a '0' has no effect + 0x1 - PHYEND - Write '1' to enable interrupt for PHYEND event - 27 - 27 + PIN24 + Pin 24 + 24 + 24 read - Disabled - Read: Disabled - 0 + Low + Read: pin driver is low + 0x0 - Enabled - Read: Enabled - 1 + High + Read: pin driver is high + 0x1 write Set - Enable - 1 + Write: a '1' sets the pin high; a '0' has no effect + 0x1 - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - READY - Write '1' to disable interrupt for READY event - 0 - 0 + PIN25 + Pin 25 + 25 + 25 read - Disabled - Read: Disabled - 0 + Low + Read: pin driver is low + 0x0 - Enabled - Read: Enabled - 1 + High + Read: pin driver is high + 0x1 write - Clear - Disable - 1 + Set + Write: a '1' sets the pin high; a '0' has no effect + 0x1 - ADDRESS - Write '1' to disable interrupt for ADDRESS event - 1 - 1 + PIN26 + Pin 26 + 26 + 26 read - Disabled - Read: Disabled - 0 + Low + Read: pin driver is low + 0x0 - Enabled - Read: Enabled - 1 + High + Read: pin driver is high + 0x1 write - Clear - Disable - 1 + Set + Write: a '1' sets the pin high; a '0' has no effect + 0x1 - PAYLOAD - Write '1' to disable interrupt for PAYLOAD event - 2 - 2 + PIN27 + Pin 27 + 27 + 27 read - Disabled - Read: Disabled - 0 + Low + Read: pin driver is low + 0x0 - Enabled - Read: Enabled - 1 + High + Read: pin driver is high + 0x1 write - Clear - Disable - 1 + Set + Write: a '1' sets the pin high; a '0' has no effect + 0x1 - END - Write '1' to disable interrupt for END event - 3 - 3 + PIN28 + Pin 28 + 28 + 28 read - Disabled - Read: Disabled - 0 + Low + Read: pin driver is low + 0x0 - Enabled - Read: Enabled - 1 + High + Read: pin driver is high + 0x1 write - Clear - Disable - 1 + Set + Write: a '1' sets the pin high; a '0' has no effect + 0x1 - DISABLED - Write '1' to disable interrupt for DISABLED event - 4 - 4 + PIN29 + Pin 29 + 29 + 29 read - Disabled - Read: Disabled - 0 + Low + Read: pin driver is low + 0x0 - Enabled - Read: Enabled - 1 + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 0x1 + + + + + PIN30 + Pin 30 + 30 + 30 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 0x1 + + + + + PIN31 + Pin 31 + 31 + 31 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 0x1 + + + + + + + OUTCLR + Clear individual bits in GPIO port + 0x50C + read-write + 0x00000000 + oneToClear + 0x20 + + + PIN0 + Pin 0 + 0 + 0 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 write Clear - Disable - 1 + Write: a '1' sets the pin low; a '0' has no effect + 0x1 - DEVMATCH - Write '1' to disable interrupt for DEVMATCH event + PIN1 + Pin 1 + 1 + 1 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 0x1 + + + + + PIN2 + Pin 2 + 2 + 2 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 0x1 + + + + + PIN3 + Pin 3 + 3 + 3 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 0x1 + + + + + PIN4 + Pin 4 + 4 + 4 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 0x1 + + + + + PIN5 + Pin 5 5 5 read - Disabled - Read: Disabled - 0 + Low + Read: pin driver is low + 0x0 - Enabled - Read: Enabled - 1 + High + Read: pin driver is high + 0x1 write Clear - Disable - 1 + Write: a '1' sets the pin low; a '0' has no effect + 0x1 - DEVMISS - Write '1' to disable interrupt for DEVMISS event + PIN6 + Pin 6 6 6 read - Disabled - Read: Disabled - 0 + Low + Read: pin driver is low + 0x0 - Enabled - Read: Enabled - 1 + High + Read: pin driver is high + 0x1 write Clear - Disable - 1 + Write: a '1' sets the pin low; a '0' has no effect + 0x1 - RSSIEND - Write '1' to disable interrupt for RSSIEND event + PIN7 + Pin 7 7 7 read - Disabled - Read: Disabled - 0 + Low + Read: pin driver is low + 0x0 - Enabled - Read: Enabled - 1 + High + Read: pin driver is high + 0x1 write Clear - Disable - 1 + Write: a '1' sets the pin low; a '0' has no effect + 0x1 - BCMATCH - Write '1' to disable interrupt for BCMATCH event + PIN8 + Pin 8 + 8 + 8 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 0x1 + + + + + PIN9 + Pin 9 + 9 + 9 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 0x1 + + + + + PIN10 + Pin 10 10 10 read - Disabled - Read: Disabled - 0 + Low + Read: pin driver is low + 0x0 - Enabled - Read: Enabled - 1 + High + Read: pin driver is high + 0x1 write Clear - Disable - 1 + Write: a '1' sets the pin low; a '0' has no effect + 0x1 - CRCOK - Write '1' to disable interrupt for CRCOK event + PIN11 + Pin 11 + 11 + 11 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 0x1 + + + + + PIN12 + Pin 12 12 12 read - Disabled - Read: Disabled - 0 + Low + Read: pin driver is low + 0x0 - Enabled - Read: Enabled - 1 + High + Read: pin driver is high + 0x1 write Clear - Disable - 1 + Write: a '1' sets the pin low; a '0' has no effect + 0x1 - CRCERROR - Write '1' to disable interrupt for CRCERROR event + PIN13 + Pin 13 13 13 read - Disabled - Read: Disabled - 0 + Low + Read: pin driver is low + 0x0 - Enabled - Read: Enabled - 1 + High + Read: pin driver is high + 0x1 write Clear - Disable - 1 + Write: a '1' sets the pin low; a '0' has no effect + 0x1 - FRAMESTART - Write '1' to disable interrupt for FRAMESTART event + PIN14 + Pin 14 14 14 read - Disabled - Read: Disabled - 0 + Low + Read: pin driver is low + 0x0 - Enabled - Read: Enabled - 1 + High + Read: pin driver is high + 0x1 write Clear - Disable - 1 + Write: a '1' sets the pin low; a '0' has no effect + 0x1 - EDEND - Write '1' to disable interrupt for EDEND event + PIN15 + Pin 15 15 15 read - Disabled - Read: Disabled - 0 + Low + Read: pin driver is low + 0x0 - Enabled - Read: Enabled - 1 + High + Read: pin driver is high + 0x1 write Clear - Disable - 1 + Write: a '1' sets the pin low; a '0' has no effect + 0x1 - EDSTOPPED - Write '1' to disable interrupt for EDSTOPPED event + PIN16 + Pin 16 16 16 read - Disabled - Read: Disabled - 0 + Low + Read: pin driver is low + 0x0 - Enabled - Read: Enabled - 1 + High + Read: pin driver is high + 0x1 write Clear - Disable - 1 + Write: a '1' sets the pin low; a '0' has no effect + 0x1 - CCAIDLE - Write '1' to disable interrupt for CCAIDLE event + PIN17 + Pin 17 17 17 read - Disabled - Read: Disabled - 0 + Low + Read: pin driver is low + 0x0 - Enabled - Read: Enabled - 1 + High + Read: pin driver is high + 0x1 write Clear - Disable - 1 + Write: a '1' sets the pin low; a '0' has no effect + 0x1 - CCABUSY - Write '1' to disable interrupt for CCABUSY event + PIN18 + Pin 18 18 18 read - Disabled - Read: Disabled - 0 + Low + Read: pin driver is low + 0x0 - Enabled - Read: Enabled - 1 + High + Read: pin driver is high + 0x1 write Clear - Disable - 1 + Write: a '1' sets the pin low; a '0' has no effect + 0x1 - CCASTOPPED - Write '1' to disable interrupt for CCASTOPPED event + PIN19 + Pin 19 19 19 read - Disabled - Read: Disabled - 0 + Low + Read: pin driver is low + 0x0 - Enabled - Read: Enabled - 1 + High + Read: pin driver is high + 0x1 write Clear - Disable - 1 + Write: a '1' sets the pin low; a '0' has no effect + 0x1 - RATEBOOST - Write '1' to disable interrupt for RATEBOOST event + PIN20 + Pin 20 20 20 read - Disabled - Read: Disabled - 0 + Low + Read: pin driver is low + 0x0 - Enabled - Read: Enabled - 1 + High + Read: pin driver is high + 0x1 write Clear - Disable - 1 + Write: a '1' sets the pin low; a '0' has no effect + 0x1 - TXREADY - Write '1' to disable interrupt for TXREADY event + PIN21 + Pin 21 21 21 read - Disabled - Read: Disabled - 0 + Low + Read: pin driver is low + 0x0 - Enabled - Read: Enabled - 1 + High + Read: pin driver is high + 0x1 write Clear - Disable - 1 + Write: a '1' sets the pin low; a '0' has no effect + 0x1 - RXREADY - Write '1' to disable interrupt for RXREADY event + PIN22 + Pin 22 22 22 read - Disabled - Read: Disabled - 0 + Low + Read: pin driver is low + 0x0 - Enabled - Read: Enabled - 1 + High + Read: pin driver is high + 0x1 write Clear - Disable - 1 + Write: a '1' sets the pin low; a '0' has no effect + 0x1 - MHRMATCH - Write '1' to disable interrupt for MHRMATCH event + PIN23 + Pin 23 23 23 read - Disabled - Read: Disabled - 0 + Low + Read: pin driver is low + 0x0 - Enabled - Read: Enabled - 1 + High + Read: pin driver is high + 0x1 write Clear - Disable - 1 + Write: a '1' sets the pin low; a '0' has no effect + 0x1 - PHYEND - Write '1' to disable interrupt for PHYEND event - 27 - 27 + PIN24 + Pin 24 + 24 + 24 read - Disabled - Read: Disabled - 0 + Low + Read: pin driver is low + 0x0 - Enabled - Read: Enabled - 1 + High + Read: pin driver is high + 0x1 write Clear - Disable - 1 + Write: a '1' sets the pin low; a '0' has no effect + 0x1 - - - - CRCSTATUS - CRC status - 0x400 - read-only - - CRCSTATUS - CRC status of packet received - 0 - 0 + PIN25 + Pin 25 + 25 + 25 + read - CRCError - Packet received with CRC error - 0 + Low + Read: pin driver is low + 0x0 - CRCOk - Packet received with CRC ok - 1 + High + Read: pin driver is high + 0x1 - - - - - RXMATCH - Received address - 0x408 - read-only - - - RXMATCH - Received address - 0 - 2 - - - - - RXCRC - CRC field of previously received packet - 0x40C - read-only - - - RXCRC - CRC field of previously received packet - 0 - 23 - - - - - DAI - Device address match index - 0x410 - read-only - - - DAI - Device address match index - 0 - 2 - - - - - PDUSTAT - Payload status - 0x414 - read-only - - - PDUSTAT - Status on payload length vs. PCNF1.MAXLEN - 0 - 0 + write - LessThan - Payload less than PCNF1.MAXLEN - 0 - - - GreaterThan - Payload greater than PCNF1.MAXLEN - 1 + Clear + Write: a '1' sets the pin low; a '0' has no effect + 0x1 - CISTAT - Status on what rate packet is received with in Long Range - 1 - 2 + PIN26 + Pin 26 + 26 + 26 + read - LR125kbit - Frame is received at 125kbps - 0 + Low + Read: pin driver is low + 0x0 - LR500kbit - Frame is received at 500kbps - 1 + High + Read: pin driver is high + 0x1 - - - - - PACKETPTR - Packet pointer - 0x504 - read-write - - - PACKETPTR - Packet pointer - 0 - 31 - - - - - FREQUENCY - Frequency - 0x508 - read-write - 0x00000002 - - - FREQUENCY - Radio channel frequency - 0 - 6 - - - MAP - Channel map selection. - 8 - 8 + write - Default - Channel map between 2400 MHZ .. 2500 MHz - 0 - - - Low - Channel map between 2360 MHZ .. 2460 MHz - 1 + Clear + Write: a '1' sets the pin low; a '0' has no effect + 0x1 - - - - TXPOWER - Output power - 0x50C - read-write - - TXPOWER - RADIO output power - 0 - 7 + PIN27 + Pin 27 + 27 + 27 + read - Pos8dBm - +8 dBm - 0x8 + Low + Read: pin driver is low + 0x0 - Pos7dBm - +7 dBm - 0x7 + High + Read: pin driver is high + 0x1 + + + write - Pos6dBm - +6 dBm - 0x6 + Clear + Write: a '1' sets the pin low; a '0' has no effect + 0x1 + + + + PIN28 + Pin 28 + 28 + 28 + + read - Pos5dBm - +5 dBm - 0x5 + Low + Read: pin driver is low + 0x0 - Pos4dBm - +4 dBm - 0x4 + High + Read: pin driver is high + 0x1 + + + write - Pos3dBm - +3 dBm - 0x3 + Clear + Write: a '1' sets the pin low; a '0' has no effect + 0x1 + + + + PIN29 + Pin 29 + 29 + 29 + + read - Pos2dBm - +2 dBm - 0x2 + Low + Read: pin driver is low + 0x0 - 0dBm - 0 dBm - 0x0 + High + Read: pin driver is high + 0x1 + + + write - Neg4dBm - -4 dBm - 0xFC + Clear + Write: a '1' sets the pin low; a '0' has no effect + 0x1 + + + + PIN30 + Pin 30 + 30 + 30 + + read - Neg8dBm - -8 dBm - 0xF8 + Low + Read: pin driver is low + 0x0 - Neg12dBm - -12 dBm - 0xF4 + High + Read: pin driver is high + 0x1 + + + write - Neg16dBm - -16 dBm - 0xF0 + Clear + Write: a '1' sets the pin low; a '0' has no effect + 0x1 + + + + PIN31 + Pin 31 + 31 + 31 + + read - Neg20dBm - -20 dBm - 0xEC + Low + Read: pin driver is low + 0x0 - Neg30dBm - Deprecated enumerator - -40 dBm - 0xFF + High + Read: pin driver is high + 0x1 + + + write - Neg40dBm - -40 dBm - 0xD8 + Clear + Write: a '1' sets the pin low; a '0' has no effect + 0x1 - MODE - Data rate and modulation + IN + Read GPIO port 0x510 - read-write + read-only + 0x00000000 + 0x20 - MODE - Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation. + PIN0 + Pin 0 0 - 3 + 0 - Nrf_1Mbit - 1 Mbit/s Nordic proprietary radio mode - 0 - - - Nrf_2Mbit - 2 Mbit/s Nordic proprietary radio mode - 1 + Low + Pin input is low + 0x0 - Ble_1Mbit - 1 Mbit/s BLE - 3 + High + Pin input is high + 0x1 + + + + PIN1 + Pin 1 + 1 + 1 + - Ble_2Mbit - 2 Mbit/s BLE - 4 + Low + Pin input is low + 0x0 - Ble_LR125Kbit - Long range 125 kbit/s TX, 125 kbit/s and 500 kbit/s RX - 5 + High + Pin input is high + 0x1 + + + + PIN2 + Pin 2 + 2 + 2 + - Ble_LR500Kbit - Long range 500 kbit/s TX, 125 kbit/s and 500 kbit/s RX - 6 + Low + Pin input is low + 0x0 - Ieee802154_250Kbit - IEEE 802.15.4-2006 250 kbit/s - 15 + High + Pin input is high + 0x1 - - - - PCNF0 - Packet configuration register 0 - 0x514 - read-write - - LFLEN - Length on air of LENGTH field in number of bits. - 0 + PIN3 + Pin 3 + 3 3 - - - S0LEN - Length on air of S0 field in number of bytes. - 8 - 8 - - - S1LEN - Length on air of S1 field in number of bits. - 16 - 19 - - - S1INCL - Include or exclude S1 field in RAM - 20 - 20 - Automatic - Include S1 field in RAM only if S1LEN &gt; 0 - 0 + Low + Pin input is low + 0x0 - Include - Always include S1 field in RAM independent of S1LEN - 1 + High + Pin input is high + 0x1 - CILEN - Length of code indicator - long range - 22 - 23 - - - PLEN - Length of preamble on air. Decision point: TASKS_START task - 24 - 25 + PIN4 + Pin 4 + 4 + 4 - 8bit - 8-bit preamble - 0 + Low + Pin input is low + 0x0 - 16bit - 16-bit preamble - 1 + High + Pin input is high + 0x1 + + + + PIN5 + Pin 5 + 5 + 5 + - 32bitZero - 32-bit zero preamble - used for IEEE 802.15.4 - 2 + Low + Pin input is low + 0x0 - LongRange - Preamble - used for BLE long range - 3 + High + Pin input is high + 0x1 - CRCINC - Indicates if LENGTH field contains CRC or not - 26 - 26 + PIN6 + Pin 6 + 6 + 6 - Exclude - LENGTH does not contain CRC - 0 + Low + Pin input is low + 0x0 - Include - LENGTH includes CRC - 1 + High + Pin input is high + 0x1 - TERMLEN - Length of TERM field in Long Range operation - 29 - 30 - - - - - PCNF1 - Packet configuration register 1 - 0x518 - read-write - - - MAXLEN - Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. - 0 + PIN7 + Pin 7 + 7 7 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + - STATLEN - Static length in number of bytes + PIN8 + Pin 8 8 - 15 - - - BALEN - Base address length in number of bytes - 16 - 18 - - - ENDIAN - On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. - 24 - 24 + 8 - Little - Least significant bit on air first - 0 + Low + Pin input is low + 0x0 - Big - Most significant bit on air first - 1 + High + Pin input is high + 0x1 - WHITEEN - Enable or disable packet whitening - 25 - 25 + PIN9 + Pin 9 + 9 + 9 - Disabled - Disable - 0 + Low + Pin input is low + 0x0 - Enabled - Enable - 1 + High + Pin input is high + 0x1 - - - - BASE0 - Base address 0 - 0x51C - read-write - - BASE0 - Base address 0 - 0 - 31 - - - - - BASE1 - Base address 1 - 0x520 - read-write - - - BASE1 - Base address 1 - 0 - 31 - - - - - PREFIX0 - Prefixes bytes for logical addresses 0-3 - 0x524 - read-write - - - AP0 - Address prefix 0. - 0 - 7 + PIN10 + Pin 10 + 10 + 10 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + - AP1 - Address prefix 1. - 8 - 15 + PIN11 + Pin 11 + 11 + 11 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + - AP2 - Address prefix 2. - 16 - 23 + PIN12 + Pin 12 + 12 + 12 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + - AP3 - Address prefix 3. - 24 - 31 + PIN13 + Pin 13 + 13 + 13 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + - - - - PREFIX1 - Prefixes bytes for logical addresses 4-7 - 0x528 - read-write - - AP4 - Address prefix 4. - 0 - 7 + PIN14 + Pin 14 + 14 + 14 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + - AP5 - Address prefix 5. - 8 + PIN15 + Pin 15 + 15 15 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + - AP6 - Address prefix 6. + PIN16 + Pin 16 16 - 23 + 16 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + - AP7 - Address prefix 7. - 24 - 31 + PIN17 + Pin 17 + 17 + 17 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + - - - - TXADDRESS - Transmit address select - 0x52C - read-write - - TXADDRESS - Transmit address select - 0 - 2 + PIN18 + Pin 18 + 18 + 18 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + - - - - RXADDRESSES - Receive address select - 0x530 - read-write - - ADDR0 - Enable or disable reception on logical address 0. - 0 - 0 + PIN19 + Pin 19 + 19 + 19 - Disabled - Disable - 0 + Low + Pin input is low + 0x0 - Enabled - Enable - 1 + High + Pin input is high + 0x1 - ADDR1 - Enable or disable reception on logical address 1. - 1 - 1 + PIN20 + Pin 20 + 20 + 20 - Disabled - Disable - 0 + Low + Pin input is low + 0x0 - Enabled - Enable - 1 + High + Pin input is high + 0x1 - ADDR2 - Enable or disable reception on logical address 2. - 2 - 2 + PIN21 + Pin 21 + 21 + 21 - Disabled - Disable - 0 + Low + Pin input is low + 0x0 - Enabled - Enable - 1 + High + Pin input is high + 0x1 - ADDR3 - Enable or disable reception on logical address 3. - 3 - 3 + PIN22 + Pin 22 + 22 + 22 - Disabled - Disable - 0 + Low + Pin input is low + 0x0 - Enabled - Enable - 1 + High + Pin input is high + 0x1 - ADDR4 - Enable or disable reception on logical address 4. - 4 - 4 + PIN23 + Pin 23 + 23 + 23 - Disabled - Disable - 0 + Low + Pin input is low + 0x0 - Enabled - Enable - 1 + High + Pin input is high + 0x1 - ADDR5 - Enable or disable reception on logical address 5. - 5 - 5 + PIN24 + Pin 24 + 24 + 24 - Disabled - Disable - 0 + Low + Pin input is low + 0x0 - Enabled - Enable - 1 + High + Pin input is high + 0x1 - ADDR6 - Enable or disable reception on logical address 6. - 6 - 6 + PIN25 + Pin 25 + 25 + 25 - Disabled - Disable - 0 + Low + Pin input is low + 0x0 - Enabled - Enable - 1 + High + Pin input is high + 0x1 - ADDR7 - Enable or disable reception on logical address 7. - 7 - 7 + PIN26 + Pin 26 + 26 + 26 - Disabled - Disable - 0 + Low + Pin input is low + 0x0 - Enabled - Enable - 1 + High + Pin input is high + 0x1 - - - - CRCCNF - CRC configuration - 0x534 - read-write - - LEN - CRC length in number of bytes. - 0 - 1 + PIN27 + Pin 27 + 27 + 27 - Disabled - CRC length is zero and CRC calculation is disabled - 0 + Low + Pin input is low + 0x0 - One - CRC length is one byte and CRC calculation is enabled - 1 + High + Pin input is high + 0x1 + + + + PIN28 + Pin 28 + 28 + 28 + - Two - CRC length is two bytes and CRC calculation is enabled - 2 + Low + Pin input is low + 0x0 - Three - CRC length is three bytes and CRC calculation is enabled - 3 + High + Pin input is high + 0x1 - SKIPADDR - Include or exclude packet address field out of CRC calculation. - 8 - 9 + PIN29 + Pin 29 + 29 + 29 - Include - CRC calculation includes address field - 0 + Low + Pin input is low + 0x0 - Skip - CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. - 1 + High + Pin input is high + 0x1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Low + Pin input is low + 0x0 - Ieee802154 - CRC calculation as per 802.15.4 standard. Starting at first byte after length field. - 2 + High + Pin input is high + 0x1 - - - - CRCPOLY - CRC polynomial - 0x538 - read-write - 0x00000000 - - CRCPOLY - CRC polynomial - 0 - 23 + PIN31 + Pin 31 + 31 + 31 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + - CRCINIT - CRC initial value - 0x53C + DIR + Direction of GPIO pins + 0x514 read-write + 0x00000000 + 0x20 - CRCINIT - CRC initial value + PIN0 + Pin 0 0 - 23 + 0 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + - - - - TIFS - Interframe spacing in us - 0x544 - read-write - - TIFS - Interframe spacing in us - 0 - 9 + PIN1 + Pin 1 + 1 + 1 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + - - - - RSSISAMPLE - RSSI sample - 0x548 - read-only - - - RSSISAMPLE - RSSI sample - 0 - 6 - - - - - STATE - Current radio state - 0x550 - read-only - - STATE - Current radio state - 0 - 3 + PIN2 + Pin 2 + 2 + 2 - Disabled - RADIO is in the Disabled state - 0 - - - RxRu - RADIO is in the RXRU state - 1 + Input + Pin set as input + 0x0 - RxIdle - RADIO is in the RXIDLE state - 2 + Output + Pin set as output + 0x1 + + + + PIN3 + Pin 3 + 3 + 3 + - Rx - RADIO is in the RX state - 3 + Input + Pin set as input + 0x0 - RxDisable - RADIO is in the RXDISABLED state - 4 + Output + Pin set as output + 0x1 + + + + PIN4 + Pin 4 + 4 + 4 + - TxRu - RADIO is in the TXRU state - 9 + Input + Pin set as input + 0x0 - TxIdle - RADIO is in the TXIDLE state - 10 + Output + Pin set as output + 0x1 + + + + PIN5 + Pin 5 + 5 + 5 + - Tx - RADIO is in the TX state - 11 + Input + Pin set as input + 0x0 - TxDisable - RADIO is in the TXDISABLED state - 12 + Output + Pin set as output + 0x1 - - - - DATAWHITEIV - Data whitening initial value - 0x554 - read-write - 0x00000040 - - DATAWHITEIV - Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. - 0 + PIN6 + Pin 6 + 6 6 - - - - - BCC - Bit counter compare - 0x560 - read-write - - - BCC - Bit counter compare - 0 - 31 - - - - - 8 - 0x4 - DAB[%s] - Description collection[n]: Device address base segment n - 0x600 - read-write - - - DAB - Device address base segment n - 0 - 31 - - - - - 8 - 0x4 - DAP[%s] - Description collection[n]: Device address prefix n - 0x620 - read-write - - - DAP - Device address prefix n - 0 - 15 - - - - - DACNF - Device address match configuration - 0x640 - read-write - - - ENA0 - Enable or disable device address matching using device address 0 - 0 - 0 - Disabled - Disabled - 0 + Input + Pin set as input + 0x0 - Enabled - Enabled - 1 + Output + Pin set as output + 0x1 - ENA1 - Enable or disable device address matching using device address 1 - 1 - 1 + PIN7 + Pin 7 + 7 + 7 - Disabled - Disabled - 0 + Input + Pin set as input + 0x0 - Enabled - Enabled - 1 + Output + Pin set as output + 0x1 - ENA2 - Enable or disable device address matching using device address 2 - 2 - 2 + PIN8 + Pin 8 + 8 + 8 - Disabled - Disabled - 0 + Input + Pin set as input + 0x0 - Enabled - Enabled - 1 + Output + Pin set as output + 0x1 - ENA3 - Enable or disable device address matching using device address 3 - 3 - 3 + PIN9 + Pin 9 + 9 + 9 - Disabled - Disabled - 0 + Input + Pin set as input + 0x0 - Enabled - Enabled - 1 + Output + Pin set as output + 0x1 - ENA4 - Enable or disable device address matching using device address 4 - 4 - 4 + PIN10 + Pin 10 + 10 + 10 - Disabled - Disabled - 0 + Input + Pin set as input + 0x0 - Enabled - Enabled - 1 + Output + Pin set as output + 0x1 - ENA5 - Enable or disable device address matching using device address 5 - 5 - 5 + PIN11 + Pin 11 + 11 + 11 - Disabled - Disabled - 0 + Input + Pin set as input + 0x0 - Enabled - Enabled - 1 + Output + Pin set as output + 0x1 - ENA6 - Enable or disable device address matching using device address 6 - 6 - 6 + PIN12 + Pin 12 + 12 + 12 - Disabled - Disabled - 0 + Input + Pin set as input + 0x0 - Enabled - Enabled - 1 + Output + Pin set as output + 0x1 - ENA7 - Enable or disable device address matching using device address 7 - 7 - 7 + PIN13 + Pin 13 + 13 + 13 - Disabled - Disabled - 0 + Input + Pin set as input + 0x0 - Enabled - Enabled - 1 + Output + Pin set as output + 0x1 - TXADD0 - TxAdd for device address 0 - 8 - 8 - - - TXADD1 - TxAdd for device address 1 - 9 - 9 - - - TXADD2 - TxAdd for device address 2 - 10 - 10 - - - TXADD3 - TxAdd for device address 3 - 11 - 11 - - - TXADD4 - TxAdd for device address 4 - 12 - 12 - - - TXADD5 - TxAdd for device address 5 - 13 - 13 - - - TXADD6 - TxAdd for device address 6 + PIN14 + Pin 14 14 14 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + - TXADD7 - TxAdd for device address 7 + PIN15 + Pin 15 15 15 - - - - - MHRMATCHCONF - Search pattern configuration - 0x644 - read-write - - - MHRMATCHMAS - Pattern mask - 0x648 - read-write - - - MODECNF0 - Radio mode configuration register 0 - 0x650 - read-write - 0x00000200 - - - RU - Radio ramp-up time - 0 - 0 - Default - Default ramp-up time (tRXEN), compatible with firmware written for nRF51 - 0 + Input + Pin set as input + 0x0 - Fast - Fast ramp-up (tRXEN,FAST), see electrical specification for more information - 1 + Output + Pin set as output + 0x1 - DTX - Default TX value - 8 - 9 + PIN16 + Pin 16 + 16 + 16 - B1 - Transmit '1' - 0 - - - B0 - Transmit '0' - 1 + Input + Pin set as input + 0x0 - Center - Transmit center frequency - 2 + Output + Pin set as output + 0x1 - - - - SFD - IEEE 802.15.4 start of frame delimiter - 0x660 - read-write - 0x000000A7 - - - SFD - IEEE 802.15.4 start of frame delimiter - 0 - 7 - - - - - EDCNT - IEEE 802.15.4 energy detect loop count - 0x664 - read-write - 0x00000000 - - - EDCNT - IEEE 802.15.4 energy detect loop count - 0 - 20 - - - - - EDSAMPLE - IEEE 802.15.4 energy detect level - 0x668 - read-write - 0x00000000 - - - EDLVL - IEEE 802.15.4 energy detect level - 0 - 7 - - - - - CCACTRL - IEEE 802.15.4 clear channel assessment control - 0x66C - read-write - 0x00000000 - - CCAMODE - CCA mode of operation - 0 - 2 + PIN17 + Pin 17 + 17 + 17 - EdMode - Energy above threshold - 0 + Input + Pin set as input + 0x0 - CarrierMode - Carrier seen - 1 + Output + Pin set as output + 0x1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Input + Pin set as input + 0x0 - CarrierAndEdMode - Energy above threshold AND carrier seen - 2 + Output + Pin set as output + 0x1 + + + + PIN19 + Pin 19 + 19 + 19 + - CarrierOrEdMode - Energy above threshold OR carrier seen - 3 + Input + Pin set as input + 0x0 - EdModeTest1 - Energy above threshold test mode that will abort when first ED measurement over threshold is seen. No averaging. - 4 + Output + Pin set as output + 0x1 - CCAEDTHRES - CCA energy busy threshold. Used in all the CCA modes except CarrierMode. - 8 - 15 - - - CCACORRTHRES - CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode and CarrierOrEdMode. - 16 - 23 - - - CCACORRCNT - Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect is enabled. - 24 - 31 - - - - - POWER - Peripheral power control - 0xFFC - read-write - 0x00000001 - - - POWER - Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. - 0 - 0 + PIN20 + Pin 20 + 20 + 20 - Disabled - Peripheral is powered off - 0 + Input + Pin set as input + 0x0 - Enabled - Peripheral is powered on - 1 + Output + Pin set as output + 0x1 - - - - - - UART0 - Universal Asynchronous Receiver/Transmitter - 0x40002000 - UART - - 0 - 0x1000 - registers - - - UARTE0_UART0 - 2 - - UART - 0x20 - - - TASKS_STARTRX - Start UART receiver - 0x000 - write-only - - - TASKS_STARTRX - 0 - 0 - - - - - TASKS_STOPRX - Stop UART receiver - 0x004 - write-only - - - TASKS_STOPRX - 0 - 0 - - - - - TASKS_STARTTX - Start UART transmitter - 0x008 - write-only - - TASKS_STARTTX - 0 - 0 + PIN21 + Pin 21 + 21 + 21 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + - - - - TASKS_STOPTX - Stop UART transmitter - 0x00C - write-only - - TASKS_STOPTX - 0 - 0 + PIN22 + Pin 22 + 22 + 22 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + - - - - TASKS_SUSPEND - Suspend UART - 0x01C - write-only - - TASKS_SUSPEND - 0 - 0 + PIN23 + Pin 23 + 23 + 23 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + - - - - EVENTS_CTS - CTS is activated (set low). Clear To Send. - 0x100 - read-write - - EVENTS_CTS - 0 - 0 + PIN24 + Pin 24 + 24 + 24 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + - - - - EVENTS_NCTS - CTS is deactivated (set high). Not Clear To Send. - 0x104 - read-write - - EVENTS_NCTS - 0 - 0 + PIN25 + Pin 25 + 25 + 25 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + - - - - EVENTS_RXDRDY - Data received in RXD - 0x108 - read-write - - EVENTS_RXDRDY - 0 - 0 + PIN26 + Pin 26 + 26 + 26 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + - - - - EVENTS_TXDRDY - Data sent from TXD - 0x11C - read-write - - EVENTS_TXDRDY - 0 - 0 + PIN27 + Pin 27 + 27 + 27 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + - - - - EVENTS_ERROR - Error detected - 0x124 - read-write - - EVENTS_ERROR - 0 - 0 + PIN28 + Pin 28 + 28 + 28 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + - - - - EVENTS_RXTO - Receiver timeout - 0x144 - read-write - - EVENTS_RXTO - 0 - 0 + PIN29 + Pin 29 + 29 + 29 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + - - - - SHORTS - Shortcut register - 0x200 - read-write - - CTS_STARTRX - Shortcut between CTS event and STARTRX task - 3 - 3 + PIN30 + Pin 30 + 30 + 30 - Disabled - Disable shortcut - 0 + Input + Pin set as input + 0x0 - Enabled - Enable shortcut - 1 + Output + Pin set as output + 0x1 - NCTS_STOPRX - Shortcut between NCTS event and STOPRX task - 4 - 4 + PIN31 + Pin 31 + 31 + 31 - Disabled - Disable shortcut - 0 + Input + Pin set as input + 0x0 - Enabled - Enable shortcut - 1 + Output + Pin set as output + 0x1 - INTENSET - Enable interrupt - 0x304 + DIRSET + DIR set register + 0x518 read-write + 0x00000000 + oneToSet + 0x20 - CTS - Write '1' to enable interrupt for CTS event + PIN0 + Set as output pin 0 0 0 read - Disabled - Read: Disabled - 0 + Input + Read: pin set as input + 0x0 - Enabled - Read: Enabled - 1 + Output + Read: pin set as output + 0x1 write Set - Enable - 1 + Write: a '1' sets pin to output; a '0' has no effect + 0x1 - NCTS - Write '1' to enable interrupt for NCTS event + PIN1 + Set as output pin 1 1 1 read - Disabled - Read: Disabled - 0 + Input + Read: pin set as input + 0x0 - Enabled - Read: Enabled - 1 + Output + Read: pin set as output + 0x1 write Set - Enable - 1 + Write: a '1' sets pin to output; a '0' has no effect + 0x1 - RXDRDY - Write '1' to enable interrupt for RXDRDY event + PIN2 + Set as output pin 2 2 2 read - Disabled - Read: Disabled - 0 + Input + Read: pin set as input + 0x0 - Enabled - Read: Enabled - 1 + Output + Read: pin set as output + 0x1 write Set - Enable - 1 + Write: a '1' sets pin to output; a '0' has no effect + 0x1 - TXDRDY - Write '1' to enable interrupt for TXDRDY event - 7 - 7 + PIN3 + Set as output pin 3 + 3 + 3 read - Disabled - Read: Disabled - 0 + Input + Read: pin set as input + 0x0 - Enabled - Read: Enabled - 1 + Output + Read: pin set as output + 0x1 write Set - Enable - 1 + Write: a '1' sets pin to output; a '0' has no effect + 0x1 - ERROR - Write '1' to enable interrupt for ERROR event - 9 - 9 + PIN4 + Set as output pin 4 + 4 + 4 read - Disabled - Read: Disabled - 0 + Input + Read: pin set as input + 0x0 - Enabled - Read: Enabled - 1 + Output + Read: pin set as output + 0x1 write Set - Enable - 1 + Write: a '1' sets pin to output; a '0' has no effect + 0x1 - RXTO - Write '1' to enable interrupt for RXTO event - 17 - 17 + PIN5 + Set as output pin 5 + 5 + 5 read - Disabled - Read: Disabled - 0 + Input + Read: pin set as input + 0x0 - Enabled - Read: Enabled - 1 + Output + Read: pin set as output + 0x1 write Set - Enable - 1 + Write: a '1' sets pin to output; a '0' has no effect + 0x1 - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - CTS - Write '1' to disable interrupt for CTS event - 0 - 0 + PIN6 + Set as output pin 6 + 6 + 6 read - Disabled - Read: Disabled - 0 + Input + Read: pin set as input + 0x0 - Enabled - Read: Enabled - 1 + Output + Read: pin set as output + 0x1 write - Clear - Disable - 1 + Set + Write: a '1' sets pin to output; a '0' has no effect + 0x1 - NCTS - Write '1' to disable interrupt for NCTS event - 1 - 1 + PIN7 + Set as output pin 7 + 7 + 7 read - Disabled - Read: Disabled - 0 + Input + Read: pin set as input + 0x0 - Enabled - Read: Enabled - 1 + Output + Read: pin set as output + 0x1 write - Clear - Disable - 1 + Set + Write: a '1' sets pin to output; a '0' has no effect + 0x1 - RXDRDY - Write '1' to disable interrupt for RXDRDY event - 2 - 2 + PIN8 + Set as output pin 8 + 8 + 8 read - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 write - Clear - Disable - 1 + Set + Write: a '1' sets pin to output; a '0' has no effect + 0x1 - TXDRDY - Write '1' to disable interrupt for TXDRDY event - 7 - 7 + PIN9 + Set as output pin 9 + 9 + 9 read - Disabled - Read: Disabled - 0 + Input + Read: pin set as input + 0x0 - Enabled - Read: Enabled - 1 + Output + Read: pin set as output + 0x1 write - Clear - Disable - 1 + Set + Write: a '1' sets pin to output; a '0' has no effect + 0x1 - ERROR - Write '1' to disable interrupt for ERROR event - 9 - 9 + PIN10 + Set as output pin 10 + 10 + 10 read - Disabled - Read: Disabled - 0 + Input + Read: pin set as input + 0x0 - Enabled - Read: Enabled - 1 + Output + Read: pin set as output + 0x1 write - Clear - Disable - 1 + Set + Write: a '1' sets pin to output; a '0' has no effect + 0x1 - RXTO - Write '1' to disable interrupt for RXTO event - 17 - 17 + PIN11 + Set as output pin 11 + 11 + 11 read - Disabled - Read: Disabled - 0 + Input + Read: pin set as input + 0x0 - Enabled - Read: Enabled - 1 + Output + Read: pin set as output + 0x1 write - Clear - Disable - 1 + Set + Write: a '1' sets pin to output; a '0' has no effect + 0x1 - - - - ERRORSRC - Error source - 0x480 - read-write - oneToClear - - OVERRUN - Overrun error - 0 - 0 + PIN12 + Set as output pin 12 + 12 + 12 read - NotPresent - Read: error not present - 0 + Input + Read: pin set as input + 0x0 - Present - Read: error present - 1 + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 0x1 - PARITY - Parity error - 1 - 1 + PIN13 + Set as output pin 13 + 13 + 13 read - NotPresent - Read: error not present - 0 + Input + Read: pin set as input + 0x0 - Present - Read: error present - 1 + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 0x1 - FRAMING - Framing error occurred - 2 - 2 + PIN14 + Set as output pin 14 + 14 + 14 read - NotPresent - Read: error not present - 0 + Input + Read: pin set as input + 0x0 - Present - Read: error present - 1 + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 0x1 - BREAK - Break condition - 3 - 3 + PIN15 + Set as output pin 15 + 15 + 15 read - NotPresent - Read: error not present - 0 + Input + Read: pin set as input + 0x0 - Present - Read: error present - 1 + Output + Read: pin set as output + 0x1 - - - - - ENABLE - Enable UART - 0x500 - read-write - - - ENABLE - Enable or disable UART - 0 - 3 + write - Disabled - Disable UART - 0 - - - Enabled - Enable UART - 4 + Set + Write: a '1' sets pin to output; a '0' has no effect + 0x1 - - - - PSEL - Unspecified - UART_PSEL - 0x508 - - RTS - Pin select for RTS - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - TXD - Pin select for TXD - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - CTS - Pin select for CTS - 0x008 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - RXD - Pin select for RXD - 0x00C - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - RXD - RXD register - 0x518 - read-only - modifyExternal - - - RXD - RX data received in previous transfers, double buffered - 0 - 7 - - - - - TXD - TXD register - 0x51C - write-only - - - TXD - TX data to be transferred - 0 - 7 - - - - - BAUDRATE - Baud rate. Accuracy depends on the HFCLK source selected. - 0x524 - read-write - 0x04000000 - - BAUDRATE - Baud rate - 0 - 31 + PIN16 + Set as output pin 16 + 16 + 16 + read - Baud1200 - 1200 baud (actual rate: 1205) - 0x0004F000 + Input + Read: pin set as input + 0x0 - Baud2400 - 2400 baud (actual rate: 2396) - 0x0009D000 + Output + Read: pin set as output + 0x1 + + + write - Baud4800 - 4800 baud (actual rate: 4808) - 0x0013B000 + Set + Write: a '1' sets pin to output; a '0' has no effect + 0x1 + + + + PIN17 + Set as output pin 17 + 17 + 17 + + read - Baud9600 - 9600 baud (actual rate: 9598) - 0x00275000 + Input + Read: pin set as input + 0x0 - Baud14400 - 14400 baud (actual rate: 14414) - 0x003B0000 + Output + Read: pin set as output + 0x1 + + + write - Baud19200 - 19200 baud (actual rate: 19208) - 0x004EA000 + Set + Write: a '1' sets pin to output; a '0' has no effect + 0x1 + + + + PIN18 + Set as output pin 18 + 18 + 18 + + read - Baud28800 - 28800 baud (actual rate: 28829) - 0x0075F000 + Input + Read: pin set as input + 0x0 - Baud31250 - 31250 baud - 0x00800000 + Output + Read: pin set as output + 0x1 + + + write - Baud38400 - 38400 baud (actual rate: 38462) - 0x009D5000 + Set + Write: a '1' sets pin to output; a '0' has no effect + 0x1 + + + + PIN19 + Set as output pin 19 + 19 + 19 + + read - Baud56000 - 56000 baud (actual rate: 55944) - 0x00E50000 + Input + Read: pin set as input + 0x0 - Baud57600 - 57600 baud (actual rate: 57762) - 0x00EBF000 + Output + Read: pin set as output + 0x1 + + + write - Baud76800 - 76800 baud (actual rate: 76923) - 0x013A9000 + Set + Write: a '1' sets pin to output; a '0' has no effect + 0x1 + + + + PIN20 + Set as output pin 20 + 20 + 20 + + read - Baud115200 - 115200 baud (actual rate: 115942) - 0x01D7E000 + Input + Read: pin set as input + 0x0 - Baud230400 - 230400 baud (actual rate: 231884) - 0x03AFB000 + Output + Read: pin set as output + 0x1 + + + write - Baud250000 - 250000 baud - 0x04000000 + Set + Write: a '1' sets pin to output; a '0' has no effect + 0x1 + + + + PIN21 + Set as output pin 21 + 21 + 21 + + read - Baud460800 - 460800 baud (actual rate: 470588) - 0x075F7000 + Input + Read: pin set as input + 0x0 - Baud921600 - 921600 baud (actual rate: 941176) - 0x0EBED000 + Output + Read: pin set as output + 0x1 + + + write - Baud1M - 1Mega baud - 0x10000000 + Set + Write: a '1' sets pin to output; a '0' has no effect + 0x1 - - - - CONFIG - Configuration of parity and hardware flow control - 0x56C - read-write - - HWFC - Hardware flow control - 0 - 0 + PIN22 + Set as output pin 22 + 22 + 22 + read - Disabled - Disabled - 0 + Input + Read: pin set as input + 0x0 - Enabled - Enabled - 1 + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 0x1 - PARITY - Parity - 1 - 3 + PIN23 + Set as output pin 23 + 23 + 23 + read - Excluded - Exclude parity bit + Input + Read: pin set as input 0x0 - Included - Include parity bit - 0x7 + Output + Read: pin set as output + 0x1 - - - - - - - UARTE0 - UART with EasyDMA 0 - 0x40002000 - UART0 - UARTE - - 0 - 0x1000 - registers - - - UARTE0_UART0 - 2 - - UARTE - 0x20 - - - TASKS_STARTRX - Start UART receiver - 0x000 - write-only - - - TASKS_STARTRX - 0 - 0 - - - - - TASKS_STOPRX - Stop UART receiver - 0x004 - write-only - - - TASKS_STOPRX - 0 - 0 - - - - - TASKS_STARTTX - Start UART transmitter - 0x008 - write-only - - - TASKS_STARTTX - 0 - 0 - - - - - TASKS_STOPTX - Stop UART transmitter - 0x00C - write-only - - - TASKS_STOPTX - 0 - 0 - - - - - TASKS_FLUSHRX - Flush RX FIFO into RX buffer - 0x02C - write-only - - - TASKS_FLUSHRX - 0 - 0 - - - - - EVENTS_CTS - CTS is activated (set low). Clear To Send. - 0x100 - read-write - - - EVENTS_CTS - 0 - 0 - - - - - EVENTS_NCTS - CTS is deactivated (set high). Not Clear To Send. - 0x104 - read-write - - - EVENTS_NCTS - 0 - 0 - - - - - EVENTS_RXDRDY - Data received in RXD (but potentially not yet transferred to Data RAM) - 0x108 - read-write - - - EVENTS_RXDRDY - 0 - 0 - - - - - EVENTS_ENDRX - Receive buffer is filled up - 0x110 - read-write - - - EVENTS_ENDRX - 0 - 0 - - - - - EVENTS_TXDRDY - Data sent from TXD - 0x11C - read-write - - - EVENTS_TXDRDY - 0 - 0 - - - - - EVENTS_ENDTX - Last TX byte transmitted - 0x120 - read-write - - - EVENTS_ENDTX - 0 - 0 - - - - - EVENTS_ERROR - Error detected - 0x124 - read-write - - - EVENTS_ERROR - 0 - 0 - - - - - EVENTS_RXTO - Receiver timeout - 0x144 - read-write - - - EVENTS_RXTO - 0 - 0 - - - - - EVENTS_RXSTARTED - UART receiver has started - 0x14C - read-write - - - EVENTS_RXSTARTED - 0 - 0 - - - - - EVENTS_TXSTARTED - UART transmitter has started - 0x150 - read-write - - - EVENTS_TXSTARTED - 0 - 0 - - - - - EVENTS_TXSTOPPED - Transmitter stopped - 0x158 - read-write - - - EVENTS_TXSTOPPED - 0 - 0 - - - - - SHORTS - Shortcut register - 0x200 - read-write - - - ENDRX_STARTRX - Shortcut between ENDRX event and STARTRX task - 5 - 5 + write - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 + Set + Write: a '1' sets pin to output; a '0' has no effect + 0x1 - ENDRX_STOPRX - Shortcut between ENDRX event and STOPRX task - 6 - 6 + PIN24 + Set as output pin 24 + 24 + 24 + read - Disabled - Disable shortcut - 0 + Input + Read: pin set as input + 0x0 - Enabled - Enable shortcut - 1 + Output + Read: pin set as output + 0x1 - - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - - CTS - Enable or disable interrupt for CTS event - 0 - 0 + write - Disabled - Disable - 0 - - - Enabled - Enable - 1 + Set + Write: a '1' sets pin to output; a '0' has no effect + 0x1 - NCTS - Enable or disable interrupt for NCTS event - 1 - 1 + PIN25 + Set as output pin 25 + 25 + 25 + read - Disabled - Disable - 0 + Input + Read: pin set as input + 0x0 - Enabled - Enable - 1 + Output + Read: pin set as output + 0x1 - - - RXDRDY - Enable or disable interrupt for RXDRDY event - 2 - 2 + write - Disabled - Disable - 0 - - - Enabled - Enable - 1 + Set + Write: a '1' sets pin to output; a '0' has no effect + 0x1 - ENDRX - Enable or disable interrupt for ENDRX event - 4 - 4 + PIN26 + Set as output pin 26 + 26 + 26 + read - Disabled - Disable - 0 + Input + Read: pin set as input + 0x0 - Enabled - Enable - 1 + Output + Read: pin set as output + 0x1 - - - TXDRDY - Enable or disable interrupt for TXDRDY event - 7 - 7 + write - Disabled - Disable - 0 - - - Enabled - Enable - 1 + Set + Write: a '1' sets pin to output; a '0' has no effect + 0x1 - ENDTX - Enable or disable interrupt for ENDTX event - 8 - 8 + PIN27 + Set as output pin 27 + 27 + 27 + read - Disabled - Disable - 0 + Input + Read: pin set as input + 0x0 - Enabled - Enable - 1 + Output + Read: pin set as output + 0x1 - - - ERROR - Enable or disable interrupt for ERROR event - 9 - 9 + write - Disabled - Disable - 0 - - - Enabled - Enable - 1 + Set + Write: a '1' sets pin to output; a '0' has no effect + 0x1 - RXTO - Enable or disable interrupt for RXTO event - 17 - 17 + PIN28 + Set as output pin 28 + 28 + 28 + read - Disabled - Disable - 0 + Input + Read: pin set as input + 0x0 - Enabled - Enable - 1 + Output + Read: pin set as output + 0x1 - - - RXSTARTED - Enable or disable interrupt for RXSTARTED event - 19 - 19 + write - Disabled - Disable - 0 - - - Enabled - Enable - 1 + Set + Write: a '1' sets pin to output; a '0' has no effect + 0x1 - TXSTARTED - Enable or disable interrupt for TXSTARTED event - 20 - 20 + PIN29 + Set as output pin 29 + 29 + 29 + read - Disabled - Disable - 0 + Input + Read: pin set as input + 0x0 - Enabled - Enable - 1 + Output + Read: pin set as output + 0x1 - - - TXSTOPPED - Enable or disable interrupt for TXSTOPPED event - 22 - 22 + write - Disabled - Disable - 0 - - - Enabled - Enable - 1 + Set + Write: a '1' sets pin to output; a '0' has no effect + 0x1 + + + + + PIN30 + Set as output pin 30 + 30 + 30 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 0x1 + + + + + PIN31 + Set as output pin 31 + 31 + 31 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 0x1 - INTENSET - Enable interrupt - 0x304 + DIRCLR + DIR clear register + 0x51C read-write + 0x00000000 + oneToClear + 0x20 - CTS - Write '1' to enable interrupt for CTS event + PIN0 + Set as input pin 0 0 0 read - Disabled - Read: Disabled - 0 + Input + Read: pin set as input + 0x0 - Enabled - Read: Enabled - 1 + Output + Read: pin set as output + 0x1 write - Set - Enable - 1 + Clear + Write: a '1' sets pin to input; a '0' has no effect + 0x1 - NCTS - Write '1' to enable interrupt for NCTS event + PIN1 + Set as input pin 1 1 1 read - Disabled - Read: Disabled - 0 + Input + Read: pin set as input + 0x0 - Enabled - Read: Enabled - 1 + Output + Read: pin set as output + 0x1 write - Set - Enable - 1 + Clear + Write: a '1' sets pin to input; a '0' has no effect + 0x1 - RXDRDY - Write '1' to enable interrupt for RXDRDY event + PIN2 + Set as input pin 2 2 2 read - Disabled - Read: Disabled - 0 + Input + Read: pin set as input + 0x0 - Enabled - Read: Enabled - 1 + Output + Read: pin set as output + 0x1 write - Set - Enable - 1 + Clear + Write: a '1' sets pin to input; a '0' has no effect + 0x1 - ENDRX - Write '1' to enable interrupt for ENDRX event - 4 - 4 + PIN3 + Set as input pin 3 + 3 + 3 read - Disabled - Read: Disabled - 0 + Input + Read: pin set as input + 0x0 - Enabled - Read: Enabled - 1 + Output + Read: pin set as output + 0x1 write - Set - Enable - 1 + Clear + Write: a '1' sets pin to input; a '0' has no effect + 0x1 - TXDRDY - Write '1' to enable interrupt for TXDRDY event - 7 - 7 + PIN4 + Set as input pin 4 + 4 + 4 read - Disabled - Read: Disabled - 0 + Input + Read: pin set as input + 0x0 - Enabled - Read: Enabled - 1 + Output + Read: pin set as output + 0x1 write - Set - Enable - 1 + Clear + Write: a '1' sets pin to input; a '0' has no effect + 0x1 - ENDTX - Write '1' to enable interrupt for ENDTX event - 8 - 8 + PIN5 + Set as input pin 5 + 5 + 5 read - Disabled - Read: Disabled - 0 + Input + Read: pin set as input + 0x0 - Enabled - Read: Enabled - 1 + Output + Read: pin set as output + 0x1 write - Set - Enable - 1 + Clear + Write: a '1' sets pin to input; a '0' has no effect + 0x1 - ERROR - Write '1' to enable interrupt for ERROR event - 9 - 9 + PIN6 + Set as input pin 6 + 6 + 6 read - Disabled - Read: Disabled - 0 + Input + Read: pin set as input + 0x0 - Enabled - Read: Enabled - 1 + Output + Read: pin set as output + 0x1 write - Set - Enable - 1 + Clear + Write: a '1' sets pin to input; a '0' has no effect + 0x1 - RXTO - Write '1' to enable interrupt for RXTO event - 17 - 17 + PIN7 + Set as input pin 7 + 7 + 7 read - Disabled - Read: Disabled - 0 + Input + Read: pin set as input + 0x0 - Enabled - Read: Enabled - 1 + Output + Read: pin set as output + 0x1 write - Set - Enable - 1 + Clear + Write: a '1' sets pin to input; a '0' has no effect + 0x1 - RXSTARTED - Write '1' to enable interrupt for RXSTARTED event - 19 - 19 + PIN8 + Set as input pin 8 + 8 + 8 read - Disabled - Read: Disabled - 0 + Input + Read: pin set as input + 0x0 - Enabled - Read: Enabled - 1 + Output + Read: pin set as output + 0x1 write - Set - Enable - 1 + Clear + Write: a '1' sets pin to input; a '0' has no effect + 0x1 - TXSTARTED - Write '1' to enable interrupt for TXSTARTED event - 20 - 20 + PIN9 + Set as input pin 9 + 9 + 9 read - Disabled - Read: Disabled - 0 + Input + Read: pin set as input + 0x0 - Enabled - Read: Enabled - 1 + Output + Read: pin set as output + 0x1 write - Set - Enable - 1 + Clear + Write: a '1' sets pin to input; a '0' has no effect + 0x1 - TXSTOPPED - Write '1' to enable interrupt for TXSTOPPED event - 22 - 22 + PIN10 + Set as input pin 10 + 10 + 10 read - Disabled - Read: Disabled - 0 + Input + Read: pin set as input + 0x0 - Enabled - Read: Enabled - 1 + Output + Read: pin set as output + 0x1 write - Set - Enable - 1 + Clear + Write: a '1' sets pin to input; a '0' has no effect + 0x1 - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - CTS - Write '1' to disable interrupt for CTS event - 0 - 0 + PIN11 + Set as input pin 11 + 11 + 11 read - Disabled - Read: Disabled - 0 + Input + Read: pin set as input + 0x0 - Enabled - Read: Enabled - 1 + Output + Read: pin set as output + 0x1 write Clear - Disable - 1 + Write: a '1' sets pin to input; a '0' has no effect + 0x1 - NCTS - Write '1' to disable interrupt for NCTS event - 1 - 1 + PIN12 + Set as input pin 12 + 12 + 12 read - Disabled - Read: Disabled - 0 + Input + Read: pin set as input + 0x0 - Enabled - Read: Enabled - 1 + Output + Read: pin set as output + 0x1 write Clear - Disable - 1 + Write: a '1' sets pin to input; a '0' has no effect + 0x1 - RXDRDY - Write '1' to disable interrupt for RXDRDY event - 2 - 2 + PIN13 + Set as input pin 13 + 13 + 13 read - Disabled - Read: Disabled - 0 + Input + Read: pin set as input + 0x0 - Enabled - Read: Enabled - 1 + Output + Read: pin set as output + 0x1 write Clear - Disable - 1 + Write: a '1' sets pin to input; a '0' has no effect + 0x1 - ENDRX - Write '1' to disable interrupt for ENDRX event - 4 - 4 + PIN14 + Set as input pin 14 + 14 + 14 read - Disabled - Read: Disabled - 0 + Input + Read: pin set as input + 0x0 - Enabled - Read: Enabled - 1 + Output + Read: pin set as output + 0x1 write Clear - Disable - 1 + Write: a '1' sets pin to input; a '0' has no effect + 0x1 - TXDRDY - Write '1' to disable interrupt for TXDRDY event - 7 - 7 + PIN15 + Set as input pin 15 + 15 + 15 read - Disabled - Read: Disabled - 0 + Input + Read: pin set as input + 0x0 - Enabled - Read: Enabled - 1 + Output + Read: pin set as output + 0x1 write Clear - Disable - 1 + Write: a '1' sets pin to input; a '0' has no effect + 0x1 - ENDTX - Write '1' to disable interrupt for ENDTX event - 8 - 8 + PIN16 + Set as input pin 16 + 16 + 16 read - Disabled - Read: Disabled - 0 + Input + Read: pin set as input + 0x0 - Enabled - Read: Enabled - 1 + Output + Read: pin set as output + 0x1 write Clear - Disable - 1 + Write: a '1' sets pin to input; a '0' has no effect + 0x1 - ERROR - Write '1' to disable interrupt for ERROR event - 9 - 9 + PIN17 + Set as input pin 17 + 17 + 17 read - Disabled - Read: Disabled - 0 + Input + Read: pin set as input + 0x0 - Enabled - Read: Enabled - 1 + Output + Read: pin set as output + 0x1 write Clear - Disable - 1 + Write: a '1' sets pin to input; a '0' has no effect + 0x1 - RXTO - Write '1' to disable interrupt for RXTO event - 17 - 17 + PIN18 + Set as input pin 18 + 18 + 18 read - Disabled - Read: Disabled - 0 + Input + Read: pin set as input + 0x0 - Enabled - Read: Enabled - 1 + Output + Read: pin set as output + 0x1 write Clear - Disable - 1 + Write: a '1' sets pin to input; a '0' has no effect + 0x1 - RXSTARTED - Write '1' to disable interrupt for RXSTARTED event + PIN19 + Set as input pin 19 19 19 read - Disabled - Read: Disabled - 0 + Input + Read: pin set as input + 0x0 - Enabled - Read: Enabled - 1 + Output + Read: pin set as output + 0x1 write Clear - Disable - 1 + Write: a '1' sets pin to input; a '0' has no effect + 0x1 - TXSTARTED - Write '1' to disable interrupt for TXSTARTED event + PIN20 + Set as input pin 20 20 20 read - Disabled - Read: Disabled - 0 + Input + Read: pin set as input + 0x0 - Enabled - Read: Enabled - 1 + Output + Read: pin set as output + 0x1 write Clear - Disable - 1 + Write: a '1' sets pin to input; a '0' has no effect + 0x1 - TXSTOPPED - Write '1' to disable interrupt for TXSTOPPED event - 22 - 22 + PIN21 + Set as input pin 21 + 21 + 21 read - Disabled - Read: Disabled - 0 + Input + Read: pin set as input + 0x0 - Enabled - Read: Enabled - 1 + Output + Read: pin set as output + 0x1 write Clear - Disable - 1 + Write: a '1' sets pin to input; a '0' has no effect + 0x1 - - - - ERRORSRC - Error source Note : this register is read / write one to clear. - 0x480 - read-write - oneToClear - - OVERRUN - Overrun error - 0 - 0 + PIN22 + Set as input pin 22 + 22 + 22 read - NotPresent - Read: error not present - 0 + Input + Read: pin set as input + 0x0 - Present - Read: error present - 1 + Output + Read: pin set as output + 0x1 - - - PARITY - Parity error - 1 - 1 - read - - NotPresent - Read: error not present - 0 - + write - Present - Read: error present - 1 + Clear + Write: a '1' sets pin to input; a '0' has no effect + 0x1 - FRAMING - Framing error occurred - 2 - 2 + PIN23 + Set as input pin 23 + 23 + 23 read - NotPresent - Read: error not present - 0 + Input + Read: pin set as input + 0x0 - Present - Read: error present - 1 + Output + Read: pin set as output + 0x1 - - - BREAK - Break condition - 3 - 3 - read - - NotPresent - Read: error not present - 0 - + write - Present - Read: error present - 1 + Clear + Write: a '1' sets pin to input; a '0' has no effect + 0x1 - - - - ENABLE - Enable UART - 0x500 - read-write - - ENABLE - Enable or disable UARTE - 0 - 3 + PIN24 + Set as input pin 24 + 24 + 24 + read - Disabled - Disable UARTE - 0 + Input + Read: pin set as input + 0x0 - Enabled - Enable UARTE - 8 + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 0x1 - - - - PSEL - Unspecified - UARTE_PSEL - 0x508 - - RTS - Pin select for RTS signal - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - TXD - Pin select for TXD signal - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - CTS - Pin select for CTS signal - 0x008 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - RXD - Pin select for RXD signal - 0x00C - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - BAUDRATE - Baud rate. Accuracy depends on the HFCLK source selected. - 0x524 - read-write - 0x04000000 - - BAUDRATE - Baud rate - 0 - 31 + PIN25 + Set as input pin 25 + 25 + 25 + read - Baud1200 - 1200 baud (actual rate: 1205) - 0x0004F000 + Input + Read: pin set as input + 0x0 - Baud2400 - 2400 baud (actual rate: 2396) - 0x0009D000 + Output + Read: pin set as output + 0x1 + + + write - Baud4800 - 4800 baud (actual rate: 4808) - 0x0013B000 + Clear + Write: a '1' sets pin to input; a '0' has no effect + 0x1 + + + + PIN26 + Set as input pin 26 + 26 + 26 + + read - Baud9600 - 9600 baud (actual rate: 9598) - 0x00275000 + Input + Read: pin set as input + 0x0 - Baud14400 - 14400 baud (actual rate: 14401) - 0x003AF000 + Output + Read: pin set as output + 0x1 + + + write - Baud19200 - 19200 baud (actual rate: 19208) - 0x004EA000 + Clear + Write: a '1' sets pin to input; a '0' has no effect + 0x1 + + + + + PIN27 + Set as input pin 27 + 27 + 27 + + read + + Input + Read: pin set as input + 0x0 - Baud28800 - 28800 baud (actual rate: 28777) - 0x0075C000 + Output + Read: pin set as output + 0x1 + + + write - Baud31250 - 31250 baud - 0x00800000 + Clear + Write: a '1' sets pin to input; a '0' has no effect + 0x1 + + + + PIN28 + Set as input pin 28 + 28 + 28 + + read - Baud38400 - 38400 baud (actual rate: 38369) - 0x009D0000 + Input + Read: pin set as input + 0x0 - Baud56000 - 56000 baud (actual rate: 55944) - 0x00E50000 + Output + Read: pin set as output + 0x1 + + + write - Baud57600 - 57600 baud (actual rate: 57554) - 0x00EB0000 + Clear + Write: a '1' sets pin to input; a '0' has no effect + 0x1 + + + + PIN29 + Set as input pin 29 + 29 + 29 + + read - Baud76800 - 76800 baud (actual rate: 76923) - 0x013A9000 + Input + Read: pin set as input + 0x0 - Baud115200 - 115200 baud (actual rate: 115108) - 0x01D60000 + Output + Read: pin set as output + 0x1 + + + write - Baud230400 - 230400 baud (actual rate: 231884) - 0x03B00000 + Clear + Write: a '1' sets pin to input; a '0' has no effect + 0x1 + + + + PIN30 + Set as input pin 30 + 30 + 30 + + read - Baud250000 - 250000 baud - 0x04000000 + Input + Read: pin set as input + 0x0 - Baud460800 - 460800 baud (actual rate: 457143) - 0x07400000 + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 0x1 + + + + PIN31 + Set as input pin 31 + 31 + 31 + + read - Baud921600 - 921600 baud (actual rate: 941176) - 0x0F000000 + Input + Read: pin set as input + 0x0 - Baud1M - 1Mega baud - 0x10000000 + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 0x1 - - RXD - RXD EasyDMA channel - UARTE_RXD - 0x534 - - PTR - Data pointer - 0x000 - read-write - - - PTR - Data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in receive buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in receive buffer - 0 - 15 - - - - - AMOUNT - Number of bytes transferred in the last transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last transaction - 0 - 15 - - - - - - TXD - TXD EasyDMA channel - UARTE_TXD - 0x544 - - PTR - Data pointer - 0x000 - read-write - - - PTR - Data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in transmit buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in transmit buffer - 0 - 15 - - - - - AMOUNT - Number of bytes transferred in the last transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last transaction - 0 - 15 - - - - - CONFIG - Configuration of parity and hardware flow control - 0x56C + LATCH + Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers + 0x520 read-write + 0x00000000 + 0x20 - HWFC - Hardware flow control + PIN0 + Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. 0 0 - Disabled - Disabled - 0 + NotLatched + Criteria has not been met + 0x0 - Enabled - Enabled - 1 + Latched + Criteria has been met + 0x1 - PARITY - Parity + PIN1 + Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. 1 - 3 + 1 - Excluded - Exclude parity bit + NotLatched + Criteria has not been met 0x0 - Included - Include even parity bit - 0x7 + Latched + Criteria has been met + 0x1 - STOP - Stop bits + PIN2 + Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. + 2 + 2 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN3 + Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. + 3 + 3 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN4 + Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. 4 4 - One - One stop bit - 0 + NotLatched + Criteria has not been met + 0x0 - Two - Two stop bits - 1 + Latched + Criteria has been met + 0x1 - - - - - - SPI0 - Serial Peripheral Interface 0 - 0x40003000 - SPI - - 0 - 0x1000 - registers - - - SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 - 3 - - SPI - 0x20 - - - EVENTS_READY - TXD byte sent and RXD byte received - 0x108 - read-write - - EVENTS_READY - 0 - 0 + PIN5 + Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. + 5 + 5 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + - - - - INTENSET - Enable interrupt - 0x304 - read-write - - READY - Write '1' to enable interrupt for READY event - 2 - 2 + PIN6 + Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. + 6 + 6 - read - Disabled - Read: Disabled - 0 + NotLatched + Criteria has not been met + 0x0 - Enabled - Read: Enabled - 1 + Latched + Criteria has been met + 0x1 + + + PIN7 + Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. + 7 + 7 - write - Set - Enable - 1 + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - READY - Write '1' to disable interrupt for READY event - 2 - 2 + PIN8 + Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. + 8 + 8 - read - Disabled - Read: Disabled - 0 + NotLatched + Criteria has not been met + 0x0 - Enabled - Read: Enabled - 1 + Latched + Criteria has been met + 0x1 + + + PIN9 + Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. + 9 + 9 - write - Clear - Disable - 1 + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 - - - - ENABLE - Enable SPI - 0x500 - read-write - - ENABLE - Enable or disable SPI - 0 - 3 + PIN10 + Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. + 10 + 10 - Disabled - Disable SPI - 0 + NotLatched + Criteria has not been met + 0x0 - Enabled - Enable SPI - 1 + Latched + Criteria has been met + 0x1 - - - - PSEL - Unspecified - SPI_PSEL - 0x508 - - SCK - Pin select for SCK - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - MOSI - Pin select for MOSI signal - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - MISO - Pin select for MISO signal - 0x008 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - RXD - RXD register - 0x518 - read-only - modifyExternal - - RXD - RX data received. Double buffered - 0 - 7 + PIN11 + Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. + 11 + 11 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + - - - - TXD - TXD register - 0x51C - read-write - - TXD - TX data to send. Double buffered - 0 - 7 + PIN12 + Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. + 12 + 12 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + - - - - FREQUENCY - SPI frequency. Accuracy depends on the HFCLK source selected. - 0x524 - read-write - 0x04000000 - - FREQUENCY - SPI master data rate - 0 - 31 + PIN13 + Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. + 13 + 13 - K125 - 125 kbps - 0x02000000 + NotLatched + Criteria has not been met + 0x0 - K250 - 250 kbps - 0x04000000 + Latched + Criteria has been met + 0x1 + + + + PIN14 + Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. + 14 + 14 + - K500 - 500 kbps - 0x08000000 + NotLatched + Criteria has not been met + 0x0 - M1 - 1 Mbps - 0x10000000 + Latched + Criteria has been met + 0x1 + + + + PIN15 + Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. + 15 + 15 + - M2 - 2 Mbps - 0x20000000 + NotLatched + Criteria has not been met + 0x0 - M4 - 4 Mbps - 0x40000000 + Latched + Criteria has been met + 0x1 + + + + PIN16 + Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. + 16 + 16 + - M8 - 8 Mbps - 0x80000000 + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 - - - - CONFIG - Configuration register - 0x554 - read-write - - ORDER - Bit order - 0 - 0 + PIN17 + Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. + 17 + 17 - MsbFirst - Most significant bit shifted out first - 0 + NotLatched + Criteria has not been met + 0x0 - LsbFirst - Least significant bit shifted out first - 1 + Latched + Criteria has been met + 0x1 - CPHA - Serial clock (SCK) phase - 1 - 1 + PIN18 + Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. + 18 + 18 - Leading - Sample on leading edge of clock, shift serial data on trailing edge - 0 + NotLatched + Criteria has not been met + 0x0 - Trailing - Sample on trailing edge of clock, shift serial data on leading edge - 1 + Latched + Criteria has been met + 0x1 - CPOL - Serial clock (SCK) polarity - 2 - 2 + PIN19 + Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. + 19 + 19 - ActiveHigh - Active high - 0 + NotLatched + Criteria has not been met + 0x0 - ActiveLow - Active low - 1 + Latched + Criteria has been met + 0x1 - - - - - - SPIM0 - Serial Peripheral Interface Master with EasyDMA 0 - 0x40003000 - SPI0 - SPIM - - 0 - 0x1000 - registers - - - SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 - 3 - - SPIM - 0x20 - - - TASKS_START - Start SPI transaction - 0x010 - write-only - - - TASKS_START - 0 - 0 - - - - - TASKS_STOP - Stop SPI transaction - 0x014 - write-only - - - TASKS_STOP - 0 - 0 - - - - - TASKS_SUSPEND - Suspend SPI transaction - 0x01C - write-only - - - TASKS_SUSPEND - 0 - 0 - - - - - TASKS_RESUME - Resume SPI transaction - 0x020 - write-only - - - TASKS_RESUME - 0 - 0 - - - - - EVENTS_STOPPED - SPI transaction has stopped - 0x104 - read-write - - - EVENTS_STOPPED - 0 - 0 - - - - - EVENTS_ENDRX - End of RXD buffer reached - 0x110 - read-write - - - EVENTS_ENDRX - 0 - 0 - - - - - EVENTS_END - End of RXD buffer and TXD buffer reached - 0x118 - read-write - - - EVENTS_END - 0 - 0 - - - - - EVENTS_ENDTX - End of TXD buffer reached - 0x120 - read-write - - - EVENTS_ENDTX - 0 - 0 - - - - - EVENTS_STARTED - Transaction started - 0x14C - read-write - - - EVENTS_STARTED - 0 - 0 - - - - - SHORTS - Shortcut register - 0x200 - read-write - - END_START - Shortcut between END event and START task - 17 - 17 + PIN20 + Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. + 20 + 20 - Disabled - Disable shortcut - 0 + NotLatched + Criteria has not been met + 0x0 - Enabled - Enable shortcut - 1 + Latched + Criteria has been met + 0x1 - - - - INTENSET - Enable interrupt - 0x304 - read-write - - STOPPED - Write '1' to enable interrupt for STOPPED event - 1 - 1 + PIN21 + Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. + 21 + 21 - read - - Disabled - Read: Disabled - 0 - - Enabled - Read: Enabled - 1 + NotLatched + Criteria has not been met + 0x0 - - - write - Set - Enable - 1 + Latched + Criteria has been met + 0x1 - ENDRX - Write '1' to enable interrupt for ENDRX event - 4 - 4 + PIN22 + Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. + 22 + 22 - read - - Disabled - Read: Disabled - 0 - - Enabled - Read: Enabled - 1 + NotLatched + Criteria has not been met + 0x0 - - - write - Set - Enable - 1 + Latched + Criteria has been met + 0x1 - END - Write '1' to enable interrupt for END event - 6 - 6 + PIN23 + Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. + 23 + 23 - read - - Disabled - Read: Disabled - 0 - - Enabled - Read: Enabled - 1 + NotLatched + Criteria has not been met + 0x0 - - - write - Set - Enable - 1 + Latched + Criteria has been met + 0x1 - ENDTX - Write '1' to enable interrupt for ENDTX event - 8 - 8 + PIN24 + Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. + 24 + 24 - read - - Disabled - Read: Disabled - 0 - - Enabled - Read: Enabled - 1 + NotLatched + Criteria has not been met + 0x0 - - - write - Set - Enable - 1 + Latched + Criteria has been met + 0x1 - STARTED - Write '1' to enable interrupt for STARTED event - 19 - 19 + PIN25 + Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. + 25 + 25 - read - - Disabled - Read: Disabled - 0 - - Enabled - Read: Enabled - 1 + NotLatched + Criteria has not been met + 0x0 - - - write - Set - Enable - 1 + Latched + Criteria has been met + 0x1 - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - STOPPED - Write '1' to disable interrupt for STOPPED event - 1 - 1 + PIN26 + Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. + 26 + 26 - read - - Disabled - Read: Disabled - 0 - - Enabled - Read: Enabled - 1 + NotLatched + Criteria has not been met + 0x0 - - - write - Clear - Disable - 1 + Latched + Criteria has been met + 0x1 - ENDRX - Write '1' to disable interrupt for ENDRX event - 4 - 4 + PIN27 + Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. + 27 + 27 - read - - Disabled - Read: Disabled - 0 - - Enabled - Read: Enabled - 1 + NotLatched + Criteria has not been met + 0x0 - - - write - Clear - Disable - 1 + Latched + Criteria has been met + 0x1 - END - Write '1' to disable interrupt for END event - 6 - 6 + PIN28 + Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. + 28 + 28 - read - - Disabled - Read: Disabled - 0 - - Enabled - Read: Enabled - 1 + NotLatched + Criteria has not been met + 0x0 - - - write - Clear - Disable - 1 + Latched + Criteria has been met + 0x1 - ENDTX - Write '1' to disable interrupt for ENDTX event - 8 - 8 + PIN29 + Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. + 29 + 29 - read - Disabled - Read: Disabled - 0 + NotLatched + Criteria has not been met + 0x0 - Enabled - Read: Enabled - 1 + Latched + Criteria has been met + 0x1 + + + PIN30 + Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. + 30 + 30 - write - Clear - Disable - 1 + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 - STARTED - Write '1' to disable interrupt for STARTED event - 19 - 19 + PIN31 + Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. + 31 + 31 - read - Disabled - Read: Disabled - 0 + NotLatched + Criteria has not been met + 0x0 - Enabled - Read: Enabled - 1 + Latched + Criteria has been met + 0x1 + + + + + DETECTMODE + Select between default DETECT signal behavior and LDETECT mode + 0x524 + read-write + 0x00000000 + 0x20 + + + DETECTMODE + Select between default DETECT signal behavior and LDETECT mode + 0 + 0 - write - Clear - Disable - 1 + Default + DETECT directly connected to PIN DETECT signals + 0x0 + + + LDETECT + Use the latched LDETECT behavior + 0x1 - STALLSTAT - Stall status for EasyDMA RAM accesses. The fields in this register is set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU. - 0x400 + 0x20 + 0x4 + PIN_CNF[%s] + Description collection: Configuration of GPIO pins + 0x700 read-write - 0x00000000 + 0x00000002 + 0x20 - TX - Stall status for EasyDMA RAM reads + DIR + Pin direction. Same physical register as DIR register 0 0 - NOSTALL - No stall - 0 + Input + Configure pin as an input pin + 0x0 - STALL - A stall has occurred - 1 + Output + Configure pin as an output pin + 0x1 - RX - Stall status for EasyDMA RAM writes + INPUT + Connect or disconnect input buffer 1 1 - NOSTALL - No stall - 0 + Connect + Connect input buffer + 0x0 - STALL - A stall has occurred - 1 + Disconnect + Disconnect input buffer + 0x1 - - - - ENABLE - Enable SPIM - 0x500 - read-write - - ENABLE - Enable or disable SPIM - 0 + PULL + Pull configuration + 2 3 Disabled - Disable SPIM - 0 + No pull + 0x0 - Enabled - Enable SPIM - 7 + Pulldown + Pull down on pin + 0x1 + + + Pullup + Pull up on pin + 0x3 - - - - PSEL - Unspecified - SPIM_PSEL - 0x508 - - SCK - Pin select for SCK - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - MOSI - Pin select for MOSI signal - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - MISO - Pin select for MISO signal - 0x008 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - CSN - Pin select for CSN - 0x00C - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - FREQUENCY - SPI frequency. Accuracy depends on the HFCLK source selected. - 0x524 - read-write - 0x04000000 - - FREQUENCY - SPI master data rate - 0 - 31 + DRIVE + Drive configuration + 8 + 10 - K125 - 125 kbps - 0x02000000 + S0S1 + Standard '0', standard '1' + 0x0 - K250 - 250 kbps - 0x04000000 + H0S1 + High drive '0', standard '1' + 0x1 - K500 - 500 kbps - 0x08000000 + S0H1 + Standard '0', high drive '1' + 0x2 - M1 - 1 Mbps - 0x10000000 + H0H1 + High drive '0', high 'drive '1'' + 0x3 - M2 - 2 Mbps - 0x20000000 + D0S1 + Disconnect '0' standard '1' (normally used for wired-or connections) + 0x4 - M4 - 4 Mbps - 0x40000000 + D0H1 + Disconnect '0', high drive '1' (normally used for wired-or connections) + 0x5 - M8 - 8 Mbps - 0x80000000 + S0D1 + Standard '0'. disconnect '1' (normally used for wired-and connections) + 0x6 - M16 - 16 Mbps - 0x0A000000 + H0D1 + High drive '0', disconnect '1' (normally used for wired-and connections) + 0x7 + + + + + SENSE + Pin sensing mechanism + 16 + 17 + + + Disabled + Disabled + 0x0 - M32 - 32 Mbps - 0x14000000 + High + Sense for high level + 0x2 + + + Low + Sense for low level + 0x3 - - RXD - RXD EasyDMA channel - SPIM_RXD - 0x534 - - PTR - Data pointer - 0x000 - read-write - - - PTR - Data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in receive buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in receive buffer - 0 - 15 - - - - - AMOUNT - Number of bytes transferred in the last transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last transaction - 0 - 15 - - - - - LIST - EasyDMA list type - 0x00C - read-write - - - LIST - List type - 0 - 1 - - - Disabled - Disable EasyDMA list - 0 - - - ArrayList - Use array list - 1 - - - - - - - - TXD - TXD EasyDMA channel - SPIM_TXD - 0x544 - - PTR - Data pointer - 0x000 - read-write - - - PTR - Data pointer - 0 - 31 - - - - - MAXCNT - Number of bytes in transmit buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in transmit buffer - 0 - 15 - - - - - AMOUNT - Number of bytes transferred in the last transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last transaction - 0 - 15 - - - - - LIST - EasyDMA list type - 0x00C - read-write - - - LIST - List type - 0 - 1 - - - Disabled - Disable EasyDMA list - 0 - - - ArrayList - Use array list - 1 - - - - - - + + + + P1 + GPIO Port 1 + 0x50000300 + P0 + + + RADIO + 2.4 GHz radio + 0x40001000 + + 0 + 0x1000 + registers + + + RADIO + 1 + + RADIO + 0x20 + - CONFIG - Configuration register - 0x554 - read-write + TASKS_TXEN + Enable RADIO in TX mode + 0x000 + write-only + 0x00000000 + 0x20 - ORDER - Bit order + TASKS_TXEN + Enable RADIO in TX mode 0 0 - MsbFirst - Most significant bit shifted out first - 0 - - - LsbFirst - Least significant bit shifted out first - 1 + Trigger + Trigger task + 0x1 + + + + TASKS_RXEN + Enable RADIO in RX mode + 0x004 + write-only + 0x00000000 + 0x20 + - CPHA - Serial clock (SCK) phase - 1 - 1 + TASKS_RXEN + Enable RADIO in RX mode + 0 + 0 - Leading - Sample on leading edge of clock, shift serial data on trailing edge - 0 - - - Trailing - Sample on trailing edge of clock, shift serial data on leading edge - 1 + Trigger + Trigger task + 0x1 + + + + TASKS_START + Start RADIO + 0x008 + write-only + 0x00000000 + 0x20 + - CPOL - Serial clock (SCK) polarity - 2 - 2 + TASKS_START + Start RADIO + 0 + 0 - ActiveHigh - Active high - 0 - - - ActiveLow - Active low - 1 + Trigger + Trigger task + 0x1 - - IFTIMING - Unspecified - SPIM_IFTIMING - 0x560 - - RXDELAY - Sample delay for input serial data on MISO - 0x000 - read-write - 0x00000002 - - - RXDELAY - Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK. - 0 - 2 - - - - - CSNDUR - Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions - 0x004 - read-write - 0x00000002 - - - CSNDUR - Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns). - 0 - 7 - - - - - CSNPOL - Polarity of CSN output - 0x568 - read-write + TASKS_STOP + Stop RADIO + 0x00C + write-only 0x00000000 + 0x20 - CSNPOL - Polarity of CSN output + TASKS_STOP + Stop RADIO 0 0 - LOW - Active low (idle state high) - 0 - - - HIGH - Active high (idle state low) - 1 + Trigger + Trigger task + 0x1 - PSELDCX - Pin select for DCX signal - 0x56C - read-write - 0xFFFFFFFF + TASKS_DISABLE + Disable RADIO + 0x010 + write-only + 0x00000000 + 0x20 - PIN - Pin number + TASKS_DISABLE + Disable RADIO 0 - 4 - - - PORT - Port number - 5 - 5 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + TASKS_RSSISTART + Start the RSSI and take one single sample of the receive signal strength + 0x014 + write-only + 0x00000000 + 0x20 + - CONNECT - Connection - 31 - 31 + TASKS_RSSISTART + Start the RSSI and take one single sample of the receive signal strength + 0 + 0 - Disconnected - Disconnect - 1 + Trigger + Trigger task + 0x1 + + + + + + TASKS_RSSISTOP + Stop the RSSI measurement + 0x018 + write-only + 0x00000000 + 0x20 + + + TASKS_RSSISTOP + Stop the RSSI measurement + 0 + 0 + - Connected - Connect - 0 + Trigger + Trigger task + 0x1 - DCXCNT - DCX configuration - 0x570 - read-write + TASKS_BCSTART + Start the bit counter + 0x01C + write-only + 0x00000000 + 0x20 - DCXCNT - This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates that all bytes are command bytes. + TASKS_BCSTART + Start the bit counter 0 - 3 + 0 + + + Trigger + Trigger task + 0x1 + + - ORC - Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT - 0x5C0 - read-write + TASKS_BCSTOP + Stop the bit counter + 0x020 + write-only + 0x00000000 + 0x20 - ORC - Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT. + TASKS_BCSTOP + Stop the bit counter 0 - 7 + 0 + + + Trigger + Trigger task + 0x1 + + - - - - SPIS0 - SPI Slave 0 - 0x40003000 - SPI0 - SPIS - - 0 - 0x1000 - registers - - - SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 - 3 - - SPIS - 0x20 - - TASKS_ACQUIRE - Acquire SPI semaphore + TASKS_EDSTART + Start the energy detect measurement used in IEEE 802.15.4 mode 0x024 write-only + 0x00000000 + 0x20 - TASKS_ACQUIRE + TASKS_EDSTART + Start the energy detect measurement used in IEEE 802.15.4 mode 0 0 + + + Trigger + Trigger task + 0x1 + + - TASKS_RELEASE - Release SPI semaphore, enabling the SPI slave to acquire it + TASKS_EDSTOP + Stop the energy detect measurement 0x028 write-only + 0x00000000 + 0x20 - TASKS_RELEASE + TASKS_EDSTOP + Stop the energy detect measurement 0 0 + + + Trigger + Trigger task + 0x1 + + - EVENTS_END - Granted transaction completed - 0x104 - read-write + TASKS_CCASTART + Start the clear channel assessment used in IEEE 802.15.4 mode + 0x02C + write-only + 0x00000000 + 0x20 - EVENTS_END + TASKS_CCASTART + Start the clear channel assessment used in IEEE 802.15.4 mode 0 0 + + + Trigger + Trigger task + 0x1 + + - EVENTS_ENDRX - End of RXD buffer reached - 0x110 - read-write + TASKS_CCASTOP + Stop the clear channel assessment + 0x030 + write-only + 0x00000000 + 0x20 - EVENTS_ENDRX + TASKS_CCASTOP + Stop the clear channel assessment 0 0 + + + Trigger + Trigger task + 0x1 + + - EVENTS_ACQUIRED - Semaphore acquired - 0x128 + EVENTS_READY + RADIO has ramped up and is ready to be started + 0x100 read-write + 0x00000000 + 0x20 - EVENTS_ACQUIRED + EVENTS_READY + RADIO has ramped up and is ready to be started 0 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + - SHORTS - Shortcut register - 0x200 + EVENTS_ADDRESS + Address sent or received + 0x104 read-write + 0x00000000 + 0x20 - END_ACQUIRE - Shortcut between END event and ACQUIRE task - 2 - 2 + EVENTS_ADDRESS + Address sent or received + 0 + 0 - Disabled - Disable shortcut - 0 + NotGenerated + Event not generated + 0x0 - Enabled - Enable shortcut - 1 + Generated + Event generated + 0x1 - INTENSET - Enable interrupt - 0x304 + EVENTS_PAYLOAD + Packet payload sent or received + 0x108 read-write + 0x00000000 + 0x20 - END - Write '1' to enable interrupt for END event - 1 - 1 + EVENTS_PAYLOAD + Packet payload sent or received + 0 + 0 - read - - Disabled - Read: Disabled - 0 - - Enabled - Read: Enabled - 1 + NotGenerated + Event not generated + 0x0 - - - write - Set - Enable - 1 + Generated + Event generated + 0x1 + + + + EVENTS_END + Packet sent or received + 0x10C + read-write + 0x00000000 + 0x20 + - ENDRX - Write '1' to enable interrupt for ENDRX event - 4 - 4 + EVENTS_END + Packet sent or received + 0 + 0 - read - - Disabled - Read: Disabled - 0 - - Enabled - Read: Enabled - 1 + NotGenerated + Event not generated + 0x0 - - - write - Set - Enable - 1 + Generated + Event generated + 0x1 + + + + EVENTS_DISABLED + RADIO has been disabled + 0x110 + read-write + 0x00000000 + 0x20 + - ACQUIRED - Write '1' to enable interrupt for ACQUIRED event - 10 - 10 + EVENTS_DISABLED + RADIO has been disabled + 0 + 0 - read - - Disabled - Read: Disabled - 0 - - Enabled - Read: Enabled - 1 + NotGenerated + Event not generated + 0x0 - - - write - Set - Enable - 1 + Generated + Event generated + 0x1 - INTENCLR - Disable interrupt - 0x308 + EVENTS_DEVMATCH + A device address match occurred on the last received packet + 0x114 read-write + 0x00000000 + 0x20 - END - Write '1' to disable interrupt for END event - 1 - 1 + EVENTS_DEVMATCH + A device address match occurred on the last received packet + 0 + 0 - read - - Disabled - Read: Disabled - 0 - - Enabled - Read: Enabled - 1 + NotGenerated + Event not generated + 0x0 - - - write - Clear - Disable - 1 + Generated + Event generated + 0x1 + + + + EVENTS_DEVMISS + No device address match occurred on the last received packet + 0x118 + read-write + 0x00000000 + 0x20 + - ENDRX - Write '1' to disable interrupt for ENDRX event - 4 - 4 + EVENTS_DEVMISS + No device address match occurred on the last received packet + 0 + 0 - read - - Disabled - Read: Disabled - 0 - - Enabled - Read: Enabled - 1 + NotGenerated + Event not generated + 0x0 - - - write - Clear - Disable - 1 + Generated + Event generated + 0x1 + + + + EVENTS_RSSIEND + Sampling of receive signal strength complete + 0x11C + read-write + 0x00000000 + 0x20 + - ACQUIRED - Write '1' to disable interrupt for ACQUIRED event - 10 - 10 + EVENTS_RSSIEND + Sampling of receive signal strength complete + 0 + 0 - read - Disabled - Read: Disabled - 0 + NotGenerated + Event not generated + 0x0 - Enabled - Read: Enabled - 1 + Generated + Event generated + 0x1 + + + + + EVENTS_BCMATCH + Bit counter reached bit count value + 0x128 + read-write + 0x00000000 + 0x20 + + + EVENTS_BCMATCH + Bit counter reached bit count value + 0 + 0 - write - Clear - Disable - 1 + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 - SEMSTAT - Semaphore status register - 0x400 - read-only - 0x00000001 + EVENTS_CRCOK + Packet received with CRC ok + 0x130 + read-write + 0x00000000 + 0x20 - SEMSTAT - Semaphore status + EVENTS_CRCOK + Packet received with CRC ok 0 - 1 + 0 - Free - Semaphore is free - 0 + NotGenerated + Event not generated + 0x0 - CPU - Semaphore is assigned to CPU - 1 + Generated + Event generated + 0x1 + + + + + + EVENTS_CRCERROR + Packet received with CRC error + 0x134 + read-write + 0x00000000 + 0x20 + + + EVENTS_CRCERROR + Packet received with CRC error + 0 + 0 + - SPIS - Semaphore is assigned to SPI slave - 2 + NotGenerated + Event not generated + 0x0 - CPUPending - Semaphore is assigned to SPI but a handover to the CPU is pending - 3 + Generated + Event generated + 0x1 - STATUS - Status from last transaction - 0x440 + EVENTS_FRAMESTART + IEEE 802.15.4 length field received + 0x138 read-write + 0x00000000 + 0x20 - OVERREAD - TX buffer over-read detected, and prevented + EVENTS_FRAMESTART + IEEE 802.15.4 length field received 0 0 - read - NotPresent - Read: error not present - 0 + NotGenerated + Event not generated + 0x0 - Present - Read: error present - 1 + Generated + Event generated + 0x1 + + + + + EVENTS_EDEND + Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. + 0x13C + read-write + 0x00000000 + 0x20 + + + EVENTS_EDEND + Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. + 0 + 0 - write - Clear - Write: clear error on writing '1' - 1 + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + EVENTS_EDSTOPPED + The sampling of energy detection has stopped + 0x140 + read-write + 0x00000000 + 0x20 + - OVERFLOW - RX buffer overflow detected, and prevented - 1 - 1 + EVENTS_EDSTOPPED + The sampling of energy detection has stopped + 0 + 0 - read - NotPresent - Read: error not present - 0 + NotGenerated + Event not generated + 0x0 - Present - Read: error present - 1 + Generated + Event generated + 0x1 + + + + + EVENTS_CCAIDLE + Wireless medium in idle - clear to send + 0x144 + read-write + 0x00000000 + 0x20 + + + EVENTS_CCAIDLE + Wireless medium in idle - clear to send + 0 + 0 - write - Clear - Write: clear error on writing '1' - 1 + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 - ENABLE - Enable SPI slave - 0x500 + EVENTS_CCABUSY + Wireless medium busy - do not send + 0x148 read-write + 0x00000000 + 0x20 - ENABLE - Enable or disable SPI slave + EVENTS_CCABUSY + Wireless medium busy - do not send 0 - 3 + 0 - Disabled - Disable SPI slave - 0 + NotGenerated + Event not generated + 0x0 - Enabled - Enable SPI slave - 2 + Generated + Event generated + 0x1 - - PSEL - Unspecified - SPIS_PSEL - 0x508 - - SCK - Pin select for SCK - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - MISO - Pin select for MISO signal - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - MOSI - Pin select for MOSI signal - 0x008 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - CSN - Pin select for CSN signal - 0x00C - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - RXD - Unspecified - SPIS_RXD - 0x534 - - PTR - RXD data pointer - 0x000 - read-write - - - PTR - RXD data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in receive buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in receive buffer - 0 - 15 - - - - - AMOUNT - Number of bytes received in last granted transaction - 0x008 - read-only - - - AMOUNT - Number of bytes received in the last granted transaction - 0 - 15 - - - - - - TXD - Unspecified - SPIS_TXD - 0x544 - - PTR - TXD data pointer - 0x000 - read-write - - - PTR - TXD data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in transmit buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in transmit buffer - 0 - 15 - - - - - AMOUNT - Number of bytes transmitted in last granted transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transmitted in last granted transaction - 0 - 15 - - - - - CONFIG - Configuration register - 0x554 + EVENTS_CCASTOPPED + The CCA has stopped + 0x14C read-write + 0x00000000 + 0x20 - ORDER - Bit order + EVENTS_CCASTOPPED + The CCA has stopped 0 0 - MsbFirst - Most significant bit shifted out first - 0 - - - LsbFirst - Least significant bit shifted out first - 1 - - - - - CPHA - Serial clock (SCK) phase - 1 - 1 - - - Leading - Sample on leading edge of clock, shift serial data on trailing edge - 0 - - - Trailing - Sample on trailing edge of clock, shift serial data on leading edge - 1 - - - - - CPOL - Serial clock (SCK) polarity - 2 - 2 - - - ActiveHigh - Active high - 0 + NotGenerated + Event not generated + 0x0 - ActiveLow - Active low - 1 + Generated + Event generated + 0x1 - DEF - Default character. Character clocked out in case of an ignored transaction. - 0x55C - read-write - - - DEF - Default character. Character clocked out in case of an ignored transaction. - 0 - 7 - - - - - ORC - Over-read character - 0x5C0 - read-write - - - ORC - Over-read character. Character clocked out after an over-read of the transmit buffer. - 0 - 7 - - - - - - - TWI0 - I2C compatible Two-Wire Interface 0 - 0x40003000 - SPI0 - TWI - - 0 - 0x1000 - registers - - - SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 - 3 - - TWI - 0x20 - - - TASKS_STARTRX - Start TWI receive sequence - 0x000 - write-only - - - TASKS_STARTRX - 0 - 0 - - - - - TASKS_STARTTX - Start TWI transmit sequence - 0x008 - write-only - - - TASKS_STARTTX - 0 - 0 - - - - - TASKS_STOP - Stop TWI transaction - 0x014 - write-only - - - TASKS_STOP - 0 - 0 - - - - - TASKS_SUSPEND - Suspend TWI transaction - 0x01C - write-only - - - TASKS_SUSPEND - 0 - 0 - - - - - TASKS_RESUME - Resume TWI transaction - 0x020 - write-only - - - TASKS_RESUME - 0 - 0 - - - - - EVENTS_STOPPED - TWI stopped - 0x104 + EVENTS_RATEBOOST + Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. + 0x150 read-write + 0x00000000 + 0x20 - EVENTS_STOPPED + EVENTS_RATEBOOST + Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. 0 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + - EVENTS_RXDREADY - TWI RXD byte received - 0x108 + EVENTS_TXREADY + RADIO has ramped up and is ready to be started TX path + 0x154 read-write + 0x00000000 + 0x20 - EVENTS_RXDREADY + EVENTS_TXREADY + RADIO has ramped up and is ready to be started TX path 0 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + - EVENTS_TXDSENT - TWI TXD byte sent - 0x11C + EVENTS_RXREADY + RADIO has ramped up and is ready to be started RX path + 0x158 read-write + 0x00000000 + 0x20 - EVENTS_TXDSENT + EVENTS_RXREADY + RADIO has ramped up and is ready to be started RX path 0 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + - EVENTS_ERROR - TWI error - 0x124 + EVENTS_MHRMATCH + MAC header match found + 0x15C read-write + 0x00000000 + 0x20 - EVENTS_ERROR + EVENTS_MHRMATCH + MAC header match found 0 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + - EVENTS_BB - TWI byte boundary, generated before each byte that is sent or received - 0x138 + EVENTS_SYNC + Preamble indicator. + 0x168 read-write + 0x00000000 + 0x20 - EVENTS_BB + EVENTS_SYNC + Preamble indicator. 0 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + - EVENTS_SUSPENDED - TWI entered the suspended state - 0x148 + EVENTS_PHYEND + Generated in Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes when last bit is sent on air. + 0x16C read-write + 0x00000000 + 0x20 - EVENTS_SUSPENDED + EVENTS_PHYEND + Generated in Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes when last bit is sent on air. 0 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + SHORTS - Shortcut register + Shortcuts between local events and tasks 0x200 read-write + 0x00000000 + 0x20 - BB_SUSPEND - Shortcut between BB event and SUSPEND task + READY_START + Shortcut between event READY and task START 0 0 Disabled Disable shortcut - 0 + 0x0 Enabled Enable shortcut - 1 + 0x1 - BB_STOP - Shortcut between BB event and STOP task + END_DISABLE + Shortcut between event END and task DISABLE 1 1 Disabled Disable shortcut - 0 + 0x0 Enabled Enable shortcut - 1 + 0x1 - - - - INTENSET - Enable interrupt - 0x304 + + DISABLED_TXEN + Shortcut between event DISABLED and task TXEN + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DISABLED_RXEN + Shortcut between event DISABLED and task RXEN + 3 + 3 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + ADDRESS_RSSISTART + Shortcut between event ADDRESS and task RSSISTART + 4 + 4 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + END_START + Shortcut between event END and task START + 5 + 5 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + ADDRESS_BCSTART + Shortcut between event ADDRESS and task BCSTART + 6 + 6 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DISABLED_RSSISTOP + Shortcut between event DISABLED and task RSSISTOP + 8 + 8 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + RXREADY_CCASTART + Shortcut between event RXREADY and task CCASTART + 11 + 11 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + CCAIDLE_TXEN + Shortcut between event CCAIDLE and task TXEN + 12 + 12 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + CCABUSY_DISABLE + Shortcut between event CCABUSY and task DISABLE + 13 + 13 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + FRAMESTART_BCSTART + Shortcut between event FRAMESTART and task BCSTART + 14 + 14 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + READY_EDSTART + Shortcut between event READY and task EDSTART + 15 + 15 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + EDEND_DISABLE + Shortcut between event EDEND and task DISABLE + 16 + 16 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + CCAIDLE_STOP + Shortcut between event CCAIDLE and task STOP + 17 + 17 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + TXREADY_START + Shortcut between event TXREADY and task START + 18 + 18 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + RXREADY_START + Shortcut between event RXREADY and task START + 19 + 19 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + PHYEND_DISABLE + Shortcut between event PHYEND and task DISABLE + 20 + 20 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + PHYEND_START + Shortcut between event PHYEND and task START + 21 + 21 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 read-write + 0x00000000 + 0x20 - STOPPED - Write '1' to enable interrupt for STOPPED event + READY + Write '1' to enable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + ADDRESS + Write '1' to enable interrupt for event ADDRESS 1 1 @@ -13156,12 +12445,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -13169,13 +12458,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - RXDREADY - Write '1' to enable interrupt for RXDREADY event + PAYLOAD + Write '1' to enable interrupt for event PAYLOAD 2 2 @@ -13183,12 +12472,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -13196,26 +12485,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - TXDSENT - Write '1' to enable interrupt for TXDSENT event - 7 - 7 + END + Write '1' to enable interrupt for event END + 3 + 3 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -13223,26 +12512,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - ERROR - Write '1' to enable interrupt for ERROR event - 9 - 9 + DISABLED + Write '1' to enable interrupt for event DISABLED + 4 + 4 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -13250,26 +12539,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - BB - Write '1' to enable interrupt for BB event - 14 - 14 + DEVMATCH + Write '1' to enable interrupt for event DEVMATCH + 5 + 5 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -13277,26 +12566,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - SUSPENDED - Write '1' to enable interrupt for SUSPENDED event - 18 - 18 + DEVMISS + Write '1' to enable interrupt for event DEVMISS + 6 + 6 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -13304,129 +12593,121 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - STOPPED - Write '1' to disable interrupt for STOPPED event - 1 - 1 + RSSIEND + Write '1' to enable interrupt for event RSSIEND + 7 + 7 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Clear - Disable - 1 + Set + Enable + 0x1 - RXDREADY - Write '1' to disable interrupt for RXDREADY event - 2 - 2 + BCMATCH + Write '1' to enable interrupt for event BCMATCH + 10 + 10 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Clear - Disable - 1 + Set + Enable + 0x1 - TXDSENT - Write '1' to disable interrupt for TXDSENT event - 7 - 7 + CRCOK + Write '1' to enable interrupt for event CRCOK + 12 + 12 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Clear - Disable - 1 + Set + Enable + 0x1 - ERROR - Write '1' to disable interrupt for ERROR event - 9 - 9 + CRCERROR + Write '1' to enable interrupt for event CRCERROR + 13 + 13 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Clear - Disable - 1 + Set + Enable + 0x1 - BB - Write '1' to disable interrupt for BB event + FRAMESTART + Write '1' to enable interrupt for event FRAMESTART 14 14 @@ -13434,948 +12715,535 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Clear - Disable - 1 + Set + Enable + 0x1 - SUSPENDED - Write '1' to disable interrupt for SUSPENDED event - 18 - 18 + EDEND + Write '1' to enable interrupt for event EDEND + 15 + 15 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Clear - Disable - 1 + Set + Enable + 0x1 - - - - ERRORSRC - Error source - 0x4C4 - read-write - oneToClear - - OVERRUN - Overrun error - 0 - 0 + EDSTOPPED + Write '1' to enable interrupt for event EDSTOPPED + 16 + 16 read - NotPresent - Read: no overrun occured - 0 + Disabled + Read: Disabled + 0x0 - Present - Read: overrun occured - 1 + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 - ANACK - NACK received after sending the address (write '1' to clear) - 1 - 1 + CCAIDLE + Write '1' to enable interrupt for event CCAIDLE + 17 + 17 read - NotPresent - Read: error not present - 0 + Disabled + Read: Disabled + 0x0 - Present - Read: error present - 1 + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 - DNACK - NACK received after sending a data byte (write '1' to clear) - 2 - 2 + CCABUSY + Write '1' to enable interrupt for event CCABUSY + 18 + 18 read - NotPresent - Read: error not present - 0 + Disabled + Read: Disabled + 0x0 - Present - Read: error present - 1 + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 - - - - ENABLE - Enable TWI - 0x500 - read-write - - ENABLE - Enable or disable TWI - 0 - 3 + CCASTOPPED + Write '1' to enable interrupt for event CCASTOPPED + 19 + 19 + read Disabled - Disable TWI - 0 + Read: Disabled + 0x0 Enabled - Enable TWI - 5 + Read: Enabled + 0x1 - - - - - PSEL - Unspecified - TWI_PSEL - 0x508 - - SCL - Pin select for SCL - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - SDA - Pin select for SDA - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - RXD - RXD register - 0x518 - read-only - modifyExternal - - - RXD - RXD register - 0 - 7 - - - - - TXD - TXD register - 0x51C - read-write - - - TXD - TXD register - 0 - 7 - - - - - FREQUENCY - TWI frequency. Accuracy depends on the HFCLK source selected. - 0x524 - read-write - 0x04000000 - - - FREQUENCY - TWI master clock frequency - 0 - 31 - - - K100 - 100 kbps - 0x01980000 - - - K250 - 250 kbps - 0x04000000 - - - K400 - 400 kbps (actual rate 410.256 kbps) - 0x06680000 - - - - - - - ADDRESS - Address used in the TWI transfer - 0x588 - read-write - - - ADDRESS - Address used in the TWI transfer - 0 - 6 - - - - - - - TWIM0 - I2C compatible Two-Wire Master Interface with EasyDMA 0 - 0x40003000 - SPI0 - TWIM - - 0 - 0x1000 - registers - - - SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 - 3 - - TWIM - 0x20 - - - TASKS_STARTRX - Start TWI receive sequence - 0x000 - write-only - - - TASKS_STARTRX - 0 - 0 - - - - - TASKS_STARTTX - Start TWI transmit sequence - 0x008 - write-only - - - TASKS_STARTTX - 0 - 0 - - - - - TASKS_STOP - Stop TWI transaction. Must be issued while the TWI master is not suspended. - 0x014 - write-only - - - TASKS_STOP - 0 - 0 - - - - - TASKS_SUSPEND - Suspend TWI transaction - 0x01C - write-only - - - TASKS_SUSPEND - 0 - 0 - - - - - TASKS_RESUME - Resume TWI transaction - 0x020 - write-only - - - TASKS_RESUME - 0 - 0 - - - - - EVENTS_STOPPED - TWI stopped - 0x104 - read-write - - - EVENTS_STOPPED - 0 - 0 - - - - - EVENTS_ERROR - TWI error - 0x124 - read-write - - - EVENTS_ERROR - 0 - 0 - - - - - EVENTS_SUSPENDED - Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. - 0x148 - read-write - - - EVENTS_SUSPENDED - 0 - 0 - - - - - EVENTS_RXSTARTED - Receive sequence started - 0x14C - read-write - - - EVENTS_RXSTARTED - 0 - 0 - - - - - EVENTS_TXSTARTED - Transmit sequence started - 0x150 - read-write - - - EVENTS_TXSTARTED - 0 - 0 - - - - - EVENTS_LASTRX - Byte boundary, starting to receive the last byte - 0x15C - read-write - - - EVENTS_LASTRX - 0 - 0 - - - - - EVENTS_LASTTX - Byte boundary, starting to transmit the last byte - 0x160 - read-write - - - EVENTS_LASTTX - 0 - 0 - - - - - SHORTS - Shortcut register - 0x200 - read-write - - - LASTTX_STARTRX - Shortcut between LASTTX event and STARTRX task - 7 - 7 + write - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 + Set + Enable + 0x1 - LASTTX_SUSPEND - Shortcut between LASTTX event and SUSPEND task - 8 - 8 + RATEBOOST + Write '1' to enable interrupt for event RATEBOOST + 20 + 20 + read Disabled - Disable shortcut - 0 + Read: Disabled + 0x0 Enabled - Enable shortcut - 1 + Read: Enabled + 0x1 - - - LASTTX_STOP - Shortcut between LASTTX event and STOP task - 9 - 9 + write - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 + Set + Enable + 0x1 - LASTRX_STARTTX - Shortcut between LASTRX event and STARTTX task - 10 - 10 + TXREADY + Write '1' to enable interrupt for event TXREADY + 21 + 21 + read Disabled - Disable shortcut - 0 + Read: Disabled + 0x0 Enabled - Enable shortcut - 1 + Read: Enabled + 0x1 - - - LASTRX_SUSPEND - Shortcut between LASTRX event and SUSPEND task - 11 - 11 + write - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 + Set + Enable + 0x1 - LASTRX_STOP - Shortcut between LASTRX event and STOP task - 12 - 12 + RXREADY + Write '1' to enable interrupt for event RXREADY + 22 + 22 + read Disabled - Disable shortcut - 0 + Read: Disabled + 0x0 Enabled - Enable shortcut - 1 + Read: Enabled + 0x1 - - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - - STOPPED - Enable or disable interrupt for STOPPED event - 1 - 1 + write - Disabled - Disable - 0 - - - Enabled + Set Enable - 1 + 0x1 - ERROR - Enable or disable interrupt for ERROR event - 9 - 9 + MHRMATCH + Write '1' to enable interrupt for event MHRMATCH + 23 + 23 + read Disabled - Disable - 0 + Read: Disabled + 0x0 Enabled - Enable - 1 + Read: Enabled + 0x1 - - - SUSPENDED - Enable or disable interrupt for SUSPENDED event - 18 - 18 + write - Disabled - Disable - 0 - - - Enabled + Set Enable - 1 + 0x1 - RXSTARTED - Enable or disable interrupt for RXSTARTED event - 19 - 19 + SYNC + Write '1' to enable interrupt for event SYNC + 26 + 26 + read Disabled - Disable - 0 + Read: Disabled + 0x0 Enabled - Enable - 1 + Read: Enabled + 0x1 - - - TXSTARTED - Enable or disable interrupt for TXSTARTED event - 20 - 20 + write - Disabled - Disable - 0 - - - Enabled + Set Enable - 1 + 0x1 - LASTRX - Enable or disable interrupt for LASTRX event - 23 - 23 + PHYEND + Write '1' to enable interrupt for event PHYEND + 27 + 27 + read Disabled - Disable - 0 + Read: Disabled + 0x0 Enabled - Enable - 1 + Read: Enabled + 0x1 - - - LASTTX - Enable or disable interrupt for LASTTX event - 24 - 24 + write - Disabled - Disable - 0 - - - Enabled + Set Enable - 1 + 0x1 - INTENSET - Enable interrupt - 0x304 + INTENCLR + Disable interrupt + 0x308 read-write + 0x00000000 + 0x20 - STOPPED - Write '1' to enable interrupt for STOPPED event - 1 - 1 + READY + Write '1' to disable interrupt for event READY + 0 + 0 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Set - Enable - 1 + Clear + Disable + 0x1 - ERROR - Write '1' to enable interrupt for ERROR event - 9 - 9 + ADDRESS + Write '1' to disable interrupt for event ADDRESS + 1 + 1 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Set - Enable - 1 + Clear + Disable + 0x1 - SUSPENDED - Write '1' to enable interrupt for SUSPENDED event - 18 - 18 + PAYLOAD + Write '1' to disable interrupt for event PAYLOAD + 2 + 2 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Set - Enable - 1 + Clear + Disable + 0x1 - RXSTARTED - Write '1' to enable interrupt for RXSTARTED event - 19 - 19 + END + Write '1' to disable interrupt for event END + 3 + 3 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Set - Enable - 1 + Clear + Disable + 0x1 - TXSTARTED - Write '1' to enable interrupt for TXSTARTED event - 20 - 20 + DISABLED + Write '1' to disable interrupt for event DISABLED + 4 + 4 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Set - Enable - 1 + Clear + Disable + 0x1 - LASTRX - Write '1' to enable interrupt for LASTRX event - 23 - 23 + DEVMATCH + Write '1' to disable interrupt for event DEVMATCH + 5 + 5 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Set - Enable - 1 + Clear + Disable + 0x1 - LASTTX - Write '1' to enable interrupt for LASTTX event - 24 - 24 + DEVMISS + Write '1' to disable interrupt for event DEVMISS + 6 + 6 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Set - Enable - 1 + Clear + Disable + 0x1 - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - STOPPED - Write '1' to disable interrupt for STOPPED event - 1 - 1 + RSSIEND + Write '1' to disable interrupt for event RSSIEND + 7 + 7 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -14383,26 +13251,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - ERROR - Write '1' to disable interrupt for ERROR event - 9 - 9 + BCMATCH + Write '1' to disable interrupt for event BCMATCH + 10 + 10 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -14410,13 +13278,175 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - SUSPENDED - Write '1' to disable interrupt for SUSPENDED event + CRCOK + Write '1' to disable interrupt for event CRCOK + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CRCERROR + Write '1' to disable interrupt for event CRCERROR + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + FRAMESTART + Write '1' to disable interrupt for event FRAMESTART + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + EDEND + Write '1' to disable interrupt for event EDEND + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + EDSTOPPED + Write '1' to disable interrupt for event EDSTOPPED + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CCAIDLE + Write '1' to disable interrupt for event CCAIDLE + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CCABUSY + Write '1' to disable interrupt for event CCABUSY 18 18 @@ -14424,12 +13454,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -14437,13 +13467,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - RXSTARTED - Write '1' to disable interrupt for RXSTARTED event + CCASTOPPED + Write '1' to disable interrupt for event CCASTOPPED 19 19 @@ -14451,12 +13481,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -14464,13 +13494,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - TXSTARTED - Write '1' to disable interrupt for TXSTARTED event + RATEBOOST + Write '1' to disable interrupt for event RATEBOOST 20 20 @@ -14478,12 +13508,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -14491,13 +13521,67 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - LASTRX - Write '1' to disable interrupt for LASTRX event + TXREADY + Write '1' to disable interrupt for event TXREADY + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RXREADY + Write '1' to disable interrupt for event RXREADY + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + MHRMATCH + Write '1' to disable interrupt for event MHRMATCH 23 23 @@ -14505,12 +13589,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -14518,26 +13602,53 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - LASTTX - Write '1' to disable interrupt for LASTTX event - 24 - 24 + SYNC + Write '1' to disable interrupt for event SYNC + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PHYEND + Write '1' to disable interrupt for event PHYEND + 27 + 27 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -14545,2125 +13656,1818 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - ERRORSRC - Error source - 0x4C4 - read-write - oneToClear + CRCSTATUS + CRC status + 0x400 + read-only + 0x00000000 + 0x20 - OVERRUN - Overrun error + CRCSTATUS + CRC status of packet received 0 0 - NotReceived - Error did not occur - 0 + CRCError + Packet received with CRC error + 0x0 - Received - Error occurred - 1 + CRCOk + Packet received with CRC ok + 0x1 + + + + RXMATCH + Received address + 0x408 + read-only + 0x00000000 + 0x20 + + + RXMATCH + Received address + 0 + 2 + + + + + RXCRC + CRC field of previously received packet + 0x40C + read-only + 0x00000000 + 0x20 + - ANACK - NACK received after sending the address (write '1' to clear) - 1 - 1 + RXCRC + CRC field of previously received packet + 0 + 23 + + + + + DAI + Device address match index + 0x410 + read-only + 0x00000000 + 0x20 + + + DAI + Device address match index + 0 + 2 + + + + + PDUSTAT + Payload status + 0x414 + read-only + 0x00000000 + 0x20 + + + PDUSTAT + Status on payload length vs. PCNF1.MAXLEN + 0 + 0 - NotReceived - Error did not occur - 0 + LessThan + Payload less than PCNF1.MAXLEN + 0x0 - Received - Error occurred - 1 + GreaterThan + Payload greater than PCNF1.MAXLEN + 0x1 - DNACK - NACK received after sending a data byte (write '1' to clear) - 2 + CISTAT + Status on what rate packet is received with in Long Range + 1 2 - NotReceived - Error did not occur - 0 + LR125kbit + Frame is received at 125kbps + 0x0 - Received - Error occurred - 1 + LR500kbit + Frame is received at 500kbps + 0x1 - ENABLE - Enable TWIM - 0x500 + PACKETPTR + Packet pointer + 0x504 read-write + 0x00000000 + 0x20 - ENABLE - Enable or disable TWIM + PACKETPTR + Packet pointer 0 - 3 + 31 + + + + + FREQUENCY + Frequency + 0x508 + read-write + 0x00000002 + 0x20 + + + FREQUENCY + Radio channel frequency + 0 + 6 + + + MAP + Channel map selection. + 8 + 8 - Disabled - Disable TWIM - 0 + Default + Channel map between 2400 MHZ .. 2500 MHz + 0x0 - Enabled - Enable TWIM - 6 + Low + Channel map between 2360 MHZ .. 2460 MHz + 0x1 - - PSEL - Unspecified - TWIM_PSEL - 0x508 - - SCL - Pin select for SCL signal - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - SDA - Pin select for SDA signal - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - FREQUENCY - TWI frequency. Accuracy depends on the HFCLK source selected. - 0x524 + TXPOWER + Output power + 0x50C read-write - 0x04000000 + 0x00000000 + 0x20 - FREQUENCY - TWI master clock frequency + TXPOWER + RADIO output power 0 - 31 + 7 - K100 - 100 kbps - 0x01980000 + Pos8dBm + +8 dBm + 0x08 - K250 - 250 kbps - 0x04000000 + Pos7dBm + +7 dBm + 0x07 - K400 - 400 kbps - 0x06400000 + Pos6dBm + +6 dBm + 0x06 + + + Pos5dBm + +5 dBm + 0x05 + + + Pos4dBm + +4 dBm + 0x04 + + + Pos3dBm + +3 dBm + 0x03 + + + Pos2dBm + +2 dBm + 0x02 + + + 0dBm + 0 dBm + 0x00 + + + Neg4dBm + -4 dBm + 0xFC + + + Neg8dBm + -8 dBm + 0xF8 + + + Neg12dBm + -12 dBm + 0xF4 + + + Neg16dBm + -16 dBm + 0xF0 + + + Neg20dBm + -20 dBm + 0xEC + + + Neg30dBm + Deprecated enumerator - -40 dBm + 0xE2 + + + Neg40dBm + -40 dBm + 0xD8 - - RXD - RXD EasyDMA channel - TWIM_RXD - 0x534 - - PTR - Data pointer - 0x000 - read-write - - - PTR - Data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in receive buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in receive buffer - 0 - 15 - - - - - AMOUNT - Number of bytes transferred in the last transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. - 0 - 15 - - - - - LIST - EasyDMA list type - 0x00C - read-write - - - LIST - List type - 0 - 2 - - - Disabled - Disable EasyDMA list - 0 - - - ArrayList - Use array list - 1 - - - - - - - - TXD - TXD EasyDMA channel - TWIM_TXD - 0x544 - - PTR - Data pointer - 0x000 - read-write - - - PTR - Data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in transmit buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in transmit buffer - 0 - 15 - - - - - AMOUNT - Number of bytes transferred in the last transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. - 0 - 15 - - - - - LIST - EasyDMA list type - 0x00C - read-write - - - LIST - List type - 0 - 2 - - - Disabled - Disable EasyDMA list - 0 - - - ArrayList - Use array list - 1 - - - - - - - ADDRESS - Address used in the TWI transfer - 0x588 + MODE + Data rate and modulation + 0x510 read-write + 0x00000000 + 0x20 - ADDRESS - Address used in the TWI transfer + MODE + Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation. 0 - 6 + 3 + + + Nrf_1Mbit + 1 Mbit/s Nordic proprietary radio mode + 0x0 + + + Nrf_2Mbit + 2 Mbit/s Nordic proprietary radio mode + 0x1 + + + Ble_1Mbit + 1 Mbit/s BLE + 0x3 + + + Ble_2Mbit + 2 Mbit/s BLE + 0x4 + + + Ble_LR125Kbit + Long range 125 kbit/s TX, 125 kbit/s and 500 kbit/s RX + 0x5 + + + Ble_LR500Kbit + Long range 500 kbit/s TX, 125 kbit/s and 500 kbit/s RX + 0x6 + + + Ieee802154_250Kbit + IEEE 802.15.4-2006 250 kbit/s + 0xF + + - - - - TWIS0 - I2C compatible Two-Wire Slave Interface with EasyDMA 0 - 0x40003000 - SPI0 - TWIS - - 0 - 0x1000 - registers - - - SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 - 3 - - TWIS - 0x20 - - TASKS_STOP - Stop TWI transaction - 0x014 - write-only + PCNF0 + Packet configuration register 0 + 0x514 + read-write + 0x00000000 + 0x20 - TASKS_STOP + LFLEN + Length on air of LENGTH field in number of bits. 0 - 0 + 3 - - - - TASKS_SUSPEND - Suspend TWI transaction - 0x01C - write-only - - TASKS_SUSPEND - 0 - 0 + S0LEN + Length on air of S0 field in number of bytes. + 8 + 8 - - - - TASKS_RESUME - Resume TWI transaction - 0x020 - write-only - - TASKS_RESUME - 0 - 0 + S1LEN + Length on air of S1 field in number of bits. + 16 + 19 - - - - TASKS_PREPARERX - Prepare the TWI slave to respond to a write command - 0x030 - write-only - - TASKS_PREPARERX - 0 - 0 + S1INCL + Include or exclude S1 field in RAM + 20 + 20 + + + Automatic + Include S1 field in RAM only if S1LEN &gt; 0 + 0x0 + + + Include + Always include S1 field in RAM independent of S1LEN + 0x1 + + - - - - TASKS_PREPARETX - Prepare the TWI slave to respond to a read command - 0x034 - write-only - - TASKS_PREPARETX - 0 - 0 + CILEN + Length of code indicator - long range + 22 + 23 - - - - EVENTS_STOPPED - TWI stopped - 0x104 - read-write - - EVENTS_STOPPED - 0 - 0 + PLEN + Length of preamble on air. Decision point: TASKS_START task + 24 + 25 + + + 8bit + 8-bit preamble + 0x0 + + + 16bit + 16-bit preamble + 0x1 + + + 32bitZero + 32-bit zero preamble - used for IEEE 802.15.4 + 0x2 + + + LongRange + Preamble - used for BLE long range + 0x3 + + - - - - EVENTS_ERROR - TWI error - 0x124 - read-write - - EVENTS_ERROR - 0 - 0 + CRCINC + Indicates if LENGTH field contains CRC or not + 26 + 26 + + + Exclude + LENGTH does not contain CRC + 0x0 + + + Include + LENGTH includes CRC + 0x1 + + - - - - EVENTS_RXSTARTED - Receive sequence started - 0x14C - read-write - - EVENTS_RXSTARTED - 0 - 0 + TERMLEN + Length of TERM field in Long Range operation + 29 + 30 - EVENTS_TXSTARTED - Transmit sequence started - 0x150 + PCNF1 + Packet configuration register 1 + 0x518 read-write + 0x00000000 + 0x20 - EVENTS_TXSTARTED - 0 - 0 + MAXLEN + Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. + 0 + 7 + + + STATLEN + Static length in number of bytes + 8 + 15 + + + BALEN + Base address length in number of bytes + 16 + 18 + + + ENDIAN + On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. + 24 + 24 + + + Little + Least significant bit on air first + 0x0 + + + Big + Most significant bit on air first + 0x1 + + + + + WHITEEN + Enable or disable packet whitening + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + - EVENTS_WRITE - Write command received - 0x164 + BASE0 + Base address 0 + 0x51C read-write + 0x00000000 + 0x20 - EVENTS_WRITE + BASE0 + Base address 0 0 - 0 + 31 - EVENTS_READ - Read command received - 0x168 + BASE1 + Base address 1 + 0x520 read-write + 0x00000000 + 0x20 - EVENTS_READ + BASE1 + Base address 1 0 - 0 + 31 - SHORTS - Shortcut register - 0x200 + PREFIX0 + Prefixes bytes for logical addresses 0-3 + 0x524 read-write + 0x00000000 + 0x20 - WRITE_SUSPEND - Shortcut between WRITE event and SUSPEND task - 13 - 13 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - + AP0 + Address prefix 0. + 0 + 7 - READ_SUSPEND - Shortcut between READ event and SUSPEND task - 14 - 14 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - + AP1 + Address prefix 1. + 8 + 15 + + + AP2 + Address prefix 2. + 16 + 23 + + + AP3 + Address prefix 3. + 24 + 31 - INTEN - Enable or disable interrupt - 0x300 + PREFIX1 + Prefixes bytes for logical addresses 4-7 + 0x528 read-write + 0x00000000 + 0x20 - STOPPED - Enable or disable interrupt for STOPPED event - 1 - 1 + AP4 + Address prefix 4. + 0 + 7 + + + AP5 + Address prefix 5. + 8 + 15 + + + AP6 + Address prefix 6. + 16 + 23 + + + AP7 + Address prefix 7. + 24 + 31 + + + + + TXADDRESS + Transmit address select + 0x52C + read-write + 0x00000000 + 0x20 + + + TXADDRESS + Transmit address select + 0 + 2 + + + + + RXADDRESSES + Receive address select + 0x530 + read-write + 0x00000000 + 0x20 + + + ADDR0 + Enable or disable reception on logical address 0. + 0 + 0 Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 - ERROR - Enable or disable interrupt for ERROR event - 9 - 9 + ADDR1 + Enable or disable reception on logical address 1. + 1 + 1 Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 - RXSTARTED - Enable or disable interrupt for RXSTARTED event - 19 - 19 + ADDR2 + Enable or disable reception on logical address 2. + 2 + 2 Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 - TXSTARTED - Enable or disable interrupt for TXSTARTED event - 20 - 20 + ADDR3 + Enable or disable reception on logical address 3. + 3 + 3 Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 - WRITE - Enable or disable interrupt for WRITE event - 25 - 25 + ADDR4 + Enable or disable reception on logical address 4. + 4 + 4 Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 - READ - Enable or disable interrupt for READ event - 26 - 26 + ADDR5 + Enable or disable reception on logical address 5. + 5 + 5 Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 - - - - INTENSET - Enable interrupt - 0x304 - read-write - - STOPPED - Write '1' to enable interrupt for STOPPED event - 1 - 1 + ADDR6 + Enable or disable reception on logical address 6. + 6 + 6 - read Disabled - Read: Disabled - 0 + Disable + 0x0 Enabled - Read: Enabled - 1 - - - - write - - Set Enable - 1 + 0x1 - ERROR - Write '1' to enable interrupt for ERROR event - 9 - 9 + ADDR7 + Enable or disable reception on logical address 7. + 7 + 7 - read Disabled - Read: Disabled - 0 + Disable + 0x0 Enabled - Read: Enabled - 1 - - - - write - - Set Enable - 1 + 0x1 + + + + CRCCNF + CRC configuration + 0x534 + read-write + 0x00000000 + 0x20 + - RXSTARTED - Write '1' to enable interrupt for RXSTARTED event - 19 - 19 + LEN + CRC length in number of bytes. + 0 + 1 - read Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 + CRC length is zero and CRC calculation is disabled + 0x0 - - - - TXSTARTED - Write '1' to enable interrupt for TXSTARTED event - 20 - 20 - - read - Disabled - Read: Disabled - 0 + One + CRC length is one byte and CRC calculation is enabled + 0x1 - Enabled - Read: Enabled - 1 + Two + CRC length is two bytes and CRC calculation is enabled + 0x2 - - - write - Set - Enable - 1 + Three + CRC length is three bytes and CRC calculation is enabled + 0x3 - WRITE - Write '1' to enable interrupt for WRITE event - 25 - 25 + SKIPADDR + Include or exclude packet address field out of CRC calculation. + 8 + 9 - read - Disabled - Read: Disabled - 0 + Include + CRC calculation includes address field + 0x0 - Enabled - Read: Enabled - 1 + Skip + CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. + 0x1 - - - write - Set - Enable - 1 + Ieee802154 + CRC calculation as per 802.15.4 standard. Starting at first byte after length field. + 0x2 + + + + CRCPOLY + CRC polynomial + 0x538 + read-write + 0x00000000 + 0x20 + - READ - Write '1' to enable interrupt for READ event - 26 - 26 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - + CRCPOLY + CRC polynomial + 0 + 23 - INTENCLR - Disable interrupt - 0x308 + CRCINIT + CRC initial value + 0x53C read-write + 0x00000000 + 0x20 - STOPPED - Write '1' to disable interrupt for STOPPED event - 1 - 1 + CRCINIT + CRC initial value + 0 + 23 + + + + + TIFS + Interframe spacing in us + 0x544 + read-write + 0x00000000 + 0x20 + + + TIFS + Interframe spacing in us + 0 + 9 + + + + + RSSISAMPLE + RSSI sample + 0x548 + read-only + 0x00000000 + 0x20 + + + RSSISAMPLE + RSSI sample + 0 + 6 + + + + + STATE + Current radio state + 0x550 + read-only + 0x00000000 + 0x20 + + + STATE + Current radio state + 0 + 3 - read Disabled - Read: Disabled - 0 + RADIO is in the Disabled state + 0x0 - Enabled - Read: Enabled - 1 + RxRu + RADIO is in the RXRU state + 0x1 - - - write - Clear - Disable - 1 + RxIdle + RADIO is in the RXIDLE state + 0x2 - - - - ERROR - Write '1' to disable interrupt for ERROR event - 9 - 9 - - read - Disabled - Read: Disabled - 0 + Rx + RADIO is in the RX state + 0x3 - Enabled - Read: Enabled - 1 + RxDisable + RADIO is in the RXDISABLED state + 0x4 - - - write - Clear - Disable - 1 + TxRu + RADIO is in the TXRU state + 0x9 - - - - RXSTARTED - Write '1' to disable interrupt for RXSTARTED event - 19 - 19 - - read - Disabled - Read: Disabled - 0 + TxIdle + RADIO is in the TXIDLE state + 0xA - Enabled - Read: Enabled - 1 + Tx + RADIO is in the TX state + 0xB - - - write - Clear - Disable - 1 + TxDisable + RADIO is in the TXDISABLED state + 0xC + + + + DATAWHITEIV + Data whitening initial value + 0x554 + read-write + 0x00000040 + 0x20 + - TXSTARTED - Write '1' to disable interrupt for TXSTARTED event - 20 - 20 + DATAWHITEIV + Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. + 0 + 6 + + + + + BCC + Bit counter compare + 0x560 + read-write + 0x00000000 + 0x20 + + + BCC + Bit counter compare + 0 + 31 + + + + + 0x8 + 0x4 + DAB[%s] + Description collection: Device address base segment n + 0x600 + read-write + 0x00000000 + 0x20 + + + DAB + Device address base segment n + 0 + 31 + + + + + 0x8 + 0x4 + DAP[%s] + Description collection: Device address prefix n + 0x620 + read-write + 0x00000000 + 0x20 + + + DAP + Device address prefix n + 0 + 15 + + + + + DACNF + Device address match configuration + 0x640 + read-write + 0x00000000 + 0x20 + + + ENA0 + Enable or disable device address matching using device address 0 + 0 + 0 - read Disabled - Read: Disabled - 0 + Disabled + 0x0 Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 + Enabled + 0x1 - WRITE - Write '1' to disable interrupt for WRITE event - 25 - 25 + ENA1 + Enable or disable device address matching using device address 1 + 1 + 1 - read Disabled - Read: Disabled - 0 + Disabled + 0x0 Enabled - Read: Enabled - 1 + Enabled + 0x1 + + + ENA2 + Enable or disable device address matching using device address 2 + 2 + 2 - write - Clear - Disable - 1 + Disabled + Disabled + 0x0 + + + Enabled + Enabled + 0x1 - READ - Write '1' to disable interrupt for READ event - 26 - 26 + ENA3 + Enable or disable device address matching using device address 3 + 3 + 3 - read Disabled - Read: Disabled - 0 + Disabled + 0x0 Enabled - Read: Enabled - 1 + Enabled + 0x1 + + + ENA4 + Enable or disable device address matching using device address 4 + 4 + 4 - write - Clear - Disable - 1 + Disabled + Disabled + 0x0 + + + Enabled + Enabled + 0x1 - - - - ERRORSRC - Error source - 0x4D0 - read-write - oneToClear - - OVERFLOW - RX buffer overflow detected, and prevented - 0 - 0 + ENA5 + Enable or disable device address matching using device address 5 + 5 + 5 - NotDetected - Error did not occur - 0 + Disabled + Disabled + 0x0 - Detected - Error occurred - 1 + Enabled + Enabled + 0x1 - DNACK - NACK sent after receiving a data byte - 2 - 2 + ENA6 + Enable or disable device address matching using device address 6 + 6 + 6 - NotReceived - Error did not occur - 0 + Disabled + Disabled + 0x0 - Received - Error occurred - 1 + Enabled + Enabled + 0x1 - OVERREAD - TX buffer over-read detected, and prevented - 3 - 3 + ENA7 + Enable or disable device address matching using device address 7 + 7 + 7 - NotDetected - Error did not occur - 0 + Disabled + Disabled + 0x0 - Detected - Error occurred - 1 + Enabled + Enabled + 0x1 - - - - MATCH - Status register indicating which address had a match - 0x4D4 - read-only - - MATCH - Which of the addresses in {ADDRESS} matched the incoming address - 0 - 0 + TXADD0 + TxAdd for device address 0 + 8 + 8 + + + TXADD1 + TxAdd for device address 1 + 9 + 9 + + + TXADD2 + TxAdd for device address 2 + 10 + 10 + + + TXADD3 + TxAdd for device address 3 + 11 + 11 + + + TXADD4 + TxAdd for device address 4 + 12 + 12 + + + TXADD5 + TxAdd for device address 5 + 13 + 13 + + + TXADD6 + TxAdd for device address 6 + 14 + 14 + + + TXADD7 + TxAdd for device address 7 + 15 + 15 - ENABLE - Enable TWIS - 0x500 + MHRMATCHCONF + Search pattern configuration + 0x644 read-write + 0x00000000 + 0x20 - ENABLE - Enable or disable TWIS + MHRMATCHCONF + Search pattern configuration 0 - 3 - - - Disabled - Disable TWIS - 0 - - - Enabled - Enable TWIS - 9 - - + 31 - - PSEL - Unspecified - TWIS_PSEL - 0x508 - - SCL - Pin select for SCL signal - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - SDA - Pin select for SDA signal - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - RXD - RXD EasyDMA channel - TWIS_RXD - 0x534 - - PTR - RXD Data pointer - 0x000 - read-write - - - PTR - RXD Data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in RXD buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in RXD buffer - 0 - 15 - - - - - AMOUNT - Number of bytes transferred in the last RXD transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last RXD transaction - 0 - 15 - - - - - - TXD - TXD EasyDMA channel - TWIS_TXD - 0x544 - - PTR - TXD Data pointer - 0x000 - read-write - - - PTR - TXD Data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in TXD buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in TXD buffer - 0 - 15 - - - - - AMOUNT - Number of bytes transferred in the last TXD transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last TXD transaction - 0 - 15 - - - - - 2 - 0x4 - ADDRESS[%s] - Description collection[n]: TWI slave address n - 0x588 + MHRMATCHMAS + Pattern mask + 0x648 read-write + 0x00000000 + 0x20 - ADDRESS - TWI slave address + MHRMATCHMAS + Pattern mask 0 - 6 + 31 - CONFIG - Configuration register for the address match mechanism - 0x594 + MODECNF0 + Radio mode configuration register 0 + 0x650 read-write - 0x00000001 + 0x00000200 + 0x20 - ADDRESS0 - Enable or disable address matching on ADDRESS[0] + RU + Radio ramp-up time 0 0 - Disabled - Disabled - 0 + Default + Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51 + 0x0 - Enabled - Enabled - 1 + Fast + Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specification for more information + 0x1 - ADDRESS1 - Enable or disable address matching on ADDRESS[1] - 1 - 1 + DTX + Default TX value + 8 + 9 - Disabled - Disabled - 0 + B1 + Transmit '1' + 0x0 - Enabled - Enabled - 1 + B0 + Transmit '0' + 0x1 - - - - - - ORC - Over-read character. Character sent out in case of an over-read of the transmit buffer. - 0x5C0 - read-write - - - ORC - Over-read character. Character sent out in case of an over-read of the transmit buffer. - 0 - 7 - - - - - - - SPI1 - Serial Peripheral Interface 1 - 0x40004000 - - SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 - 4 - - - - SPIM1 - Serial Peripheral Interface Master with EasyDMA 1 - 0x40004000 - SPI1 - - SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 - 4 - - - - SPIS1 - SPI Slave 1 - 0x40004000 - SPI1 - - SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 - 4 - - - - TWI1 - I2C compatible Two-Wire Interface 1 - 0x40004000 - SPI1 - - SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 - 4 - - - - TWIM1 - I2C compatible Two-Wire Master Interface with EasyDMA 1 - 0x40004000 - SPI1 - - SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 - 4 - - - - TWIS1 - I2C compatible Two-Wire Slave Interface with EasyDMA 1 - 0x40004000 - SPI1 - - SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 - 4 - - - - NFCT - NFC-A compatible radio - 0x40005000 - - 0 - 0x1000 - registers - - - NFCT - 5 - - NFCT - 0x20 - - - TASKS_ACTIVATE - Activate NFCT peripheral for incoming and outgoing frames, change state to activated - 0x000 - write-only - - - TASKS_ACTIVATE - 0 - 0 - - - - - TASKS_DISABLE - Disable NFCT peripheral - 0x004 - write-only - - - TASKS_DISABLE - 0 - 0 - - - - - TASKS_SENSE - Enable NFC sense field mode, change state to sense mode - 0x008 - write-only - - - TASKS_SENSE - 0 - 0 - - - - - TASKS_STARTTX - Start transmission of an outgoing frame, change state to transmit - 0x00C - write-only - - - TASKS_STARTTX - 0 - 0 + + Center + Transmit center frequency + 0x2 + + - TASKS_ENABLERXDATA - Initializes the EasyDMA for receive. - 0x01C - write-only + SFD + IEEE 802.15.4 start of frame delimiter + 0x660 + read-write + 0x000000A7 + 0x20 - TASKS_ENABLERXDATA + SFD + IEEE 802.15.4 start of frame delimiter 0 - 0 + 7 - TASKS_GOIDLE - Force state machine to IDLE state - 0x024 - write-only + EDCNT + IEEE 802.15.4 energy detect loop count + 0x664 + read-write + 0x00000000 + 0x20 - TASKS_GOIDLE + EDCNT + IEEE 802.15.4 energy detect loop count 0 - 0 + 20 - TASKS_GOSLEEP - Force state machine to SLEEP_A state - 0x028 - write-only + EDSAMPLE + IEEE 802.15.4 energy detect level + 0x668 + read-write + 0x00000000 + 0x20 - TASKS_GOSLEEP + EDLVL + IEEE 802.15.4 energy detect level 0 - 0 + 7 - EVENTS_READY - The NFCT peripheral is ready to receive and send frames - 0x100 + CCACTRL + IEEE 802.15.4 clear channel assessment control + 0x66C read-write + 0x052D0000 + 0x20 - EVENTS_READY + CCAMODE + CCA mode of operation 0 - 0 + 2 + + + EdMode + Energy above threshold + 0x0 + + + CarrierMode + Carrier seen + 0x1 + + + CarrierAndEdMode + Energy above threshold AND carrier seen + 0x2 + + + CarrierOrEdMode + Energy above threshold OR carrier seen + 0x3 + + + EdModeTest1 + Energy above threshold test mode that will abort when first ED measurement over threshold is seen. No averaging. + 0x4 + + - - - - EVENTS_FIELDDETECTED - Remote NFC field detected - 0x104 - read-write - - EVENTS_FIELDDETECTED - 0 - 0 + CCAEDTHRES + CCA energy busy threshold. Used in all the CCA modes except CarrierMode. + 8 + 15 - - - - EVENTS_FIELDLOST - Remote NFC field lost - 0x108 - read-write - - EVENTS_FIELDLOST - 0 - 0 + CCACORRTHRES + CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode and CarrierOrEdMode. + 16 + 23 - - - - EVENTS_TXFRAMESTART - Marks the start of the first symbol of a transmitted frame - 0x10C - read-write - - EVENTS_TXFRAMESTART - 0 - 0 + CCACORRCNT + Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect is enabled. + 24 + 31 - EVENTS_TXFRAMEEND - Marks the end of the last transmitted on-air symbol of a frame - 0x110 + POWER + Peripheral power control + 0xFFC read-write + 0x00000001 + 0x20 - EVENTS_TXFRAMEEND + POWER + Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. 0 0 + + + Disabled + Peripheral is powered off + 0x0 + + + Enabled + Peripheral is powered on + 0x1 + + + + + + UART0 + Universal Asynchronous Receiver/Transmitter + 0x40002000 + UART + + 0 + 0x1000 + registers + + + UART0_UARTE0 + 2 + + UART + 0x20 + - EVENTS_RXFRAMESTART - Marks the end of the first symbol of a received frame - 0x114 - read-write + TASKS_STARTRX + Start UART receiver + 0x000 + write-only + 0x00000000 + 0x20 - EVENTS_RXFRAMESTART + TASKS_STARTRX + Start UART receiver 0 0 + + + Trigger + Trigger task + 0x1 + + - EVENTS_RXFRAMEEND - Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer - 0x118 - read-write + TASKS_STOPRX + Stop UART receiver + 0x004 + write-only + 0x00000000 + 0x20 - EVENTS_RXFRAMEEND + TASKS_STOPRX + Stop UART receiver 0 0 + + + Trigger + Trigger task + 0x1 + + - EVENTS_ERROR - NFC error reported. The ERRORSTATUS register contains details on the source of the error. - 0x11C - read-write + TASKS_STARTTX + Start UART transmitter + 0x008 + write-only + 0x00000000 + 0x20 - EVENTS_ERROR + TASKS_STARTTX + Start UART transmitter 0 0 + + + Trigger + Trigger task + 0x1 + + - EVENTS_RXERROR - NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. - 0x128 - read-write + TASKS_STOPTX + Stop UART transmitter + 0x00C + write-only + 0x00000000 + 0x20 - EVENTS_RXERROR + TASKS_STOPTX + Stop UART transmitter 0 0 + + + Trigger + Trigger task + 0x1 + + - EVENTS_ENDRX - RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. - 0x12C - read-write + TASKS_SUSPEND + Suspend UART + 0x01C + write-only + 0x00000000 + 0x20 - EVENTS_ENDRX + TASKS_SUSPEND + Suspend UART 0 0 + + + Trigger + Trigger task + 0x1 + + - EVENTS_ENDTX - Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer - 0x130 + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0x100 read-write + 0x00000000 + 0x20 - EVENTS_ENDTX + EVENTS_CTS + CTS is activated (set low). Clear To Send. 0 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + - EVENTS_AUTOCOLRESSTARTED - Auto collision resolution process has started - 0x138 + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0x104 read-write + 0x00000000 + 0x20 - EVENTS_AUTOCOLRESSTARTED + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. 0 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + - EVENTS_COLLISION - NFC auto collision resolution error reported. - 0x148 + EVENTS_RXDRDY + Data received in RXD + 0x108 read-write + 0x00000000 + 0x20 - EVENTS_COLLISION + EVENTS_RXDRDY + Data received in RXD 0 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + - EVENTS_SELECTED - NFC auto collision resolution successfully completed - 0x14C + EVENTS_TXDRDY + Data sent from TXD + 0x11C read-write + 0x00000000 + 0x20 - EVENTS_SELECTED + EVENTS_TXDRDY + Data sent from TXD 0 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + - EVENTS_STARTED - EasyDMA is ready to receive or send frames. - 0x150 + EVENTS_ERROR + Error detected + 0x124 read-write + 0x00000000 + 0x20 - EVENTS_STARTED + EVENTS_ERROR + Error detected 0 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + - SHORTS - Shortcut register - 0x200 + EVENTS_RXTO + Receiver timeout + 0x144 read-write + 0x00000000 + 0x20 - FIELDDETECTED_ACTIVATE - Shortcut between FIELDDETECTED event and ACTIVATE task + EVENTS_RXTO + Receiver timeout 0 0 - Disabled - Disable shortcut - 0 + NotGenerated + Event not generated + 0x0 - Enabled - Enable shortcut - 1 + Generated + Event generated + 0x1 + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + - FIELDLOST_SENSE - Shortcut between FIELDLOST event and SENSE task - 1 - 1 + CTS_STARTRX + Shortcut between event CTS and task STARTRX + 3 + 3 Disabled Disable shortcut - 0 + 0x0 Enabled Enable shortcut - 1 + 0x1 - TXFRAMEEND_ENABLERXDATA - Shortcut between TXFRAMEEND event and ENABLERXDATA task - 5 - 5 + NCTS_STOPRX + Shortcut between event NCTS and task STOPRX + 4 + 4 Disabled Disable shortcut - 0 + 0x0 Enabled Enable shortcut - 1 + 0x1 - INTEN - Enable or disable interrupt - 0x300 + INTENSET + Enable interrupt + 0x304 read-write + 0x00000000 + 0x20 - READY - Enable or disable interrupt for READY event + CTS + Write '1' to enable interrupt for event CTS 0 0 + read Disabled - Disable - 0 + Read: Disabled + 0x0 Enabled - Enable - 1 - - - - - FIELDDETECTED - Enable or disable interrupt for FIELDDETECTED event - 1 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - FIELDLOST - Enable or disable interrupt for FIELDLOST event - 2 - 2 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TXFRAMESTART - Enable or disable interrupt for TXFRAMESTART event - 3 - 3 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TXFRAMEEND - Enable or disable interrupt for TXFRAMEEND event - 4 - 4 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RXFRAMESTART - Enable or disable interrupt for RXFRAMESTART event - 5 - 5 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RXFRAMEEND - Enable or disable interrupt for RXFRAMEEND event - 6 - 6 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ERROR - Enable or disable interrupt for ERROR event - 7 - 7 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RXERROR - Enable or disable interrupt for RXERROR event - 10 - 10 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ENDRX - Enable or disable interrupt for ENDRX event - 11 - 11 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ENDTX - Enable or disable interrupt for ENDTX event - 12 - 12 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - AUTOCOLRESSTARTED - Enable or disable interrupt for AUTOCOLRESSTARTED event - 14 - 14 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - COLLISION - Enable or disable interrupt for COLLISION event - 18 - 18 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - SELECTED - Enable or disable interrupt for SELECTED event - 19 - 19 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - STARTED - Enable or disable interrupt for STARTED event - 20 - 20 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - READY - Write '1' to enable interrupt for READY event - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 + Read: Enabled + 0x1 @@ -16671,13 +15475,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - FIELDDETECTED - Write '1' to enable interrupt for FIELDDETECTED event + NCTS + Write '1' to enable interrupt for event NCTS 1 1 @@ -16685,12 +15489,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -16698,13 +15502,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - FIELDLOST - Write '1' to enable interrupt for FIELDLOST event + RXDRDY + Write '1' to enable interrupt for event RXDRDY 2 2 @@ -16712,93 +15516,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TXFRAMESTART - Write '1' to enable interrupt for TXFRAMESTART event - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TXFRAMEEND - Write '1' to enable interrupt for TXFRAMEEND event - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RXFRAMESTART - Write '1' to enable interrupt for RXFRAMESTART event - 5 - 5 - - read - - Disabled - Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -16806,26 +15529,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - RXFRAMEEND - Write '1' to enable interrupt for RXFRAMEEND event - 6 - 6 + TXDRDY + Write '1' to enable interrupt for event TXDRDY + 7 + 7 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -16833,26 +15556,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 ERROR - Write '1' to enable interrupt for ERROR event - 7 - 7 + Write '1' to enable interrupt for event ERROR + 9 + 9 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -16860,26 +15583,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - RXERROR - Write '1' to enable interrupt for RXERROR event - 10 - 10 + RXTO + Write '1' to enable interrupt for event RXTO + 17 + 17 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -16887,1408 +15610,1365 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + - ENDRX - Write '1' to enable interrupt for ENDRX event - 11 - 11 + CTS + Write '1' to disable interrupt for event CTS + 0 + 0 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Set - Enable - 1 + Clear + Disable + 0x1 - ENDTX - Write '1' to enable interrupt for ENDTX event - 12 - 12 + NCTS + Write '1' to disable interrupt for event NCTS + 1 + 1 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Set - Enable - 1 + Clear + Disable + 0x1 - AUTOCOLRESSTARTED - Write '1' to enable interrupt for AUTOCOLRESSTARTED event - 14 - 14 + RXDRDY + Write '1' to disable interrupt for event RXDRDY + 2 + 2 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Set - Enable - 1 + Clear + Disable + 0x1 - COLLISION - Write '1' to enable interrupt for COLLISION event - 18 - 18 + TXDRDY + Write '1' to disable interrupt for event TXDRDY + 7 + 7 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Set - Enable - 1 + Clear + Disable + 0x1 - SELECTED - Write '1' to enable interrupt for SELECTED event - 19 - 19 + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Set - Enable - 1 + Clear + Disable + 0x1 - STARTED - Write '1' to enable interrupt for STARTED event - 20 - 20 + RXTO + Write '1' to disable interrupt for event RXTO + 17 + 17 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Set - Enable - 1 + Clear + Disable + 0x1 - INTENCLR - Disable interrupt - 0x308 + ERRORSRC + Error source + 0x480 read-write + 0x00000000 + oneToClear + 0x20 - READY - Write '1' to disable interrupt for READY event + OVERRUN + Overrun error 0 0 read - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 + NotPresent + Read: error not present + 0x0 - - - write - Clear - Disable - 1 + Present + Read: error present + 0x1 - FIELDDETECTED - Write '1' to disable interrupt for FIELDDETECTED event + PARITY + Parity error 1 1 read - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 + NotPresent + Read: error not present + 0x0 - - - write - Clear - Disable - 1 + Present + Read: error present + 0x1 - FIELDLOST - Write '1' to disable interrupt for FIELDLOST event + FRAMING + Framing error occurred 2 2 read - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 + NotPresent + Read: error not present + 0x0 - - - write - Clear - Disable - 1 + Present + Read: error present + 0x1 - TXFRAMESTART - Write '1' to disable interrupt for TXFRAMESTART event + BREAK + Break condition 3 3 read - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 + NotPresent + Read: error not present + 0x0 - - - write - Clear - Disable - 1 + Present + Read: error present + 0x1 + + + + ENABLE + Enable UART + 0x500 + read-write + 0x00000000 + 0x20 + - TXFRAMEEND - Write '1' to disable interrupt for TXFRAMEEND event - 4 - 4 + ENABLE + Enable or disable UART + 0 + 3 - read Disabled - Read: Disabled - 0 + Disable UART + 0x0 Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 + Enable UART + 0x4 + + + + PSEL + Unspecified + UART_PSEL + read-write + 0x508 + + RTS + Pin select for RTS + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + TXD + Pin select for TXD + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + CTS + Pin select for CTS + 0x008 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + RXD + Pin select for RXD + 0x00C + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + RXD + RXD register. Register is cleared on read and the double buffered byte will be moved to RXD if it exists. + 0x518 + read-only + 0x00000000 + modifyExternal + 0x20 + + + RXD + RX data received in previous transfers, double buffered + 0 + 7 + + + + + TXD + TXD register + 0x51C + write-only + 0x00000000 + 0x20 + - RXFRAMESTART - Write '1' to disable interrupt for RXFRAMESTART event - 5 - 5 + TXD + TX data to be transferred + 0 + 7 + + + + + BAUDRATE + Baud rate. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + 0x20 + + + BAUDRATE + Baud rate + 0 + 31 - read - Disabled - Read: Disabled - 0 + Baud1200 + 1200 baud (actual rate: 1205) + 0x0004F000 - Enabled - Read: Enabled - 1 + Baud2400 + 2400 baud (actual rate: 2396) + 0x0009D000 - - - write - Clear - Disable - 1 + Baud4800 + 4800 baud (actual rate: 4808) + 0x0013B000 - - - - RXFRAMEEND - Write '1' to disable interrupt for RXFRAMEEND event - 6 - 6 - - read - Disabled - Read: Disabled - 0 + Baud9600 + 9600 baud (actual rate: 9598) + 0x00275000 - Enabled - Read: Enabled - 1 + Baud14400 + 14400 baud (actual rate: 14414) + 0x003B0000 - - - write - Clear - Disable - 1 + Baud19200 + 19200 baud (actual rate: 19208) + 0x004EA000 - - - - ERROR - Write '1' to disable interrupt for ERROR event - 7 - 7 - - read - Disabled - Read: Disabled - 0 + Baud28800 + 28800 baud (actual rate: 28829) + 0x0075F000 - Enabled - Read: Enabled - 1 + Baud31250 + 31250 baud + 0x00800000 - - - write - Clear - Disable - 1 + Baud38400 + 38400 baud (actual rate: 38462) + 0x009D5000 - - - - RXERROR - Write '1' to disable interrupt for RXERROR event - 10 - 10 - - read - Disabled - Read: Disabled - 0 + Baud56000 + 56000 baud (actual rate: 55944) + 0x00E50000 - Enabled - Read: Enabled - 1 + Baud57600 + 57600 baud (actual rate: 57762) + 0x00EBF000 - - - write - Clear - Disable - 1 + Baud76800 + 76800 baud (actual rate: 76923) + 0x013A9000 - - - - ENDRX - Write '1' to disable interrupt for ENDRX event - 11 - 11 - - read - Disabled - Read: Disabled - 0 + Baud115200 + 115200 baud (actual rate: 115942) + 0x01D7E000 - Enabled - Read: Enabled - 1 + Baud230400 + 230400 baud (actual rate: 231884) + 0x03AFB000 - - - write - Clear - Disable - 1 + Baud250000 + 250000 baud + 0x04000000 - - - - ENDTX - Write '1' to disable interrupt for ENDTX event - 12 - 12 - - read - Disabled - Read: Disabled - 0 + Baud460800 + 460800 baud (actual rate: 470588) + 0x075F7000 - Enabled - Read: Enabled - 1 + Baud921600 + 921600 baud (actual rate: 941176) + 0x0EBED000 - - - write - Clear - Disable - 1 + Baud1M + 1Mega baud + 0x10000000 + + + + CONFIG + Configuration of parity and hardware flow control + 0x56C + read-write + 0x00000000 + 0x20 + - AUTOCOLRESSTARTED - Write '1' to disable interrupt for AUTOCOLRESSTARTED event - 14 - 14 + HWFC + Hardware flow control + 0 + 0 - read Disabled - Read: Disabled - 0 + Disabled + 0x0 Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 + Enabled + 0x1 - COLLISION - Write '1' to disable interrupt for COLLISION event - 18 - 18 + PARITY + Parity + 1 + 3 - read - - Disabled - Read: Disabled - 0 - - Enabled - Read: Enabled - 1 + Excluded + Exclude parity bit + 0x0 - - - write - Clear - Disable - 1 + Included + Include parity bit + 0x7 - SELECTED - Write '1' to disable interrupt for SELECTED event - 19 - 19 + STOP + Stop bits + 4 + 4 - read - Disabled - Read: Disabled - 0 + One + One stop bit + 0x0 - Enabled - Read: Enabled - 1 + Two + Two stop bits + 0x1 + + + + + + + UARTE0 + UART with EasyDMA 0 + 0x40002000 + UART0 + UARTE + + 0 + 0x1000 + registers + + + UART0_UARTE0 + 2 + + UARTE + 0x20 + + + TASKS_STARTRX + Start UART receiver + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_STARTRX + Start UART receiver + 0 + 0 - write - Clear - Disable - 1 + Trigger + Trigger task + 0x1 + + + + TASKS_STOPRX + Stop UART receiver + 0x004 + write-only + 0x00000000 + 0x20 + - STARTED - Write '1' to disable interrupt for STARTED event - 20 - 20 + TASKS_STOPRX + Stop UART receiver + 0 + 0 - read - - Disabled - Read: Disabled - 0 - - Enabled - Read: Enabled - 1 + Trigger + Trigger task + 0x1 + + + + + TASKS_STARTTX + Start UART transmitter + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_STARTTX + Start UART transmitter + 0 + 0 - write - Clear - Disable - 1 + Trigger + Trigger task + 0x1 - ERRORSTATUS - NFC Error Status register - 0x404 - read-write - oneToClear + TASKS_STOPTX + Stop UART transmitter + 0x00C + write-only + 0x00000000 + 0x20 - FRAMEDELAYTIMEOUT - No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX + TASKS_STOPTX + Stop UART transmitter 0 0 - + + + Trigger + Trigger task + 0x1 + + + - - FRAMESTATUS - Unspecified - NFCT_FRAMESTATUS - 0x40C - - RX - Result of last incoming frame - 0x000 - read-write - oneToClear - - - CRCERROR - No valid end of frame (EoF) detected - 0 - 0 - - - CRCCorrect - Valid CRC detected - 0 - - - CRCError - CRC received does not match local check - 1 - - - - - PARITYSTATUS - Parity status of received frame - 2 - 2 - - - ParityOK - Frame received with parity OK - 0 - - - ParityError - Frame received with parity error - 1 - - - - - OVERRUN - Overrun detected - 3 - 3 - - - NoOverrun - No overrun detected - 0 - - - Overrun - Overrun error - 1 - - - - - - - NFCTAGSTATE - NfcTag state register - 0x410 - read-only + TASKS_FLUSHRX + Flush RX FIFO into RX buffer + 0x02C + write-only + 0x00000000 + 0x20 - NFCTAGSTATE - NfcTag state + TASKS_FLUSHRX + Flush RX FIFO into RX buffer 0 - 2 + 0 - Disabled - Disabled or sense - 0 - - - RampUp - RampUp - 2 + Trigger + Trigger task + 0x1 + + + + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0 + 0 + - Idle - Idle - 3 + NotGenerated + Event not generated + 0x0 - Receive - Receive - 4 + Generated + Event generated + 0x1 + + + + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0 + 0 + - FrameDelay - FrameDelay - 5 + NotGenerated + Event not generated + 0x0 - Transmit - Transmit - 6 + Generated + Event generated + 0x1 - SLEEPSTATE - Sleep state during automatic collision resolution - 0x420 - read-only + EVENTS_RXDRDY + Data received in RXD (but potentially not yet transferred to Data RAM) + 0x108 + read-write 0x00000000 + 0x20 - SLEEPSTATE - Reflects the sleep state during automatic collision resolution. Set to IDLE - by a GOIDLE task. Set to SLEEP_A when a valid SLEEP_REQ frame is received or by a - GOSLEEP task. + EVENTS_RXDRDY + Data received in RXD (but potentially not yet transferred to Data RAM) 0 0 - Idle - State is IDLE. - 0 + NotGenerated + Event not generated + 0x0 - SleepA - State is SLEEP_A. - 1 + Generated + Event generated + 0x1 - FIELDPRESENT - Indicates the presence or not of a valid field - 0x43C - read-only + EVENTS_ENDRX + Receive buffer is filled up + 0x110 + read-write + 0x00000000 + 0x20 - FIELDPRESENT - Indicates if a valid field is present. Available only in the activated state. + EVENTS_ENDRX + Receive buffer is filled up 0 0 - NoField - No valid field detected - 0 + NotGenerated + Event not generated + 0x0 - FieldPresent - Valid field detected - 1 + Generated + Event generated + 0x1 + + + + EVENTS_TXDRDY + Data sent from TXD + 0x11C + read-write + 0x00000000 + 0x20 + - LOCKDETECT - Indicates if the low level has locked to the field - 1 - 1 + EVENTS_TXDRDY + Data sent from TXD + 0 + 0 - NotLocked - Not locked to field - 0 + NotGenerated + Event not generated + 0x0 - Locked - Locked to field - 1 + Generated + Event generated + 0x1 - FRAMEDELAYMIN - Minimum frame delay - 0x504 + EVENTS_ENDTX + Last TX byte transmitted + 0x120 read-write - 0x00000480 + 0x00000000 + 0x20 - FRAMEDELAYMIN - Minimum frame delay in number of 13.56 MHz clocks + EVENTS_ENDTX + Last TX byte transmitted 0 - 15 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + - FRAMEDELAYMAX - Maximum frame delay - 0x508 + EVENTS_ERROR + Error detected + 0x124 read-write - 0x00001000 + 0x00000000 + 0x20 - FRAMEDELAYMAX - Maximum frame delay in number of 13.56 MHz clocks + EVENTS_ERROR + Error detected 0 - 19 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + - FRAMEDELAYMODE - Configuration register for the Frame Delay Timer - 0x50C + EVENTS_RXTO + Receiver timeout + 0x144 read-write - 0x00000001 + 0x00000000 + 0x20 - FRAMEDELAYMODE - Configuration register for the Frame Delay Timer + EVENTS_RXTO + Receiver timeout 0 - 1 + 0 - FreeRun - Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. - 0 + NotGenerated + Event not generated + 0x0 - Window - Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX - 1 + Generated + Event generated + 0x1 + + + + + + EVENTS_RXSTARTED + UART receiver has started + 0x14C + read-write + 0x00000000 + 0x20 + + + EVENTS_RXSTARTED + UART receiver has started + 0 + 0 + - ExactVal - Frame is transmitted exactly at FRAMEDELAYMAX - 2 + NotGenerated + Event not generated + 0x0 - WindowGrid - Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX - 3 + Generated + Event generated + 0x1 - PACKETPTR - Packet pointer for TXD and RXD data storage in Data RAM - 0x510 + EVENTS_TXSTARTED + UART transmitter has started + 0x150 read-write 0x00000000 + 0x20 - PTR - Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte-aligned RAM address. + EVENTS_TXSTARTED + UART transmitter has started 0 - 31 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + - MAXLEN - Size of the RAM buffer allocated to TXD and RXD data storage each - 0x514 + EVENTS_TXSTOPPED + Transmitter stopped + 0x158 read-write + 0x00000000 + 0x20 - MAXLEN - Size of the RAM buffer allocated to TXD and RXD data storage each + EVENTS_TXSTOPPED + Transmitter stopped 0 - 8 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + - - TXD - Unspecified - NFCT_TXD - 0x518 - - FRAMECONFIG - Configuration of outgoing frames - 0x000 - read-write - 0x00000017 - - - PARITY - Indicates if parity is added to the frame - 0 - 0 - - - NoParity - Parity is not added to TX frames - 0 - - - Parity - Parity is added to TX frames - 1 - - - - - DISCARDMODE - Discarding unused bits at start or end of a frame - 1 - 1 - - - DiscardEnd - Unused bits are discarded at end of frame (EoF) - 0 - - - DiscardStart - Unused bits are discarded at start of frame (SoF) - 1 - - - - - SOF - Adding SoF or not in TX frames - 2 - 2 - - - NoSoF - SoF symbol not added - 0 - - - SoF - SoF symbol added - 1 - - - - - CRCMODETX - CRC mode for outgoing frames - 4 - 4 - - - NoCRCTX - CRC is not added to the frame - 0 - - - CRC16TX - 16 bit CRC added to the frame based on all the data read from RAM that is used in the frame - 1 - - - - - - - AMOUNT - Size of outgoing frame - 0x004 - read-write - - - TXDATABITS - Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit). - 0 - 2 - - - TXDATABYTES - Number of complete bytes that shall be included in the frame, excluding CRC, parity and framing - 3 - 11 - - - - - - RXD - Unspecified - NFCT_RXD - 0x520 - - FRAMECONFIG - Configuration of incoming frames - 0x000 - read-write - 0x00000015 - - - PARITY - Indicates if parity expected in RX frame - 0 - 0 - - - NoParity - Parity is not expected in RX frames - 0 - - - Parity - Parity is expected in RX frames - 1 - - - - - SOF - SoF expected or not in RX frames - 2 - 2 - - - NoSoF - SoF symbol is not expected in RX frames - 0 - - - SoF - SoF symbol is expected in RX frames - 1 - - - - - CRCMODERX - CRC mode for incoming frames - 4 - 4 - - - NoCRCRX - CRC is not expected in RX frames - 0 - - - CRC16RX - Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated - 1 - - - - - - - AMOUNT - Size of last incoming frame - 0x004 - read-only - - - RXDATABITS - Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing). - 0 - 2 - - - RXDATABYTES - Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing) - 3 - 11 - - - - - NFCID1_LAST - Last NFCID1 part (4, 7 or 10 bytes ID) - 0x590 + SHORTS + Shortcuts between local events and tasks + 0x200 read-write - 0x00006363 + 0x00000000 + 0x20 - NFCID1_Z - NFCID1 byte Z (very last byte sent) - 0 - 7 + ENDRX_STARTRX + Shortcut between event ENDRX and task STARTRX + 5 + 5 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + - NFCID1_Y - NFCID1 byte Y - 8 - 15 - - - NFCID1_X - NFCID1 byte X - 16 - 23 - - - NFCID1_W - NFCID1 byte W - 24 - 31 - - - - - NFCID1_2ND_LAST - Second last NFCID1 part (7 or 10 bytes ID) - 0x594 - read-write - - - NFCID1_V - NFCID1 byte V - 0 - 7 - - - NFCID1_U - NFCID1 byte U - 8 - 15 - - - NFCID1_T - NFCID1 byte T - 16 - 23 - - - - - NFCID1_3RD_LAST - Third last NFCID1 part (10 bytes ID) - 0x598 - read-write - - - NFCID1_S - NFCID1 byte S - 0 - 7 - - - NFCID1_R - NFCID1 byte R - 8 - 15 - - - NFCID1_Q - NFCID1 byte Q - 16 - 23 + ENDRX_STOPRX + Shortcut between event ENDRX and task STOPRX + 6 + 6 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + - AUTOCOLRESCONFIG - Controls the auto collision resolution function. This setting must be done before the NFCT peripheral is enabled. - 0x59C + INTEN + Enable or disable interrupt + 0x300 read-write - 0x00000002 + 0x00000000 + 0x20 - MODE - Enables/disables auto collision resolution + CTS + Enable or disable interrupt for event CTS 0 0 - Enabled - Auto collision resolution enabled - 0 + Disabled + Disable + 0x0 - Disabled - Auto collision resolution disabled - 1 + Enabled + Enable + 0x1 - - - - SENSRES - NFC-A SENS_RES auto-response settings - 0x5A0 - read-write - 0x00000001 - - BITFRAMESDD - Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification - 0 - 4 + NCTS + Enable or disable interrupt for event NCTS + 1 + 1 - SDD00000 - SDD pattern 00000 - 0 + Disabled + Disable + 0x0 - SDD00001 - SDD pattern 00001 - 1 + Enabled + Enable + 0x1 + + + + RXDRDY + Enable or disable interrupt for event RXDRDY + 2 + 2 + - SDD00010 - SDD pattern 00010 - 2 + Disabled + Disable + 0x0 - SDD00100 - SDD pattern 00100 - 4 + Enabled + Enable + 0x1 + + + + ENDRX + Enable or disable interrupt for event ENDRX + 4 + 4 + - SDD01000 - SDD pattern 01000 - 8 + Disabled + Disable + 0x0 - SDD10000 - SDD pattern 10000 - 16 + Enabled + Enable + 0x1 - RFU5 - Reserved for future use. Shall be 0. - 5 - 5 - - - NFCIDSIZE - NFCID1 size. This value is used by the auto collision resolution engine. - 6 + TXDRDY + Enable or disable interrupt for event TXDRDY + 7 7 - NFCID1Single - NFCID1 size: single (4 bytes) - 0 - - - NFCID1Double - NFCID1 size: double (7 bytes) - 1 + Disabled + Disable + 0x0 - NFCID1Triple - NFCID1 size: triple (10 bytes) - 2 + Enabled + Enable + 0x1 - PLATFCONFIG - Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification + ENDTX + Enable or disable interrupt for event ENDTX 8 - 11 - - - RFU74 - Reserved for future use. Shall be 0. - 12 - 15 - - - - - SELRES - NFC-A SEL_RES auto-response settings - 0x5A4 - read-write - - - RFU10 - Reserved for future use. Shall be 0. - 0 - 1 - - - CASCADE - Cascade as defined by the b3 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification (controlled by hardware, shall be 0) - 2 - 2 - - - RFU43 - Reserved for future use. Shall be 0. - 3 - 4 - - - PROTOCOL - Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification - 5 - 6 - - - RFU7 - Reserved for future use. Shall be 0. - 7 - 7 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + - - - - - - GPIOTE - GPIO Tasks and Events - 0x40006000 - - 0 - 0x1000 - registers - - - GPIOTE - 6 - - GPIOTE - 0x20 - - - 8 - 0x4 - TASKS_OUT[%s] - Description collection[n]: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. - 0x000 - write-only - - TASKS_OUT - 0 - 0 + ERROR + Enable or disable interrupt for event ERROR + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + - - - - 8 - 0x4 - TASKS_SET[%s] - Description collection[n]: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. - 0x030 - write-only - - TASKS_SET - 0 - 0 + RXTO + Enable or disable interrupt for event RXTO + 17 + 17 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + - - - - 8 - 0x4 - TASKS_CLR[%s] - Description collection[n]: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. - 0x060 - write-only - - TASKS_CLR - 0 - 0 + RXSTARTED + Enable or disable interrupt for event RXSTARTED + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + - - - - 8 - 0x4 - EVENTS_IN[%s] - Description collection[n]: Event generated from pin specified in CONFIG[n].PSEL - 0x100 - read-write - - EVENTS_IN - 0 - 0 + TXSTARTED + Enable or disable interrupt for event TXSTARTED + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + - - - - EVENTS_PORT - Event generated from multiple input GPIO pins with SENSE mechanism enabled - 0x17C - read-write - - EVENTS_PORT - 0 - 0 + TXSTOPPED + Enable or disable interrupt for event TXSTOPPED + 22 + 22 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + @@ -18297,10 +16977,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Enable interrupt 0x304 read-write + 0x00000000 + 0x20 - IN0 - Write '1' to enable interrupt for IN[0] event + CTS + Write '1' to enable interrupt for event CTS 0 0 @@ -18308,12 +16990,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -18321,13 +17003,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - IN1 - Write '1' to enable interrupt for IN[1] event + NCTS + Write '1' to enable interrupt for event NCTS 1 1 @@ -18335,12 +17017,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -18348,13 +17030,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - IN2 - Write '1' to enable interrupt for IN[2] event + RXDRDY + Write '1' to enable interrupt for event RXDRDY 2 2 @@ -18362,12 +17044,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -18375,26 +17057,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - IN3 - Write '1' to enable interrupt for IN[3] event - 3 - 3 + ENDRX + Write '1' to enable interrupt for event ENDRX + 4 + 4 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -18402,26 +17084,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - IN4 - Write '1' to enable interrupt for IN[4] event - 4 - 4 + TXDRDY + Write '1' to enable interrupt for event TXDRDY + 7 + 7 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -18429,26 +17111,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - IN5 - Write '1' to enable interrupt for IN[5] event - 5 - 5 + ENDTX + Write '1' to enable interrupt for event ENDTX + 8 + 8 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -18456,26 +17138,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - IN6 - Write '1' to enable interrupt for IN[6] event - 6 - 6 + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -18483,26 +17165,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - IN7 - Write '1' to enable interrupt for IN[7] event - 7 - 7 + RXTO + Write '1' to enable interrupt for event RXTO + 17 + 17 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -18510,26 +17192,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - PORT - Write '1' to enable interrupt for PORT event - 31 - 31 + RXSTARTED + Write '1' to enable interrupt for event RXSTARTED + 19 + 19 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -18537,88 +17219,90 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - IN0 - Write '1' to disable interrupt for IN[0] event - 0 - 0 + TXSTARTED + Write '1' to enable interrupt for event TXSTARTED + 20 + 20 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Clear - Disable - 1 + Set + Enable + 0x1 - IN1 - Write '1' to disable interrupt for IN[1] event - 1 - 1 + TXSTOPPED + Write '1' to enable interrupt for event TXSTOPPED + 22 + 22 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Clear - Disable - 1 + Set + Enable + 0x1 + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + - IN2 - Write '1' to disable interrupt for IN[2] event - 2 - 2 + CTS + Write '1' to disable interrupt for event CTS + 0 + 0 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -18626,26 +17310,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - IN3 - Write '1' to disable interrupt for IN[3] event - 3 - 3 + NCTS + Write '1' to disable interrupt for event NCTS + 1 + 1 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -18653,26 +17337,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - IN4 - Write '1' to disable interrupt for IN[4] event - 4 - 4 + RXDRDY + Write '1' to disable interrupt for event RXDRDY + 2 + 2 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -18680,26 +17364,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - IN5 - Write '1' to disable interrupt for IN[5] event - 5 - 5 + ENDRX + Write '1' to disable interrupt for event ENDRX + 4 + 4 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -18707,26 +17391,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - IN6 - Write '1' to disable interrupt for IN[6] event - 6 - 6 + TXDRDY + Write '1' to disable interrupt for event TXDRDY + 7 + 7 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -18734,26 +17418,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - IN7 - Write '1' to disable interrupt for IN[7] event - 7 - 7 + ENDTX + Write '1' to disable interrupt for event ENDTX + 8 + 8 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -18761,26 +17445,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - PORT - Write '1' to disable interrupt for PORT event - 31 - 31 + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -18788,738 +17472,755 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 - - - - - - - 8 - 0x4 - CONFIG[%s] - Description collection[n]: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event - 0x510 - read-write - - - MODE - Mode - 0 - 1 - - - Disabled - Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. - 0 - - - Event - Event mode - 1 - - - Task - Task mode - 3 + 0x1 - PSEL - GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event - 8 - 12 - - - PORT - Port number - 13 - 13 - - - POLARITY - When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. - 16 + RXTO + Write '1' to disable interrupt for event RXTO + 17 17 - - None - Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. - 0 - - - LoToHi - Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. - 1 - - - HiToLo - Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. - 2 - - - Toggle - Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. - 3 - - - - - OUTINIT - When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. - 20 - 20 - - - Low - Task mode: Initial value of pin before task triggering is low - 0 - - - High - Task mode: Initial value of pin before task triggering is high - 1 - - - - - - - - - SAADC - Successive approximation register (SAR) analog-to-digital converter - 0x40007000 - - 0 - 0x1000 - registers - - - SAADC - 7 - - SAADC - 0x20 - - - TASKS_START - Starts the SAADC and prepares the result buffer in RAM - 0x000 - write-only - - - TASKS_START - 0 - 0 - - - - - TASKS_SAMPLE - Takes one SAADC sample - 0x004 - write-only - - - TASKS_SAMPLE - 0 - 0 - - - - - TASKS_STOP - Stops the SAADC and terminates all on-going conversions - 0x008 - write-only - - - TASKS_STOP - 0 - 0 - - - - - TASKS_CALIBRATEOFFSET - Starts offset auto-calibration - 0x00C - write-only - - - TASKS_CALIBRATEOFFSET - 0 - 0 - - - - - EVENTS_STARTED - The SAADC has started - 0x100 - read-write - - - EVENTS_STARTED - 0 - 0 - - - - - EVENTS_END - The SAADC has filled up the result buffer - 0x104 - read-write - - - EVENTS_END - 0 - 0 - - - - - EVENTS_DONE - A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM. - 0x108 - read-write - - - EVENTS_DONE - 0 - 0 - - - - - EVENTS_RESULTDONE - Result ready for transfer to RAM - 0x10C - read-write - - - EVENTS_RESULTDONE - 0 - 0 - - - - - EVENTS_CALIBRATEDONE - Calibration is complete - 0x110 - read-write - - - EVENTS_CALIBRATEDONE - 0 - 0 - - - - - EVENTS_STOPPED - The SAADC has stopped - 0x114 - read-write - - - EVENTS_STOPPED - 0 - 0 - - - - - 8 - 0x008 - EVENTS_CH[%s] - Unspecified - SAADC_EVENTS_CH - 0x118 - - LIMITH - Description cluster[n]: Last result is equal or above CH[n].LIMIT.HIGH - 0x000 - read-write - - - LIMITH - 0 - 0 - - - - - LIMITL - Description cluster[n]: Last result is equal or below CH[n].LIMIT.LOW - 0x004 - read-write - - - LIMITL - 0 - 0 - - - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - - STARTED - Enable or disable interrupt for STARTED event - 0 - 0 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - END - Enable or disable interrupt for END event - 1 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - DONE - Enable or disable interrupt for DONE event - 2 - 2 - + read Disabled - Disable - 0 + Read: Disabled + 0x0 Enabled - Enable - 1 + Read: Enabled + 0x1 - - - RESULTDONE - Enable or disable interrupt for RESULTDONE event - 3 - 3 + write - Disabled + Clear Disable - 0 - - - Enabled - Enable - 1 + 0x1 - CALIBRATEDONE - Enable or disable interrupt for CALIBRATEDONE event - 4 - 4 + RXSTARTED + Write '1' to disable interrupt for event RXSTARTED + 19 + 19 + read Disabled - Disable - 0 + Read: Disabled + 0x0 Enabled - Enable - 1 + Read: Enabled + 0x1 - - - STOPPED - Enable or disable interrupt for STOPPED event - 5 - 5 + write - Disabled + Clear Disable - 0 - - - Enabled - Enable - 1 + 0x1 - CH0LIMITH - Enable or disable interrupt for CH[0].LIMITH event - 6 - 6 + TXSTARTED + Write '1' to disable interrupt for event TXSTARTED + 20 + 20 + read Disabled - Disable - 0 + Read: Disabled + 0x0 Enabled - Enable - 1 + Read: Enabled + 0x1 - - - CH0LIMITL - Enable or disable interrupt for CH[0].LIMITL event - 7 - 7 + write - Disabled + Clear Disable - 0 - - - Enabled - Enable - 1 + 0x1 - CH1LIMITH - Enable or disable interrupt for CH[1].LIMITH event - 8 - 8 + TXSTOPPED + Write '1' to disable interrupt for event TXSTOPPED + 22 + 22 + read Disabled - Disable - 0 + Read: Disabled + 0x0 Enabled - Enable - 1 + Read: Enabled + 0x1 - - - CH1LIMITL - Enable or disable interrupt for CH[1].LIMITL event - 9 - 9 + write - Disabled + Clear Disable - 0 - - - Enabled - Enable - 1 + 0x1 + + + + ERRORSRC + Error source This register is read/write one to clear. + 0x480 + read-write + 0x00000000 + oneToClear + 0x20 + - CH2LIMITH - Enable or disable interrupt for CH[2].LIMITH event - 10 - 10 + OVERRUN + Overrun error + 0 + 0 + read - Disabled - Disable - 0 + NotPresent + Read: error not present + 0x0 - Enabled - Enable - 1 + Present + Read: error present + 0x1 - CH2LIMITL - Enable or disable interrupt for CH[2].LIMITL event - 11 - 11 + PARITY + Parity error + 1 + 1 + read - Disabled - Disable - 0 + NotPresent + Read: error not present + 0x0 - Enabled - Enable - 1 + Present + Read: error present + 0x1 - CH3LIMITH - Enable or disable interrupt for CH[3].LIMITH event - 12 - 12 + FRAMING + Framing error occurred + 2 + 2 + read - Disabled - Disable - 0 + NotPresent + Read: error not present + 0x0 - Enabled - Enable - 1 + Present + Read: error present + 0x1 - CH3LIMITL - Enable or disable interrupt for CH[3].LIMITL event - 13 - 13 + BREAK + Break condition + 3 + 3 + read - Disabled - Disable - 0 + NotPresent + Read: error not present + 0x0 - Enabled - Enable - 1 + Present + Read: error present + 0x1 + + + + ENABLE + Enable UART + 0x500 + read-write + 0x00000000 + 0x20 + - CH4LIMITH - Enable or disable interrupt for CH[4].LIMITH event - 14 - 14 + ENABLE + Enable or disable UARTE + 0 + 3 Disabled - Disable - 0 + Disable UARTE + 0x0 Enabled - Enable - 1 + Enable UARTE + 0x8 - - CH4LIMITL - Enable or disable interrupt for CH[4].LIMITL event - 15 - 15 - - - Disabled - Disable - 0 + + + + PSEL + Unspecified + UARTE_PSEL + read-write + 0x508 + + RTS + Pin select for RTS signal + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + TXD + Pin select for TXD signal + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + CTS + Pin select for CTS signal + 0x008 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + RXD + Pin select for RXD signal + 0x00C + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + BAUDRATE + Baud rate. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + 0x20 + + + BAUDRATE + Baud rate + 0 + 31 + + + Baud1200 + 1200 baud (actual rate: 1205) + 0x0004F000 - Enabled - Enable - 1 + Baud2400 + 2400 baud (actual rate: 2396) + 0x0009D000 - - - - CH5LIMITH - Enable or disable interrupt for CH[5].LIMITH event - 16 - 16 - - Disabled - Disable - 0 + Baud4800 + 4800 baud (actual rate: 4808) + 0x0013B000 - Enabled - Enable - 1 + Baud9600 + 9600 baud (actual rate: 9598) + 0x00275000 - - - - CH5LIMITL - Enable or disable interrupt for CH[5].LIMITL event - 17 - 17 - - Disabled - Disable - 0 + Baud14400 + 14400 baud (actual rate: 14401) + 0x003AF000 - Enabled - Enable - 1 + Baud19200 + 19200 baud (actual rate: 19208) + 0x004EA000 - - - - CH6LIMITH - Enable or disable interrupt for CH[6].LIMITH event - 18 - 18 - - Disabled - Disable - 0 + Baud28800 + 28800 baud (actual rate: 28777) + 0x0075C000 - Enabled - Enable - 1 + Baud31250 + 31250 baud + 0x00800000 + + + Baud38400 + 38400 baud (actual rate: 38369) + 0x009D0000 + + + Baud56000 + 56000 baud (actual rate: 55944) + 0x00E50000 + + + Baud57600 + 57600 baud (actual rate: 57554) + 0x00EB0000 + + + Baud76800 + 76800 baud (actual rate: 76923) + 0x013A9000 + + + Baud115200 + 115200 baud (actual rate: 115108) + 0x01D60000 + + + Baud230400 + 230400 baud (actual rate: 231884) + 0x03B00000 + + + Baud250000 + 250000 baud + 0x04000000 + + + Baud460800 + 460800 baud (actual rate: 457143) + 0x07400000 + + + Baud921600 + 921600 baud (actual rate: 941176) + 0x0F000000 + + + Baud1M + 1 megabaud + 0x10000000 + + + + RXD + RXD EasyDMA channel + UARTE_RXD + read-write + 0x534 + + PTR + Data pointer + 0x000 + read-write + 0x00000000 + 0x20 + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 15 + + + + + + TXD + TXD EasyDMA channel + UARTE_TXD + read-write + 0x544 + + PTR + Data pointer + 0x000 + read-write + 0x00000000 + 0x20 + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 15 + + + + + + CONFIG + Configuration of parity and hardware flow control + 0x56C + read-write + 0x00000000 + 0x20 + - CH6LIMITL - Enable or disable interrupt for CH[6].LIMITL event - 19 - 19 + HWFC + Hardware flow control + 0 + 0 Disabled - Disable - 0 + Disabled + 0x0 Enabled - Enable - 1 + Enabled + 0x1 - CH7LIMITH - Enable or disable interrupt for CH[7].LIMITH event - 20 - 20 + PARITY + Parity + 1 + 3 - Disabled - Disable - 0 + Excluded + Exclude parity bit + 0x0 - Enabled - Enable - 1 + Included + Include even parity bit + 0x7 - CH7LIMITL - Enable or disable interrupt for CH[7].LIMITL event - 21 - 21 + STOP + Stop bits + 4 + 4 - Disabled - Disable - 0 + One + One stop bit + 0x0 - Enabled - Enable - 1 + Two + Two stop bits + 0x1 + + + + SPI0 + Serial Peripheral Interface 0 + 0x40003000 + SPI + + 0 + 0x1000 + registers + + + SPI0_SPIM0_SPIS0_TWI0_TWIM0_TWIS0 + 3 + + SPI + 0x20 + - INTENSET - Enable interrupt - 0x304 + EVENTS_READY + TXD byte sent and RXD byte received + 0x108 read-write + 0x00000000 + 0x20 - STARTED - Write '1' to enable interrupt for STARTED event + EVENTS_READY + TXD byte sent and RXD byte received 0 0 - read - - Disabled - Read: Disabled - 0 - - Enabled - Read: Enabled - 1 + NotGenerated + Event not generated + 0x0 - - - write - Set - Enable - 1 + Generated + Event generated + 0x1 + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + - END - Write '1' to enable interrupt for END event - 1 - 1 + READY + Write '1' to enable interrupt for event READY + 2 + 2 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -19527,13 +18228,23 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + - DONE - Write '1' to enable interrupt for DONE event + READY + Write '1' to disable interrupt for event READY 2 2 @@ -19541,228 +18252,634 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Set - Enable - 1 + Clear + Disable + 0x1 - - RESULTDONE - Write '1' to enable interrupt for RESULTDONE event - 3 + + + + ENABLE + Enable SPI + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable SPI + 0 3 - read Disabled - Read: Disabled - 0 + Disable SPI + 0x0 Enabled - Read: Enabled - 1 + Enable SPI + 0x1 + + + + + PSEL + Unspecified + SPI_PSEL + read-write + 0x508 + + SCK + Pin select for SCK + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + MOSI + Pin select for MOSI signal + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + MISO + Pin select for MISO signal + 0x008 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + RXD + RXD register. Register is cleared on read and the buffer pointer will be modified if read. + 0x518 + read-only + 0x00000000 + modifyExternal + 0x20 + + + RXD + RX data received. Double buffered + 0 + 7 + + + + + TXD + TXD register + 0x51C + read-write + 0x00000000 + 0x20 + + + TXD + TX data to send. Double buffered. + 0 + 7 + + + + + FREQUENCY + SPI frequency. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + 0x20 + + + FREQUENCY + SPI master data rate + 0 + 31 - write - Set - Enable - 1 + K125 + 125 kbps + 0x02000000 + + + K250 + 250 kbps + 0x04000000 + + + K500 + 500 kbps + 0x08000000 + + + M1 + 1 Mbps + 0x10000000 + + + M2 + 2 Mbps + 0x20000000 + + + M4 + 4 Mbps + 0x40000000 + + + M8 + 8 Mbps + 0x80000000 + + + + CONFIG + Configuration register + 0x554 + read-write + 0x00000000 + 0x20 + - CALIBRATEDONE - Write '1' to enable interrupt for CALIBRATEDONE event - 4 - 4 + ORDER + Bit order + 0 + 0 - read - Disabled - Read: Disabled - 0 + MsbFirst + Most significant bit shifted out first + 0x0 - Enabled - Read: Enabled - 1 + LsbFirst + Least significant bit shifted out first + 0x1 + + + CPHA + Serial clock (SCK) phase + 1 + 1 - write - Set - Enable - 1 + Leading + Sample on leading edge of clock, shift serial data on trailing edge + 0x0 + + + Trailing + Sample on trailing edge of clock, shift serial data on leading edge + 0x1 - STOPPED - Write '1' to enable interrupt for STOPPED event - 5 - 5 + CPOL + Serial clock (SCK) polarity + 2 + 2 - read - Disabled - Read: Disabled - 0 + ActiveHigh + Active high + 0x0 - Enabled - Read: Enabled - 1 + ActiveLow + Active low + 0x1 + + + + + + + SPIM0 + Serial Peripheral Interface Master with EasyDMA 0 + 0x40003000 + SPI0 + SPIM + + 0 + 0x1000 + registers + + + SPI0_SPIM0_SPIS0_TWI0_TWIM0_TWIS0 + 3 + + SPIM + 0x20 + + + TASKS_START + Start SPI transaction + 0x010 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start SPI transaction + 0 + 0 - write - Set - Enable - 1 + Trigger + Trigger task + 0x1 + + + + TASKS_STOP + Stop SPI transaction + 0x014 + write-only + 0x00000000 + 0x20 + - CH0LIMITH - Write '1' to enable interrupt for CH[0].LIMITH event - 6 - 6 + TASKS_STOP + Stop SPI transaction + 0 + 0 - read - Disabled - Read: Disabled - 0 + Trigger + Trigger task + 0x1 + + + + + + TASKS_SUSPEND + Suspend SPI transaction + 0x01C + write-only + 0x00000000 + 0x20 + + + TASKS_SUSPEND + Suspend SPI transaction + 0 + 0 + - Enabled - Read: Enabled - 1 + Trigger + Trigger task + 0x1 + + + + + TASKS_RESUME + Resume SPI transaction + 0x020 + write-only + 0x00000000 + 0x20 + + + TASKS_RESUME + Resume SPI transaction + 0 + 0 - write - Set - Enable - 1 + Trigger + Trigger task + 0x1 + + + + EVENTS_STOPPED + SPI transaction has stopped + 0x104 + read-write + 0x00000000 + 0x20 + - CH0LIMITL - Write '1' to enable interrupt for CH[0].LIMITL event - 7 - 7 + EVENTS_STOPPED + SPI transaction has stopped + 0 + 0 - read - Disabled - Read: Disabled - 0 + NotGenerated + Event not generated + 0x0 - Enabled - Read: Enabled - 1 + Generated + Event generated + 0x1 + + + + + EVENTS_ENDRX + End of RXD buffer reached + 0x110 + read-write + 0x00000000 + 0x20 + + + EVENTS_ENDRX + End of RXD buffer reached + 0 + 0 - write - Set - Enable - 1 + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + EVENTS_END + End of RXD buffer and TXD buffer reached + 0x118 + read-write + 0x00000000 + 0x20 + - CH1LIMITH - Write '1' to enable interrupt for CH[1].LIMITH event - 8 - 8 + EVENTS_END + End of RXD buffer and TXD buffer reached + 0 + 0 - read - Disabled - Read: Disabled - 0 + NotGenerated + Event not generated + 0x0 - Enabled - Read: Enabled - 1 + Generated + Event generated + 0x1 + + + + + EVENTS_ENDTX + End of TXD buffer reached + 0x120 + read-write + 0x00000000 + 0x20 + + + EVENTS_ENDTX + End of TXD buffer reached + 0 + 0 - write - Set - Enable - 1 + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + EVENTS_STARTED + Transaction started + 0x14C + read-write + 0x00000000 + 0x20 + - CH1LIMITL - Write '1' to enable interrupt for CH[1].LIMITL event - 9 - 9 + EVENTS_STARTED + Transaction started + 0 + 0 - read - Disabled - Read: Disabled - 0 + NotGenerated + Event not generated + 0x0 - Enabled - Read: Enabled - 1 + Generated + Event generated + 0x1 + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + END_START + Shortcut between event END and task START + 17 + 17 - write - Set - Enable - 1 + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + - CH2LIMITH - Write '1' to enable interrupt for CH[2].LIMITH event - 10 - 10 + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -19770,26 +18887,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - CH2LIMITL - Write '1' to enable interrupt for CH[2].LIMITL event - 11 - 11 - + ENDRX + Write '1' to enable interrupt for event ENDRX + 4 + 4 + read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -19797,26 +18914,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - CH3LIMITH - Write '1' to enable interrupt for CH[3].LIMITH event - 12 - 12 + END + Write '1' to enable interrupt for event END + 6 + 6 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -19824,26 +18941,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - CH3LIMITL - Write '1' to enable interrupt for CH[3].LIMITL event - 13 - 13 + ENDTX + Write '1' to enable interrupt for event ENDTX + 8 + 8 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -19851,26 +18968,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - CH4LIMITH - Write '1' to enable interrupt for CH[4].LIMITH event - 14 - 14 + STARTED + Write '1' to enable interrupt for event STARTED + 19 + 19 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -19878,121 +18995,131 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + - CH4LIMITL - Write '1' to enable interrupt for CH[4].LIMITL event - 15 - 15 + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Set - Enable - 1 + Clear + Disable + 0x1 - CH5LIMITH - Write '1' to enable interrupt for CH[5].LIMITH event - 16 - 16 + ENDRX + Write '1' to disable interrupt for event ENDRX + 4 + 4 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Set - Enable - 1 + Clear + Disable + 0x1 - CH5LIMITL - Write '1' to enable interrupt for CH[5].LIMITL event - 17 - 17 + END + Write '1' to disable interrupt for event END + 6 + 6 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Set - Enable - 1 + Clear + Disable + 0x1 - CH6LIMITH - Write '1' to enable interrupt for CH[6].LIMITH event - 18 - 18 + ENDTX + Write '1' to disable interrupt for event ENDTX + 8 + 8 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Set - Enable - 1 + Clear + Disable + 0x1 - CH6LIMITL - Write '1' to enable interrupt for CH[6].LIMITL event + STARTED + Write '1' to disable interrupt for event STARTED 19 19 @@ -20000,560 +19127,991 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CH7LIMITH - Write '1' to enable interrupt for CH[7].LIMITH event - 20 - 20 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CH7LIMITL - Write '1' to enable interrupt for CH[7].LIMITL event - 21 - 21 - - read - - Disabled - Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Set - Enable - 1 + Clear + Disable + 0x1 - INTENCLR - Disable interrupt - 0x308 + STALLSTAT + Stall status for EasyDMA RAM accesses. The fields in this register are set to STALL by hardware whenever a stall occurs and can be cleared (set to NOSTALL) by the CPU. + 0x400 read-write + 0x00000000 + 0x20 - STARTED - Write '1' to disable interrupt for STARTED event + TX + Stall status for EasyDMA RAM reads 0 0 - read - - Disabled - Read: Disabled - 0 - - Enabled - Read: Enabled - 1 + NOSTALL + No stall + 0x0 - - - write - Clear - Disable - 1 + STALL + A stall has occurred + 0x1 - END - Write '1' to disable interrupt for END event + RX + Stall status for EasyDMA RAM writes 1 1 - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - DONE - Write '1' to disable interrupt for DONE event - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - Enabled - Read: Enabled - 1 + NOSTALL + No stall + 0x0 - - - write - Clear - Disable - 1 + STALL + A stall has occurred + 0x1 + + + + ENABLE + Enable SPIM + 0x500 + read-write + 0x00000000 + 0x20 + - RESULTDONE - Write '1' to disable interrupt for RESULTDONE event - 3 + ENABLE + Enable or disable SPIM + 0 3 - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CALIBRATEDONE - Write '1' to disable interrupt for CALIBRATEDONE event - 4 - 4 - - read Disabled - Read: Disabled - 0 + Disable SPIM + 0x0 Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 + Enable SPIM + 0x7 + + + + PSEL + Unspecified + SPIM_PSEL + read-write + 0x508 + + SCK + Pin select for SCK + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + MOSI + Pin select for MOSI signal + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + MISO + Pin select for MISO signal + 0x008 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + CSN + Pin select for CSN + 0x00C + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + FREQUENCY + SPI frequency. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + 0x20 + - STOPPED - Write '1' to disable interrupt for STOPPED event - 5 - 5 + FREQUENCY + SPI master data rate + 0 + 31 - read - Disabled - Read: Disabled - 0 + K125 + 125 kbps + 0x02000000 - Enabled - Read: Enabled - 1 + K250 + 250 kbps + 0x04000000 - - - write - Clear - Disable - 1 + K500 + 500 kbps + 0x08000000 - - - - CH0LIMITH - Write '1' to disable interrupt for CH[0].LIMITH event - 6 - 6 - - read - Disabled - Read: Disabled - 0 + M1 + 1 Mbps + 0x10000000 - Enabled - Read: Enabled - 1 + M2 + 2 Mbps + 0x20000000 - - - write - Clear - Disable - 1 + M4 + 4 Mbps + 0x40000000 - - - - CH0LIMITL - Write '1' to disable interrupt for CH[0].LIMITL event - 7 - 7 - - read - Disabled - Read: Disabled - 0 + M8 + 8 Mbps + 0x80000000 - Enabled - Read: Enabled - 1 + M16 + 16 Mbps + 0x0A000000 - - - write - Clear - Disable - 1 + M32 + 32 Mbps + 0x14000000 - - CH1LIMITH - Write '1' to disable interrupt for CH[1].LIMITH event - 8 - 8 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 + + + + RXD + RXD EasyDMA channel + SPIM_RXD + read-write + 0x534 + + PTR + Data pointer + 0x000 + read-write + 0x00000000 + 0x20 + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + 0x00000000 + 0x20 + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + + TXD + TXD EasyDMA channel + SPIM_TXD + read-write + 0x544 + + PTR + Data pointer + 0x000 + read-write + 0x00000000 + 0x20 + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Number of bytes in transmit buffer + 0x004 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + 0x00000000 + 0x20 + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + + CONFIG + Configuration register + 0x554 + read-write + 0x00000000 + 0x20 + + + ORDER + Bit order + 0 + 0 + + + MsbFirst + Most significant bit shifted out first + 0x0 + + + LsbFirst + Least significant bit shifted out first + 0x1 - CH1LIMITL - Write '1' to disable interrupt for CH[1].LIMITL event - 9 - 9 + CPHA + Serial clock (SCK) phase + 1 + 1 - read - Disabled - Read: Disabled - 0 + Leading + Sample on leading edge of clock, shift serial data on trailing edge + 0x0 - Enabled - Read: Enabled - 1 + Trailing + Sample on trailing edge of clock, shift serial data on leading edge + 0x1 + + + CPOL + Serial clock (SCK) polarity + 2 + 2 - write - Clear - Disable - 1 + ActiveHigh + Active high + 0x0 + + + ActiveLow + Active low + 0x1 + + + + IFTIMING + Unspecified + SPIM_IFTIMING + read-write + 0x560 + + RXDELAY + Sample delay for input serial data on MISO + 0x000 + read-write + 0x00000002 + 0x20 + + + RXDELAY + Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK. + 0 + 2 + + + + + CSNDUR + Minimum duration between edge of CSN and edge of SCK at the start and the end of a transaction, and minimum duration CSN will stay high between transactions if END-START shortcut is used + 0x004 + read-write + 0x00000002 + 0x20 + + + CSNDUR + Minimum duration between edge of CSN and edge of SCK at the start and end of a transaction. If END-START shortcut is used, minimum duration CSN will stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns). + 0 + 7 + + + + + + CSNPOL + Polarity of CSN output + 0x568 + read-write + 0x00000000 + 0x20 + - CH2LIMITH - Write '1' to disable interrupt for CH[2].LIMITH event - 10 - 10 + CSNPOL + Polarity of CSN output + 0 + 0 - read - Disabled - Read: Disabled - 0 + LOW + Active low (idle state high) + 0x0 - Enabled - Read: Enabled - 1 + HIGH + Active high (idle state low) + 0x1 + + + + + PSELDCX + Pin select for DCX signal + 0x56C + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 - write - Clear - Disable - 1 + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + DCXCNT + DCX configuration + 0x570 + read-write + 0x00000000 + 0x20 + - CH2LIMITL - Write '1' to disable interrupt for CH[2].LIMITL event - 11 - 11 + DCXCNT + This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates that all bytes are command bytes. + 0 + 3 + + + + + ORC + Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT + 0x5C0 + read-write + 0x00000000 + 0x20 + + + ORC + Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT. + 0 + 7 + + + + + + + SPIS0 + SPI Slave 0 + 0x40003000 + SPI0 + SPIS + + 0 + 0x1000 + registers + + + SPI0_SPIM0_SPIS0_TWI0_TWIM0_TWIS0 + 3 + + SPIS + 0x20 + + + TASKS_ACQUIRE + Acquire SPI semaphore + 0x024 + write-only + 0x00000000 + 0x20 + + + TASKS_ACQUIRE + Acquire SPI semaphore + 0 + 0 - read - - Disabled - Read: Disabled - 0 - - Enabled - Read: Enabled - 1 + Trigger + Trigger task + 0x1 + + + + + TASKS_RELEASE + Release SPI semaphore, enabling the SPI slave to acquire it + 0x028 + write-only + 0x00000000 + 0x20 + + + TASKS_RELEASE + Release SPI semaphore, enabling the SPI slave to acquire it + 0 + 0 - write - Clear - Disable - 1 + Trigger + Trigger task + 0x1 + + + + EVENTS_END + Granted transaction completed + 0x104 + read-write + 0x00000000 + 0x20 + - CH3LIMITH - Write '1' to disable interrupt for CH[3].LIMITH event - 12 - 12 + EVENTS_END + Granted transaction completed + 0 + 0 - read - Disabled - Read: Disabled - 0 + NotGenerated + Event not generated + 0x0 - Enabled - Read: Enabled - 1 + Generated + Event generated + 0x1 + + + + + EVENTS_ENDRX + End of RXD buffer reached + 0x110 + read-write + 0x00000000 + 0x20 + + + EVENTS_ENDRX + End of RXD buffer reached + 0 + 0 - write - Clear - Disable - 1 + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + EVENTS_ACQUIRED + Semaphore acquired + 0x128 + read-write + 0x00000000 + 0x20 + - CH3LIMITL - Write '1' to disable interrupt for CH[3].LIMITL event - 13 - 13 + EVENTS_ACQUIRED + Semaphore acquired + 0 + 0 - read - Disabled - Read: Disabled - 0 + NotGenerated + Event not generated + 0x0 - Enabled - Read: Enabled - 1 + Generated + Event generated + 0x1 + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + END_ACQUIRE + Shortcut between event END and task ACQUIRE + 2 + 2 - write - Clear - Disable - 1 + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + - CH4LIMITH - Write '1' to disable interrupt for CH[4].LIMITH event - 14 - 14 + END + Write '1' to enable interrupt for event END + 1 + 1 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Clear - Disable - 1 + Set + Enable + 0x1 - CH4LIMITL - Write '1' to disable interrupt for CH[4].LIMITL event - 15 - 15 + ENDRX + Write '1' to enable interrupt for event ENDRX + 4 + 4 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Clear - Disable - 1 + Set + Enable + 0x1 - CH5LIMITH - Write '1' to disable interrupt for CH[5].LIMITH event - 16 - 16 + ACQUIRED + Write '1' to enable interrupt for event ACQUIRED + 10 + 10 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Clear - Disable - 1 + Set + Enable + 0x1 + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + - CH5LIMITL - Write '1' to disable interrupt for CH[5].LIMITL event - 17 - 17 + END + Write '1' to disable interrupt for event END + 1 + 1 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -20561,26 +20119,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - CH6LIMITH - Write '1' to disable interrupt for CH[6].LIMITH event - 18 - 18 + ENDRX + Write '1' to disable interrupt for event ENDRX + 4 + 4 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -20588,26 +20146,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - CH6LIMITL - Write '1' to disable interrupt for CH[6].LIMITL event - 19 - 19 + ACQUIRED + Write '1' to disable interrupt for event ACQUIRED + 10 + 10 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -20615,87 +20173,109 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 + + + + SEMSTAT + Semaphore status register + 0x400 + read-only + 0x00000001 + 0x20 + - CH7LIMITH - Write '1' to disable interrupt for CH[7].LIMITH event - 20 - 20 + SEMSTAT + Semaphore status + 0 + 1 - read - Disabled - Read: Disabled - 0 + Free + Semaphore is free + 0x0 - Enabled - Read: Enabled - 1 + CPU + Semaphore is assigned to CPU + 0x1 - - - write - Clear - Disable - 1 + SPIS + Semaphore is assigned to SPI slave + 0x2 + + + CPUPending + Semaphore is assigned to SPI but a handover to the CPU is pending + 0x3 + + + + STATUS + Status from last transaction + 0x440 + read-write + 0x00000000 + 0x20 + - CH7LIMITL - Write '1' to disable interrupt for CH[7].LIMITL event - 21 - 21 + OVERREAD + TX buffer over-read detected, and prevented + 0 + 0 read - Disabled - Read: Disabled - 0 + NotPresent + Read: error not present + 0x0 - Enabled - Read: Enabled - 1 + Present + Read: error present + 0x1 write Clear - Disable - 1 + Write: clear error on writing '1' + 0x1 - - - - STATUS - Status - 0x400 - read-only - - STATUS - Status - 0 - 0 + OVERFLOW + RX buffer overflow detected, and prevented + 1 + 1 + read - Ready - SAADC is ready. No on-going conversions. - 0 + NotPresent + Read: error not present + 0x0 - Busy - SAADC is busy. Conversion in progress. - 1 + Present + Read: error present + 0x1 + + + + write + + Clear + Write: clear error on writing '1' + 0x1 @@ -20703,552 +20283,299 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ ENABLE - Enable or disable SAADC + Enable SPI slave 0x500 read-write + 0x00000000 + 0x20 ENABLE - Enable or disable SAADC + Enable or disable SPI slave 0 - 0 + 3 Disabled - Disable SAADC - 0 + Disable SPI slave + 0x0 Enabled - Enable SAADC - 1 + Enable SPI slave + 0x2 - 8 - 0x010 - CH[%s] + PSEL Unspecified - SAADC_CH - 0x510 + SPIS_PSEL + read-write + 0x508 - PSELP - Description cluster[n]: Input positive pin selection for CH[n] + SCK + Pin select for SCK 0x000 read-write - 0x00000000 + 0xFFFFFFFF + 0x20 - PSELP - Analog positive input channel + PIN + Pin number 0 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 - NC - Not connected - 0 - - - AnalogInput0 - AIN0 - 1 - - - AnalogInput1 - AIN1 - 2 - - - AnalogInput2 - AIN2 - 3 - - - AnalogInput3 - AIN3 - 4 - - - AnalogInput4 - AIN4 - 5 - - - AnalogInput5 - AIN5 - 6 - - - AnalogInput6 - AIN6 - 7 - - - AnalogInput7 - AIN7 - 8 - - - VDD - VDD - 9 + Disconnected + Disconnect + 0x1 - VDDHDIV5 - VDDH/5 - 0x0D + Connected + Connect + 0x0 - PSELN - Description cluster[n]: Input negative pin selection for CH[n] + MISO + Pin select for MISO signal 0x004 read-write - 0x00000000 + 0xFFFFFFFF + 0x20 - PSELN - Analog negative input, enables differential channel + PIN + Pin number 0 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 - NC - Not connected - 0 - - - AnalogInput0 - AIN0 - 1 - - - AnalogInput1 - AIN1 - 2 - - - AnalogInput2 - AIN2 - 3 - - - AnalogInput3 - AIN3 - 4 - - - AnalogInput4 - AIN4 - 5 - - - AnalogInput5 - AIN5 - 6 - - - AnalogInput6 - AIN6 - 7 - - - AnalogInput7 - AIN7 - 8 - - - VDD - VDD - 9 + Disconnected + Disconnect + 0x1 - VDDHDIV5 - VDDH/5 - 0x0D + Connected + Connect + 0x0 - CONFIG - Description cluster[n]: Input configuration for CH[n] + MOSI + Pin select for MOSI signal 0x008 read-write - 0x00020000 + 0xFFFFFFFF + 0x20 - RESP - Positive channel resistor control + PIN + Pin number 0 - 1 - - - Bypass - Bypass resistor ladder - 0 - - - Pulldown - Pull-down to GND - 1 - - - Pullup - Pull-up to VDD - 2 - - - VDD1_2 - Set input at VDD/2 - 3 - - + 4 - RESN - Negative channel resistor control - 4 + PORT + Port number + 5 5 - - - Bypass - Bypass resistor ladder - 0 - - - Pulldown - Pull-down to GND - 1 - - - Pullup - Pull-up to VDD - 2 - - - VDD1_2 - Set input at VDD/2 - 3 - - - - - GAIN - Gain control - 8 - 10 - - - Gain1_6 - 1/6 - 0 - - - Gain1_5 - 1/5 - 1 - - - Gain1_4 - 1/4 - 2 - - - Gain1_3 - 1/3 - 3 - - - Gain1_2 - 1/2 - 4 - - - Gain1 - 1 - 5 - - - Gain2 - 2 - 6 - - - Gain4 - 4 - 7 - - - REFSEL - Reference control - 12 - 12 + CONNECT + Connection + 31 + 31 - Internal - Internal reference (0.6 V) - 0 + Disconnected + Disconnect + 0x1 - VDD1_4 - VDD/4 as reference - 1 + Connected + Connect + 0x0 + + + + CSN + Pin select for CSN signal + 0x00C + read-write + 0xFFFFFFFF + 0x20 + - TACQ - Acquisition time, the time the SAADC uses to sample the input voltage - 16 - 18 - - - 3us - 3 us - 0 - - - 5us - 5 us - 1 - - - 10us - 10 us - 2 - - - 15us - 15 us - 3 - - - 20us - 20 us - 4 - - - 40us - 40 us - 5 - - + PIN + Pin number + 0 + 4 - MODE - Enable differential mode - 20 - 20 - - - SE - Single-ended, PSELN will be ignored, negative input to SAADC shorted to GND - 0 - - - Diff - Differential - 1 - - + PORT + Port number + 5 + 5 - BURST - Enable burst mode - 24 - 24 + CONNECT + Connection + 31 + 31 - Disabled - Burst mode is disabled (normal operation) - 0 + Disconnected + Disconnect + 0x1 - Enabled - Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. - 1 + Connected + Connect + 0x0 + + + RXD + Unspecified + SPIS_RXD + read-write + 0x534 - LIMIT - Description cluster[n]: High/low limits for event monitoring of a channel - 0x00C + PTR + RXD data pointer + 0x000 read-write - 0x7FFF8000 + 0x00000000 + 0x20 - LOW - Low level limit + PTR + RXD data pointer 0 - 15 - - - HIGH - High level limit - 16 31 - - - RESOLUTION - Resolution configuration - 0x5F0 - read-write - 0x00000001 - - - VAL - Set the resolution - 0 - 2 - - - 8bit - 8 bits - 0 - - - 10bit - 10 bits - 1 - - - 12bit - 12 bits - 2 - - - 14bit - 14 bits - 3 - - - - - - - OVERSAMPLE - Oversampling configuration. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. - 0x5F4 - read-write - - - OVERSAMPLE - Oversample control - 0 - 3 - - - Bypass - Bypass oversampling - 0 - - - Over2x - Oversample 2x - 1 - - - Over4x - Oversample 4x - 2 - - - Over8x - Oversample 8x - 3 - - - Over16x - Oversample 16x - 4 - - - Over32x - Oversample 32x - 5 - - - Over64x - Oversample 64x - 6 - - - Over128x - Oversample 128x - 7 - - - Over256x - Oversample 256x - 8 - - - - - - - SAMPLERATE - Controls normal or continuous sample rate - 0x5F8 - read-write - - - CC - Capture and compare value. Sample rate is 16 MHz/CC - 0 - 10 - - - MODE - Select mode for sample rate control - 12 - 12 - - - Task - Rate is controlled from SAMPLE task - 0 - - - Timers - Rate is controlled from local timer (use CC to control the rate) - 1 - - - - - + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 15 + + + + + AMOUNT + Number of bytes received in last granted transaction + 0x008 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes received in the last granted transaction + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + 0x00000000 + 0x20 + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + - RESULT - RESULT EasyDMA channel - SAADC_RESULT - 0x62C + TXD + Unspecified + SPIS_TXD + read-write + 0x544 PTR - Data pointer + TXD data pointer 0x000 read-write + 0x00000000 + 0x20 PTR - Data pointer + TXD data pointer 0 31 @@ -21256,321 +20583,588 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ MAXCNT - Maximum number of 16-bit samples to be written to output RAM buffer + Maximum number of bytes in transmit buffer 0x004 read-write + 0x00000000 + 0x20 MAXCNT - Maximum number of 16-bit samples to be written to output RAM buffer + Maximum number of bytes in transmit buffer 0 - 14 + 15 AMOUNT - Number of 16-bit samples written to output RAM buffer since the previous START task + Number of bytes transmitted in last granted transaction 0x008 read-only + 0x00000000 + 0x20 AMOUNT - Number of 16-bit samples written to output RAM buffer since the previous START task. This register can be read after an END or STOPPED event. + Number of bytes transmitted in last granted transaction 0 - 14 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + 0x00000000 + 0x20 + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + CONFIG + Configuration register + 0x554 + read-write + 0x00000000 + 0x20 + + + ORDER + Bit order + 0 + 0 + + + MsbFirst + Most significant bit shifted out first + 0x0 + + + LsbFirst + Least significant bit shifted out first + 0x1 + + + + + CPHA + Serial clock (SCK) phase + 1 + 1 + + + Leading + Sample on leading edge of clock, shift serial data on trailing edge + 0x0 + + + Trailing + Sample on trailing edge of clock, shift serial data on leading edge + 0x1 + + + + + CPOL + Serial clock (SCK) polarity + 2 + 2 + + + ActiveHigh + Active high + 0x0 + + + ActiveLow + Active low + 0x1 + + + + + + + DEF + Default character. Character clocked out in case of an ignored transaction. + 0x55C + read-write + 0x00000000 + 0x20 + + + DEF + Default character. Character clocked out in case of an ignored transaction. + 0 + 7 + + + + + ORC + Over-read character + 0x5C0 + read-write + 0x00000000 + 0x20 + + + ORC + Over-read character. Character clocked out after an over-read of the transmit buffer. + 0 + 7 + + + - TIMER0 - Timer/Counter 0 - 0x40008000 - TIMER + TWI0 + I2C compatible Two-Wire Interface 0 + 0x40003000 + SPI0 + TWI 0 0x1000 registers - TIMER0 - 8 + SPI0_SPIM0_SPIS0_TWI0_TWIM0_TWIS0 + 3 - TIMER + TWI 0x20 - TASKS_START - Start Timer + TASKS_STARTRX + Start TWI receive sequence 0x000 write-only + 0x00000000 + 0x20 - TASKS_START + TASKS_STARTRX + Start TWI receive sequence 0 0 + + + Trigger + Trigger task + 0x1 + + - TASKS_STOP - Stop Timer - 0x004 + TASKS_STARTTX + Start TWI transmit sequence + 0x008 write-only + 0x00000000 + 0x20 - TASKS_STOP + TASKS_STARTTX + Start TWI transmit sequence 0 0 + + + Trigger + Trigger task + 0x1 + + - TASKS_COUNT - Increment Timer (Counter mode only) - 0x008 + TASKS_STOP + Stop TWI transaction + 0x014 write-only + 0x00000000 + 0x20 - TASKS_COUNT + TASKS_STOP + Stop TWI transaction 0 0 + + + Trigger + Trigger task + 0x1 + + - TASKS_CLEAR - Clear time - 0x00C + TASKS_SUSPEND + Suspend TWI transaction + 0x01C write-only + 0x00000000 + 0x20 - TASKS_CLEAR + TASKS_SUSPEND + Suspend TWI transaction 0 0 + + + Trigger + Trigger task + 0x1 + + - TASKS_SHUTDOWN - Deprecated register - Shut down timer - 0x010 + TASKS_RESUME + Resume TWI transaction + 0x020 write-only + 0x00000000 + 0x20 - TASKS_SHUTDOWN + TASKS_RESUME + Resume TWI transaction 0 0 + + + Trigger + Trigger task + 0x1 + + - 4 - 0x4 - TASKS_CAPTURE[%s] - Description collection[n]: Capture Timer value to CC[n] register - 0x040 - write-only + EVENTS_STOPPED + TWI stopped + 0x104 + read-write + 0x00000000 + 0x20 - TASKS_CAPTURE + EVENTS_STOPPED + TWI stopped 0 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + - 4 - 0x4 - EVENTS_COMPARE[%s] - Description collection[n]: Compare event on CC[n] match - 0x140 + EVENTS_RXDREADY + TWI RXD byte received + 0x108 read-write + 0x00000000 + 0x20 - EVENTS_COMPARE + EVENTS_RXDREADY + TWI RXD byte received 0 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + - SHORTS - Shortcut register - 0x200 + EVENTS_TXDSENT + TWI TXD byte sent + 0x11C read-write + 0x00000000 + 0x20 - COMPARE0_CLEAR - Shortcut between COMPARE[0] event and CLEAR task + EVENTS_TXDSENT + TWI TXD byte sent 0 0 - Disabled - Disable shortcut - 0 + NotGenerated + Event not generated + 0x0 - Enabled - Enable shortcut - 1 + Generated + Event generated + 0x1 + + + + EVENTS_ERROR + TWI error + 0x124 + read-write + 0x00000000 + 0x20 + - COMPARE1_CLEAR - Shortcut between COMPARE[1] event and CLEAR task - 1 - 1 + EVENTS_ERROR + TWI error + 0 + 0 - Disabled - Disable shortcut - 0 + NotGenerated + Event not generated + 0x0 - Enabled - Enable shortcut - 1 + Generated + Event generated + 0x1 + + + + EVENTS_BB + TWI byte boundary, generated before each byte that is sent or received + 0x138 + read-write + 0x00000000 + 0x20 + - COMPARE2_CLEAR - Shortcut between COMPARE[2] event and CLEAR task - 2 - 2 + EVENTS_BB + TWI byte boundary, generated before each byte that is sent or received + 0 + 0 - Disabled - Disable shortcut - 0 + NotGenerated + Event not generated + 0x0 - Enabled - Enable shortcut - 1 + Generated + Event generated + 0x1 + + + + EVENTS_SUSPENDED + TWI entered the suspended state + 0x148 + read-write + 0x00000000 + 0x20 + - COMPARE3_CLEAR - Shortcut between COMPARE[3] event and CLEAR task - 3 - 3 + EVENTS_SUSPENDED + TWI entered the suspended state + 0 + 0 - Disabled - Disable shortcut - 0 + NotGenerated + Event not generated + 0x0 - Enabled - Enable shortcut - 1 + Generated + Event generated + 0x1 + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + - COMPARE0_STOP - Shortcut between COMPARE[0] event and STOP task - 8 - 8 + BB_SUSPEND + Shortcut between event BB and task SUSPEND + 0 + 0 Disabled Disable shortcut - 0 + 0x0 Enabled Enable shortcut - 1 + 0x1 - COMPARE1_STOP - Shortcut between COMPARE[1] event and STOP task - 9 - 9 + BB_STOP + Shortcut between event BB and task STOP + 1 + 1 Disabled Disable shortcut - 0 + 0x0 Enabled Enable shortcut - 1 + 0x1 + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + - COMPARE2_STOP - Shortcut between COMPARE[2] event and STOP task - 10 - 10 + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + read Disabled - Disable shortcut - 0 + Read: Disabled + 0x0 Enabled - Enable shortcut - 1 + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 - COMPARE3_STOP - Shortcut between COMPARE[3] event and STOP task - 11 - 11 + RXDREADY + Write '1' to enable interrupt for event RXDREADY + 2 + 2 + read Disabled - Disable shortcut - 0 + Read: Disabled + 0x0 Enabled - Enable shortcut - 1 + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 - - - - INTENSET - Enable interrupt - 0x304 - read-write - - COMPARE0 - Write '1' to enable interrupt for COMPARE[0] event - 16 - 16 + TXDSENT + Write '1' to enable interrupt for event TXDSENT + 7 + 7 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -21578,26 +21172,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - COMPARE1 - Write '1' to enable interrupt for COMPARE[1] event - 17 - 17 + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -21605,26 +21199,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - COMPARE2 - Write '1' to enable interrupt for COMPARE[2] event - 18 - 18 + BB + Write '1' to enable interrupt for event BB + 14 + 14 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -21632,26 +21226,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - COMPARE3 - Write '1' to enable interrupt for COMPARE[3] event - 19 - 19 + SUSPENDED + Write '1' to enable interrupt for event SUSPENDED + 18 + 18 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -21659,7 +21253,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 @@ -21670,23 +21264,25 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disable interrupt 0x308 read-write + 0x00000000 + 0x20 - COMPARE0 - Write '1' to disable interrupt for COMPARE[0] event - 16 - 16 + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -21694,26 +21290,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - COMPARE1 - Write '1' to disable interrupt for COMPARE[1] event - 17 - 17 + RXDREADY + Write '1' to disable interrupt for event RXDREADY + 2 + 2 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -21721,26 +21317,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - COMPARE2 - Write '1' to disable interrupt for COMPARE[2] event - 18 - 18 + TXDSENT + Write '1' to disable interrupt for event TXDSENT + 7 + 7 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -21748,26 +21344,80 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - COMPARE3 - Write '1' to disable interrupt for COMPARE[3] event - 19 - 19 + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + BB + Write '1' to disable interrupt for event BB + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SUSPENDED + Write '1' to disable interrupt for event SUSPENDED + 18 + 18 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -21775,718 +21425,886 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - MODE - Timer mode selection - 0x504 + ERRORSRC + Error source + 0x4C4 read-write + 0x00000000 + oneToClear + 0x20 - MODE - Timer mode + OVERRUN + Overrun error 0 + 0 + + read + + NotPresent + Read: no overrun occured + 0x0 + + + Present + Read: overrun occured + 0x1 + + + + + ANACK + NACK received after sending the address (write '1' to clear) + 1 1 + read - Timer - Select Timer mode - 0 + NotPresent + Read: error not present + 0x0 - Counter - Deprecated enumerator - Select Counter mode - 1 + Present + Read: error present + 0x1 + + + + + DNACK + NACK received after sending a data byte (write '1' to clear) + 2 + 2 + + read + + NotPresent + Read: error not present + 0x0 - LowPowerCounter - Select Low Power Counter mode - 2 + Present + Read: error present + 0x1 - BITMODE - Configure the number of bits used by the TIMER - 0x508 + ENABLE + Enable TWI + 0x500 read-write + 0x00000000 + 0x20 - BITMODE - Timer bit width + ENABLE + Enable or disable TWI 0 - 1 + 3 - 16Bit - 16 bit timer bit width - 0 - - - 08Bit - 8 bit timer bit width - 1 - - - 24Bit - 24 bit timer bit width - 2 + Disabled + Disable TWI + 0x0 - 32Bit - 32 bit timer bit width - 3 + Enabled + Enable TWI + 0x5 + + PSEL + Unspecified + TWI_PSEL + read-write + 0x508 + + SCL + Pin select for SCL + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + SDA + Pin select for SDA + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + RXD + RXD register. Register is cleared on read and the buffer pointer will be modified if read. + 0x518 + read-only + 0x00000000 + modifyExternal + 0x20 + + + RXD + RXD register + 0 + 7 + + + - PRESCALER - Timer prescaler register - 0x510 + TXD + TXD register + 0x51C read-write - 0x00000004 + 0x00000000 + 0x20 - PRESCALER - Prescaler value + TXD + TXD register 0 - 3 + 7 - 4 - 0x4 - CC[%s] - Description collection[n]: Capture/Compare register n - 0x540 + FREQUENCY + TWI frequency. Accuracy depends on the HFCLK source selected. + 0x524 read-write + 0x04000000 + 0x20 - CC - Capture/Compare value + FREQUENCY + TWI master clock frequency 0 31 + + + K100 + 100 kbps + 0x01980000 + + + K250 + 250 kbps + 0x04000000 + + + K400 + 400 kbps (actual rate 410.256 kbps) + 0x06680000 + + + + + + + ADDRESS + Address used in the TWI transfer + 0x588 + read-write + 0x00000000 + 0x20 + + + ADDRESS + Address used in the TWI transfer + 0 + 6 - - TIMER1 - Timer/Counter 1 - 0x40009000 - - TIMER1 - 9 - - - - TIMER2 - Timer/Counter 2 - 0x4000A000 - - TIMER2 - 10 - - - RTC0 - Real time counter 0 - 0x4000B000 - RTC + TWIM0 + I2C compatible Two-Wire Master Interface with EasyDMA 0 + 0x40003000 + SPI0 + TWIM 0 0x1000 registers - RTC0 - 11 + SPI0_SPIM0_SPIS0_TWI0_TWIM0_TWIS0 + 3 - RTC + TWIM 0x20 - TASKS_START - Start RTC COUNTER + TASKS_STARTRX + Start TWI receive sequence 0x000 write-only + 0x00000000 + 0x20 - TASKS_START + TASKS_STARTRX + Start TWI receive sequence 0 0 + + + Trigger + Trigger task + 0x1 + + - TASKS_STOP - Stop RTC COUNTER - 0x004 + TASKS_STARTTX + Start TWI transmit sequence + 0x008 write-only + 0x00000000 + 0x20 - TASKS_STOP + TASKS_STARTTX + Start TWI transmit sequence 0 0 + + + Trigger + Trigger task + 0x1 + + - TASKS_CLEAR - Clear RTC COUNTER - 0x008 + TASKS_STOP + Stop TWI transaction. Must be issued while the TWI master is not suspended. + 0x014 write-only + 0x00000000 + 0x20 - TASKS_CLEAR + TASKS_STOP + Stop TWI transaction. Must be issued while the TWI master is not suspended. 0 0 + + + Trigger + Trigger task + 0x1 + + - TASKS_TRIGOVRFLW - Set COUNTER to 0xFFFFF0 - 0x00C + TASKS_SUSPEND + Suspend TWI transaction + 0x01C write-only + 0x00000000 + 0x20 - TASKS_TRIGOVRFLW + TASKS_SUSPEND + Suspend TWI transaction 0 0 + + + Trigger + Trigger task + 0x1 + + - EVENTS_TICK - Event on COUNTER increment - 0x100 - read-write + TASKS_RESUME + Resume TWI transaction + 0x020 + write-only + 0x00000000 + 0x20 - EVENTS_TICK + TASKS_RESUME + Resume TWI transaction 0 0 + + + Trigger + Trigger task + 0x1 + + - EVENTS_OVRFLW - Event on COUNTER overflow + EVENTS_STOPPED + TWI stopped 0x104 read-write + 0x00000000 + 0x20 - EVENTS_OVRFLW + EVENTS_STOPPED + TWI stopped 0 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + - 4 - 0x4 - EVENTS_COMPARE[%s] - Description collection[n]: Compare event on CC[n] match - 0x140 + EVENTS_ERROR + TWI error + 0x124 read-write + 0x00000000 + 0x20 - EVENTS_COMPARE + EVENTS_ERROR + TWI error 0 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + - INTENSET - Enable interrupt - 0x304 + EVENTS_SUSPENDED + SUSPEND task has been issued, TWI traffic is now suspended. + 0x148 read-write + 0x00000000 + 0x20 - TICK - Write '1' to enable interrupt for TICK event + EVENTS_SUSPENDED + SUSPEND task has been issued, TWI traffic is now suspended. 0 0 - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - OVRFLW - Write '1' to enable interrupt for OVRFLW event - 1 - 1 - - read - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 + NotGenerated + Event not generated + 0x0 - - - write - Set - Enable - 1 + Generated + Event generated + 0x1 + + + + EVENTS_RXSTARTED + Receive sequence started + 0x14C + read-write + 0x00000000 + 0x20 + - COMPARE0 - Write '1' to enable interrupt for COMPARE[0] event - 16 - 16 + EVENTS_RXSTARTED + Receive sequence started + 0 + 0 - read - - Disabled - Read: Disabled - 0 - - Enabled - Read: Enabled - 1 + NotGenerated + Event not generated + 0x0 - - - write - Set - Enable - 1 + Generated + Event generated + 0x1 + + + + EVENTS_TXSTARTED + Transmit sequence started + 0x150 + read-write + 0x00000000 + 0x20 + - COMPARE1 - Write '1' to enable interrupt for COMPARE[1] event - 17 - 17 + EVENTS_TXSTARTED + Transmit sequence started + 0 + 0 - read - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 + NotGenerated + Event not generated + 0x0 - - - write - Set - Enable - 1 + Generated + Event generated + 0x1 + + + + EVENTS_LASTRX + Byte boundary, starting to receive the last byte + 0x15C + read-write + 0x00000000 + 0x20 + - COMPARE2 - Write '1' to enable interrupt for COMPARE[2] event - 18 - 18 + EVENTS_LASTRX + Byte boundary, starting to receive the last byte + 0 + 0 - read - - Disabled - Read: Disabled - 0 - - Enabled - Read: Enabled - 1 + NotGenerated + Event not generated + 0x0 - - - write - Set - Enable - 1 + Generated + Event generated + 0x1 + + + + EVENTS_LASTTX + Byte boundary, starting to transmit the last byte + 0x160 + read-write + 0x00000000 + 0x20 + - COMPARE3 - Write '1' to enable interrupt for COMPARE[3] event - 19 - 19 + EVENTS_LASTTX + Byte boundary, starting to transmit the last byte + 0 + 0 - read - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 + NotGenerated + Event not generated + 0x0 - - - write - Set - Enable - 1 + Generated + Event generated + 0x1 - INTENCLR - Disable interrupt - 0x308 + SHORTS + Shortcuts between local events and tasks + 0x200 read-write + 0x00000000 + 0x20 - TICK - Write '1' to disable interrupt for TICK event - 0 - 0 + LASTTX_STARTRX + Shortcut between event LASTTX and task STARTRX + 7 + 7 - read Disabled - Read: Disabled - 0 + Disable shortcut + 0x0 Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 + Enable shortcut + 0x1 - OVRFLW - Write '1' to disable interrupt for OVRFLW event - 1 - 1 + LASTTX_SUSPEND + Shortcut between event LASTTX and task SUSPEND + 8 + 8 - read Disabled - Read: Disabled - 0 + Disable shortcut + 0x0 Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 + Enable shortcut + 0x1 - COMPARE0 - Write '1' to disable interrupt for COMPARE[0] event - 16 - 16 + LASTTX_STOP + Shortcut between event LASTTX and task STOP + 9 + 9 - read Disabled - Read: Disabled - 0 + Disable shortcut + 0x0 Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 + Enable shortcut + 0x1 - COMPARE1 - Write '1' to disable interrupt for COMPARE[1] event - 17 - 17 + LASTRX_STARTTX + Shortcut between event LASTRX and task STARTTX + 10 + 10 - read Disabled - Read: Disabled - 0 + Disable shortcut + 0x0 Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 + Enable shortcut + 0x1 - COMPARE2 - Write '1' to disable interrupt for COMPARE[2] event - 18 - 18 + LASTRX_SUSPEND + Shortcut between event LASTRX and task SUSPEND + 11 + 11 - read Disabled - Read: Disabled - 0 + Disable shortcut + 0x0 Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 + Enable shortcut + 0x1 - COMPARE3 - Write '1' to disable interrupt for COMPARE[3] event - 19 - 19 + LASTRX_STOP + Shortcut between event LASTRX and task STOP + 12 + 12 - read Disabled - Read: Disabled - 0 + Disable shortcut + 0x0 Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 + Enable shortcut + 0x1 - EVTEN - Enable or disable event routing - 0x340 + INTEN + Enable or disable interrupt + 0x300 read-write + 0x00000000 + 0x20 - TICK - Enable or disable event routing for TICK event - 0 - 0 + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 - OVRFLW - Enable or disable event routing for OVRFLW event - 1 - 1 + ERROR + Enable or disable interrupt for event ERROR + 9 + 9 Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 - COMPARE0 - Enable or disable event routing for COMPARE[0] event - 16 - 16 + SUSPENDED + Enable or disable interrupt for event SUSPENDED + 18 + 18 Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 - COMPARE1 - Enable or disable event routing for COMPARE[1] event - 17 - 17 + RXSTARTED + Enable or disable interrupt for event RXSTARTED + 19 + 19 Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 - COMPARE2 - Enable or disable event routing for COMPARE[2] event - 18 - 18 + TXSTARTED + Enable or disable interrupt for event TXSTARTED + 20 + 20 Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 - COMPARE3 - Enable or disable event routing for COMPARE[3] event - 19 - 19 + LASTRX + Enable or disable interrupt for event LASTRX + 23 + 23 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + LASTTX + Enable or disable interrupt for event LASTTX + 24 + 24 Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 - EVTENSET - Enable event routing - 0x344 + INTENSET + Enable interrupt + 0x304 read-write + 0x00000000 + 0x20 - TICK - Write '1' to enable event routing for TICK event - 0 - 0 + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -22494,26 +22312,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - OVRFLW - Write '1' to enable event routing for OVRFLW event - 1 - 1 + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -22521,26 +22339,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - COMPARE0 - Write '1' to enable event routing for COMPARE[0] event - 16 - 16 + SUSPENDED + Write '1' to enable interrupt for event SUSPENDED + 18 + 18 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -22548,26 +22366,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - COMPARE1 - Write '1' to enable event routing for COMPARE[1] event - 17 - 17 + RXSTARTED + Write '1' to enable interrupt for event RXSTARTED + 19 + 19 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -22575,26 +22393,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - COMPARE2 - Write '1' to enable event routing for COMPARE[2] event - 18 - 18 + TXSTARTED + Write '1' to enable interrupt for event TXSTARTED + 20 + 20 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -22602,26 +22420,53 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - COMPARE3 - Write '1' to enable event routing for COMPARE[3] event - 19 - 19 + LASTRX + Write '1' to enable interrupt for event LASTRX + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + LASTTX + Write '1' to enable interrupt for event LASTTX + 24 + 24 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -22629,34 +22474,36 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - EVTENCLR - Disable event routing - 0x348 + INTENCLR + Disable interrupt + 0x308 read-write + 0x00000000 + 0x20 - TICK - Write '1' to disable event routing for TICK event - 0 - 0 + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -22664,26 +22511,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - OVRFLW - Write '1' to disable event routing for OVRFLW event - 1 - 1 + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -22691,26 +22538,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - COMPARE0 - Write '1' to disable event routing for COMPARE[0] event - 16 - 16 + SUSPENDED + Write '1' to disable interrupt for event SUSPENDED + 18 + 18 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -22718,26 +22565,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - COMPARE1 - Write '1' to disable event routing for COMPARE[1] event - 17 - 17 + RXSTARTED + Write '1' to disable interrupt for event RXSTARTED + 19 + 19 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -22745,26 +22592,53 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - COMPARE2 - Write '1' to disable event routing for COMPARE[2] event - 18 - 18 + TXSTARTED + Write '1' to disable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + LASTRX + Write '1' to disable interrupt for event LASTRX + 23 + 23 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -22772,26 +22646,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - COMPARE3 - Write '1' to disable event routing for COMPARE[3] event - 19 - 19 + LASTTX + Write '1' to disable interrupt for event LASTTX + 24 + 24 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -22799,713 +22673,871 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - COUNTER - Current COUNTER value - 0x504 - read-only + ERRORSRC + Error source + 0x4C4 + read-write + 0x00000000 + oneToClear + 0x20 - COUNTER - Counter value + OVERRUN + Overrun error 0 - 23 + 0 + + + NotReceived + Error did not occur + 0x0 + + + Received + Error occurred + 0x1 + + + + + ANACK + NACK received after sending the address (write '1' to clear) + 1 + 1 + + + NotReceived + Error did not occur + 0x0 + + + Received + Error occurred + 0x1 + + + + + DNACK + NACK received after sending a data byte (write '1' to clear) + 2 + 2 + + + NotReceived + Error did not occur + 0x0 + + + Received + Error occurred + 0x1 + + - PRESCALER - 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped + ENABLE + Enable TWIM + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable TWIM + 0 + 3 + + + Disabled + Disable TWIM + 0x0 + + + Enabled + Enable TWIM + 0x6 + + + + + + + PSEL + Unspecified + TWIM_PSEL + read-write 0x508 + + SCL + Pin select for SCL signal + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + SDA + Pin select for SDA signal + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + FREQUENCY + TWI frequency. Accuracy depends on the HFCLK source selected. + 0x524 read-write + 0x04000000 + 0x20 - PRESCALER - Prescaler value + FREQUENCY + TWI master clock frequency 0 - 11 + 31 + + + K100 + 100 kbps + 0x01980000 + + + K250 + 250 kbps + 0x04000000 + + + K400 + 400 kbps + 0x06400000 + + + + RXD + RXD EasyDMA channel + TWIM_RXD + read-write + 0x534 + + PTR + Data pointer + 0x000 + read-write + 0x00000000 + 0x20 + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + 0x00000000 + 0x20 + + + LIST + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + + TXD + TXD EasyDMA channel + TWIM_TXD + read-write + 0x544 + + PTR + Data pointer + 0x000 + read-write + 0x00000000 + 0x20 + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + 0x00000000 + 0x20 + + + LIST + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + - 4 - 0x4 - CC[%s] - Description collection[n]: Compare register n - 0x540 + ADDRESS + Address used in the TWI transfer + 0x588 read-write + 0x00000000 + 0x20 - COMPARE - Compare value + ADDRESS + Address used in the TWI transfer 0 - 23 + 6 - TEMP - Temperature Sensor - 0x4000C000 + TWIS0 + I2C compatible Two-Wire Slave Interface with EasyDMA 0 + 0x40003000 + SPI0 + TWIS 0 0x1000 registers - TEMP - 12 + SPI0_SPIM0_SPIS0_TWI0_TWIM0_TWIS0 + 3 - TEMP + TWIS 0x20 - TASKS_START - Start temperature measurement - 0x000 + TASKS_STOP + Stop TWI transaction + 0x014 write-only + 0x00000000 + 0x20 - TASKS_START + TASKS_STOP + Stop TWI transaction 0 0 + + + Trigger + Trigger task + 0x1 + + - TASKS_STOP - Stop temperature measurement - 0x004 + TASKS_SUSPEND + Suspend TWI transaction + 0x01C write-only + 0x00000000 + 0x20 - TASKS_STOP + TASKS_SUSPEND + Suspend TWI transaction 0 0 + + + Trigger + Trigger task + 0x1 + + - EVENTS_DATARDY - Temperature measurement complete, data ready - 0x100 - read-write + TASKS_RESUME + Resume TWI transaction + 0x020 + write-only + 0x00000000 + 0x20 - EVENTS_DATARDY + TASKS_RESUME + Resume TWI transaction 0 0 + + + Trigger + Trigger task + 0x1 + + - INTENSET - Enable interrupt - 0x304 - read-write + TASKS_PREPARERX + Prepare the TWI slave to respond to a write command + 0x030 + write-only + 0x00000000 + 0x20 - DATARDY - Write '1' to enable interrupt for DATARDY event + TASKS_PREPARERX + Prepare the TWI slave to respond to a write command 0 0 - read - - Disabled - Read: Disabled - 0 - - Enabled - Read: Enabled - 1 + Trigger + Trigger task + 0x1 + + + + + TASKS_PREPARETX + Prepare the TWI slave to respond to a read command + 0x034 + write-only + 0x00000000 + 0x20 + + + TASKS_PREPARETX + Prepare the TWI slave to respond to a read command + 0 + 0 - write - Set - Enable - 1 + Trigger + Trigger task + 0x1 - INTENCLR - Disable interrupt - 0x308 + EVENTS_STOPPED + TWI stopped + 0x104 read-write + 0x00000000 + 0x20 - DATARDY - Write '1' to disable interrupt for DATARDY event + EVENTS_STOPPED + TWI stopped 0 0 - read - - Disabled - Read: Disabled - 0 - - Enabled - Read: Enabled - 1 + NotGenerated + Event not generated + 0x0 - - - write - Clear - Disable - 1 + Generated + Event generated + 0x1 - TEMP - Temperature in degC (0.25deg steps) - 0x508 - read-only - int32_t + EVENTS_ERROR + TWI error + 0x124 + read-write + 0x00000000 + 0x20 - TEMP - Temperature in degC (0.25deg steps) + EVENTS_ERROR + TWI error 0 - 31 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + - A0 - Slope of 1st piece wise linear function - 0x520 + EVENTS_RXSTARTED + Receive sequence started + 0x14C read-write - 0x00000326 + 0x00000000 + 0x20 - A0 - Slope of 1st piece wise linear function + EVENTS_RXSTARTED + Receive sequence started 0 - 11 - - - - - A1 - Slope of 2nd piece wise linear function - 0x524 - read-write - 0x00000348 - - - A1 - Slope of 2nd piece wise linear function - 0 - 11 - - - - - A2 - Slope of 3rd piece wise linear function - 0x528 - read-write - 0x000003AA - - - A2 - Slope of 3rd piece wise linear function - 0 - 11 - - - - - A3 - Slope of 4th piece wise linear function - 0x52C - read-write - 0x0000040E - - - A3 - Slope of 4th piece wise linear function - 0 - 11 - - - - - A4 - Slope of 5th piece wise linear function - 0x530 - read-write - 0x000004BD - - - A4 - Slope of 5th piece wise linear function - 0 - 11 - - - - - A5 - Slope of 6th piece wise linear function - 0x534 - read-write - 0x000005A3 - - - A5 - Slope of 6th piece wise linear function - 0 - 11 - - - - - B0 - y-intercept of 1st piece wise linear function - 0x540 - read-write - 0x00003FEF - - - B0 - y-intercept of 1st piece wise linear function - 0 - 13 - - - - - B1 - y-intercept of 2nd piece wise linear function - 0x544 - read-write - 0x00003FBE - - - B1 - y-intercept of 2nd piece wise linear function - 0 - 13 - - - - - B2 - y-intercept of 3rd piece wise linear function - 0x548 - read-write - 0x00003FBE - - - B2 - y-intercept of 3rd piece wise linear function - 0 - 13 - - - - - B3 - y-intercept of 4th piece wise linear function - 0x54C - read-write - 0x00000012 - - - B3 - y-intercept of 4th piece wise linear function - 0 - 13 - - - - - B4 - y-intercept of 5th piece wise linear function - 0x550 - read-write - 0x00000124 - - - B4 - y-intercept of 5th piece wise linear function - 0 - 13 - - - - - B5 - y-intercept of 6th piece wise linear function - 0x554 - read-write - 0x0000027C - - - B5 - y-intercept of 6th piece wise linear function - 0 - 13 - - - - - T0 - End point of 1st piece wise linear function - 0x560 - read-write - 0x000000E2 - - - T0 - End point of 1st piece wise linear function - 0 - 7 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + - T1 - End point of 2nd piece wise linear function - 0x564 + EVENTS_TXSTARTED + Transmit sequence started + 0x150 read-write 0x00000000 + 0x20 - T1 - End point of 2nd piece wise linear function - 0 - 7 - - - - - T2 - End point of 3rd piece wise linear function - 0x568 - read-write - 0x00000019 - - - T2 - End point of 3rd piece wise linear function - 0 - 7 - - - - - T3 - End point of 4th piece wise linear function - 0x56C - read-write - 0x0000003C - - - T3 - End point of 4th piece wise linear function - 0 - 7 - - - - - T4 - End point of 5th piece wise linear function - 0x570 - read-write - 0x00000050 - - - T4 - End point of 5th piece wise linear function - 0 - 7 - - - - - - - RNG - Random Number Generator - 0x4000D000 - - 0 - 0x1000 - registers - - - RNG - 13 - - RNG - 0x20 - - - TASKS_START - Task starting the random number generator - 0x000 - write-only - - - TASKS_START + EVENTS_TXSTARTED + Transmit sequence started 0 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + - TASKS_STOP - Task stopping the random number generator - 0x004 - write-only + EVENTS_WRITE + Write command received + 0x164 + read-write + 0x00000000 + 0x20 - TASKS_STOP + EVENTS_WRITE + Write command received 0 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + - EVENTS_VALRDY - Event being generated for every new random number written to the VALUE register - 0x100 + EVENTS_READ + Read command received + 0x168 read-write + 0x00000000 + 0x20 - EVENTS_VALRDY + EVENTS_READ + Read command received 0 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + SHORTS - Shortcut register + Shortcuts between local events and tasks 0x200 read-write + 0x00000000 + 0x20 - VALRDY_STOP - Shortcut between VALRDY event and STOP task - 0 - 0 + WRITE_SUSPEND + Shortcut between event WRITE and task SUSPEND + 13 + 13 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + READ_SUSPEND + Shortcut between event READ and task SUSPEND + 14 + 14 Disabled Disable shortcut - 0 + 0x0 Enabled Enable shortcut - 1 + 0x1 - INTENSET - Enable interrupt - 0x304 + INTEN + Enable or disable interrupt + 0x300 read-write + 0x00000000 + 0x20 - VALRDY - Write '1' to enable interrupt for VALRDY event - 0 - 0 + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 - read Disabled - Read: Disabled - 0 + Disable + 0x0 Enabled - Read: Enabled - 1 + Enable + 0x1 + + + ERROR + Enable or disable interrupt for event ERROR + 9 + 9 - write - Set + Disabled + Disable + 0x0 + + + Enabled Enable - 1 + 0x1 - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - VALRDY - Write '1' to disable interrupt for VALRDY event - 0 - 0 + RXSTARTED + Enable or disable interrupt for event RXSTARTED + 19 + 19 - read Disabled - Read: Disabled - 0 + Disable + 0x0 Enabled - Read: Enabled - 1 + Enable + 0x1 + + + TXSTARTED + Enable or disable interrupt for event TXSTARTED + 20 + 20 - write - Clear + Disabled Disable - 1 + 0x0 + + + Enabled + Enable + 0x1 - - - - CONFIG - Configuration register - 0x504 - read-write - - DERCEN - Bias correction - 0 - 0 + WRITE + Enable or disable interrupt for event WRITE + 25 + 25 Disabled - Disabled - 0 + Disable + 0x0 Enabled - Enabled - 1 + Enable + 0x1 - - - - VALUE - Output random number - 0x508 - read-only - - - VALUE - Generated random number - 0 - 7 - - - - - - - ECB - AES ECB Mode Encryption - 0x4000E000 - - 0 - 0x1000 - registers - - - ECB - 14 - - ECB - 0x20 - - - TASKS_STARTECB - Start ECB block encrypt - 0x000 - write-only - - - TASKS_STARTECB - 0 - 0 - - - - - TASKS_STOPECB - Abort a possible executing ECB operation - 0x004 - write-only - - - TASKS_STOPECB - 0 - 0 - - - - - EVENTS_ENDECB - ECB block encrypt complete - 0x100 - read-write - - - EVENTS_ENDECB - 0 - 0 - - - - - EVENTS_ERRORECB - ECB block encrypt aborted because of a STOPECB task or due to an error - 0x104 - read-write - - EVENTS_ERRORECB - 0 - 0 + READ + Enable or disable interrupt for event READ + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + @@ -23514,23 +23546,25 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Enable interrupt 0x304 read-write + 0x00000000 + 0x20 - ENDECB - Write '1' to enable interrupt for ENDECB event - 0 - 0 + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -23538,26 +23572,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - ERRORECB - Write '1' to enable interrupt for ERRORECB event - 1 - 1 + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -23565,193 +23599,53 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - ENDECB - Write '1' to disable interrupt for ENDECB event - 0 - 0 + RXSTARTED + Write '1' to enable interrupt for event RXSTARTED + 19 + 19 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Clear - Disable - 1 - - - - - ERRORECB - Write '1' to disable interrupt for ERRORECB event - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 + Set + Enable + 0x1 - - - - ECBDATAPTR - ECB block encrypt memory pointers - 0x504 - read-write - - - ECBDATAPTR - Pointer to the ECB data structure (see Table 1 ECB data structure overview) - 0 - 31 - - - - - - - AAR - Accelerated Address Resolver - 0x4000F000 - - 0 - 0x1000 - registers - - - CCM_AAR - 15 - - AAR - 0x20 - - - TASKS_START - Start resolving addresses based on IRKs specified in the IRK data structure - 0x000 - write-only - - - TASKS_START - 0 - 0 - - - - - TASKS_STOP - Stop resolving addresses - 0x008 - write-only - - - TASKS_STOP - 0 - 0 - - - - - EVENTS_END - Address resolution procedure complete - 0x100 - read-write - - - EVENTS_END - 0 - 0 - - - - - EVENTS_RESOLVED - Address resolved - 0x104 - read-write - - - EVENTS_RESOLVED - 0 - 0 - - - - - EVENTS_NOTRESOLVED - Address not resolved - 0x108 - read-write - - - EVENTS_NOTRESOLVED - 0 - 0 - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - END - Write '1' to enable interrupt for END event - 0 - 0 + TXSTARTED + Write '1' to enable interrupt for event TXSTARTED + 20 + 20 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -23759,26 +23653,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - RESOLVED - Write '1' to enable interrupt for RESOLVED event - 1 - 1 + WRITE + Write '1' to enable interrupt for event WRITE + 25 + 25 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -23786,26 +23680,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - NOTRESOLVED - Write '1' to enable interrupt for NOTRESOLVED event - 2 - 2 + READ + Write '1' to enable interrupt for event READ + 26 + 26 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -23813,7 +23707,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 @@ -23824,23 +23718,25 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disable interrupt 0x308 read-write + 0x00000000 + 0x20 - END - Write '1' to disable interrupt for END event - 0 - 0 + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -23848,26 +23744,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - RESOLVED - Write '1' to disable interrupt for RESOLVED event - 1 - 1 + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -23875,26 +23771,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - NOTRESOLVED - Write '1' to disable interrupt for NOTRESOLVED event - 2 - 2 + RXSTARTED + Write '1' to disable interrupt for event RXSTARTED + 19 + 19 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -23902,1499 +23798,1750 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 - - - - - - - STATUS - Resolution status - 0x400 - read-only - - - STATUS - The IRK that was used last time an address was resolved - 0 - 3 - - - - - ENABLE - Enable AAR - 0x500 - read-write - - - ENABLE - Enable or disable AAR - 0 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 3 - - - - - - - NIRK - Number of IRKs - 0x504 - read-write - 0x00000001 - - - NIRK - Number of Identity root keys available in the IRK data structure - 0 - 4 - - - - - IRKPTR - Pointer to IRK data structure - 0x508 - read-write - - - IRKPTR - Pointer to the IRK data structure - 0 - 31 - - - - - ADDRPTR - Pointer to the resolvable address - 0x510 - read-write - - - ADDRPTR - Pointer to the resolvable address (6-bytes) - 0 - 31 - - - - - SCRATCHPTR - Pointer to data area used for temporary storage - 0x514 - read-write - - - SCRATCHPTR - Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved. - 0 - 31 - - - - - - - CCM - AES CCM Mode Encryption - 0x4000F000 - AAR - - 0 - 0x1000 - registers - - - CCM_AAR - 15 - - CCM - 0x20 - - - TASKS_KSGEN - Start generation of key-stream. This operation will stop by itself when completed. - 0x000 - write-only - - - TASKS_KSGEN - 0 - 0 - - - - - TASKS_CRYPT - Start encryption/decryption. This operation will stop by itself when completed. - 0x004 - write-only - - - TASKS_CRYPT - 0 - 0 - - - - - TASKS_STOP - Stop encryption/decryption - 0x008 - write-only - - - TASKS_STOP - 0 - 0 - - - - - TASKS_RATEOVERRIDE - Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption - 0x00C - write-only - - - TASKS_RATEOVERRIDE - 0 - 0 - - - - - EVENTS_ENDKSGEN - Key-stream generation complete - 0x100 - read-write - - - EVENTS_ENDKSGEN - 0 - 0 - - - - - EVENTS_ENDCRYPT - Encrypt/decrypt complete - 0x104 - read-write - - - EVENTS_ENDCRYPT - 0 - 0 - - - - - EVENTS_ERROR - Deprecated register - CCM error event - 0x108 - read-write - - - EVENTS_ERROR - 0 - 0 - - - - - SHORTS - Shortcut register - 0x200 - read-write - - - ENDKSGEN_CRYPT - Shortcut between ENDKSGEN event and CRYPT task - 0 - 0 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 + 0x1 - - - - INTENSET - Enable interrupt - 0x304 - read-write - - ENDKSGEN - Write '1' to enable interrupt for ENDKSGEN event - 0 - 0 + TXSTARTED + Write '1' to disable interrupt for event TXSTARTED + 20 + 20 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Set - Enable - 1 + Clear + Disable + 0x1 - ENDCRYPT - Write '1' to enable interrupt for ENDCRYPT event - 1 - 1 + WRITE + Write '1' to disable interrupt for event WRITE + 25 + 25 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Set - Enable - 1 + Clear + Disable + 0x1 - ERROR - Write '1' to enable interrupt for ERROR event - 2 - 2 + READ + Write '1' to disable interrupt for event READ + 26 + 26 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Set - Enable - 1 + Clear + Disable + 0x1 - INTENCLR - Disable interrupt - 0x308 + ERRORSRC + Error source + 0x4D0 read-write + 0x00000000 + oneToClear + 0x20 - ENDKSGEN - Write '1' to disable interrupt for ENDKSGEN event + OVERFLOW + RX buffer overflow detected, and prevented 0 0 - read - - Disabled - Read: Disabled - 0 - - Enabled - Read: Enabled - 1 + NotDetected + Error did not occur + 0x0 - - - write - Clear - Disable - 1 + Detected + Error occurred + 0x1 - ENDCRYPT - Write '1' to disable interrupt for ENDCRYPT event - 1 - 1 + DNACK + NACK sent after receiving a data byte + 2 + 2 - read - - Disabled - Read: Disabled - 0 - - Enabled - Read: Enabled - 1 + NotReceived + Error did not occur + 0x0 - - - write - Clear - Disable - 1 + Received + Error occurred + 0x1 - ERROR - Write '1' to disable interrupt for ERROR event - 2 - 2 + OVERREAD + TX buffer over-read detected, and prevented + 3 + 3 - read - - Disabled - Read: Disabled - 0 - - Enabled - Read: Enabled - 1 + NotDetected + Error did not occur + 0x0 - - - write - Clear - Disable - 1 + Detected + Error occurred + 0x1 - MICSTATUS - MIC check result - 0x400 + MATCH + Status register indicating which address had a match + 0x4D4 read-only + 0x00000000 + 0x20 - MICSTATUS - The result of the MIC check performed during the previous decryption operation + MATCH + Indication of which address in ADDRESS that matched the incoming address 0 0 - - - CheckFailed - MIC check failed - 0 - - - CheckPassed - MIC check passed - 1 - - ENABLE - Enable + Enable TWIS 0x500 read-write + 0x00000000 + 0x20 ENABLE - Enable or disable CCM + Enable or disable TWIS 0 - 1 + 3 Disabled - Disable - 0 + Disable TWIS + 0x0 Enabled - Enable - 2 + Enable TWIS + 0x9 + + PSEL + Unspecified + TWIS_PSEL + read-write + 0x508 + + SCL + Pin select for SCL signal + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + SDA + Pin select for SDA signal + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + RXD + RXD EasyDMA channel + TWIS_RXD + read-write + 0x534 + + PTR + RXD Data pointer + 0x000 + read-write + 0x00000000 + 0x20 + + + PTR + RXD Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in RXD buffer + 0x004 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in RXD buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last RXD transaction + 0x008 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last RXD transaction + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + 0x00000000 + 0x20 + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + + TXD + TXD EasyDMA channel + TWIS_TXD + read-write + 0x544 + + PTR + TXD Data pointer + 0x000 + read-write + 0x00000000 + 0x20 + + + PTR + TXD Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in TXD buffer + 0x004 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in TXD buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last TXD transaction + 0x008 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last TXD transaction + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + 0x00000000 + 0x20 + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + + 0x2 + 0x4 + ADDRESS[%s] + Description collection: TWI slave address n + 0x588 + read-write + 0x00000000 + 0x20 + + + ADDRESS + TWI slave address + 0 + 6 + + + - MODE - Operation mode - 0x504 + CONFIG + Configuration register for the address match mechanism + 0x594 read-write 0x00000001 + 0x20 - MODE - The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered. + ADDRESS0 + Enable or disable address matching on ADDRESS[0] 0 0 - Encryption - AES CCM packet encryption mode - 0 - - - Decryption - AES CCM packet decryption mode - 1 - - - - - DATARATE - Radio data rate that the CCM shall run synchronous with - 16 - 17 - - - 1Mbit - 1 Mbps - 0 - - - 2Mbit - 2 Mbps - 1 - - - 125Kbps - 125 Kbps - 2 + Disabled + Disabled + 0x0 - 500Kbps - 500 Kbps - 3 + Enabled + Enabled + 0x1 - LENGTH - Packet length configuration - 24 - 24 + ADDRESS1 + Enable or disable address matching on ADDRESS[1] + 1 + 1 - Default - Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packet payloads up to 27 bytes will be generated. - 0 + Disabled + Disabled + 0x0 - Extended - Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packet payloads up to MAXPACKETSIZE bytes will be generated. - 1 + Enabled + Enabled + 0x1 - CNFPTR - Pointer to data structure holding AES key and NONCE vector - 0x508 + ORC + Over-read character. Character sent out in case of an over-read of the transmit buffer. + 0x5C0 read-write + 0x00000000 + 0x20 - CNFPTR - Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) + ORC + Over-read character. Character sent out in case of an over-read of the transmit buffer. 0 - 31 + 7 + + + + SPI1 + Serial Peripheral Interface 1 + 0x40004000 + + SPI1_SPIM1_SPIS1_TWI1_TWIM1_TWIS1 + 4 + + + + SPIM1 + Serial Peripheral Interface Master with EasyDMA 1 + 0x40004000 + SPI1 + + SPI1_SPIM1_SPIS1_TWI1_TWIM1_TWIS1 + 4 + + + + SPIS1 + SPI Slave 1 + 0x40004000 + SPI1 + + SPI1_SPIM1_SPIS1_TWI1_TWIM1_TWIS1 + 4 + + + + TWI1 + I2C compatible Two-Wire Interface 1 + 0x40004000 + SPI1 + + SPI1_SPIM1_SPIS1_TWI1_TWIM1_TWIS1 + 4 + + + + TWIM1 + I2C compatible Two-Wire Master Interface with EasyDMA 1 + 0x40004000 + SPI1 + + SPI1_SPIM1_SPIS1_TWI1_TWIM1_TWIS1 + 4 + + + + TWIS1 + I2C compatible Two-Wire Slave Interface with EasyDMA 1 + 0x40004000 + SPI1 + + SPI1_SPIM1_SPIS1_TWI1_TWIM1_TWIS1 + 4 + + + + NFCT + NFC-A compatible radio + 0x40005000 + + 0 + 0x1000 + registers + + + NFCT + 5 + + NFCT + 0x20 + - INPTR - Input pointer - 0x50C - read-write + TASKS_ACTIVATE + Activate NFCT peripheral for incoming and outgoing frames, change state to activated + 0x000 + write-only + 0x00000000 + 0x20 - INPTR - Input pointer + TASKS_ACTIVATE + Activate NFCT peripheral for incoming and outgoing frames, change state to activated 0 - 31 + 0 + + + Trigger + Trigger task + 0x1 + + - OUTPTR - Output pointer - 0x510 - read-write + TASKS_DISABLE + Disable NFCT peripheral + 0x004 + write-only + 0x00000000 + 0x20 - OUTPTR - Output pointer + TASKS_DISABLE + Disable NFCT peripheral 0 - 31 + 0 + + + Trigger + Trigger task + 0x1 + + - SCRATCHPTR - Pointer to data area used for temporary storage - 0x514 - read-write + TASKS_SENSE + Enable NFC sense field mode, change state to sense mode + 0x008 + write-only + 0x00000000 + 0x20 - SCRATCHPTR - Pointer to a scratch data area used for temporary storage during key-stream generation, - MIC generation and encryption/decryption. + TASKS_SENSE + Enable NFC sense field mode, change state to sense mode 0 - 31 + 0 + + + Trigger + Trigger task + 0x1 + + - MAXPACKETSIZE - Length of key-stream generated when MODE.LENGTH = Extended. - 0x518 - read-write - 0x000000FB + TASKS_STARTTX + Start transmission of an outgoing frame, change state to transmit + 0x00C + write-only + 0x00000000 + 0x20 - MAXPACKETSIZE - Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. + TASKS_STARTTX + Start transmission of an outgoing frame, change state to transmit 0 - 7 + 0 + + + Trigger + Trigger task + 0x1 + + - RATEOVERRIDE - Data rate override setting. - 0x51C - read-write + TASKS_ENABLERXDATA + Initializes the EasyDMA for receive. + 0x01C + write-only 0x00000000 + 0x20 - RATEOVERRIDE - Data rate override setting. + TASKS_ENABLERXDATA + Initializes the EasyDMA for receive. 0 - 1 + 0 - 1Mbit - 1 Mbps - 0 - - - 2Mbit - 2 Mbps - 1 - - - 125Kbps - 125 Kbps - 2 + Trigger + Trigger task + 0x1 - - 500Kbps - 500 Kbps - 3 + + + + + + TASKS_GOIDLE + Force state machine to IDLE state + 0x024 + write-only + 0x00000000 + 0x20 + + + TASKS_GOIDLE + Force state machine to IDLE state + 0 + 0 + + + Trigger + Trigger task + 0x1 - - - - WDT - Watchdog Timer - 0x40010000 - - 0 - 0x1000 - registers - - - WDT - 16 - - WDT - 0x20 - - TASKS_START - Start the watchdog - 0x000 + TASKS_GOSLEEP + Force state machine to SLEEP_A state + 0x028 write-only + 0x00000000 + 0x20 - TASKS_START + TASKS_GOSLEEP + Force state machine to SLEEP_A state 0 0 + + + Trigger + Trigger task + 0x1 + + - EVENTS_TIMEOUT - Watchdog timeout + EVENTS_READY + The NFCT peripheral is ready to receive and send frames 0x100 read-write + 0x00000000 + 0x20 - EVENTS_TIMEOUT + EVENTS_READY + The NFCT peripheral is ready to receive and send frames 0 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + - INTENSET - Enable interrupt - 0x304 + EVENTS_FIELDDETECTED + Remote NFC field detected + 0x104 read-write + 0x00000000 + 0x20 - TIMEOUT - Write '1' to enable interrupt for TIMEOUT event + EVENTS_FIELDDETECTED + Remote NFC field detected 0 0 - read - Disabled - Read: Disabled - 0 + NotGenerated + Event not generated + 0x0 - Enabled - Read: Enabled - 1 + Generated + Event generated + 0x1 + + + + + EVENTS_FIELDLOST + Remote NFC field lost + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_FIELDLOST + Remote NFC field lost + 0 + 0 - write - Set - Enable - 1 + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 - INTENCLR - Disable interrupt - 0x308 + EVENTS_TXFRAMESTART + Marks the start of the first symbol of a transmitted frame + 0x10C read-write + 0x00000000 + 0x20 - TIMEOUT - Write '1' to disable interrupt for TIMEOUT event + EVENTS_TXFRAMESTART + Marks the start of the first symbol of a transmitted frame 0 0 - read - Disabled - Read: Disabled - 0 + NotGenerated + Event not generated + 0x0 - Enabled - Read: Enabled - 1 + Generated + Event generated + 0x1 + + + + + EVENTS_TXFRAMEEND + Marks the end of the last transmitted on-air symbol of a frame + 0x110 + read-write + 0x00000000 + 0x20 + + + EVENTS_TXFRAMEEND + Marks the end of the last transmitted on-air symbol of a frame + 0 + 0 - write - Clear - Disable - 1 + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 - RUNSTATUS - Run status - 0x400 - read-only + EVENTS_RXFRAMESTART + Marks the end of the first symbol of a received frame + 0x114 + read-write + 0x00000000 + 0x20 - RUNSTATUS - Indicates whether or not the watchdog is running + EVENTS_RXFRAMESTART + Marks the end of the first symbol of a received frame 0 0 - NotRunning - Watchdog not running - 0 + NotGenerated + Event not generated + 0x0 - Running - Watchdog is running - 1 + Generated + Event generated + 0x1 - REQSTATUS - Request status - 0x404 - read-only - 0x00000001 + EVENTS_RXFRAMEEND + Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer + 0x118 + read-write + 0x00000000 + 0x20 - RR0 - Request status for RR[0] register + EVENTS_RXFRAMEEND + Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer 0 0 - DisabledOrRequested - RR[0] register is not enabled, or are already requesting reload - 0 + NotGenerated + Event not generated + 0x0 - EnabledAndUnrequested - RR[0] register is enabled, and are not yet requesting reload - 1 + Generated + Event generated + 0x1 + + + + EVENTS_ERROR + NFC error reported. The ERRORSTATUS register contains details on the source of the error. + 0x11C + read-write + 0x00000000 + 0x20 + - RR1 - Request status for RR[1] register - 1 - 1 + EVENTS_ERROR + NFC error reported. The ERRORSTATUS register contains details on the source of the error. + 0 + 0 - DisabledOrRequested - RR[1] register is not enabled, or are already requesting reload - 0 + NotGenerated + Event not generated + 0x0 - EnabledAndUnrequested - RR[1] register is enabled, and are not yet requesting reload - 1 + Generated + Event generated + 0x1 + + + + EVENTS_RXERROR + NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. + 0x128 + read-write + 0x00000000 + 0x20 + - RR2 - Request status for RR[2] register - 2 - 2 + EVENTS_RXERROR + NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. + 0 + 0 - DisabledOrRequested - RR[2] register is not enabled, or are already requesting reload - 0 + NotGenerated + Event not generated + 0x0 - EnabledAndUnrequested - RR[2] register is enabled, and are not yet requesting reload - 1 + Generated + Event generated + 0x1 + + + + EVENTS_ENDRX + RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. + 0x12C + read-write + 0x00000000 + 0x20 + - RR3 - Request status for RR[3] register - 3 - 3 + EVENTS_ENDRX + RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. + 0 + 0 - DisabledOrRequested - RR[3] register is not enabled, or are already requesting reload - 0 + NotGenerated + Event not generated + 0x0 - EnabledAndUnrequested - RR[3] register is enabled, and are not yet requesting reload - 1 + Generated + Event generated + 0x1 + + + + EVENTS_ENDTX + Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer + 0x130 + read-write + 0x00000000 + 0x20 + - RR4 - Request status for RR[4] register - 4 - 4 + EVENTS_ENDTX + Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer + 0 + 0 - DisabledOrRequested - RR[4] register is not enabled, or are already requesting reload - 0 + NotGenerated + Event not generated + 0x0 - EnabledAndUnrequested - RR[4] register is enabled, and are not yet requesting reload - 1 + Generated + Event generated + 0x1 + + + + EVENTS_AUTOCOLRESSTARTED + Auto collision resolution process has started + 0x138 + read-write + 0x00000000 + 0x20 + - RR5 - Request status for RR[5] register - 5 - 5 + EVENTS_AUTOCOLRESSTARTED + Auto collision resolution process has started + 0 + 0 - DisabledOrRequested - RR[5] register is not enabled, or are already requesting reload - 0 + NotGenerated + Event not generated + 0x0 - EnabledAndUnrequested - RR[5] register is enabled, and are not yet requesting reload - 1 + Generated + Event generated + 0x1 + + + + EVENTS_COLLISION + NFC auto collision resolution error reported. + 0x148 + read-write + 0x00000000 + 0x20 + - RR6 - Request status for RR[6] register - 6 - 6 + EVENTS_COLLISION + NFC auto collision resolution error reported. + 0 + 0 - DisabledOrRequested - RR[6] register is not enabled, or are already requesting reload - 0 + NotGenerated + Event not generated + 0x0 - EnabledAndUnrequested - RR[6] register is enabled, and are not yet requesting reload - 1 + Generated + Event generated + 0x1 + + + + EVENTS_SELECTED + NFC auto collision resolution successfully completed + 0x14C + read-write + 0x00000000 + 0x20 + - RR7 - Request status for RR[7] register - 7 - 7 + EVENTS_SELECTED + NFC auto collision resolution successfully completed + 0 + 0 - DisabledOrRequested - RR[7] register is not enabled, or are already requesting reload - 0 + NotGenerated + Event not generated + 0x0 - EnabledAndUnrequested - RR[7] register is enabled, and are not yet requesting reload - 1 + Generated + Event generated + 0x1 - CRV - Counter reload value - 0x504 + EVENTS_STARTED + EasyDMA is ready to receive or send frames. + 0x150 read-write - 0xFFFFFFFF + 0x00000000 + 0x20 - CRV - Counter reload value in number of cycles of the 32.768 kHz clock + EVENTS_STARTED + EasyDMA is ready to receive or send frames. 0 - 31 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + - RREN - Enable register for reload request registers - 0x508 + SHORTS + Shortcuts between local events and tasks + 0x200 read-write - 0x00000001 + 0x00000000 + 0x20 - RR0 - Enable or disable RR[0] register + FIELDDETECTED_ACTIVATE + Shortcut between event FIELDDETECTED and task ACTIVATE 0 0 Disabled - Disable RR[0] register - 0 + Disable shortcut + 0x0 Enabled - Enable RR[0] register - 1 + Enable shortcut + 0x1 - RR1 - Enable or disable RR[1] register + FIELDLOST_SENSE + Shortcut between event FIELDLOST and task SENSE 1 1 Disabled - Disable RR[1] register - 0 + Disable shortcut + 0x0 Enabled - Enable RR[1] register - 1 + Enable shortcut + 0x1 - RR2 - Enable or disable RR[2] register + TXFRAMEEND_ENABLERXDATA + Shortcut between event TXFRAMEEND and task ENABLERXDATA + 5 + 5 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + READY + Enable or disable interrupt for event READY + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + FIELDDETECTED + Enable or disable interrupt for event FIELDDETECTED + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + FIELDLOST + Enable or disable interrupt for event FIELDLOST 2 2 Disabled - Disable RR[2] register - 0 + Disable + 0x0 Enabled - Enable RR[2] register - 1 + Enable + 0x1 - RR3 - Enable or disable RR[3] register + TXFRAMESTART + Enable or disable interrupt for event TXFRAMESTART 3 3 Disabled - Disable RR[3] register - 0 + Disable + 0x0 Enabled - Enable RR[3] register - 1 + Enable + 0x1 - RR4 - Enable or disable RR[4] register + TXFRAMEEND + Enable or disable interrupt for event TXFRAMEEND 4 4 Disabled - Disable RR[4] register - 0 + Disable + 0x0 Enabled - Enable RR[4] register - 1 + Enable + 0x1 - RR5 - Enable or disable RR[5] register + RXFRAMESTART + Enable or disable interrupt for event RXFRAMESTART 5 5 Disabled - Disable RR[5] register - 0 + Disable + 0x0 Enabled - Enable RR[5] register - 1 + Enable + 0x1 - RR6 - Enable or disable RR[6] register + RXFRAMEEND + Enable or disable interrupt for event RXFRAMEEND 6 6 Disabled - Disable RR[6] register - 0 + Disable + 0x0 Enabled - Enable RR[6] register - 1 + Enable + 0x1 - RR7 - Enable or disable RR[7] register + ERROR + Enable or disable interrupt for event ERROR 7 7 Disabled - Disable RR[7] register - 0 + Disable + 0x0 Enabled - Enable RR[7] register - 1 + Enable + 0x1 - - - - CONFIG - Configuration register - 0x50C - read-write - 0x00000001 - - SLEEP - Configure the watchdog to either be paused, or kept running, while the CPU is sleeping - 0 - 0 + RXERROR + Enable or disable interrupt for event RXERROR + 10 + 10 - Pause - Pause watchdog while the CPU is sleeping - 0 + Disabled + Disable + 0x0 - Run - Keep the watchdog running while the CPU is sleeping - 1 + Enabled + Enable + 0x1 - HALT - Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger - 3 - 3 + ENDRX + Enable or disable interrupt for event ENDRX + 11 + 11 - Pause - Pause watchdog while the CPU is halted by the debugger - 0 + Disabled + Disable + 0x0 - Run - Keep the watchdog running while the CPU is halted by the debugger - 1 + Enabled + Enable + 0x1 - - - - 8 - 0x4 - RR[%s] - Description collection[n]: Reload request n - 0x600 - write-only - - RR - Reload request register - 0 - 31 + ENDTX + Enable or disable interrupt for event ENDTX + 12 + 12 - Reload - Value to request a reload of the watchdog timer - 0x6E524635 + Disabled + Disable + 0x0 - - - - - - - - RTC1 - Real time counter 1 - 0x40011000 - - RTC1 - 17 - - - - QDEC - Quadrature Decoder - 0x40012000 - - 0 - 0x1000 - registers - - - QDEC - 18 - - QDEC - 0x20 - - - TASKS_START - Task starting the quadrature decoder - 0x000 - write-only - - - TASKS_START - 0 - 0 - - - - - TASKS_STOP - Task stopping the quadrature decoder - 0x004 - write-only - - - TASKS_STOP - 0 - 0 - - - - - TASKS_READCLRACC - Read and clear ACC and ACCDBL - 0x008 - write-only - - - TASKS_READCLRACC - 0 - 0 - - - - - TASKS_RDCLRACC - Read and clear ACC - 0x00C - write-only - - - TASKS_RDCLRACC - 0 - 0 - - - - - TASKS_RDCLRDBL - Read and clear ACCDBL - 0x010 - write-only - - - TASKS_RDCLRDBL - 0 - 0 - - - - - EVENTS_SAMPLERDY - Event being generated for every new sample value written to the SAMPLE register - 0x100 - read-write - - - EVENTS_SAMPLERDY - 0 - 0 + + Enabled + Enable + 0x1 + + - - - - EVENTS_REPORTRDY - Non-null report ready - 0x104 - read-write - - EVENTS_REPORTRDY - 0 - 0 + AUTOCOLRESSTARTED + Enable or disable interrupt for event AUTOCOLRESSTARTED + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + - - - - EVENTS_ACCOF - ACC or ACCDBL register overflow - 0x108 - read-write - - EVENTS_ACCOF - 0 - 0 + COLLISION + Enable or disable interrupt for event COLLISION + 18 + 18 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + - - - - EVENTS_DBLRDY - Double displacement(s) detected - 0x10C - read-write - - EVENTS_DBLRDY - 0 - 0 + SELECTED + Enable or disable interrupt for event SELECTED + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + - - - - EVENTS_STOPPED - QDEC has been stopped - 0x110 - read-write - - EVENTS_STOPPED - 0 - 0 + STARTED + Enable or disable interrupt for event STARTED + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + - SHORTS - Shortcut register - 0x200 + INTENSET + Enable interrupt + 0x304 read-write + 0x00000000 + 0x20 - REPORTRDY_READCLRACC - Shortcut between REPORTRDY event and READCLRACC task + READY + Write '1' to enable interrupt for event READY 0 0 + read Disabled - Disable shortcut - 0 + Read: Disabled + 0x0 Enabled - Enable shortcut - 1 + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 - SAMPLERDY_STOP - Shortcut between SAMPLERDY event and STOP task + FIELDDETECTED + Write '1' to enable interrupt for event FIELDDETECTED 1 1 + read Disabled - Disable shortcut - 0 + Read: Disabled + 0x0 Enabled - Enable shortcut - 1 + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 - REPORTRDY_RDCLRACC - Shortcut between REPORTRDY event and RDCLRACC task + FIELDLOST + Write '1' to enable interrupt for event FIELDLOST 2 2 + read Disabled - Disable shortcut - 0 + Read: Disabled + 0x0 Enabled - Enable shortcut - 1 + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 - REPORTRDY_STOP - Shortcut between REPORTRDY event and STOP task + TXFRAMESTART + Write '1' to enable interrupt for event TXFRAMESTART 3 3 + read Disabled - Disable shortcut - 0 + Read: Disabled + 0x0 Enabled - Enable shortcut - 1 + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 - DBLRDY_RDCLRDBL - Shortcut between DBLRDY event and RDCLRDBL task + TXFRAMEEND + Write '1' to enable interrupt for event TXFRAMEEND 4 4 + read Disabled - Disable shortcut - 0 + Read: Disabled + 0x0 Enabled - Enable shortcut - 1 + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 - DBLRDY_STOP - Shortcut between DBLRDY event and STOP task + RXFRAMESTART + Write '1' to enable interrupt for event RXFRAMESTART 5 5 + read Disabled - Disable shortcut - 0 + Read: Disabled + 0x0 Enabled - Enable shortcut - 1 + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 - SAMPLERDY_READCLRACC - Shortcut between SAMPLERDY event and READCLRACC task + RXFRAMEEND + Write '1' to enable interrupt for event RXFRAMEEND 6 6 + read Disabled - Disable shortcut - 0 + Read: Disabled + 0x0 Enabled - Enable shortcut - 1 + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 - - - - INTENSET - Enable interrupt - 0x304 - read-write - - SAMPLERDY - Write '1' to enable interrupt for SAMPLERDY event - 0 - 0 + ERROR + Write '1' to enable interrupt for event ERROR + 7 + 7 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -25402,26 +25549,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - REPORTRDY - Write '1' to enable interrupt for REPORTRDY event - 1 - 1 + RXERROR + Write '1' to enable interrupt for event RXERROR + 10 + 10 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -25429,26 +25576,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - ACCOF - Write '1' to enable interrupt for ACCOF event - 2 - 2 + ENDRX + Write '1' to enable interrupt for event ENDRX + 11 + 11 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -25456,26 +25603,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - DBLRDY - Write '1' to enable interrupt for DBLRDY event - 3 - 3 + ENDTX + Write '1' to enable interrupt for event ENDTX + 12 + 12 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -25483,26 +25630,107 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - STOPPED - Write '1' to enable interrupt for STOPPED event - 4 - 4 + AUTOCOLRESSTARTED + Write '1' to enable interrupt for event AUTOCOLRESSTARTED + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COLLISION + Write '1' to enable interrupt for event COLLISION + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SELECTED + Write '1' to enable interrupt for event SELECTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STARTED + Write '1' to enable interrupt for event STARTED + 20 + 20 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -25510,7 +25738,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 @@ -25521,10 +25749,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disable interrupt 0x308 read-write + 0x00000000 + 0x20 - SAMPLERDY - Write '1' to disable interrupt for SAMPLERDY event + READY + Write '1' to disable interrupt for event READY 0 0 @@ -25532,12 +25762,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -25545,13 +25775,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - REPORTRDY - Write '1' to disable interrupt for REPORTRDY event + FIELDDETECTED + Write '1' to disable interrupt for event FIELDDETECTED 1 1 @@ -25559,12 +25789,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -25572,13 +25802,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - ACCOF - Write '1' to disable interrupt for ACCOF event + FIELDLOST + Write '1' to disable interrupt for event FIELDLOST 2 2 @@ -25586,12 +25816,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -25599,13 +25829,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - DBLRDY - Write '1' to disable interrupt for DBLRDY event + TXFRAMESTART + Write '1' to disable interrupt for event TXFRAMESTART 3 3 @@ -25613,12 +25843,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -25626,13 +25856,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - STOPPED - Write '1' to disable interrupt for STOPPED event + TXFRAMEEND + Write '1' to disable interrupt for event TXFRAMEEND 4 4 @@ -25640,12 +25870,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -25653,358 +25883,365 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - - - - ENABLE - Enable the quadrature decoder - 0x500 - read-write - - ENABLE - Enable or disable the quadrature decoder - 0 - 0 + RXFRAMESTART + Write '1' to disable interrupt for event RXFRAMESTART + 5 + 5 + read Disabled - Disable - 0 + Read: Disabled + 0x0 Enabled - Enable - 1 + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 - - - - LEDPOL - LED output pin polarity - 0x504 - read-write - - LEDPOL - LED output pin polarity - 0 - 0 + RXFRAMEEND + Write '1' to disable interrupt for event RXFRAMEEND + 6 + 6 + read - ActiveLow - Led active on output pin low - 0 + Disabled + Read: Disabled + 0x0 - ActiveHigh - Led active on output pin high - 1 + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 - - - - SAMPLEPER - Sample period - 0x508 - read-write - - SAMPLEPER - Sample period. The SAMPLE register will be updated for every new sample - 0 - 3 + ERROR + Write '1' to disable interrupt for event ERROR + 7 + 7 + read - 128us - 128 us - 0 + Disabled + Read: Disabled + 0x0 - 256us - 256 us - 1 + Enabled + Read: Enabled + 0x1 + + + write - 512us - 512 us - 2 + Clear + Disable + 0x1 + + + + RXERROR + Write '1' to disable interrupt for event RXERROR + 10 + 10 + + read - 1024us - 1024 us - 3 + Disabled + Read: Disabled + 0x0 - 2048us - 2048 us - 4 + Enabled + Read: Enabled + 0x1 + + + write - 4096us - 4096 us - 5 + Clear + Disable + 0x1 + + + + ENDRX + Write '1' to disable interrupt for event ENDRX + 11 + 11 + + read - 8192us - 8192 us - 6 + Disabled + Read: Disabled + 0x0 - 16384us - 16384 us - 7 + Enabled + Read: Enabled + 0x1 + + + write - 32ms - 32768 us - 8 + Clear + Disable + 0x1 + + + + ENDTX + Write '1' to disable interrupt for event ENDTX + 12 + 12 + + read - 65ms - 65536 us - 9 + Disabled + Read: Disabled + 0x0 - 131ms - 131072 us - 10 + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 - - - - SAMPLE - Motion sample value - 0x50C - read-only - int32_t - - - SAMPLE - Last motion sample - 0 - 31 - - - - - REPORTPER - Number of samples to be taken before REPORTRDY and DBLRDY events can be generated - 0x510 - read-write - - REPORTPER - Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated - 0 - 3 + AUTOCOLRESSTARTED + Write '1' to disable interrupt for event AUTOCOLRESSTARTED + 14 + 14 + read - 10Smpl - 10 samples / report - 0 + Disabled + Read: Disabled + 0x0 - 40Smpl - 40 samples / report - 1 + Enabled + Read: Enabled + 0x1 + + + write - 80Smpl - 80 samples / report - 2 + Clear + Disable + 0x1 + + + + COLLISION + Write '1' to disable interrupt for event COLLISION + 18 + 18 + + read - 120Smpl - 120 samples / report - 3 + Disabled + Read: Disabled + 0x0 - 160Smpl - 160 samples / report - 4 + Enabled + Read: Enabled + 0x1 + + + write - 200Smpl - 200 samples / report - 5 + Clear + Disable + 0x1 + + + + SELECTED + Write '1' to disable interrupt for event SELECTED + 19 + 19 + + read - 240Smpl - 240 samples / report - 6 + Disabled + Read: Disabled + 0x0 - 280Smpl - 280 samples / report - 7 + Enabled + Read: Enabled + 0x1 + + + write - 1Smpl - 1 sample / report - 8 + Clear + Disable + 0x1 - - - - ACC - Register accumulating the valid transitions - 0x514 - read-only - int32_t - - ACC - Register accumulating all valid samples (not double transition) read from the SAMPLE register - 0 - 31 + STARTED + Write '1' to disable interrupt for event STARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + - ACCREAD - Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task - 0x518 - read-only - int32_t + ERRORSTATUS + NFC Error Status register + 0x404 + read-write + 0x00000000 + oneToClear + 0x20 - ACCREAD - Snapshot of the ACC register. + FRAMEDELAYTIMEOUT + No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX 0 - 31 + 0 - PSEL + FRAMESTATUS Unspecified - QDEC_PSEL - 0x51C + NFCT_FRAMESTATUS + read-write + 0x40C - LED - Pin select for LED signal + RX + Result of last incoming frame 0x000 read-write - 0xFFFFFFFF + 0x00000000 + oneToClear + 0x20 - PIN - Pin number + CRCERROR + No valid end of frame (EoF) detected 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 + 0 - Disconnected - Disconnect - 1 + CRCCorrect + Valid CRC detected + 0x0 - Connected - Connect - 0 + CRCError + CRC received does not match local check + 0x1 - - - - A - Pin select for A signal - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - CONNECT - Connection - 31 - 31 + PARITYSTATUS + Parity status of received frame + 2 + 2 - Disconnected - Disconnect - 1 + ParityOK + Frame received with parity OK + 0x0 - Connected - Connect - 0 + ParityError + Frame received with parity error + 0x1 - - - - B - Pin select for B signal - 0x008 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - CONNECT - Connection - 31 - 31 + OVERRUN + Overrun detected + 3 + 3 - Disconnected - Disconnect - 1 + NoOverrun + No overrun detected + 0x0 - Connected - Connect - 0 + Overrun + Overrun error + 0x1 @@ -26012,358 +26249,830 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ - DBFEN - Enable input debounce filters - 0x528 - read-write + NFCTAGSTATE + NfcTag state register + 0x410 + read-only + 0x00000000 + 0x20 - DBFEN - Enable input debounce filters + NFCTAGSTATE + NfcTag state 0 - 0 + 2 Disabled - Debounce input filters disabled - 0 + Disabled or sense + 0x0 - Enabled - Debounce input filters enabled - 1 + RampUp + RampUp + 0x2 + + + Idle + Idle + 0x3 + + + Receive + Receive + 0x4 + + + FrameDelay + FrameDelay + 0x5 + + + Transmit + Transmit + 0x6 - LEDPRE - Time period the LED is switched ON prior to sampling - 0x540 - read-write - 0x00000010 + SLEEPSTATE + Sleep state during automatic collision resolution + 0x420 + read-only + 0x00000000 + 0x20 - LEDPRE - Period in us the LED is switched on prior to sampling + SLEEPSTATE + Reflects the sleep state during automatic collision resolution. Set to IDLE + by a GOIDLE task. Set to SLEEP_A when a valid SLEEP_REQ frame is received or by a + GOSLEEP task. 0 - 8 + 0 + + + Idle + State is IDLE. + 0x0 + + + SleepA + State is SLEEP_A. + 0x1 + + - ACCDBL - Register accumulating the number of detected double transitions - 0x544 + FIELDPRESENT + Indicates the presence or not of a valid field + 0x43C read-only + 0x00000000 + 0x20 - ACCDBL - Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). + FIELDPRESENT + Indicates if a valid field is present. Available only in the activated state. 0 - 3 + 0 + + + NoField + No valid field detected + 0x0 + + + FieldPresent + Valid field detected + 0x1 + + + + + LOCKDETECT + Indicates if the low level has locked to the field + 1 + 1 + + + NotLocked + Not locked to field + 0x0 + + + Locked + Locked to field + 0x1 + + - ACCDBLREAD - Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task - 0x548 - read-only + FRAMEDELAYMIN + Minimum frame delay + 0x504 + read-write + 0x00000480 + 0x20 - ACCDBLREAD - Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. + FRAMEDELAYMIN + Minimum frame delay in number of 13.56 MHz clocks 0 - 3 + 15 - - - - COMP - Comparator - 0x40013000 - - 0 - 0x1000 - registers - - - COMP_LPCOMP - 19 - - COMP - 0x20 - - TASKS_START - Start comparator - 0x000 - write-only + FRAMEDELAYMAX + Maximum frame delay + 0x508 + read-write + 0x00001000 + 0x20 - TASKS_START + FRAMEDELAYMAX + Maximum frame delay in number of 13.56 MHz clocks 0 - 0 + 19 - TASKS_STOP - Stop comparator - 0x004 - write-only + FRAMEDELAYMODE + Configuration register for the Frame Delay Timer + 0x50C + read-write + 0x00000001 + 0x20 - TASKS_STOP + FRAMEDELAYMODE + Configuration register for the Frame Delay Timer 0 - 0 + 1 + + + FreeRun + Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. + 0x0 + + + Window + Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX + 0x1 + + + ExactVal + Frame is transmitted exactly at FRAMEDELAYMAX + 0x2 + + + WindowGrid + Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX + 0x3 + + - TASKS_SAMPLE - Sample comparator value - 0x008 - write-only + PACKETPTR + Packet pointer for TXD and RXD data storage in Data RAM + 0x510 + read-write + 0x00000000 + 0x20 - TASKS_SAMPLE + PTR + Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte-aligned RAM address. 0 - 0 + 31 - EVENTS_READY - COMP is ready and output is valid - 0x100 + MAXLEN + Size of the RAM buffer allocated to TXD and RXD data storage each + 0x514 read-write + 0x00000000 + 0x20 - EVENTS_READY + MAXLEN + Size of the RAM buffer allocated to TXD and RXD data storage each 0 - 0 + 8 + + TXD + Unspecified + NFCT_TXD + read-write + 0x518 + + FRAMECONFIG + Configuration of outgoing frames + 0x000 + read-write + 0x00000017 + 0x20 + + + PARITY + Indicates if parity is added to the frame + 0 + 0 + + + NoParity + Parity is not added to TX frames + 0x0 + + + Parity + Parity is added to TX frames + 0x1 + + + + + DISCARDMODE + Discarding unused bits at start or end of a frame + 1 + 1 + + + DiscardEnd + Unused bits are discarded at end of frame (EoF) + 0x0 + + + DiscardStart + Unused bits are discarded at start of frame (SoF) + 0x1 + + + + + SOF + Adding SoF or not in TX frames + 2 + 2 + + + NoSoF + SoF symbol not added + 0x0 + + + SoF + SoF symbol added + 0x1 + + + + + CRCMODETX + CRC mode for outgoing frames + 4 + 4 + + + NoCRCTX + CRC is not added to the frame + 0x0 + + + CRC16TX + 16 bit CRC added to the frame based on all the data read from RAM that is used in the frame + 0x1 + + + + + + + AMOUNT + Size of outgoing frame + 0x004 + read-write + 0x00000000 + 0x20 + + + TXDATABITS + Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit). + 0 + 2 + + + TXDATABYTES + Number of complete bytes that shall be included in the frame, excluding CRC, parity and framing + 3 + 11 + + + + + + RXD + Unspecified + NFCT_RXD + read-write + 0x520 + + FRAMECONFIG + Configuration of incoming frames + 0x000 + read-write + 0x00000015 + 0x20 + + + PARITY + Indicates if parity expected in RX frame + 0 + 0 + + + NoParity + Parity is not expected in RX frames + 0x0 + + + Parity + Parity is expected in RX frames + 0x1 + + + + + SOF + SoF expected or not in RX frames + 2 + 2 + + + NoSoF + SoF symbol is not expected in RX frames + 0x0 + + + SoF + SoF symbol is expected in RX frames + 0x1 + + + + + CRCMODERX + CRC mode for incoming frames + 4 + 4 + + + NoCRCRX + CRC is not expected in RX frames + 0x0 + + + CRC16RX + Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated + 0x1 + + + + + + + AMOUNT + Size of last incoming frame + 0x004 + read-only + 0x00000000 + 0x20 + + + RXDATABITS + Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing). + 0 + 2 + + + RXDATABYTES + Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing) + 3 + 11 + + + + - EVENTS_DOWN - Downward crossing - 0x104 + NFCID1_LAST + Last NFCID1 part (4, 7 or 10 bytes ID) + 0x590 read-write + 0x00006363 + 0x20 - EVENTS_DOWN + NFCID1_Z + NFCID1 byte Z (very last byte sent) 0 - 0 + 7 + + + NFCID1_Y + NFCID1 byte Y + 8 + 15 + + + NFCID1_X + NFCID1 byte X + 16 + 23 + + + NFCID1_W + NFCID1 byte W + 24 + 31 - EVENTS_UP - Upward crossing - 0x108 + NFCID1_2ND_LAST + Second last NFCID1 part (7 or 10 bytes ID) + 0x594 read-write + 0x00000000 + 0x20 - EVENTS_UP + NFCID1_V + NFCID1 byte V 0 - 0 + 7 + + + NFCID1_U + NFCID1 byte U + 8 + 15 + + + NFCID1_T + NFCID1 byte T + 16 + 23 - EVENTS_CROSS - Downward or upward crossing - 0x10C + NFCID1_3RD_LAST + Third last NFCID1 part (10 bytes ID) + 0x598 read-write + 0x00000000 + 0x20 - EVENTS_CROSS + NFCID1_S + NFCID1 byte S 0 - 0 + 7 + + + NFCID1_R + NFCID1 byte R + 8 + 15 + + + NFCID1_Q + NFCID1 byte Q + 16 + 23 - SHORTS - Shortcut register - 0x200 + AUTOCOLRESCONFIG + Controls the auto collision resolution function. This setting must be done before the NFCT peripheral is activated. + 0x59C read-write + 0x00000002 + 0x20 - READY_SAMPLE - Shortcut between READY event and SAMPLE task + MODE + Enables/disables auto collision resolution 0 0 - Disabled - Disable shortcut - 0 + Enabled + Auto collision resolution enabled + 0x0 - Enabled - Enable shortcut - 1 + Disabled + Auto collision resolution disabled + 0x1 + + + + SENSRES + NFC-A SENS_RES auto-response settings + 0x5A0 + read-write + 0x00000001 + 0x20 + - READY_STOP - Shortcut between READY event and STOP task - 1 - 1 + BITFRAMESDD + Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification + 0 + 4 - Disabled - Disable shortcut - 0 + SDD00000 + SDD pattern 00000 + 0x00 - Enabled - Enable shortcut - 1 + SDD00001 + SDD pattern 00001 + 0x01 - - - - DOWN_STOP - Shortcut between DOWN event and STOP task - 2 - 2 - - Disabled - Disable shortcut - 0 + SDD00010 + SDD pattern 00010 + 0x02 - Enabled - Enable shortcut - 1 + SDD00100 + SDD pattern 00100 + 0x04 - - - - UP_STOP - Shortcut between UP event and STOP task - 3 - 3 - - Disabled - Disable shortcut - 0 + SDD01000 + SDD pattern 01000 + 0x08 - Enabled - Enable shortcut - 1 + SDD10000 + SDD pattern 10000 + 0x10 - CROSS_STOP - Shortcut between CROSS event and STOP task - 4 - 4 + RFU5 + Reserved for future use. Shall be 0. + 5 + 5 + + + NFCIDSIZE + NFCID1 size. This value is used by the auto collision resolution engine. + 6 + 7 - Disabled - Disable shortcut - 0 + NFCID1Single + NFCID1 size: single (4 bytes) + 0x0 - Enabled - Enable shortcut - 1 + NFCID1Double + NFCID1 size: double (7 bytes) + 0x1 + + + NFCID1Triple + NFCID1 size: triple (10 bytes) + 0x2 + + PLATFCONFIG + Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification + 8 + 11 + + + RFU74 + Reserved for future use. Shall be 0. + 12 + 15 + - INTEN - Enable or disable interrupt - 0x300 + SELRES + NFC-A SEL_RES auto-response settings + 0x5A4 read-write + 0x00000000 + 0x20 - READY - Enable or disable interrupt for READY event + RFU10 + Reserved for future use. Shall be 0. 0 - 0 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - DOWN - Enable or disable interrupt for DOWN event - 1 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - UP - Enable or disable interrupt for UP event + CASCADE + Cascade as defined by the b3 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification (controlled by hardware, shall be 0) 2 2 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - CROSS - Enable or disable interrupt for CROSS event + RFU43 + Reserved for future use. Shall be 0. 3 - 3 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - + 4 + + + PROTOCOL + Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification + 5 + 6 + + + RFU7 + Reserved for future use. Shall be 0. + 7 + 7 + + + + + + + GPIOTE + GPIO Tasks and Events + 0x40006000 + + 0 + 0x1000 + registers + + + GPIOTE + 6 + + GPIOTE + 0x20 + + + 0x8 + 0x4 + TASKS_OUT[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_OUT + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + TASKS_SET[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. + 0x030 + write-only + 0x00000000 + 0x20 + + + TASKS_SET + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + TASKS_CLR[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. + 0x060 + write-only + 0x00000000 + 0x20 + + + TASKS_CLR + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + EVENTS_IN[%s] + Description collection: Event generated from pin specified in CONFIG[n].PSEL + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_IN + Event generated from pin specified in CONFIG[n].PSEL + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_PORT + Event generated from multiple input GPIO pins with SENSE mechanism enabled + 0x17C + read-write + 0x00000000 + 0x20 + + + EVENTS_PORT + Event generated from multiple input GPIO pins with SENSE mechanism enabled + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + @@ -26372,10 +27081,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Enable interrupt 0x304 read-write + 0x00000000 + 0x20 - READY - Write '1' to enable interrupt for READY event + IN0 + Write '1' to enable interrupt for event IN[0] 0 0 @@ -26383,12 +27094,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -26396,13 +27107,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - DOWN - Write '1' to enable interrupt for DOWN event + IN1 + Write '1' to enable interrupt for event IN[1] 1 1 @@ -26410,12 +27121,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -26423,13 +27134,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - UP - Write '1' to enable interrupt for UP event + IN2 + Write '1' to enable interrupt for event IN[2] 2 2 @@ -26437,12 +27148,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -26450,13 +27161,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - CROSS - Write '1' to enable interrupt for CROSS event + IN3 + Write '1' to enable interrupt for event IN[3] 3 3 @@ -26464,12 +27175,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -26477,425 +27188,488 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - READY - Write '1' to disable interrupt for READY event - 0 - 0 + IN4 + Write '1' to enable interrupt for event IN[4] + 4 + 4 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Clear - Disable - 1 + Set + Enable + 0x1 - DOWN - Write '1' to disable interrupt for DOWN event - 1 - 1 + IN5 + Write '1' to enable interrupt for event IN[5] + 5 + 5 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Clear - Disable - 1 + Set + Enable + 0x1 - UP - Write '1' to disable interrupt for UP event - 2 - 2 + IN6 + Write '1' to enable interrupt for event IN[6] + 6 + 6 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Clear - Disable - 1 + Set + Enable + 0x1 - CROSS - Write '1' to disable interrupt for CROSS event - 3 - 3 + IN7 + Write '1' to enable interrupt for event IN[7] + 7 + 7 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Clear - Disable - 1 + Set + Enable + 0x1 - - - - RESULT - Compare result - 0x400 - read-only - - RESULT - Result of last compare. Decision point SAMPLE task. - 0 - 0 + PORT + Write '1' to enable interrupt for event PORT + 31 + 31 + read - Below - Input voltage is below the threshold (VIN+ &lt; VIN-) - 0 + Disabled + Read: Disabled + 0x0 - Above - Input voltage is above the threshold (VIN+ &gt; VIN-) - 1 + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 - ENABLE - COMP enable - 0x500 + INTENCLR + Disable interrupt + 0x308 read-write + 0x00000000 + 0x20 - ENABLE - Enable or disable COMP + IN0 + Write '1' to disable interrupt for event IN[0] 0 - 1 + 0 + read Disabled - Disable - 0 + Read: Disabled + 0x0 Enabled - Enable - 2 + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 - - - - PSEL - Pin select - 0x504 - read-write - - PSEL - Analog pin select - 0 - 2 + IN1 + Write '1' to disable interrupt for event IN[1] + 1 + 1 + read - AnalogInput0 - AIN0 selected as analog input - 0 + Disabled + Read: Disabled + 0x0 - AnalogInput1 - AIN1 selected as analog input - 1 + Enabled + Read: Enabled + 0x1 + + + write - AnalogInput2 - AIN2 selected as analog input - 2 + Clear + Disable + 0x1 + + + + IN2 + Write '1' to disable interrupt for event IN[2] + 2 + 2 + + read - AnalogInput3 - AIN3 selected as analog input - 3 + Disabled + Read: Disabled + 0x0 - AnalogInput4 - AIN4 selected as analog input - 4 + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + IN3 + Write '1' to disable interrupt for event IN[3] + 3 + 3 + + read - AnalogInput5 - AIN5 selected as analog input - 5 + Disabled + Read: Disabled + 0x0 - AnalogInput6 - AIN6 selected as analog input - 6 + Enabled + Read: Enabled + 0x1 + + + write - AnalogInput7 - AIN7 selected as analog input - 7 + Clear + Disable + 0x1 - - - - REFSEL - Reference source select for single-ended mode - 0x508 - read-write - 0x00000004 - - REFSEL - Reference select - 0 - 2 + IN4 + Write '1' to disable interrupt for event IN[4] + 4 + 4 + read - Int1V2 - VREF = internal 1.2 V reference (VDD &gt;= 1.7 V) - 0 + Disabled + Read: Disabled + 0x0 - Int1V8 - VREF = internal 1.8 V reference (VDD &gt;= VREF + 0.2 V) - 1 + Enabled + Read: Enabled + 0x1 + + + write - Int2V4 - VREF = internal 2.4 V reference (VDD &gt;= VREF + 0.2 V) - 2 + Clear + Disable + 0x1 + + + + + IN5 + Write '1' to disable interrupt for event IN[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 - VDD - VREF = VDD - 4 + Enabled + Read: Enabled + 0x1 + + + write - ARef - VREF = AREF (VDD &gt;= VREF &gt;= AREFMIN) - 5 + Clear + Disable + 0x1 - - - - EXTREFSEL - External reference select - 0x50C - read-write - - EXTREFSEL - External analog reference select - 0 - 2 + IN6 + Write '1' to disable interrupt for event IN[6] + 6 + 6 + read - AnalogReference0 - Use AIN0 as external analog reference - 0 + Disabled + Read: Disabled + 0x0 - AnalogReference1 - Use AIN1 as external analog reference - 1 + Enabled + Read: Enabled + 0x1 + + + write - AnalogReference2 - Use AIN2 as external analog reference - 2 + Clear + Disable + 0x1 + + + + IN7 + Write '1' to disable interrupt for event IN[7] + 7 + 7 + + read - AnalogReference3 - Use AIN3 as external analog reference - 3 + Disabled + Read: Disabled + 0x0 - AnalogReference4 - Use AIN4 as external analog reference - 4 + Enabled + Read: Enabled + 0x1 + + + write - AnalogReference5 - Use AIN5 as external analog reference - 5 + Clear + Disable + 0x1 + + + + PORT + Write '1' to disable interrupt for event PORT + 31 + 31 + + read - AnalogReference6 - Use AIN6 as external analog reference - 6 + Disabled + Read: Disabled + 0x0 - AnalogReference7 - Use AIN7 as external analog reference - 7 + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 - TH - Threshold configuration for hysteresis unit - 0x530 + 0x8 + 0x4 + CONFIG[%s] + Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event + 0x510 read-write 0x00000000 + 0x20 - THDOWN - VDOWN = (THDOWN+1)/64*VREF - 0 - 5 - - - THUP - VUP = (THUP+1)/64*VREF - 8 - 13 - - - - - MODE - Mode configuration - 0x534 - read-write - - - SP - Speed and power modes + MODE + Mode 0 1 - Low - Low-power mode - 0 + Disabled + Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. + 0x0 - Normal - Normal mode - 1 + Event + Event mode + 0x1 - High - High-speed mode - 2 + Task + Task mode + 0x3 - MAIN - Main operation modes + PSEL + GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event 8 - 8 - - - SE - Single-ended mode - 0 - - - Diff - Differential mode - 1 - - + 12 - - - - HYST - Comparator hysteresis enable - 0x538 - read-write - - HYST - Comparator hysteresis - 0 - 0 + PORT + Port number + 13 + 13 + + + POLARITY + When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. + 16 + 17 - NoHyst - Comparator hysteresis disabled - 0 + None + Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. + 0x0 - Hyst50mV - Comparator hysteresis enabled - 1 + LoToHi + Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. + 0x1 + + + HiToLo + Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. + 0x2 + + + Toggle + Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. + 0x3 + + + + + OUTINIT + When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. + 20 + 20 + + + Low + Task mode: Initial value of pin before task triggering is low + 0x0 + + + High + Task mode: Initial value of pin before task triggering is high + 0x1 @@ -26904,1098 +27678,1181 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ - LPCOMP - Low Power Comparator - 0x40013000 - COMP + SAADC + Successive approximation register (SAR) analog-to-digital converter + 0x40007000 0 0x1000 registers - COMP_LPCOMP - 19 + SAADC + 7 - LPCOMP + SAADC 0x20 TASKS_START - Start comparator + Starts the SAADC and prepares the result buffer in RAM 0x000 write-only + 0x00000000 + 0x20 TASKS_START + Starts the SAADC and prepares the result buffer in RAM 0 0 + + + Trigger + Trigger task + 0x1 + + - TASKS_STOP - Stop comparator + TASKS_SAMPLE + Takes one SAADC sample 0x004 write-only + 0x00000000 + 0x20 - TASKS_STOP + TASKS_SAMPLE + Takes one SAADC sample 0 0 + + + Trigger + Trigger task + 0x1 + + - TASKS_SAMPLE - Sample comparator value + TASKS_STOP + Stops the SAADC and terminates all on-going conversions 0x008 write-only + 0x00000000 + 0x20 - TASKS_SAMPLE + TASKS_STOP + Stops the SAADC and terminates all on-going conversions + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_CALIBRATEOFFSET + Starts offset auto-calibration + 0x00C + write-only + 0x00000000 + 0x20 + + + TASKS_CALIBRATEOFFSET + Starts offset auto-calibration 0 0 + + + Trigger + Trigger task + 0x1 + + - EVENTS_READY - LPCOMP is ready and output is valid + EVENTS_STARTED + The SAADC has started 0x100 read-write + 0x00000000 + 0x20 - EVENTS_READY + EVENTS_STARTED + The SAADC has started 0 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + - EVENTS_DOWN - Downward crossing + EVENTS_END + The SAADC has filled up the result buffer 0x104 read-write + 0x00000000 + 0x20 - EVENTS_DOWN + EVENTS_END + The SAADC has filled up the result buffer 0 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + - EVENTS_UP - Upward crossing + EVENTS_DONE + A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM. 0x108 read-write + 0x00000000 + 0x20 - EVENTS_UP + EVENTS_DONE + A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM. 0 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + - EVENTS_CROSS - Downward or upward crossing + EVENTS_RESULTDONE + Result ready for transfer to RAM 0x10C read-write + 0x00000000 + 0x20 - EVENTS_CROSS + EVENTS_RESULTDONE + Result ready for transfer to RAM 0 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + - SHORTS - Shortcut register - 0x200 + EVENTS_CALIBRATEDONE + Calibration is complete + 0x110 read-write + 0x00000000 + 0x20 - READY_SAMPLE - Shortcut between READY event and SAMPLE task + EVENTS_CALIBRATEDONE + Calibration is complete + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_STOPPED + The SAADC has stopped + 0x114 + read-write + 0x00000000 + 0x20 + + + EVENTS_STOPPED + The SAADC has stopped + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 8 + 0x008 + EVENTS_CH[%s] + Peripheral events. + SAADC_EVENTS_CH + read-write + 0x118 + + LIMITH + Description cluster: Last result is equal or above CH[n].LIMIT.HIGH + 0x000 + read-write + 0x00000000 + 0x20 + + + LIMITH + Last result is equal or above CH[n].LIMIT.HIGH + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + LIMITL + Description cluster: Last result is equal or below CH[n].LIMIT.LOW + 0x004 + read-write + 0x00000000 + 0x20 + + + LIMITL + Last result is equal or below CH[n].LIMIT.LOW + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + STARTED + Enable or disable interrupt for event STARTED 0 0 Disabled - Disable shortcut - 0 + Disable + 0x0 Enabled - Enable shortcut - 1 + Enable + 0x1 - READY_STOP - Shortcut between READY event and STOP task + END + Enable or disable interrupt for event END 1 1 Disabled - Disable shortcut - 0 + Disable + 0x0 Enabled - Enable shortcut - 1 + Enable + 0x1 - DOWN_STOP - Shortcut between DOWN event and STOP task + DONE + Enable or disable interrupt for event DONE 2 2 Disabled - Disable shortcut - 0 + Disable + 0x0 Enabled - Enable shortcut - 1 + Enable + 0x1 - UP_STOP - Shortcut between UP event and STOP task + RESULTDONE + Enable or disable interrupt for event RESULTDONE 3 3 Disabled - Disable shortcut - 0 + Disable + 0x0 Enabled - Enable shortcut - 1 + Enable + 0x1 - CROSS_STOP - Shortcut between CROSS event and STOP task + CALIBRATEDONE + Enable or disable interrupt for event CALIBRATEDONE 4 4 Disabled - Disable shortcut - 0 + Disable + 0x0 Enabled - Enable shortcut - 1 + Enable + 0x1 - - - - INTENSET - Enable interrupt - 0x304 - read-write - - READY - Write '1' to enable interrupt for READY event - 0 - 0 + STOPPED + Enable or disable interrupt for event STOPPED + 5 + 5 - read Disabled - Read: Disabled - 0 + Disable + 0x0 Enabled - Read: Enabled - 1 + Enable + 0x1 + + + CH0LIMITH + Enable or disable interrupt for event CH0LIMITH + 6 + 6 - write - Set + Disabled + Disable + 0x0 + + + Enabled Enable - 1 + 0x1 - DOWN - Write '1' to enable interrupt for DOWN event - 1 - 1 + CH0LIMITL + Enable or disable interrupt for event CH0LIMITL + 7 + 7 - read Disabled - Read: Disabled - 0 + Disable + 0x0 Enabled - Read: Enabled - 1 + Enable + 0x1 + + + CH1LIMITH + Enable or disable interrupt for event CH1LIMITH + 8 + 8 - write - Set + Disabled + Disable + 0x0 + + + Enabled Enable - 1 + 0x1 - UP - Write '1' to enable interrupt for UP event - 2 - 2 + CH1LIMITL + Enable or disable interrupt for event CH1LIMITL + 9 + 9 - read Disabled - Read: Disabled - 0 + Disable + 0x0 Enabled - Read: Enabled - 1 + Enable + 0x1 + + + CH2LIMITH + Enable or disable interrupt for event CH2LIMITH + 10 + 10 - write - Set + Disabled + Disable + 0x0 + + + Enabled Enable - 1 + 0x1 - CROSS - Write '1' to enable interrupt for CROSS event - 3 - 3 + CH2LIMITL + Enable or disable interrupt for event CH2LIMITL + 11 + 11 - read Disabled - Read: Disabled - 0 + Disable + 0x0 Enabled - Read: Enabled - 1 + Enable + 0x1 + + + CH3LIMITH + Enable or disable interrupt for event CH3LIMITH + 12 + 12 - write - Set + Disabled + Disable + 0x0 + + + Enabled Enable - 1 + 0x1 - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - READY - Write '1' to disable interrupt for READY event - 0 - 0 + CH3LIMITL + Enable or disable interrupt for event CH3LIMITL + 13 + 13 - read Disabled - Read: Disabled - 0 + Disable + 0x0 Enabled - Read: Enabled - 1 + Enable + 0x1 + + + CH4LIMITH + Enable or disable interrupt for event CH4LIMITH + 14 + 14 - write - Clear + Disabled Disable - 1 + 0x0 + + + Enabled + Enable + 0x1 - DOWN - Write '1' to disable interrupt for DOWN event - 1 - 1 + CH4LIMITL + Enable or disable interrupt for event CH4LIMITL + 15 + 15 - read Disabled - Read: Disabled - 0 + Disable + 0x0 Enabled - Read: Enabled - 1 + Enable + 0x1 + + + CH5LIMITH + Enable or disable interrupt for event CH5LIMITH + 16 + 16 - write - Clear + Disabled Disable - 1 + 0x0 + + + Enabled + Enable + 0x1 - UP - Write '1' to disable interrupt for UP event - 2 - 2 + CH5LIMITL + Enable or disable interrupt for event CH5LIMITL + 17 + 17 - read Disabled - Read: Disabled - 0 + Disable + 0x0 Enabled - Read: Enabled - 1 + Enable + 0x1 + + + CH6LIMITH + Enable or disable interrupt for event CH6LIMITH + 18 + 18 - write - Clear + Disabled Disable - 1 + 0x0 + + + Enabled + Enable + 0x1 - CROSS - Write '1' to disable interrupt for CROSS event - 3 - 3 + CH6LIMITL + Enable or disable interrupt for event CH6LIMITL + 19 + 19 - read Disabled - Read: Disabled - 0 + Disable + 0x0 Enabled - Read: Enabled - 1 + Enable + 0x1 + + + CH7LIMITH + Enable or disable interrupt for event CH7LIMITH + 20 + 20 - write - Clear + Disabled Disable - 1 - - - - - - - RESULT - Compare result - 0x400 - read-only - - - RESULT - Result of last compare. Decision point SAMPLE task. - 0 - 0 - - - Below - Input voltage is below the reference threshold (VIN+ &lt; VIN-). - 0 + 0x0 - Above - Input voltage is above the reference threshold (VIN+ &gt; VIN-). - 1 + Enabled + Enable + 0x1 - - - - ENABLE - Enable LPCOMP - 0x500 - read-write - - ENABLE - Enable or disable LPCOMP - 0 - 1 + CH7LIMITL + Enable or disable interrupt for event CH7LIMITL + 21 + 21 Disabled Disable - 0 + 0x0 Enabled Enable - 1 - - - - - - - PSEL - Input pin select - 0x504 - read-write - - - PSEL - Analog pin select - 0 - 2 - - - AnalogInput0 - AIN0 selected as analog input - 0 - - - AnalogInput1 - AIN1 selected as analog input - 1 - - - AnalogInput2 - AIN2 selected as analog input - 2 - - - AnalogInput3 - AIN3 selected as analog input - 3 - - - AnalogInput4 - AIN4 selected as analog input - 4 - - - AnalogInput5 - AIN5 selected as analog input - 5 - - - AnalogInput6 - AIN6 selected as analog input - 6 - - - AnalogInput7 - AIN7 selected as analog input - 7 - - - - - - - REFSEL - Reference select - 0x508 - read-write - 0x00000004 - - - REFSEL - Reference select - 0 - 3 - - - Ref1_8Vdd - VDD * 1/8 selected as reference - 0 - - - Ref2_8Vdd - VDD * 2/8 selected as reference - 1 - - - Ref3_8Vdd - VDD * 3/8 selected as reference - 2 - - - Ref4_8Vdd - VDD * 4/8 selected as reference - 3 - - - Ref5_8Vdd - VDD * 5/8 selected as reference - 4 - - - Ref6_8Vdd - VDD * 6/8 selected as reference - 5 - - - Ref7_8Vdd - VDD * 7/8 selected as reference - 6 - - - ARef - External analog reference selected - 7 - - - Ref1_16Vdd - VDD * 1/16 selected as reference - 8 - - - Ref3_16Vdd - VDD * 3/16 selected as reference - 9 - - - Ref5_16Vdd - VDD * 5/16 selected as reference - 10 - - - Ref7_16Vdd - VDD * 7/16 selected as reference - 11 - - - Ref9_16Vdd - VDD * 9/16 selected as reference - 12 - - - Ref11_16Vdd - VDD * 11/16 selected as reference - 13 - - - Ref13_16Vdd - VDD * 13/16 selected as reference - 14 - - - Ref15_16Vdd - VDD * 15/16 selected as reference - 15 + 0x1 - EXTREFSEL - External reference select - 0x50C + INTENSET + Enable interrupt + 0x304 read-write + 0x00000000 + 0x20 - EXTREFSEL - External analog reference select + STARTED + Write '1' to enable interrupt for event STARTED 0 0 + read - AnalogReference0 - Use AIN0 as external analog reference - 0 + Disabled + Read: Disabled + 0x0 - AnalogReference1 - Use AIN1 as external analog reference - 1 + Enabled + Read: Enabled + 0x1 - - - - - ANADETECT - Analog detect configuration - 0x520 - read-write - - - ANADETECT - Analog detect configuration - 0 - 1 + write - Cross - Generate ANADETECT on crossing, both upward crossing and downward crossing - 0 - - - Up - Generate ANADETECT on upward crossing only - 1 - - - Down - Generate ANADETECT on downward crossing only - 2 + Set + Enable + 0x1 - - - - HYST - Comparator hysteresis enable - 0x538 - read-write - - HYST - Comparator hysteresis enable - 0 - 0 + END + Write '1' to enable interrupt for event END + 1 + 1 + read Disabled - Comparator hysteresis disabled - 0 + Read: Disabled + 0x0 Enabled - Comparator hysteresis enabled - 1 + Read: Enabled + 0x1 - - - - - - - EGU0 - Event Generator Unit 0 - 0x40014000 - EGU - - 0 - 0x1000 - registers - - - SWI0_EGU0 - 20 - - EGU - 0x20 - - - 16 - 0x4 - TASKS_TRIGGER[%s] - Description collection[n]: Trigger n for triggering the corresponding TRIGGERED[n] event - 0x000 - write-only - - - TASKS_TRIGGER - 0 - 0 - - - - - 16 - 0x4 - EVENTS_TRIGGERED[%s] - Description collection[n]: Event number n generated by triggering the corresponding TRIGGER[n] task - 0x100 - read-write - - - EVENTS_TRIGGERED - 0 - 0 - - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - - TRIGGERED0 - Enable or disable interrupt for TRIGGERED[0] event - 0 - 0 + write - Disabled - Disable - 0 - - - Enabled + Set Enable - 1 + 0x1 - TRIGGERED1 - Enable or disable interrupt for TRIGGERED[1] event - 1 - 1 + DONE + Write '1' to enable interrupt for event DONE + 2 + 2 + read Disabled - Disable - 0 + Read: Disabled + 0x0 Enabled - Enable - 1 + Read: Enabled + 0x1 - - - TRIGGERED2 - Enable or disable interrupt for TRIGGERED[2] event - 2 - 2 + write - Disabled - Disable - 0 - - - Enabled + Set Enable - 1 + 0x1 - TRIGGERED3 - Enable or disable interrupt for TRIGGERED[3] event + RESULTDONE + Write '1' to enable interrupt for event RESULTDONE 3 3 + read Disabled - Disable - 0 + Read: Disabled + 0x0 Enabled + Read: Enabled + 0x1 + + + + write + + Set Enable - 1 + 0x1 - TRIGGERED4 - Enable or disable interrupt for TRIGGERED[4] event + CALIBRATEDONE + Write '1' to enable interrupt for event CALIBRATEDONE 4 4 + read Disabled - Disable - 0 + Read: Disabled + 0x0 Enabled + Read: Enabled + 0x1 + + + + write + + Set Enable - 1 + 0x1 - TRIGGERED5 - Enable or disable interrupt for TRIGGERED[5] event + STOPPED + Write '1' to enable interrupt for event STOPPED 5 5 + read Disabled - Disable - 0 + Read: Disabled + 0x0 Enabled + Read: Enabled + 0x1 + + + + write + + Set Enable - 1 + 0x1 - TRIGGERED6 - Enable or disable interrupt for TRIGGERED[6] event + CH0LIMITH + Write '1' to enable interrupt for event CH0LIMITH 6 6 + read Disabled - Disable - 0 + Read: Disabled + 0x0 Enabled + Read: Enabled + 0x1 + + + + write + + Set Enable - 1 + 0x1 - TRIGGERED7 - Enable or disable interrupt for TRIGGERED[7] event + CH0LIMITL + Write '1' to enable interrupt for event CH0LIMITL 7 7 + read Disabled - Disable - 0 + Read: Disabled + 0x0 Enabled + Read: Enabled + 0x1 + + + + write + + Set Enable - 1 + 0x1 - TRIGGERED8 - Enable or disable interrupt for TRIGGERED[8] event + CH1LIMITH + Write '1' to enable interrupt for event CH1LIMITH 8 8 + read Disabled - Disable - 0 + Read: Disabled + 0x0 Enabled + Read: Enabled + 0x1 + + + + write + + Set Enable - 1 + 0x1 - TRIGGERED9 - Enable or disable interrupt for TRIGGERED[9] event + CH1LIMITL + Write '1' to enable interrupt for event CH1LIMITL 9 9 + read Disabled - Disable - 0 + Read: Disabled + 0x0 Enabled + Read: Enabled + 0x1 + + + + write + + Set Enable - 1 + 0x1 - TRIGGERED10 - Enable or disable interrupt for TRIGGERED[10] event + CH2LIMITH + Write '1' to enable interrupt for event CH2LIMITH 10 10 + read Disabled - Disable - 0 + Read: Disabled + 0x0 Enabled + Read: Enabled + 0x1 + + + + write + + Set Enable - 1 + 0x1 - TRIGGERED11 - Enable or disable interrupt for TRIGGERED[11] event + CH2LIMITL + Write '1' to enable interrupt for event CH2LIMITL 11 11 + read Disabled - Disable - 0 + Read: Disabled + 0x0 Enabled + Read: Enabled + 0x1 + + + + write + + Set Enable - 1 + 0x1 - TRIGGERED12 - Enable or disable interrupt for TRIGGERED[12] event + CH3LIMITH + Write '1' to enable interrupt for event CH3LIMITH 12 12 + read Disabled - Disable - 0 + Read: Disabled + 0x0 Enabled + Read: Enabled + 0x1 + + + + write + + Set Enable - 1 + 0x1 - TRIGGERED13 - Enable or disable interrupt for TRIGGERED[13] event + CH3LIMITL + Write '1' to enable interrupt for event CH3LIMITL 13 13 + read Disabled - Disable - 0 + Read: Disabled + 0x0 Enabled + Read: Enabled + 0x1 + + + + write + + Set Enable - 1 + 0x1 - TRIGGERED14 - Enable or disable interrupt for TRIGGERED[14] event + CH4LIMITH + Write '1' to enable interrupt for event CH4LIMITH 14 14 + read Disabled - Disable - 0 + Read: Disabled + 0x0 Enabled - Enable - 1 + Read: Enabled + 0x1 - - - TRIGGERED15 - Enable or disable interrupt for TRIGGERED[15] event - 15 - 15 + write - Disabled - Disable - 0 - - - Enabled + Set Enable - 1 + 0x1 - - - - INTENSET - Enable interrupt - 0x304 - read-write - - TRIGGERED0 - Write '1' to enable interrupt for TRIGGERED[0] event - 0 - 0 + CH4LIMITL + Write '1' to enable interrupt for event CH4LIMITL + 15 + 15 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -28003,26 +28860,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - TRIGGERED1 - Write '1' to enable interrupt for TRIGGERED[1] event - 1 - 1 + CH5LIMITH + Write '1' to enable interrupt for event CH5LIMITH + 16 + 16 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -28030,107 +28887,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - TRIGGERED2 - Write '1' to enable interrupt for TRIGGERED[2] event - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TRIGGERED3 - Write '1' to enable interrupt for TRIGGERED[3] event - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TRIGGERED4 - Write '1' to enable interrupt for TRIGGERED[4] event - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TRIGGERED5 - Write '1' to enable interrupt for TRIGGERED[5] event - 5 - 5 + CH5LIMITL + Write '1' to enable interrupt for event CH5LIMITL + 17 + 17 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -28138,26 +28914,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - TRIGGERED6 - Write '1' to enable interrupt for TRIGGERED[6] event - 6 - 6 + CH6LIMITH + Write '1' to enable interrupt for event CH6LIMITH + 18 + 18 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -28165,26 +28941,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - TRIGGERED7 - Write '1' to enable interrupt for TRIGGERED[7] event - 7 - 7 + CH6LIMITL + Write '1' to enable interrupt for event CH6LIMITL + 19 + 19 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -28192,26 +28968,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - TRIGGERED8 - Write '1' to enable interrupt for TRIGGERED[8] event - 8 - 8 + CH7LIMITH + Write '1' to enable interrupt for event CH7LIMITH + 20 + 20 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -28219,26 +28995,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - TRIGGERED9 - Write '1' to enable interrupt for TRIGGERED[9] event - 9 - 9 + CH7LIMITL + Write '1' to enable interrupt for event CH7LIMITL + 21 + 21 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -28246,196 +29022,198 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + - TRIGGERED10 - Write '1' to enable interrupt for TRIGGERED[10] event - 10 - 10 + STARTED + Write '1' to disable interrupt for event STARTED + 0 + 0 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Set - Enable - 1 + Clear + Disable + 0x1 - TRIGGERED11 - Write '1' to enable interrupt for TRIGGERED[11] event - 11 - 11 + END + Write '1' to disable interrupt for event END + 1 + 1 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Set - Enable - 1 + Clear + Disable + 0x1 - TRIGGERED12 - Write '1' to enable interrupt for TRIGGERED[12] event - 12 - 12 + DONE + Write '1' to disable interrupt for event DONE + 2 + 2 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Set - Enable - 1 + Clear + Disable + 0x1 - TRIGGERED13 - Write '1' to enable interrupt for TRIGGERED[13] event - 13 - 13 + RESULTDONE + Write '1' to disable interrupt for event RESULTDONE + 3 + 3 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Set - Enable - 1 + Clear + Disable + 0x1 - TRIGGERED14 - Write '1' to enable interrupt for TRIGGERED[14] event - 14 - 14 + CALIBRATEDONE + Write '1' to disable interrupt for event CALIBRATEDONE + 4 + 4 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Set - Enable - 1 + Clear + Disable + 0x1 - TRIGGERED15 - Write '1' to enable interrupt for TRIGGERED[15] event - 15 - 15 + STOPPED + Write '1' to disable interrupt for event STOPPED + 5 + 5 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Set - Enable - 1 + Clear + Disable + 0x1 - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - TRIGGERED0 - Write '1' to disable interrupt for TRIGGERED[0] event - 0 - 0 + CH0LIMITH + Write '1' to disable interrupt for event CH0LIMITH + 6 + 6 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -28443,26 +29221,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - TRIGGERED1 - Write '1' to disable interrupt for TRIGGERED[1] event - 1 - 1 + CH0LIMITL + Write '1' to disable interrupt for event CH0LIMITL + 7 + 7 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -28470,26 +29248,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - TRIGGERED2 - Write '1' to disable interrupt for TRIGGERED[2] event - 2 - 2 + CH1LIMITH + Write '1' to disable interrupt for event CH1LIMITH + 8 + 8 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -28497,26 +29275,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - TRIGGERED3 - Write '1' to disable interrupt for TRIGGERED[3] event - 3 - 3 + CH1LIMITL + Write '1' to disable interrupt for event CH1LIMITL + 9 + 9 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -28524,26 +29302,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - TRIGGERED4 - Write '1' to disable interrupt for TRIGGERED[4] event - 4 - 4 + CH2LIMITH + Write '1' to disable interrupt for event CH2LIMITH + 10 + 10 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -28551,26 +29329,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - TRIGGERED5 - Write '1' to disable interrupt for TRIGGERED[5] event - 5 - 5 + CH2LIMITL + Write '1' to disable interrupt for event CH2LIMITL + 11 + 11 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -28578,26 +29356,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - TRIGGERED6 - Write '1' to disable interrupt for TRIGGERED[6] event - 6 - 6 + CH3LIMITH + Write '1' to disable interrupt for event CH3LIMITH + 12 + 12 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -28605,26 +29383,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - TRIGGERED7 - Write '1' to disable interrupt for TRIGGERED[7] event - 7 - 7 + CH3LIMITL + Write '1' to disable interrupt for event CH3LIMITL + 13 + 13 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -28632,26 +29410,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - TRIGGERED8 - Write '1' to disable interrupt for TRIGGERED[8] event - 8 - 8 + CH4LIMITH + Write '1' to disable interrupt for event CH4LIMITH + 14 + 14 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -28659,26 +29437,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - TRIGGERED9 - Write '1' to disable interrupt for TRIGGERED[9] event - 9 - 9 + CH4LIMITL + Write '1' to disable interrupt for event CH4LIMITL + 15 + 15 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -28686,26 +29464,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - TRIGGERED10 - Write '1' to disable interrupt for TRIGGERED[10] event - 10 - 10 + CH5LIMITH + Write '1' to disable interrupt for event CH5LIMITH + 16 + 16 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -28713,26 +29491,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - TRIGGERED11 - Write '1' to disable interrupt for TRIGGERED[11] event - 11 - 11 + CH5LIMITL + Write '1' to disable interrupt for event CH5LIMITL + 17 + 17 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -28740,26 +29518,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - TRIGGERED12 - Write '1' to disable interrupt for TRIGGERED[12] event - 12 - 12 + CH6LIMITH + Write '1' to disable interrupt for event CH6LIMITH + 18 + 18 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -28767,26 +29545,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - TRIGGERED13 - Write '1' to disable interrupt for TRIGGERED[13] event - 13 - 13 + CH6LIMITL + Write '1' to disable interrupt for event CH6LIMITL + 19 + 19 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -28794,26 +29572,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - TRIGGERED14 - Write '1' to disable interrupt for TRIGGERED[14] event - 14 - 14 + CH7LIMITH + Write '1' to disable interrupt for event CH7LIMITH + 20 + 20 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -28821,26 +29599,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - TRIGGERED15 - Write '1' to disable interrupt for TRIGGERED[15] event - 15 - 15 + CH7LIMITL + Write '1' to disable interrupt for event CH7LIMITL + 21 + 21 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -28848,466 +29626,1051 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - - - - SWI0 - Software interrupt 0 - 0x40014000 - EGU0 - SWI - - 0 - 0x1000 - registers - - - SWI0_EGU0 - 20 - - SWI - 0x20 - - UNUSED - Unused. - 0x000 - 0x00000000 + STATUS + Status + 0x400 read-only - - - - - EGU1 - Event Generator Unit 1 - 0x40015000 - - SWI1_EGU1 - 21 - - - - SWI1 - Software interrupt 1 - 0x40015000 - EGU1 - - SWI1_EGU1 - 21 - - - - EGU2 - Event Generator Unit 2 - 0x40016000 - - SWI2_EGU2 - 22 - - - - SWI2 - Software interrupt 2 - 0x40016000 - EGU2 - - SWI2_EGU2 - 22 - - - - EGU3 - Event Generator Unit 3 - 0x40017000 - - SWI3_EGU3 - 23 - - - - SWI3 - Software interrupt 3 - 0x40017000 - EGU3 - - SWI3_EGU3 - 23 - - - - EGU4 - Event Generator Unit 4 - 0x40018000 - - SWI4_EGU4 - 24 - - - - SWI4 - Software interrupt 4 - 0x40018000 - EGU4 - - SWI4_EGU4 - 24 - - - - EGU5 - Event Generator Unit 5 - 0x40019000 - - SWI5_EGU5 - 25 - - - - SWI5 - Software interrupt 5 - 0x40019000 - EGU5 - - SWI5_EGU5 - 25 - - - - TIMER3 - Timer/Counter 3 - TIMER - 0x4001A000 - 0x20 - - 0 - 0x1000 - registers - - - TIMER3 - 26 - - - - TASKS_START - Start Timer - 0x000 - write-only - - - TASKS_START - 0 - 0 - - - - - TASKS_STOP - Stop Timer - 0x004 - write-only - - - TASKS_STOP - 0 - 0 - - - - - TASKS_COUNT - Increment Timer (Counter mode only) - 0x008 - write-only - - - TASKS_COUNT - 0 - 0 - - - - - TASKS_CLEAR - Clear time - 0x00C - write-only + 0x00000000 + 0x20 - TASKS_CLEAR + STATUS + Status 0 0 + + + Ready + SAADC is ready. No on-going conversions. + 0x0 + + + Busy + SAADC is busy. Conversion in progress. + 0x1 + + - TASKS_SHUTDOWN - Deprecated register - Shut down timer - 0x010 - write-only + ENABLE + Enable or disable SAADC + 0x500 + read-write + 0x00000000 + 0x20 - TASKS_SHUTDOWN + ENABLE + Enable or disable SAADC 0 0 + + + Disabled + Disable SAADC + 0x0 + + + Enabled + Enable SAADC + 0x1 + + - - 6 - 0x4 - TASKS_CAPTURE[%s] - Description collection[n]: Capture Timer value to CC[n] register - 0x040 - write-only - - - TASKS_CAPTURE - 0 - 0 - - - - - 6 - 0x4 - EVENTS_COMPARE[%s] - Description collection[n]: Compare event on CC[n] match - 0x140 + + 8 + 0x010 + CH[%s] + Unspecified + SAADC_CH read-write - - - EVENTS_COMPARE - 0 - 0 - - - + 0x510 + + PSELP + Description cluster: Input positive pin selection for CH[n] + 0x000 + read-write + 0x00000000 + 0x20 + + + PSELP + Analog positive input channel + 0 + 4 + + + NC + Not connected + 0x00 + + + AnalogInput0 + AIN0 + 0x01 + + + AnalogInput1 + AIN1 + 0x02 + + + AnalogInput2 + AIN2 + 0x03 + + + AnalogInput3 + AIN3 + 0x04 + + + AnalogInput4 + AIN4 + 0x05 + + + AnalogInput5 + AIN5 + 0x06 + + + AnalogInput6 + AIN6 + 0x07 + + + AnalogInput7 + AIN7 + 0x08 + + + VDD + VDD + 0x09 + + + VDDHDIV5 + VDDH/5 + 0x0D + + + + + + + PSELN + Description cluster: Input negative pin selection for CH[n] + 0x004 + read-write + 0x00000000 + 0x20 + + + PSELN + Analog negative input, enables differential channel + 0 + 4 + + + NC + Not connected + 0x00 + + + AnalogInput0 + AIN0 + 0x01 + + + AnalogInput1 + AIN1 + 0x02 + + + AnalogInput2 + AIN2 + 0x03 + + + AnalogInput3 + AIN3 + 0x04 + + + AnalogInput4 + AIN4 + 0x05 + + + AnalogInput5 + AIN5 + 0x06 + + + AnalogInput6 + AIN6 + 0x07 + + + AnalogInput7 + AIN7 + 0x08 + + + VDD + VDD + 0x09 + + + VDDHDIV5 + VDDH/5 + 0x0D + + + + + + + CONFIG + Description cluster: Input configuration for CH[n] + 0x008 + read-write + 0x00020000 + 0x20 + + + RESP + Positive channel resistor control + 0 + 1 + + + Bypass + Bypass resistor ladder + 0x0 + + + Pulldown + Pull-down to GND + 0x1 + + + Pullup + Pull-up to VDD + 0x2 + + + VDD1_2 + Set input at VDD/2 + 0x3 + + + + + RESN + Negative channel resistor control + 4 + 5 + + + Bypass + Bypass resistor ladder + 0x0 + + + Pulldown + Pull-down to GND + 0x1 + + + Pullup + Pull-up to VDD + 0x2 + + + VDD1_2 + Set input at VDD/2 + 0x3 + + + + + GAIN + Gain control + 8 + 10 + + + Gain1_6 + 1/6 + 0x0 + + + Gain1_5 + 1/5 + 0x1 + + + Gain1_4 + 1/4 + 0x2 + + + Gain1_3 + 1/3 + 0x3 + + + Gain1_2 + 1/2 + 0x4 + + + Gain1 + 1 + 0x5 + + + Gain2 + 2 + 0x6 + + + Gain4 + 4 + 0x7 + + + + + REFSEL + Reference control + 12 + 12 + + + Internal + Internal reference (0.6 V) + 0x0 + + + VDD1_4 + VDD/4 as reference + 0x1 + + + + + TACQ + Acquisition time, the time the SAADC uses to sample the input voltage + 16 + 18 + + + 3us + 3 us + 0x0 + + + 5us + 5 us + 0x1 + + + 10us + 10 us + 0x2 + + + 15us + 15 us + 0x3 + + + 20us + 20 us + 0x4 + + + 40us + 40 us + 0x5 + + + + + MODE + Enable differential mode + 20 + 20 + + + SE + Single-ended, PSELN will be ignored, negative input to SAADC shorted to GND + 0x0 + + + Diff + Differential + 0x1 + + + + + BURST + Enable burst mode + 24 + 24 + + + Disabled + Burst mode is disabled (normal operation) + 0x0 + + + Enabled + Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. + 0x1 + + + + + + + LIMIT + Description cluster: High/low limits for event monitoring of a channel + 0x00C + read-write + 0x7FFF8000 + 0x20 + + + LOW + Low level limit + 0 + 15 + + + HIGH + High level limit + 16 + 31 + + + + - SHORTS - Shortcut register - 0x200 + RESOLUTION + Resolution configuration + 0x5F0 read-write + 0x00000001 + 0x20 - COMPARE0_CLEAR - Shortcut between COMPARE[0] event and CLEAR task + VAL + Set the resolution 0 - 0 + 2 - Disabled - Disable shortcut - 0 + 8bit + 8 bits + 0x0 - Enabled - Enable shortcut - 1 + 10bit + 10 bits + 0x1 - - - - COMPARE1_CLEAR - Shortcut between COMPARE[1] event and CLEAR task - 1 - 1 - - Disabled - Disable shortcut - 0 + 12bit + 12 bits + 0x2 - Enabled - Enable shortcut - 1 + 14bit + 14 bits + 0x3 + + + + OVERSAMPLE + Oversampling configuration. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. + 0x5F4 + read-write + 0x00000000 + 0x20 + - COMPARE2_CLEAR - Shortcut between COMPARE[2] event and CLEAR task - 2 - 2 + OVERSAMPLE + Oversample control + 0 + 3 - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 + Bypass + Bypass oversampling + 0x0 - - - - COMPARE3_CLEAR - Shortcut between COMPARE[3] event and CLEAR task - 3 - 3 - - Disabled - Disable shortcut - 0 + Over2x + Oversample 2x + 0x1 - Enabled - Enable shortcut - 1 + Over4x + Oversample 4x + 0x2 - - - - COMPARE4_CLEAR - Shortcut between COMPARE[4] event and CLEAR task - 4 - 4 - - Disabled - Disable shortcut - 0 + Over8x + Oversample 8x + 0x3 - Enabled - Enable shortcut - 1 + Over16x + Oversample 16x + 0x4 - - - - COMPARE5_CLEAR - Shortcut between COMPARE[5] event and CLEAR task - 5 - 5 - - Disabled - Disable shortcut - 0 + Over32x + Oversample 32x + 0x5 - Enabled - Enable shortcut - 1 + Over64x + Oversample 64x + 0x6 - - - - COMPARE0_STOP - Shortcut between COMPARE[0] event and STOP task - 8 - 8 - - Disabled - Disable shortcut - 0 + Over128x + Oversample 128x + 0x7 - Enabled - Enable shortcut - 1 + Over256x + Oversample 256x + 0x8 + + + + SAMPLERATE + Controls normal or continuous sample rate + 0x5F8 + read-write + 0x00000000 + 0x20 + + + CC + Capture and compare value. Sample rate is 16 MHz/CC + 0 + 10 + - COMPARE1_STOP - Shortcut between COMPARE[1] event and STOP task - 9 - 9 + MODE + Select mode for sample rate control + 12 + 12 - Disabled - Disable shortcut - 0 + Task + Rate is controlled from SAMPLE task + 0x0 - Enabled - Enable shortcut - 1 + Timers + Rate is controlled from local timer (use CC to control the rate) + 0x1 - - COMPARE2_STOP - Shortcut between COMPARE[2] event and STOP task - 10 - 10 - - - Disabled - Disable shortcut - 0 - + + + + RESULT + RESULT EasyDMA channel + SAADC_RESULT + read-write + 0x62C + + PTR + Data pointer + 0x000 + read-write + 0x00000000 + 0x20 + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of 16-bit samples to be written to output RAM buffer + 0x004 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of 16-bit samples to be written to output RAM buffer + 0 + 14 + + + + + AMOUNT + Number of 16-bit samples written to output RAM buffer since the previous START task + 0x008 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of 16-bit samples written to output RAM buffer since the previous START task. This register can be read after an END or STOPPED event. + 0 + 14 + + + + + + + + TIMER0 + Timer/Counter 0 + 0x40008000 + TIMER + + 0 + 0x1000 + registers + + + TIMER0 + 8 + + TIMER + 0x20 + + + TASKS_START + Start Timer + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start Timer + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop Timer + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop Timer + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_COUNT + Increment Timer (Counter mode only) + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_COUNT + Increment Timer (Counter mode only) + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_CLEAR + Clear time + 0x00C + write-only + 0x00000000 + 0x20 + + + TASKS_CLEAR + Clear time + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_SHUTDOWN + Deprecated register - Shut down timer + 0x010 + write-only + 0x00000000 + 0x20 + + + TASKS_SHUTDOWN + Deprecated field - Shut down timer + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x6 + 0x4 + TASKS_CAPTURE[%s] + Description collection: Capture Timer value to CC[n] register + 0x040 + write-only + 0x00000000 + 0x20 + + + TASKS_CAPTURE + Capture Timer value to CC[n] register + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x6 + 0x4 + EVENTS_COMPARE[%s] + Description collection: Compare event on CC[n] match + 0x140 + read-write + 0x00000000 + 0x20 + + + EVENTS_COMPARE + Compare event on CC[n] match + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + COMPARE0_CLEAR + Shortcut between event COMPARE[0] and task CLEAR + 0 + 0 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE1_CLEAR + Shortcut between event COMPARE[1] and task CLEAR + 1 + 1 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE2_CLEAR + Shortcut between event COMPARE[2] and task CLEAR + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE3_CLEAR + Shortcut between event COMPARE[3] and task CLEAR + 3 + 3 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE4_CLEAR + Shortcut between event COMPARE[4] and task CLEAR + 4 + 4 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE5_CLEAR + Shortcut between event COMPARE[5] and task CLEAR + 5 + 5 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE0_STOP + Shortcut between event COMPARE[0] and task STOP + 8 + 8 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE1_STOP + Shortcut between event COMPARE[1] and task STOP + 9 + 9 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE2_STOP + Shortcut between event COMPARE[2] and task STOP + 10 + 10 + + + Disabled + Disable shortcut + 0x0 + Enabled Enable shortcut - 1 + 0x1 COMPARE3_STOP - Shortcut between COMPARE[3] event and STOP task + Shortcut between event COMPARE[3] and task STOP 11 11 Disabled Disable shortcut - 0 + 0x0 Enabled Enable shortcut - 1 + 0x1 COMPARE4_STOP - Shortcut between COMPARE[4] event and STOP task + Shortcut between event COMPARE[4] and task STOP 12 12 Disabled Disable shortcut - 0 + 0x0 Enabled Enable shortcut - 1 + 0x1 COMPARE5_STOP - Shortcut between COMPARE[5] event and STOP task + Shortcut between event COMPARE[5] and task STOP 13 13 Disabled Disable shortcut - 0 + 0x0 Enabled Enable shortcut - 1 + 0x1 @@ -29318,10 +30681,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Enable interrupt 0x304 read-write + 0x00000000 + 0x20 COMPARE0 - Write '1' to enable interrupt for COMPARE[0] event + Write '1' to enable interrupt for event COMPARE[0] 16 16 @@ -29329,12 +30694,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -29342,13 +30707,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 COMPARE1 - Write '1' to enable interrupt for COMPARE[1] event + Write '1' to enable interrupt for event COMPARE[1] 17 17 @@ -29356,12 +30721,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -29369,13 +30734,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 COMPARE2 - Write '1' to enable interrupt for COMPARE[2] event + Write '1' to enable interrupt for event COMPARE[2] 18 18 @@ -29383,12 +30748,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -29396,13 +30761,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 COMPARE3 - Write '1' to enable interrupt for COMPARE[3] event + Write '1' to enable interrupt for event COMPARE[3] 19 19 @@ -29410,12 +30775,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -29423,13 +30788,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 COMPARE4 - Write '1' to enable interrupt for COMPARE[4] event + Write '1' to enable interrupt for event COMPARE[4] 20 20 @@ -29437,12 +30802,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -29450,13 +30815,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 COMPARE5 - Write '1' to enable interrupt for COMPARE[5] event + Write '1' to enable interrupt for event COMPARE[5] 21 21 @@ -29464,12 +30829,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -29477,7 +30842,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 @@ -29488,10 +30853,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disable interrupt 0x308 read-write + 0x00000000 + 0x20 COMPARE0 - Write '1' to disable interrupt for COMPARE[0] event + Write '1' to disable interrupt for event COMPARE[0] 16 16 @@ -29499,12 +30866,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -29512,13 +30879,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 COMPARE1 - Write '1' to disable interrupt for COMPARE[1] event + Write '1' to disable interrupt for event COMPARE[1] 17 17 @@ -29526,12 +30893,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -29539,13 +30906,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 COMPARE2 - Write '1' to disable interrupt for COMPARE[2] event + Write '1' to disable interrupt for event COMPARE[2] 18 18 @@ -29553,12 +30920,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -29566,13 +30933,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 COMPARE3 - Write '1' to disable interrupt for COMPARE[3] event + Write '1' to disable interrupt for event COMPARE[3] 19 19 @@ -29580,12 +30947,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -29593,13 +30960,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 COMPARE4 - Write '1' to disable interrupt for COMPARE[4] event + Write '1' to disable interrupt for event COMPARE[4] 20 20 @@ -29607,12 +30974,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -29620,13 +30987,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 COMPARE5 - Write '1' to disable interrupt for COMPARE[5] event + Write '1' to disable interrupt for event COMPARE[5] 21 21 @@ -29634,12 +31001,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -29647,7 +31014,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 @@ -29658,6 +31025,8 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Timer mode selection 0x504 read-write + 0x00000000 + 0x20 MODE @@ -29668,17 +31037,17 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Timer Select Timer mode - 0 + 0x0 Counter Deprecated enumerator - Select Counter mode - 1 + 0x1 LowPowerCounter Select Low Power Counter mode - 2 + 0x2 @@ -29689,6 +31058,8 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Configure the number of bits used by the TIMER 0x508 read-write + 0x00000000 + 0x20 BITMODE @@ -29699,22 +31070,22 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ 16Bit 16 bit timer bit width - 0 + 0x0 08Bit 8 bit timer bit width - 1 + 0x1 24Bit 24 bit timer bit width - 2 + 0x2 32Bit 32 bit timer bit width - 3 + 0x3 @@ -29726,6 +31097,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ 0x510 read-write 0x00000004 + 0x20 PRESCALER @@ -29736,12 +31108,14 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ - 6 + 0x6 0x4 CC[%s] - Description collection[n]: Capture/Compare register n + Description collection: Capture/Compare register n 0x540 read-write + 0x00000000 + 0x20 CC @@ -29753,450 +31127,705 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ - - TIMER4 - Timer/Counter 4 - 0x4001B000 + + TIMER1 + Timer/Counter 1 + 0x40009000 - TIMER4 - 27 + TIMER1 + 9 + + + + TIMER2 + Timer/Counter 2 + 0x4000A000 + + TIMER2 + 10 - PWM0 - Pulse width modulation unit 0 - 0x4001C000 - PWM + RTC0 + Real time counter 0 + 0x4000B000 + RTC 0 0x1000 registers - PWM0 - 28 + RTC0 + 11 - PWM + RTC 0x20 - TASKS_STOP - Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback - 0x004 + TASKS_START + Start RTC COUNTER + 0x000 write-only + 0x00000000 + 0x20 - TASKS_STOP + TASKS_START + Start RTC COUNTER 0 0 + + + Trigger + Trigger task + 0x1 + + - 2 - 0x4 - TASKS_SEQSTART[%s] - Description collection[n]: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. - 0x008 + TASKS_STOP + Stop RTC COUNTER + 0x004 write-only + 0x00000000 + 0x20 - TASKS_SEQSTART + TASKS_STOP + Stop RTC COUNTER 0 0 + + + Trigger + Trigger task + 0x1 + + - TASKS_NEXTSTEP - Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. - 0x010 + TASKS_CLEAR + Clear RTC COUNTER + 0x008 write-only + 0x00000000 + 0x20 - TASKS_NEXTSTEP + TASKS_CLEAR + Clear RTC COUNTER 0 0 + + + Trigger + Trigger task + 0x1 + + - EVENTS_STOPPED - Response to STOP task, emitted when PWM pulses are no longer generated - 0x104 - read-write + TASKS_TRIGOVRFLW + Set COUNTER to 0xFFFFF0 + 0x00C + write-only + 0x00000000 + 0x20 - EVENTS_STOPPED + TASKS_TRIGOVRFLW + Set COUNTER to 0xFFFFF0 0 0 + + + Trigger + Trigger task + 0x1 + + - 2 - 0x4 - EVENTS_SEQSTARTED[%s] - Description collection[n]: First PWM period started on sequence n - 0x108 + EVENTS_TICK + Event on COUNTER increment + 0x100 read-write + 0x00000000 + 0x20 - EVENTS_SEQSTARTED + EVENTS_TICK + Event on COUNTER increment 0 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + - 2 - 0x4 - EVENTS_SEQEND[%s] - Description collection[n]: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter - 0x110 + EVENTS_OVRFLW + Event on COUNTER overflow + 0x104 read-write + 0x00000000 + 0x20 - EVENTS_SEQEND + EVENTS_OVRFLW + Event on COUNTER overflow 0 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + - EVENTS_PWMPERIODEND - Emitted at the end of each PWM period - 0x118 + 0x4 + 0x4 + EVENTS_COMPARE[%s] + Description collection: Compare event on CC[n] match + 0x140 read-write + 0x00000000 + 0x20 - EVENTS_PWMPERIODEND + EVENTS_COMPARE + Compare event on CC[n] match 0 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + - EVENTS_LOOPSDONE - Concatenated sequences have been played the amount of times defined in LOOP.CNT - 0x11C - read-write - - - EVENTS_LOOPSDONE - 0 - 0 - - - - - SHORTS - Shortcut register - 0x200 + INTENSET + Enable interrupt + 0x304 read-write + 0x00000000 + 0x20 - SEQEND0_STOP - Shortcut between SEQEND[0] event and STOP task + TICK + Write '1' to enable interrupt for event TICK 0 0 + read Disabled - Disable shortcut - 0 + Read: Disabled + 0x0 Enabled - Enable shortcut - 1 + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 - SEQEND1_STOP - Shortcut between SEQEND[1] event and STOP task + OVRFLW + Write '1' to enable interrupt for event OVRFLW 1 1 + read Disabled - Disable shortcut - 0 + Read: Disabled + 0x0 Enabled - Enable shortcut - 1 + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 - LOOPSDONE_SEQSTART0 - Shortcut between LOOPSDONE event and SEQSTART[0] task - 2 - 2 + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 16 + 16 + read Disabled - Disable shortcut - 0 + Read: Disabled + 0x0 Enabled - Enable shortcut - 1 + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 - LOOPSDONE_SEQSTART1 - Shortcut between LOOPSDONE event and SEQSTART[1] task - 3 - 3 + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 17 + 17 + read Disabled - Disable shortcut - 0 + Read: Disabled + 0x0 Enabled - Enable shortcut - 1 + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 - LOOPSDONE_STOP - Shortcut between LOOPSDONE event and STOP task - 4 - 4 + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 18 + 18 + read Disabled - Disable shortcut - 0 + Read: Disabled + 0x0 Enabled - Enable shortcut - 1 + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 - INTEN - Enable or disable interrupt - 0x300 + INTENCLR + Disable interrupt + 0x308 read-write + 0x00000000 + 0x20 - STOPPED - Enable or disable interrupt for STOPPED event + TICK + Write '1' to disable interrupt for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + OVRFLW + Write '1' to disable interrupt for event OVRFLW 1 1 + read Disabled - Disable - 0 + Read: Disabled + 0x0 Enabled - Enable - 1 + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 - SEQSTARTED0 - Enable or disable interrupt for SEQSTARTED[0] event - 2 - 2 + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 16 + 16 + read Disabled - Disable - 0 + Read: Disabled + 0x0 Enabled - Enable - 1 + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 - SEQSTARTED1 - Enable or disable interrupt for SEQSTARTED[1] event - 3 - 3 + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 17 + 17 + read Disabled - Disable - 0 + Read: Disabled + 0x0 Enabled - Enable - 1 + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 - SEQEND0 - Enable or disable interrupt for SEQEND[0] event - 4 - 4 + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 18 + 18 + read Disabled - Disable - 0 + Read: Disabled + 0x0 Enabled - Enable - 1 + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 - SEQEND1 - Enable or disable interrupt for SEQEND[1] event - 5 - 5 + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 19 + 19 + read Disabled - Disable - 0 + Read: Disabled + 0x0 Enabled - Enable - 1 + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + EVTEN + Enable or disable event routing + 0x340 + read-write + 0x00000000 + 0x20 + - PWMPERIODEND - Enable or disable interrupt for PWMPERIODEND event - 6 - 6 + TICK + Enable or disable event routing for event TICK + 0 + 0 Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 - LOOPSDONE - Enable or disable interrupt for LOOPSDONE event - 7 - 7 + OVRFLW + Enable or disable event routing for event OVRFLW + 1 + 1 Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 - - - - INTENSET - Enable interrupt - 0x304 - read-write - - STOPPED - Write '1' to enable interrupt for STOPPED event - 1 - 1 + COMPARE0 + Enable or disable event routing for event COMPARE[0] + 16 + 16 - read Disabled - Read: Disabled - 0 + Disable + 0x0 Enabled - Read: Enabled - 1 + Enable + 0x1 + + + COMPARE1 + Enable or disable event routing for event COMPARE[1] + 17 + 17 - write - Set + Disabled + Disable + 0x0 + + + Enabled Enable - 1 + 0x1 - SEQSTARTED0 - Write '1' to enable interrupt for SEQSTARTED[0] event - 2 - 2 + COMPARE2 + Enable or disable event routing for event COMPARE[2] + 18 + 18 - read Disabled - Read: Disabled - 0 + Disable + 0x0 Enabled - Read: Enabled - 1 + Enable + 0x1 + + + COMPARE3 + Enable or disable event routing for event COMPARE[3] + 19 + 19 - write - Set + Disabled + Disable + 0x0 + + + Enabled Enable - 1 + 0x1 + + + + EVTENSET + Enable event routing + 0x344 + read-write + 0x00000000 + 0x20 + - SEQSTARTED1 - Write '1' to enable interrupt for SEQSTARTED[1] event - 3 - 3 + TICK + Write '1' to enable event routing for event TICK + 0 + 0 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -30204,26 +31833,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - SEQEND0 - Write '1' to enable interrupt for SEQEND[0] event - 4 - 4 + OVRFLW + Write '1' to enable event routing for event OVRFLW + 1 + 1 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -30231,26 +31860,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - SEQEND1 - Write '1' to enable interrupt for SEQEND[1] event - 5 - 5 + COMPARE0 + Write '1' to enable event routing for event COMPARE[0] + 16 + 16 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -30258,26 +31887,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - PWMPERIODEND - Write '1' to enable interrupt for PWMPERIODEND event - 6 - 6 + COMPARE1 + Write '1' to enable event routing for event COMPARE[1] + 17 + 17 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -30285,26 +31914,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - LOOPSDONE - Write '1' to enable interrupt for LOOPSDONE event - 7 - 7 + COMPARE2 + Write '1' to enable event routing for event COMPARE[2] + 18 + 18 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -30312,61 +31941,63 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - STOPPED - Write '1' to disable interrupt for STOPPED event - 1 - 1 + COMPARE3 + Write '1' to enable event routing for event COMPARE[3] + 19 + 19 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Clear - Disable - 1 + Set + Enable + 0x1 + + + + EVTENCLR + Disable event routing + 0x348 + read-write + 0x00000000 + 0x20 + - SEQSTARTED0 - Write '1' to disable interrupt for SEQSTARTED[0] event - 2 - 2 + TICK + Write '1' to disable event routing for event TICK + 0 + 0 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -30374,26 +32005,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - SEQSTARTED1 - Write '1' to disable interrupt for SEQSTARTED[1] event - 3 - 3 + OVRFLW + Write '1' to disable event routing for event OVRFLW + 1 + 1 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -30401,26 +32032,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - SEQEND0 - Write '1' to disable interrupt for SEQEND[0] event - 4 - 4 + COMPARE0 + Write '1' to disable event routing for event COMPARE[0] + 16 + 16 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -30428,26 +32059,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - SEQEND1 - Write '1' to disable interrupt for SEQEND[1] event - 5 - 5 + COMPARE1 + Write '1' to disable event routing for event COMPARE[1] + 17 + 17 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -30455,26 +32086,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - PWMPERIODEND - Write '1' to disable interrupt for PWMPERIODEND event - 6 - 6 + COMPARE2 + Write '1' to disable event routing for event COMPARE[2] + 18 + 18 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -30482,26 +32113,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - LOOPSDONE - Write '1' to disable interrupt for LOOPSDONE event - 7 - 7 + COMPARE3 + Write '1' to disable event routing for event COMPARE[3] + 19 + 19 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -30509,484 +32140,149 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - ENABLE - PWM module enable register - 0x500 - read-write + COUNTER + Current COUNTER value + 0x504 + read-only 0x00000000 + 0x20 - ENABLE - Enable or disable PWM module + COUNTER + Counter value 0 - 0 - - - Disabled - Disabled - 0 - - - Enabled - Enable - 1 - - + 23 - MODE - Selects operating mode of the wave counter - 0x504 + PRESCALER + 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is stopped. + 0x508 read-write 0x00000000 + 0x20 - UPDOWN - Selects up mode or up-and-down mode for the counter + PRESCALER + Prescaler value 0 - 0 - - - Up - Up counter, edge-aligned PWM duty cycle - 0 - - - UpAndDown - Up and down counter, center-aligned PWM duty cycle - 1 - - + 11 - COUNTERTOP - Value up to which the pulse generator counter counts - 0x508 + 0x4 + 0x4 + CC[%s] + Description collection: Compare register n + 0x540 read-write - 0x000003FF + 0x00000000 + 0x20 - COUNTERTOP - Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. + COMPARE + Compare value 0 - 14 + 23 - - PRESCALER - Configuration for PWM_CLK - 0x50C - read-write - 0x00000000 - - - PRESCALER - Prescaler of PWM_CLK - 0 - 2 - - - DIV_1 - Divide by 1 (16 MHz) - 0 - - - DIV_2 - Divide by 2 (8 MHz) - 1 - - - DIV_4 - Divide by 4 (4 MHz) - 2 - - - DIV_8 - Divide by 8 (2 MHz) - 3 - - - DIV_16 - Divide by 16 (1 MHz) - 4 - - - DIV_32 - Divide by 32 (500 kHz) - 5 - - - DIV_64 - Divide by 64 (250 kHz) - 6 - - - DIV_128 - Divide by 128 (125 kHz) - 7 - - - - - - - DECODER - Configuration of the decoder - 0x510 - read-write - 0x00000000 - - - LOAD - How a sequence is read from RAM and spread to the compare register - 0 - 1 - - - Common - 1st half word (16-bit) used in all PWM channels 0..3 - 0 - - - Grouped - 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 - 1 - - - Individual - 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 - 2 - - - WaveForm - 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP - 3 - - - - - MODE - Selects source for advancing the active sequence - 8 - 8 - - - RefreshCount - SEQ[n].REFRESH is used to determine loading internal compare registers - 0 - - - NextStep - NEXTSTEP task causes a new value to be loaded to internal compare registers - 1 - - - - - - - LOOP - Number of playbacks of a loop - 0x514 - read-write - 0x00000000 - - - CNT - Number of playbacks of pattern cycles - 0 - 15 - - - Disabled - Looping disabled (stop at the end of the sequence) - 0 - - - - - - - 2 - 0x020 - SEQ[%s] - Unspecified - PWM_SEQ - 0x520 - - PTR - Description cluster[n]: Beginning address in RAM of this sequence - 0x000 - read-write - 0x00000000 - - - PTR - Beginning address in RAM of this sequence - 0 - 31 - - - - - CNT - Description cluster[n]: Number of values (duty cycles) in this sequence - 0x004 - read-write - 0x00000000 - - - CNT - Number of values (duty cycles) in this sequence - 0 - 14 - - - Disabled - Sequence is disabled, and shall not be started as it is empty - 0 - - - - - - - REFRESH - Description cluster[n]: Number of additional PWM periods between samples loaded into compare register - 0x008 - read-write - 0x00000001 - - - CNT - Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) - 0 - 23 - - - Continuous - Update every PWM period - 0 - - - - - - - ENDDELAY - Description cluster[n]: Time added after the sequence - 0x00C - read-write - 0x00000000 - - - CNT - Time added after the sequence in PWM periods - 0 - 23 - - - - - - PSEL - Unspecified - PWM_PSEL - 0x560 - - 4 - 0x4 - OUT[%s] - Description collection[n]: Output pin select for PWM channel n - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - PDM - Pulse Density Modulation (Digital Microphone) Interface - 0x4001D000 + TEMP + Temperature Sensor + 0x4000C000 0 0x1000 registers - PDM - 29 + TEMP + 12 - PDM + TEMP 0x20 TASKS_START - Starts continuous PDM transfer + Start temperature measurement 0x000 write-only + 0x00000000 + 0x20 TASKS_START + Start temperature measurement 0 0 + + + Trigger + Trigger task + 0x1 + + TASKS_STOP - Stops PDM transfer + Stop temperature measurement 0x004 write-only + 0x00000000 + 0x20 TASKS_STOP + Stop temperature measurement 0 0 + + + Trigger + Trigger task + 0x1 + + - EVENTS_STARTED - PDM transfer has started + EVENTS_DATARDY + Temperature measurement complete, data ready 0x100 read-write + 0x00000000 + 0x20 - EVENTS_STARTED - 0 - 0 - - - - - EVENTS_STOPPED - PDM transfer has finished - 0x104 - read-write - - - EVENTS_STOPPED - 0 - 0 - - - - - EVENTS_END - The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM - 0x108 - read-write - - - EVENTS_END - 0 - 0 - - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - - STARTED - Enable or disable interrupt for STARTED event + EVENTS_DATARDY + Temperature measurement complete, data ready 0 0 - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - STOPPED - Enable or disable interrupt for STOPPED event - 1 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - END - Enable or disable interrupt for END event - 2 - 2 - - - Disabled - Disable - 0 + NotGenerated + Event not generated + 0x0 - Enabled - Enable - 1 + Generated + Event generated + 0x1 @@ -30997,10 +32293,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Enable interrupt 0x304 read-write + 0x00000000 + 0x20 - STARTED - Write '1' to enable interrupt for STARTED event + DATARDY + Write '1' to enable interrupt for event DATARDY 0 0 @@ -31008,66 +32306,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - STOPPED - Write '1' to enable interrupt for STOPPED event - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - END - Write '1' to enable interrupt for END event - 2 - 2 - - read - - Disabled - Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -31075,7 +32319,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 @@ -31086,10 +32330,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disable interrupt 0x308 read-write + 0x00000000 + 0x20 - STARTED - Write '1' to disable interrupt for STARTED event + DATARDY + Write '1' to disable interrupt for event DATARDY 0 0 @@ -31097,66 +32343,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - STOPPED - Write '1' to disable interrupt for STOPPED event - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - END - Write '1' to disable interrupt for END event - 2 - 2 - - read - - Disabled - Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -31164,4309 +32356,4872 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - ENABLE - PDM module enable register - 0x500 - read-write + TEMP + Temperature in degC (0.25deg steps) + 0x508 + read-only 0x00000000 + int32_t + 0x20 - ENABLE - Enable or disable PDM module + TEMP + Temperature in degC (0.25deg steps) 0 - 0 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - + 31 - PDMCLKCTRL - PDM clock generator control - 0x504 + A0 + Slope of first piecewise linear function + 0x520 read-write - 0x08400000 + 0x00000326 + 0x20 - FREQ - PDM_CLK frequency + A0 + Slope of first piecewise linear function 0 - 31 - - - 1000K - PDM_CLK = 32 MHz / 32 = 1.000 MHz - 0x08000000 - - - Default - PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64. - 0x08400000 - - - 1067K - PDM_CLK = 32 MHz / 30 = 1.067 MHz - 0x08800000 - - - 1231K - PDM_CLK = 32 MHz / 26 = 1.231 MHz - 0x09800000 - - - 1280K - PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80. - 0x0A000000 - - - 1333K - PDM_CLK = 32 MHz / 24 = 1.333 MHz - 0x0A800000 - - + 11 - MODE - Defines the routing of the connected PDM microphones' signals - 0x508 + A1 + Slope of second piecewise linear function + 0x524 read-write - 0x00000000 + 0x00000348 + 0x20 - OPERATION - Mono or stereo operation + A1 + Slope of second piecewise linear function 0 - 0 - - - Stereo - Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] - 0 - - - Mono - Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] - 1 - - + 11 + + + + A2 + Slope of third piecewise linear function + 0x528 + read-write + 0x000003AA + 0x20 + - EDGE - Defines on which PDM_CLK edge Left (or mono) is sampled - 1 - 1 - - - LeftFalling - Left (or mono) is sampled on falling edge of PDM_CLK - 0 - - - LeftRising - Left (or mono) is sampled on rising edge of PDM_CLK - 1 - - + A2 + Slope of third piecewise linear function + 0 + 11 - GAINL - Left output gain adjustment - 0x518 + A3 + Slope of fourth piecewise linear function + 0x52C read-write - 0x00000028 + 0x0000040E + 0x20 - GAINL - Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust + A3 + Slope of fourth piecewise linear function 0 - 6 - - - MinGain - -20dB gain adjustment (minimum) - 0x00 - - - DefaultGain - 0dB gain adjustment - 0x28 - - - MaxGain - +20dB gain adjustment (maximum) - 0x50 - - + 11 - GAINR - Right output gain adjustment - 0x51C + A4 + Slope of fifth piecewise linear function + 0x530 read-write - 0x00000028 + 0x000004BD + 0x20 - GAINR - Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) + A4 + Slope of fifth piecewise linear function 0 - 6 - - - MinGain - -20dB gain adjustment (minimum) - 0x00 - - - DefaultGain - 0dB gain adjustment - 0x28 - - - MaxGain - +20dB gain adjustment (maximum) - 0x50 - - + 11 - RATIO - Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. - 0x520 + A5 + Slope of sixth piecewise linear function + 0x534 read-write - 0x00000000 + 0x000005A3 + 0x20 - RATIO - Selects the ratio between PDM_CLK and output sample rate + A5 + Slope of sixth piecewise linear function 0 - 0 - - - Ratio64 - Ratio of 64 - 0 - - - Ratio80 - Ratio of 80 - 1 - - + 11 - - PSEL - Unspecified - PDM_PSEL - 0x540 - - CLK - Pin number configuration for PDM CLK signal - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - DIN - Pin number configuration for PDM DIN signal - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - SAMPLE - Unspecified - PDM_SAMPLE - 0x560 - - PTR - RAM address pointer to write samples to with EasyDMA - 0x000 - read-write - - - SAMPLEPTR - Address to write PDM samples to over DMA - 0 - 31 - - - - - MAXCNT - Number of samples to allocate memory for in EasyDMA mode - 0x004 - read-write - - - BUFFSIZE - Length of DMA RAM allocation in number of samples - 0 - 14 - - - - - - - - ACL - Access control lists - 0x4001E000 - - 0 - 0x1000 - registers - - ACL - 0x20 - - - 8 - 0x010 - ACL[%s] - Unspecified - ACL_ACL - 0x800 - - ADDR - Description cluster[n]: Configure the word-aligned start address of region n to protect - 0x000 - read-write - 0x00000000 - - - ADDR - Valid word-aligned start address of region n to protect. Address must point to a flash page boundary. - 0 - 31 - - - - - SIZE - Description cluster[n]: Size of region to protect counting from address ACL[n].ADDR. Write '0' as no effect. - 0x004 - read-write - 0x00000000 - - - SIZE - Size of flash region n in bytes. Must be a multiple of the flash page size, and the maximum region size is limited to 512kB. - 0 - 31 - - - - - PERM - Description cluster[n]: Access permissions for region n as defined by start address ACL[n].ADDR and size ACL[n].SIZE - 0x008 - read-write - 0x00000000 - - - WRITE - Configure write and erase permissions for region n. Write '0' has no effect. - 1 - 1 - - - Enable - Allow write and erase instructions to region n - 0 - - - Disable - Block write and erase instructions to region n - 1 - - - - - READ - Configure read permissions for region n. Write '0' has no effect. - 2 - 2 - - - Enable - Allow read instructions to region n - 0 - - - Disable - Block read instructions to region n - 1 - - - - - - - UNUSED0 - Unspecified - 0x00C - read-write - - - - - - NVMC - Non Volatile Memory Controller - 0x4001E000 - ACL - - 0 - 0x1000 - registers - - NVMC - 0x20 - - READY - Ready flag - 0x400 - read-only - 0x00000001 + B0 + y-intercept of first piecewise linear function + 0x540 + read-write + 0x00003FEF + 0x20 - READY - NVMC is ready or busy + B0 + y-intercept of first piecewise linear function 0 - 0 - - - Busy - NVMC is busy (on-going write or erase operation) - 0 - - - Ready - NVMC is ready - 1 - - + 13 - READYNEXT - Ready flag - 0x408 - read-only + B1 + y-intercept of second piecewise linear function + 0x544 + read-write + 0x00003FBE + 0x20 - READYNEXT - NVMC can accept a new write operation + B1 + y-intercept of second piecewise linear function 0 - 0 - - - Busy - NVMC cannot accept any write operation - 0 - - - Ready - NVMC is ready - 1 - - + 13 - CONFIG - Configuration register - 0x504 + B2 + y-intercept of third piecewise linear function + 0x548 read-write + 0x00003FBE + 0x20 - WEN - Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. + B2 + y-intercept of third piecewise linear function 0 - 1 - - - Ren - Read only access - 0 - - - Wen - Write enabled - 1 - - - Een - Erase enabled - 2 - - + 13 - ERASEPAGE - Register for erasing a page in code area - 0x508 + B3 + y-intercept of fourth piecewise linear function + 0x54C read-write + 0x00000012 + 0x20 - ERASEPAGE - Register for starting erase of a page in code area + B3 + y-intercept of fourth piecewise linear function 0 - 31 + 13 - ERASEPCR1 - Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. - 0x508 + B4 + y-intercept of fifth piecewise linear function + 0x550 read-write - ERASEPAGE + 0x00000124 + 0x20 - ERASEPCR1 - Register for erasing a page in code area. Equivalent to ERASEPAGE. + B4 + y-intercept of fifth piecewise linear function 0 - 31 + 13 - ERASEALL - Register for erasing all non-volatile user memory - 0x50C + B5 + y-intercept of sixth piecewise linear function + 0x554 read-write + 0x0000027C + 0x20 - ERASEALL - Erase all non-volatile memory including UICR registers. Note that the erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased. + B5 + y-intercept of sixth piecewise linear function 0 - 0 - - - NoOperation - No operation - 0 - - - Erase - Start chip erase - 1 - - + 13 - ERASEPCR0 - Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. - 0x510 + T0 + End point of first piecewise linear function + 0x560 read-write + 0x000000E2 + 0x20 - ERASEPCR0 - Register for starting erase of a page in code area. Equivalent to ERASEPAGE. + T0 + End point of first piecewise linear function 0 - 31 + 7 - ERASEUICR - Register for erasing user information configuration registers - 0x514 + T1 + End point of second piecewise linear function + 0x564 read-write + 0x00000000 + 0x20 - ERASEUICR - Register starting erase of all user information configuration registers. Note that the erase must be enabled using CONFIG.WEN before the UICR can be erased. + T1 + End point of second piecewise linear function 0 - 0 - - - NoOperation - No operation - 0 - - - Erase - Start erase of UICR - 1 - - + 7 - ERASEPAGEPARTIAL - Register for partial erase of a page in code area - 0x518 + T2 + End point of third piecewise linear function + 0x568 read-write + 0x00000019 + 0x20 - ERASEPAGEPARTIAL - Register for starting partial erase of a page in code area + T2 + End point of third piecewise linear function 0 - 31 + 7 - ERASEPAGEPARTIALCFG - Register for partial erase configuration - 0x51C + T3 + End point of fourth piecewise linear function + 0x56C read-write - 0x0000000A + 0x0000003C + 0x20 - DURATION - Duration of the partial erase in milliseconds + T3 + End point of fourth piecewise linear function 0 - 6 + 7 - ICACHECNF - I-code cache configuration register. - 0x540 + T4 + End point of fifth piecewise linear function + 0x570 read-write - 0x00000000 + 0x00000050 + 0x20 - CACHEEN - Cache enable + T4 + End point of fifth piecewise linear function 0 - 0 - - - Disabled - Disable cache. Invalidates all cache entries. - 0 - - - Enabled - Enable cache - 1 - - - - - CACHEPROFEN - Cache profiling enable - 8 - 8 - - - Disabled - Disable cache profiling - 0 - - - Enabled - Enable cache profiling - 1 - - - - - - - IHIT - I-code cache hit counter. - 0x548 - read-write - - - HITS - Number of cache hits - 0 - 31 - - - - - IMISS - I-code cache miss counter. - 0x54C - read-write - - - MISSES - Number of cache misses - 0 - 31 + 7 - PPI - Programmable Peripheral Interconnect - 0x4001F000 + RNG + Random Number Generator + 0x4000D000 0 0x1000 registers - PPI + + RNG + 13 + + RNG 0x20 - - 6 - 0x008 - TASKS_CHG[%s] - Channel group tasks - PPI_TASKS_CHG - 0x000 - - EN - Description cluster[n]: Enable channel group n - 0x000 - write-only - - - EN - 0 - 0 - - - - - DIS - Description cluster[n]: Disable channel group n - 0x004 - write-only - - - DIS - 0 - 0 - - - - - CHEN - Channel enable register - 0x500 - read-write + TASKS_START + Task starting the random number generator + 0x000 + write-only + 0x00000000 + 0x20 - CH0 - Enable or disable channel 0 + TASKS_START + Task starting the random number generator 0 0 - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 + Trigger + Trigger task + 0x1 + + + + TASKS_STOP + Task stopping the random number generator + 0x004 + write-only + 0x00000000 + 0x20 + - CH1 - Enable or disable channel 1 - 1 - 1 + TASKS_STOP + Task stopping the random number generator + 0 + 0 - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 + Trigger + Trigger task + 0x1 + + + + EVENTS_VALRDY + Event being generated for every new random number written to the VALUE register + 0x100 + read-write + 0x00000000 + 0x20 + - CH2 - Enable or disable channel 2 - 2 - 2 + EVENTS_VALRDY + Event being generated for every new random number written to the VALUE register + 0 + 0 - Disabled - Disable channel - 0 + NotGenerated + Event not generated + 0x0 - Enabled - Enable channel - 1 + Generated + Event generated + 0x1 + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + - CH3 - Enable or disable channel 3 - 3 - 3 + VALRDY_STOP + Shortcut between event VALRDY and task STOP + 0 + 0 Disabled - Disable channel - 0 + Disable shortcut + 0x0 Enabled - Enable channel - 1 + Enable shortcut + 0x1 + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + - CH4 - Enable or disable channel 4 - 4 - 4 + VALRDY + Write '1' to enable interrupt for event VALRDY + 0 + 0 + read Disabled - Disable channel - 0 + Read: Disabled + 0x0 Enabled - Enable channel - 1 + Read: Enabled + 0x1 - - - CH5 - Enable or disable channel 5 - 5 - 5 + write - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 + Set + Enable + 0x1 + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + - CH6 - Enable or disable channel 6 - 6 - 6 + VALRDY + Write '1' to disable interrupt for event VALRDY + 0 + 0 + read Disabled - Disable channel - 0 + Read: Disabled + 0x0 Enabled - Enable channel - 1 + Read: Enabled + 0x1 - - - CH7 - Enable or disable channel 7 - 7 - 7 + write - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 + Clear + Disable + 0x1 + + + + CONFIG + Configuration register + 0x504 + read-write + 0x00000000 + 0x20 + - CH8 - Enable or disable channel 8 - 8 - 8 + DERCEN + Bias correction + 0 + 0 Disabled - Disable channel - 0 + Disabled + 0x0 Enabled - Enable channel - 1 + Enabled + 0x1 + + + + VALUE + Output random number + 0x508 + read-only + 0x00000000 + 0x20 + - CH9 - Enable or disable channel 9 - 9 - 9 + VALUE + Generated random number + 0 + 7 + + + + + + + ECB + AES ECB Mode Encryption + 0x4000E000 + + 0 + 0x1000 + registers + + + ECB + 14 + + ECB + 0x20 + + + TASKS_STARTECB + Start ECB block encrypt + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_STARTECB + Start ECB block encrypt + 0 + 0 - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 + Trigger + Trigger task + 0x1 + + + + TASKS_STOPECB + Abort a possible executing ECB operation + 0x004 + write-only + 0x00000000 + 0x20 + - CH10 - Enable or disable channel 10 - 10 - 10 + TASKS_STOPECB + Abort a possible executing ECB operation + 0 + 0 - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 + Trigger + Trigger task + 0x1 + + + + EVENTS_ENDECB + ECB block encrypt complete + 0x100 + read-write + 0x00000000 + 0x20 + - CH11 - Enable or disable channel 11 - 11 - 11 + EVENTS_ENDECB + ECB block encrypt complete + 0 + 0 - Disabled - Disable channel - 0 + NotGenerated + Event not generated + 0x0 - Enabled - Enable channel - 1 + Generated + Event generated + 0x1 + + + + EVENTS_ERRORECB + ECB block encrypt aborted because of a STOPECB task or due to an error + 0x104 + read-write + 0x00000000 + 0x20 + - CH12 - Enable or disable channel 12 - 12 - 12 + EVENTS_ERRORECB + ECB block encrypt aborted because of a STOPECB task or due to an error + 0 + 0 - Disabled - Disable channel - 0 + NotGenerated + Event not generated + 0x0 - Enabled - Enable channel - 1 + Generated + Event generated + 0x1 + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + - CH13 - Enable or disable channel 13 - 13 - 13 + ENDECB + Write '1' to enable interrupt for event ENDECB + 0 + 0 + read Disabled - Disable channel - 0 + Read: Disabled + 0x0 Enabled - Enable channel - 1 + Read: Enabled + 0x1 - - - CH14 - Enable or disable channel 14 - 14 - 14 + write - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 + Set + Enable + 0x1 - CH15 - Enable or disable channel 15 - 15 - 15 + ERRORECB + Write '1' to enable interrupt for event ERRORECB + 1 + 1 + read Disabled - Disable channel - 0 + Read: Disabled + 0x0 Enabled - Enable channel - 1 + Read: Enabled + 0x1 - - - CH16 - Enable or disable channel 16 - 16 - 16 + write - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 + Set + Enable + 0x1 + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + - CH17 - Enable or disable channel 17 - 17 - 17 + ENDECB + Write '1' to disable interrupt for event ENDECB + 0 + 0 + read Disabled - Disable channel - 0 + Read: Disabled + 0x0 Enabled - Enable channel - 1 + Read: Enabled + 0x1 - - - CH18 - Enable or disable channel 18 - 18 - 18 + write - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 + Clear + Disable + 0x1 - CH19 - Enable or disable channel 19 - 19 - 19 + ERRORECB + Write '1' to disable interrupt for event ERRORECB + 1 + 1 + read Disabled - Disable channel - 0 + Read: Disabled + 0x0 Enabled - Enable channel - 1 + Read: Enabled + 0x1 - - - CH20 - Enable or disable channel 20 - 20 - 20 + write - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 + Clear + Disable + 0x1 - - CH21 - Enable or disable channel 21 - 21 - 21 - - - Disabled - Disable channel - 0 - + + + + ECBDATAPTR + ECB block encrypt memory pointers + 0x504 + read-write + 0x00000000 + 0x20 + + + ECBDATAPTR + Pointer to the ECB data structure (see Table 1 ECB data structure overview) + 0 + 31 + + + + + + + AAR + Accelerated Address Resolver + 0x4000F000 + + 0 + 0x1000 + registers + + + AAR_CCM + 15 + + AAR + 0x20 + + + TASKS_START + Start resolving addresses based on IRKs specified in the IRK data structure + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start resolving addresses based on IRKs specified in the IRK data structure + 0 + 0 + - Enabled - Enable channel - 1 + Trigger + Trigger task + 0x1 + + + + TASKS_STOP + Stop resolving addresses + 0x008 + write-only + 0x00000000 + 0x20 + - CH22 - Enable or disable channel 22 - 22 - 22 + TASKS_STOP + Stop resolving addresses + 0 + 0 - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 + Trigger + Trigger task + 0x1 + + + + EVENTS_END + Address resolution procedure complete + 0x100 + read-write + 0x00000000 + 0x20 + - CH23 - Enable or disable channel 23 - 23 - 23 + EVENTS_END + Address resolution procedure complete + 0 + 0 - Disabled - Disable channel - 0 + NotGenerated + Event not generated + 0x0 - Enabled - Enable channel - 1 + Generated + Event generated + 0x1 + + + + EVENTS_RESOLVED + Address resolved + 0x104 + read-write + 0x00000000 + 0x20 + - CH24 - Enable or disable channel 24 - 24 - 24 + EVENTS_RESOLVED + Address resolved + 0 + 0 - Disabled - Disable channel - 0 + NotGenerated + Event not generated + 0x0 - Enabled - Enable channel - 1 + Generated + Event generated + 0x1 + + + + EVENTS_NOTRESOLVED + Address not resolved + 0x108 + read-write + 0x00000000 + 0x20 + - CH25 - Enable or disable channel 25 - 25 - 25 + EVENTS_NOTRESOLVED + Address not resolved + 0 + 0 - Disabled - Disable channel - 0 + NotGenerated + Event not generated + 0x0 - Enabled - Enable channel - 1 + Generated + Event generated + 0x1 + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + - CH26 - Enable or disable channel 26 - 26 - 26 + END + Write '1' to enable interrupt for event END + 0 + 0 + read Disabled - Disable channel - 0 + Read: Disabled + 0x0 Enabled - Enable channel - 1 + Read: Enabled + 0x1 - - - CH27 - Enable or disable channel 27 - 27 - 27 + write - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 + Set + Enable + 0x1 - CH28 - Enable or disable channel 28 - 28 - 28 + RESOLVED + Write '1' to enable interrupt for event RESOLVED + 1 + 1 + read Disabled - Disable channel - 0 + Read: Disabled + 0x0 Enabled - Enable channel - 1 + Read: Enabled + 0x1 - - - CH29 - Enable or disable channel 29 - 29 - 29 + write - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 + Set + Enable + 0x1 - CH30 - Enable or disable channel 30 - 30 - 30 + NOTRESOLVED + Write '1' to enable interrupt for event NOTRESOLVED + 2 + 2 + read Disabled - Disable channel - 0 + Read: Disabled + 0x0 Enabled - Enable channel - 1 + Read: Enabled + 0x1 - - - CH31 - Enable or disable channel 31 - 31 - 31 + write - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 + Set + Enable + 0x1 - CHENSET - Channel enable set register - 0x504 + INTENCLR + Disable interrupt + 0x308 read-write - oneToSet + 0x00000000 + 0x20 - CH0 - Channel 0 enable set register. Writing '0' has no effect + END + Write '1' to disable interrupt for event END 0 0 read Disabled - Read: channel disabled - 0 + Read: Disabled + 0x0 Enabled - Read: channel enabled - 1 + Read: Enabled + 0x1 write - Set - Write: Enable channel - 1 + Clear + Disable + 0x1 - CH1 - Channel 1 enable set register. Writing '0' has no effect + RESOLVED + Write '1' to disable interrupt for event RESOLVED 1 1 read Disabled - Read: channel disabled - 0 + Read: Disabled + 0x0 Enabled - Read: channel enabled - 1 + Read: Enabled + 0x1 write - Set - Write: Enable channel - 1 + Clear + Disable + 0x1 - CH2 - Channel 2 enable set register. Writing '0' has no effect + NOTRESOLVED + Write '1' to disable interrupt for event NOTRESOLVED 2 2 read Disabled - Read: channel disabled - 0 + Read: Disabled + 0x0 Enabled - Read: channel enabled - 1 + Read: Enabled + 0x1 write - Set - Write: Enable channel - 1 + Clear + Disable + 0x1 + + + + STATUS + Resolution status + 0x400 + read-only + 0x00000000 + 0x20 + - CH3 - Channel 3 enable set register. Writing '0' has no effect - 3 + STATUS + The IRK that was used last time an address was resolved + 0 3 + + + + + ENABLE + Enable AAR + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable AAR + 0 + 1 - read Disabled - Read: channel disabled - 0 + Disable + 0x0 Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 + Enable + 0x3 + + + + NIRK + Number of IRKs + 0x504 + read-write + 0x00000001 + 0x20 + - CH4 - Channel 4 enable set register. Writing '0' has no effect - 4 + NIRK + Number of Identity Root Keys available in the IRK data structure + 0 4 + + + + + IRKPTR + Pointer to IRK data structure + 0x508 + read-write + 0x00000000 + 0x20 + + + IRKPTR + Pointer to the IRK data structure + 0 + 31 + + + + + ADDRPTR + Pointer to the resolvable address + 0x510 + read-write + 0x00000000 + 0x20 + + + ADDRPTR + Pointer to the resolvable address (6-bytes) + 0 + 31 + + + + + SCRATCHPTR + Pointer to data area used for temporary storage + 0x514 + read-write + 0x00000000 + 0x20 + + + SCRATCHPTR + Pointer to a scratch data area used for temporary storage during resolution. A space of minimum 3 bytes must be reserved. + 0 + 31 + + + + + + + CCM + AES CCM mode encryption + 0x4000F000 + AAR + + 0 + 0x1000 + registers + + + AAR_CCM + 15 + + CCM + 0x20 + + + TASKS_KSGEN + Start generation of keystream. This operation will stop by itself when completed. + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_KSGEN + Start generation of keystream. This operation will stop by itself when completed. + 0 + 0 - read - - Disabled - Read: channel disabled - 0 - - Enabled - Read: channel enabled - 1 + Trigger + Trigger task + 0x1 + + + + + TASKS_CRYPT + Start encryption/decryption. This operation will stop by itself when completed. + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_CRYPT + Start encryption/decryption. This operation will stop by itself when completed. + 0 + 0 - write - Set - Write: Enable channel - 1 + Trigger + Trigger task + 0x1 + + + + TASKS_STOP + Stop encryption/decryption + 0x008 + write-only + 0x00000000 + 0x20 + - CH5 - Channel 5 enable set register. Writing '0' has no effect - 5 - 5 + TASKS_STOP + Stop encryption/decryption + 0 + 0 - read - - Disabled - Read: channel disabled - 0 - - Enabled - Read: channel enabled - 1 + Trigger + Trigger task + 0x1 + + + + + TASKS_RATEOVERRIDE + Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption + 0x00C + write-only + 0x00000000 + 0x20 + + + TASKS_RATEOVERRIDE + Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption + 0 + 0 - write - Set - Write: Enable channel - 1 + Trigger + Trigger task + 0x1 + + + + EVENTS_ENDKSGEN + Keystream generation complete + 0x100 + read-write + 0x00000000 + 0x20 + - CH6 - Channel 6 enable set register. Writing '0' has no effect - 6 - 6 + EVENTS_ENDKSGEN + Keystream generation complete + 0 + 0 - read - - Disabled - Read: channel disabled - 0 - - Enabled - Read: channel enabled - 1 + NotGenerated + Event not generated + 0x0 - - - write - Set - Write: Enable channel - 1 + Generated + Event generated + 0x1 + + + + EVENTS_ENDCRYPT + Encrypt/decrypt complete + 0x104 + read-write + 0x00000000 + 0x20 + - CH7 - Channel 7 enable set register. Writing '0' has no effect - 7 - 7 + EVENTS_ENDCRYPT + Encrypt/decrypt complete + 0 + 0 - read - Disabled - Read: channel disabled - 0 + NotGenerated + Event not generated + 0x0 - Enabled - Read: channel enabled - 1 + Generated + Event generated + 0x1 + + + + + EVENTS_ERROR + Deprecated register - CCM error event + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_ERROR + Deprecated field - CCM error event + 0 + 0 - write - Set - Write: Enable channel - 1 + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + - CH8 - Channel 8 enable set register. Writing '0' has no effect - 8 - 8 + ENDKSGEN_CRYPT + Shortcut between event ENDKSGEN and task CRYPT + 0 + 0 - read Disabled - Read: channel disabled - 0 + Disable shortcut + 0x0 Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 + Enable shortcut + 0x1 + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + - CH9 - Channel 9 enable set register. Writing '0' has no effect - 9 - 9 + ENDKSGEN + Write '1' to enable interrupt for event ENDKSGEN + 0 + 0 read Disabled - Read: channel disabled - 0 + Read: Disabled + 0x0 Enabled - Read: channel enabled - 1 + Read: Enabled + 0x1 write Set - Write: Enable channel - 1 + Enable + 0x1 - CH10 - Channel 10 enable set register. Writing '0' has no effect - 10 - 10 + ENDCRYPT + Write '1' to enable interrupt for event ENDCRYPT + 1 + 1 read Disabled - Read: channel disabled - 0 + Read: Disabled + 0x0 Enabled - Read: channel enabled - 1 + Read: Enabled + 0x1 write Set - Write: Enable channel - 1 + Enable + 0x1 - CH11 - Channel 11 enable set register. Writing '0' has no effect - 11 - 11 + ERROR + Deprecated intsetfield - Write '1' to enable interrupt for event ERROR + 2 + 2 read Disabled - Read: channel disabled - 0 + Read: Disabled + 0x0 Enabled - Read: channel enabled - 1 + Read: Enabled + 0x1 write Set - Write: Enable channel - 1 + Enable + 0x1 + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + - CH12 - Channel 12 enable set register. Writing '0' has no effect - 12 - 12 + ENDKSGEN + Write '1' to disable interrupt for event ENDKSGEN + 0 + 0 read Disabled - Read: channel disabled - 0 + Read: Disabled + 0x0 Enabled - Read: channel enabled - 1 + Read: Enabled + 0x1 write - Set - Write: Enable channel - 1 + Clear + Disable + 0x1 - CH13 - Channel 13 enable set register. Writing '0' has no effect - 13 - 13 + ENDCRYPT + Write '1' to disable interrupt for event ENDCRYPT + 1 + 1 read Disabled - Read: channel disabled - 0 + Read: Disabled + 0x0 Enabled - Read: channel enabled - 1 + Read: Enabled + 0x1 write - Set - Write: Enable channel - 1 + Clear + Disable + 0x1 - CH14 - Channel 14 enable set register. Writing '0' has no effect - 14 - 14 + ERROR + Deprecated intclrfield - Write '1' to disable interrupt for event ERROR + 2 + 2 read Disabled - Read: channel disabled - 0 + Read: Disabled + 0x0 Enabled - Read: channel enabled - 1 + Read: Enabled + 0x1 write - Set - Write: Enable channel - 1 + Clear + Disable + 0x1 + + + + MICSTATUS + MIC check result + 0x400 + read-only + 0x00000000 + 0x20 + - CH15 - Channel 15 enable set register. Writing '0' has no effect - 15 - 15 + MICSTATUS + The result of the MIC check performed during the previous decryption operation + 0 + 0 - read - - Disabled - Read: channel disabled - 0 - - Enabled - Read: channel enabled - 1 + CheckFailed + MIC check failed + 0x0 - - - write - Set - Write: Enable channel - 1 + CheckPassed + MIC check passed + 0x1 + + + + ENABLE + Enable + 0x500 + read-write + 0x00000000 + 0x20 + - CH16 - Channel 16 enable set register. Writing '0' has no effect - 16 - 16 + ENABLE + Enable or disable CCM + 0 + 1 - read Disabled - Read: channel disabled - 0 + Disable + 0x0 Enabled - Read: channel enabled - 1 + Enable + 0x2 + + + + + MODE + Operation mode + 0x504 + read-write + 0x00000001 + 0x20 + + + MODE + The mode of operation to be used. Settings in this register apply whenever either the KSGEN task or the CRYPT task is triggered. + 0 + 0 - write - Set - Write: Enable channel - 1 + Encryption + AES CCM packet encryption mode + 0x0 + + + Decryption + AES CCM packet decryption mode + 0x1 - CH17 - Channel 17 enable set register. Writing '0' has no effect - 17 + DATARATE + Radio data rate that the CCM shall run synchronous with + 16 17 - read - Disabled - Read: channel disabled - 0 + 1Mbit + 1 Mbps + 0x0 - Enabled - Read: channel enabled - 1 + 2Mbit + 2 Mbps + 0x1 - - - write - Set - Write: Enable channel - 1 + 125Kbps + 125 kbps + 0x2 + + + 500Kbps + 500 kbps + 0x3 - CH18 - Channel 18 enable set register. Writing '0' has no effect - 18 - 18 + LENGTH + Packet length configuration + 24 + 24 - read - - Disabled - Read: channel disabled - 0 - - Enabled - Read: channel enabled - 1 + Default + Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A keystream for packet payloads up to 27 bytes will be generated. + 0x0 - - - write - Set - Write: Enable channel - 1 + Extended + Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A keystream for packet payloads up to MAXPACKETSIZE bytes will be generated. + 0x1 + + + + CNFPTR + Pointer to data structure holding the AES key and the NONCE vector + 0x508 + read-write + 0x00000000 + 0x20 + - CH19 - Channel 19 enable set register. Writing '0' has no effect - 19 - 19 + CNFPTR + Pointer to the data structure holding the AES key and the CCM NONCE vector (see table CCM data structure overview) + 0 + 31 + + + + + INPTR + Input pointer + 0x50C + read-write + 0x00000000 + 0x20 + + + INPTR + Input pointer + 0 + 31 + + + + + OUTPTR + Output pointer + 0x510 + read-write + 0x00000000 + 0x20 + + + OUTPTR + Output pointer + 0 + 31 + + + + + SCRATCHPTR + Pointer to data area used for temporary storage + 0x514 + read-write + 0x00000000 + 0x20 + + + SCRATCHPTR + Pointer to a scratch data area used for temporary storage during keystream generation, + MIC generation and encryption/decryption. + 0 + 31 + + + + + MAXPACKETSIZE + Length of keystream generated when MODE.LENGTH = Extended + 0x518 + read-write + 0x000000FB + 0x20 + + + MAXPACKETSIZE + Length of keystream generated when MODE.LENGTH = Extended. This value must be greater than or equal to the subsequent packet payload to be encrypted/decrypted. + 0 + 7 + + + + + RATEOVERRIDE + Data rate override setting. + 0x51C + read-write + 0x00000000 + 0x20 + + + RATEOVERRIDE + Data rate override setting + 0 + 1 - read - - Disabled - Read: channel disabled - 0 - - Enabled - Read: channel enabled - 1 + 1Mbit + 1 Mbps + 0x0 - - - write - Set - Write: Enable channel - 1 + 2Mbit + 2 Mbps + 0x1 - - - - CH20 - Channel 20 enable set register. Writing '0' has no effect - 20 - 20 - - read - Disabled - Read: channel disabled - 0 + 125Kbps + 125 kbps + 0x2 - Enabled - Read: channel enabled - 1 + 500Kbps + 500 kbps + 0x3 + + + + + + + WDT + Watchdog Timer + 0x40010000 + + 0 + 0x1000 + registers + + + WDT + 16 + + WDT + 0x20 + + + TASKS_START + Start the watchdog + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start the watchdog + 0 + 0 - write - Set - Write: Enable channel - 1 + Trigger + Trigger task + 0x1 + + + + EVENTS_TIMEOUT + Watchdog timeout + 0x100 + read-write + 0x00000000 + 0x20 + - CH21 - Channel 21 enable set register. Writing '0' has no effect - 21 - 21 + EVENTS_TIMEOUT + Watchdog timeout + 0 + 0 - read - - Disabled - Read: channel disabled - 0 - - Enabled - Read: channel enabled - 1 + NotGenerated + Event not generated + 0x0 - - - write - Set - Write: Enable channel - 1 + Generated + Event generated + 0x1 + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + - CH22 - Channel 22 enable set register. Writing '0' has no effect - 22 - 22 + TIMEOUT + Write '1' to enable interrupt for event TIMEOUT + 0 + 0 read Disabled - Read: channel disabled - 0 + Read: Disabled + 0x0 Enabled - Read: channel enabled - 1 + Read: Enabled + 0x1 write Set - Write: Enable channel - 1 + Enable + 0x1 + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + - CH23 - Channel 23 enable set register. Writing '0' has no effect - 23 - 23 + TIMEOUT + Write '1' to disable interrupt for event TIMEOUT + 0 + 0 read Disabled - Read: channel disabled - 0 + Read: Disabled + 0x0 Enabled - Read: channel enabled - 1 + Read: Enabled + 0x1 write - Set - Write: Enable channel - 1 + Clear + Disable + 0x1 - - CH24 - Channel 24 enable set register. Writing '0' has no effect - 24 - 24 + + + + RUNSTATUS + Run status + 0x400 + read-only + 0x00000000 + 0x20 + + + RUNSTATUS + Indicates whether or not the watchdog is running + 0 + 0 - read - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 + NotRunning + Watchdog not running + 0x0 - - - write - Set - Write: Enable channel - 1 + Running + Watchdog is running + 0x1 + + + + REQSTATUS + Request status + 0x404 + read-only + 0x00000001 + 0x20 + - CH25 - Channel 25 enable set register. Writing '0' has no effect - 25 - 25 + RR0 + Request status for RR[0] register + 0 + 0 - read - - Disabled - Read: channel disabled - 0 - - Enabled - Read: channel enabled - 1 + DisabledOrRequested + RR[0] register is not enabled, or is already requesting reload + 0x0 - - - write - Set - Write: Enable channel - 1 + EnabledAndUnrequested + RR[0] register is enabled, and is not yet requesting reload + 0x1 - CH26 - Channel 26 enable set register. Writing '0' has no effect - 26 - 26 + RR1 + Request status for RR[1] register + 1 + 1 - read - - Disabled - Read: channel disabled - 0 - - Enabled - Read: channel enabled - 1 + DisabledOrRequested + RR[1] register is not enabled, or is already requesting reload + 0x0 - - - write - Set - Write: Enable channel - 1 + EnabledAndUnrequested + RR[1] register is enabled, and is not yet requesting reload + 0x1 - CH27 - Channel 27 enable set register. Writing '0' has no effect - 27 - 27 + RR2 + Request status for RR[2] register + 2 + 2 - read - - Disabled - Read: channel disabled - 0 - - Enabled - Read: channel enabled - 1 + DisabledOrRequested + RR[2] register is not enabled, or is already requesting reload + 0x0 - - - write - Set - Write: Enable channel - 1 + EnabledAndUnrequested + RR[2] register is enabled, and is not yet requesting reload + 0x1 - CH28 - Channel 28 enable set register. Writing '0' has no effect - 28 - 28 + RR3 + Request status for RR[3] register + 3 + 3 - read - - Disabled - Read: channel disabled - 0 - - Enabled - Read: channel enabled - 1 + DisabledOrRequested + RR[3] register is not enabled, or is already requesting reload + 0x0 - - - write - Set - Write: Enable channel - 1 + EnabledAndUnrequested + RR[3] register is enabled, and is not yet requesting reload + 0x1 - CH29 - Channel 29 enable set register. Writing '0' has no effect - 29 - 29 + RR4 + Request status for RR[4] register + 4 + 4 - read - - Disabled - Read: channel disabled - 0 - - Enabled - Read: channel enabled - 1 + DisabledOrRequested + RR[4] register is not enabled, or is already requesting reload + 0x0 - - - write - Set - Write: Enable channel - 1 + EnabledAndUnrequested + RR[4] register is enabled, and is not yet requesting reload + 0x1 - CH30 - Channel 30 enable set register. Writing '0' has no effect - 30 - 30 + RR5 + Request status for RR[5] register + 5 + 5 - read - - Disabled - Read: channel disabled - 0 - - Enabled - Read: channel enabled - 1 + DisabledOrRequested + RR[5] register is not enabled, or is already requesting reload + 0x0 - - - write - Set - Write: Enable channel - 1 + EnabledAndUnrequested + RR[5] register is enabled, and is not yet requesting reload + 0x1 - CH31 - Channel 31 enable set register. Writing '0' has no effect - 31 - 31 + RR6 + Request status for RR[6] register + 6 + 6 - read - Disabled - Read: channel disabled - 0 + DisabledOrRequested + RR[6] register is not enabled, or is already requesting reload + 0x0 - Enabled - Read: channel enabled - 1 + EnabledAndUnrequested + RR[6] register is enabled, and is not yet requesting reload + 0x1 + + + RR7 + Request status for RR[7] register + 7 + 7 - write - Set - Write: Enable channel - 1 + DisabledOrRequested + RR[7] register is not enabled, or is already requesting reload + 0x0 + + + EnabledAndUnrequested + RR[7] register is enabled, and is not yet requesting reload + 0x1 - CHENCLR - Channel enable clear register + CRV + Counter reload value + 0x504 + read-write + 0xFFFFFFFF + 0x20 + + + CRV + Counter reload value in number of cycles of the 32.768 kHz clock + 0 + 31 + + + + + RREN + Enable register for reload request registers 0x508 read-write - oneToClear + 0x00000001 + 0x20 - CH0 - Channel 0 enable clear register. Writing '0' has no effect + RR0 + Enable or disable RR[0] register 0 0 - read Disabled - Read: channel disabled - 0 + Disable RR[0] register + 0x0 Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel - 1 + Enable RR[0] register + 0x1 - CH1 - Channel 1 enable clear register. Writing '0' has no effect + RR1 + Enable or disable RR[1] register 1 1 - read Disabled - Read: channel disabled - 0 + Disable RR[1] register + 0x0 Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel - 1 + Enable RR[1] register + 0x1 - CH2 - Channel 2 enable clear register. Writing '0' has no effect + RR2 + Enable or disable RR[2] register 2 2 - read Disabled - Read: channel disabled - 0 + Disable RR[2] register + 0x0 Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel - 1 + Enable RR[2] register + 0x1 - CH3 - Channel 3 enable clear register. Writing '0' has no effect + RR3 + Enable or disable RR[3] register 3 3 - read Disabled - Read: channel disabled - 0 + Disable RR[3] register + 0x0 Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel - 1 + Enable RR[3] register + 0x1 - CH4 - Channel 4 enable clear register. Writing '0' has no effect + RR4 + Enable or disable RR[4] register 4 4 - read Disabled - Read: channel disabled - 0 + Disable RR[4] register + 0x0 Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel - 1 + Enable RR[4] register + 0x1 - CH5 - Channel 5 enable clear register. Writing '0' has no effect + RR5 + Enable or disable RR[5] register 5 5 - read Disabled - Read: channel disabled - 0 + Disable RR[5] register + 0x0 Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel - 1 + Enable RR[5] register + 0x1 - CH6 - Channel 6 enable clear register. Writing '0' has no effect + RR6 + Enable or disable RR[6] register 6 6 - read Disabled - Read: channel disabled - 0 + Disable RR[6] register + 0x0 Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel - 1 + Enable RR[6] register + 0x1 - CH7 - Channel 7 enable clear register. Writing '0' has no effect + RR7 + Enable or disable RR[7] register 7 7 - read Disabled - Read: channel disabled - 0 + Disable RR[7] register + 0x0 Enabled - Read: channel enabled - 1 + Enable RR[7] register + 0x1 + + + + + CONFIG + Configuration register + 0x50C + read-write + 0x00000001 + 0x20 + + + SLEEP + Configure the watchdog to either be paused, or kept running, while the CPU is sleeping + 0 + 0 - write - Clear - Write: disable channel - 1 + Pause + Pause watchdog while the CPU is sleeping + 0x0 + + + Run + Keep the watchdog running while the CPU is sleeping + 0x1 - CH8 - Channel 8 enable clear register. Writing '0' has no effect - 8 - 8 + HALT + Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger + 3 + 3 - read - Disabled - Read: channel disabled - 0 + Pause + Pause watchdog while the CPU is halted by the debugger + 0x0 - Enabled - Read: channel enabled - 1 + Run + Keep the watchdog running while the CPU is halted by the debugger + 0x1 + + + + + 0x8 + 0x4 + RR[%s] + Description collection: Reload request n + 0x600 + write-only + 0x00000000 + 0x20 + + + RR + Reload request register + 0 + 31 - write - Clear - Write: disable channel - 1 + Reload + Value to request a reload of the watchdog timer + 0x6E524635 + + + + + + RTC1 + Real time counter 1 + 0x40011000 + + RTC1 + 17 + + + + QDEC + Quadrature Decoder + 0x40012000 + + 0 + 0x1000 + registers + + + QDEC + 18 + + QDEC + 0x20 + + + TASKS_START + Task starting the quadrature decoder + 0x000 + write-only + 0x00000000 + 0x20 + - CH9 - Channel 9 enable clear register. Writing '0' has no effect - 9 - 9 + TASKS_START + Task starting the quadrature decoder + 0 + 0 - read - - Disabled - Read: channel disabled - 0 - - Enabled - Read: channel enabled - 1 + Trigger + Trigger task + 0x1 + + + + + TASKS_STOP + Task stopping the quadrature decoder + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Task stopping the quadrature decoder + 0 + 0 - write - Clear - Write: disable channel - 1 + Trigger + Trigger task + 0x1 + + + + TASKS_READCLRACC + Read and clear ACC and ACCDBL + 0x008 + write-only + 0x00000000 + 0x20 + - CH10 - Channel 10 enable clear register. Writing '0' has no effect - 10 - 10 + TASKS_READCLRACC + Read and clear ACC and ACCDBL + 0 + 0 - read - - Disabled - Read: channel disabled - 0 - - Enabled - Read: channel enabled - 1 + Trigger + Trigger task + 0x1 + + + + + TASKS_RDCLRACC + Read and clear ACC + 0x00C + write-only + 0x00000000 + 0x20 + + + TASKS_RDCLRACC + Read and clear ACC + 0 + 0 - write - Clear - Write: disable channel - 1 + Trigger + Trigger task + 0x1 + + + + TASKS_RDCLRDBL + Read and clear ACCDBL + 0x010 + write-only + 0x00000000 + 0x20 + - CH11 - Channel 11 enable clear register. Writing '0' has no effect - 11 - 11 + TASKS_RDCLRDBL + Read and clear ACCDBL + 0 + 0 - read - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 + Trigger + Trigger task + 0x1 + + + + + EVENTS_SAMPLERDY + Event being generated for every new sample value written to the SAMPLE register + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_SAMPLERDY + Event being generated for every new sample value written to the SAMPLE register + 0 + 0 - write - Clear - Write: disable channel - 1 + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + EVENTS_REPORTRDY + Non-null report ready + 0x104 + read-write + 0x00000000 + 0x20 + - CH12 - Channel 12 enable clear register. Writing '0' has no effect - 12 - 12 + EVENTS_REPORTRDY + Non-null report ready + 0 + 0 - read - Disabled - Read: channel disabled - 0 + NotGenerated + Event not generated + 0x0 - Enabled - Read: channel enabled - 1 + Generated + Event generated + 0x1 + + + + + EVENTS_ACCOF + ACC or ACCDBL register overflow + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_ACCOF + ACC or ACCDBL register overflow + 0 + 0 - write - Clear - Write: disable channel - 1 + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + EVENTS_DBLRDY + Double displacement(s) detected + 0x10C + read-write + 0x00000000 + 0x20 + - CH13 - Channel 13 enable clear register. Writing '0' has no effect - 13 - 13 + EVENTS_DBLRDY + Double displacement(s) detected + 0 + 0 - read - Disabled - Read: channel disabled - 0 + NotGenerated + Event not generated + 0x0 - Enabled - Read: channel enabled - 1 + Generated + Event generated + 0x1 + + + + + EVENTS_STOPPED + QDEC has been stopped + 0x110 + read-write + 0x00000000 + 0x20 + + + EVENTS_STOPPED + QDEC has been stopped + 0 + 0 - write - Clear - Write: disable channel - 1 + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + - CH14 - Channel 14 enable clear register. Writing '0' has no effect - 14 - 14 + REPORTRDY_READCLRACC + Shortcut between event REPORTRDY and task READCLRACC + 0 + 0 - read Disabled - Read: channel disabled - 0 + Disable shortcut + 0x0 Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel - 1 + Enable shortcut + 0x1 - CH15 - Channel 15 enable clear register. Writing '0' has no effect - 15 - 15 + SAMPLERDY_STOP + Shortcut between event SAMPLERDY and task STOP + 1 + 1 - read Disabled - Read: channel disabled - 0 + Disable shortcut + 0x0 Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel - 1 + Enable shortcut + 0x1 - CH16 - Channel 16 enable clear register. Writing '0' has no effect - 16 - 16 + REPORTRDY_RDCLRACC + Shortcut between event REPORTRDY and task RDCLRACC + 2 + 2 - read Disabled - Read: channel disabled - 0 + Disable shortcut + 0x0 Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel - 1 + Enable shortcut + 0x1 - CH17 - Channel 17 enable clear register. Writing '0' has no effect - 17 - 17 + REPORTRDY_STOP + Shortcut between event REPORTRDY and task STOP + 3 + 3 - read Disabled - Read: channel disabled - 0 + Disable shortcut + 0x0 Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel - 1 + Enable shortcut + 0x1 - CH18 - Channel 18 enable clear register. Writing '0' has no effect - 18 - 18 + DBLRDY_RDCLRDBL + Shortcut between event DBLRDY and task RDCLRDBL + 4 + 4 - read Disabled - Read: channel disabled - 0 + Disable shortcut + 0x0 Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel - 1 + Enable shortcut + 0x1 - CH19 - Channel 19 enable clear register. Writing '0' has no effect - 19 - 19 + DBLRDY_STOP + Shortcut between event DBLRDY and task STOP + 5 + 5 - read Disabled - Read: channel disabled - 0 + Disable shortcut + 0x0 Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel - 1 + Enable shortcut + 0x1 - CH20 - Channel 20 enable clear register. Writing '0' has no effect - 20 - 20 + SAMPLERDY_READCLRACC + Shortcut between event SAMPLERDY and task READCLRACC + 6 + 6 - read Disabled - Read: channel disabled - 0 + Disable shortcut + 0x0 Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel - 1 + Enable shortcut + 0x1 + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + - CH21 - Channel 21 enable clear register. Writing '0' has no effect - 21 - 21 + SAMPLERDY + Write '1' to enable interrupt for event SAMPLERDY + 0 + 0 read Disabled - Read: channel disabled - 0 + Read: Disabled + 0x0 Enabled - Read: channel enabled - 1 + Read: Enabled + 0x1 write - Clear - Write: disable channel - 1 + Set + Enable + 0x1 - CH22 - Channel 22 enable clear register. Writing '0' has no effect - 22 - 22 + REPORTRDY + Write '1' to enable interrupt for event REPORTRDY + 1 + 1 read Disabled - Read: channel disabled - 0 + Read: Disabled + 0x0 Enabled - Read: channel enabled - 1 + Read: Enabled + 0x1 write - Clear - Write: disable channel - 1 + Set + Enable + 0x1 - CH23 - Channel 23 enable clear register. Writing '0' has no effect - 23 - 23 + ACCOF + Write '1' to enable interrupt for event ACCOF + 2 + 2 read Disabled - Read: channel disabled - 0 + Read: Disabled + 0x0 Enabled - Read: channel enabled - 1 + Read: Enabled + 0x1 write - Clear - Write: disable channel - 1 + Set + Enable + 0x1 - CH24 - Channel 24 enable clear register. Writing '0' has no effect - 24 - 24 + DBLRDY + Write '1' to enable interrupt for event DBLRDY + 3 + 3 read Disabled - Read: channel disabled - 0 + Read: Disabled + 0x0 Enabled - Read: channel enabled - 1 + Read: Enabled + 0x1 write - Clear - Write: disable channel - 1 + Set + Enable + 0x1 - CH25 - Channel 25 enable clear register. Writing '0' has no effect - 25 - 25 + STOPPED + Write '1' to enable interrupt for event STOPPED + 4 + 4 read Disabled - Read: channel disabled - 0 + Read: Disabled + 0x0 Enabled - Read: channel enabled - 1 + Read: Enabled + 0x1 write - Clear - Write: disable channel - 1 + Set + Enable + 0x1 + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + - CH26 - Channel 26 enable clear register. Writing '0' has no effect - 26 - 26 + SAMPLERDY + Write '1' to disable interrupt for event SAMPLERDY + 0 + 0 read Disabled - Read: channel disabled - 0 + Read: Disabled + 0x0 Enabled - Read: channel enabled - 1 + Read: Enabled + 0x1 write Clear - Write: disable channel - 1 + Disable + 0x1 - CH27 - Channel 27 enable clear register. Writing '0' has no effect - 27 - 27 + REPORTRDY + Write '1' to disable interrupt for event REPORTRDY + 1 + 1 read Disabled - Read: channel disabled - 0 + Read: Disabled + 0x0 Enabled - Read: channel enabled - 1 + Read: Enabled + 0x1 write Clear - Write: disable channel - 1 + Disable + 0x1 - CH28 - Channel 28 enable clear register. Writing '0' has no effect - 28 - 28 + ACCOF + Write '1' to disable interrupt for event ACCOF + 2 + 2 read Disabled - Read: channel disabled - 0 + Read: Disabled + 0x0 Enabled - Read: channel enabled - 1 + Read: Enabled + 0x1 write Clear - Write: disable channel - 1 + Disable + 0x1 - CH29 - Channel 29 enable clear register. Writing '0' has no effect - 29 - 29 + DBLRDY + Write '1' to disable interrupt for event DBLRDY + 3 + 3 read Disabled - Read: channel disabled - 0 + Read: Disabled + 0x0 Enabled - Read: channel enabled - 1 + Read: Enabled + 0x1 write Clear - Write: disable channel - 1 + Disable + 0x1 - CH30 - Channel 30 enable clear register. Writing '0' has no effect - 30 - 30 + STOPPED + Write '1' to disable interrupt for event STOPPED + 4 + 4 read Disabled - Read: channel disabled - 0 + Read: Disabled + 0x0 Enabled - Read: channel enabled - 1 + Read: Enabled + 0x1 write Clear - Write: disable channel - 1 + Disable + 0x1 + + + + ENABLE + Enable the quadrature decoder + 0x500 + read-write + 0x00000000 + 0x20 + - CH31 - Channel 31 enable clear register. Writing '0' has no effect - 31 - 31 + ENABLE + Enable or disable the quadrature decoder + 0 + 0 - read Disabled - Read: channel disabled - 0 + Disable + 0x0 Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel - 1 + Enable + 0x1 - - 20 - 0x008 - CH[%s] - PPI Channel - PPI_CH - 0x510 - - EEP - Description cluster[n]: Channel n event end-point - 0x000 - read-write - - - EEP - Pointer to event register. Accepts only addresses to registers from the Event group. - 0 - 31 - - - - - TEP - Description cluster[n]: Channel n task end-point - 0x004 - read-write - - - TEP - Pointer to task register. Accepts only addresses to registers from the Task group. - 0 - 31 - - - - - 6 - 0x4 - CHG[%s] - Description collection[n]: Channel group n - 0x800 + LEDPOL + LED output pin polarity + 0x504 read-write + 0x00000000 + 0x20 - CH0 - Include or exclude channel 0 + LEDPOL + LED output pin polarity 0 0 - Excluded - Exclude - 0 + ActiveLow + Led active on output pin low + 0x0 - Included - Include - 1 + ActiveHigh + Led active on output pin high + 0x1 - - CH1 - Include or exclude channel 1 - 1 - 1 + + + + SAMPLEPER + Sample period + 0x508 + read-write + 0x00000000 + 0x20 + + + SAMPLEPER + Sample period. The SAMPLE register will be updated for every new sample + 0 + 3 - Excluded - Exclude - 0 + 128us + 128 us + 0x0 - Included - Include - 1 + 256us + 256 us + 0x1 - - - - CH2 - Include or exclude channel 2 - 2 - 2 - - Excluded - Exclude - 0 + 512us + 512 us + 0x2 - Included - Include - 1 + 1024us + 1024 us + 0x3 + + + 2048us + 2048 us + 0x4 + + + 4096us + 4096 us + 0x5 + + + 8192us + 8192 us + 0x6 + + + 16384us + 16384 us + 0x7 + + + 32ms + 32768 us + 0x8 + + + 65ms + 65536 us + 0x9 + + + 131ms + 131072 us + 0xA + + + + SAMPLE + Motion sample value + 0x50C + read-only + 0x00000000 + int32_t + 0x20 + - CH3 - Include or exclude channel 3 - 3 + SAMPLE + Last motion sample + 0 + 31 + + + + + REPORTPER + Number of samples to be taken before REPORTRDY and DBLRDY events can be generated + 0x510 + read-write + 0x00000000 + 0x20 + + + REPORTPER + Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated. + 0 3 - Excluded - Exclude - 0 + 10Smpl + 10 samples/report + 0x0 - Included - Include - 1 + 40Smpl + 40 samples/report + 0x1 - - - - CH4 - Include or exclude channel 4 - 4 - 4 - - Excluded - Exclude - 0 + 80Smpl + 80 samples/report + 0x2 - Included - Include - 1 + 120Smpl + 120 samples/report + 0x3 - - - - CH5 - Include or exclude channel 5 - 5 - 5 - - Excluded - Exclude - 0 + 160Smpl + 160 samples/report + 0x4 - Included - Include - 1 + 200Smpl + 200 samples/report + 0x5 - - - - CH6 - Include or exclude channel 6 - 6 - 6 - - Excluded - Exclude - 0 + 240Smpl + 240 samples/report + 0x6 - Included - Include - 1 + 280Smpl + 280 samples/report + 0x7 + + + 1Smpl + 1 sample/report + 0x8 + + + + ACC + Register accumulating the valid transitions + 0x514 + read-only + 0x00000000 + int32_t + 0x20 + - CH7 - Include or exclude channel 7 - 7 - 7 + ACC + Register accumulating all valid samples (not double transition) read from the SAMPLE register. + 0 + 31 + + + + + ACCREAD + Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task + 0x518 + read-only + 0x00000000 + int32_t + 0x20 + + + ACCREAD + Snapshot of the ACC register. + 0 + 31 + + + + + PSEL + Unspecified + QDEC_PSEL + read-write + 0x51C + + LED + Pin select for LED signal + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + A + Pin select for A signal + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + B + Pin select for B signal + 0x008 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + DBFEN + Enable input debounce filters + 0x528 + read-write + 0x00000000 + 0x20 + + + DBFEN + Enable input debounce filters + 0 + 0 - Excluded - Exclude - 0 + Disabled + Debounce input filters disabled + 0x0 - Included - Include - 1 + Enabled + Debounce input filters enabled + 0x1 + + + + LEDPRE + Time period the LED is switched ON prior to sampling + 0x540 + read-write + 0x00000010 + 0x20 + - CH8 - Include or exclude channel 8 - 8 + LEDPRE + Period in us the LED is switched on prior to sampling + 0 8 + + + + + ACCDBL + Register accumulating the number of detected double transitions + 0x544 + read-only + 0x00000000 + 0x20 + + + ACCDBL + Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). + 0 + 3 + + + + + ACCDBLREAD + Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task + 0x548 + read-only + 0x00000000 + 0x20 + + + ACCDBLREAD + Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. + 0 + 3 + + + + + + + COMP + Comparator + 0x40013000 + + 0 + 0x1000 + registers + + + COMP_LPCOMP + 19 + + COMP + 0x20 + + + TASKS_START + Start comparator + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start comparator + 0 + 0 - Excluded - Exclude - 0 - - - Included - Include - 1 + Trigger + Trigger task + 0x1 + + + + TASKS_STOP + Stop comparator + 0x004 + write-only + 0x00000000 + 0x20 + - CH9 - Include or exclude channel 9 - 9 - 9 + TASKS_STOP + Stop comparator + 0 + 0 - Excluded - Exclude - 0 - - - Included - Include - 1 + Trigger + Trigger task + 0x1 + + + + TASKS_SAMPLE + Sample comparator value + 0x008 + write-only + 0x00000000 + 0x20 + - CH10 - Include or exclude channel 10 - 10 - 10 + TASKS_SAMPLE + Sample comparator value + 0 + 0 - Excluded - Exclude - 0 - - - Included - Include - 1 + Trigger + Trigger task + 0x1 + + + + EVENTS_READY + COMP is ready and output is valid + 0x100 + read-write + 0x00000000 + 0x20 + - CH11 - Include or exclude channel 11 - 11 - 11 + EVENTS_READY + COMP is ready and output is valid + 0 + 0 - Excluded - Exclude - 0 + NotGenerated + Event not generated + 0x0 - Included - Include - 1 + Generated + Event generated + 0x1 + + + + EVENTS_DOWN + Downward crossing + 0x104 + read-write + 0x00000000 + 0x20 + - CH12 - Include or exclude channel 12 - 12 - 12 + EVENTS_DOWN + Downward crossing + 0 + 0 - Excluded - Exclude - 0 + NotGenerated + Event not generated + 0x0 - Included - Include - 1 + Generated + Event generated + 0x1 - - CH13 - Include or exclude channel 13 - 13 - 13 + + + + EVENTS_UP + Upward crossing + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_UP + Upward crossing + 0 + 0 - Excluded - Exclude - 0 + NotGenerated + Event not generated + 0x0 - Included - Include - 1 + Generated + Event generated + 0x1 + + + + EVENTS_CROSS + Downward or upward crossing + 0x10C + read-write + 0x00000000 + 0x20 + - CH14 - Include or exclude channel 14 - 14 - 14 + EVENTS_CROSS + Downward or upward crossing + 0 + 0 - Excluded - Exclude - 0 + NotGenerated + Event not generated + 0x0 - Included - Include - 1 + Generated + Event generated + 0x1 + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + - CH15 - Include or exclude channel 15 - 15 - 15 + READY_SAMPLE + Shortcut between event READY and task SAMPLE + 0 + 0 - Excluded - Exclude - 0 + Disabled + Disable shortcut + 0x0 - Included - Include - 1 + Enabled + Enable shortcut + 0x1 - CH16 - Include or exclude channel 16 - 16 - 16 + READY_STOP + Shortcut between event READY and task STOP + 1 + 1 - Excluded - Exclude - 0 + Disabled + Disable shortcut + 0x0 - Included - Include - 1 + Enabled + Enable shortcut + 0x1 - CH17 - Include or exclude channel 17 - 17 - 17 + DOWN_STOP + Shortcut between event DOWN and task STOP + 2 + 2 - Excluded - Exclude - 0 + Disabled + Disable shortcut + 0x0 - Included - Include - 1 + Enabled + Enable shortcut + 0x1 - CH18 - Include or exclude channel 18 - 18 - 18 + UP_STOP + Shortcut between event UP and task STOP + 3 + 3 - Excluded - Exclude - 0 + Disabled + Disable shortcut + 0x0 - Included - Include - 1 + Enabled + Enable shortcut + 0x1 - CH19 - Include or exclude channel 19 - 19 - 19 + CROSS_STOP + Shortcut between event CROSS and task STOP + 4 + 4 - Excluded - Exclude - 0 + Disabled + Disable shortcut + 0x0 - Included - Include - 1 + Enabled + Enable shortcut + 0x1 + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + - CH20 - Include or exclude channel 20 - 20 - 20 + READY + Enable or disable interrupt for event READY + 0 + 0 - Excluded - Exclude - 0 + Disabled + Disable + 0x0 - Included - Include - 1 + Enabled + Enable + 0x1 - CH21 - Include or exclude channel 21 - 21 - 21 + DOWN + Enable or disable interrupt for event DOWN + 1 + 1 - Excluded - Exclude - 0 + Disabled + Disable + 0x0 - Included - Include - 1 + Enabled + Enable + 0x1 - CH22 - Include or exclude channel 22 - 22 - 22 + UP + Enable or disable interrupt for event UP + 2 + 2 - Excluded - Exclude - 0 + Disabled + Disable + 0x0 - Included - Include - 1 + Enabled + Enable + 0x1 - CH23 - Include or exclude channel 23 - 23 - 23 + CROSS + Enable or disable interrupt for event CROSS + 3 + 3 - Excluded - Exclude - 0 + Disabled + Disable + 0x0 - Included - Include - 1 + Enabled + Enable + 0x1 + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + - CH24 - Include or exclude channel 24 - 24 - 24 + READY + Write '1' to enable interrupt for event READY + 0 + 0 + read - Excluded - Exclude - 0 + Disabled + Read: Disabled + 0x0 - Included - Include - 1 + Enabled + Read: Enabled + 0x1 - - - CH25 - Include or exclude channel 25 - 25 - 25 + write - Excluded - Exclude - 0 - - - Included - Include - 1 + Set + Enable + 0x1 - CH26 - Include or exclude channel 26 - 26 - 26 + DOWN + Write '1' to enable interrupt for event DOWN + 1 + 1 + read - Excluded - Exclude - 0 + Disabled + Read: Disabled + 0x0 - Included - Include - 1 + Enabled + Read: Enabled + 0x1 - - - CH27 - Include or exclude channel 27 - 27 - 27 + write - Excluded - Exclude - 0 - - - Included - Include - 1 + Set + Enable + 0x1 - CH28 - Include or exclude channel 28 - 28 - 28 + UP + Write '1' to enable interrupt for event UP + 2 + 2 + read - Excluded - Exclude - 0 + Disabled + Read: Disabled + 0x0 - Included - Include - 1 + Enabled + Read: Enabled + 0x1 - - - CH29 - Include or exclude channel 29 - 29 - 29 + write - Excluded - Exclude - 0 - - - Included - Include - 1 + Set + Enable + 0x1 - CH30 - Include or exclude channel 30 - 30 - 30 + CROSS + Write '1' to enable interrupt for event CROSS + 3 + 3 + read - Excluded - Exclude - 0 + Disabled + Read: Disabled + 0x0 - Included - Include - 1 + Enabled + Read: Enabled + 0x1 - - - CH31 - Include or exclude channel 31 - 31 - 31 + write - Excluded - Exclude - 0 - - - Included - Include - 1 + Set + Enable + 0x1 - - 32 - 0x004 - FORK[%s] - Fork - PPI_FORK - 0x910 - - TEP - Description cluster[n]: Channel n task end-point - 0x000 - read-write - - - TEP - Pointer to task register - 0 - 31 - - - - - - - - MWU - Memory Watch Unit - 0x40020000 - - 0 - 0x1000 - registers - - - MWU - 32 - - MWU - 0x20 - - - 4 - 0x008 - EVENTS_REGION[%s] - Unspecified - MWU_EVENTS_REGION - 0x100 - - WA - Description cluster[n]: Write access to region n detected - 0x000 - read-write - - - WA - 0 - 0 - - - - - RA - Description cluster[n]: Read access to region n detected - 0x004 - read-write - - - RA - 0 - 0 - - - - - - 2 - 0x008 - EVENTS_PREGION[%s] - Unspecified - MWU_EVENTS_PREGION - 0x160 - - WA - Description cluster[n]: Write access to peripheral region n detected - 0x000 - read-write - - - WA - 0 - 0 - - - - - RA - Description cluster[n]: Read access to peripheral region n detected - 0x004 - read-write - - - RA - 0 - 0 - - - - - INTEN - Enable or disable interrupt - 0x300 + INTENCLR + Disable interrupt + 0x308 read-write + 0x00000000 + 0x20 - REGION0WA - Enable or disable interrupt for REGION[0].WA event + READY + Write '1' to disable interrupt for event READY 0 0 + read Disabled - Disable - 0 + Read: Disabled + 0x0 Enabled - Enable - 1 + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 - REGION0RA - Enable or disable interrupt for REGION[0].RA event + DOWN + Write '1' to disable interrupt for event DOWN 1 1 + read Disabled - Disable - 0 + Read: Disabled + 0x0 Enabled - Enable - 1 + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 - REGION1WA - Enable or disable interrupt for REGION[1].WA event + UP + Write '1' to disable interrupt for event UP 2 2 + read Disabled - Disable - 0 + Read: Disabled + 0x0 Enabled - Enable - 1 + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 - REGION1RA - Enable or disable interrupt for REGION[1].RA event + CROSS + Write '1' to disable interrupt for event CROSS 3 3 + read Disabled - Disable - 0 + Read: Disabled + 0x0 Enabled - Enable - 1 + Read: Enabled + 0x1 - - - REGION2WA - Enable or disable interrupt for REGION[2].WA event - 4 - 4 + write - Disabled + Clear Disable - 0 - - - Enabled - Enable - 1 + 0x1 + + + + RESULT + Compare result + 0x400 + read-only + 0x00000000 + 0x20 + - REGION2RA - Enable or disable interrupt for REGION[2].RA event - 5 - 5 + RESULT + Result of last compare. Decision point SAMPLE task. + 0 + 0 - Disabled - Disable - 0 + Below + Input voltage is below the threshold (VIN+ &lt; VIN-) + 0x0 - Enabled - Enable - 1 + Above + Input voltage is above the threshold (VIN+ &gt; VIN-) + 0x1 + + + + ENABLE + COMP enable + 0x500 + read-write + 0x00000000 + 0x20 + - REGION3WA - Enable or disable interrupt for REGION[3].WA event - 6 - 6 + ENABLE + Enable or disable COMP + 0 + 1 Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x2 + + + + PSEL + Pin select + 0x504 + read-write + 0x00000000 + 0x20 + - REGION3RA - Enable or disable interrupt for REGION[3].RA event - 7 - 7 + PSEL + Analog pin select + 0 + 2 - Disabled - Disable - 0 + AnalogInput0 + AIN0 selected as analog input + 0x0 - Enabled - Enable - 1 + AnalogInput1 + AIN1 selected as analog input + 0x1 + + + AnalogInput2 + AIN2 selected as analog input + 0x2 + + + AnalogInput3 + AIN3 selected as analog input + 0x3 + + + AnalogInput4 + AIN4 selected as analog input + 0x4 + + + AnalogInput5 + AIN5 selected as analog input + 0x5 + + + AnalogInput6 + AIN6 selected as analog input + 0x6 + + + AnalogInput7 + AIN7 selected as analog input + 0x7 + + + + REFSEL + Reference source select for single-ended mode + 0x508 + read-write + 0x00000004 + 0x20 + - PREGION0WA - Enable or disable interrupt for PREGION[0].WA event - 24 - 24 + REFSEL + Reference select + 0 + 2 - Disabled - Disable - 0 + Int1V2 + VREF = internal 1.2 V reference (VDD &gt;= 1.7 V) + 0x0 - Enabled - Enable - 1 + Int1V8 + VREF = internal 1.8 V reference (VDD &gt;= VREF + 0.2 V) + 0x1 + + + Int2V4 + VREF = internal 2.4 V reference (VDD &gt;= VREF + 0.2 V) + 0x2 + + + VDD + VREF = VDD + 0x4 + + + ARef + VREF = AREF + 0x5 + + + + EXTREFSEL + External reference select + 0x50C + read-write + 0x00000000 + 0x20 + - PREGION0RA - Enable or disable interrupt for PREGION[0].RA event - 25 - 25 + EXTREFSEL + External analog reference select + 0 + 2 - Disabled - Disable - 0 + AnalogReference0 + Use AIN0 as external analog reference + 0x0 - Enabled - Enable - 1 + AnalogReference1 + Use AIN1 as external analog reference + 0x1 + + + AnalogReference2 + Use AIN2 as external analog reference + 0x2 + + + AnalogReference3 + Use AIN3 as external analog reference + 0x3 + + + AnalogReference4 + Use AIN4 as external analog reference + 0x4 + + + AnalogReference5 + Use AIN5 as external analog reference + 0x5 + + + AnalogReference6 + Use AIN6 as external analog reference + 0x6 + + + AnalogReference7 + Use AIN7 as external analog reference + 0x7 + + + + TH + Threshold configuration for hysteresis unit + 0x530 + read-write + 0x00000000 + 0x20 + - PREGION1WA - Enable or disable interrupt for PREGION[1].WA event - 26 - 26 + THDOWN + VDOWN = (THDOWN+1)/64*VREF + 0 + 5 + + + THUP + VUP = (THUP+1)/64*VREF + 8 + 13 + + + + + MODE + Mode configuration + 0x534 + read-write + 0x00000000 + 0x20 + + + SP + Speed and power modes + 0 + 1 - Disabled - Disable - 0 + Low + Low-power mode + 0x0 - Enabled - Enable - 1 + Normal + Normal mode + 0x1 + + + High + High-speed mode + 0x2 - PREGION1RA - Enable or disable interrupt for PREGION[1].RA event - 27 - 27 + MAIN + Main operation modes + 8 + 8 - Disabled - Disable - 0 + SE + Single-ended mode + 0x0 - Enabled - Enable - 1 + Diff + Differential mode + 0x1 - INTENSET - Enable interrupt - 0x304 + HYST + Comparator hysteresis enable + 0x538 read-write + 0x00000000 + 0x20 - REGION0WA - Write '1' to enable interrupt for REGION[0].WA event + HYST + Comparator hysteresis 0 0 - read - Disabled - Read: Disabled - 0 + NoHyst + Comparator hysteresis disabled + 0x0 - Enabled - Read: Enabled - 1 + Hyst50mV + Comparator hysteresis enabled + 0x1 + + + + + + + LPCOMP + Low-power comparator + 0x40013000 + COMP + + 0 + 0x1000 + registers + + + COMP_LPCOMP + 19 + + LPCOMP + 0x20 + + + TASKS_START + Start comparator + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start comparator + 0 + 0 - write - Set - Enable - 1 + Trigger + Trigger task + 0x1 + + + + TASKS_STOP + Stop comparator + 0x004 + write-only + 0x00000000 + 0x20 + - REGION0RA - Write '1' to enable interrupt for REGION[0].RA event - 1 - 1 + TASKS_STOP + Stop comparator + 0 + 0 - read - - Disabled - Read: Disabled - 0 - - Enabled - Read: Enabled - 1 + Trigger + Trigger task + 0x1 + + + + + TASKS_SAMPLE + Sample comparator value + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_SAMPLE + Sample comparator value + 0 + 0 - write - Set - Enable - 1 + Trigger + Trigger task + 0x1 + + + + EVENTS_READY + LPCOMP is ready and output is valid + 0x100 + read-write + 0x00000000 + 0x20 + - REGION1WA - Write '1' to enable interrupt for REGION[1].WA event - 2 - 2 + EVENTS_READY + LPCOMP is ready and output is valid + 0 + 0 - read - Disabled - Read: Disabled - 0 + NotGenerated + Event not generated + 0x0 - Enabled - Read: Enabled - 1 + Generated + Event generated + 0x1 + + + + + EVENTS_DOWN + Downward crossing + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_DOWN + Downward crossing + 0 + 0 - write - Set - Enable - 1 + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + EVENTS_UP + Upward crossing + 0x108 + read-write + 0x00000000 + 0x20 + - REGION1RA - Write '1' to enable interrupt for REGION[1].RA event - 3 - 3 + EVENTS_UP + Upward crossing + 0 + 0 - read - Disabled - Read: Disabled - 0 + NotGenerated + Event not generated + 0x0 - Enabled - Read: Enabled - 1 + Generated + Event generated + 0x1 + + + + + EVENTS_CROSS + Downward or upward crossing + 0x10C + read-write + 0x00000000 + 0x20 + + + EVENTS_CROSS + Downward or upward crossing + 0 + 0 - write - Set - Enable - 1 + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + - REGION2WA - Write '1' to enable interrupt for REGION[2].WA event - 4 - 4 + READY_SAMPLE + Shortcut between event READY and task SAMPLE + 0 + 0 - read Disabled - Read: Disabled - 0 + Disable shortcut + 0x0 Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 + Enable shortcut + 0x1 - REGION2RA - Write '1' to enable interrupt for REGION[2].RA event - 5 - 5 + READY_STOP + Shortcut between event READY and task STOP + 1 + 1 - read Disabled - Read: Disabled - 0 + Disable shortcut + 0x0 Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 + Enable shortcut + 0x1 - REGION3WA - Write '1' to enable interrupt for REGION[3].WA event - 6 - 6 + DOWN_STOP + Shortcut between event DOWN and task STOP + 2 + 2 - read Disabled - Read: Disabled - 0 + Disable shortcut + 0x0 Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 + Enable shortcut + 0x1 - REGION3RA - Write '1' to enable interrupt for REGION[3].RA event - 7 - 7 + UP_STOP + Shortcut between event UP and task STOP + 3 + 3 - read Disabled - Read: Disabled - 0 + Disable shortcut + 0x0 Enabled - Read: Enabled - 1 + Enable shortcut + 0x1 + + + CROSS_STOP + Shortcut between event CROSS and task STOP + 4 + 4 - write - Set - Enable - 1 + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + - PREGION0WA - Write '1' to enable interrupt for PREGION[0].WA event - 24 - 24 + READY + Write '1' to enable interrupt for event READY + 0 + 0 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -35474,26 +37229,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - PREGION0RA - Write '1' to enable interrupt for PREGION[0].RA event - 25 - 25 + DOWN + Write '1' to enable interrupt for event DOWN + 1 + 1 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -35501,26 +37256,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - PREGION1WA - Write '1' to enable interrupt for PREGION[1].WA event - 26 - 26 + UP + Write '1' to enable interrupt for event UP + 2 + 2 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -35528,26 +37283,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - PREGION1RA - Write '1' to enable interrupt for PREGION[1].RA event - 27 - 27 + CROSS + Write '1' to enable interrupt for event CROSS + 3 + 3 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -35555,7 +37310,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 @@ -35566,10 +37321,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disable interrupt 0x308 read-write + 0x00000000 + 0x20 - REGION0WA - Write '1' to disable interrupt for REGION[0].WA event + READY + Write '1' to disable interrupt for event READY 0 0 @@ -35577,12 +37334,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -35590,13 +37347,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - REGION0RA - Write '1' to disable interrupt for REGION[0].RA event + DOWN + Write '1' to disable interrupt for event DOWN 1 1 @@ -35604,12 +37361,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -35617,13 +37374,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - REGION1WA - Write '1' to disable interrupt for REGION[1].WA event + UP + Write '1' to disable interrupt for event UP 2 2 @@ -35631,12 +37388,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -35644,13 +37401,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - REGION1RA - Write '1' to disable interrupt for REGION[1].RA event + CROSS + Write '1' to disable interrupt for event CROSS 3 3 @@ -35658,12 +37415,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -35671,501 +37428,709 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 + + + + RESULT + Compare result + 0x400 + read-only + 0x00000000 + 0x20 + - REGION2WA - Write '1' to disable interrupt for REGION[2].WA event - 4 - 4 + RESULT + Result of last compare. Decision point SAMPLE task. + 0 + 0 - read - Disabled - Read: Disabled - 0 + Below + Input voltage is below the reference threshold (VIN+ &lt; VIN-) + 0x0 - Enabled - Read: Enabled - 1 + Above + Input voltage is above the reference threshold (VIN+ &gt; VIN-) + 0x1 + + + + + ENABLE + Enable LPCOMP + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable LPCOMP + 0 + 1 - write - Clear + Disabled Disable - 1 + 0x0 + + + Enabled + Enable + 0x1 + + + + PSEL + Input pin select + 0x504 + read-write + 0x00000000 + 0x20 + - REGION2RA - Write '1' to disable interrupt for REGION[2].RA event - 5 - 5 + PSEL + Analog pin select + 0 + 2 - read - Disabled - Read: Disabled - 0 + AnalogInput0 + AIN0 selected as analog input + 0x0 - Enabled - Read: Enabled - 1 + AnalogInput1 + AIN1 selected as analog input + 0x1 - - - write - Clear - Disable - 1 + AnalogInput2 + AIN2 selected as analog input + 0x2 - - - - REGION3WA - Write '1' to disable interrupt for REGION[3].WA event - 6 - 6 - - read - Disabled - Read: Disabled - 0 + AnalogInput3 + AIN3 selected as analog input + 0x3 - Enabled - Read: Enabled - 1 + AnalogInput4 + AIN4 selected as analog input + 0x4 - - - write - Clear - Disable - 1 + AnalogInput5 + AIN5 selected as analog input + 0x5 + + + AnalogInput6 + AIN6 selected as analog input + 0x6 + + + AnalogInput7 + AIN7 selected as analog input + 0x7 + + + + REFSEL + Reference select + 0x508 + read-write + 0x00000004 + 0x20 + - REGION3RA - Write '1' to disable interrupt for REGION[3].RA event - 7 - 7 + REFSEL + Reference select + 0 + 3 - read - Disabled - Read: Disabled - 0 + Ref1_8Vdd + VDD * 1/8 selected as reference + 0x0 - Enabled - Read: Enabled - 1 + Ref2_8Vdd + VDD * 2/8 selected as reference + 0x1 - - - write - Clear - Disable - 1 + Ref3_8Vdd + VDD * 3/8 selected as reference + 0x2 - - - - PREGION0WA - Write '1' to disable interrupt for PREGION[0].WA event - 24 - 24 - - read - Disabled - Read: Disabled - 0 + Ref4_8Vdd + VDD * 4/8 selected as reference + 0x3 - Enabled - Read: Enabled - 1 + Ref5_8Vdd + VDD * 5/8 selected as reference + 0x4 - - - write - Clear - Disable - 1 + Ref6_8Vdd + VDD * 6/8 selected as reference + 0x5 + + + Ref7_8Vdd + VDD * 7/8 selected as reference + 0x6 + + + ARef + External analog reference selected + 0x7 + + + Ref1_16Vdd + VDD * 1/16 selected as reference + 0x8 + + + Ref3_16Vdd + VDD * 3/16 selected as reference + 0x9 + + + Ref5_16Vdd + VDD * 5/16 selected as reference + 0xA + + + Ref7_16Vdd + VDD * 7/16 selected as reference + 0xB + + + Ref9_16Vdd + VDD * 9/16 selected as reference + 0xC + + + Ref11_16Vdd + VDD * 11/16 selected as reference + 0xD + + + Ref13_16Vdd + VDD * 13/16 selected as reference + 0xE + + + Ref15_16Vdd + VDD * 15/16 selected as reference + 0xF + + + + EXTREFSEL + External reference select + 0x50C + read-write + 0x00000000 + 0x20 + - PREGION0RA - Write '1' to disable interrupt for PREGION[0].RA event - 25 - 25 + EXTREFSEL + External analog reference select + 0 + 0 - read - Disabled - Read: Disabled - 0 + AnalogReference0 + Use AIN0 as external analog reference + 0x0 - Enabled - Read: Enabled - 1 + AnalogReference1 + Use AIN1 as external analog reference + 0x1 + + + + + ANADETECT + Analog detect configuration + 0x520 + read-write + 0x00000000 + 0x20 + + + ANADETECT + Analog detect configuration + 0 + 1 - write - Clear - Disable - 1 + Cross + Generate ANADETECT on crossing, both upward crossing and downward crossing + 0x0 + + + Up + Generate ANADETECT on upward crossing only + 0x1 + + + Down + Generate ANADETECT on downward crossing only + 0x2 + + + + HYST + Comparator hysteresis enable + 0x538 + read-write + 0x00000000 + 0x20 + - PREGION1WA - Write '1' to disable interrupt for PREGION[1].WA event - 26 - 26 + HYST + Comparator hysteresis enable + 0 + 0 - read Disabled - Read: Disabled - 0 + Comparator hysteresis disabled + 0x0 Enabled - Read: Enabled - 1 + Comparator hysteresis enabled + 0x1 + + + + + + + EGU0 + Event generator unit 0 + 0x40014000 + EGU + + 0 + 0x1000 + registers + + + EGU0_SWI0 + 20 + + EGU + 0x20 + + + 0x10 + 0x4 + TASKS_TRIGGER[%s] + Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_TRIGGER + Trigger n for triggering the corresponding TRIGGERED[n] event + 0 + 0 - write - Clear - Disable - 1 + Trigger + Trigger task + 0x1 + + + + 0x10 + 0x4 + EVENTS_TRIGGERED[%s] + Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task + 0x100 + read-write + 0x00000000 + 0x20 + - PREGION1RA - Write '1' to disable interrupt for PREGION[1].RA event - 27 - 27 + EVENTS_TRIGGERED + Event number n generated by triggering the corresponding TRIGGER[n] task + 0 + 0 - read - - Disabled - Read: Disabled - 0 - - Enabled - Read: Enabled - 1 + NotGenerated + Event not generated + 0x0 - - - write - Clear - Disable - 1 + Generated + Event generated + 0x1 - NMIEN - Enable or disable non-maskable interrupt - 0x320 + INTEN + Enable or disable interrupt + 0x300 read-write + 0x00000000 + 0x20 - REGION0WA - Enable or disable non-maskable interrupt for REGION[0].WA event + TRIGGERED0 + Enable or disable interrupt for event TRIGGERED[0] 0 0 Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 - REGION0RA - Enable or disable non-maskable interrupt for REGION[0].RA event + TRIGGERED1 + Enable or disable interrupt for event TRIGGERED[1] 1 1 Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 - REGION1WA - Enable or disable non-maskable interrupt for REGION[1].WA event + TRIGGERED2 + Enable or disable interrupt for event TRIGGERED[2] 2 2 Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 - REGION1RA - Enable or disable non-maskable interrupt for REGION[1].RA event + TRIGGERED3 + Enable or disable interrupt for event TRIGGERED[3] 3 3 Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 - REGION2WA - Enable or disable non-maskable interrupt for REGION[2].WA event + TRIGGERED4 + Enable or disable interrupt for event TRIGGERED[4] 4 4 Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 - REGION2RA - Enable or disable non-maskable interrupt for REGION[2].RA event + TRIGGERED5 + Enable or disable interrupt for event TRIGGERED[5] 5 5 Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 - REGION3WA - Enable or disable non-maskable interrupt for REGION[3].WA event + TRIGGERED6 + Enable or disable interrupt for event TRIGGERED[6] 6 6 Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 - REGION3RA - Enable or disable non-maskable interrupt for REGION[3].RA event + TRIGGERED7 + Enable or disable interrupt for event TRIGGERED[7] 7 7 Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 - PREGION0WA - Enable or disable non-maskable interrupt for PREGION[0].WA event - 24 - 24 + TRIGGERED8 + Enable or disable interrupt for event TRIGGERED[8] + 8 + 8 Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 - PREGION0RA - Enable or disable non-maskable interrupt for PREGION[0].RA event - 25 - 25 + TRIGGERED9 + Enable or disable interrupt for event TRIGGERED[9] + 9 + 9 Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 - PREGION1WA - Enable or disable non-maskable interrupt for PREGION[1].WA event - 26 - 26 + TRIGGERED10 + Enable or disable interrupt for event TRIGGERED[10] + 10 + 10 Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 - PREGION1RA - Enable or disable non-maskable interrupt for PREGION[1].RA event - 27 - 27 + TRIGGERED11 + Enable or disable interrupt for event TRIGGERED[11] + 11 + 11 Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 - - - - NMIENSET - Enable non-maskable interrupt - 0x324 - read-write - - REGION0WA - Write '1' to enable non-maskable interrupt for REGION[0].WA event - 0 - 0 + TRIGGERED12 + Enable or disable interrupt for event TRIGGERED[12] + 12 + 12 - read Disabled - Read: Disabled - 0 + Disable + 0x0 Enabled - Read: Enabled - 1 - - - - write - - Set Enable - 1 + 0x1 - REGION0RA - Write '1' to enable non-maskable interrupt for REGION[0].RA event - 1 - 1 - - read + TRIGGERED13 + Enable or disable interrupt for event TRIGGERED[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED14 + Enable or disable interrupt for event TRIGGERED[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED15 + Enable or disable interrupt for event TRIGGERED[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + TRIGGERED0 + Write '1' to enable interrupt for event TRIGGERED[0] + 0 + 0 + + read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -36173,13 +38138,40 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - REGION1WA - Write '1' to enable non-maskable interrupt for REGION[1].WA event + TRIGGERED1 + Write '1' to enable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED2 + Write '1' to enable interrupt for event TRIGGERED[2] 2 2 @@ -36187,12 +38179,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -36200,13 +38192,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - REGION1RA - Write '1' to enable non-maskable interrupt for REGION[1].RA event + TRIGGERED3 + Write '1' to enable interrupt for event TRIGGERED[3] 3 3 @@ -36214,12 +38206,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -36227,13 +38219,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - REGION2WA - Write '1' to enable non-maskable interrupt for REGION[2].WA event + TRIGGERED4 + Write '1' to enable interrupt for event TRIGGERED[4] 4 4 @@ -36241,12 +38233,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -36254,13 +38246,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - REGION2RA - Write '1' to enable non-maskable interrupt for REGION[2].RA event + TRIGGERED5 + Write '1' to enable interrupt for event TRIGGERED[5] 5 5 @@ -36268,12 +38260,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -36281,13 +38273,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - REGION3WA - Write '1' to enable non-maskable interrupt for REGION[3].WA event + TRIGGERED6 + Write '1' to enable interrupt for event TRIGGERED[6] 6 6 @@ -36295,12 +38287,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -36308,13 +38300,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - REGION3RA - Write '1' to enable non-maskable interrupt for REGION[3].RA event + TRIGGERED7 + Write '1' to enable interrupt for event TRIGGERED[7] 7 7 @@ -36322,12 +38314,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -36335,26 +38327,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - PREGION0WA - Write '1' to enable non-maskable interrupt for PREGION[0].WA event - 24 - 24 + TRIGGERED8 + Write '1' to enable interrupt for event TRIGGERED[8] + 8 + 8 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -36362,26 +38354,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - PREGION0RA - Write '1' to enable non-maskable interrupt for PREGION[0].RA event - 25 - 25 + TRIGGERED9 + Write '1' to enable interrupt for event TRIGGERED[9] + 9 + 9 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -36389,26 +38381,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - PREGION1WA - Write '1' to enable non-maskable interrupt for PREGION[1].WA event - 26 - 26 + TRIGGERED10 + Write '1' to enable interrupt for event TRIGGERED[10] + 10 + 10 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -36416,26 +38408,134 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - PREGION1RA - Write '1' to enable non-maskable interrupt for PREGION[1].RA event - 27 - 27 + TRIGGERED11 + Write '1' to enable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED12 + Write '1' to enable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED13 + Write '1' to enable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED14 + Write '1' to enable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED15 + Write '1' to enable interrupt for event TRIGGERED[15] + 15 + 15 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -36443,21 +38543,23 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - NMIENCLR - Disable non-maskable interrupt - 0x328 + INTENCLR + Disable interrupt + 0x308 read-write + 0x00000000 + 0x20 - REGION0WA - Write '1' to disable non-maskable interrupt for REGION[0].WA event + TRIGGERED0 + Write '1' to disable interrupt for event TRIGGERED[0] 0 0 @@ -36465,12 +38567,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -36478,13 +38580,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - REGION0RA - Write '1' to disable non-maskable interrupt for REGION[0].RA event + TRIGGERED1 + Write '1' to disable interrupt for event TRIGGERED[1] 1 1 @@ -36492,12 +38594,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -36505,13 +38607,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - REGION1WA - Write '1' to disable non-maskable interrupt for REGION[1].WA event + TRIGGERED2 + Write '1' to disable interrupt for event TRIGGERED[2] 2 2 @@ -36519,12 +38621,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -36532,13 +38634,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - REGION1RA - Write '1' to disable non-maskable interrupt for REGION[1].RA event + TRIGGERED3 + Write '1' to disable interrupt for event TRIGGERED[3] 3 3 @@ -36546,12 +38648,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -36559,13 +38661,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - REGION2WA - Write '1' to disable non-maskable interrupt for REGION[2].WA event + TRIGGERED4 + Write '1' to disable interrupt for event TRIGGERED[4] 4 4 @@ -36573,12 +38675,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -36586,13 +38688,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - REGION2RA - Write '1' to disable non-maskable interrupt for REGION[2].RA event + TRIGGERED5 + Write '1' to disable interrupt for event TRIGGERED[5] 5 5 @@ -36600,12 +38702,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -36613,13 +38715,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - REGION3WA - Write '1' to disable non-maskable interrupt for REGION[3].WA event + TRIGGERED6 + Write '1' to disable interrupt for event TRIGGERED[6] 6 6 @@ -36627,12 +38729,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -36640,13 +38742,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - REGION3RA - Write '1' to disable non-maskable interrupt for REGION[3].RA event + TRIGGERED7 + Write '1' to disable interrupt for event TRIGGERED[7] 7 7 @@ -36654,12 +38756,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -36667,26 +38769,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - PREGION0WA - Write '1' to disable non-maskable interrupt for PREGION[0].WA event - 24 - 24 + TRIGGERED8 + Write '1' to disable interrupt for event TRIGGERED[8] + 8 + 8 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -36694,26 +38796,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - PREGION0RA - Write '1' to disable non-maskable interrupt for PREGION[0].RA event - 25 - 25 + TRIGGERED9 + Write '1' to disable interrupt for event TRIGGERED[9] + 9 + 9 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -36721,26 +38823,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - PREGION1WA - Write '1' to disable non-maskable interrupt for PREGION[1].WA event - 26 - 26 + TRIGGERED10 + Write '1' to disable interrupt for event TRIGGERED[10] + 10 + 10 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -36748,26 +38850,134 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - PREGION1RA - Write '1' to disable non-maskable interrupt for PREGION[1].RA event - 27 - 27 + TRIGGERED11 + Write '1' to disable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED12 + Write '1' to disable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED13 + Write '1' to disable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED14 + Write '1' to disable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED15 + Write '1' to disable interrupt for event TRIGGERED[15] + 15 + 15 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -36775,2730 +38985,1359 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - - 2 - 0x008 - PERREGION[%s] - Unspecified - MWU_PERREGION - 0x400 - - SUBSTATWA - Description cluster[n]: Source of event/interrupt in region n, write access detected while corresponding subregion was enabled for watching - 0x000 - read-write - oneToClear - - - SR0 - Subregion 0 in region n (write '1' to clear) - 0 - 0 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR1 - Subregion 1 in region n (write '1' to clear) - 1 - 1 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR2 - Subregion 2 in region n (write '1' to clear) - 2 - 2 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR3 - Subregion 3 in region n (write '1' to clear) - 3 - 3 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR4 - Subregion 4 in region n (write '1' to clear) - 4 - 4 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR5 - Subregion 5 in region n (write '1' to clear) - 5 - 5 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR6 - Subregion 6 in region n (write '1' to clear) - 6 - 6 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR7 - Subregion 7 in region n (write '1' to clear) - 7 - 7 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR8 - Subregion 8 in region n (write '1' to clear) - 8 - 8 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR9 - Subregion 9 in region n (write '1' to clear) - 9 - 9 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR10 - Subregion 10 in region n (write '1' to clear) - 10 - 10 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR11 - Subregion 11 in region n (write '1' to clear) - 11 - 11 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR12 - Subregion 12 in region n (write '1' to clear) - 12 - 12 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR13 - Subregion 13 in region n (write '1' to clear) - 13 - 13 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR14 - Subregion 14 in region n (write '1' to clear) - 14 - 14 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR15 - Subregion 15 in region n (write '1' to clear) - 15 - 15 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR16 - Subregion 16 in region n (write '1' to clear) - 16 - 16 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR17 - Subregion 17 in region n (write '1' to clear) - 17 - 17 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR18 - Subregion 18 in region n (write '1' to clear) - 18 - 18 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR19 - Subregion 19 in region n (write '1' to clear) - 19 - 19 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR20 - Subregion 20 in region n (write '1' to clear) - 20 - 20 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR21 - Subregion 21 in region n (write '1' to clear) - 21 - 21 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR22 - Subregion 22 in region n (write '1' to clear) - 22 - 22 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR23 - Subregion 23 in region n (write '1' to clear) - 23 - 23 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR24 - Subregion 24 in region n (write '1' to clear) - 24 - 24 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR25 - Subregion 25 in region n (write '1' to clear) - 25 - 25 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR26 - Subregion 26 in region n (write '1' to clear) - 26 - 26 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR27 - Subregion 27 in region n (write '1' to clear) - 27 - 27 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR28 - Subregion 28 in region n (write '1' to clear) - 28 - 28 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR29 - Subregion 29 in region n (write '1' to clear) - 29 - 29 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR30 - Subregion 30 in region n (write '1' to clear) - 30 - 30 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR31 - Subregion 31 in region n (write '1' to clear) - 31 - 31 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - - - SUBSTATRA - Description cluster[n]: Source of event/interrupt in region n, read access detected while corresponding subregion was enabled for watching - 0x004 - read-write - oneToClear - - - SR0 - Subregion 0 in region n (write '1' to clear) - 0 - 0 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR1 - Subregion 1 in region n (write '1' to clear) - 1 - 1 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR2 - Subregion 2 in region n (write '1' to clear) - 2 - 2 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR3 - Subregion 3 in region n (write '1' to clear) - 3 - 3 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR4 - Subregion 4 in region n (write '1' to clear) - 4 - 4 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR5 - Subregion 5 in region n (write '1' to clear) - 5 - 5 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR6 - Subregion 6 in region n (write '1' to clear) - 6 - 6 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR7 - Subregion 7 in region n (write '1' to clear) - 7 - 7 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR8 - Subregion 8 in region n (write '1' to clear) - 8 - 8 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR9 - Subregion 9 in region n (write '1' to clear) - 9 - 9 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR10 - Subregion 10 in region n (write '1' to clear) - 10 - 10 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR11 - Subregion 11 in region n (write '1' to clear) - 11 - 11 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR12 - Subregion 12 in region n (write '1' to clear) - 12 - 12 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR13 - Subregion 13 in region n (write '1' to clear) - 13 - 13 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR14 - Subregion 14 in region n (write '1' to clear) - 14 - 14 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR15 - Subregion 15 in region n (write '1' to clear) - 15 - 15 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR16 - Subregion 16 in region n (write '1' to clear) - 16 - 16 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR17 - Subregion 17 in region n (write '1' to clear) - 17 - 17 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR18 - Subregion 18 in region n (write '1' to clear) - 18 - 18 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR19 - Subregion 19 in region n (write '1' to clear) - 19 - 19 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR20 - Subregion 20 in region n (write '1' to clear) - 20 - 20 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR21 - Subregion 21 in region n (write '1' to clear) - 21 - 21 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR22 - Subregion 22 in region n (write '1' to clear) - 22 - 22 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR23 - Subregion 23 in region n (write '1' to clear) - 23 - 23 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR24 - Subregion 24 in region n (write '1' to clear) - 24 - 24 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR25 - Subregion 25 in region n (write '1' to clear) - 25 - 25 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR26 - Subregion 26 in region n (write '1' to clear) - 26 - 26 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR27 - Subregion 27 in region n (write '1' to clear) - 27 - 27 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR28 - Subregion 28 in region n (write '1' to clear) - 28 - 28 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR29 - Subregion 29 in region n (write '1' to clear) - 29 - 29 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR30 - Subregion 30 in region n (write '1' to clear) - 30 - 30 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR31 - Subregion 31 in region n (write '1' to clear) - 31 - 31 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - - + + + + SWI0 + Software interrupt 0 + 0x40014000 + EGU0 + SWI + + 0 + 0x1000 + registers + + + EGU0_SWI0 + 20 + + SWI + 0x20 + - REGIONEN - Enable/disable regions watch - 0x510 - read-write + UNUSED + Unused. + 0x000 + 0x00000000 + read-only + + + + + EGU1 + Event generator unit 1 + 0x40015000 + + EGU1_SWI1 + 21 + + + + SWI1 + Software interrupt 1 + 0x40015000 + EGU1 + + EGU1_SWI1 + 21 + + + + EGU2 + Event generator unit 2 + 0x40016000 + + EGU2_SWI2 + 22 + + + + SWI2 + Software interrupt 2 + 0x40016000 + EGU2 + + EGU2_SWI2 + 22 + + + + EGU3 + Event generator unit 3 + 0x40017000 + + EGU3_SWI3 + 23 + + + + SWI3 + Software interrupt 3 + 0x40017000 + EGU3 + + EGU3_SWI3 + 23 + + + + EGU4 + Event generator unit 4 + 0x40018000 + + EGU4_SWI4 + 24 + + + + SWI4 + Software interrupt 4 + 0x40018000 + EGU4 + + EGU4_SWI4 + 24 + + + + EGU5 + Event generator unit 5 + 0x40019000 + + EGU5_SWI5 + 25 + + + + SWI5 + Software interrupt 5 + 0x40019000 + EGU5 + + EGU5_SWI5 + 25 + + + + TIMER3 + Timer/Counter 3 + 0x4001A000 + + TIMER3 + 26 + + + + TIMER4 + Timer/Counter 4 + 0x4001B000 + + TIMER4 + 27 + + + + PWM0 + Pulse width modulation unit 0 + 0x4001C000 + PWM + + 0 + 0x1000 + registers + + + PWM0 + 28 + + PWM + 0x20 + + + TASKS_STOP + Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback + 0x004 + write-only + 0x00000000 + 0x20 - RGN0WA - Enable/disable write access watch in region[0] + TASKS_STOP + Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback 0 0 - Disable - Disable write access watch in this region - 0 - - - Enable - Enable write access watch in this region - 1 + Trigger + Trigger task + 0x1 + + + + 0x2 + 0x4 + TASKS_SEQSTART[%s] + Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. + 0x008 + write-only + 0x00000000 + 0x20 + - RGN0RA - Enable/disable read access watch in region[0] - 1 - 1 + TASKS_SEQSTART + Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. + 0 + 0 - Disable - Disable read access watch in this region - 0 - - - Enable - Enable read access watch in this region - 1 + Trigger + Trigger task + 0x1 + + + + TASKS_NEXTSTEP + Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. + 0x010 + write-only + 0x00000000 + 0x20 + - RGN1WA - Enable/disable write access watch in region[1] - 2 - 2 + TASKS_NEXTSTEP + Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. + 0 + 0 - Disable - Disable write access watch in this region - 0 - - - Enable - Enable write access watch in this region - 1 + Trigger + Trigger task + 0x1 + + + + EVENTS_STOPPED + Response to STOP task, emitted when PWM pulses are no longer generated + 0x104 + read-write + 0x00000000 + 0x20 + - RGN1RA - Enable/disable read access watch in region[1] - 3 - 3 + EVENTS_STOPPED + Response to STOP task, emitted when PWM pulses are no longer generated + 0 + 0 - Disable - Disable read access watch in this region - 0 + NotGenerated + Event not generated + 0x0 - Enable - Enable read access watch in this region - 1 + Generated + Event generated + 0x1 + + + + 0x2 + 0x4 + EVENTS_SEQSTARTED[%s] + Description collection: First PWM period started on sequence n + 0x108 + read-write + 0x00000000 + 0x20 + - RGN2WA - Enable/disable write access watch in region[2] - 4 - 4 + EVENTS_SEQSTARTED + First PWM period started on sequence n + 0 + 0 - Disable - Disable write access watch in this region - 0 + NotGenerated + Event not generated + 0x0 - Enable - Enable write access watch in this region - 1 + Generated + Event generated + 0x1 + + + + 0x2 + 0x4 + EVENTS_SEQEND[%s] + Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter + 0x110 + read-write + 0x00000000 + 0x20 + - RGN2RA - Enable/disable read access watch in region[2] - 5 - 5 + EVENTS_SEQEND + Emitted at end of every sequence n, when last value from RAM has been applied to wave counter + 0 + 0 - Disable - Disable read access watch in this region - 0 + NotGenerated + Event not generated + 0x0 - Enable - Enable read access watch in this region - 1 + Generated + Event generated + 0x1 + + + + EVENTS_PWMPERIODEND + Emitted at the end of each PWM period + 0x118 + read-write + 0x00000000 + 0x20 + - RGN3WA - Enable/disable write access watch in region[3] - 6 - 6 + EVENTS_PWMPERIODEND + Emitted at the end of each PWM period + 0 + 0 - Disable - Disable write access watch in this region - 0 + NotGenerated + Event not generated + 0x0 - Enable - Enable write access watch in this region - 1 + Generated + Event generated + 0x1 - - RGN3RA - Enable/disable read access watch in region[3] - 7 - 7 + + + + EVENTS_LOOPSDONE + Concatenated sequences have been played the amount of times defined in LOOP.CNT + 0x11C + read-write + 0x00000000 + 0x20 + + + EVENTS_LOOPSDONE + Concatenated sequences have been played the amount of times defined in LOOP.CNT + 0 + 0 - Disable - Disable read access watch in this region - 0 + NotGenerated + Event not generated + 0x0 - Enable - Enable read access watch in this region - 1 + Generated + Event generated + 0x1 + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + - PRGN0WA - Enable/disable write access watch in PREGION[0] - 24 - 24 + SEQEND0_STOP + Shortcut between event SEQEND[0] and task STOP + 0 + 0 - Disable - Disable write access watch in this PREGION - 0 + Disabled + Disable shortcut + 0x0 - Enable - Enable write access watch in this PREGION - 1 + Enabled + Enable shortcut + 0x1 - PRGN0RA - Enable/disable read access watch in PREGION[0] - 25 - 25 + SEQEND1_STOP + Shortcut between event SEQEND[1] and task STOP + 1 + 1 - Disable - Disable read access watch in this PREGION - 0 + Disabled + Disable shortcut + 0x0 - Enable - Enable read access watch in this PREGION - 1 + Enabled + Enable shortcut + 0x1 - PRGN1WA - Enable/disable write access watch in PREGION[1] - 26 - 26 + LOOPSDONE_SEQSTART0 + Shortcut between event LOOPSDONE and task SEQSTART[0] + 2 + 2 - Disable - Disable write access watch in this PREGION - 0 + Disabled + Disable shortcut + 0x0 - Enable - Enable write access watch in this PREGION - 1 + Enabled + Enable shortcut + 0x1 - PRGN1RA - Enable/disable read access watch in PREGION[1] - 27 - 27 + LOOPSDONE_SEQSTART1 + Shortcut between event LOOPSDONE and task SEQSTART[1] + 3 + 3 - Disable - Disable read access watch in this PREGION - 0 + Disabled + Disable shortcut + 0x0 - Enable - Enable read access watch in this PREGION - 1 + Enabled + Enable shortcut + 0x1 - - - - REGIONENSET - Enable regions watch - 0x514 - read-write - - RGN0WA - Enable write access watch in region[0] - 0 - 0 + LOOPSDONE_STOP + Shortcut between event LOOPSDONE and task STOP + 4 + 4 - read Disabled - Write access watch in this region is disabled - 0 + Disable shortcut + 0x0 Enabled - Write access watch in this region is enabled - 1 - - - - write - - Set - Enable write access watch in this region - 1 + Enable shortcut + 0x1 + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + - RGN0RA - Enable read access watch in region[0] + STOPPED + Enable or disable interrupt for event STOPPED 1 1 - read Disabled - Read access watch in this region is disabled - 0 + Disable + 0x0 Enabled - Read access watch in this region is enabled - 1 - - - - write - - Set - Enable read access watch in this region - 1 + Enable + 0x1 - RGN1WA - Enable write access watch in region[1] + SEQSTARTED0 + Enable or disable interrupt for event SEQSTARTED[0] 2 2 - read Disabled - Write access watch in this region is disabled - 0 + Disable + 0x0 Enabled - Write access watch in this region is enabled - 1 - - - - write - - Set - Enable write access watch in this region - 1 + Enable + 0x1 - RGN1RA - Enable read access watch in region[1] + SEQSTARTED1 + Enable or disable interrupt for event SEQSTARTED[1] 3 3 - read Disabled - Read access watch in this region is disabled - 0 + Disable + 0x0 Enabled - Read access watch in this region is enabled - 1 - - - - write - - Set - Enable read access watch in this region - 1 + Enable + 0x1 - RGN2WA - Enable write access watch in region[2] + SEQEND0 + Enable or disable interrupt for event SEQEND[0] 4 4 - read Disabled - Write access watch in this region is disabled - 0 + Disable + 0x0 Enabled - Write access watch in this region is enabled - 1 + Enable + 0x1 + + + SEQEND1 + Enable or disable interrupt for event SEQEND[1] + 5 + 5 - write - Set - Enable write access watch in this region - 1 + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 - RGN2RA - Enable read access watch in region[2] - 5 - 5 + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 6 + 6 - read Disabled - Read access watch in this region is disabled - 0 + Disable + 0x0 Enabled - Read access watch in this region is enabled - 1 + Enable + 0x1 + + + LOOPSDONE + Enable or disable interrupt for event LOOPSDONE + 7 + 7 - write - Set - Enable read access watch in this region - 1 + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + - RGN3WA - Enable write access watch in region[3] - 6 - 6 + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 read Disabled - Write access watch in this region is disabled - 0 + Read: Disabled + 0x0 Enabled - Write access watch in this region is enabled - 1 + Read: Enabled + 0x1 write Set - Enable write access watch in this region - 1 + Enable + 0x1 - RGN3RA - Enable read access watch in region[3] - 7 - 7 + SEQSTARTED0 + Write '1' to enable interrupt for event SEQSTARTED[0] + 2 + 2 read Disabled - Read access watch in this region is disabled - 0 + Read: Disabled + 0x0 Enabled - Read access watch in this region is enabled - 1 + Read: Enabled + 0x1 write Set - Enable read access watch in this region - 1 + Enable + 0x1 - PRGN0WA - Enable write access watch in PREGION[0] - 24 - 24 + SEQSTARTED1 + Write '1' to enable interrupt for event SEQSTARTED[1] + 3 + 3 read Disabled - Write access watch in this PREGION is disabled - 0 + Read: Disabled + 0x0 Enabled - Write access watch in this PREGION is enabled - 1 + Read: Enabled + 0x1 write Set - Enable write access watch in this PREGION - 1 + Enable + 0x1 - PRGN0RA - Enable read access watch in PREGION[0] - 25 - 25 + SEQEND0 + Write '1' to enable interrupt for event SEQEND[0] + 4 + 4 read Disabled - Read access watch in this PREGION is disabled - 0 + Read: Disabled + 0x0 Enabled - Read access watch in this PREGION is enabled - 1 + Read: Enabled + 0x1 write Set - Enable read access watch in this PREGION - 1 + Enable + 0x1 - PRGN1WA - Enable write access watch in PREGION[1] - 26 - 26 + SEQEND1 + Write '1' to enable interrupt for event SEQEND[1] + 5 + 5 read Disabled - Write access watch in this PREGION is disabled - 0 + Read: Disabled + 0x0 Enabled - Write access watch in this PREGION is enabled - 1 + Read: Enabled + 0x1 write Set - Enable write access watch in this PREGION - 1 + Enable + 0x1 - PRGN1RA - Enable read access watch in PREGION[1] - 27 - 27 + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 6 + 6 read Disabled - Read access watch in this PREGION is disabled - 0 + Read: Disabled + 0x0 Enabled - Read access watch in this PREGION is enabled - 1 + Read: Enabled + 0x1 write Set - Enable read access watch in this PREGION - 1 + Enable + 0x1 - - - - REGIONENCLR - Disable regions watch - 0x518 - read-write - - RGN0WA - Disable write access watch in region[0] - 0 - 0 + LOOPSDONE + Write '1' to enable interrupt for event LOOPSDONE + 7 + 7 read Disabled - Write access watch in this region is disabled - 0 + Read: Disabled + 0x0 Enabled - Write access watch in this region is enabled - 1 + Read: Enabled + 0x1 write - Clear - Disable write access watch in this region - 1 + Set + Enable + 0x1 + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + - RGN0RA - Disable read access watch in region[0] + STOPPED + Write '1' to disable interrupt for event STOPPED 1 1 read Disabled - Read access watch in this region is disabled - 0 + Read: Disabled + 0x0 Enabled - Read access watch in this region is enabled - 1 + Read: Enabled + 0x1 write Clear - Disable read access watch in this region - 1 + Disable + 0x1 - RGN1WA - Disable write access watch in region[1] + SEQSTARTED0 + Write '1' to disable interrupt for event SEQSTARTED[0] 2 2 read Disabled - Write access watch in this region is disabled - 0 + Read: Disabled + 0x0 Enabled - Write access watch in this region is enabled - 1 + Read: Enabled + 0x1 write Clear - Disable write access watch in this region - 1 + Disable + 0x1 - RGN1RA - Disable read access watch in region[1] + SEQSTARTED1 + Write '1' to disable interrupt for event SEQSTARTED[1] 3 3 read Disabled - Read access watch in this region is disabled - 0 + Read: Disabled + 0x0 Enabled - Read access watch in this region is enabled - 1 + Read: Enabled + 0x1 write Clear - Disable read access watch in this region - 1 + Disable + 0x1 - RGN2WA - Disable write access watch in region[2] + SEQEND0 + Write '1' to disable interrupt for event SEQEND[0] 4 4 read Disabled - Write access watch in this region is disabled - 0 + Read: Disabled + 0x0 Enabled - Write access watch in this region is enabled - 1 + Read: Enabled + 0x1 write Clear - Disable write access watch in this region - 1 + Disable + 0x1 - RGN2RA - Disable read access watch in region[2] + SEQEND1 + Write '1' to disable interrupt for event SEQEND[1] 5 5 read Disabled - Read access watch in this region is disabled - 0 + Read: Disabled + 0x0 Enabled - Read access watch in this region is enabled - 1 + Read: Enabled + 0x1 write Clear - Disable read access watch in this region - 1 + Disable + 0x1 - RGN3WA - Disable write access watch in region[3] + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND 6 6 read Disabled - Write access watch in this region is disabled - 0 + Read: Disabled + 0x0 Enabled - Write access watch in this region is enabled - 1 + Read: Enabled + 0x1 write Clear - Disable write access watch in this region - 1 + Disable + 0x1 - RGN3RA - Disable read access watch in region[3] + LOOPSDONE + Write '1' to disable interrupt for event LOOPSDONE 7 7 read Disabled - Read access watch in this region is disabled - 0 + Read: Disabled + 0x0 Enabled - Read access watch in this region is enabled - 1 + Read: Enabled + 0x1 write Clear - Disable read access watch in this region - 1 + Disable + 0x1 + + + + ENABLE + PWM module enable register + 0x500 + read-write + 0x00000000 + 0x20 + - PRGN0WA - Disable write access watch in PREGION[0] - 24 - 24 + ENABLE + Enable or disable PWM module + 0 + 0 - read Disabled - Write access watch in this PREGION is disabled - 0 + Disabled + 0x0 Enabled - Write access watch in this PREGION is enabled - 1 + Enable + 0x1 + + + + + + + MODE + Selects operating mode of the wave counter + 0x504 + read-write + 0x00000000 + 0x20 + + + UPDOWN + Selects up mode or up-and-down mode for the counter + 0 + 0 + + + Up + Up counter, edge-aligned PWM duty cycle + 0x0 + + + UpAndDown + Up and down counter, center-aligned PWM duty cycle + 0x1 + + + + + COUNTERTOP + Value up to which the pulse generator counter counts + 0x508 + read-write + 0x000003FF + 0x20 + + + COUNTERTOP + Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. + 0 + 14 + + + + + PRESCALER + Configuration for PWM_CLK + 0x50C + read-write + 0x00000000 + 0x20 + + + PRESCALER + Prescaler of PWM_CLK + 0 + 2 - write - Clear - Disable write access watch in this PREGION - 1 + DIV_1 + Divide by 1 (16 MHz) + 0x0 + + + DIV_2 + Divide by 2 (8 MHz) + 0x1 + + + DIV_4 + Divide by 4 (4 MHz) + 0x2 + + + DIV_8 + Divide by 8 (2 MHz) + 0x3 + + + DIV_16 + Divide by 16 (1 MHz) + 0x4 - - - - PRGN0RA - Disable read access watch in PREGION[0] - 25 - 25 - - read - Disabled - Read access watch in this PREGION is disabled - 0 + DIV_32 + Divide by 32 (500 kHz) + 0x5 - Enabled - Read access watch in this PREGION is enabled - 1 + DIV_64 + Divide by 64 (250 kHz) + 0x6 - - - write - Clear - Disable read access watch in this PREGION - 1 + DIV_128 + Divide by 128 (125 kHz) + 0x7 + + + + DECODER + Configuration of the decoder + 0x510 + read-write + 0x00000000 + 0x20 + - PRGN1WA - Disable write access watch in PREGION[1] - 26 - 26 + LOAD + How a sequence is read from RAM and spread to the compare register + 0 + 1 - read - Disabled - Write access watch in this PREGION is disabled - 0 + Common + 1st half word (16-bit) used in all PWM channels 0..3 + 0x0 - Enabled - Write access watch in this PREGION is enabled - 1 + Grouped + 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 + 0x1 - - - write - Clear - Disable write access watch in this PREGION - 1 + Individual + 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 + 0x2 + + + WaveForm + 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP + 0x3 - PRGN1RA - Disable read access watch in PREGION[1] - 27 - 27 + MODE + Selects source for advancing the active sequence + 8 + 8 - read - - Disabled - Read access watch in this PREGION is disabled - 0 - - Enabled - Read access watch in this PREGION is enabled - 1 + RefreshCount + SEQ[n].REFRESH is used to determine loading internal compare registers + 0x0 - - - write - Clear - Disable read access watch in this PREGION - 1 - - - - - - - 4 - 0x010 - REGION[%s] - Unspecified - MWU_REGION - 0x600 - - START - Description cluster[n]: Start address for region n - 0x000 - read-write - 0x00000000 - - - START - Start address for region - 0 - 31 - - - - - END - Description cluster[n]: End address of region n - 0x004 - read-write - - - END - End address of region. - 0 - 31 - - - - - - 2 - 0x010 - PREGION[%s] - Unspecified - MWU_PREGION - 0x6C0 - - START - Description cluster[n]: Reserved for future use - 0x000 - read-only - - - START - Reserved for future use - 0 - 31 - - - - - END - Description cluster[n]: Reserved for future use - 0x004 - read-only - - - END - Reserved for future use - 0 - 31 - - - - - SUBS - Description cluster[n]: Subregions of region n - 0x008 - read-write - 0x00000000 - - - SR0 - Include or exclude subregion 0 in region - 0 - 0 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR1 - Include or exclude subregion 1 in region - 1 - 1 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR2 - Include or exclude subregion 2 in region - 2 - 2 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR3 - Include or exclude subregion 3 in region - 3 - 3 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR4 - Include or exclude subregion 4 in region - 4 - 4 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR5 - Include or exclude subregion 5 in region - 5 - 5 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR6 - Include or exclude subregion 6 in region - 6 - 6 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR7 - Include or exclude subregion 7 in region - 7 - 7 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR8 - Include or exclude subregion 8 in region - 8 - 8 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR9 - Include or exclude subregion 9 in region - 9 - 9 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR10 - Include or exclude subregion 10 in region - 10 - 10 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR11 - Include or exclude subregion 11 in region - 11 - 11 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR12 - Include or exclude subregion 12 in region - 12 - 12 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR13 - Include or exclude subregion 13 in region - 13 - 13 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR14 - Include or exclude subregion 14 in region - 14 - 14 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR15 - Include or exclude subregion 15 in region - 15 - 15 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR16 - Include or exclude subregion 16 in region - 16 - 16 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR17 - Include or exclude subregion 17 in region - 17 - 17 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR18 - Include or exclude subregion 18 in region - 18 - 18 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR19 - Include or exclude subregion 19 in region - 19 - 19 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR20 - Include or exclude subregion 20 in region - 20 - 20 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - + NextStep + NEXTSTEP task causes a new value to be loaded to internal compare registers + 0x1 + + + + + + + LOOP + Number of playbacks of a loop + 0x514 + read-write + 0x00000000 + 0x20 + + + CNT + Number of playbacks of pattern cycles + 0 + 15 + + + Disabled + Looping disabled (stop at the end of the sequence) + 0x0000 + + + + + + + 2 + 0x020 + SEQ[%s] + Unspecified + PWM_SEQ + read-write + 0x520 + + PTR + Description cluster: Beginning address in RAM of this sequence + 0x000 + read-write + 0x00000000 + 0x20 + - SR21 - Include or exclude subregion 21 in region - 21 - 21 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - + PTR + Beginning address in RAM of this sequence + 0 + 31 + + + + CNT + Description cluster: Number of values (duty cycles) in this sequence + 0x004 + read-write + 0x00000000 + 0x20 + - SR22 - Include or exclude subregion 22 in region - 22 - 22 + CNT + Number of values (duty cycles) in this sequence + 0 + 14 - Exclude - Exclude - 0 - - - Include - Include - 1 + Disabled + Sequence is disabled, and shall not be started as it is empty + 0x0000 + + + + REFRESH + Description cluster: Number of additional PWM periods between samples loaded into compare register + 0x008 + read-write + 0x00000001 + 0x20 + - SR23 - Include or exclude subregion 23 in region - 23 + CNT + Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) + 0 23 - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR24 - Include or exclude subregion 24 in region - 24 - 24 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR25 - Include or exclude subregion 25 in region - 25 - 25 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR26 - Include or exclude subregion 26 in region - 26 - 26 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR27 - Include or exclude subregion 27 in region - 27 - 27 - - - Exclude - Exclude - 0 - - - Include - Include - 1 + Continuous + Update every PWM period + 0x000000 + + + + ENDDELAY + Description cluster: Time added after the sequence + 0x00C + read-write + 0x00000000 + 0x20 + - SR28 - Include or exclude subregion 28 in region - 28 - 28 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - + CNT + Time added after the sequence in PWM periods + 0 + 23 + + + + + PSEL + Unspecified + PWM_PSEL + read-write + 0x560 + + 0x4 + 0x4 + OUT[%s] + Description collection: Output pin select for PWM channel n + 0x000 + read-write + 0xFFFFFFFF + 0x20 + - SR29 - Include or exclude subregion 29 in region - 29 - 29 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - + PIN + Pin number + 0 + 4 - SR30 - Include or exclude subregion 30 in region - 30 - 30 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - + PORT + Port number + 5 + 5 - SR31 - Include or exclude subregion 31 in region + CONNECT + Connection 31 31 - Exclude - Exclude - 0 + Disconnected + Disconnect + 0x1 - Include - Include - 1 + Connected + Connect + 0x0 @@ -39507,142 +40346,149 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ - - PWM1 - Pulse width modulation unit 1 - 0x40021000 - - PWM1 - 33 - - - - PWM2 - Pulse width modulation unit 2 - 0x40022000 - - PWM2 - 34 - - - - SPI2 - Serial Peripheral Interface 2 - 0x40023000 - - SPIM2_SPIS2_SPI2 - 35 - - - - SPIM2 - Serial Peripheral Interface Master with EasyDMA 2 - 0x40023000 - SPI2 - - SPIM2_SPIS2_SPI2 - 35 - - - - SPIS2 - SPI Slave 2 - 0x40023000 - SPI2 - - SPIM2_SPIS2_SPI2 - 35 - - - - RTC2 - Real time counter 2 - 0x40024000 - - RTC2 - 36 - - - I2S - Inter-IC Sound - 0x40025000 + PDM + Pulse Density Modulation (Digital Microphone) Interface + 0x4001D000 0 0x1000 registers - I2S - 37 + PDM + 29 - I2S + PDM 0x20 TASKS_START - Starts continuous I2S transfer. Also starts MCK generator when this is enabled. + Starts continuous PDM transfer 0x000 write-only + 0x00000000 + 0x20 TASKS_START + Starts continuous PDM transfer 0 0 + + + Trigger + Trigger task + 0x1 + + TASKS_STOP - Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the {event:STOPPED} event to be generated. + Stops PDM transfer 0x004 write-only + 0x00000000 + 0x20 TASKS_STOP + Stops PDM transfer 0 0 + + + Trigger + Trigger task + 0x1 + + - EVENTS_RXPTRUPD - The RXD.PTR register has been copied to internal double-buffers. - When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. - 0x104 + EVENTS_STARTED + PDM transfer has started + 0x100 read-write + 0x00000000 + 0x20 - EVENTS_RXPTRUPD + EVENTS_STARTED + PDM transfer has started 0 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + EVENTS_STOPPED - I2S transfer stopped. - 0x108 + PDM transfer has finished + 0x104 read-write + 0x00000000 + 0x20 EVENTS_STOPPED + PDM transfer has finished 0 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + - EVENTS_TXPTRUPD - The TDX.PTR register has been copied to internal double-buffers. - When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. - 0x114 + EVENTS_END + The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM + 0x108 read-write + 0x00000000 + 0x20 - EVENTS_TXPTRUPD + EVENTS_END + The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM 0 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + @@ -39651,58 +40497,60 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Enable or disable interrupt 0x300 read-write + 0x00000000 + 0x20 - RXPTRUPD - Enable or disable interrupt for RXPTRUPD event - 1 - 1 + STARTED + Enable or disable interrupt for event STARTED + 0 + 0 Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 STOPPED - Enable or disable interrupt for STOPPED event - 2 - 2 + Enable or disable interrupt for event STOPPED + 1 + 1 Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 - TXPTRUPD - Enable or disable interrupt for TXPTRUPD event - 5 - 5 + END + Enable or disable interrupt for event END + 2 + 2 Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -39713,10 +40561,39 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Enable interrupt 0x304 read-write + 0x00000000 + 0x20 - RXPTRUPD - Write '1' to enable interrupt for RXPTRUPD event + STARTED + Write '1' to enable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED 1 1 @@ -39724,12 +40601,39 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + END + Write '1' to enable interrupt for event END + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -39737,13 +40641,77 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + STARTED + Write '1' to disable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 STOPPED - Write '1' to enable interrupt for STOPPED event + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + END + Write '1' to disable interrupt for event END 2 2 @@ -39751,563 +40719,322 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Set - Enable - 1 + Clear + Disable + 0x1 + + + + ENABLE + PDM module enable register + 0x500 + read-write + 0x00000000 + 0x20 + - TXPTRUPD - Write '1' to enable interrupt for TXPTRUPD event - 5 - 5 + ENABLE + Enable or disable PDM module + 0 + 0 - read Disabled - Read: Disabled - 0 + Disable + 0x0 Enabled - Read: Enabled - 1 + Enable + 0x1 + + + + + PDMCLKCTRL + PDM clock generator control + 0x504 + read-write + 0x08400000 + 0x20 + + + FREQ + PDM_CLK frequency configuration + 0 + 31 - write - Set - Enable - 1 + 1000K + PDM_CLK = 32 MHz / 32 = 1.000 MHz + 0x08000000 + + + Default + PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64. + 0x08400000 + + + 1067K + PDM_CLK = 32 MHz / 30 = 1.067 MHz + 0x08800000 + + + 1231K + PDM_CLK = 32 MHz / 26 = 1.231 MHz + 0x09800000 + + + 1280K + PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80. + 0x0A000000 + + + 1333K + PDM_CLK = 32 MHz / 24 = 1.333 MHz + 0x0A800000 - INTENCLR - Disable interrupt - 0x308 + MODE + Defines the routing of the connected PDM microphones' signals + 0x508 read-write + 0x00000000 + 0x20 - RXPTRUPD - Write '1' to disable interrupt for RXPTRUPD event - 1 - 1 + OPERATION + Mono or stereo operation + 0 + 0 - read - Disabled - Read: Disabled - 0 + Stereo + Sample and store one pair (left + right) of 16-bit samples per RAM word R=[31:16]; L=[15:0] + 0x0 - Enabled - Read: Enabled - 1 + Mono + Sample and store two successive left samples (16 bits each) per RAM word L1=[31:16]; L0=[15:0] + 0x1 + + + EDGE + Defines on which PDM_CLK edge left (or mono) is sampled + 1 + 1 - write - Clear - Disable - 1 + LeftFalling + Left (or mono) is sampled on falling edge of PDM_CLK + 0x0 + + + LeftRising + Left (or mono) is sampled on rising edge of PDM_CLK + 0x1 + + + + GAINL + Left output gain adjustment + 0x518 + read-write + 0x00000028 + 0x20 + - STOPPED - Write '1' to disable interrupt for STOPPED event - 2 - 2 + GAINL + Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust + 0 + 6 - read - Disabled - Read: Disabled - 0 + MinGain + -20 dB gain adjustment (minimum) + 0x00 - Enabled - Read: Enabled - 1 + DefaultGain + 0 dB gain adjustment + 0x28 - - - write - Clear - Disable - 1 + MaxGain + +20 dB gain adjustment (maximum) + 0x50 + + + + GAINR + Right output gain adjustment + 0x51C + read-write + 0x00000028 + 0x20 + - TXPTRUPD - Write '1' to disable interrupt for TXPTRUPD event - 5 - 5 + GAINR + Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) + 0 + 6 - read - Disabled - Read: Disabled - 0 + MinGain + -20 dB gain adjustment (minimum) + 0x00 - Enabled - Read: Enabled - 1 + DefaultGain + 0 dB gain adjustment + 0x28 - - - write - Clear - Disable - 1 + MaxGain + +20 dB gain adjustment (maximum) + 0x50 - ENABLE - Enable I2S module. - 0x500 + RATIO + Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. + 0x520 read-write 0x00000000 + 0x20 - ENABLE - Enable I2S module. + RATIO + Selects the ratio between PDM_CLK and output sample rate 0 0 - Disabled - Disable - 0 + Ratio64 + Ratio of 64 + 0x0 - Enabled - Enable - 1 + Ratio80 + Ratio of 80 + 0x1 - CONFIG + PSEL Unspecified - I2S_CONFIG - 0x504 + PDM_PSEL + read-write + 0x540 - MODE - I2S mode. + CLK + Pin number configuration for PDM CLK signal 0x000 read-write - 0x00000000 - - - MODE - I2S mode. - 0 - 0 - - - Master - Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. - 0 - - - Slave - Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx - 1 - - - - - - - RXEN - Reception (RX) enable. - 0x004 - read-write - 0x00000000 - - - RXEN - Reception (RX) enable. - 0 - 0 - - - Disabled - Reception disabled and now data will be written to the RXD.PTR address. - 0 - - - Enabled - Reception enabled. - 1 - - - - - - - TXEN - Transmission (TX) enable. - 0x008 - read-write - 0x00000001 - - - TXEN - Transmission (TX) enable. - 0 - 0 - - - Disabled - Transmission disabled and now data will be read from the RXD.TXD address. - 0 - - - Enabled - Transmission enabled. - 1 - - - - - - - MCKEN - Master clock generator enable. - 0x00C - read-write - 0x00000001 - - - MCKEN - Master clock generator enable. - 0 - 0 - - - Disabled - Master clock generator disabled and PSEL.MCK not connected(available as GPIO). - 0 - - - Enabled - Master clock generator running and MCK output on PSEL.MCK. - 1 - - - - - - - MCKFREQ - Master clock generator frequency. - 0x010 - read-write - 0x20000000 - - - MCKFREQ - Master clock generator frequency. - 0 - 31 - - - 32MDIV2 - 32 MHz / 2 = 16.0 MHz - 0x80000000 - - - 32MDIV3 - 32 MHz / 3 = 10.6666667 MHz - 0x50000000 - - - 32MDIV4 - 32 MHz / 4 = 8.0 MHz - 0x40000000 - - - 32MDIV5 - 32 MHz / 5 = 6.4 MHz - 0x30000000 - - - 32MDIV6 - 32 MHz / 6 = 5.3333333 MHz - 0x28000000 - - - 32MDIV8 - 32 MHz / 8 = 4.0 MHz - 0x20000000 - - - 32MDIV10 - 32 MHz / 10 = 3.2 MHz - 0x18000000 - - - 32MDIV11 - 32 MHz / 11 = 2.9090909 MHz - 0x16000000 - - - 32MDIV15 - 32 MHz / 15 = 2.1333333 MHz - 0x11000000 - - - 32MDIV16 - 32 MHz / 16 = 2.0 MHz - 0x10000000 - - - 32MDIV21 - 32 MHz / 21 = 1.5238095 - 0x0C000000 - - - 32MDIV23 - 32 MHz / 23 = 1.3913043 MHz - 0x0B000000 - - - 32MDIV30 - 32 MHz / 30 = 1.0666667 MHz - 0x08800000 - - - 32MDIV31 - 32 MHz / 31 = 1.0322581 MHz - 0x08400000 - - - 32MDIV32 - 32 MHz / 32 = 1.0 MHz - 0x08000000 - - - 32MDIV42 - 32 MHz / 42 = 0.7619048 MHz - 0x06000000 - - - 32MDIV63 - 32 MHz / 63 = 0.5079365 MHz - 0x04100000 - - - 32MDIV125 - 32 MHz / 125 = 0.256 MHz - 0x020C0000 - - - - - - - RATIO - MCK / LRCK ratio. - 0x014 - read-write - 0x00000006 - - - RATIO - MCK / LRCK ratio. - 0 - 3 - - - 32X - LRCK = MCK / 32 - 0 - - - 48X - LRCK = MCK / 48 - 1 - - - 64X - LRCK = MCK / 64 - 2 - - - 96X - LRCK = MCK / 96 - 3 - - - 128X - LRCK = MCK / 128 - 4 - - - 192X - LRCK = MCK / 192 - 5 - - - 256X - LRCK = MCK / 256 - 6 - - - 384X - LRCK = MCK / 384 - 7 - - - 512X - LRCK = MCK / 512 - 8 - - - - - - - SWIDTH - Sample width. - 0x018 - read-write - 0x00000001 - - - SWIDTH - Sample width. - 0 - 1 - - - 8Bit - 8 bit. - 0 - - - 16Bit - 16 bit. - 1 - - - 24Bit - 24 bit. - 2 - - - - - - - ALIGN - Alignment of sample within a frame. - 0x01C - read-write - 0x00000000 + 0xFFFFFFFF + 0x20 - ALIGN - Alignment of sample within a frame. + PIN + Pin number 0 - 0 - - - Left - Left-aligned. - 0 - - - Right - Right-aligned. - 1 - - + 4 - - - - FORMAT - Frame format. - 0x020 - read-write - 0x00000000 - - FORMAT - Frame format. - 0 - 0 + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 - I2S - Original I2S format. - 0 + Disconnected + Disconnect + 0x1 - Aligned - Alternate (left- or right-aligned) format. - 1 + Connected + Connect + 0x0 - CHANNELS - Enable channels. - 0x024 + DIN + Pin number configuration for PDM DIN signal + 0x004 read-write - 0x00000000 + 0xFFFFFFFF + 0x20 - CHANNELS - Enable channels. + PIN + Pin number 0 - 1 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 - Stereo - Stereo. - 0 - - - Left - Left only. - 1 + Disconnected + Disconnect + 0x1 - Right - Right only. - 2 + Connected + Connect + 0x0 @@ -40315,1158 +41042,4104 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ - RXD + SAMPLE Unspecified - I2S_RXD - 0x538 + PDM_SAMPLE + read-write + 0x560 PTR - Receive buffer RAM start address. + RAM address pointer to write samples to with EasyDMA 0x000 read-write 0x00000000 + 0x20 - PTR - Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. + SAMPLEPTR + Address to write PDM samples to over DMA 0 31 - - - TXD - Unspecified - I2S_TXD - 0x540 - PTR - Transmit buffer RAM start address. - 0x000 + MAXCNT + Number of samples to allocate memory for in EasyDMA mode + 0x004 read-write 0x00000000 + 0x20 - PTR - Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. + BUFFSIZE + Length of DMA RAM allocation in number of samples 0 - 31 + 14 + + + + ACL + Access control lists + 0x4001E000 + + 0 + 0x1000 + registers + + ACL + 0x20 + - RXTXD + 8 + 0x010 + ACL[%s] Unspecified - I2S_RXTXD - 0x550 + ACL_ACL + read-write + 0x800 - MAXCNT - Size of RXD and TXD buffers. + ADDR + Description cluster: Start address of region to protect. The start address must be word-aligned. 0x000 - read-write + read-writeOnce 0x00000000 + 0x20 - MAXCNT - Size of RXD and TXD buffers in number of 32 bit words. + ADDR + Start address of flash region n. The start address must point to a flash page boundary. 0 - 13 + 31 - - - PSEL - Unspecified - I2S_PSEL - 0x560 - MCK - Pin select for MCK signal. - 0x000 - read-write - 0xFFFFFFFF + SIZE + Description cluster: Size of region to protect counting from address ACL[n].ADDR. Writing a '0' has no effect. + 0x004 + read-writeOnce + 0x00000000 + 0x20 - PIN - Pin number + SIZE + Size of flash region n in bytes. Must be a multiple of the flash page size. 0 - 4 + 31 + + + + PERM + Description cluster: Access permissions for region n as defined by start address ACL[n].ADDR and size ACL[n].SIZE + 0x008 + read-writeOnce + 0x00000000 + 0x20 + - PORT - Port number - 5 - 5 + WRITE + Configure write and erase permissions for region n. Writing a '0' has no effect. + 1 + 1 + + + Enable + Allow write and erase instructions to region n. + 0x0 + + + Disable + Block write and erase instructions to region n. + 0x1 + + - CONNECT - Connection - 31 - 31 + READ + Configure read permissions for region n. Writing a '0' has no effect. + 2 + 2 - Disconnected - Disconnect - 1 + Enable + Allow read instructions to region n. + 0x0 - Connected - Connect - 0 + Disable + Block read instructions to region n. + 0x1 + + + + + NVMC + Non Volatile Memory Controller + 0x4001E000 + ACL + + 0 + 0x1000 + registers + + NVMC + 0x20 + + + READY + Ready flag + 0x400 + read-only + 0x00000001 + 0x20 + + + READY + NVMC is ready or busy + 0 + 0 + + + Busy + NVMC is busy (on-going write or erase operation) + 0x0 + + + Ready + NVMC is ready + 0x1 + + + + + + + READYNEXT + Ready flag + 0x408 + read-only + 0x00000001 + 0x20 + + + READYNEXT + NVMC can accept a new write operation + 0 + 0 + + + Busy + NVMC cannot accept any write operation + 0x0 + + + Ready + NVMC is ready + 0x1 + + + + + + + CONFIG + Configuration register + 0x504 + read-write + 0x00000000 + 0x20 + + + WEN + Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. + 0 + 1 + + + Ren + Read only access + 0x0 + + + Wen + Write enabled + 0x1 + + + Een + Erase enabled + 0x2 + + + + + + + ERASEPAGE + Register for erasing a page in code area + 0x508 + write-only + 0x00000000 + 0x20 + + + ERASEPAGE + Register for starting erase of a page in code area + 0 + 31 + + + + + ERASEALL + Register for erasing all non-volatile user memory + 0x50C + write-only + 0x00000000 + 0x20 + + + ERASEALL + Erase all non-volatile memory including UICR registers. The erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased. + 0 + 0 + + + NoOperation + No operation + 0x0 + + + Erase + Start chip erase + 0x1 + + + + + + + ERASEUICR + Register for erasing user information configuration registers + 0x514 + write-only + 0x00000000 + 0x20 + + + ERASEUICR + Register starting erase of all user information configuration registers. The erase must be enabled using CONFIG.WEN before the UICR can be erased. + 0 + 0 + + + NoOperation + No operation + 0x0 + + + Erase + Start erase of UICR + 0x1 + + + + + + + ERASEPAGEPARTIAL + Register for partial erase of a page in code area + 0x518 + write-only + 0x00000000 + 0x20 + + + ERASEPAGEPARTIAL + Register for starting partial erase of a page in code area + 0 + 31 + + + + + ERASEPAGEPARTIALCFG + Register for partial erase configuration + 0x51C + read-write + 0x0000000A + 0x20 + + + DURATION + Duration of the partial erase in milliseconds + 0 + 6 + + + + + ICACHECNF + I-code cache configuration register + 0x540 + read-write + 0x00000000 + 0x20 + + + CACHEEN + Cache enable + 0 + 0 + + + Disabled + Disable cache. Invalidates all cache entries. + 0x0 + + + Enabled + Enable cache + 0x1 + + + + + CACHEPROFEN + Cache profiling enable + 8 + 8 + + + Disabled + Disable cache profiling + 0x0 + + + Enabled + Enable cache profiling + 0x1 + + + + + + + IHIT + I-code cache hit counter + 0x548 + read-write + 0x00000000 + 0x20 + + + HITS + Number of cache hits. Register is writable, but only to '0'. + 0 + 31 + + + + + IMISS + I-code cache miss counter + 0x54C + read-write + 0x00000000 + 0x20 + + + MISSES + Number of cache misses. Register is writable, but only to '0'. + 0 + 31 + + + + + + + PPI + Programmable Peripheral Interconnect + 0x4001F000 + + 0 + 0x1000 + registers + + PPI + 0x20 + + + 6 + 0x008 + TASKS_CHG[%s] + Channel group tasks + PPI_TASKS_CHG + write-only + 0x000 - SCK - Pin select for SCK signal. - 0x004 - read-write - 0xFFFFFFFF + EN + Description cluster: Enable channel group n + 0x000 + write-only + 0x00000000 + 0x20 - PIN - Pin number + EN + Enable channel group n 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 + 0 - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 + Trigger + Trigger task + 0x1 - LRCK - Pin select for LRCK signal. - 0x008 - read-write - 0xFFFFFFFF + DIS + Description cluster: Disable channel group n + 0x004 + write-only + 0x00000000 + 0x20 - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 + DIS + Disable channel group n + 0 + 0 - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 + Trigger + Trigger task + 0x1 + + + CHEN + Channel enable register + 0x500 + read-write + 0x00000000 + 0x20 + + + CH0 + Enable or disable channel 0 + 0 + 0 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH1 + Enable or disable channel 1 + 1 + 1 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH2 + Enable or disable channel 2 + 2 + 2 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH3 + Enable or disable channel 3 + 3 + 3 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH4 + Enable or disable channel 4 + 4 + 4 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH5 + Enable or disable channel 5 + 5 + 5 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH6 + Enable or disable channel 6 + 6 + 6 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH7 + Enable or disable channel 7 + 7 + 7 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH8 + Enable or disable channel 8 + 8 + 8 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH9 + Enable or disable channel 9 + 9 + 9 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH10 + Enable or disable channel 10 + 10 + 10 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH11 + Enable or disable channel 11 + 11 + 11 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH12 + Enable or disable channel 12 + 12 + 12 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH13 + Enable or disable channel 13 + 13 + 13 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH14 + Enable or disable channel 14 + 14 + 14 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH15 + Enable or disable channel 15 + 15 + 15 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH16 + Enable or disable channel 16 + 16 + 16 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH17 + Enable or disable channel 17 + 17 + 17 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH18 + Enable or disable channel 18 + 18 + 18 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH19 + Enable or disable channel 19 + 19 + 19 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH20 + Enable or disable channel 20 + 20 + 20 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH21 + Enable or disable channel 21 + 21 + 21 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH22 + Enable or disable channel 22 + 22 + 22 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH23 + Enable or disable channel 23 + 23 + 23 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH24 + Enable or disable channel 24 + 24 + 24 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH25 + Enable or disable channel 25 + 25 + 25 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH26 + Enable or disable channel 26 + 26 + 26 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH27 + Enable or disable channel 27 + 27 + 27 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH28 + Enable or disable channel 28 + 28 + 28 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH29 + Enable or disable channel 29 + 29 + 29 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH30 + Enable or disable channel 30 + 30 + 30 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH31 + Enable or disable channel 31 + 31 + 31 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + + + CHENSET + Channel enable set register + 0x504 + read-write + 0x00000000 + oneToSet + 0x20 + + + CH0 + Channel 0 enable set register. Writing '0' has no effect. + 0 + 0 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH1 + Channel 1 enable set register. Writing '0' has no effect. + 1 + 1 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH2 + Channel 2 enable set register. Writing '0' has no effect. + 2 + 2 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH3 + Channel 3 enable set register. Writing '0' has no effect. + 3 + 3 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH4 + Channel 4 enable set register. Writing '0' has no effect. + 4 + 4 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH5 + Channel 5 enable set register. Writing '0' has no effect. + 5 + 5 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH6 + Channel 6 enable set register. Writing '0' has no effect. + 6 + 6 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH7 + Channel 7 enable set register. Writing '0' has no effect. + 7 + 7 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH8 + Channel 8 enable set register. Writing '0' has no effect. + 8 + 8 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH9 + Channel 9 enable set register. Writing '0' has no effect. + 9 + 9 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH10 + Channel 10 enable set register. Writing '0' has no effect. + 10 + 10 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH11 + Channel 11 enable set register. Writing '0' has no effect. + 11 + 11 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH12 + Channel 12 enable set register. Writing '0' has no effect. + 12 + 12 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH13 + Channel 13 enable set register. Writing '0' has no effect. + 13 + 13 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH14 + Channel 14 enable set register. Writing '0' has no effect. + 14 + 14 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH15 + Channel 15 enable set register. Writing '0' has no effect. + 15 + 15 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH16 + Channel 16 enable set register. Writing '0' has no effect. + 16 + 16 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH17 + Channel 17 enable set register. Writing '0' has no effect. + 17 + 17 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH18 + Channel 18 enable set register. Writing '0' has no effect. + 18 + 18 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH19 + Channel 19 enable set register. Writing '0' has no effect. + 19 + 19 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH20 + Channel 20 enable set register. Writing '0' has no effect. + 20 + 20 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH21 + Channel 21 enable set register. Writing '0' has no effect. + 21 + 21 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH22 + Channel 22 enable set register. Writing '0' has no effect. + 22 + 22 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH23 + Channel 23 enable set register. Writing '0' has no effect. + 23 + 23 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH24 + Channel 24 enable set register. Writing '0' has no effect. + 24 + 24 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH25 + Channel 25 enable set register. Writing '0' has no effect. + 25 + 25 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH26 + Channel 26 enable set register. Writing '0' has no effect. + 26 + 26 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH27 + Channel 27 enable set register. Writing '0' has no effect. + 27 + 27 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH28 + Channel 28 enable set register. Writing '0' has no effect. + 28 + 28 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH29 + Channel 29 enable set register. Writing '0' has no effect. + 29 + 29 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH30 + Channel 30 enable set register. Writing '0' has no effect. + 30 + 30 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH31 + Channel 31 enable set register. Writing '0' has no effect. + 31 + 31 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + + + CHENCLR + Channel enable clear register + 0x508 + read-write + 0x00000000 + oneToClear + 0x20 + + + CH0 + Channel 0 enable clear register. Writing '0' has no effect. + 0 + 0 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Clear + Write: disable channel + 0x1 + + + + + CH1 + Channel 1 enable clear register. Writing '0' has no effect. + 1 + 1 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Clear + Write: disable channel + 0x1 + + + + + CH2 + Channel 2 enable clear register. Writing '0' has no effect. + 2 + 2 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Clear + Write: disable channel + 0x1 + + + + + CH3 + Channel 3 enable clear register. Writing '0' has no effect. + 3 + 3 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Clear + Write: disable channel + 0x1 + + + + + CH4 + Channel 4 enable clear register. Writing '0' has no effect. + 4 + 4 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Clear + Write: disable channel + 0x1 + + + + + CH5 + Channel 5 enable clear register. Writing '0' has no effect. + 5 + 5 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Clear + Write: disable channel + 0x1 + + + + + CH6 + Channel 6 enable clear register. Writing '0' has no effect. + 6 + 6 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Clear + Write: disable channel + 0x1 + + + + + CH7 + Channel 7 enable clear register. Writing '0' has no effect. + 7 + 7 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Clear + Write: disable channel + 0x1 + + + + + CH8 + Channel 8 enable clear register. Writing '0' has no effect. + 8 + 8 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Clear + Write: disable channel + 0x1 + + + + + CH9 + Channel 9 enable clear register. Writing '0' has no effect. + 9 + 9 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Clear + Write: disable channel + 0x1 + + + + + CH10 + Channel 10 enable clear register. Writing '0' has no effect. + 10 + 10 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Clear + Write: disable channel + 0x1 + + + + + CH11 + Channel 11 enable clear register. Writing '0' has no effect. + 11 + 11 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Clear + Write: disable channel + 0x1 + + + + + CH12 + Channel 12 enable clear register. Writing '0' has no effect. + 12 + 12 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Clear + Write: disable channel + 0x1 + + + + + CH13 + Channel 13 enable clear register. Writing '0' has no effect. + 13 + 13 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Clear + Write: disable channel + 0x1 + + + + + CH14 + Channel 14 enable clear register. Writing '0' has no effect. + 14 + 14 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Clear + Write: disable channel + 0x1 + + + + + CH15 + Channel 15 enable clear register. Writing '0' has no effect. + 15 + 15 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Clear + Write: disable channel + 0x1 + + + + + CH16 + Channel 16 enable clear register. Writing '0' has no effect. + 16 + 16 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Clear + Write: disable channel + 0x1 + + + + + CH17 + Channel 17 enable clear register. Writing '0' has no effect. + 17 + 17 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Clear + Write: disable channel + 0x1 + + + + + CH18 + Channel 18 enable clear register. Writing '0' has no effect. + 18 + 18 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Clear + Write: disable channel + 0x1 + + + + + CH19 + Channel 19 enable clear register. Writing '0' has no effect. + 19 + 19 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Clear + Write: disable channel + 0x1 + + + + + CH20 + Channel 20 enable clear register. Writing '0' has no effect. + 20 + 20 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Clear + Write: disable channel + 0x1 + + + + + CH21 + Channel 21 enable clear register. Writing '0' has no effect. + 21 + 21 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Clear + Write: disable channel + 0x1 + + + + + CH22 + Channel 22 enable clear register. Writing '0' has no effect. + 22 + 22 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Clear + Write: disable channel + 0x1 + + + + + CH23 + Channel 23 enable clear register. Writing '0' has no effect. + 23 + 23 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Clear + Write: disable channel + 0x1 + + + + + CH24 + Channel 24 enable clear register. Writing '0' has no effect. + 24 + 24 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Clear + Write: disable channel + 0x1 + + + + + CH25 + Channel 25 enable clear register. Writing '0' has no effect. + 25 + 25 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Clear + Write: disable channel + 0x1 + + + + + CH26 + Channel 26 enable clear register. Writing '0' has no effect. + 26 + 26 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Clear + Write: disable channel + 0x1 + + + + + CH27 + Channel 27 enable clear register. Writing '0' has no effect. + 27 + 27 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Clear + Write: disable channel + 0x1 + + + + + CH28 + Channel 28 enable clear register. Writing '0' has no effect. + 28 + 28 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Clear + Write: disable channel + 0x1 + + + + + CH29 + Channel 29 enable clear register. Writing '0' has no effect. + 29 + 29 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Clear + Write: disable channel + 0x1 + + + + + CH30 + Channel 30 enable clear register. Writing '0' has no effect. + 30 + 30 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Clear + Write: disable channel + 0x1 + + + + + CH31 + Channel 31 enable clear register. Writing '0' has no effect. + 31 + 31 + + read + + Disabled + Read: channel disabled + 0x0 + + + Enabled + Read: channel enabled + 0x1 + + + + write + + Clear + Write: disable channel + 0x1 + + + + + + + 20 + 0x008 + CH[%s] + PPI Channel + PPI_CH + read-write + 0x510 - SDIN - Pin select for SDIN signal. - 0x00C + EEP + Description cluster: Channel n event endpoint + 0x000 read-write - 0xFFFFFFFF + 0x00000000 + 0x20 - PIN - Pin number + EEP + Pointer to event register. Accepts only addresses to registers from the Event group. 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - SDOUT - Pin select for SDOUT signal. - 0x010 + TEP + Description cluster: Channel n task endpoint + 0x004 read-write - 0xFFFFFFFF + 0x00000000 + 0x20 - PIN - Pin number + TEP + Pointer to task register. Accepts only addresses to registers from the Task group. 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - FPU - FPU - 0x40026000 - - 0 - 0x1000 - registers - - - FPU - 38 - - FPU - 0x20 - - - UNUSED - Unused. - 0x000 - 0x00000000 - read-only - - - - - USBD - Universal serial bus device - 0x40027000 - - 0 - 0x1000 - registers - - - USBD - 39 - - USBD - 0x20 - - 8 + 0x6 0x4 - TASKS_STARTEPIN[%s] - Description collection[n]: Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host - 0x004 - write-only + CHG[%s] + Description collection: Channel group n + 0x800 + read-write + 0x00000000 + 0x20 - TASKS_STARTEPIN + CH0 + Include or exclude channel 0 0 0 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + - - - - TASKS_STARTISOIN - Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint - 0x024 - write-only - - TASKS_STARTISOIN - 0 - 0 + CH1 + Include or exclude channel 1 + 1 + 1 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + - - - - 8 - 0x4 - TASKS_STARTEPOUT[%s] - Description collection[n]: Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host - 0x028 - write-only - - TASKS_STARTEPOUT - 0 - 0 + CH2 + Include or exclude channel 2 + 2 + 2 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + - - - - TASKS_STARTISOOUT - Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint - 0x048 - write-only - - TASKS_STARTISOOUT - 0 - 0 + CH3 + Include or exclude channel 3 + 3 + 3 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + - - - - TASKS_EP0RCVOUT - Allows OUT data stage on control endpoint 0 - 0x04C - write-only - - TASKS_EP0RCVOUT - 0 - 0 + CH4 + Include or exclude channel 4 + 4 + 4 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + - - - - TASKS_EP0STATUS - Allows status stage on control endpoint 0 - 0x050 - write-only - - TASKS_EP0STATUS - 0 - 0 + CH5 + Include or exclude channel 5 + 5 + 5 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + - - - - TASKS_EP0STALL - Stalls data and status stage on control endpoint 0 - 0x054 - write-only - - TASKS_EP0STALL - 0 - 0 + CH6 + Include or exclude channel 6 + 6 + 6 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + - - - - TASKS_DPDMDRIVE - Forces D+ and D- lines into the state defined in the DPDMVALUE register - 0x058 - write-only - - TASKS_DPDMDRIVE - 0 - 0 + CH7 + Include or exclude channel 7 + 7 + 7 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH8 + Include or exclude channel 8 + 8 + 8 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH9 + Include or exclude channel 9 + 9 + 9 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH10 + Include or exclude channel 10 + 10 + 10 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH11 + Include or exclude channel 11 + 11 + 11 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH12 + Include or exclude channel 12 + 12 + 12 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH13 + Include or exclude channel 13 + 13 + 13 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH14 + Include or exclude channel 14 + 14 + 14 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + - - - - TASKS_DPDMNODRIVE - Stops forcing D+ and D- lines into any state (USB engine takes control) - 0x05C - write-only - - TASKS_DPDMNODRIVE - 0 - 0 + CH15 + Include or exclude channel 15 + 15 + 15 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + - - - - EVENTS_USBRESET - Signals that a USB reset condition has been detected on USB lines - 0x100 - read-write - - EVENTS_USBRESET - 0 - 0 + CH16 + Include or exclude channel 16 + 16 + 16 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + - - - - EVENTS_STARTED - Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register - 0x104 - read-write - - EVENTS_STARTED - 0 - 0 + CH17 + Include or exclude channel 17 + 17 + 17 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + - - - - 8 - 0x4 - EVENTS_ENDEPIN[%s] - Description collection[n]: The whole EPIN[n] buffer has been consumed. The RAM buffer can be accessed safely by software. - 0x108 - read-write - - EVENTS_ENDEPIN - 0 - 0 + CH18 + Include or exclude channel 18 + 18 + 18 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + - - - - EVENTS_EP0DATADONE - An acknowledged data transfer has taken place on the control endpoint - 0x128 - read-write - - EVENTS_EP0DATADONE - 0 - 0 + CH19 + Include or exclude channel 19 + 19 + 19 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + - - - - EVENTS_ENDISOIN - The whole ISOIN buffer has been consumed. The RAM buffer can be accessed safely by software. - 0x12C - read-write - - EVENTS_ENDISOIN - 0 - 0 + CH20 + Include or exclude channel 20 + 20 + 20 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + - - - - 8 - 0x4 - EVENTS_ENDEPOUT[%s] - Description collection[n]: The whole EPOUT[n] buffer has been consumed. The RAM buffer can be accessed safely by software. - 0x130 - read-write - - EVENTS_ENDEPOUT - 0 - 0 + CH21 + Include or exclude channel 21 + 21 + 21 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + - - - - EVENTS_ENDISOOUT - The whole ISOOUT buffer has been consumed. The RAM buffer can be accessed safely by software. - 0x150 - read-write - - EVENTS_ENDISOOUT - 0 - 0 + CH22 + Include or exclude channel 22 + 22 + 22 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + - - - - EVENTS_SOF - Signals that a SOF (start of frame) condition has been detected on USB lines - 0x154 - read-write - - EVENTS_SOF - 0 - 0 + CH23 + Include or exclude channel 23 + 23 + 23 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + - - - - EVENTS_USBEVENT - An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. - 0x158 - read-write - - EVENTS_USBEVENT - 0 - 0 + CH24 + Include or exclude channel 24 + 24 + 24 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + - - - - EVENTS_EP0SETUP - A valid SETUP token has been received (and acknowledged) on the control endpoint - 0x15C - read-write - - EVENTS_EP0SETUP - 0 - 0 + CH25 + Include or exclude channel 25 + 25 + 25 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + - - - - EVENTS_EPDATA - A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register - 0x160 - read-write - - EVENTS_EPDATA - 0 - 0 + CH26 + Include or exclude channel 26 + 26 + 26 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + - - - - SHORTS - Shortcut register - 0x200 - read-write - - EP0DATADONE_STARTEPIN0 - Shortcut between EP0DATADONE event and STARTEPIN[0] task - 0 - 0 + CH27 + Include or exclude channel 27 + 27 + 27 - Disabled - Disable shortcut - 0 + Excluded + Exclude + 0x0 - Enabled - Enable shortcut - 1 + Included + Include + 0x1 - EP0DATADONE_STARTEPOUT0 - Shortcut between EP0DATADONE event and STARTEPOUT[0] task - 1 - 1 + CH28 + Include or exclude channel 28 + 28 + 28 - Disabled - Disable shortcut - 0 + Excluded + Exclude + 0x0 - Enabled - Enable shortcut - 1 + Included + Include + 0x1 - EP0DATADONE_EP0STATUS - Shortcut between EP0DATADONE event and EP0STATUS task - 2 - 2 + CH29 + Include or exclude channel 29 + 29 + 29 - Disabled - Disable shortcut - 0 + Excluded + Exclude + 0x0 - Enabled - Enable shortcut - 1 + Included + Include + 0x1 - ENDEPOUT0_EP0STATUS - Shortcut between ENDEPOUT[0] event and EP0STATUS task - 3 - 3 + CH30 + Include or exclude channel 30 + 30 + 30 - Disabled - Disable shortcut - 0 + Excluded + Exclude + 0x0 - Enabled - Enable shortcut - 1 + Included + Include + 0x1 - ENDEPOUT0_EP0RCVOUT - Shortcut between ENDEPOUT[0] event and EP0RCVOUT task - 4 - 4 + CH31 + Include or exclude channel 31 + 31 + 31 - Disabled - Disable shortcut - 0 + Excluded + Exclude + 0x0 - Enabled - Enable shortcut - 1 + Included + Include + 0x1 + + 32 + 0x004 + FORK[%s] + Fork + PPI_FORK + read-write + 0x910 + + TEP + Description cluster: Channel n task endpoint + 0x000 + read-write + 0x00000000 + 0x20 + + + TEP + Pointer to task register + 0 + 31 + + + + + + + + MWU + Memory Watch Unit + 0x40020000 + + 0 + 0x1000 + registers + + + MWU + 32 + + MWU + 0x20 + + + 4 + 0x008 + EVENTS_REGION[%s] + Peripheral events. + MWU_EVENTS_REGION + read-write + 0x100 + + WA + Description cluster: Write access to region n detected + 0x000 + read-write + 0x00000000 + 0x20 + + + WA + Write access to region n detected + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + RA + Description cluster: Read access to region n detected + 0x004 + read-write + 0x00000000 + 0x20 + + + RA + Read access to region n detected + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + 2 + 0x008 + EVENTS_PREGION[%s] + Peripheral events. + MWU_EVENTS_PREGION + read-write + 0x160 + + WA + Description cluster: Write access to peripheral region n detected + 0x000 + read-write + 0x00000000 + 0x20 + + + WA + Write access to peripheral region n detected + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + RA + Description cluster: Read access to peripheral region n detected + 0x004 + read-write + 0x00000000 + 0x20 + + + RA + Read access to peripheral region n detected + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + INTEN Enable or disable interrupt 0x300 read-write + 0x00000000 + 0x20 - USBRESET - Enable or disable interrupt for USBRESET event + REGION0WA + Enable or disable interrupt for event REGION0WA 0 0 Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 - STARTED - Enable or disable interrupt for STARTED event + REGION0RA + Enable or disable interrupt for event REGION0RA 1 1 Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 - ENDEPIN0 - Enable or disable interrupt for ENDEPIN[0] event + REGION1WA + Enable or disable interrupt for event REGION1WA 2 2 Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 - ENDEPIN1 - Enable or disable interrupt for ENDEPIN[1] event + REGION1RA + Enable or disable interrupt for event REGION1RA 3 3 Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 - ENDEPIN2 - Enable or disable interrupt for ENDEPIN[2] event + REGION2WA + Enable or disable interrupt for event REGION2WA 4 4 Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 - ENDEPIN3 - Enable or disable interrupt for ENDEPIN[3] event + REGION2RA + Enable or disable interrupt for event REGION2RA 5 5 Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 - ENDEPIN4 - Enable or disable interrupt for ENDEPIN[4] event + REGION3WA + Enable or disable interrupt for event REGION3WA 6 6 Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 - ENDEPIN5 - Enable or disable interrupt for ENDEPIN[5] event + REGION3RA + Enable or disable interrupt for event REGION3RA 7 7 Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 - ENDEPIN6 - Enable or disable interrupt for ENDEPIN[6] event - 8 - 8 + PREGION0WA + Enable or disable interrupt for event PREGION0WA + 24 + 24 Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 - ENDEPIN7 - Enable or disable interrupt for ENDEPIN[7] event - 9 - 9 + PREGION0RA + Enable or disable interrupt for event PREGION0RA + 25 + 25 Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 - EP0DATADONE - Enable or disable interrupt for EP0DATADONE event - 10 - 10 + PREGION1WA + Enable or disable interrupt for event PREGION1WA + 26 + 26 Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 - ENDISOIN - Enable or disable interrupt for ENDISOIN event - 11 - 11 + PREGION1RA + Enable or disable interrupt for event PREGION1RA + 27 + 27 Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + - ENDEPOUT0 - Enable or disable interrupt for ENDEPOUT[0] event - 12 - 12 + REGION0WA + Write '1' to enable interrupt for event REGION0WA + 0 + 0 + read Disabled - Disable - 0 + Read: Disabled + 0x0 Enabled - Enable - 1 + Read: Enabled + 0x1 - - - ENDEPOUT1 - Enable or disable interrupt for ENDEPOUT[1] event - 13 - 13 + write - Disabled - Disable - 0 - - - Enabled + Set Enable - 1 + 0x1 - ENDEPOUT2 - Enable or disable interrupt for ENDEPOUT[2] event - 14 - 14 + REGION0RA + Write '1' to enable interrupt for event REGION0RA + 1 + 1 + read Disabled - Disable - 0 + Read: Disabled + 0x0 Enabled - Enable - 1 + Read: Enabled + 0x1 - - - ENDEPOUT3 - Enable or disable interrupt for ENDEPOUT[3] event - 15 - 15 + write - Disabled - Disable - 0 - - - Enabled + Set Enable - 1 + 0x1 - ENDEPOUT4 - Enable or disable interrupt for ENDEPOUT[4] event - 16 - 16 + REGION1WA + Write '1' to enable interrupt for event REGION1WA + 2 + 2 + read Disabled - Disable - 0 + Read: Disabled + 0x0 Enabled - Enable - 1 + Read: Enabled + 0x1 - - - ENDEPOUT5 - Enable or disable interrupt for ENDEPOUT[5] event - 17 - 17 + write - Disabled - Disable - 0 - - - Enabled + Set Enable - 1 + 0x1 - ENDEPOUT6 - Enable or disable interrupt for ENDEPOUT[6] event - 18 - 18 + REGION1RA + Write '1' to enable interrupt for event REGION1RA + 3 + 3 + read Disabled - Disable - 0 + Read: Disabled + 0x0 Enabled - Enable - 1 + Read: Enabled + 0x1 - - - ENDEPOUT7 - Enable or disable interrupt for ENDEPOUT[7] event - 19 - 19 + write - Disabled - Disable - 0 - - - Enabled + Set Enable - 1 + 0x1 - ENDISOOUT - Enable or disable interrupt for ENDISOOUT event - 20 - 20 + REGION2WA + Write '1' to enable interrupt for event REGION2WA + 4 + 4 + read Disabled - Disable - 0 + Read: Disabled + 0x0 Enabled - Enable - 1 + Read: Enabled + 0x1 - - - SOF - Enable or disable interrupt for SOF event - 21 - 21 + write - Disabled - Disable - 0 - - - Enabled + Set Enable - 1 + 0x1 - USBEVENT - Enable or disable interrupt for USBEVENT event - 22 - 22 + REGION2RA + Write '1' to enable interrupt for event REGION2RA + 5 + 5 + read Disabled - Disable - 0 + Read: Disabled + 0x0 Enabled + Read: Enabled + 0x1 + + + + write + + Set Enable - 1 + 0x1 - EP0SETUP - Enable or disable interrupt for EP0SETUP event - 23 - 23 + REGION3WA + Write '1' to enable interrupt for event REGION3WA + 6 + 6 + read Disabled - Disable - 0 + Read: Disabled + 0x0 Enabled + Read: Enabled + 0x1 + + + + write + + Set Enable - 1 + 0x1 - EPDATA - Enable or disable interrupt for EPDATA event - 24 - 24 + REGION3RA + Write '1' to enable interrupt for event REGION3RA + 7 + 7 + read Disabled - Disable - 0 + Read: Disabled + 0x0 Enabled + Read: Enabled + 0x1 + + + + write + + Set Enable - 1 + 0x1 - - - - INTENSET - Enable interrupt - 0x304 - read-write - - USBRESET - Write '1' to enable interrupt for USBRESET event - 0 - 0 + PREGION0WA + Write '1' to enable interrupt for event PREGION0WA + 24 + 24 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -41474,26 +45147,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - STARTED - Write '1' to enable interrupt for STARTED event - 1 - 1 + PREGION0RA + Write '1' to enable interrupt for event PREGION0RA + 25 + 25 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -41501,26 +45174,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - ENDEPIN0 - Write '1' to enable interrupt for ENDEPIN[0] event - 2 - 2 + PREGION1WA + Write '1' to enable interrupt for event PREGION1WA + 26 + 26 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -41528,26 +45201,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 - ENDEPIN1 - Write '1' to enable interrupt for ENDEPIN[1] event - 3 - 3 + PREGION1RA + Write '1' to enable interrupt for event PREGION1RA + 27 + 27 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -41555,588 +45228,583 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + - ENDEPIN2 - Write '1' to enable interrupt for ENDEPIN[2] event - 4 - 4 + REGION0WA + Write '1' to disable interrupt for event REGION0WA + 0 + 0 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Set - Enable - 1 + Clear + Disable + 0x1 - ENDEPIN3 - Write '1' to enable interrupt for ENDEPIN[3] event - 5 - 5 + REGION0RA + Write '1' to disable interrupt for event REGION0RA + 1 + 1 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Set - Enable - 1 + Clear + Disable + 0x1 - ENDEPIN4 - Write '1' to enable interrupt for ENDEPIN[4] event - 6 - 6 + REGION1WA + Write '1' to disable interrupt for event REGION1WA + 2 + 2 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Set - Enable - 1 + Clear + Disable + 0x1 - ENDEPIN5 - Write '1' to enable interrupt for ENDEPIN[5] event - 7 - 7 + REGION1RA + Write '1' to disable interrupt for event REGION1RA + 3 + 3 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Set - Enable - 1 + Clear + Disable + 0x1 - ENDEPIN6 - Write '1' to enable interrupt for ENDEPIN[6] event - 8 - 8 + REGION2WA + Write '1' to disable interrupt for event REGION2WA + 4 + 4 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Set - Enable - 1 + Clear + Disable + 0x1 - ENDEPIN7 - Write '1' to enable interrupt for ENDEPIN[7] event - 9 - 9 + REGION2RA + Write '1' to disable interrupt for event REGION2RA + 5 + 5 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Set - Enable - 1 + Clear + Disable + 0x1 - EP0DATADONE - Write '1' to enable interrupt for EP0DATADONE event - 10 - 10 + REGION3WA + Write '1' to disable interrupt for event REGION3WA + 6 + 6 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Set - Enable - 1 + Clear + Disable + 0x1 - ENDISOIN - Write '1' to enable interrupt for ENDISOIN event - 11 - 11 + REGION3RA + Write '1' to disable interrupt for event REGION3RA + 7 + 7 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Set - Enable - 1 + Clear + Disable + 0x1 - ENDEPOUT0 - Write '1' to enable interrupt for ENDEPOUT[0] event - 12 - 12 + PREGION0WA + Write '1' to disable interrupt for event PREGION0WA + 24 + 24 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Set - Enable - 1 + Clear + Disable + 0x1 - ENDEPOUT1 - Write '1' to enable interrupt for ENDEPOUT[1] event - 13 - 13 + PREGION0RA + Write '1' to disable interrupt for event PREGION0RA + 25 + 25 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Set - Enable - 1 + Clear + Disable + 0x1 - ENDEPOUT2 - Write '1' to enable interrupt for ENDEPOUT[2] event - 14 - 14 + PREGION1WA + Write '1' to disable interrupt for event PREGION1WA + 26 + 26 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Set - Enable - 1 + Clear + Disable + 0x1 - ENDEPOUT3 - Write '1' to enable interrupt for ENDEPOUT[3] event - 15 - 15 + PREGION1RA + Write '1' to disable interrupt for event PREGION1RA + 27 + 27 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Set - Enable - 1 + Clear + Disable + 0x1 + + + + NMIEN + Enable or disable interrupt + 0x320 + read-write + 0x00000000 + 0x20 + - ENDEPOUT4 - Write '1' to enable interrupt for ENDEPOUT[4] event - 16 - 16 + REGION0WA + Enable or disable interrupt for event REGION0WA + 0 + 0 - read Disabled - Read: Disabled - 0 + Disable + 0x0 Enabled - Read: Enabled - 1 + Enable + 0x1 + + + REGION0RA + Enable or disable interrupt for event REGION0RA + 1 + 1 - write - Set + Disabled + Disable + 0x0 + + + Enabled Enable - 1 + 0x1 - ENDEPOUT5 - Write '1' to enable interrupt for ENDEPOUT[5] event - 17 - 17 + REGION1WA + Enable or disable interrupt for event REGION1WA + 2 + 2 - read Disabled - Read: Disabled - 0 + Disable + 0x0 Enabled - Read: Enabled - 1 + Enable + 0x1 + + + REGION1RA + Enable or disable interrupt for event REGION1RA + 3 + 3 - write - Set + Disabled + Disable + 0x0 + + + Enabled Enable - 1 + 0x1 - ENDEPOUT6 - Write '1' to enable interrupt for ENDEPOUT[6] event - 18 - 18 + REGION2WA + Enable or disable interrupt for event REGION2WA + 4 + 4 - read Disabled - Read: Disabled - 0 + Disable + 0x0 Enabled - Read: Enabled - 1 + Enable + 0x1 + + + REGION2RA + Enable or disable interrupt for event REGION2RA + 5 + 5 - write - Set + Disabled + Disable + 0x0 + + + Enabled Enable - 1 + 0x1 - ENDEPOUT7 - Write '1' to enable interrupt for ENDEPOUT[7] event - 19 - 19 + REGION3WA + Enable or disable interrupt for event REGION3WA + 6 + 6 - read Disabled - Read: Disabled - 0 + Disable + 0x0 Enabled - Read: Enabled - 1 - - - - write - - Set Enable - 1 + 0x1 - ENDISOOUT - Write '1' to enable interrupt for ENDISOOUT event - 20 - 20 + REGION3RA + Enable or disable interrupt for event REGION3RA + 7 + 7 - read Disabled - Read: Disabled - 0 + Disable + 0x0 Enabled - Read: Enabled - 1 - - - - write - - Set Enable - 1 + 0x1 - SOF - Write '1' to enable interrupt for SOF event - 21 - 21 + PREGION0WA + Enable or disable interrupt for event PREGION0WA + 24 + 24 - read Disabled - Read: Disabled - 0 + Disable + 0x0 Enabled - Read: Enabled - 1 - - - - write - - Set Enable - 1 + 0x1 - USBEVENT - Write '1' to enable interrupt for USBEVENT event - 22 - 22 + PREGION0RA + Enable or disable interrupt for event PREGION0RA + 25 + 25 - read Disabled - Read: Disabled - 0 + Disable + 0x0 Enabled - Read: Enabled - 1 - - - - write - - Set Enable - 1 + 0x1 - EP0SETUP - Write '1' to enable interrupt for EP0SETUP event - 23 - 23 + PREGION1WA + Enable or disable interrupt for event PREGION1WA + 26 + 26 - read Disabled - Read: Disabled - 0 + Disable + 0x0 Enabled - Read: Enabled - 1 - - - - write - - Set Enable - 1 + 0x1 - EPDATA - Write '1' to enable interrupt for EPDATA event - 24 - 24 + PREGION1RA + Enable or disable interrupt for event PREGION1RA + 27 + 27 - read Disabled - Read: Disabled - 0 + Disable + 0x0 Enabled - Read: Enabled - 1 - - - - write - - Set Enable - 1 + 0x1 - INTENCLR - Disable interrupt - 0x308 + NMIENSET + Enable interrupt + 0x324 read-write + 0x00000000 + 0x20 - USBRESET - Write '1' to disable interrupt for USBRESET event + REGION0WA + Write '1' to enable interrupt for event REGION0WA 0 0 @@ -42144,26 +45812,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Clear - Disable - 1 + Set + Enable + 0x1 - STARTED - Write '1' to disable interrupt for STARTED event + REGION0RA + Write '1' to enable interrupt for event REGION0RA 1 1 @@ -42171,26 +45839,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Clear - Disable - 1 + Set + Enable + 0x1 - ENDEPIN0 - Write '1' to disable interrupt for ENDEPIN[0] event + REGION1WA + Write '1' to enable interrupt for event REGION1WA 2 2 @@ -42198,26 +45866,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Clear - Disable - 1 + Set + Enable + 0x1 - ENDEPIN1 - Write '1' to disable interrupt for ENDEPIN[1] event + REGION1RA + Write '1' to enable interrupt for event REGION1RA 3 3 @@ -42225,26 +45893,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Clear - Disable - 1 + Set + Enable + 0x1 - ENDEPIN2 - Write '1' to disable interrupt for ENDEPIN[2] event + REGION2WA + Write '1' to enable interrupt for event REGION2WA 4 4 @@ -42252,26 +45920,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Clear - Disable - 1 + Set + Enable + 0x1 - ENDEPIN3 - Write '1' to disable interrupt for ENDEPIN[3] event + REGION2RA + Write '1' to enable interrupt for event REGION2RA 5 5 @@ -42279,26 +45947,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Clear - Disable - 1 + Set + Enable + 0x1 - ENDEPIN4 - Write '1' to disable interrupt for ENDEPIN[4] event + REGION3WA + Write '1' to enable interrupt for event REGION3WA 6 6 @@ -42306,26 +45974,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Clear - Disable - 1 + Set + Enable + 0x1 - ENDEPIN5 - Write '1' to disable interrupt for ENDEPIN[5] event + REGION3RA + Write '1' to enable interrupt for event REGION3RA 7 7 @@ -42333,174 +46001,157 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disabled Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ENDEPIN6 - Write '1' to disable interrupt for ENDEPIN[6] event - 8 - 8 - - read - - Disabled - Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Clear - Disable - 1 + Set + Enable + 0x1 - ENDEPIN7 - Write '1' to disable interrupt for ENDEPIN[7] event - 9 - 9 + PREGION0WA + Write '1' to enable interrupt for event PREGION0WA + 24 + 24 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Clear - Disable - 1 + Set + Enable + 0x1 - EP0DATADONE - Write '1' to disable interrupt for EP0DATADONE event - 10 - 10 + PREGION0RA + Write '1' to enable interrupt for event PREGION0RA + 25 + 25 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Clear - Disable - 1 + Set + Enable + 0x1 - ENDISOIN - Write '1' to disable interrupt for ENDISOIN event - 11 - 11 + PREGION1WA + Write '1' to enable interrupt for event PREGION1WA + 26 + 26 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Clear - Disable - 1 + Set + Enable + 0x1 - ENDEPOUT0 - Write '1' to disable interrupt for ENDEPOUT[0] event - 12 - 12 + PREGION1RA + Write '1' to enable interrupt for event PREGION1RA + 27 + 27 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 write - Clear - Disable - 1 + Set + Enable + 0x1 + + + + NMIENCLR + Disable interrupt + 0x328 + read-write + 0x00000000 + 0x20 + - ENDEPOUT1 - Write '1' to disable interrupt for ENDEPOUT[1] event - 13 - 13 + REGION0WA + Write '1' to disable interrupt for event REGION0WA + 0 + 0 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -42508,26 +46159,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - ENDEPOUT2 - Write '1' to disable interrupt for ENDEPOUT[2] event - 14 - 14 + REGION0RA + Write '1' to disable interrupt for event REGION0RA + 1 + 1 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -42535,26 +46186,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - ENDEPOUT3 - Write '1' to disable interrupt for ENDEPOUT[3] event - 15 - 15 + REGION1WA + Write '1' to disable interrupt for event REGION1WA + 2 + 2 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -42562,26 +46213,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - ENDEPOUT4 - Write '1' to disable interrupt for ENDEPOUT[4] event - 16 - 16 + REGION1RA + Write '1' to disable interrupt for event REGION1RA + 3 + 3 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -42589,26 +46240,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - ENDEPOUT5 - Write '1' to disable interrupt for ENDEPOUT[5] event - 17 - 17 + REGION2WA + Write '1' to disable interrupt for event REGION2WA + 4 + 4 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -42616,26 +46267,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - ENDEPOUT6 - Write '1' to disable interrupt for ENDEPOUT[6] event - 18 - 18 + REGION2RA + Write '1' to disable interrupt for event REGION2RA + 5 + 5 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -42643,26 +46294,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - ENDEPOUT7 - Write '1' to disable interrupt for ENDEPOUT[7] event - 19 - 19 + REGION3WA + Write '1' to disable interrupt for event REGION3WA + 6 + 6 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -42670,26 +46321,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - ENDISOOUT - Write '1' to disable interrupt for ENDISOOUT event - 20 - 20 + REGION3RA + Write '1' to disable interrupt for event REGION3RA + 7 + 7 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -42697,26 +46348,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - SOF - Write '1' to disable interrupt for SOF event - 21 - 21 + PREGION0WA + Write '1' to disable interrupt for event PREGION0WA + 24 + 24 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -42724,26 +46375,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - USBEVENT - Write '1' to disable interrupt for USBEVENT event - 22 - 22 + PREGION0RA + Write '1' to disable interrupt for event PREGION0RA + 25 + 25 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -42751,26 +46402,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - EP0SETUP - Write '1' to disable interrupt for EP0SETUP event - 23 - 23 + PREGION1WA + Write '1' to disable interrupt for event PREGION1WA + 26 + 26 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -42778,26 +46429,26 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 - EPDATA - Write '1' to disable interrupt for EPDATA event - 24 - 24 + PREGION1RA + Write '1' to disable interrupt for event PREGION1RA + 27 + 27 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -42805,2000 +46456,2962 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 - - - - - - - EVENTCAUSE - Details on what caused the USBEVENT event - 0x400 - read-write - oneToClear - - - ISOOUTCRC - CRC error was detected on isochronous OUT endpoint 8. Write '1' to clear. - 0 - 0 - - - NotDetected - No error detected - 0 - - - Detected - Error detected - 1 - - - - - SUSPEND - Signals that USB lines have been idle long enough for the device to enter suspend. Write '1' to clear. - 8 - 8 - - - NotDetected - Suspend not detected - 0 - - - Detected - Suspend detected - 1 - - - - - RESUME - Signals that a RESUME condition (K state or activity restart) has been detected on USB lines. Write '1' to clear. - 9 - 9 - - - NotDetected - Resume not detected - 0 - - - Detected - Resume detected - 1 - - - - - USBWUALLOWED - USB MAC has been woken up and operational. Write '1' to clear. - 10 - 10 - - - NotAllowed - Wake up not allowed - 0 - - - Allowed - Wake up allowed - 1 - - - - - READY - USB device is ready for normal operation. Write '1' to clear. - 11 - 11 - - - NotDetected - USBEVENT was not issued due to USBD peripheral ready - 0 - - - Ready - USBD peripheral is ready - 1 + 0x1 - HALTED + 2 + 0x008 + PERREGION[%s] Unspecified - USBD_HALTED - 0x420 + MWU_PERREGION + read-write + 0x400 + + SUBSTATWA + Description cluster: Source of event/interrupt in region n, write access detected while corresponding subregion was enabled for watching + 0x000 + read-write + 0x00000000 + oneToClear + 0x20 + + + SR0 + Subregion 0 in region n (write '1' to clear) + 0 + 0 + + + NoAccess + No write access occurred in this subregion + 0x0 + + + Access + Write access(es) occurred in this subregion + 0x1 + + + + + SR1 + Subregion 1 in region n (write '1' to clear) + 1 + 1 + + + NoAccess + No write access occurred in this subregion + 0x0 + + + Access + Write access(es) occurred in this subregion + 0x1 + + + + + SR2 + Subregion 2 in region n (write '1' to clear) + 2 + 2 + + + NoAccess + No write access occurred in this subregion + 0x0 + + + Access + Write access(es) occurred in this subregion + 0x1 + + + + + SR3 + Subregion 3 in region n (write '1' to clear) + 3 + 3 + + + NoAccess + No write access occurred in this subregion + 0x0 + + + Access + Write access(es) occurred in this subregion + 0x1 + + + + + SR4 + Subregion 4 in region n (write '1' to clear) + 4 + 4 + + + NoAccess + No write access occurred in this subregion + 0x0 + + + Access + Write access(es) occurred in this subregion + 0x1 + + + + + SR5 + Subregion 5 in region n (write '1' to clear) + 5 + 5 + + + NoAccess + No write access occurred in this subregion + 0x0 + + + Access + Write access(es) occurred in this subregion + 0x1 + + + + + SR6 + Subregion 6 in region n (write '1' to clear) + 6 + 6 + + + NoAccess + No write access occurred in this subregion + 0x0 + + + Access + Write access(es) occurred in this subregion + 0x1 + + + + + SR7 + Subregion 7 in region n (write '1' to clear) + 7 + 7 + + + NoAccess + No write access occurred in this subregion + 0x0 + + + Access + Write access(es) occurred in this subregion + 0x1 + + + + + SR8 + Subregion 8 in region n (write '1' to clear) + 8 + 8 + + + NoAccess + No write access occurred in this subregion + 0x0 + + + Access + Write access(es) occurred in this subregion + 0x1 + + + + + SR9 + Subregion 9 in region n (write '1' to clear) + 9 + 9 + + + NoAccess + No write access occurred in this subregion + 0x0 + + + Access + Write access(es) occurred in this subregion + 0x1 + + + + + SR10 + Subregion 10 in region n (write '1' to clear) + 10 + 10 + + + NoAccess + No write access occurred in this subregion + 0x0 + + + Access + Write access(es) occurred in this subregion + 0x1 + + + + + SR11 + Subregion 11 in region n (write '1' to clear) + 11 + 11 + + + NoAccess + No write access occurred in this subregion + 0x0 + + + Access + Write access(es) occurred in this subregion + 0x1 + + + + + SR12 + Subregion 12 in region n (write '1' to clear) + 12 + 12 + + + NoAccess + No write access occurred in this subregion + 0x0 + + + Access + Write access(es) occurred in this subregion + 0x1 + + + + + SR13 + Subregion 13 in region n (write '1' to clear) + 13 + 13 + + + NoAccess + No write access occurred in this subregion + 0x0 + + + Access + Write access(es) occurred in this subregion + 0x1 + + + + + SR14 + Subregion 14 in region n (write '1' to clear) + 14 + 14 + + + NoAccess + No write access occurred in this subregion + 0x0 + + + Access + Write access(es) occurred in this subregion + 0x1 + + + + + SR15 + Subregion 15 in region n (write '1' to clear) + 15 + 15 + + + NoAccess + No write access occurred in this subregion + 0x0 + + + Access + Write access(es) occurred in this subregion + 0x1 + + + + + SR16 + Subregion 16 in region n (write '1' to clear) + 16 + 16 + + + NoAccess + No write access occurred in this subregion + 0x0 + + + Access + Write access(es) occurred in this subregion + 0x1 + + + + + SR17 + Subregion 17 in region n (write '1' to clear) + 17 + 17 + + + NoAccess + No write access occurred in this subregion + 0x0 + + + Access + Write access(es) occurred in this subregion + 0x1 + + + + + SR18 + Subregion 18 in region n (write '1' to clear) + 18 + 18 + + + NoAccess + No write access occurred in this subregion + 0x0 + + + Access + Write access(es) occurred in this subregion + 0x1 + + + + + SR19 + Subregion 19 in region n (write '1' to clear) + 19 + 19 + + + NoAccess + No write access occurred in this subregion + 0x0 + + + Access + Write access(es) occurred in this subregion + 0x1 + + + + + SR20 + Subregion 20 in region n (write '1' to clear) + 20 + 20 + + + NoAccess + No write access occurred in this subregion + 0x0 + + + Access + Write access(es) occurred in this subregion + 0x1 + + + + + SR21 + Subregion 21 in region n (write '1' to clear) + 21 + 21 + + + NoAccess + No write access occurred in this subregion + 0x0 + + + Access + Write access(es) occurred in this subregion + 0x1 + + + + + SR22 + Subregion 22 in region n (write '1' to clear) + 22 + 22 + + + NoAccess + No write access occurred in this subregion + 0x0 + + + Access + Write access(es) occurred in this subregion + 0x1 + + + + + SR23 + Subregion 23 in region n (write '1' to clear) + 23 + 23 + + + NoAccess + No write access occurred in this subregion + 0x0 + + + Access + Write access(es) occurred in this subregion + 0x1 + + + + + SR24 + Subregion 24 in region n (write '1' to clear) + 24 + 24 + + + NoAccess + No write access occurred in this subregion + 0x0 + + + Access + Write access(es) occurred in this subregion + 0x1 + + + + + SR25 + Subregion 25 in region n (write '1' to clear) + 25 + 25 + + + NoAccess + No write access occurred in this subregion + 0x0 + + + Access + Write access(es) occurred in this subregion + 0x1 + + + + + SR26 + Subregion 26 in region n (write '1' to clear) + 26 + 26 + + + NoAccess + No write access occurred in this subregion + 0x0 + + + Access + Write access(es) occurred in this subregion + 0x1 + + + + + SR27 + Subregion 27 in region n (write '1' to clear) + 27 + 27 + + + NoAccess + No write access occurred in this subregion + 0x0 + + + Access + Write access(es) occurred in this subregion + 0x1 + + + + + SR28 + Subregion 28 in region n (write '1' to clear) + 28 + 28 + + + NoAccess + No write access occurred in this subregion + 0x0 + + + Access + Write access(es) occurred in this subregion + 0x1 + + + + + SR29 + Subregion 29 in region n (write '1' to clear) + 29 + 29 + + + NoAccess + No write access occurred in this subregion + 0x0 + + + Access + Write access(es) occurred in this subregion + 0x1 + + + + + SR30 + Subregion 30 in region n (write '1' to clear) + 30 + 30 + + + NoAccess + No write access occurred in this subregion + 0x0 + + + Access + Write access(es) occurred in this subregion + 0x1 + + + + + SR31 + Subregion 31 in region n (write '1' to clear) + 31 + 31 + + + NoAccess + No write access occurred in this subregion + 0x0 + + + Access + Write access(es) occurred in this subregion + 0x1 + + + + + - 8 - 0x4 - EPIN[%s] - Description collection[n]: IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. - 0x000 - read-only + SUBSTATRA + Description cluster: Source of event/interrupt in region n, read access detected while corresponding subregion was enabled for watching + 0x004 + read-write + 0x00000000 + oneToClear + 0x20 - GETSTATUS - IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. - 0 - 15 + SR0 + Subregion 0 in region n (write '1' to clear) + 0 + 0 + + + NoAccess + No read access occurred in this subregion + 0x0 + + + Access + Read access(es) occurred in this subregion + 0x1 + + + + + SR1 + Subregion 1 in region n (write '1' to clear) + 1 + 1 + + + NoAccess + No read access occurred in this subregion + 0x0 + + + Access + Read access(es) occurred in this subregion + 0x1 + + + + + SR2 + Subregion 2 in region n (write '1' to clear) + 2 + 2 + + + NoAccess + No read access occurred in this subregion + 0x0 + + + Access + Read access(es) occurred in this subregion + 0x1 + + + + + SR3 + Subregion 3 in region n (write '1' to clear) + 3 + 3 + + + NoAccess + No read access occurred in this subregion + 0x0 + + + Access + Read access(es) occurred in this subregion + 0x1 + + + + + SR4 + Subregion 4 in region n (write '1' to clear) + 4 + 4 + + + NoAccess + No read access occurred in this subregion + 0x0 + + + Access + Read access(es) occurred in this subregion + 0x1 + + + + + SR5 + Subregion 5 in region n (write '1' to clear) + 5 + 5 - NotHalted - Endpoint is not halted - 0 + NoAccess + No read access occurred in this subregion + 0x0 - Halted - Endpoint is halted - 1 + Access + Read access(es) occurred in this subregion + 0x1 - - - - 8 - 0x4 - EPOUT[%s] - Description collection[n]: OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. - 0x024 - read-only - - GETSTATUS - OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. - 0 + SR6 + Subregion 6 in region n (write '1' to clear) + 6 + 6 + + + NoAccess + No read access occurred in this subregion + 0x0 + + + Access + Read access(es) occurred in this subregion + 0x1 + + + + + SR7 + Subregion 7 in region n (write '1' to clear) + 7 + 7 + + + NoAccess + No read access occurred in this subregion + 0x0 + + + Access + Read access(es) occurred in this subregion + 0x1 + + + + + SR8 + Subregion 8 in region n (write '1' to clear) + 8 + 8 + + + NoAccess + No read access occurred in this subregion + 0x0 + + + Access + Read access(es) occurred in this subregion + 0x1 + + + + + SR9 + Subregion 9 in region n (write '1' to clear) + 9 + 9 + + + NoAccess + No read access occurred in this subregion + 0x0 + + + Access + Read access(es) occurred in this subregion + 0x1 + + + + + SR10 + Subregion 10 in region n (write '1' to clear) + 10 + 10 + + + NoAccess + No read access occurred in this subregion + 0x0 + + + Access + Read access(es) occurred in this subregion + 0x1 + + + + + SR11 + Subregion 11 in region n (write '1' to clear) + 11 + 11 + + + NoAccess + No read access occurred in this subregion + 0x0 + + + Access + Read access(es) occurred in this subregion + 0x1 + + + + + SR12 + Subregion 12 in region n (write '1' to clear) + 12 + 12 + + + NoAccess + No read access occurred in this subregion + 0x0 + + + Access + Read access(es) occurred in this subregion + 0x1 + + + + + SR13 + Subregion 13 in region n (write '1' to clear) + 13 + 13 + + + NoAccess + No read access occurred in this subregion + 0x0 + + + Access + Read access(es) occurred in this subregion + 0x1 + + + + + SR14 + Subregion 14 in region n (write '1' to clear) + 14 + 14 + + + NoAccess + No read access occurred in this subregion + 0x0 + + + Access + Read access(es) occurred in this subregion + 0x1 + + + + + SR15 + Subregion 15 in region n (write '1' to clear) + 15 15 - NotHalted - Endpoint is not halted - 0 + NoAccess + No read access occurred in this subregion + 0x0 - Halted - Endpoint is halted - 1 + Access + Read access(es) occurred in this subregion + 0x1 - - - - - EPSTATUS - Provides information on which endpoint's EasyDMA registers have been captured - 0x468 - read-write - oneToClear - - - EPIN0 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. - 0 - 0 - - - NoData - EasyDMA registers have not been captured for this endpoint - 0 - - - DataDone - EasyDMA registers have been captured for this endpoint - 1 - - - - - EPIN1 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. - 1 - 1 - - - NoData - EasyDMA registers have not been captured for this endpoint - 0 - - - DataDone - EasyDMA registers have been captured for this endpoint - 1 - - - - - EPIN2 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. - 2 - 2 - - - NoData - EasyDMA registers have not been captured for this endpoint - 0 - - - DataDone - EasyDMA registers have been captured for this endpoint - 1 - - - - - EPIN3 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. - 3 - 3 - - - NoData - EasyDMA registers have not been captured for this endpoint - 0 - - - DataDone - EasyDMA registers have been captured for this endpoint - 1 - - - - - EPIN4 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. - 4 - 4 - - - NoData - EasyDMA registers have not been captured for this endpoint - 0 - - - DataDone - EasyDMA registers have been captured for this endpoint - 1 - - - - - EPIN5 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. - 5 - 5 - - - NoData - EasyDMA registers have not been captured for this endpoint - 0 - - - DataDone - EasyDMA registers have been captured for this endpoint - 1 - - - - - EPIN6 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. - 6 - 6 - - - NoData - EasyDMA registers have not been captured for this endpoint - 0 - - - DataDone - EasyDMA registers have been captured for this endpoint - 1 - - - - - EPIN7 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. - 7 - 7 - - - NoData - EasyDMA registers have not been captured for this endpoint - 0 - - - DataDone - EasyDMA registers have been captured for this endpoint - 1 - - - - - EPIN8 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. - 8 - 8 - - - NoData - EasyDMA registers have not been captured for this endpoint - 0 - - - DataDone - EasyDMA registers have been captured for this endpoint - 1 - - - - - EPOUT0 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. - 16 - 16 - - - NoData - EasyDMA registers have not been captured for this endpoint - 0 - - - DataDone - EasyDMA registers have been captured for this endpoint - 1 - - - - - EPOUT1 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. - 17 - 17 - - - NoData - EasyDMA registers have not been captured for this endpoint - 0 - - - DataDone - EasyDMA registers have been captured for this endpoint - 1 - - - - - EPOUT2 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. - 18 - 18 - - - NoData - EasyDMA registers have not been captured for this endpoint - 0 - - - DataDone - EasyDMA registers have been captured for this endpoint - 1 - - - - - EPOUT3 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. - 19 - 19 - - - NoData - EasyDMA registers have not been captured for this endpoint - 0 - - - DataDone - EasyDMA registers have been captured for this endpoint - 1 - - - - - EPOUT4 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. - 20 - 20 - - - NoData - EasyDMA registers have not been captured for this endpoint - 0 - - - DataDone - EasyDMA registers have been captured for this endpoint - 1 - - - - - EPOUT5 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. - 21 - 21 - - - NoData - EasyDMA registers have not been captured for this endpoint - 0 - - - DataDone - EasyDMA registers have been captured for this endpoint - 1 - - - - - EPOUT6 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. - 22 - 22 - - - NoData - EasyDMA registers have not been captured for this endpoint - 0 - - - DataDone - EasyDMA registers have been captured for this endpoint - 1 - - - - - EPOUT7 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. - 23 - 23 - - - NoData - EasyDMA registers have not been captured for this endpoint - 0 - - - DataDone - EasyDMA registers have been captured for this endpoint - 1 - - - + + SR16 + Subregion 16 in region n (write '1' to clear) + 16 + 16 + + + NoAccess + No read access occurred in this subregion + 0x0 + + + Access + Read access(es) occurred in this subregion + 0x1 + + + + + SR17 + Subregion 17 in region n (write '1' to clear) + 17 + 17 + + + NoAccess + No read access occurred in this subregion + 0x0 + + + Access + Read access(es) occurred in this subregion + 0x1 + + + + + SR18 + Subregion 18 in region n (write '1' to clear) + 18 + 18 + + + NoAccess + No read access occurred in this subregion + 0x0 + + + Access + Read access(es) occurred in this subregion + 0x1 + + + + + SR19 + Subregion 19 in region n (write '1' to clear) + 19 + 19 + + + NoAccess + No read access occurred in this subregion + 0x0 + + + Access + Read access(es) occurred in this subregion + 0x1 + + + + + SR20 + Subregion 20 in region n (write '1' to clear) + 20 + 20 + + + NoAccess + No read access occurred in this subregion + 0x0 + + + Access + Read access(es) occurred in this subregion + 0x1 + + + + + SR21 + Subregion 21 in region n (write '1' to clear) + 21 + 21 + + + NoAccess + No read access occurred in this subregion + 0x0 + + + Access + Read access(es) occurred in this subregion + 0x1 + + + + + SR22 + Subregion 22 in region n (write '1' to clear) + 22 + 22 + + + NoAccess + No read access occurred in this subregion + 0x0 + + + Access + Read access(es) occurred in this subregion + 0x1 + + + + + SR23 + Subregion 23 in region n (write '1' to clear) + 23 + 23 + + + NoAccess + No read access occurred in this subregion + 0x0 + + + Access + Read access(es) occurred in this subregion + 0x1 + + + + + SR24 + Subregion 24 in region n (write '1' to clear) + 24 + 24 + + + NoAccess + No read access occurred in this subregion + 0x0 + + + Access + Read access(es) occurred in this subregion + 0x1 + + + + + SR25 + Subregion 25 in region n (write '1' to clear) + 25 + 25 + + + NoAccess + No read access occurred in this subregion + 0x0 + + + Access + Read access(es) occurred in this subregion + 0x1 + + + + + SR26 + Subregion 26 in region n (write '1' to clear) + 26 + 26 + + + NoAccess + No read access occurred in this subregion + 0x0 + + + Access + Read access(es) occurred in this subregion + 0x1 + + + + + SR27 + Subregion 27 in region n (write '1' to clear) + 27 + 27 + + + NoAccess + No read access occurred in this subregion + 0x0 + + + Access + Read access(es) occurred in this subregion + 0x1 + + + + + SR28 + Subregion 28 in region n (write '1' to clear) + 28 + 28 + + + NoAccess + No read access occurred in this subregion + 0x0 + + + Access + Read access(es) occurred in this subregion + 0x1 + + + + + SR29 + Subregion 29 in region n (write '1' to clear) + 29 + 29 + + + NoAccess + No read access occurred in this subregion + 0x0 + + + Access + Read access(es) occurred in this subregion + 0x1 + + + + + SR30 + Subregion 30 in region n (write '1' to clear) + 30 + 30 + + + NoAccess + No read access occurred in this subregion + 0x0 + + + Access + Read access(es) occurred in this subregion + 0x1 + + + + + SR31 + Subregion 31 in region n (write '1' to clear) + 31 + 31 + + + NoAccess + No read access occurred in this subregion + 0x0 + + + Access + Read access(es) occurred in this subregion + 0x1 + + + + + + + + REGIONEN + Enable/disable regions watch + 0x510 + read-write + 0x00000000 + 0x20 + - EPOUT8 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. - 24 - 24 + RGN0WA + Enable/disable write access watch in region[0] + 0 + 0 - NoData - EasyDMA registers have not been captured for this endpoint - 0 + Disable + Disable write access watch in this region + 0x0 - DataDone - EasyDMA registers have been captured for this endpoint - 1 + Enable + Enable write access watch in this region + 0x1 - - - - EPDATASTATUS - Provides information on which endpoint(s) an acknowledged data transfer has occurred (EPDATA event) - 0x46C - read-write - oneToClear - - EPIN1 - Acknowledged data transfer on this IN endpoint. Write '1' to clear. + RGN0RA + Enable/disable read access watch in region[0] 1 1 - NotDone - No acknowledged data transfer on this endpoint - 0 + Disable + Disable read access watch in this region + 0x0 - DataDone - Acknowledged data transfer on this endpoint has occurred - 1 + Enable + Enable read access watch in this region + 0x1 - EPIN2 - Acknowledged data transfer on this IN endpoint. Write '1' to clear. + RGN1WA + Enable/disable write access watch in region[1] 2 2 - NotDone - No acknowledged data transfer on this endpoint - 0 + Disable + Disable write access watch in this region + 0x0 - DataDone - Acknowledged data transfer on this endpoint has occurred - 1 + Enable + Enable write access watch in this region + 0x1 - EPIN3 - Acknowledged data transfer on this IN endpoint. Write '1' to clear. + RGN1RA + Enable/disable read access watch in region[1] 3 3 - NotDone - No acknowledged data transfer on this endpoint - 0 + Disable + Disable read access watch in this region + 0x0 - DataDone - Acknowledged data transfer on this endpoint has occurred - 1 + Enable + Enable read access watch in this region + 0x1 - EPIN4 - Acknowledged data transfer on this IN endpoint. Write '1' to clear. + RGN2WA + Enable/disable write access watch in region[2] 4 4 - NotDone - No acknowledged data transfer on this endpoint - 0 - - - DataDone - Acknowledged data transfer on this endpoint has occurred - 1 - - - - - EPIN5 - Acknowledged data transfer on this IN endpoint. Write '1' to clear. - 5 - 5 - - - NotDone - No acknowledged data transfer on this endpoint - 0 - - - DataDone - Acknowledged data transfer on this endpoint has occurred - 1 - - - - - EPIN6 - Acknowledged data transfer on this IN endpoint. Write '1' to clear. - 6 - 6 - - - NotDone - No acknowledged data transfer on this endpoint - 0 - - - DataDone - Acknowledged data transfer on this endpoint has occurred - 1 - - - - - EPIN7 - Acknowledged data transfer on this IN endpoint. Write '1' to clear. - 7 - 7 - - - NotDone - No acknowledged data transfer on this endpoint - 0 - - - DataDone - Acknowledged data transfer on this endpoint has occurred - 1 - - - - - EPOUT1 - Acknowledged data transfer on this OUT endpoint. Write '1' to clear. - 17 - 17 - - - NotStarted - No acknowledged data transfer on this endpoint - 0 - - - Started - Acknowledged data transfer on this endpoint has occurred - 1 - - - - - EPOUT2 - Acknowledged data transfer on this OUT endpoint. Write '1' to clear. - 18 - 18 - - - NotStarted - No acknowledged data transfer on this endpoint - 0 - - - Started - Acknowledged data transfer on this endpoint has occurred - 1 - - - - - EPOUT3 - Acknowledged data transfer on this OUT endpoint. Write '1' to clear. - 19 - 19 - - - NotStarted - No acknowledged data transfer on this endpoint - 0 - - - Started - Acknowledged data transfer on this endpoint has occurred - 1 - - - - - EPOUT4 - Acknowledged data transfer on this OUT endpoint. Write '1' to clear. - 20 - 20 - - - NotStarted - No acknowledged data transfer on this endpoint - 0 - - - Started - Acknowledged data transfer on this endpoint has occurred - 1 - - - - - EPOUT5 - Acknowledged data transfer on this OUT endpoint. Write '1' to clear. - 21 - 21 - - - NotStarted - No acknowledged data transfer on this endpoint - 0 - - - Started - Acknowledged data transfer on this endpoint has occurred - 1 - - - - - EPOUT6 - Acknowledged data transfer on this OUT endpoint. Write '1' to clear. - 22 - 22 - - - NotStarted - No acknowledged data transfer on this endpoint - 0 - - - Started - Acknowledged data transfer on this endpoint has occurred - 1 - - - - - EPOUT7 - Acknowledged data transfer on this OUT endpoint. Write '1' to clear. - 23 - 23 - - - NotStarted - No acknowledged data transfer on this endpoint - 0 - - - Started - Acknowledged data transfer on this endpoint has occurred - 1 - - - - - - - USBADDR - Device USB address - 0x470 - read-only - - - ADDR - Device USB address - 0 - 6 - - - - - BMREQUESTTYPE - SETUP data, byte 0, bmRequestType - 0x480 - read-only - 0x00000000 - - - RECIPIENT - Data transfer type - 0 - 4 - - - Device - Device - 0 - - - Interface - Interface - 1 - - - Endpoint - Endpoint - 2 + Disable + Disable write access watch in this region + 0x0 - Other - Other - 3 + Enable + Enable write access watch in this region + 0x1 - TYPE - Data transfer type + RGN2RA + Enable/disable read access watch in region[2] 5 - 6 + 5 - Standard - Standard - 0 - - - Class - Class - 1 + Disable + Disable read access watch in this region + 0x0 - Vendor - Vendor - 2 + Enable + Enable read access watch in this region + 0x1 - DIRECTION - Data transfer direction - 7 - 7 + RGN3WA + Enable/disable write access watch in region[3] + 6 + 6 - HostToDevice - Host-to-device - 0 + Disable + Disable write access watch in this region + 0x0 - DeviceToHost - Device-to-host - 1 + Enable + Enable write access watch in this region + 0x1 - - - - BREQUEST - SETUP data, byte 1, bRequest - 0x484 - read-only - 0x00000000 - - BREQUEST - SETUP data, byte 1, bRequest. Values provided for standard requests only, user must implement class and vendor values. - 0 + RGN3RA + Enable/disable read access watch in region[3] + 7 7 - STD_GET_STATUS - Standard request GET_STATUS - 0 - - - STD_CLEAR_FEATURE - Standard request CLEAR_FEATURE - 1 + Disable + Disable read access watch in this region + 0x0 - STD_SET_FEATURE - Standard request SET_FEATURE - 3 + Enable + Enable read access watch in this region + 0x1 + + + + PRGN0WA + Enable/disable write access watch in PREGION[0] + 24 + 24 + - STD_SET_ADDRESS - Standard request SET_ADDRESS - 5 + Disable + Disable write access watch in this PREGION + 0x0 - STD_GET_DESCRIPTOR - Standard request GET_DESCRIPTOR - 6 + Enable + Enable write access watch in this PREGION + 0x1 + + + + PRGN0RA + Enable/disable read access watch in PREGION[0] + 25 + 25 + - STD_SET_DESCRIPTOR - Standard request SET_DESCRIPTOR - 7 + Disable + Disable read access watch in this PREGION + 0x0 - STD_GET_CONFIGURATION - Standard request GET_CONFIGURATION - 8 + Enable + Enable read access watch in this PREGION + 0x1 + + + + PRGN1WA + Enable/disable write access watch in PREGION[1] + 26 + 26 + - STD_SET_CONFIGURATION - Standard request SET_CONFIGURATION - 9 + Disable + Disable write access watch in this PREGION + 0x0 - STD_GET_INTERFACE - Standard request GET_INTERFACE - 10 + Enable + Enable write access watch in this PREGION + 0x1 + + + + PRGN1RA + Enable/disable read access watch in PREGION[1] + 27 + 27 + - STD_SET_INTERFACE - Standard request SET_INTERFACE - 11 + Disable + Disable read access watch in this PREGION + 0x0 - STD_SYNCH_FRAME - Standard request SYNCH_FRAME - 12 + Enable + Enable read access watch in this PREGION + 0x1 - WVALUEL - SETUP data, byte 2, LSB of wValue - 0x488 - read-only - 0x00000000 - - - WVALUEL - SETUP data, byte 2, LSB of wValue - 0 - 7 - - - - - WVALUEH - SETUP data, byte 3, MSB of wValue - 0x48C - read-only - 0x00000000 - - - WVALUEH - SETUP data, byte 3, MSB of wValue - 0 - 7 - - - - - WINDEXL - SETUP data, byte 4, LSB of wIndex - 0x490 - read-only - 0x00000000 - - - WINDEXL - SETUP data, byte 4, LSB of wIndex - 0 - 7 - - - - - WINDEXH - SETUP data, byte 5, MSB of wIndex - 0x494 - read-only - 0x00000000 - - - WINDEXH - SETUP data, byte 5, MSB of wIndex - 0 - 7 - - - - - WLENGTHL - SETUP data, byte 6, LSB of wLength - 0x498 - read-only + REGIONENSET + Enable regions watch + 0x514 + read-write 0x00000000 + 0x20 - WLENGTHL - SETUP data, byte 6, LSB of wLength + RGN0WA + Enable write access watch in region[0] 0 - 7 + 0 + + read + + Disabled + Write access watch in this region is disabled + 0x0 + + + Enabled + Write access watch in this region is enabled + 0x1 + + + + write + + Set + Enable write access watch in this region + 0x1 + + - - - - WLENGTHH - SETUP data, byte 7, MSB of wLength - 0x49C - read-only - 0x00000000 - - WLENGTHH - SETUP data, byte 7, MSB of wLength - 0 - 7 + RGN0RA + Enable read access watch in region[0] + 1 + 1 + + read + + Disabled + Read access watch in this region is disabled + 0x0 + + + Enabled + Read access watch in this region is enabled + 0x1 + + + + write + + Set + Enable read access watch in this region + 0x1 + + - - - - SIZE - Unspecified - USBD_SIZE - 0x4A0 - - 8 - 0x4 - EPOUT[%s] - Description collection[n]: Number of bytes received last in the data stage of this OUT endpoint - 0x000 - read-write - - - SIZE - Number of bytes received last in the data stage of this OUT endpoint - 0 - 6 - - - - - ISOOUT - Number of bytes received last on this ISO OUT data endpoint - 0x020 - read-only - 0x00010000 - - - SIZE - Number of bytes received last on this ISO OUT data endpoint - 0 - 9 - - - ZERO - Zero-length data packet received - 16 - 16 - - - Normal - No zero-length data received, use value in SIZE - 0 - - - ZeroData - Zero-length data received, ignore value in SIZE - 1 - - - - - - - - ENABLE - Enable USB - 0x500 - read-write - - ENABLE - Enable USB - 0 - 0 + RGN1WA + Enable write access watch in region[1] + 2 + 2 + read Disabled - USB peripheral is disabled - 0 + Write access watch in this region is disabled + 0x0 Enabled - USB peripheral is enabled - 1 + Write access watch in this region is enabled + 0x1 + + + + write + + Set + Enable write access watch in this region + 0x1 - - - - USBPULLUP - Control of the USB pull-up - 0x504 - read-write - - CONNECT - Control of the USB pull-up on the D+ line - 0 - 0 + RGN1RA + Enable read access watch in region[1] + 3 + 3 + read Disabled - Pull-up is disconnected - 0 + Read access watch in this region is disabled + 0x0 Enabled - Pull-up is connected to D+ - 1 + Read access watch in this region is enabled + 0x1 + + + + write + + Set + Enable read access watch in this region + 0x1 - - - - DPDMVALUE - State D+ and D- lines will be forced into by the DPDMDRIVE task. The DPDMNODRIVE task reverts the control of the lines to MAC IP (no forcing). - 0x508 - read-write - - STATE - State D+ and D- lines will be forced into by the DPDMDRIVE task - 0 + RGN2WA + Enable write access watch in region[2] + 4 4 + read - Resume - D+ forced low, D- forced high (K state) for a timing preset in hardware (50 us or 5 ms, depending on bus state) - 1 + Disabled + Write access watch in this region is disabled + 0x0 - J - D+ forced high, D- forced low (J state) - 2 + Enabled + Write access watch in this region is enabled + 0x1 + + + write - K - D+ forced low, D- forced high (K state) - 4 + Set + Enable write access watch in this region + 0x1 - - - - DTOGGLE - Data toggle control and status - 0x50C - read-write - 0x00000100 - - - EP - Select bulk endpoint number - 0 - 2 - - IO - Selects IN or OUT endpoint - 7 - 7 + RGN2RA + Enable read access watch in region[2] + 5 + 5 + read - Out - Selects OUT endpoint - 0 + Disabled + Read access watch in this region is disabled + 0x0 - In - Selects IN endpoint - 1 + Enabled + Read access watch in this region is enabled + 0x1 + + + + write + + Set + Enable read access watch in this region + 0x1 - VALUE - Data toggle value - 8 - 9 + RGN3WA + Enable write access watch in region[3] + 6 + 6 + read - Nop - No action on data toggle when writing the register with this value - 0 + Disabled + Write access watch in this region is disabled + 0x0 - Data0 - Data toggle is DATA0 on endpoint set by EP and IO - 1 + Enabled + Write access watch in this region is enabled + 0x1 + + + write - Data1 - Data toggle is DATA1 on endpoint set by EP and IO - 2 + Set + Enable write access watch in this region + 0x1 - - - - EPINEN - Endpoint IN enable - 0x510 - read-write - 0x00000001 - - IN0 - Enable IN endpoint 0 - 0 - 0 + RGN3RA + Enable read access watch in region[3] + 7 + 7 + read - Disable - Disable endpoint IN 0 (no response to IN tokens) - 0 + Disabled + Read access watch in this region is disabled + 0x0 - Enable - Enable endpoint IN 0 (response to IN tokens) - 1 + Enabled + Read access watch in this region is enabled + 0x1 + + + + write + + Set + Enable read access watch in this region + 0x1 - IN1 - Enable IN endpoint 1 - 1 - 1 + PRGN0WA + Enable write access watch in PREGION[0] + 24 + 24 + read - Disable - Disable endpoint IN 1 (no response to IN tokens) - 0 + Disabled + Write access watch in this PREGION is disabled + 0x0 - Enable - Enable endpoint IN 1 (response to IN tokens) - 1 + Enabled + Write access watch in this PREGION is enabled + 0x1 - - - IN2 - Enable IN endpoint 2 - 2 - 2 + write - Disable - Disable endpoint IN 2 (no response to IN tokens) - 0 - - - Enable - Enable endpoint IN 2 (response to IN tokens) - 1 + Set + Enable write access watch in this PREGION + 0x1 - IN3 - Enable IN endpoint 3 - 3 - 3 + PRGN0RA + Enable read access watch in PREGION[0] + 25 + 25 + read - Disable - Disable endpoint IN 3 (no response to IN tokens) - 0 + Disabled + Read access watch in this PREGION is disabled + 0x0 - Enable - Enable endpoint IN 3 (response to IN tokens) - 1 + Enabled + Read access watch in this PREGION is enabled + 0x1 - - - IN4 - Enable IN endpoint 4 - 4 - 4 + write - Disable - Disable endpoint IN 4 (no response to IN tokens) - 0 - - - Enable - Enable endpoint IN 4 (response to IN tokens) - 1 + Set + Enable read access watch in this PREGION + 0x1 - IN5 - Enable IN endpoint 5 - 5 - 5 + PRGN1WA + Enable write access watch in PREGION[1] + 26 + 26 + read - Disable - Disable endpoint IN 5 (no response to IN tokens) - 0 + Disabled + Write access watch in this PREGION is disabled + 0x0 - Enable - Enable endpoint IN 5 (response to IN tokens) - 1 + Enabled + Write access watch in this PREGION is enabled + 0x1 - - - IN6 - Enable IN endpoint 6 - 6 - 6 + write - Disable - Disable endpoint IN 6 (no response to IN tokens) - 0 - - - Enable - Enable endpoint IN 6 (response to IN tokens) - 1 + Set + Enable write access watch in this PREGION + 0x1 - IN7 - Enable IN endpoint 7 - 7 - 7 + PRGN1RA + Enable read access watch in PREGION[1] + 27 + 27 + read - Disable - Disable endpoint IN 7 (no response to IN tokens) - 0 + Disabled + Read access watch in this PREGION is disabled + 0x0 - Enable - Enable endpoint IN 7 (response to IN tokens) - 1 + Enabled + Read access watch in this PREGION is enabled + 0x1 - - - ISOIN - Enable ISO IN endpoint - 8 - 8 + write - Disable - Disable ISO IN endpoint 8 - 0 - - - Enable - Enable ISO IN endpoint 8 - 1 + Set + Enable read access watch in this PREGION + 0x1 - EPOUTEN - Endpoint OUT enable - 0x514 + REGIONENCLR + Disable regions watch + 0x518 read-write - 0x00000001 + 0x00000000 + 0x20 - OUT0 - Enable OUT endpoint 0 + RGN0WA + Disable write access watch in region[0] 0 0 + read - Disable - Disable endpoint OUT 0 (no response to OUT tokens) - 0 + Disabled + Write access watch in this region is disabled + 0x0 - Enable - Enable endpoint OUT 0 (response to OUT tokens) - 1 + Enabled + Write access watch in this region is enabled + 0x1 + + + + write + + Clear + Disable write access watch in this region + 0x1 - OUT1 - Enable OUT endpoint 1 + RGN0RA + Disable read access watch in region[0] 1 1 + read - Disable - Disable endpoint OUT 1 (no response to OUT tokens) - 0 + Disabled + Read access watch in this region is disabled + 0x0 - Enable - Enable endpoint OUT 1 (response to OUT tokens) - 1 + Enabled + Read access watch in this region is enabled + 0x1 + + + + write + + Clear + Disable read access watch in this region + 0x1 - OUT2 - Enable OUT endpoint 2 + RGN1WA + Disable write access watch in region[1] 2 2 + read - Disable - Disable endpoint OUT 2 (no response to OUT tokens) - 0 + Disabled + Write access watch in this region is disabled + 0x0 - Enable - Enable endpoint OUT 2 (response to OUT tokens) - 1 + Enabled + Write access watch in this region is enabled + 0x1 + + + + write + + Clear + Disable write access watch in this region + 0x1 - OUT3 - Enable OUT endpoint 3 + RGN1RA + Disable read access watch in region[1] 3 3 + read - Disable - Disable endpoint OUT 3 (no response to OUT tokens) - 0 + Disabled + Read access watch in this region is disabled + 0x0 - Enable - Enable endpoint OUT 3 (response to OUT tokens) - 1 + Enabled + Read access watch in this region is enabled + 0x1 + + + + write + + Clear + Disable read access watch in this region + 0x1 - OUT4 - Enable OUT endpoint 4 + RGN2WA + Disable write access watch in region[2] 4 4 + read - Disable - Disable endpoint OUT 4 (no response to OUT tokens) - 0 + Disabled + Write access watch in this region is disabled + 0x0 - Enable - Enable endpoint OUT 4 (response to OUT tokens) - 1 + Enabled + Write access watch in this region is enabled + 0x1 + + + + write + + Clear + Disable write access watch in this region + 0x1 - OUT5 - Enable OUT endpoint 5 + RGN2RA + Disable read access watch in region[2] 5 5 + read - Disable - Disable endpoint OUT 5 (no response to OUT tokens) - 0 + Disabled + Read access watch in this region is disabled + 0x0 - Enable - Enable endpoint OUT 5 (response to OUT tokens) - 1 + Enabled + Read access watch in this region is enabled + 0x1 + + + + write + + Clear + Disable read access watch in this region + 0x1 - OUT6 - Enable OUT endpoint 6 + RGN3WA + Disable write access watch in region[3] 6 6 + read - Disable - Disable endpoint OUT 6 (no response to OUT tokens) - 0 + Disabled + Write access watch in this region is disabled + 0x0 - Enable - Enable endpoint OUT 6 (response to OUT tokens) - 1 + Enabled + Write access watch in this region is enabled + 0x1 + + + + write + + Clear + Disable write access watch in this region + 0x1 - OUT7 - Enable OUT endpoint 7 + RGN3RA + Disable read access watch in region[3] 7 7 + read - Disable - Disable endpoint OUT 7 (no response to OUT tokens) - 0 + Disabled + Read access watch in this region is disabled + 0x0 - Enable - Enable endpoint OUT 7 (response to OUT tokens) - 1 + Enabled + Read access watch in this region is enabled + 0x1 - - - ISOOUT - Enable ISO OUT endpoint 8 - 8 - 8 + write - Disable - Disable ISO OUT endpoint 8 - 0 - - - Enable - Enable ISO OUT endpoint 8 - 1 + Clear + Disable read access watch in this region + 0x1 - - - - EPSTALL - STALL endpoints - 0x518 - write-only - 0x00000000 - modifyExternal - - - EP - Select endpoint number - 0 - 2 - - IO - Selects IN or OUT endpoint - 7 - 7 + PRGN0WA + Disable write access watch in PREGION[0] + 24 + 24 + read - Out - Selects OUT endpoint - 0 + Disabled + Write access watch in this PREGION is disabled + 0x0 - In - Selects IN endpoint - 1 + Enabled + Write access watch in this PREGION is enabled + 0x1 - - - STALL - Stall selected endpoint - 8 - 8 + write - UnStall - Don't stall selected endpoint - 0 - - - Stall - Stall selected endpoint - 1 + Clear + Disable write access watch in this PREGION + 0x1 - - - - ISOSPLIT - Controls the split of ISO buffers - 0x51C - read-write - - SPLIT - Controls the split of ISO buffers - 0 - 15 + PRGN0RA + Disable read access watch in PREGION[0] + 25 + 25 + read - OneDir - Full buffer dedicated to either iso IN or OUT - 0x0000 + Disabled + Read access watch in this PREGION is disabled + 0x0 - HalfIN - Lower half for IN, upper half for OUT - 0x0080 + Enabled + Read access watch in this PREGION is enabled + 0x1 + + + + write + + Clear + Disable read access watch in this PREGION + 0x1 - - - - FRAMECNTR - Returns the current value of the start of frame counter - 0x520 - read-only - - - FRAMECNTR - Returns the current value of the start of frame counter - 0 - 10 - - - - - LOWPOWER - Controls USBD peripheral low power mode during USB suspend - 0x52C - read-write - 0x00000000 - - LOWPOWER - Controls USBD peripheral low-power mode during USB suspend - 0 - 0 + PRGN1WA + Disable write access watch in PREGION[1] + 26 + 26 + read - ForceNormal - Software must write this value to exit low power mode and before performing a remote wake-up - 0 + Disabled + Write access watch in this PREGION is disabled + 0x0 - LowPower - Software must write this value to enter low power mode after DMA and software have finished interacting with the USB peripheral - 1 + Enabled + Write access watch in this PREGION is enabled + 0x1 + + + + write + + Clear + Disable write access watch in this PREGION + 0x1 - - - - ISOINCONFIG - Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent - 0x530 - read-write - - RESPONSE - Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent - 0 - 0 + PRGN1RA + Disable read access watch in PREGION[1] + 27 + 27 + read - NoResp - Endpoint does not respond in that case - 0 + Disabled + Read access watch in this PREGION is disabled + 0x0 - ZeroData - Endpoint responds with a zero-length data packet in that case - 1 + Enabled + Read access watch in this PREGION is enabled + 0x1 - - - - - 8 - 0x014 - EPIN[%s] - Unspecified - USBD_EPIN - 0x600 - - PTR - Description cluster[n]: Data pointer - 0x000 - read-write - - - PTR - Data pointer. Accepts any address in Data RAM. - 0 - 31 - - - - - MAXCNT - Description cluster[n]: Maximum number of bytes to transfer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes to transfer - 0 - 6 - - - - - AMOUNT - Description cluster[n]: Number of bytes transferred in the last transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last transaction - 0 - 6 - - - - + + write + + Clear + Disable read access watch in this PREGION + 0x1 + + + + + - ISOIN + 4 + 0x010 + REGION[%s] Unspecified - USBD_ISOIN - 0x6A0 + MWU_REGION + read-write + 0x600 - PTR - Data pointer + START + Description cluster: Start address for region n 0x000 read-write + 0x00000000 + 0x20 - PTR - Data pointer. Accepts any address in Data RAM. + START + Start address for region 0 31 - MAXCNT - Maximum number of bytes to transfer + END + Description cluster: End address of region n 0x004 read-write + 0x00000000 + 0x20 - MAXCNT - Maximum number of bytes to transfer + END + End address of region. 0 - 9 + 31 + + + 2 + 0x010 + PREGION[%s] + Unspecified + MWU_PREGION + read-write + 0x6C0 - AMOUNT - Number of bytes transferred in the last transaction - 0x008 + START + Description cluster: Reserved for future use + 0x000 read-only + 0x00000000 + 0x20 - AMOUNT - Number of bytes transferred in the last transaction + START + Reserved for future use 0 - 9 + 31 - - - 8 - 0x014 - EPOUT[%s] - Unspecified - USBD_EPOUT - 0x700 - PTR - Description cluster[n]: Data pointer - 0x000 - read-write + END + Description cluster: Reserved for future use + 0x004 + read-only + 0x00000000 + 0x20 - PTR - Data pointer. Accepts any address in Data RAM. + END + Reserved for future use 0 31 - MAXCNT - Description cluster[n]: Maximum number of bytes to transfer - 0x004 + SUBS + Description cluster: Subregions of region n + 0x008 read-write + 0x00000000 + 0x20 - MAXCNT - Maximum number of bytes to transfer + SR0 + Include or exclude subregion 0 in region 0 + 0 + + + Exclude + Exclude + 0x0 + + + Include + Include + 0x1 + + + + + SR1 + Include or exclude subregion 1 in region + 1 + 1 + + + Exclude + Exclude + 0x0 + + + Include + Include + 0x1 + + + + + SR2 + Include or exclude subregion 2 in region + 2 + 2 + + + Exclude + Exclude + 0x0 + + + Include + Include + 0x1 + + + + + SR3 + Include or exclude subregion 3 in region + 3 + 3 + + + Exclude + Exclude + 0x0 + + + Include + Include + 0x1 + + + + + SR4 + Include or exclude subregion 4 in region + 4 + 4 + + + Exclude + Exclude + 0x0 + + + Include + Include + 0x1 + + + + + SR5 + Include or exclude subregion 5 in region + 5 + 5 + + + Exclude + Exclude + 0x0 + + + Include + Include + 0x1 + + + + + SR6 + Include or exclude subregion 6 in region + 6 6 + + + Exclude + Exclude + 0x0 + + + Include + Include + 0x1 + + + + + SR7 + Include or exclude subregion 7 in region + 7 + 7 + + + Exclude + Exclude + 0x0 + + + Include + Include + 0x1 + + + + + SR8 + Include or exclude subregion 8 in region + 8 + 8 + + + Exclude + Exclude + 0x0 + + + Include + Include + 0x1 + + + + + SR9 + Include or exclude subregion 9 in region + 9 + 9 + + + Exclude + Exclude + 0x0 + + + Include + Include + 0x1 + + + + + SR10 + Include or exclude subregion 10 in region + 10 + 10 + + + Exclude + Exclude + 0x0 + + + Include + Include + 0x1 + + + + + SR11 + Include or exclude subregion 11 in region + 11 + 11 + + + Exclude + Exclude + 0x0 + + + Include + Include + 0x1 + + + + + SR12 + Include or exclude subregion 12 in region + 12 + 12 + + + Exclude + Exclude + 0x0 + + + Include + Include + 0x1 + + + + + SR13 + Include or exclude subregion 13 in region + 13 + 13 + + + Exclude + Exclude + 0x0 + + + Include + Include + 0x1 + + + + + SR14 + Include or exclude subregion 14 in region + 14 + 14 + + + Exclude + Exclude + 0x0 + + + Include + Include + 0x1 + + + + + SR15 + Include or exclude subregion 15 in region + 15 + 15 + + + Exclude + Exclude + 0x0 + + + Include + Include + 0x1 + + + + + SR16 + Include or exclude subregion 16 in region + 16 + 16 + + + Exclude + Exclude + 0x0 + + + Include + Include + 0x1 + + + + + SR17 + Include or exclude subregion 17 in region + 17 + 17 + + + Exclude + Exclude + 0x0 + + + Include + Include + 0x1 + + + + + SR18 + Include or exclude subregion 18 in region + 18 + 18 + + + Exclude + Exclude + 0x0 + + + Include + Include + 0x1 + + + + + SR19 + Include or exclude subregion 19 in region + 19 + 19 + + + Exclude + Exclude + 0x0 + + + Include + Include + 0x1 + + + + + SR20 + Include or exclude subregion 20 in region + 20 + 20 + + + Exclude + Exclude + 0x0 + + + Include + Include + 0x1 + + + + + SR21 + Include or exclude subregion 21 in region + 21 + 21 + + + Exclude + Exclude + 0x0 + + + Include + Include + 0x1 + + + + + SR22 + Include or exclude subregion 22 in region + 22 + 22 + + + Exclude + Exclude + 0x0 + + + Include + Include + 0x1 + + + + + SR23 + Include or exclude subregion 23 in region + 23 + 23 + + + Exclude + Exclude + 0x0 + + + Include + Include + 0x1 + + + + + SR24 + Include or exclude subregion 24 in region + 24 + 24 + + + Exclude + Exclude + 0x0 + + + Include + Include + 0x1 + + + + + SR25 + Include or exclude subregion 25 in region + 25 + 25 + + + Exclude + Exclude + 0x0 + + + Include + Include + 0x1 + + + + + SR26 + Include or exclude subregion 26 in region + 26 + 26 + + + Exclude + Exclude + 0x0 + + + Include + Include + 0x1 + + + + + SR27 + Include or exclude subregion 27 in region + 27 + 27 + + + Exclude + Exclude + 0x0 + + + Include + Include + 0x1 + + - - - - AMOUNT - Description cluster[n]: Number of bytes transferred in the last transaction - 0x008 - read-only - - AMOUNT - Number of bytes transferred in the last transaction - 0 - 6 + SR28 + Include or exclude subregion 28 in region + 28 + 28 + + + Exclude + Exclude + 0x0 + + + Include + Include + 0x1 + + - - - - - ISOOUT - Unspecified - USBD_ISOOUT - 0x7A0 - - PTR - Data pointer - 0x000 - read-write - - PTR - Data pointer. Accepts any address in Data RAM. - 0 - 31 + SR29 + Include or exclude subregion 29 in region + 29 + 29 + + + Exclude + Exclude + 0x0 + + + Include + Include + 0x1 + + - - - - MAXCNT - Maximum number of bytes to transfer - 0x004 - read-write - - MAXCNT - Maximum number of bytes to transfer - 0 - 9 + SR30 + Include or exclude subregion 30 in region + 30 + 30 + + + Exclude + Exclude + 0x0 + + + Include + Include + 0x1 + + - - - - AMOUNT - Number of bytes transferred in the last transaction - 0x008 - read-only - - AMOUNT - Number of bytes transferred in the last transaction - 0 - 9 + SR31 + Include or exclude subregion 31 in region + 31 + 31 + + + Exclude + Exclude + 0x0 + + + Include + Include + 0x1 + + - - UARTE1 - UART with EasyDMA 1 - 0x40028000 + + PWM1 + Pulse width modulation unit 1 + 0x40021000 - UARTE1 - 40 + PWM1 + 33 + + + + PWM2 + Pulse width modulation unit 2 + 0x40022000 + + PWM2 + 34 + + + + SPI2 + Serial Peripheral Interface 2 + 0x40023000 + + SPI2_SPIM2_SPIS2 + 35 + + + + SPIM2 + Serial Peripheral Interface Master with EasyDMA 2 + 0x40023000 + SPI2 + + SPI2_SPIM2_SPIS2 + 35 + + + + SPIS2 + SPI Slave 2 + 0x40023000 + SPI2 + + SPI2_SPIM2_SPIS2 + 35 + + + + RTC2 + Real time counter 2 + 0x40024000 + + RTC2 + 36 - QSPI - External flash interface - 0x40029000 + I2S + Inter-IC Sound + 0x40025000 0 0x1000 registers - QSPI - 41 + I2S + 37 - QSPI + I2S 0x20 - TASKS_ACTIVATE - Activate QSPI interface + TASKS_START + Starts continuous I2S transfer. Also starts MCK generator when this is enabled. 0x000 write-only + 0x00000000 + 0x20 - TASKS_ACTIVATE + TASKS_START + Starts continuous I2S transfer. Also starts MCK generator when this is enabled. 0 0 + + + Trigger + Trigger task + 0x1 + + - TASKS_READSTART - Start transfer from external flash memory to internal RAM + TASKS_STOP + Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. 0x004 write-only + 0x00000000 + 0x20 - TASKS_READSTART - 0 - 0 - - - - - TASKS_WRITESTART - Start transfer from internal RAM to external flash memory - 0x008 - write-only - - - TASKS_WRITESTART + TASKS_STOP + Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. 0 0 + + + Trigger + Trigger task + 0x1 + + - TASKS_ERASESTART - Start external flash memory erase operation - 0x00C - write-only + EVENTS_RXPTRUPD + The RXD.PTR register has been copied to internal double-buffers. + When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. + 0x104 + read-write + 0x00000000 + 0x20 - TASKS_ERASESTART + EVENTS_RXPTRUPD + The RXD.PTR register has been copied to internal double-buffers. + When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. 0 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + - TASKS_DEACTIVATE - Deactivate QSPI interface - 0x010 - write-only + EVENTS_STOPPED + I2S transfer stopped. + 0x108 + read-write + 0x00000000 + 0x20 - TASKS_DEACTIVATE + EVENTS_STOPPED + I2S transfer stopped. 0 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + - EVENTS_READY - QSPI peripheral is ready. This event will be generated as a response to any QSPI task. - 0x100 + EVENTS_TXPTRUPD + The TDX.PTR register has been copied to internal double-buffers. + When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. + 0x114 read-write + 0x00000000 + 0x20 - EVENTS_READY + EVENTS_TXPTRUPD + The TDX.PTR register has been copied to internal double-buffers. + When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. 0 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + @@ -44807,22 +49420,60 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Enable or disable interrupt 0x300 read-write + 0x00000000 + 0x20 - READY - Enable or disable interrupt for READY event - 0 - 0 + RXPTRUPD + Enable or disable interrupt for event RXPTRUPD + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + STOPPED + Enable or disable interrupt for event STOPPED + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TXPTRUPD + Enable or disable interrupt for event TXPTRUPD + 5 + 5 Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -44833,23 +49484,79 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Enable interrupt 0x304 read-write + 0x00000000 + 0x20 - READY - Write '1' to enable interrupt for READY event - 0 - 0 + RXPTRUPD + Write '1' to enable interrupt for event RXPTRUPD + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TXPTRUPD + Write '1' to enable interrupt for event TXPTRUPD + 5 + 5 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -44857,7 +49564,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Set Enable - 1 + 0x1 @@ -44868,23 +49575,79 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disable interrupt 0x308 read-write + 0x00000000 + 0x20 - READY - Write '1' to disable interrupt for READY event - 0 - 0 + RXPTRUPD + Write '1' to disable interrupt for event RXPTRUPD + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TXPTRUPD + Write '1' to disable interrupt for event TXPTRUPD + 5 + 5 read Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -44892,7 +49655,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Clear Disable - 1 + 0x1 @@ -44900,171 +49663,413 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ ENABLE - Enable QSPI peripheral and acquire the pins selected in PSELn registers + Enable I2S module. 0x500 read-write + 0x00000000 + 0x20 ENABLE - Enable or disable QSPI + Enable I2S module. 0 0 Disabled - Disable QSPI - 0 + Disable + 0x0 Enabled - Enable QSPI - 1 + Enable + 0x1 - READ + CONFIG Unspecified - QSPI_READ + I2S_CONFIG + read-write 0x504 - SRC - Flash memory source address + MODE + I2S mode. 0x000 read-write + 0x00000000 + 0x20 - SRC - Word-aligned flash memory source address. + MODE + I2S mode. 0 - 31 + 0 + + + Master + Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. + 0x0 + + + Slave + Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx + 0x1 + + + + + + + RXEN + Reception (RX) enable. + 0x004 + read-write + 0x00000000 + 0x20 + + + RXEN + Reception (RX) enable. + 0 + 0 + + + Disabled + Reception disabled and now data will be written to the RXD.PTR address. + 0x0 + + + Enabled + Reception enabled. + 0x1 + + + + + + + TXEN + Transmission (TX) enable. + 0x008 + read-write + 0x00000001 + 0x20 + + + TXEN + Transmission (TX) enable. + 0 + 0 + + + Disabled + Transmission disabled and now data will be read from the RXD.TXD address. + 0x0 + + + Enabled + Transmission enabled. + 0x1 + + - DST - RAM destination address - 0x004 + MCKEN + Master clock generator enable. + 0x00C read-write + 0x00000001 + 0x20 - DST - Word-aligned RAM destination address. + MCKEN + Master clock generator enable. 0 - 31 + 0 + + + Disabled + Master clock generator disabled and PSEL.MCK not connected(available as GPIO). + 0x0 + + + Enabled + Master clock generator running and MCK output on PSEL.MCK. + 0x1 + + - CNT - Read transfer length - 0x008 + MCKFREQ + Master clock generator frequency. + 0x010 read-write + 0x20000000 + 0x20 - CNT - Read transfer length in number of bytes. The length must be a multiple of 4 bytes. + MCKFREQ + Master clock generator frequency. 0 - 20 + 31 + + + 32MDIV8 + 32 MHz / 8 = 4.0 MHz + 0x20000000 + + + 32MDIV10 + 32 MHz / 10 = 3.2 MHz + 0x18000000 + + + 32MDIV11 + 32 MHz / 11 = 2.9090909 MHz + 0x16000000 + + + 32MDIV15 + 32 MHz / 15 = 2.1333333 MHz + 0x11000000 + + + 32MDIV16 + 32 MHz / 16 = 2.0 MHz + 0x10000000 + + + 32MDIV21 + 32 MHz / 21 = 1.5238095 + 0x0C000000 + + + 32MDIV23 + 32 MHz / 23 = 1.3913043 MHz + 0x0B000000 + + + 32MDIV30 + 32 MHz / 30 = 1.0666667 MHz + 0x08800000 + + + 32MDIV31 + 32 MHz / 31 = 1.0322581 MHz + 0x08400000 + + + 32MDIV32 + 32 MHz / 32 = 1.0 MHz + 0x08000000 + + + 32MDIV42 + 32 MHz / 42 = 0.7619048 MHz + 0x06000000 + + + 32MDIV63 + 32 MHz / 63 = 0.5079365 MHz + 0x04100000 + + + 32MDIV125 + 32 MHz / 125 = 0.256 MHz + 0x020C0000 + + - - - WRITE - Unspecified - QSPI_WRITE - 0x510 - DST - Flash destination address - 0x000 + RATIO + MCK / LRCK ratio. + 0x014 read-write + 0x00000006 + 0x20 - DST - Word-aligned flash destination address. + RATIO + MCK / LRCK ratio. 0 - 31 + 3 + + + 32X + LRCK = MCK / 32 + 0x0 + + + 48X + LRCK = MCK / 48 + 0x1 + + + 64X + LRCK = MCK / 64 + 0x2 + + + 96X + LRCK = MCK / 96 + 0x3 + + + 128X + LRCK = MCK / 128 + 0x4 + + + 192X + LRCK = MCK / 192 + 0x5 + + + 256X + LRCK = MCK / 256 + 0x6 + + + 384X + LRCK = MCK / 384 + 0x7 + + + 512X + LRCK = MCK / 512 + 0x8 + + - SRC - RAM source address - 0x004 + SWIDTH + Sample width. + 0x018 read-write + 0x00000001 + 0x20 - SRC - Word-aligned RAM source address. + SWIDTH + Sample width. 0 - 31 + 1 + + + 8Bit + 8 bit. + 0x0 + + + 16Bit + 16 bit. + 0x1 + + + 24Bit + 24 bit. + 0x2 + + - CNT - Write transfer length - 0x008 + ALIGN + Alignment of sample within a frame. + 0x01C read-write + 0x00000000 + 0x20 - CNT - Write transfer length in number of bytes. The length must be a multiple of 4 bytes. + ALIGN + Alignment of sample within a frame. 0 - 20 + 0 + + + Left + Left-aligned. + 0x0 + + + Right + Right-aligned. + 0x1 + + - - - ERASE - Unspecified - QSPI_ERASE - 0x51C - PTR - Start address of flash block to be erased - 0x000 + FORMAT + Frame format. + 0x020 read-write + 0x00000000 + 0x20 - PTR - Word-aligned start address of block to be erased. + FORMAT + Frame format. 0 - 31 + 0 + + + I2S + Original I2S format. + 0x0 + + + Aligned + Alternate (left- or right-aligned) format. + 0x1 + + - LEN - Size of block to be erased. - 0x004 + CHANNELS + Enable channels. + 0x024 read-write + 0x00000000 + 0x20 - LEN - LEN + CHANNELS + Enable channels. 0 1 - 4KB - Erase 4 kB block (flash command 0x20) - 0 + Stereo + Stereo. + 0x0 - 64KB - Erase 64 kB block (flash command 0xD8) - 1 + Left + Left only. + 0x1 - All - Erase all (flash command 0xC7) - 2 + Right + Right only. + 0x2 @@ -45072,55 +50077,87 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ - PSEL + RXD Unspecified - QSPI_PSEL - 0x524 + I2S_RXD + read-write + 0x538 - SCK - Pin select for serial clock SCK + PTR + Receive buffer RAM start address. 0x000 read-write - 0xFFFFFFFF + 0x00000000 + 0x20 - PIN - Pin number + PTR + Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. 0 - 4 + 31 + + + + + TXD + Unspecified + I2S_TXD + read-write + 0x540 + + PTR + Transmit buffer RAM start address. + 0x000 + read-write + 0x00000000 + 0x20 + - PORT - Port number - 5 - 5 + PTR + Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. + 0 + 31 + + + + + RXTXD + Unspecified + I2S_RXTXD + read-write + 0x550 + + MAXCNT + Size of RXD and TXD buffers. + 0x000 + read-write + 0x00000000 + 0x20 + - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - + MAXCNT + Size of RXD and TXD buffers in number of 32 bit words. + 0 + 13 + + + PSEL + Unspecified + I2S_PSEL + read-write + 0x560 - CSN - Pin select for chip select signal CSN. - 0x004 + MCK + Pin select for MCK signal. + 0x000 read-write 0xFFFFFFFF + 0x20 PIN @@ -45143,23 +50180,24 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disconnected Disconnect - 1 + 0x1 Connected Connect - 0 + 0x0 - IO0 - Pin select for serial data MOSI/IO0. - 0x00C + SCK + Pin select for SCK signal. + 0x004 read-write 0xFFFFFFFF + 0x20 PIN @@ -45182,23 +50220,24 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disconnected Disconnect - 1 + 0x1 Connected Connect - 0 + 0x0 - IO1 - Pin select for serial data MISO/IO1. - 0x010 + LRCK + Pin select for LRCK signal. + 0x008 read-write 0xFFFFFFFF + 0x20 PIN @@ -45221,23 +50260,24 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disconnected Disconnect - 1 + 0x1 Connected Connect - 0 + 0x0 - IO2 - Pin select for serial data IO2. - 0x014 + SDIN + Pin select for SDIN signal. + 0x00C read-write 0xFFFFFFFF + 0x20 PIN @@ -45260,23 +50300,24 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disconnected Disconnect - 1 + 0x1 Connected Connect - 0 + 0x0 - IO3 - Pin select for serial data IO3. - 0x018 + SDOUT + Pin select for SDOUT signal. + 0x010 read-write 0xFFFFFFFF + 0x20 PIN @@ -45299,6853 +50340,10286 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ Disconnected Disconnect - 1 + 0x1 Connected Connect - 0 + 0x0 + + + + FPU + FPU + 0x40026000 + + 0 + 0x1000 + registers + + + FPU + 38 + + FPU + 0x20 + + + UNUSED + Unused. + 0x000 + 0x00000000 + read-only + + + + + USBD + Universal serial bus device + 0x40027000 + + 0 + 0x1000 + registers + + + USBD + 39 + + USBD + 0x20 + + + 0x8 + 0x4 + TASKS_STARTEPIN[%s] + Description collection: Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STARTEPIN + Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STARTISOIN + Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint + 0x024 + write-only + 0x00000000 + 0x20 + + + TASKS_STARTISOIN + Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + TASKS_STARTEPOUT[%s] + Description collection: Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host + 0x028 + write-only + 0x00000000 + 0x20 + + + TASKS_STARTEPOUT + Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STARTISOOUT + Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint + 0x048 + write-only + 0x00000000 + 0x20 + + + TASKS_STARTISOOUT + Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_EP0RCVOUT + Allows OUT data stage on control endpoint 0 + 0x04C + write-only + 0x00000000 + 0x20 + + + TASKS_EP0RCVOUT + Allows OUT data stage on control endpoint 0 + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + - XIPOFFSET - Address offset into the external memory for Execute in Place operation. - 0x540 - read-write + TASKS_EP0STATUS + Allows status stage on control endpoint 0 + 0x050 + write-only + 0x00000000 + 0x20 - XIPOFFSET - Address offset into the external memory for Execute in Place operation. Value must be a multiple of 4. + TASKS_EP0STATUS + Allows status stage on control endpoint 0 0 - 31 + 0 + + + Trigger + Trigger task + 0x1 + + - IFCONFIG0 - Interface configuration. - 0x544 - read-write + TASKS_EP0STALL + Stalls data and status stage on control endpoint 0 + 0x054 + write-only + 0x00000000 + 0x20 - READOC - Configure number of data lines and opcode used for reading. + TASKS_EP0STALL + Stalls data and status stage on control endpoint 0 0 - 2 + 0 - FASTREAD - Single data line SPI. FAST_READ (opcode 0x0B). - 0 + Trigger + Trigger task + 0x1 + + + + + + TASKS_DPDMDRIVE + Forces D+ and D- lines into the state defined in the DPDMVALUE register + 0x058 + write-only + 0x00000000 + 0x20 + + + TASKS_DPDMDRIVE + Forces D+ and D- lines into the state defined in the DPDMVALUE register + 0 + 0 + - READ2O - Dual data line SPI. READ2O (opcode 0x3B). - 1 + Trigger + Trigger task + 0x1 + + + + + + TASKS_DPDMNODRIVE + Stops forcing D+ and D- lines into any state (USB engine takes control) + 0x05C + write-only + 0x00000000 + 0x20 + + + TASKS_DPDMNODRIVE + Stops forcing D+ and D- lines into any state (USB engine takes control) + 0 + 0 + - READ2IO - Dual data line SPI. READ2IO (opcode 0xBB). - 2 + Trigger + Trigger task + 0x1 + + + + + + EVENTS_USBRESET + Signals that a USB reset condition has been detected on USB lines + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_USBRESET + Signals that a USB reset condition has been detected on USB lines + 0 + 0 + - READ4O - Quad data line SPI. READ4O (opcode 0x6B). - 3 + NotGenerated + Event not generated + 0x0 - READ4IO - Quad data line SPI. READ4IO (opcode 0xEB). - 4 + Generated + Event generated + 0x1 + + + + EVENTS_STARTED + Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register + 0x104 + read-write + 0x00000000 + 0x20 + - WRITEOC - Configure number of data lines and opcode used for writing. - 3 - 5 + EVENTS_STARTED + Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register + 0 + 0 - PP - Single data line SPI. PP (opcode 0x02). - 0 + NotGenerated + Event not generated + 0x0 - PP2O - Dual data line SPI. PP2O (opcode 0xA2). - 1 + Generated + Event generated + 0x1 + + + + + + 0x8 + 0x4 + EVENTS_ENDEPIN[%s] + Description collection: The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software. + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_ENDEPIN + The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software. + 0 + 0 + - PP4O - Quad data line SPI. PP4O (opcode 0x32). - 2 + NotGenerated + Event not generated + 0x0 - PP4IO - Quad data line SPI. PP4IO (opcode 0x38). - 3 + Generated + Event generated + 0x1 + + + + EVENTS_EP0DATADONE + An acknowledged data transfer has taken place on the control endpoint + 0x128 + read-write + 0x00000000 + 0x20 + - ADDRMODE - Addressing mode. - 6 - 6 + EVENTS_EP0DATADONE + An acknowledged data transfer has taken place on the control endpoint + 0 + 0 - 24BIT - 24-bit addressing. - 0 + NotGenerated + Event not generated + 0x0 - 32BIT - 32-bit addressing. - 1 + Generated + Event generated + 0x1 + + + + EVENTS_ENDISOIN + The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software. + 0x12C + read-write + 0x00000000 + 0x20 + - DPMENABLE - Enable deep power-down mode (DPM) feature. - 7 - 7 + EVENTS_ENDISOIN + The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software. + 0 + 0 - Disable - Disable DPM feature. - 0 + NotGenerated + Event not generated + 0x0 - Enable - Enable DPM feature. - 1 + Generated + Event generated + 0x1 + + + + 0x8 + 0x4 + EVENTS_ENDEPOUT[%s] + Description collection: The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software. + 0x130 + read-write + 0x00000000 + 0x20 + - PPSIZE - Page size for commands PP, PP2O, PP4O and PP4IO. - 12 - 12 + EVENTS_ENDEPOUT + The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software. + 0 + 0 - 256Bytes - 256 bytes. - 0 + NotGenerated + Event not generated + 0x0 - 512Bytes - 512 bytes. - 1 + Generated + Event generated + 0x1 - IFCONFIG1 - Interface configuration. - 0x600 + EVENTS_ENDISOOUT + The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software. + 0x150 read-write - 0x00040480 + 0x00000000 + 0x20 - SCKDELAY - Minimum amount of time that the CSN pin must stay high before it can go low again. Value is specified in number of 16 MHz periods (62.5 ns). + EVENTS_ENDISOOUT + The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software. 0 - 7 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + EVENTS_SOF + Signals that a SOF (start of frame) condition has been detected on USB lines + 0x154 + read-write + 0x00000000 + 0x20 + - DPMEN - Enter/exit deep power-down mode (DPM) for external flash memory. - 24 - 24 + EVENTS_SOF + Signals that a SOF (start of frame) condition has been detected on USB lines + 0 + 0 - Exit - Exit DPM. - 0 + NotGenerated + Event not generated + 0x0 - Enter - Enter DPM. - 1 + Generated + Event generated + 0x1 + + + + EVENTS_USBEVENT + An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. + 0x158 + read-write + 0x00000000 + 0x20 + - SPIMODE - Select SPI mode. - 25 - 25 + EVENTS_USBEVENT + An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. + 0 + 0 - MODE0 - Mode 0: Data are captured on the clock rising edge and data is output on a falling edge. Base level of clock is 0 (CPOL=0, CPHA=0). - 0 + NotGenerated + Event not generated + 0x0 - MODE3 - Mode 3: Data are captured on the clock falling edge and data is output on a rising edge. Base level of clock is 1 (CPOL=1, CPHA=1). - 1 + Generated + Event generated + 0x1 + + + + EVENTS_EP0SETUP + A valid SETUP token has been received (and acknowledged) on the control endpoint + 0x15C + read-write + 0x00000000 + 0x20 + - SCKFREQ - SCK frequency is given as 32 MHz / (SCKFREQ + 1). - 28 - 31 + EVENTS_EP0SETUP + A valid SETUP token has been received (and acknowledged) on the control endpoint + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + - STATUS - Status register. - 0x604 - read-only + EVENTS_EPDATA + A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register + 0x160 + read-write + 0x00000000 + 0x20 - DPM - Deep power-down mode (DPM) status of external flash. + EVENTS_EPDATA + A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + EP0DATADONE_STARTEPIN0 + Shortcut between event EP0DATADONE and task STARTEPIN[0] + 0 + 0 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + EP0DATADONE_STARTEPOUT0 + Shortcut between event EP0DATADONE and task STARTEPOUT[0] + 1 + 1 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + EP0DATADONE_EP0STATUS + Shortcut between event EP0DATADONE and task EP0STATUS 2 2 Disabled - External flash is not in DPM. - 0 + Disable shortcut + 0x0 Enabled - External flash is in DPM. - 1 + Enable shortcut + 0x1 - READY - Ready status. + ENDEPOUT0_EP0STATUS + Shortcut between event ENDEPOUT[0] and task EP0STATUS 3 3 - READY - QSPI peripheral is ready. It is allowed to trigger new tasks, writing custom instructions or enter/exit DPM. - 1 + Disabled + Disable shortcut + 0x0 - BUSY - QSPI peripheral is busy. It is not allowed to trigger any new tasks, writing custom instructions or enter/exit DPM. - 0 + Enabled + Enable shortcut + 0x1 - SREG - Value of external flash device Status Register. When the external flash has two bytes status register this field includes the value of the low byte. - 24 - 31 + ENDEPOUT0_EP0RCVOUT + Shortcut between event ENDEPOUT[0] and task EP0RCVOUT + 4 + 4 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + - DPMDUR - Set the duration required to enter/exit deep power-down mode (DPM). - 0x614 + INTEN + Enable or disable interrupt + 0x300 read-write - 0xFFFFFFFF + 0x00000000 + 0x20 - ENTER - Duration needed by external flash to enter DPM. Duration is given as ENTER * 256 * 62.5 ns. + USBRESET + Enable or disable interrupt for event USBRESET 0 - 15 - - - EXIT - Duration needed by external flash to exit DPM. Duration is given as EXIT * 256 * 62.5 ns. - 16 - 31 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + - - - - ADDRCONF - Extended address configuration. - 0x624 - read-write - 0x000000B7 - - OPCODE - Opcode that enters the 32-bit addressing mode. - 0 - 7 + STARTED + Enable or disable interrupt for event STARTED + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + - BYTE0 - Byte 0 following opcode. - 8 - 15 + ENDEPIN0 + Enable or disable interrupt for event ENDEPIN[0] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + - BYTE1 - Byte 1 following byte 0. - 16 - 23 + ENDEPIN1 + Enable or disable interrupt for event ENDEPIN[1] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + - MODE - Extended addressing mode. - 24 - 25 + ENDEPIN2 + Enable or disable interrupt for event ENDEPIN[2] + 4 + 4 - NoInstr - Do not send any instruction. - 0 + Disabled + Disable + 0x0 - Opcode - Send opcode. - 1 + Enabled + Enable + 0x1 + + + + ENDEPIN3 + Enable or disable interrupt for event ENDEPIN[3] + 5 + 5 + - OpByte0 - Send opcode, byte0. - 2 + Disabled + Disable + 0x0 - All - Send opcode, byte0, byte1. - 3 + Enabled + Enable + 0x1 - WIPWAIT - Wait for write complete before sending command. - 26 - 26 + ENDEPIN4 + Enable or disable interrupt for event ENDEPIN[4] + 6 + 6 - Disable - No wait. - 0 + Disabled + Disable + 0x0 - Enable - Wait. - 1 + Enabled + Enable + 0x1 - WREN - Send WREN (write enable opcode 0x06) before instruction. - 27 - 27 + ENDEPIN5 + Enable or disable interrupt for event ENDEPIN[5] + 7 + 7 - Disable - Do not send WREN. - 0 + Disabled + Disable + 0x0 - Enable - Send WREN. - 1 + Enabled + Enable + 0x1 - - - - CINSTRCONF - Custom instruction configuration register. - 0x634 - read-write - 0x00002000 - - - OPCODE - Opcode of Custom instruction. - 0 - 7 - - LENGTH - Length of custom instruction in number of bytes. + ENDEPIN6 + Enable or disable interrupt for event ENDEPIN[6] 8 - 11 + 8 - 1B - Send opcode only. - 1 - - - 2B - Send opcode, CINSTRDAT0.BYTE0. - 2 + Disabled + Disable + 0x0 - 3B - Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT0.BYTE1. - 3 + Enabled + Enable + 0x1 + + + + ENDEPIN7 + Enable or disable interrupt for event ENDEPIN[7] + 9 + 9 + - 4B - Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT0.BYTE2. - 4 + Disabled + Disable + 0x0 - 5B - Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT0.BYTE3. - 5 + Enabled + Enable + 0x1 + + + + EP0DATADONE + Enable or disable interrupt for event EP0DATADONE + 10 + 10 + - 6B - Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE4. - 6 + Disabled + Disable + 0x0 - 7B - Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE5. - 7 + Enabled + Enable + 0x1 + + + + ENDISOIN + Enable or disable interrupt for event ENDISOIN + 11 + 11 + - 8B - Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE6. - 8 + Disabled + Disable + 0x0 - 9B - Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE7. - 9 + Enabled + Enable + 0x1 - LIO2 - Level of the IO2 pin (if connected) during transmission of custom instruction. + ENDEPOUT0 + Enable or disable interrupt for event ENDEPOUT[0] 12 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + - LIO3 - Level of the IO3 pin (if connected) during transmission of custom instruction. + ENDEPOUT1 + Enable or disable interrupt for event ENDEPOUT[1] 13 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + - WIPWAIT - Wait for write complete before sending command. + ENDEPOUT2 + Enable or disable interrupt for event ENDEPOUT[2] 14 14 - Disable - No wait. - 0 + Disabled + Disable + 0x0 - Enable - Wait. - 1 + Enabled + Enable + 0x1 - WREN - Send WREN (write enable opcode 0x06) before instruction. + ENDEPOUT3 + Enable or disable interrupt for event ENDEPOUT[3] 15 15 - Disable - Do not send WREN. - 0 + Disabled + Disable + 0x0 - Enable - Send WREN. - 1 + Enabled + Enable + 0x1 - LFEN - Enable long frame mode. When enabled, a custom instruction transaction has to be ended by writing the LFSTOP field. + ENDEPOUT4 + Enable or disable interrupt for event ENDEPOUT[4] 16 16 - Disable - Long frame mode disabled - 0 + Disabled + Disable + 0x0 - Enable - Long frame mode enabled - 1 + Enabled + Enable + 0x1 - LFSTOP - Stop (finalize) long frame transaction + ENDEPOUT5 + Enable or disable interrupt for event ENDEPOUT[5] 17 17 - Stop - Stop - 1 + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 - - - - CINSTRDAT0 - Custom instruction data register 0. - 0x638 - read-write - - - BYTE0 - Data byte 0 - 0 - 7 - - BYTE1 - Data byte 1 - 8 - 15 + ENDEPOUT6 + Enable or disable interrupt for event ENDEPOUT[6] + 18 + 18 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + - BYTE2 - Data byte 2 - 16 - 23 + ENDEPOUT7 + Enable or disable interrupt for event ENDEPOUT[7] + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + - BYTE3 - Data byte 3 - 24 - 31 + ENDISOOUT + Enable or disable interrupt for event ENDISOOUT + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + - - - - CINSTRDAT1 - Custom instruction data register 1. - 0x63C - read-write - - BYTE4 - Data byte 4 - 0 - 7 + SOF + Enable or disable interrupt for event SOF + 21 + 21 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + - BYTE5 - Data byte 5 - 8 - 15 + USBEVENT + Enable or disable interrupt for event USBEVENT + 22 + 22 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + - BYTE6 - Data byte 6 - 16 + EP0SETUP + Enable or disable interrupt for event EP0SETUP + 23 23 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + - BYTE7 - Data byte 7 + EPDATA + Enable or disable interrupt for event EPDATA 24 - 31 - - - - - IFTIMING - SPI interface timing. - 0x640 - read-write - 0x00000200 - - - RXDELAY - Timing related to sampling of the input serial data. The value of RXDELAY specifies the number of 64 MHz cycles (15.625 ns) delay from the the rising edge of the SPI Clock (SCK) until the input serial data is sampled. As en example, if set to 0 the input serial data is sampled on the rising edge of SCK. - 8 - 10 + 24 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + - - - - PWM3 - Pulse width modulation unit 3 - 0x4002D000 - - PWM3 - 45 - - - - SPIM3 - Serial Peripheral Interface Master with EasyDMA 3 - 0x4002F000 - - SPIM3 - 47 - - - - P0 - GPIO Port 1 - 0x50000000 - GPIO - - 0 - 0x1000 - registers - - GPIO - 0x20 - - OUT - Write GPIO port - 0x504 + INTENSET + Enable interrupt + 0x304 read-write + 0x00000000 + 0x20 - PIN0 - Pin 0 + USBRESET + Write '1' to enable interrupt for event USBRESET 0 0 + read - Low - Pin driver is low - 0 + Disabled + Read: Disabled + 0x0 - High - Pin driver is high - 1 + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 - PIN1 - Pin 1 + STARTED + Write '1' to enable interrupt for event STARTED 1 1 + read - Low - Pin driver is low - 0 + Disabled + Read: Disabled + 0x0 - High - Pin driver is high - 1 + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 - PIN2 - Pin 2 + ENDEPIN0 + Write '1' to enable interrupt for event ENDEPIN[0] 2 2 + read - Low - Pin driver is low - 0 + Disabled + Read: Disabled + 0x0 - High - Pin driver is high - 1 + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 - PIN3 - Pin 3 + ENDEPIN1 + Write '1' to enable interrupt for event ENDEPIN[1] 3 3 + read - Low - Pin driver is low - 0 + Disabled + Read: Disabled + 0x0 - High - Pin driver is high - 1 + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 - PIN4 - Pin 4 + ENDEPIN2 + Write '1' to enable interrupt for event ENDEPIN[2] 4 4 + read - Low - Pin driver is low - 0 + Disabled + Read: Disabled + 0x0 - High - Pin driver is high - 1 + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 - PIN5 - Pin 5 + ENDEPIN3 + Write '1' to enable interrupt for event ENDEPIN[3] 5 5 + read - Low - Pin driver is low - 0 + Disabled + Read: Disabled + 0x0 - High - Pin driver is high - 1 + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 - PIN6 - Pin 6 + ENDEPIN4 + Write '1' to enable interrupt for event ENDEPIN[4] 6 6 + read - Low - Pin driver is low - 0 + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + write - High - Pin driver is high - 1 + Set + Enable + 0x1 - PIN7 - Pin 7 + ENDEPIN5 + Write '1' to enable interrupt for event ENDEPIN[5] 7 7 + read - Low - Pin driver is low - 0 + Disabled + Read: Disabled + 0x0 - High - Pin driver is high - 1 + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 - PIN8 - Pin 8 + ENDEPIN6 + Write '1' to enable interrupt for event ENDEPIN[6] 8 8 + read - Low - Pin driver is low - 0 + Disabled + Read: Disabled + 0x0 - High - Pin driver is high - 1 + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 - PIN9 - Pin 9 + ENDEPIN7 + Write '1' to enable interrupt for event ENDEPIN[7] 9 9 + read - Low - Pin driver is low - 0 + Disabled + Read: Disabled + 0x0 - High - Pin driver is high - 1 + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 - PIN10 - Pin 10 + EP0DATADONE + Write '1' to enable interrupt for event EP0DATADONE 10 10 + read - Low - Pin driver is low - 0 + Disabled + Read: Disabled + 0x0 - High - Pin driver is high - 1 + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 - PIN11 - Pin 11 + ENDISOIN + Write '1' to enable interrupt for event ENDISOIN 11 11 + read - Low - Pin driver is low - 0 + Disabled + Read: Disabled + 0x0 - High - Pin driver is high - 1 + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 - PIN12 - Pin 12 + ENDEPOUT0 + Write '1' to enable interrupt for event ENDEPOUT[0] 12 12 + read - Low - Pin driver is low - 0 + Disabled + Read: Disabled + 0x0 - High - Pin driver is high - 1 + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 - PIN13 - Pin 13 + ENDEPOUT1 + Write '1' to enable interrupt for event ENDEPOUT[1] 13 13 + read - Low - Pin driver is low - 0 + Disabled + Read: Disabled + 0x0 - High - Pin driver is high - 1 + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 - PIN14 - Pin 14 + ENDEPOUT2 + Write '1' to enable interrupt for event ENDEPOUT[2] 14 14 + read - Low - Pin driver is low - 0 + Disabled + Read: Disabled + 0x0 - High - Pin driver is high - 1 + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 - PIN15 - Pin 15 + ENDEPOUT3 + Write '1' to enable interrupt for event ENDEPOUT[3] 15 15 + read - Low - Pin driver is low - 0 + Disabled + Read: Disabled + 0x0 - High - Pin driver is high - 1 + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 - PIN16 - Pin 16 + ENDEPOUT4 + Write '1' to enable interrupt for event ENDEPOUT[4] 16 16 + read - Low - Pin driver is low - 0 + Disabled + Read: Disabled + 0x0 - High - Pin driver is high - 1 + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 - PIN17 - Pin 17 + ENDEPOUT5 + Write '1' to enable interrupt for event ENDEPOUT[5] 17 17 + read - Low - Pin driver is low - 0 + Disabled + Read: Disabled + 0x0 - High - Pin driver is high - 1 + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 - PIN18 - Pin 18 + ENDEPOUT6 + Write '1' to enable interrupt for event ENDEPOUT[6] 18 18 + read - Low - Pin driver is low - 0 + Disabled + Read: Disabled + 0x0 - High - Pin driver is high - 1 + Enabled + Read: Enabled + 0x1 - - - PIN19 - Pin 19 - 19 - 19 + write - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 + Set + Enable + 0x1 - PIN20 - Pin 20 - 20 - 20 + ENDEPOUT7 + Write '1' to enable interrupt for event ENDEPOUT[7] + 19 + 19 + read - Low - Pin driver is low - 0 + Disabled + Read: Disabled + 0x0 - High - Pin driver is high - 1 + Enabled + Read: Enabled + 0x1 - - - PIN21 - Pin 21 - 21 - 21 + write - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 + Set + Enable + 0x1 - PIN22 - Pin 22 - 22 - 22 + ENDISOOUT + Write '1' to enable interrupt for event ENDISOOUT + 20 + 20 + read - Low - Pin driver is low - 0 + Disabled + Read: Disabled + 0x0 - High - Pin driver is high - 1 + Enabled + Read: Enabled + 0x1 - - - PIN23 - Pin 23 - 23 - 23 + write - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 + Set + Enable + 0x1 - PIN24 - Pin 24 - 24 - 24 + SOF + Write '1' to enable interrupt for event SOF + 21 + 21 + read - Low - Pin driver is low - 0 + Disabled + Read: Disabled + 0x0 - High - Pin driver is high - 1 + Enabled + Read: Enabled + 0x1 - - - PIN25 - Pin 25 - 25 - 25 + write - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 + Set + Enable + 0x1 - PIN26 - Pin 26 - 26 - 26 + USBEVENT + Write '1' to enable interrupt for event USBEVENT + 22 + 22 + read - Low - Pin driver is low - 0 + Disabled + Read: Disabled + 0x0 - High - Pin driver is high - 1 + Enabled + Read: Enabled + 0x1 - - - PIN27 - Pin 27 - 27 - 27 + write - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 + Set + Enable + 0x1 - PIN28 - Pin 28 - 28 - 28 + EP0SETUP + Write '1' to enable interrupt for event EP0SETUP + 23 + 23 + read - Low - Pin driver is low - 0 + Disabled + Read: Disabled + 0x0 - High - Pin driver is high - 1 + Enabled + Read: Enabled + 0x1 - - - PIN29 - Pin 29 - 29 - 29 + write - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 + Set + Enable + 0x1 - PIN30 - Pin 30 - 30 - 30 + EPDATA + Write '1' to enable interrupt for event EPDATA + 24 + 24 + read - Low - Pin driver is low - 0 + Disabled + Read: Disabled + 0x0 - High - Pin driver is high - 1 + Enabled + Read: Enabled + 0x1 - - - PIN31 - Pin 31 - 31 - 31 + write - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 + Set + Enable + 0x1 - OUTSET - Set individual bits in GPIO port - 0x508 + INTENCLR + Disable interrupt + 0x308 read-write - oneToSet + 0x00000000 + 0x20 - PIN0 - Pin 0 + USBRESET + Write '1' to disable interrupt for event USBRESET 0 0 read - Low - Read: pin driver is low - 0 + Disabled + Read: Disabled + 0x0 - High - Read: pin driver is high - 1 + Enabled + Read: Enabled + 0x1 write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + Clear + Disable + 0x1 - PIN1 - Pin 1 + STARTED + Write '1' to disable interrupt for event STARTED 1 1 read - Low - Read: pin driver is low - 0 + Disabled + Read: Disabled + 0x0 - High - Read: pin driver is high - 1 + Enabled + Read: Enabled + 0x1 write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + Clear + Disable + 0x1 - PIN2 - Pin 2 + ENDEPIN0 + Write '1' to disable interrupt for event ENDEPIN[0] 2 2 read - Low - Read: pin driver is low - 0 + Disabled + Read: Disabled + 0x0 - High - Read: pin driver is high - 1 + Enabled + Read: Enabled + 0x1 write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + Clear + Disable + 0x1 - PIN3 - Pin 3 + ENDEPIN1 + Write '1' to disable interrupt for event ENDEPIN[1] 3 3 read - Low - Read: pin driver is low - 0 + Disabled + Read: Disabled + 0x0 - High - Read: pin driver is high - 1 + Enabled + Read: Enabled + 0x1 write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + Clear + Disable + 0x1 - PIN4 - Pin 4 + ENDEPIN2 + Write '1' to disable interrupt for event ENDEPIN[2] 4 4 read - Low - Read: pin driver is low - 0 + Disabled + Read: Disabled + 0x0 - High - Read: pin driver is high - 1 + Enabled + Read: Enabled + 0x1 write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + Clear + Disable + 0x1 - PIN5 - Pin 5 + ENDEPIN3 + Write '1' to disable interrupt for event ENDEPIN[3] 5 5 read - Low - Read: pin driver is low - 0 + Disabled + Read: Disabled + 0x0 - High - Read: pin driver is high - 1 + Enabled + Read: Enabled + 0x1 write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + Clear + Disable + 0x1 - PIN6 - Pin 6 + ENDEPIN4 + Write '1' to disable interrupt for event ENDEPIN[4] 6 6 read - Low - Read: pin driver is low - 0 + Disabled + Read: Disabled + 0x0 - High - Read: pin driver is high - 1 + Enabled + Read: Enabled + 0x1 write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + Clear + Disable + 0x1 - PIN7 - Pin 7 + ENDEPIN5 + Write '1' to disable interrupt for event ENDEPIN[5] 7 7 read - Low - Read: pin driver is low - 0 + Disabled + Read: Disabled + 0x0 - High - Read: pin driver is high - 1 + Enabled + Read: Enabled + 0x1 write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + Clear + Disable + 0x1 - PIN8 - Pin 8 + ENDEPIN6 + Write '1' to disable interrupt for event ENDEPIN[6] 8 8 read - Low - Read: pin driver is low - 0 + Disabled + Read: Disabled + 0x0 - High - Read: pin driver is high - 1 + Enabled + Read: Enabled + 0x1 write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + Clear + Disable + 0x1 - PIN9 - Pin 9 + ENDEPIN7 + Write '1' to disable interrupt for event ENDEPIN[7] 9 9 read - Low - Read: pin driver is low - 0 + Disabled + Read: Disabled + 0x0 - High - Read: pin driver is high - 1 + Enabled + Read: Enabled + 0x1 write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + Clear + Disable + 0x1 - PIN10 - Pin 10 + EP0DATADONE + Write '1' to disable interrupt for event EP0DATADONE 10 10 read - Low - Read: pin driver is low - 0 + Disabled + Read: Disabled + 0x0 - High - Read: pin driver is high - 1 + Enabled + Read: Enabled + 0x1 write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + Clear + Disable + 0x1 - PIN11 - Pin 11 + ENDISOIN + Write '1' to disable interrupt for event ENDISOIN 11 11 read - Low - Read: pin driver is low - 0 + Disabled + Read: Disabled + 0x0 - High - Read: pin driver is high - 1 + Enabled + Read: Enabled + 0x1 write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + Clear + Disable + 0x1 - PIN12 - Pin 12 + ENDEPOUT0 + Write '1' to disable interrupt for event ENDEPOUT[0] 12 12 read - Low - Read: pin driver is low - 0 + Disabled + Read: Disabled + 0x0 - High - Read: pin driver is high - 1 + Enabled + Read: Enabled + 0x1 write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + Clear + Disable + 0x1 - PIN13 - Pin 13 + ENDEPOUT1 + Write '1' to disable interrupt for event ENDEPOUT[1] 13 13 read - Low - Read: pin driver is low - 0 + Disabled + Read: Disabled + 0x0 - High - Read: pin driver is high - 1 + Enabled + Read: Enabled + 0x1 write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + Clear + Disable + 0x1 - PIN14 - Pin 14 + ENDEPOUT2 + Write '1' to disable interrupt for event ENDEPOUT[2] 14 14 read - Low - Read: pin driver is low - 0 + Disabled + Read: Disabled + 0x0 - High - Read: pin driver is high - 1 + Enabled + Read: Enabled + 0x1 write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + Clear + Disable + 0x1 - PIN15 - Pin 15 + ENDEPOUT3 + Write '1' to disable interrupt for event ENDEPOUT[3] 15 15 read - Low - Read: pin driver is low - 0 + Disabled + Read: Disabled + 0x0 - High - Read: pin driver is high - 1 + Enabled + Read: Enabled + 0x1 write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + Clear + Disable + 0x1 - PIN16 - Pin 16 + ENDEPOUT4 + Write '1' to disable interrupt for event ENDEPOUT[4] 16 16 read - Low - Read: pin driver is low - 0 + Disabled + Read: Disabled + 0x0 - High - Read: pin driver is high - 1 + Enabled + Read: Enabled + 0x1 write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + Clear + Disable + 0x1 - PIN17 - Pin 17 + ENDEPOUT5 + Write '1' to disable interrupt for event ENDEPOUT[5] 17 17 read - Low - Read: pin driver is low - 0 + Disabled + Read: Disabled + 0x0 - High - Read: pin driver is high - 1 + Enabled + Read: Enabled + 0x1 write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + Clear + Disable + 0x1 - PIN18 - Pin 18 + ENDEPOUT6 + Write '1' to disable interrupt for event ENDEPOUT[6] 18 18 read - Low - Read: pin driver is low - 0 + Disabled + Read: Disabled + 0x0 - High - Read: pin driver is high - 1 + Enabled + Read: Enabled + 0x1 write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + Clear + Disable + 0x1 - PIN19 - Pin 19 + ENDEPOUT7 + Write '1' to disable interrupt for event ENDEPOUT[7] 19 19 read - Low - Read: pin driver is low - 0 + Disabled + Read: Disabled + 0x0 - High - Read: pin driver is high - 1 + Enabled + Read: Enabled + 0x1 write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + Clear + Disable + 0x1 - PIN20 - Pin 20 + ENDISOOUT + Write '1' to disable interrupt for event ENDISOOUT 20 20 read - Low - Read: pin driver is low - 0 + Disabled + Read: Disabled + 0x0 - High - Read: pin driver is high - 1 + Enabled + Read: Enabled + 0x1 write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + Clear + Disable + 0x1 - PIN21 - Pin 21 + SOF + Write '1' to disable interrupt for event SOF 21 21 read - Low - Read: pin driver is low - 0 + Disabled + Read: Disabled + 0x0 - High - Read: pin driver is high - 1 + Enabled + Read: Enabled + 0x1 write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + Clear + Disable + 0x1 - PIN22 - Pin 22 + USBEVENT + Write '1' to disable interrupt for event USBEVENT 22 22 read - Low - Read: pin driver is low - 0 + Disabled + Read: Disabled + 0x0 - High - Read: pin driver is high - 1 + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + EP0SETUP + Write '1' to disable interrupt for event EP0SETUP + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + EPDATA + Write '1' to disable interrupt for event EPDATA + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + Clear + Disable + 0x1 + + + + + + + EVENTCAUSE + Details on what caused the USBEVENT event + 0x400 + read-write + 0x00000000 + oneToClear + 0x20 + + + ISOOUTCRC + CRC error was detected on isochronous OUT endpoint 8. Write '1' to clear. + 0 + 0 + + + NotDetected + No error detected + 0x0 + + + Detected + Error detected + 0x1 + + + + + SUSPEND + Signals that USB lines have been idle long enough for the device to enter suspend. Write '1' to clear. + 8 + 8 + + + NotDetected + Suspend not detected + 0x0 + + + Detected + Suspend detected + 0x1 + + + + + RESUME + Signals that a RESUME condition (K state or activity restart) has been detected on USB lines. Write '1' to clear. + 9 + 9 + + + NotDetected + Resume not detected + 0x0 + + + Detected + Resume detected + 0x1 + + + + + USBWUALLOWED + USB MAC has been woken up and operational. Write '1' to clear. + 10 + 10 + + + NotAllowed + Wake up not allowed + 0x0 + + + Allowed + Wake up allowed + 0x1 + + + + + READY + USB device is ready for normal operation. Write '1' to clear. + 11 + 11 + + + NotDetected + USBEVENT was not issued due to USBD peripheral ready + 0x0 + + + Ready + USBD peripheral is ready + 0x1 + + + + + + + HALTED + Unspecified + USBD_HALTED + read-write + 0x420 + + 0x8 + 0x4 + EPIN[%s] + Description collection: IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. + 0x000 + read-only + 0x00000000 + 0x20 + + + GETSTATUS + IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. + 0 + 15 + + + NotHalted + Endpoint is not halted + 0x0000 + + + Halted + Endpoint is halted + 0x0001 + + + + + + + 0x8 + 0x4 + EPOUT[%s] + Description collection: OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. + 0x024 + read-only + 0x00000000 + 0x20 + + + GETSTATUS + OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. + 0 + 15 + + + NotHalted + Endpoint is not halted + 0x0000 + + + Halted + Endpoint is halted + 0x0001 + + + + + + + + EPSTATUS + Provides information on which endpoint's EasyDMA registers have been captured + 0x468 + read-write + 0x00000000 + oneToClear + 0x20 + + + EPIN0 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 0 + 0 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0x0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 0x1 - PIN23 - Pin 23 - 23 - 23 + EPIN1 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 1 + 1 - read - - Low - Read: pin driver is low - 0 - - High - Read: pin driver is high - 1 + NoData + EasyDMA registers have not been captured for this endpoint + 0x0 - - - write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + DataDone + EasyDMA registers have been captured for this endpoint + 0x1 - PIN24 - Pin 24 - 24 - 24 + EPIN2 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 2 + 2 - read - Low - Read: pin driver is low - 0 + NoData + EasyDMA registers have not been captured for this endpoint + 0x0 - High - Read: pin driver is high - 1 + DataDone + EasyDMA registers have been captured for this endpoint + 0x1 + + + EPIN3 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 3 + 3 - write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + NoData + EasyDMA registers have not been captured for this endpoint + 0x0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 0x1 - PIN25 - Pin 25 - 25 - 25 + EPIN4 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 4 + 4 - read - Low - Read: pin driver is low - 0 + NoData + EasyDMA registers have not been captured for this endpoint + 0x0 - High - Read: pin driver is high - 1 + DataDone + EasyDMA registers have been captured for this endpoint + 0x1 + + + EPIN5 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 5 + 5 - write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + NoData + EasyDMA registers have not been captured for this endpoint + 0x0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 0x1 - PIN26 - Pin 26 - 26 - 26 + EPIN6 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 6 + 6 - read - Low - Read: pin driver is low - 0 + NoData + EasyDMA registers have not been captured for this endpoint + 0x0 - High - Read: pin driver is high - 1 + DataDone + EasyDMA registers have been captured for this endpoint + 0x1 + + + EPIN7 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 7 + 7 - write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + NoData + EasyDMA registers have not been captured for this endpoint + 0x0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 0x1 - PIN27 - Pin 27 - 27 - 27 + EPIN8 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 8 + 8 - read - Low - Read: pin driver is low - 0 + NoData + EasyDMA registers have not been captured for this endpoint + 0x0 - High - Read: pin driver is high - 1 + DataDone + EasyDMA registers have been captured for this endpoint + 0x1 + + + EPOUT0 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 16 + 16 - write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + NoData + EasyDMA registers have not been captured for this endpoint + 0x0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 0x1 - PIN28 - Pin 28 - 28 - 28 + EPOUT1 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 17 + 17 - read - Low - Read: pin driver is low - 0 + NoData + EasyDMA registers have not been captured for this endpoint + 0x0 - High - Read: pin driver is high - 1 + DataDone + EasyDMA registers have been captured for this endpoint + 0x1 + + + EPOUT2 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 18 + 18 - write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + NoData + EasyDMA registers have not been captured for this endpoint + 0x0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 0x1 - PIN29 - Pin 29 - 29 - 29 + EPOUT3 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 19 + 19 - read - Low - Read: pin driver is low - 0 + NoData + EasyDMA registers have not been captured for this endpoint + 0x0 - High - Read: pin driver is high - 1 + DataDone + EasyDMA registers have been captured for this endpoint + 0x1 + + + EPOUT4 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 20 + 20 - write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + NoData + EasyDMA registers have not been captured for this endpoint + 0x0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 0x1 - PIN30 - Pin 30 - 30 - 30 + EPOUT5 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 21 + 21 - read - Low - Read: pin driver is low - 0 + NoData + EasyDMA registers have not been captured for this endpoint + 0x0 - High - Read: pin driver is high - 1 + DataDone + EasyDMA registers have been captured for this endpoint + 0x1 + + + EPOUT6 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 22 + 22 - write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + NoData + EasyDMA registers have not been captured for this endpoint + 0x0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 0x1 - PIN31 - Pin 31 - 31 - 31 + EPOUT7 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 23 + 23 - read - Low - Read: pin driver is low - 0 + NoData + EasyDMA registers have not been captured for this endpoint + 0x0 - High - Read: pin driver is high - 1 + DataDone + EasyDMA registers have been captured for this endpoint + 0x1 + + + EPOUT8 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 24 + 24 - write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + NoData + EasyDMA registers have not been captured for this endpoint + 0x0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 0x1 - OUTCLR - Clear individual bits in GPIO port - 0x50C + EPDATASTATUS + Provides information on which endpoint(s) an acknowledged data transfer has occurred (EPDATA event) + 0x46C read-write + 0x00000000 oneToClear + 0x20 - PIN0 - Pin 0 - 0 - 0 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN1 - Pin 1 + EPIN1 + Acknowledged data transfer on this IN endpoint. Write '1' to clear. 1 1 - read - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 + NotDone + No acknowledged data transfer on this endpoint + 0x0 - - - write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + DataDone + Acknowledged data transfer on this endpoint has occurred + 0x1 - PIN2 - Pin 2 + EPIN2 + Acknowledged data transfer on this IN endpoint. Write '1' to clear. 2 2 - read - - Low - Read: pin driver is low - 0 - - High - Read: pin driver is high - 1 + NotDone + No acknowledged data transfer on this endpoint + 0x0 - - - write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + DataDone + Acknowledged data transfer on this endpoint has occurred + 0x1 - PIN3 - Pin 3 + EPIN3 + Acknowledged data transfer on this IN endpoint. Write '1' to clear. 3 3 - read - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 + NotDone + No acknowledged data transfer on this endpoint + 0x0 - - - write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + DataDone + Acknowledged data transfer on this endpoint has occurred + 0x1 - PIN4 - Pin 4 + EPIN4 + Acknowledged data transfer on this IN endpoint. Write '1' to clear. 4 4 - read - - Low - Read: pin driver is low - 0 - - High - Read: pin driver is high - 1 + NotDone + No acknowledged data transfer on this endpoint + 0x0 - - - write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + DataDone + Acknowledged data transfer on this endpoint has occurred + 0x1 - PIN5 - Pin 5 + EPIN5 + Acknowledged data transfer on this IN endpoint. Write '1' to clear. 5 5 - read - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 + NotDone + No acknowledged data transfer on this endpoint + 0x0 - - - write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + DataDone + Acknowledged data transfer on this endpoint has occurred + 0x1 - PIN6 - Pin 6 + EPIN6 + Acknowledged data transfer on this IN endpoint. Write '1' to clear. 6 6 - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN7 - Pin 7 - 7 - 7 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN8 - Pin 8 - 8 - 8 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN9 - Pin 9 - 9 - 9 - - read - - Low - Read: pin driver is low - 0 - - High - Read: pin driver is high - 1 + NotDone + No acknowledged data transfer on this endpoint + 0x0 - - - write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + DataDone + Acknowledged data transfer on this endpoint has occurred + 0x1 - PIN10 - Pin 10 - 10 - 10 + EPIN7 + Acknowledged data transfer on this IN endpoint. Write '1' to clear. + 7 + 7 - read - Low - Read: pin driver is low - 0 + NotDone + No acknowledged data transfer on this endpoint + 0x0 - High - Read: pin driver is high - 1 + DataDone + Acknowledged data transfer on this endpoint has occurred + 0x1 + + + EPOUT1 + Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + 17 + 17 - write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + NotStarted + No acknowledged data transfer on this endpoint + 0x0 + + + Started + Acknowledged data transfer on this endpoint has occurred + 0x1 - PIN11 - Pin 11 - 11 - 11 + EPOUT2 + Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + 18 + 18 - read - Low - Read: pin driver is low - 0 + NotStarted + No acknowledged data transfer on this endpoint + 0x0 - High - Read: pin driver is high - 1 + Started + Acknowledged data transfer on this endpoint has occurred + 0x1 + + + EPOUT3 + Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + 19 + 19 - write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + NotStarted + No acknowledged data transfer on this endpoint + 0x0 + + + Started + Acknowledged data transfer on this endpoint has occurred + 0x1 - PIN12 - Pin 12 - 12 - 12 + EPOUT4 + Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + 20 + 20 - read - Low - Read: pin driver is low - 0 + NotStarted + No acknowledged data transfer on this endpoint + 0x0 - High - Read: pin driver is high - 1 + Started + Acknowledged data transfer on this endpoint has occurred + 0x1 + + + EPOUT5 + Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + 21 + 21 - write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + NotStarted + No acknowledged data transfer on this endpoint + 0x0 + + + Started + Acknowledged data transfer on this endpoint has occurred + 0x1 - PIN13 - Pin 13 - 13 - 13 + EPOUT6 + Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + 22 + 22 - read - Low - Read: pin driver is low - 0 + NotStarted + No acknowledged data transfer on this endpoint + 0x0 - High - Read: pin driver is high - 1 + Started + Acknowledged data transfer on this endpoint has occurred + 0x1 + + + EPOUT7 + Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + 23 + 23 - write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + NotStarted + No acknowledged data transfer on this endpoint + 0x0 + + + Started + Acknowledged data transfer on this endpoint has occurred + 0x1 + + + + USBADDR + Device USB address + 0x470 + read-only + 0x00000000 + 0x20 + - PIN14 - Pin 14 - 14 - 14 + ADDR + Device USB address + 0 + 6 + + + + + BMREQUESTTYPE + SETUP data, byte 0, bmRequestType + 0x480 + read-only + 0x00000000 + 0x20 + + + RECIPIENT + Data transfer type + 0 + 4 - read - Low - Read: pin driver is low - 0 + Device + Device + 0x00 - High - Read: pin driver is high - 1 + Interface + Interface + 0x01 - - - write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + Endpoint + Endpoint + 0x02 + + + Other + Other + 0x03 - PIN15 - Pin 15 - 15 - 15 + TYPE + Data transfer type + 5 + 6 - read - Low - Read: pin driver is low - 0 + Standard + Standard + 0x0 - High - Read: pin driver is high - 1 + Class + Class + 0x1 - - - write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + Vendor + Vendor + 0x2 - PIN16 - Pin 16 - 16 - 16 + DIRECTION + Data transfer direction + 7 + 7 - read - - Low - Read: pin driver is low - 0 - - High - Read: pin driver is high - 1 + HostToDevice + Host-to-device + 0x0 - - - write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + DeviceToHost + Device-to-host + 0x1 + + + + BREQUEST + SETUP data, byte 1, bRequest + 0x484 + read-only + 0x00000000 + 0x20 + - PIN17 - Pin 17 - 17 - 17 + BREQUEST + SETUP data, byte 1, bRequest. Values provided for standard requests only, user must implement class and vendor values. + 0 + 7 - read - Low - Read: pin driver is low - 0 + STD_GET_STATUS + Standard request GET_STATUS + 0x00 - High - Read: pin driver is high - 1 + STD_CLEAR_FEATURE + Standard request CLEAR_FEATURE + 0x01 - - - write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + STD_SET_FEATURE + Standard request SET_FEATURE + 0x03 - - - - PIN18 - Pin 18 - 18 - 18 - - read - Low - Read: pin driver is low - 0 + STD_SET_ADDRESS + Standard request SET_ADDRESS + 0x05 - High - Read: pin driver is high - 1 + STD_GET_DESCRIPTOR + Standard request GET_DESCRIPTOR + 0x06 - - - write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + STD_SET_DESCRIPTOR + Standard request SET_DESCRIPTOR + 0x07 - - - - PIN19 - Pin 19 - 19 - 19 - - read - Low - Read: pin driver is low - 0 + STD_GET_CONFIGURATION + Standard request GET_CONFIGURATION + 0x08 - High - Read: pin driver is high - 1 + STD_SET_CONFIGURATION + Standard request SET_CONFIGURATION + 0x09 - - - write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + STD_GET_INTERFACE + Standard request GET_INTERFACE + 0x0A - - - - PIN20 - Pin 20 - 20 - 20 - - read - Low - Read: pin driver is low - 0 + STD_SET_INTERFACE + Standard request SET_INTERFACE + 0x0B - High - Read: pin driver is high - 1 + STD_SYNCH_FRAME + Standard request SYNCH_FRAME + 0x0C + + + + + WVALUEL + SETUP data, byte 2, LSB of wValue + 0x488 + read-only + 0x00000000 + 0x20 + + + WVALUEL + SETUP data, byte 2, LSB of wValue + 0 + 7 + + + + + WVALUEH + SETUP data, byte 3, MSB of wValue + 0x48C + read-only + 0x00000000 + 0x20 + + + WVALUEH + SETUP data, byte 3, MSB of wValue + 0 + 7 + + + + + WINDEXL + SETUP data, byte 4, LSB of wIndex + 0x490 + read-only + 0x00000000 + 0x20 + + + WINDEXL + SETUP data, byte 4, LSB of wIndex + 0 + 7 + + + + + WINDEXH + SETUP data, byte 5, MSB of wIndex + 0x494 + read-only + 0x00000000 + 0x20 + + + WINDEXH + SETUP data, byte 5, MSB of wIndex + 0 + 7 + + + + + WLENGTHL + SETUP data, byte 6, LSB of wLength + 0x498 + read-only + 0x00000000 + 0x20 + + + WLENGTHL + SETUP data, byte 6, LSB of wLength + 0 + 7 + + + + + WLENGTHH + SETUP data, byte 7, MSB of wLength + 0x49C + read-only + 0x00000000 + 0x20 + + + WLENGTHH + SETUP data, byte 7, MSB of wLength + 0 + 7 + + + + + SIZE + Unspecified + USBD_SIZE + read-write + 0x4A0 + + 0x8 + 0x4 + EPOUT[%s] + Description collection: Number of bytes received last in the data stage of this OUT endpoint + 0x000 + read-write + 0x00000000 + zeroToClear + 0x20 + + + SIZE + Number of bytes received last in the data stage of this OUT endpoint + 0 + 6 + + + + + ISOOUT + Number of bytes received last on this ISO OUT data endpoint + 0x020 + read-only + 0x00010000 + 0x20 + + + SIZE + Number of bytes received last on this ISO OUT data endpoint + 0 + 9 + + + ZERO + Zero-length data packet received + 16 + 16 + + + Normal + No zero-length data received, use value in SIZE + 0x0 + + + ZeroData + Zero-length data received, ignore value in SIZE + 0x1 + + + + + + + + ENABLE + Enable USB + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable USB + 0 + 0 - write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + Disabled + USB peripheral is disabled + 0x0 + + + Enabled + USB peripheral is enabled + 0x1 + + + + USBPULLUP + Control of the USB pull-up + 0x504 + read-write + 0x00000000 + 0x20 + - PIN21 - Pin 21 - 21 - 21 + CONNECT + Control of the USB pull-up on the D+ line + 0 + 0 - read - - Low - Read: pin driver is low - 0 - - High - Read: pin driver is high - 1 + Disabled + Pull-up is disconnected + 0x0 - - - write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + Enabled + Pull-up is connected to D+ + 0x1 + + + + DPDMVALUE + State D+ and D- lines will be forced into by the DPDMDRIVE task. The DPDMNODRIVE task reverts the control of the lines to MAC IP (no forcing). + 0x508 + read-write + 0x00000000 + 0x20 + - PIN22 - Pin 22 - 22 - 22 + STATE + State D+ and D- lines will be forced into by the DPDMDRIVE task + 0 + 4 - read - Low - Read: pin driver is low - 0 + Resume + D+ forced low, D- forced high (K state) for a timing preset in hardware (50 us or 5 ms, depending on bus state) + 0x01 - High - Read: pin driver is high - 1 + J + D+ forced high, D- forced low (J state) + 0x02 - - - write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + K + D+ forced low, D- forced high (K state) + 0x04 + + + + DTOGGLE + Data toggle control and status + 0x50C + read-write + 0x00000100 + 0x20 + - PIN23 - Pin 23 - 23 - 23 + EP + Select bulk endpoint number + 0 + 2 + + + IO + Selects IN or OUT endpoint + 7 + 7 - read - - Low - Read: pin driver is low - 0 - - High - Read: pin driver is high - 1 + Out + Selects OUT endpoint + 0x0 - - - write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + In + Selects IN endpoint + 0x1 - PIN24 - Pin 24 - 24 - 24 + VALUE + Data toggle value + 8 + 9 - read - Low - Read: pin driver is low - 0 + Nop + No action on data toggle when writing the register with this value + 0x0 - High - Read: pin driver is high - 1 + Data0 + Data toggle is DATA0 on endpoint set by EP and IO + 0x1 - - - write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + Data1 + Data toggle is DATA1 on endpoint set by EP and IO + 0x2 + + + + EPINEN + Endpoint IN enable + 0x510 + read-write + 0x00000001 + 0x20 + - PIN25 - Pin 25 - 25 - 25 + IN0 + Enable IN endpoint 0 + 0 + 0 - read - - Low - Read: pin driver is low - 0 - - High - Read: pin driver is high - 1 + Disable + Disable endpoint IN 0 (no response to IN tokens) + 0x0 - - - write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + Enable + Enable endpoint IN 0 (response to IN tokens) + 0x1 - PIN26 - Pin 26 - 26 - 26 + IN1 + Enable IN endpoint 1 + 1 + 1 - read - - Low - Read: pin driver is low - 0 - - High - Read: pin driver is high - 1 + Disable + Disable endpoint IN 1 (no response to IN tokens) + 0x0 - - - write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + Enable + Enable endpoint IN 1 (response to IN tokens) + 0x1 - PIN27 - Pin 27 - 27 - 27 + IN2 + Enable IN endpoint 2 + 2 + 2 - read - - Low - Read: pin driver is low - 0 - - High - Read: pin driver is high - 1 + Disable + Disable endpoint IN 2 (no response to IN tokens) + 0x0 - - - write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + Enable + Enable endpoint IN 2 (response to IN tokens) + 0x1 - PIN28 - Pin 28 - 28 - 28 + IN3 + Enable IN endpoint 3 + 3 + 3 - read - - Low - Read: pin driver is low - 0 - - High - Read: pin driver is high - 1 + Disable + Disable endpoint IN 3 (no response to IN tokens) + 0x0 - - - write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + Enable + Enable endpoint IN 3 (response to IN tokens) + 0x1 - PIN29 - Pin 29 - 29 - 29 + IN4 + Enable IN endpoint 4 + 4 + 4 - read - - Low - Read: pin driver is low - 0 - - High - Read: pin driver is high - 1 + Disable + Disable endpoint IN 4 (no response to IN tokens) + 0x0 - - - write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + Enable + Enable endpoint IN 4 (response to IN tokens) + 0x1 - PIN30 - Pin 30 - 30 - 30 + IN5 + Enable IN endpoint 5 + 5 + 5 - read - Low - Read: pin driver is low - 0 + Disable + Disable endpoint IN 5 (no response to IN tokens) + 0x0 - High - Read: pin driver is high - 1 + Enable + Enable endpoint IN 5 (response to IN tokens) + 0x1 + + + IN6 + Enable IN endpoint 6 + 6 + 6 - write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + Disable + Disable endpoint IN 6 (no response to IN tokens) + 0x0 + + + Enable + Enable endpoint IN 6 (response to IN tokens) + 0x1 - PIN31 - Pin 31 - 31 - 31 + IN7 + Enable IN endpoint 7 + 7 + 7 - read - Low - Read: pin driver is low - 0 + Disable + Disable endpoint IN 7 (no response to IN tokens) + 0x0 - High - Read: pin driver is high - 1 + Enable + Enable endpoint IN 7 (response to IN tokens) + 0x1 + + + ISOIN + Enable ISO IN endpoint + 8 + 8 - write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + Disable + Disable ISO IN endpoint 8 + 0x0 + + + Enable + Enable ISO IN endpoint 8 + 0x1 - IN - Read GPIO port - 0x510 - read-only + EPOUTEN + Endpoint OUT enable + 0x514 + read-write + 0x00000001 + 0x20 - PIN0 - Pin 0 + OUT0 + Enable OUT endpoint 0 0 0 - Low - Pin input is low - 0 + Disable + Disable endpoint OUT 0 (no response to OUT tokens) + 0x0 - High - Pin input is high - 1 + Enable + Enable endpoint OUT 0 (response to OUT tokens) + 0x1 - PIN1 - Pin 1 + OUT1 + Enable OUT endpoint 1 1 1 - Low - Pin input is low - 0 + Disable + Disable endpoint OUT 1 (no response to OUT tokens) + 0x0 - High - Pin input is high - 1 + Enable + Enable endpoint OUT 1 (response to OUT tokens) + 0x1 - PIN2 - Pin 2 + OUT2 + Enable OUT endpoint 2 2 2 - Low - Pin input is low - 0 + Disable + Disable endpoint OUT 2 (no response to OUT tokens) + 0x0 - High - Pin input is high - 1 + Enable + Enable endpoint OUT 2 (response to OUT tokens) + 0x1 - PIN3 - Pin 3 + OUT3 + Enable OUT endpoint 3 3 3 - Low - Pin input is low - 0 + Disable + Disable endpoint OUT 3 (no response to OUT tokens) + 0x0 - High - Pin input is high - 1 + Enable + Enable endpoint OUT 3 (response to OUT tokens) + 0x1 - PIN4 - Pin 4 + OUT4 + Enable OUT endpoint 4 4 4 - Low - Pin input is low - 0 + Disable + Disable endpoint OUT 4 (no response to OUT tokens) + 0x0 - High - Pin input is high - 1 + Enable + Enable endpoint OUT 4 (response to OUT tokens) + 0x1 - PIN5 - Pin 5 + OUT5 + Enable OUT endpoint 5 5 5 - Low - Pin input is low - 0 + Disable + Disable endpoint OUT 5 (no response to OUT tokens) + 0x0 - High - Pin input is high - 1 + Enable + Enable endpoint OUT 5 (response to OUT tokens) + 0x1 - PIN6 - Pin 6 + OUT6 + Enable OUT endpoint 6 6 6 - Low - Pin input is low - 0 + Disable + Disable endpoint OUT 6 (no response to OUT tokens) + 0x0 - High - Pin input is high - 1 + Enable + Enable endpoint OUT 6 (response to OUT tokens) + 0x1 - PIN7 - Pin 7 + OUT7 + Enable OUT endpoint 7 7 7 - Low - Pin input is low - 0 + Disable + Disable endpoint OUT 7 (no response to OUT tokens) + 0x0 - High - Pin input is high - 1 + Enable + Enable endpoint OUT 7 (response to OUT tokens) + 0x1 - PIN8 - Pin 8 + ISOOUT + Enable ISO OUT endpoint 8 8 8 - Low - Pin input is low - 0 + Disable + Disable ISO OUT endpoint 8 + 0x0 - High - Pin input is high - 1 + Enable + Enable ISO OUT endpoint 8 + 0x1 + + + + EPSTALL + STALL endpoints + 0x518 + write-only + 0x00000000 + modifyExternal + 0x20 + - PIN9 - Pin 9 - 9 - 9 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - + EP + Select endpoint number + 0 + 2 - PIN10 - Pin 10 - 10 - 10 + IO + Selects IN or OUT endpoint + 7 + 7 - Low - Pin input is low - 0 + Out + Selects OUT endpoint + 0x0 - High - Pin input is high - 1 + In + Selects IN endpoint + 0x1 - PIN11 - Pin 11 - 11 - 11 + STALL + Stall selected endpoint + 8 + 8 - Low - Pin input is low - 0 + UnStall + Don't stall selected endpoint + 0x0 - High - Pin input is high - 1 + Stall + Stall selected endpoint + 0x1 + + + + ISOSPLIT + Controls the split of ISO buffers + 0x51C + read-write + 0x00000000 + 0x20 + - PIN12 - Pin 12 - 12 - 12 + SPLIT + Controls the split of ISO buffers + 0 + 15 - Low - Pin input is low - 0 + OneDir + Full buffer dedicated to either ISO IN or OUT + 0x0000 - High - Pin input is high - 1 + HalfIN + Lower half for IN, upper half for OUT + 0x0080 + + + + FRAMECNTR + Returns the current value of the start of frame counter + 0x520 + read-only + 0x00000000 + 0x20 + - PIN13 - Pin 13 - 13 - 13 + FRAMECNTR + Returns the current value of the start of frame counter + 0 + 10 + + + + + LOWPOWER + Controls USBD peripheral low power mode during USB suspend + 0x52C + read-write + 0x00000000 + 0x20 + + + LOWPOWER + Controls USBD peripheral low-power mode during USB suspend + 0 + 0 - Low - Pin input is low - 0 + ForceNormal + Software must write this value to exit low power mode and before performing a remote wake-up + 0x0 - High - Pin input is high - 1 + LowPower + Software must write this value to enter low power mode after DMA and software have finished interacting with the USB peripheral + 0x1 + + + + ISOINCONFIG + Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent + 0x530 + read-write + 0x00000000 + 0x20 + - PIN14 - Pin 14 - 14 - 14 + RESPONSE + Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent + 0 + 0 - Low - Pin input is low - 0 + NoResp + Endpoint does not respond in that case + 0x0 - High - Pin input is high - 1 + ZeroData + Endpoint responds with a zero-length data packet in that case + 0x1 + + + + 8 + 0x014 + EPIN[%s] + Unspecified + USBD_EPIN + read-write + 0x600 + + PTR + Description cluster: Data pointer + 0x000 + read-write + 0x00000000 + 0x20 + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Description cluster: Maximum number of bytes to transfer + 0x004 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes to transfer + 0 + 6 + + + + + AMOUNT + Description cluster: Number of bytes transferred in the last transaction + 0x008 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 6 + + + + + + ISOIN + Unspecified + USBD_ISOIN + read-write + 0x6A0 + + PTR + Data pointer + 0x000 + read-write + 0x00000000 + 0x20 + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes to transfer + 0x004 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes to transfer + 0 + 9 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 9 + + + + + + 8 + 0x014 + EPOUT[%s] + Unspecified + USBD_EPOUT + read-write + 0x700 + + PTR + Description cluster: Data pointer + 0x000 + read-write + 0x00000000 + 0x20 + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Description cluster: Maximum number of bytes to transfer + 0x004 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes to transfer + 0 + 6 + + + + + AMOUNT + Description cluster: Number of bytes transferred in the last transaction + 0x008 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 6 + + + + + + ISOOUT + Unspecified + USBD_ISOOUT + read-write + 0x7A0 + + PTR + Data pointer + 0x000 + read-write + 0x00000000 + 0x20 + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes to transfer + 0x004 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes to transfer + 0 + 9 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 9 + + + + + + + + UARTE1 + UART with EasyDMA 1 + 0x40028000 + + UARTE1 + 40 + + + + QSPI + External flash interface + 0x40029000 + + 0 + 0x1000 + registers + + + QSPI + 41 + + QSPI + 0x20 + + + TASKS_ACTIVATE + Activate QSPI interface + 0x000 + write-only + 0x00000000 + 0x20 + - PIN15 - Pin 15 - 15 - 15 + TASKS_ACTIVATE + Activate QSPI interface + 0 + 0 - Low - Pin input is low - 0 - - - High - Pin input is high - 1 + Trigger + Trigger task + 0x1 + + + + TASKS_READSTART + Start transfer from external flash memory to internal RAM + 0x004 + write-only + 0x00000000 + 0x20 + - PIN16 - Pin 16 - 16 - 16 + TASKS_READSTART + Start transfer from external flash memory to internal RAM + 0 + 0 - Low - Pin input is low - 0 - - - High - Pin input is high - 1 + Trigger + Trigger task + 0x1 + + + + TASKS_WRITESTART + Start transfer from internal RAM to external flash memory + 0x008 + write-only + 0x00000000 + 0x20 + - PIN17 - Pin 17 - 17 - 17 + TASKS_WRITESTART + Start transfer from internal RAM to external flash memory + 0 + 0 - Low - Pin input is low - 0 - - - High - Pin input is high - 1 + Trigger + Trigger task + 0x1 + + + + TASKS_ERASESTART + Start external flash memory erase operation + 0x00C + write-only + 0x00000000 + 0x20 + - PIN18 - Pin 18 - 18 - 18 + TASKS_ERASESTART + Start external flash memory erase operation + 0 + 0 - Low - Pin input is low - 0 - - - High - Pin input is high - 1 + Trigger + Trigger task + 0x1 + + + + TASKS_DEACTIVATE + Deactivate QSPI interface + 0x010 + write-only + 0x00000000 + 0x20 + - PIN19 - Pin 19 - 19 - 19 + TASKS_DEACTIVATE + Deactivate QSPI interface + 0 + 0 - Low - Pin input is low - 0 - - - High - Pin input is high - 1 + Trigger + Trigger task + 0x1 + + + + EVENTS_READY + QSPI peripheral is ready. This event will be generated as a response to any QSPI task. + 0x100 + read-write + 0x00000000 + 0x20 + - PIN20 - Pin 20 - 20 - 20 + EVENTS_READY + QSPI peripheral is ready. This event will be generated as a response to any QSPI task. + 0 + 0 - Low - Pin input is low - 0 + NotGenerated + Event not generated + 0x0 - High - Pin input is high - 1 + Generated + Event generated + 0x1 + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + - PIN21 - Pin 21 - 21 - 21 + READY + Enable or disable interrupt for event READY + 0 + 0 - Low - Pin input is low - 0 + Disabled + Disable + 0x0 - High - Pin input is high - 1 + Enabled + Enable + 0x1 + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + - PIN22 - Pin 22 - 22 - 22 + READY + Write '1' to enable interrupt for event READY + 0 + 0 + read - Low - Pin input is low - 0 + Disabled + Read: Disabled + 0x0 - High - Pin input is high - 1 + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 - - PIN23 - Pin 23 - 23 - 23 + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + READY + Write '1' to disable interrupt for event READY + 0 + 0 + read - Low - Pin input is low - 0 + Disabled + Read: Disabled + 0x0 - High - Pin input is high - 1 + Enabled + Read: Enabled + 0x1 - - - PIN24 - Pin 24 - 24 - 24 + write - Low - Pin input is low - 0 - - - High - Pin input is high - 1 + Clear + Disable + 0x1 + + + + ENABLE + Enable QSPI peripheral and acquire the pins selected in PSELn registers + 0x500 + read-write + 0x00000000 + 0x20 + - PIN25 - Pin 25 - 25 - 25 + ENABLE + Enable or disable QSPI + 0 + 0 - Low - Pin input is low - 0 + Disabled + Disable QSPI + 0x0 - High - Pin input is high - 1 + Enabled + Enable QSPI + 0x1 + + + + READ + Unspecified + QSPI_READ + read-write + 0x504 + + SRC + Flash memory source address + 0x000 + read-write + 0x00000000 + 0x20 + + + SRC + Word-aligned flash memory source address. + 0 + 31 + + + + + DST + RAM destination address + 0x004 + read-write + 0x00000000 + 0x20 + + + DST + Word-aligned RAM destination address. + 0 + 31 + + + + + CNT + Read transfer length + 0x008 + read-write + 0x00000000 + 0x20 + + + CNT + Read transfer length in number of bytes. The length must be a multiple of 4 bytes. + 0 + 17 + + + + + + WRITE + Unspecified + QSPI_WRITE + read-write + 0x510 + + DST + Flash destination address + 0x000 + read-write + 0x00000000 + 0x20 + + + DST + Word-aligned flash destination address. + 0 + 31 + + + + + SRC + RAM source address + 0x004 + read-write + 0x00000000 + 0x20 + + + SRC + Word-aligned RAM source address. + 0 + 31 + + + + + CNT + Write transfer length + 0x008 + read-write + 0x00000000 + 0x20 + + + CNT + Write transfer length in number of bytes. The length must be a multiple of 4 bytes. + 0 + 17 + + + + + + ERASE + Unspecified + QSPI_ERASE + read-write + 0x51C + + PTR + Start address of flash block to be erased + 0x000 + read-write + 0x00000000 + 0x20 + + + PTR + Word-aligned start address of block to be erased. + 0 + 31 + + + + + LEN + Size of block to be erased. + 0x004 + read-write + 0x00000000 + 0x20 + + + LEN + LEN + 0 + 1 + + + 4KB + Erase 4 kB block (flash command 0x20) + 0x0 + + + 64KB + Erase 64 kB block (flash command 0xD8) + 0x1 + + + All + Erase all (flash command 0xC7) + 0x2 + + + + + + + + PSEL + Unspecified + QSPI_PSEL + read-write + 0x524 + + SCK + Pin select for serial clock SCK + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + CSN + Pin select for chip select signal CSN. + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + IO0 + Pin select for serial data MOSI/IO0. + 0x00C + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + IO1 + Pin select for serial data MISO/IO1. + 0x010 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + IO2 + Pin select for serial data IO2. + 0x014 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + IO3 + Pin select for serial data IO3. + 0x018 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + XIPOFFSET + Address offset into the external memory for Execute in Place operation. + 0x540 + read-write + 0x00000000 + 0x20 + + + XIPOFFSET + Address offset into the external memory for Execute in Place operation. Value must be a multiple of 4. + 0 + 31 + + + + + IFCONFIG0 + Interface configuration. + 0x544 + read-write + 0x00000000 + 0x20 + - PIN26 - Pin 26 - 26 - 26 + READOC + Configure number of data lines and opcode used for reading. + 0 + 2 - Low - Pin input is low - 0 + FASTREAD + Single data line SPI. FAST_READ (opcode 0x0B). + 0x0 - High - Pin input is high - 1 + READ2O + Dual data line SPI. READ2O (opcode 0x3B). + 0x1 - - - - PIN27 - Pin 27 - 27 - 27 - - Low - Pin input is low - 0 + READ2IO + Dual data line SPI. READ2IO (opcode 0xBB). + 0x2 - High - Pin input is high - 1 + READ4O + Quad data line SPI. READ4O (opcode 0x6B). + 0x3 + + + READ4IO + Quad data line SPI. READ4IO (opcode 0xEB). + 0x4 - PIN28 - Pin 28 - 28 - 28 + WRITEOC + Configure number of data lines and opcode used for writing. + 3 + 5 - Low - Pin input is low - 0 + PP + Single data line SPI. PP (opcode 0x02). + 0x0 - High - Pin input is high - 1 + PP2O + Dual data line SPI. PP2O (opcode 0xA2). + 0x1 + + + PP4O + Quad data line SPI. PP4O (opcode 0x32). + 0x2 + + + PP4IO + Quad data line SPI. PP4IO (opcode 0x38). + 0x3 - PIN29 - Pin 29 - 29 - 29 + ADDRMODE + Addressing mode. + 6 + 6 - Low - Pin input is low - 0 + 24BIT + 24-bit addressing. + 0x0 - High - Pin input is high - 1 + 32BIT + 32-bit addressing. + 0x1 - PIN30 - Pin 30 - 30 - 30 + DPMENABLE + Enable deep power-down mode (DPM) feature. + 7 + 7 - Low - Pin input is low - 0 + Disable + Disable DPM feature. + 0x0 - High - Pin input is high - 1 + Enable + Enable DPM feature. + 0x1 - PIN31 - Pin 31 - 31 - 31 + PPSIZE + Page size for commands PP, PP2O, PP4O and PP4IO. + 12 + 12 - Low - Pin input is low - 0 + 256Bytes + 256 bytes. + 0x0 - High - Pin input is high - 1 + 512Bytes + 512 bytes. + 0x1 - DIR - Direction of GPIO pins - 0x514 + IFCONFIG1 + Interface configuration. + 0x600 read-write + 0x00040480 + 0x20 - PIN0 - Pin 0 + SCKDELAY + Minimum amount of time that the CSN pin must stay high before it can go low again. Value is specified in number of 16 MHz periods (62.5 ns). 0 - 0 + 7 + + + DPMEN + Enter/exit deep power-down mode (DPM) for external flash memory. + 24 + 24 - Input - Pin set as input - 0 + Exit + Exit DPM. + 0x0 - Output - Pin set as output - 1 + Enter + Enter DPM. + 0x1 - PIN1 - Pin 1 - 1 - 1 + SPIMODE + Select SPI mode. + 25 + 25 - Input - Pin set as input - 0 + MODE0 + Mode 0: Data are captured on the clock rising edge and data is output on a falling edge. Base level of clock is 0 (CPOL=0, CPHA=0). + 0x0 - Output - Pin set as output - 1 + MODE3 + Mode 3: Data are captured on the clock falling edge and data is output on a rising edge. Base level of clock is 1 (CPOL=1, CPHA=1). + 0x1 - PIN2 - Pin 2 + SCKFREQ + SCK frequency is given as 32 MHz / (SCKFREQ + 1). + 28 + 31 + + + + + STATUS + Status register. + 0x604 + read-only + 0x00000000 + 0x20 + + + DPM + Deep power-down mode (DPM) status of external flash. 2 2 - Input - Pin set as input - 0 + Disabled + External flash is not in DPM. + 0x0 - Output - Pin set as output - 1 + Enabled + External flash is in DPM. + 0x1 - PIN3 - Pin 3 + READY + Ready status. 3 3 - Input - Pin set as input - 0 + READY + QSPI peripheral is ready. It is allowed to trigger new tasks, writing custom instructions or enter/exit DPM. + 0x1 - Output - Pin set as output - 1 + BUSY + QSPI peripheral is busy. It is not allowed to trigger any new tasks, writing custom instructions or enter/exit DPM. + 0x0 - PIN4 - Pin 4 - 4 - 4 + SREG + Value of external flash device Status Register. When the external flash has two bytes status register this field includes the value of the low byte. + 24 + 31 + + + + + DPMDUR + Set the duration required to enter/exit deep power-down mode (DPM). + 0x614 + read-write + 0xFFFFFFFF + 0x20 + + + ENTER + Duration needed by external flash to enter DPM. Duration is given as ENTER * 256 * 62.5 ns. + 0 + 15 + + + EXIT + Duration needed by external flash to exit DPM. Duration is given as EXIT * 256 * 62.5 ns. + 16 + 31 + + + + + ADDRCONF + Extended address configuration. + 0x624 + read-write + 0x000000B7 + 0x20 + + + OPCODE + Opcode that enters the 32-bit addressing mode. + 0 + 7 + + + BYTE0 + Byte 0 following opcode. + 8 + 15 + + + BYTE1 + Byte 1 following byte 0. + 16 + 23 + + + MODE + Extended addressing mode. + 24 + 25 - Input - Pin set as input - 0 + NoInstr + Do not send any instruction. + 0x0 - Output - Pin set as output - 1 + Opcode + Send opcode. + 0x1 - - - - PIN5 - Pin 5 - 5 - 5 - - Input - Pin set as input - 0 + OpByte0 + Send opcode, byte0. + 0x2 - Output - Pin set as output - 1 + All + Send opcode, byte0, byte1. + 0x3 - PIN6 - Pin 6 - 6 - 6 + WIPWAIT + Wait for write complete before sending command. + 26 + 26 - Input - Pin set as input - 0 + Disable + No wait. + 0x0 - Output - Pin set as output - 1 + Enable + Wait. + 0x1 - PIN7 - Pin 7 - 7 - 7 + WREN + Send WREN (write enable opcode 0x06) before instruction. + 27 + 27 - Input - Pin set as input - 0 + Disable + Do not send WREN. + 0x0 - Output - Pin set as output - 1 + Enable + Send WREN. + 0x1 + + + + CINSTRCONF + Custom instruction configuration register. + 0x634 + read-write + 0x00002000 + 0x20 + + + OPCODE + Opcode of Custom instruction. + 0 + 7 + - PIN8 - Pin 8 + LENGTH + Length of custom instruction in number of bytes. 8 - 8 + 11 - Input - Pin set as input - 0 + 1B + Send opcode only. + 0x1 - Output - Pin set as output - 1 + 2B + Send opcode, CINSTRDAT0.BYTE0. + 0x2 - - - - PIN9 - Pin 9 - 9 - 9 - - Input - Pin set as input - 0 + 3B + Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT0.BYTE1. + 0x3 - Output - Pin set as output - 1 + 4B + Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT0.BYTE2. + 0x4 - - - - PIN10 - Pin 10 - 10 - 10 - - Input - Pin set as input - 0 + 5B + Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT0.BYTE3. + 0x5 - Output - Pin set as output - 1 + 6B + Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE4. + 0x6 - - - - PIN11 - Pin 11 - 11 - 11 - - Input - Pin set as input - 0 + 7B + Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE5. + 0x7 - Output - Pin set as output - 1 + 8B + Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE6. + 0x8 + + + 9B + Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE7. + 0x9 - PIN12 - Pin 12 + LIO2 + Level of the IO2 pin (if connected) during transmission of custom instruction. 12 12 + + + LIO3 + Level of the IO3 pin (if connected) during transmission of custom instruction. + 13 + 13 + + + WIPWAIT + Wait for write complete before sending command. + 14 + 14 - Input - Pin set as input - 0 + Disable + No wait. + 0x0 - Output - Pin set as output - 1 + Enable + Wait. + 0x1 - PIN13 - Pin 13 - 13 - 13 + WREN + Send WREN (write enable opcode 0x06) before instruction. + 15 + 15 - Input - Pin set as input - 0 + Disable + Do not send WREN. + 0x0 - Output - Pin set as output - 1 + Enable + Send WREN. + 0x1 - PIN14 - Pin 14 - 14 - 14 + LFEN + Enable long frame mode. When enabled, a custom instruction transaction has to be ended by writing the LFSTOP field. + 16 + 16 - Input - Pin set as input - 0 + Disable + Long frame mode disabled + 0x0 - Output - Pin set as output - 1 + Enable + Long frame mode enabled + 0x1 - PIN15 - Pin 15 - 15 - 15 + LFSTOP + Stop (finalize) long frame transaction + 17 + 17 - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 + Stop + Stop + 0x1 + + + + CINSTRDAT0 + Custom instruction data register 0. + 0x638 + read-write + 0x00000000 + 0x20 + + + BYTE0 + Data byte 0 + 0 + 7 + + + BYTE1 + Data byte 1 + 8 + 15 + + + BYTE2 + Data byte 2 + 16 + 23 + + + BYTE3 + Data byte 3 + 24 + 31 + + + + + CINSTRDAT1 + Custom instruction data register 1. + 0x63C + read-write + 0x00000000 + 0x20 + + + BYTE4 + Data byte 4 + 0 + 7 + + + BYTE5 + Data byte 5 + 8 + 15 + + + BYTE6 + Data byte 6 + 16 + 23 + + + BYTE7 + Data byte 7 + 24 + 31 + + + + + IFTIMING + SPI interface timing. + 0x640 + read-write + 0x00000200 + 0x20 + + + RXDELAY + Timing related to sampling of the input serial data. The value of RXDELAY specifies the number of 64 MHz cycles (15.625 ns) delay from the the rising edge of the SPI Clock (SCK) until the input serial data is sampled. As en example, if set to 0 the input serial data is sampled on the rising edge of SCK. + 8 + 10 + + + + + + + CRYPTOCELL + CRYPTOCELL register interface + 0x5002A000 + + 0 + 0x1000 + registers + + + CRYPTOCELL + 42 + + CRYPTOCELL + 0x20 + + + ENABLE + Enable CRYPTOCELL subsystem. + 0x500 + read-write + 0x00000000 + 0x20 + - PIN16 - Pin 16 - 16 - 16 + ENABLE + Enable or disable the CRYPTOCELL subsystem. + 0 + 0 - Input - Pin set as input - 0 + Disabled + CRYPTOCELL subsystem disabled. + 0x0 - Output - Pin set as output - 1 + Enabled + CRYPTOCELL subsystem enabled. + 0x1 + + + + + + CC_AES + CRYPTOCELL AES engine + 0x5002B000 + + 0 + 0x1000 + registers + + CC_AES + 0x20 + + + 0x8 + 0x4 + AES_KEY_0[%s] + Description collection: AES key value to use. + The initial AES_KEY_0[0] register holds the least significant bits [31:0] of the key value. + 0x400 + write-only + 0x00000000 + 0x20 + - PIN17 - Pin 17 - 17 - 17 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - + VALUE + AES key value. + 0 + 31 + + + + 0x4 + 0x4 + AES_IV_0[%s] + Description collection: AES Initialization Vector (IV) to use. + The initial AES_IV_0[0] register holds the least significant bits [31:0] of the IV. + 0x440 + read-write + 0x00000000 + 0x20 + - PIN18 - Pin 18 - 18 - 18 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - + VALUE + AES non-tunneling or first tunnel stage IV value. + 0 + 31 + + + + 0x4 + 0x4 + AES_CTR[%s] + Description collection: AES counter (CTR) to use. + The initial AES_CTR[0] register holds the least significant bits [31:0] of the CTR. + 0x460 + read-write + 0x00000000 + 0x20 + - PIN19 - Pin 19 - 19 - 19 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - + VALUE + AES CTR value. + 0 + 31 + + + + AES_BUSY + Status register for AES engine activity. + 0x470 + read-only + 0x00000000 + 0x20 + - PIN20 - Pin 20 - 20 - 20 + STATUS + AES engine status. + 0 + 0 - Input - Pin set as input - 0 + Idle + AES engine is idle + 0x0 - Output - Pin set as output - 1 + Busy + AES engine is busy + 0x1 + + + + AES_SK + Writing to this address trigger sampling of the HW key to the AES_KEY_0 register + 0x478 + write-only + 0x00000000 + 0x20 + - PIN21 - Pin 21 - 21 - 21 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - + AES_SK + Sample HW key to AES_KEY_0 registers. + 0 + 0 + + + + AES_CMAC_INIT + Writing to this address triggers the AES engine to generate K1 and K2 for AES-CMAC operations. + 0x47C + write-only + 0x00000000 + 0x20 + - PIN22 - Pin 22 - 22 - 22 + ENABLE + Generate K1 and K2 for the AES-CMAC operations. + 0 + 0 - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 + Enable + Initialize AES-CMAC operations. + 0x1 + + + + AES_REMAINING_BYTES + This register should be set with the amount of remaining bytes until the end of the current AES operation. + 0x4BC + read-write + 0x00000000 + 0x20 + - PIN23 - Pin 23 - 23 - 23 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - + VALUE + Remaining bytes util the end of the current AES operation. + 0 + 31 + + + + AES_CONTROL + Control the AES engine behavior. + 0x4C0 + read-write + 0x00000000 + 0x20 + - PIN24 - Pin 24 - 24 - 24 + DEC_KEY0 + Set AES encrypt or decrypt mode in non-tunneling operations. + 0 + 0 - Input - Pin set as input - 0 + Encrypt + Perform AES encryption + 0x0 - Output - Pin set as output - 1 + Decrypt + Perform AES decryption + 0x1 - PIN25 - Pin 25 - 25 - 25 + MODE_KEY0 + Set the AES mode. + 2 + 4 - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 + ECB + Electronic codebook mode + 0x0 - - - - PIN26 - Pin 26 - 26 - 26 - - Input - Pin set as input - 0 + CBC + Cipher block chaining mode + 0x1 - Output - Pin set as output - 1 + CTR + Counter mode + 0x2 - - - - PIN27 - Pin 27 - 27 - 27 - - Input - Pin set as input - 0 + CBC_MAC + Cipher Block Chaining Message Authentication Code + 0x3 - Output - Pin set as output - 1 + CMAC + Cipher-based Message Authentication Code + 0x7 - PIN28 - Pin 28 - 28 - 28 + NK_KEY0 + Set the AES key length. + 12 + 13 - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 + 128Bits + 128 bits key length + 0x0 - PIN29 - Pin 29 + AES_XOR_CRYPTOKEY + This field determines the value that is written to AES_KEY_0, when AES_SK is kicked. 29 29 - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN30 - Pin 30 - 30 - 30 - - - Input - Pin set as input - 0 + Disable + The value that is written to AES_KEY_0 is the value of the HW cryptokey as is. + 0x0 - Output - Pin set as output - 1 + Enable + The value that is written to AES_KEY_0 is the value of the HW cryptokey XOR with the current value of AES_KEY_0. + 0x1 - PIN31 - Pin 31 + DIRECT_ACCESS + Using direct access and not the DIN-DOUT DMA interface 31 31 - Input - Pin set as input - 0 + Disable + Access using the DIN-DOUT DMA interface + 0x0 - Output - Pin set as output - 1 + Enable + Access using direct access + 0x1 - DIRSET - DIR set register - 0x518 - read-write - oneToSet + AES_HW_FLAGS + Hardware configuration of the AES engine. Reset value holds the supported features. + 0x4C8 + read-only + 0x00000108 + 0x20 - PIN0 - Set as output pin 0 + SUPPORT_256_192_KEY + If this flag is set, the engine support 192 bits and 256 bits key size. 0 0 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - PIN1 - Set as output pin 1 + AES_LARGE_RKEK + If this flag is set, the engine support AES_LARGE_RKEK. 1 1 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - PIN2 - Set as output pin 2 + DPA_CNTRMSR_EXIST + If this flag is set, the engine support DPA countermeasures. 2 2 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - PIN3 - Set as output pin 3 + CTR_EXIST + If this flag is set, the engine support AES CTR mode. 3 3 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - PIN4 - Set as output pin 4 + ONLY_ENCRYPT + If this flag is set, the engine only support encrypt operations. 4 4 + + + USE_SBOX_TABLE + If this flag is set, the engine uses SBOX tables. + 5 + 5 + + + USE_5_SBOXES + If this flag is set, the engine uses 5 SBOX where each AES round takes 4 cycles. + 8 + 8 + + + AES_SUPPORT_PREV_IV + If this flag is set, the engine contains the PREV_IV register for faster AES XCBC MAC calculation. + 9 + 9 + + + AES_TUNNEL_EXIST + If this flag is set, the engine support tunneling operations. + 10 + 10 + + + SECOND_REGS_SET_EXIST + If this flag is set, the engine support a second register set for tunneling operations. + 11 + 11 + + + DFA_CNTRMSR_EXIST + If this flag is set, the engine support DFA countermeasures. + 12 + 12 + + + + + AES_CTR_NO_INCREMENT + This register enables the AES CTR no increment mode in which the counter mode is not incremented between two blocks + 0x4D8 + read-write + 0x00000000 + 0x20 + + + ENABLE + This field enables the AES CTR no increment mode in which the counter mode is not incremented between two blocks + 0 + 0 - read - Input - Read: pin set as input - 0 + Disable + Counter always incremented between blocks + 0x0 - Output - Read: pin set as output - 1 + Enable + Do not increment counter between blocks + 0x1 + + + + + AES_SW_RESET + Reset the AES engine. + 0x4F4 + write-only + 0x00000000 + 0x20 + + + RESET + Writing any value to this address resets the AES engine. The reset takes 4 CPU clock cycles to complete. + 0 + 0 - write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + Enable + Reset AES engine. + 0x1 + + + + AES_CMAC_SIZE0_KICK + Writing to this address triggers the AES engine to perform a CMAC operation with size 0. The CMAC result can be read from the AES_IV_0 register. + 0x524 + write-only + 0x00000000 + 0x20 + - PIN5 - Set as output pin 5 - 5 - 5 + ENABLE + Force AES CMAC operation with size 0. + 0 + 0 - read - - Input - Read: pin set as input - 0 - - Output - Read: pin set as output - 1 + Disable + Normal AES CMAC operation + 0x0 - - - write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + Enable + Force CMAC operation with size 0 + 0x1 + + + + + + CC_CHACHA + CRYPTOCELL CHACHA engine + 0x5002B000 + CC_AES + + 0 + 0x1000 + registers + + CC_CHACHA + 0x20 + + + CHACHA_CONTROL + Control the CHACHA engine behavior. + 0x380 + read-write + 0x00000000 + 0x20 + - PIN6 - Set as output pin 6 - 6 - 6 + CHACHA_OR_SALSA + Run engine in ChaCha or Salsa mode + 0 + 0 - read - Input - Read: pin set as input - 0 + ChaCha + Run engine in ChaCha mode + 0x0 - Output - Read: pin set as output - 1 + Salsa + Run engine in Salsa mode + 0x1 + + + INIT + Perform initialization for a new message + 1 + 1 - write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + Disable + Message already initialized + 0x0 + + + Enable + Initialize new message + 0x1 - PIN7 - Set as output pin 7 - 7 - 7 + GEN_KEY_POLY1305 + Generate the key to use in Poly1305 message authentication code calculation. + 2 + 2 - read - Input - Read: pin set as input - 0 + Disable + Do not generate Poly1305 key + 0x0 - Output - Read: pin set as output - 1 + Enable + Generate Poly1305 key + 0x1 + + + KEY_LEN + Key length selection. + 3 + 3 - write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + 256Bits + Use 256 bits key length + 0x0 + + + 128Bits + Use 128 bits key length + 0x1 - PIN8 - Set as output pin 8 - 8 - 8 + NUM_OF_ROUNDS + Set number of permutation rounds, default value is 20. + 4 + 5 - read - Input - Read: pin set as input - 0 + Default + Use 20 rounds of rotation (default) + 0x0 - Output - Read: pin set as output - 1 + 12Rounds + Use 12 rounds of rotation + 0x1 - - - write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + 8Rounds + Use 8 rounds of rotation + 0x2 - PIN9 - Set as output pin 9 + RESET_BLOCK_CNT + Reset block counter for new messages 9 9 - read - - Input - Read: pin set as input - 0 - - Output - Read: pin set as output - 1 + Disable + Use current block counter value + 0x0 - - - write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + Enable + Reset block counter value to zero + 0x1 - PIN10 - Set as output pin 10 + USE_IV_96BIT + Use 96 bits Initialization Vector (IV) 10 10 - read - - Input - Read: pin set as input - 0 - - Output - Read: pin set as output - 1 + Disable + Use default size IV of 64 bit + 0x0 - - - write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + Enable + The IV is 96 bits + 0x1 + + + + CHACHA_VERSION + CHACHA engine HW version + 0x384 + read-only + 0x00000001 + 0x20 + + + CHACHA_VERSION + 0 + 31 + + + + + 0x8 + 0x4 + CHACHA_KEY[%s] + Description collection: CHACHA key value to use. The initial CHACHA_KEY[0] register holds the least significant bits [31:0] of the key value. + 0x388 + write-only + 0x00000000 + 0x20 + - PIN11 - Set as output pin 11 - 11 - 11 + VALUE + CHACHA key value. + 0 + 31 + + + + + 0x2 + 0x4 + CHACHA_IV[%s] + Description collection: CHACHA Initialization Vector (IV) to use. The IV is also known as the nonce. + 0x3A8 + read-write + 0x00000000 + 0x20 + + + VALUE + CHACHA IV value. + 0 + 31 + + + + + CHACHA_BUSY + Status register for CHACHA engine activity. + 0x3B0 + read-only + 0x00000000 + 0x20 + + + STATUS + CHACHA engine status. + 0 + 0 - read - Input - Read: pin set as input - 0 + Idle + CHACHA engine is idle + 0x0 - Output - Read: pin set as output - 1 + Busy + CHACHA engine is busy + 0x1 + + + + + CHACHA_HW_FLAGS + Hardware configuration of the CHACHA engine. Reset value holds the supported features. + 0x3B4 + read-only + 0x00000001 + 0x20 + + + CHACHA_EXISTS + If this flag is set, the engine include ChaCha support + 0 + 0 + + + SALSA_EXISTS + If this flag is set, the engine include Salsa support + 1 + 1 + + + FAST_CHACHA + If this flag is set, the next matrix calculated when the current one is written to data output path. + 2 + 2 + + + + + CHACHA_BLOCK_CNT_LSB + Store the LSB value of the block counter, in order to support suspend/resume of operation + 0x3B8 + read-write + 0x00000000 + 0x20 + + + VALUE + This register holds the ChaCha block counter bits [31:0] and must be read and written during respectively suspend and resume operations. + 0 + 31 + + + + + CHACHA_BLOCK_CNT_MSB + Store the MSB value of the block counter, in order to support suspend/resume of operation + 0x3BC + read-write + 0x00000000 + 0x20 + + + VALUE + This register holds the ChaCha block counter bits [63:32] and must be read and written during respectively suspend and resume operations. + 0 + 31 + + + + + CHACHA_SW_RESET + Reset the CHACHA engine. + 0x3C0 + write-only + 0x00000000 + 0x20 + + + RESET + Writing any value to this address resets the CHACHA engine. The reset takes 4 CPU clock cycles to complete. + 0 + 0 - write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + Enable + Reset CHACHA engine. + 0x1 + + + + 0x8 + 0x4 + CHACHA_POLY1305_KEY[%s] + Description collection: The auto-generated key to use in Poly1305 MAC calculation. The initial CHACHA_POLY1305_KEY[0] register holds the least significant bits [31:0] of the key value. + 0x3C4 + read-only + 0x00000000 + 0x20 + - PIN12 - Set as output pin 12 - 12 - 12 + VALUE + Poly1305 key value. + 0 + 31 + + + + + CHACHA_ENDIANNESS + CHACHA engine data order configuration. + 0x3E4 + read-write + 0x00000000 + 0x20 + + + CHACHA_DIN_WORD_ORDER + Change the word order of the input data. + 0 + 0 - read - - Input - Read: pin set as input - 0 - - Output - Read: pin set as output - 1 + Default + Use default word order for 128-bits input, where words are ordered as follows: w0, w1, w2, w3. + 0x0 - - - write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + Reverse + Reverses the word order for 128-bits input, where words are re-ordered as follows: w3, w2, w1, w0. + 0x1 - PIN13 - Set as output pin 13 - 13 - 13 + CHACHA_DIN_BYTE_ORDER + Change the byte order of the input data. + 1 + 1 - read - Input - Read: pin set as input - 0 + Default + Use default byte order within each input word, where bytes are ordered as follows: B0, B1, B2, B3. + 0x0 - Output - Read: pin set as output - 1 + Reverse + Reverse the byte order within each input word, where bytes are re-ordered as follows: B3, B2, B1, B0. + 0x1 + + + CHACHA_CORE_MATRIX_LBE_ORDER + Change the quarter of a matrix order in the engine. + 2 + 2 - write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + Default + Use default quarter of matrix order, where quarters are ordered as follows: q0, q1, q2, q3. Each quarter represents a 128-bits section of the matrix. + 0x0 + + + Reverse + Reverse the order of matrix quarters, where quarters are re-ordered as follows: q3, q2, q1, q0. Each quarter represents a 128-bits section of the matrix. + 0x1 - PIN14 - Set as output pin 14 - 14 - 14 + CHACHA_DOUT_WORD_ORDER + Change the word order of the output data. + 3 + 3 - read - Input - Read: pin set as input - 0 + Default + Uses default word order for 128-bits output, where words are ordered as follows: w0, w1, w2, w3. + 0x0 - Output - Read: pin set as output - 1 + Reverse + Reverse the word order for 128-bits output, where words are re-ordered as follows: w3, w2, w1, w0. + 0x1 + + + CHACHA_DOUT_BYTE_ORDER + Change the byte order of the output data. + 4 + 4 - write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + Default + Use default byte order within each output word, where bytes are ordered as follows: B0, B1, B2, B3. + 0x0 + + + Reverse + Reverse the byte order within each output word, where bytes are re-ordered as follows: B3, B2, B1, B0. + 0x1 + + + + CHACHA_DEBUG + Debug register for the CHACHA engine + 0x3E8 + read-only + 0x00000000 + 0x20 + - PIN15 - Set as output pin 15 - 15 - 15 + FSM_STATE + Reflects the debug state of the CHACHA FSM. + 0 + 1 - read - Input - Read: pin set as input - 0 + IDLE_STATE + CHACHA FSM is in idle state + 0x0 - Output - Read: pin set as output - 1 + INIT_STATE + CHACHA FSM is in init state + 0x1 - - - write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + ROUNDS_STATE + CHACHA FSM is in rounds state + 0x2 + + + FINAL_STATE + CHACHA FSM is in final state + 0x3 + + + + + + CC_CTL + CRYPTOCELL CTL interface + 0x5002B000 + CC_AES + + 0 + 0x1000 + registers + + CC_CTL + 0x20 + + + CRYPTO_CTL + Defines the cryptographic flow. + 0x900 + write-only + 0x00000000 + 0x20 + - PIN16 - Set as output pin 16 - 16 - 16 + MODE + Configure the cryptographic engine mode. + 0 + 4 - read - Input - Read: pin set as input - 0 + Bypass + Bypass cryptographic engine + 0x00 - Output - Read: pin set as output - 1 + AESActive + Use AES engine + 0x01 - - - write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + AESToHashActive + Pipe AES engine output to HASH engine input + 0x02 - - - - PIN17 - Set as output pin 17 - 17 - 17 - - read - Input - Read: pin set as input - 0 + AESAndHashActive + Process input using both AES and HASH engine in parallell + 0x03 - Output - Read: pin set as output - 1 + HashActive + Use HASH engine + 0x07 + + + AESMACAndBypassActive + Calculate AES MAC and bypass + 0x09 + + + AESToHashAndDOUTActive + Pipe AES engine output to HASH engine input. The resulting digest output is piped to DOUT buffer. + 0x0A + + + ChaChaActive + Use CHACHA engine + 0x10 + + + + + CRYPTO_BUSY + Status register for cryptographic cores engine activity. + 0x910 + read-only + 0x00000000 + 0x20 + + + STATUS + Cryptographic core engines status. + 0 + 0 - write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + Idle + Cryptographic core engines are idle + 0x0 + + + Busy + Cryptographic core engines are busy + 0x1 + + + + HASH_BUSY + Status register for HASH engine activity. + 0x91C + read-only + 0x00000000 + 0x20 + - PIN18 - Set as output pin 18 - 18 - 18 + STATUS + Hash engine status. + 0 + 0 - read - Input - Read: pin set as input - 0 + Idle + HASH engine is idle + 0x0 - Output - Read: pin set as output - 1 + Busy + HASH engine is busy + 0x1 + + + + + CONTEXT_ID + A general-purpose read/write register. + 0x930 + read-write + 0x00000000 + 0x20 + + + CONTEXT_ID + Context ID + 0 + 7 + + + + + + + CC_DIN + CRYPTOCELL Data IN interface + 0x5002B000 + CC_AES + + 0 + 0x1000 + registers + + CC_DIN + 0x20 + + + DIN_BUFFER + Used by CPU to write data directly to the DIN buffer, which is then sent to the cryptographic engines for processing. + 0xC00 + write-only + 0x00000000 + 0x20 + + + DATA + This register is mapped into 8 addresses in order to enable a CPU burst. + 0 + 31 + + + + + DIN_DMA_MEM_BUSY + Status register for DIN DMA engine activity when accessing memory. + 0xC20 + read-only + 0x00000000 + 0x20 + + + STATUS + DIN memory DMA engine status. + 0 + 0 - write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + Idle + DIN memory DMA engine is idle + 0x0 + + + Busy + DIN memory DMA engine is busy + 0x1 + + + + SRC_MEM_ADDR + Data source address in memory. + 0xC28 + write-only + 0x00000000 + 0x20 + - PIN19 - Set as output pin 19 - 19 - 19 + ADDR + Source address in memory. + 0 + 31 + + + + + SRC_MEM_SIZE + The number of bytes to be read from memory. Writing to this register triggers the DMA operation. + 0xC2C + write-only + 0x00000000 + 0x20 + + + SIZE + Total number of bytes to read from memory. + 0 + 29 + + + FIRST + This field is reserved + 30 + 30 + + + LAST + This field is reserved + 31 + 31 + + + + + SRC_SRAM_ADDR + Data source address in RNG SRAM. + 0xC30 + read-write + 0x00000000 + 0x20 + + + ADDR + Source address in RNG SRAM. + 0 + 31 + + + + + SRC_SRAM_SIZE + The number of bytes to be read from RNG SRAM. Writing to this register triggers the DMA operation. + 0xC34 + write-only + 0x00000000 + 0x20 + + + SIZE + Total number of bytes to read from RNG SRAM. + 0 + 31 + + + + + DIN_DMA_SRAM_BUSY + Status register for DIN DMA engine activity when accessing RNG SRAM. + 0xC38 + read-only + 0x00000000 + 0x20 + + + STATUS + DIN RNG SRAM DMA engine status. + 0 + 0 - read - - Input - Read: pin set as input - 0 - - Output - Read: pin set as output - 1 + Idle + DIN RNG SRAM DMA engine is idle + 0x0 - - - write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + Busy + DIN RNG SRAM DMA engine is busy + 0x1 + + + + DIN_DMA_SRAM_ENDIANNESS + Configure the endianness of DIN DMA transactions towards RNG SRAM. + 0xC3C + read-write + 0x00000000 + 0x20 + - PIN20 - Set as output pin 20 - 20 - 20 + ENDIAN + Endianness of DIN DMA transactions towards RNG SRAM. The default value is little-endian. + 0 + 0 - read - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 + LittleEndian + Use little-endian format for RNG SRAM DMA transactions + 0x0 - - - write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + BigEndian + Use big-endian format for RNG SRAM DMA transactions + 0x1 + + + + DIN_SW_RESET + Reset the DIN DMA engine. + 0xC44 + write-only + 0x00000000 + 0x20 + - PIN21 - Set as output pin 21 - 21 - 21 + RESET + Writing any value to this address resets the DIN DMA engine. The reset takes 4 CPU clock cycles to complete. + 0 + 0 - read - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 + Enable + Reset DIN DMA engine. + 0x1 + + + + + DIN_CPU_DATA + Specifies the number of bytes the CPU will write to the DIN_BUFFER, ensuring the cryptographic engine processes the correct amount of data. + 0xC48 + write-only + 0x00000000 + 0x20 + + + SIZE + When using CPU direct write to the DIN_BUFFER, the size of input data in bytes should be written to this register. + 0 + 15 + + + + + DIN_WRITE_ALIGN + Indicates that the next CPU write to the DIN_BUFFER is the last in the sequence. This is needed only when the data size is NOT modulo 4 (e.g. HASH padding). + 0xC4C + write-only + 0x00000000 + 0x20 + + + LAST + Next CPU write to the DIN_BUFFER is the last word. + 0 + 0 - write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + Confirm + The next CPU write is the last in the sequence. + 0x1 + + + + DIN_FIFO_EMPTY + Register indicating if DIN FIFO is empty and if more data can be accepted. + 0xC50 + read-only + 0x00000001 + 0x20 + - PIN22 - Set as output pin 22 - 22 - 22 + STATUS + DIN FIFO status + 0 + 0 - read - Input - Read: pin set as input - 0 + NotEmpty + DIN FIFO is not empty + 0x0 - Output - Read: pin set as output - 1 + Empty + DIN FIFO is empty, and more data can be accepted + 0x1 + + + + + DIN_FIFO_RESET + Reset the DIN FIFO, effectively clearing the FIFO for new data. + 0xC58 + write-only + 0x00000000 + 0x20 + + + RESET + Writing any value to this address resets the DIN FIFO. + 0 + 0 - write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + Enable + Reset DIN FIFO. + 0x1 + + + + + + CC_DOUT + CRYPTOCELL Data OUT interface + 0x5002B000 + CC_AES + + 0 + 0x1000 + registers + + CC_DOUT + 0x20 + + + DOUT_BUFFER + Cryptographic results directly accessible by the CPU. + 0xC00 + read-only + 0x00000000 + 0x20 + + + DATA + This address can be used by the CPU to read data directly from the DOUT buffer. + 0 + 31 + + + + + DOUT_DMA_MEM_BUSY + Status register for DOUT DMA engine activity when accessing memory. + 0xD20 + read-only + 0x00000000 + 0x20 + - PIN23 - Set as output pin 23 - 23 - 23 + STATUS + DOUT memory DMA engine status. + 0 + 0 - read - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 + Idle + DOUT memory DMA engine is idle + 0x0 - - - write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + Busy + DOUT memory DMA engine is busy + 0x1 + + + + DST_MEM_ADDR + Data destination address in memory. + 0xD28 + write-only + 0x00000000 + 0x20 + - PIN24 - Set as output pin 24 - 24 - 24 + ADDR + Destination address in memory. + 0 + 31 + + + + + DST_MEM_SIZE + The number of bytes to be written to memory. + 0xD2C + write-only + 0x00000000 + 0x20 + + + SIZE + Total number of bytes to write to memory. + 0 + 29 + + + FIRST + This field is reserved + 30 + 30 + + + LAST + This field is reserved + 31 + 31 + + + + + DST_SRAM_ADDR + Data destination address in RNG SRAM. + 0xD30 + read-write + 0x00000000 + 0x20 + + + ADDR + Destination address in RNG SRAM. + 0 + 31 + + + + + DST_SRAM_SIZE + The number of bytes to be written to RNG SRAM. + 0xD34 + write-only + 0x00000000 + 0x20 + + + SIZE + Total number of bytes to write to RNG SRAM. + 0 + 31 + + + + + DOUT_DMA_SRAM_BUSY + Status register for DOUT DMA engine activity when accessing RNG SRAM. + 0xD38 + read-only + 0x00000000 + 0x20 + + + STATUS + DOUT RNG SRAM DMA engine status. + 0 + 0 - read - - Input - Read: pin set as input - 0 - - Output - Read: pin set as output - 1 + Idle + DOUT RNG SRAM DMA engine is idle + 0x0 - - - write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + Busy + DOUT RNG SRAM DMA engine is busy + 0x1 + + + + DOUT_DMA_SRAM_ENDIANNESS + Configure the endianness of DOUT DMA transactions towards RNG SRAM. + 0xD3C + read-write + 0x00000000 + 0x20 + - PIN25 - Set as output pin 25 - 25 - 25 + ENDIAN + Endianness of DOUT DMA transactions towards RNG SRAM. The default value is little-endian. + 0 + 0 - read - Input - Read: pin set as input - 0 + LittleEndian + Use little-endian format for RNG SRAM DMA transactions + 0x0 - Output - Read: pin set as output - 1 + BigEndian + Use big-endian format for RNG SRAM DMA transactions + 0x1 + + + + + DOUT_READ_ALIGN + Indication that the next CPU read from the DOUT_BUFFER is the last in the sequence. This is needed only when the data size is NOT modulo 4 (e.g. HASH padding). + 0xD44 + write-only + 0x00000000 + 0x20 + + + LAST + Next CPU read from the DOUT_BUFFER is the last word, and the remaining read aligned content can be flushed. + 0 + 0 - write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + Flush + Flush the remaining read aligned content. + 0x1 + + + + DOUT_FIFO_EMPTY + Register indicating if DOUT FIFO is empty or if more data will come. + 0xD50 + read-only + 0x00000001 + 0x20 + - PIN26 - Set as output pin 26 - 26 - 26 + STATUS + DOUT FIFO status + 0 + 0 - read - Input - Read: pin set as input - 0 + NotEmpty + DOUT FIFO is not empty, and more data will come + 0x0 - Output - Read: pin set as output - 1 + Empty + DOUT FIFO is empty + 0x1 + + + + + DOUT_SW_RESET + Reset the DOUT DMA engine. + 0xD58 + write-only + 0x00000000 + 0x20 + + + RESET + Writing any value to this address resets the DOUT DMA engine. The reset takes 4 CPU clock cycles to complete. + 0 + 0 - write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + Enable + Reset DOUT DMA engine. + 0x1 + + + + + + CC_HASH + CRYPTOCELL HASH engine + 0x5002B000 + CC_AES + + 0 + 0x1000 + registers + + CC_HASH + 0x20 + + + 0x8 + 0x4 + HASH_H[%s] + Description collection: HASH_H value registers. The initial HASH_H[0] register holds the least significant bits [31:0] of the value. + 0x640 + read-write + 0x00000000 + 0x20 + + + VALUE + Write the initial hash value before start of digest operation, and read the final hash value result after + the digest operation has been completed. + 0 + 31 + + + + + HASH_PAD_AUTO + Configure the HASH engine to automatically pad data at the end of the DMA transfer to complete the digest operation. + 0x684 + write-only + 0x00000000 + 0x20 + - PIN27 - Set as output pin 27 - 27 - 27 + HWPAD + Enable automatic padding in hardware. + 0 + 0 - read - - Input - Read: pin set as input - 0 - - Output - Read: pin set as output - 1 + Disable + Do not enable automatic hardware padding. + 0x0 - - - write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + Enable + Enable automatic hardware padding. + 0x1 + + + + HASH_INIT_STATE + Configure HASH engine initial state registers. + 0x694 + write-only + 0x00000000 + 0x20 + - PIN28 - Set as output pin 28 - 28 - 28 + LOAD + Enable loading of data to initial state registers. Digest/IV for HASH/AES_MAC. + 0 + 0 - read - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 + Disable + Disable loading of data to initial state registers. + 0x0 - - - write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + Enable + Enable loading of data to initial state registers. + 0x1 + + + + HASH_VERSION + HASH engine HW version + 0x7B0 + read-only + 0x00000000 + 0x20 + + + PATCH + 0 + 7 + - PIN29 - Set as output pin 29 - 29 - 29 + MINOR_VERSION_NUMBER + Minor version number + 8 + 11 + + + MAJOR_VERSION_NUMBER + Major version number + 12 + 15 + + + + + HASH_CONTROL + Control the HASH engine behavior. + 0x7C0 + read-write + 0x00000000 + 0x20 + + + MODE + Select HASH mode to execute + 0 + 3 - read - Input - Read: pin set as input - 0 + SHA1 + Select SHA1 mode + 0x1 - Output - Read: pin set as output - 1 + SHA256 + Select SHA256 mode + 0x2 - - - write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + SHA224 + Select SHA224 mode + 0xA + + + + HASH_PAD + Enable the hardware padding feature of the HASH engine. + 0x7C4 + read-write + 0x00000001 + 0x20 + - PIN30 - Set as output pin 30 - 30 - 30 + ENABLE + Configure hardware padding feature. + 0 + 0 - read - - Input - Read: pin set as input - 0 - - Output - Read: pin set as output - 1 + Disable + Disable hardware padding feature. + 0x0 - - - write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + Enable + Enable hardware padding feature. + 0x1 + + + + HASH_PAD_FORCE + Force the hardware padding operation to trigger if the input data length is zero bytes. + 0x7C8 + read-write + 0x00000000 + 0x20 + - PIN31 - Set as output pin 31 - 31 - 31 + ENABLE + Trigger hardware padding operation. + 2 + 2 - read - - Input - Read: pin set as input - 0 - - Output - Read: pin set as output - 1 + Disable + Do not force hardware padding to trigger. + 0x0 - - - write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + Enable + Force hardware padding to trigger. + 0x1 - DIRCLR - DIR clear register - 0x51C + HASH_CUR_LEN_0 + Bits [31:0] of the number of bytes that have been digested so far. + 0x7CC read-write - oneToClear + 0x00000000 + 0x20 - PIN0 - Set as input pin 0 + VALUE + Bits [31:0] of current length of digested data in bytes. 0 - 0 - - read - - Input - Read: pin set as input - 0 - + 31 + + + + + HASH_CUR_LEN_1 + Bits [63:32] of the number of bytes that have been digested so far. + 0x7D0 + read-write + 0x00000000 + 0x20 + + + VALUE + Bits [63:32] of current length of digested data in bytes. + 0 + 31 + + + + + HASH_HW_FLAGS + Hardware configuration of the HASH engine. Reset value holds the supported features. + 0x7DC + read-only + 0x00012001 + 0x20 + + + CW + Indicates the number of concurrent words the hash is using to compute signature. + 0 + 3 + - Output - Read: pin set as output - 1 + One + One concurrent word used by hash during signature generation + 0x1 - - - write - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + Two + Two concurrent words used by hash during signature generation + 0x2 - PIN1 - Set as input pin 1 - 1 - 1 + CH + Indicate if Hi adders are present for each Hi value or 1 adder is shared for all Hi. + 4 + 7 - read - - Input - Read: pin set as input - 0 - - Output - Read: pin set as output - 1 + One + One Hi value is updated at a time. + 0x0 - - - write - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + All + All Hi values are updated at the same time. + 0x1 - PIN2 - Set as input pin 2 - 2 - 2 + DW + Determine the granularity of word size. + 8 + 11 - read - Input - Read: pin set as input - 0 + 32Bits + 32 bits word data. + 0x0 - Output - Read: pin set as output - 1 + 64Bits + 64 bits word data. + 0x1 + + + SHA_512_EXISTS + If this flag is set, the engine include SHA-512 support. + 12 + 12 + + + PAD_EXISTS + If this flag is set, the engine include pad block support. + 13 + 13 + + + MD5_EXISTS + If this flag is set, the engine include MD5 support. + 14 + 14 + + + HMAC_EXISTS + If this flag is set, the engine include HMAC support. + 15 + 15 + + + SHA_256_EXISTS + If this flag is set, the engine include SHA-256 support. + 16 + 16 + + + HASH_COMPARE_EXISTS + If this flag is set, the engine include compare digest logic. + 17 + 17 + + + DUMP_HASH_TO_DOUT_EXISTS + If this flag is set, the engine include HASH to DOUT support. + 18 + 18 + + + + + HASH_SW_RESET + Reset the HASH engine. + 0x7E4 + write-only + 0x00000000 + 0x20 + + + RESET + Writing any value to this address resets the HASH engine. The reset takes 4 CPU clock cycles to complete. + 0 + 0 - write - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + Enable + Reset HASH engine. + 0x1 + + + + HASH_ENDIANNESS + Configure the endianness of HASH data and padding generation. + 0x7E8 + read-write + 0x00000001 + 0x20 + - PIN3 - Set as input pin 3 - 3 - 3 + ENDIAN + Endianness of HASH data and padding generation. The default value is little-endian. + 0 + 0 - read - - Input - Read: pin set as input - 0 - - Output - Read: pin set as output - 1 + LittleEndian + Use little-endian format for data and padding + 0x0 - - - write - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + BigEndian + Use big-endian format for data and padding + 0x1 + + + + + + CC_HOST_RGF + CRYPTOCELL HOST register interface + 0x5002B000 + CC_AES + + 0 + 0x1000 + registers + + CC_HOST_RGF + 0x20 + + + IRR + Interrupt request register. Each bit of this register holds the interrupt + status of a single interrupt source. If corresponding IMR bit is + unmasked, an interrupt is generated. + 0xA00 + read-only + 0x00000000 + 0x20 + - PIN4 - Set as input pin 4 + SRAM_TO_DIN_INT + The RNG SRAM to DIN DMA done interrupt status. This interrupt is asserted when all data was delivered from RNG SRAM to DIN buffer. + 4 + 4 + + + DOUT_TO_SRAM_INT + The DOUT to RNG SRAM DMA done interrupt status. This interrupt is asserted when all data was delivered from DOUT buffer to RNG SRAM. + 5 + 5 + + + MEM_TO_DIN_INT + The memory to DIN DMA done interrupt status. This interrupt is asserted when all data was delivered from memory to DIN buffer. + 6 + 6 + + + DOUT_TO_MEM_INT + The DOUT to memory DMA done interrupt status. This interrupt is asserted when all data was delivered from DOUT buffer to memory. + 7 + 7 + + + AHB_ERR_INT + The AHB error interrupt status. + 8 + 8 + + + PKA_INT + The PKA end of operation interrupt status. + 9 + 9 + + + RNG_INT + The RNG interrupt status. + 10 + 10 + + + + + IMR + Interrupt mask register. Each bit of this register holds the mask of a single interrupt source. + 0xA04 + read-write + 0x01FFFFFF + 0x20 + + + SRAM_TO_DIN_MASK + The RNG SRAM to DIN DMA done interrupt mask. 4 4 - read - - Input - Read: pin set as input - 0 - - Output - Read: pin set as output - 1 + IRQEnable + Do not mask RNG SRAM to DIN DMA done interrupt i.e. interrupt is generated + 0x0 - - - write - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + IRQDisable + Mask RNG SRAM to DIN DMA done interrupt i.e. no interrupt is generated + 0x1 - PIN5 - Set as input pin 5 + DOUT_TO_SRAM_MASK + The DOUT to RNG SRAM DMA done interrupt mask. 5 5 - read - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 + IRQEnable + Do not mask DOUT to RNG SRAM DMA done interrupt i.e. interrupt is generated + 0x0 - - - write - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + IRQDisable + Mask DOUT to RNG SRAM DMA done interrupt i.e. no interrupt is generated + 0x1 - PIN6 - Set as input pin 6 + MEM_TO_DIN_MASK + The memory to DIN DMA done interrupt mask. 6 6 - read - - Input - Read: pin set as input - 0 - - Output - Read: pin set as output - 1 + IRQEnable + Do not mask memory to DIN DMA done interrupt i.e. interrupt is generated + 0x0 - - - write - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + IRQDisable + Mask memory to DIN DMA done interrupt i.e. no interrupt is generated + 0x1 - PIN7 - Set as input pin 7 + DOUT_TO_MEM_MASK + The DOUT to memory DMA done interrupt mask. 7 7 - read - - Input - Read: pin set as input - 0 - - Output - Read: pin set as output - 1 + IRQEnable + Do not mask DOUT to memory DMA done interrupt i.e. interrupt is generated + 0x0 - - - write - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + IRQDisable + Mask DOUT to memory DMA done interrupt i.e. no interrupt is generated + 0x1 - PIN8 - Set as input pin 8 + AHB_ERR_MASK + The AHB error interrupt mask. 8 8 - read - - Input - Read: pin set as input - 0 - - Output - Read: pin set as output - 1 + IRQEnable + Do not mask AHB error interrupt i.e. interrupt is generated + 0x0 - - - write - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + IRQDisable + Mask AHB error interrupt i.e. no interrupt is generated + 0x1 - PIN9 - Set as input pin 9 + PKA_MASK + The PKA end of operation interrupt mask. 9 9 - read - Input - Read: pin set as input - 0 + IRQEnable + Do not mask PKA end of operation interrupt i.e. interrupt is generated + 0x0 - Output - Read: pin set as output - 1 + IRQDisable + Mask PKA end of operation interrupt i.e. no interrupt is generated + 0x1 + + + RNG_MASK + The RNG interrupt mask. + 10 + 10 - write - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + IRQEnable + Do not mask RNG interrupt i.e. interrupt is generated + 0x0 + + + IRQDisable + Mask RNG interrupt i.e. no interrupt is generated + 0x1 + + + + ICR + Interrupt clear register. Writing a 1 bit into a field in this register will clear the corresponding bit in IRR. + 0xA08 + write-only + 0x00000000 + 0x20 + - PIN10 - Set as input pin 10 + SRAM_TO_DIN_CLEAR + The RNG SRAM to DIN DMA done interrupt clear. + 4 + 4 + + + DOUT_TO_SRAM_CLEAR + The DOUT to RNG SRAM DMA done interrupt clear. + 5 + 5 + + + MEM_TO_DIN_CLEAR + The memory to DIN DMA done interrupt clear. + 6 + 6 + + + DOUT_TO_MEM_CLEAR + The DOUT to memory DMA done interrupt clear. + 7 + 7 + + + AHB_ERR_CLEAR + The AHB error interrupt clear. + 8 + 8 + + + PKA_CLEAR + The PKA end of operation interrupt clear. + 9 + 9 + + + RNG_CLEAR + The RNG interrupt clear. Register RNG_ISR in the RNG engine must be cleared before this interrupt can be cleared. 10 10 + + + + + ENDIANNESS + This register defines the endianness of the Host-accessible registers, and can only be written once. + 0xA0C + read-write + 0x00000000 + 0x20 + + + DOUT_WR_BG + DOUT write endianness. + 3 + 3 - read - Input - Read: pin set as input - 0 + LittleEndian + Configure DOUT write as little-endian + 0x0 - Output - Read: pin set as output - 1 + BigEndian + Configure DOUT write as big-endian + 0x1 + + + DIN_RD_BG + DIN read endianness. + 7 + 7 - write - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + LittleEndian + Configure DIN read as little-endian + 0x0 + + + BigEndian + Configure DIN read as big-endian + 0x1 - PIN11 - Set as input pin 11 + DOUT_WR_WBG + DOUT write word endianness. 11 11 - read - - Input - Read: pin set as input - 0 - - Output - Read: pin set as output - 1 + LittleEndian + Configure DOUT write word as little-endian + 0x0 - - - write - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + BigEndian + Configure DOUT write word as big-endian + 0x1 - PIN12 - Set as input pin 12 - 12 - 12 + DIN_RD_WBG + DIN read word endianness. + 15 + 15 - read - - Input - Read: pin set as input - 0 - - Output - Read: pin set as output - 1 + LittleEndian + Configure DIN read word as little-endian + 0x0 - - - write - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + BigEndian + Configure DIN read word as big-endian + 0x1 + + + + HOST_SIGNATURE + This register holds the CRYPTOCELL subsystem signature. See reset value. + 0xA24 + read-only + 0x20E00000 + 0x20 + + + VALUE + Fixed-value identification signature used by host driver to verify CRYPTOCELL presence at this address. + 0 + 31 + + + + + HOST_BOOT + Hardware configuration of the CRYPTOCELL subsystem. Reset value holds the supported features. + 0xA28 + read-only + 0x4622982C + 0x20 + - PIN13 - Set as input pin 13 + POWER_GATING_EXISTS_LOCAL + If this flag is set, full power gating is implemented + 0 + 0 + + + LARGE_RKEK_LOCAL + If this flag is set, large RKEK is supported + 1 + 1 + + + HASH_IN_FUSES_LOCAL + If this flag is set, HASH in fuses is supported + 2 + 2 + + + EXT_MEM_SECURED_LOCAL + If this flag is set, external secure memory is supported + 3 + 3 + + + RKEK_ECC_EXISTS_LOCAL_N + If this flag is set, RKEK ECC is supported + 5 + 5 + + + SRAM_SIZE_LOCAL + SRAM size + 6 + 8 + + + DSCRPTR_EXISTS_LOCAL + If this flag is set, Descriptors are supported + 9 + 9 + + + PAU_EXISTS_LOCAL + If this flag is set, PAU is supported + 10 + 10 + + + RNG_EXISTS_LOCAL + If this flag is set, the RNG engine is present + 11 + 11 + + + PKA_EXISTS_LOCAL + If this flag is set, the PKA engine is present + 12 + 12 + + + RC4_EXISTS_LOCAL + If this flag is set, the RC4 engine is present 13 13 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - PIN14 - Set as input pin 14 + SHA_512_PRSNT_LOCAL + If this flag is set, the HASH engine supports SHA512 14 14 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - PIN15 - Set as input pin 15 + SHA_256_PRSNT_LOCAL + If this flag is set, the HASH engine supports SHA256 15 15 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - PIN16 - Set as input pin 16 - 16 - 16 + MD5_PRSNT_LOCAL + If this flag is set, the HASH engine supports MD5 + 16 + 16 + + + HASH_EXISTS_LOCAL + If this flag is set, the HASH engine is present + 17 + 17 + + + C2_EXISTS_LOCAL + If this flag is set, the C2 engine is present + 18 + 18 + + + DES_EXISTS_LOCAL + If this flag is set, the DES engine is present + 19 + 19 + + + AES_XCBC_MAC_EXISTS_LOCAL + If this flag is set, AES XCBC-MAC mode is supported + 20 + 20 + + + AES_CMAC_EXISTS_LOCAL + If this flag is set, AES CMAC mode is supported + 21 + 21 + + + AES_CCM_EXISTS_LOCAL + If this flag is set, AES CCM mode is supported + 22 + 22 + + + AES_XEX_HW_T_CALC_LOCAL + If this flag is set, AES XEX mode T-value calculation in HW is supported + 23 + 23 + + + AES_XEX_EXISTS_LOCAL + If this flag is set, AES XEX mode is supported + 24 + 24 + + + CTR_EXISTS_LOCAL + If this flag is set, AES CTR mode is supported + 25 + 25 + + + AES_DIN_BYTE_RESOLUTION_LOCAL + If this flag is set, the AES engine data input support byte size resolution + 26 + 26 + + + TUNNELING_ENB_LOCAL + If this flag is set, the AES engine supports tunneling operations + 27 + 27 + + + SUPPORT_256_192_KEY_LOCAL + If this flag is set, the AES engine supports 192/256 bits key sizes + 28 + 28 + + + ONLY_ENCRYPT_LOCAL + If this flag is set, the AES engine only support encryption + 29 + 29 + + + AES_EXISTS_LOCAL + If this flag is set, the AES engine is present + 30 + 30 + + + + + HOST_CRYPTOKEY_SEL + AES hardware key select. + 0xA38 + read-write + 0x00000000 + 0x20 + + + HOST_CRYPTOKEY_SEL + Select the source of the HW key that is used by the AES engine + 0 + 1 - read - Input - Read: pin set as input - 0 + K_DR + Use device root key K_DR from CRYPTOCELL AO power domain + 0x0 - Output - Read: pin set as output - 1 + K_PRTL + Use hard-coded RTL key K_PRTL + 0x1 - - - write - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + Session + Use provided session key + 0x2 + + + + HOST_IOT_KPRTL_LOCK + This write-once register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. + 0xA4C + read-writeOnce + 0x00000000 + 0x20 + - PIN17 - Set as input pin 17 - 17 - 17 + HOST_IOT_KPRTL_LOCK + This register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. + 0 + 0 - read - - Input - Read: pin set as input - 0 - - Output - Read: pin set as output - 1 + Disabled + K_PRTL can be selected for use from register HOST_CRYPTOKEY_SEL + 0x0 - - - write - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + Enabled + K_PRTL has been locked until next power-on reset (POR). If K_PRTL is selected anyway, a zeroed key will be used instead. + 0x1 + + + + HOST_IOT_KDR0 + This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained. + 0xA50 + read-writeOnce + 0x00000000 + 0x20 + - PIN18 - Set as input pin 18 - 18 - 18 + HOST_IOT_KDR0 + This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained. Write: K_DR bits 31:0. + 0 + 31 - read - - Input - Read: pin set as input - 0 - - Output - Read: pin set as output - 1 + NotRetained + Read: 128 bits K_DR key value is not yet retained in the CRYPTOCELL AO power domain. + 0x00000000 - - - write - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + Retained + Read: 128 bits K_DR key value is successfully retained in the CRYPTOCELL AO power domain. + 0x00000001 + + + + HOST_IOT_KDR1 + This register holds bits 63:32 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. + 0xA54 + writeOnce + 0x00000000 + 0x20 + - PIN19 - Set as input pin 19 - 19 - 19 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - + HOST_IOT_KDR1 + K_DR bits 63:32 + 0 + 31 + + + + HOST_IOT_KDR2 + This register holds bits 95:64 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. + 0xA58 + writeOnce + 0x00000000 + 0x20 + - PIN20 - Set as input pin 20 - 20 - 20 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - + HOST_IOT_KDR2 + K_DR bits 95:64 + 0 + 31 + + + + HOST_IOT_KDR3 + This register holds bits 127:96 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. + 0xA5C + writeOnce + 0x00000000 + 0x20 + - PIN21 - Set as input pin 21 - 21 - 21 + HOST_IOT_KDR3 + K_DR bits 127:96 + 0 + 31 + + + + + HOST_IOT_LCS + Controls life-cycle state (LCS) for CRYPTOCELL subsystem + 0xA60 + read-write + 0x00000002 + 0x20 + + + LCS + Life-cycle state value. This field is write-once per reset. + 0 + 2 + read-writeOnce - read - - Input - Read: pin set as input - 0 - - Output - Read: pin set as output - 1 + DebugEnable + CC310 operates in debug mode + 0x0 - - - write - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + Secure + CC310 operates in secure mode + 0x2 - PIN22 - Set as input pin 22 - 22 - 22 + LCS_IS_VALID + Read-only field. Indicates if CRYPTOCELL LCS has been successfully configured since last reset. + 8 + 8 + read-only - read - - Input - Read: pin set as input - 0 - - Output - Read: pin set as output - 1 + Invalid + Valid LCS not yet retained in the CRYPTOCELL AO power domain + 0x0 - - - write - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + Valid + Valid LCS successfully retained in the CRYPTOCELL AO power domain + 0x1 + + + + + + CC_MISC + CRYPTOCELL MISC interface + 0x5002B000 + CC_AES + + 0 + 0x1000 + registers + + CC_MISC + 0x20 + + + AES_CLK + Clock control for the AES engine. + 0x810 + write-only + 0x00000000 + 0x20 + - PIN23 - Set as input pin 23 - 23 - 23 + ENABLE + Enables clock for the AES engine. + 0 + 0 - read - - Input - Read: pin set as input - 0 - - Output - Read: pin set as output - 1 + Disable + Disable clock for the AES engine. + 0x0 - - - write - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + Enable + Enable clock for the AES engine. + 0x1 + + + + HASH_CLK + Clock control for the HASH engine. + 0x818 + write-only + 0x00000000 + 0x20 + - PIN24 - Set as input pin 24 - 24 - 24 + ENABLE + Enables clock for the HASH engine. + 0 + 0 - read - - Input - Read: pin set as input - 0 - - Output - Read: pin set as output - 1 + Disable + Disable clock for the HASH engine. + 0x0 - - - write - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + Enable + Enable clock for the HASH engine. + 0x1 + + + + PKA_CLK + Clock control for the PKA engine. + 0x81C + write-only + 0x00000000 + 0x20 + - PIN25 - Set as input pin 25 - 25 - 25 + ENABLE + Enables clock for the PKA engine. + 0 + 0 - read - - Input - Read: pin set as input - 0 - - Output - Read: pin set as output - 1 + Disable + Disable clock for the PKA engine. + 0x0 - - - write - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + Enable + Enable clock for the PKA engine. + 0x1 + + + + DMA_CLK + Clock control for the DMA engines. + 0x820 + write-only + 0x00000000 + 0x20 + - PIN26 - Set as input pin 26 - 26 - 26 + ENABLE + Enables clock for the DMA engines. + 0 + 0 - read - - Input - Read: pin set as input - 0 - - Output - Read: pin set as output - 1 + Disable + Disable clock for the DMA engines. + 0x0 - - - write - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + Enable + Enable clock for the DMA engines. + 0x1 + + + + CLK_STATUS + CRYPTOCELL clocks status register. + 0x824 + read-only + 0x00000100 + 0x20 + - PIN27 - Set as input pin 27 - 27 - 27 + AES_CLK + Status of AES engine clock. + 0 + 0 - read - - Input - Read: pin set as input - 0 - - Output - Read: pin set as output - 1 + Disabled + Clock for AES engine is disabled + 0x0 - - - write - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + Enabled + Clock for AES engine is enabled + 0x1 - PIN28 - Set as input pin 28 - 28 - 28 + HASH_CLK + Status of HASH engine clock. + 2 + 2 - read - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 + Disabled + Clock for HASH engine is disabled + 0x0 - - - write - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + Enabled + Clock for HASH engine is enabled + 0x1 - PIN29 - Set as input pin 29 - 29 - 29 + PKA_CLK + Status of PKA engine clock. + 3 + 3 - read - - Input - Read: pin set as input - 0 - - Output - Read: pin set as output - 1 + Disabled + Clock for PKA engine is disabled + 0x0 - - - write - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + Enabled + Clock for PKA engine is enabled + 0x1 - PIN30 - Set as input pin 30 - 30 - 30 + CHACHA_CLK + Status of CHACHA engine clock. + 7 + 7 - read - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 + Disabled + Clock for CHACHA engine is disabled + 0x0 - - - write - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + Enabled + Clock for CHACHA engine is enabled + 0x1 - PIN31 - Set as input pin 31 - 31 - 31 + DMA_CLK + Status of DMA engines clock. + 8 + 8 - read - - Input - Read: pin set as input - 0 - - Output - Read: pin set as output - 1 + Disabled + Clocks for DMA engines are disabled + 0x0 - - - write - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + Enabled + Clocks for DMA engines are enabled + 0x1 - LATCH - Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers - 0x520 - read-write + CHACHA_CLK + Clock control for the CHACHA engine. + 0x858 + write-only + 0x00000000 + 0x20 - PIN0 - Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. + ENABLE + Enables clock for the CHACHA engine. 0 0 - NotLatched - Criteria has not been met - 0 + Disable + Disable clock for the CHACHA engine. + 0x0 - Latched - Criteria has been met - 1 + Enable + Enable clock for the CHACHA engine. + 0x1 + + + + + + CC_PKA + CRYPTOCELL PKA engine + 0x5002B000 + CC_AES + + 0 + 0x1000 + registers + + CC_PKA + 0x20 + + + 0x20 + 0x4 + MEMORY_MAP[%s] + Description collection: Register for mapping the virtual register R[n] to a physical address in the PKA SRAM. + 0x0 + read-write + 0x00000000 + 0x20 + - PIN1 - Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. + ADDR + The physical word address used for the virtual register. 1 - 1 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - + 9 + + + + OPCODE + Operation code to be executed by the PKA engine. Writing to this register triggers the PKA operation. + 0x80 + read-write + 0x00000000 + 0x20 + - PIN2 - Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. - 2 - 2 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - + TAG + Holds the operation tag or the operand C virtual register index. + 0 + 5 - PIN3 - Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. - 3 - 3 + REG_R + Result register virtual register index. + 6 + 10 + + + DISCARD_R + This field controls the interpretation of REG_R. + 11 + 11 - NotLatched - Criteria has not been met - 0 + Register + REG_R is intepreted as a register index. + 0x0 - Latched - Criteria has been met - 1 + Discard + Result is discarded. + 0x1 - PIN4 - Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. - 4 - 4 + REG_B + Operand B virtual register index. + 12 + 16 + + + CONST_B + This field controls the interpretation of REG_B. + 17 + 17 - NotLatched - Criteria has not been met - 0 + Register + REG_B is intepreted as a register index. + 0x0 - Latched - Criteria has been met - 1 + Constant + REG_B is intepreted as a constant. + 0x1 - PIN5 - Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. - 5 - 5 + REG_A + Operand A virtual register index. + 18 + 22 + + + CONST_A + This field controls the interpretation of REG_A. + 23 + 23 - NotLatched - Criteria has not been met - 0 + Register + REG_A is intepreted as a register index. + 0x0 - Latched - Criteria has been met - 1 + Constant + REG_A is intepreted as a constant. + 0x1 - PIN6 - Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. - 6 - 6 + LEN + The length of the operands. This value serves as an PKA length register index. E.g.: if LEN field value is set to 0, PKA_L[0] holds the size of the operands. + 24 + 26 + + + OPCODE + Operation code to be executed by the PKA engine + 27 + 31 - NotLatched - Criteria has not been met - 0 + Terminate + Terminate operation + 0x00 - Latched - Criteria has been met - 1 + AddInc + Add or Increment + 0x04 - - - - PIN7 - Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. - 7 - 7 - - NotLatched - Criteria has not been met - 0 + SubDecNeg + Subtract, Decrement, or Negate + 0x05 - Latched - Criteria has been met - 1 + ModAddInc + Modular Add or Modular Increment + 0x06 - - - - PIN8 - Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. - 8 - 8 - - NotLatched - Criteria has not been met - 0 + ModSubDecNeg + Modular Subtract, Modular Decrement, or Modular Negate + 0x07 - Latched - Criteria has been met - 1 + ANDTST0CLR0 + Perform AND, test, or clear + 0x08 - - - - PIN9 - Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. - 9 - 9 - - NotLatched - Criteria has not been met - 0 + ORCOPYSET0 + Perform OR, copy, or set bits + 0x09 - Latched - Criteria has been met - 1 + XORFLP0INVCMP + Perform XOR, flip bits, invert, or compare + 0x0A - - - - PIN10 - Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. - 10 - 10 - - NotLatched - Criteria has not been met - 0 + SHR0 + Shift right 0 operation + 0x0C - Latched - Criteria has been met - 1 + SHR1 + Shift right 1 operation + 0x0D - - - - PIN11 - Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. - 11 - 11 - - NotLatched - Criteria has not been met - 0 + SHL0 + Shift left 0 operation + 0x0E - Latched - Criteria has been met - 1 + SHL1 + Shift left 1 operation + 0x0F - - - - PIN12 - Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. - 12 - 12 - - NotLatched - Criteria has not been met - 0 + MulLow + Multiply low operation + 0x10 - Latched - Criteria has been met - 1 + ModMul + Modular multiply operation + 0x11 - - - - PIN13 - Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. - 13 - 13 - - NotLatched - Criteria has not been met - 0 + ModMulN + Modular multiply N operation + 0x12 - Latched - Criteria has been met - 1 + ModExp + Modular exponentiation operation + 0x13 + + + Division + Division operation + 0x14 + + + ModInv + Modular inversion operation + 0x15 + + + ModDiv + Modular division operation + 0x16 + + + MulHigh + Multiply high operation + 0x17 + + + ModMLAC + Modular multiplication acceleration + 0x18 + + + ModMLACNR + Modular multiplication acceleration where final reduction is omitted + 0x19 + + + Reduction + Reduction operation + 0x1B + + + + N_NP_T0_T1_ADDR + This register defines the N, Np, T0, and T1 virtual register index. + 0x84 + read-write + 0x000FF820 + 0x20 + - PIN14 - Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. + N_VIRTUAL_ADDR + Register N virtual register index. Default is R0. + 0 + 4 + + + NP_VIRTUAL_ADDR + Register Np virtual register index. Default is R1. + 5 + 9 + + + T0_VIRTUAL_ADDR + Temporary register 0 virtual register index. Default is R30. + 10 + 14 + + + T1_VIRTUAL_ADDR + Temporary register 1 virtual register index. Default is R31. + 15 + 19 + + + + + PKA_STATUS + This register holds the status for the PKA pipeline. + 0x88 + read-only + 0x00001000 + 0x20 + + + ALU_MSB_4BITS + The most significant 4-bits of the operand updated in shift operation. + 0 + 3 + + + ALU_LSB_4BITS + The least significant 4-bits of the operand updated in shift operation. + 4 + 7 + + + ALU_SIGN_OUT + Indicates the MSB sign of the last operation. + 8 + 8 + + + ALU_CARRY + Holds the carry of the last ALU operation. + 9 + 9 + + + ALU_CARRY_MOD + Holds the carry of the last modular operation. + 10 + 10 + + + ALU_SUB_IS_ZERO + Indicates the last subtraction operation sign. + 11 + 11 + + + ALU_OUT_ZERO + Indicates if the result of ALU OUT is zero. + 12 + 12 + + + ALU_MODOVRFLW + Modular overflow flag. + 13 + 13 + + + DIV_BY_ZERO + Indication if the division is done by zero. 14 14 + + + MODINV_OF_ZERO + Indicates the modular inverse of zero. + 15 + 15 + + + OPCODE + Opcode of the last operation + 16 + 20 + + + + + PKA_SW_RESET + Reset the PKA engine. + 0x8C + write-only + 0x00000000 + 0x20 + + + RESET + Writing any value to this address resets the PKA engine. The reset takes 4 CPU clock cycles to complete. + 0 + 0 - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 + Enable + Reset PKA engine. + 0x1 + + + + 0x8 + 0x4 + PKA_L[%s] + Description collection: This register holds the operands bit size. + 0x90 + read-write + 0x00000000 + 0x20 + - PIN15 - Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. - 15 - 15 + OpSize + Operand bit size. + 0 + 12 + + + + + PKA_PIPE + Status register indicating if the PKA pipeline is ready to receive a new OPCODE. + 0xB0 + read-only + 0x00000001 + 0x20 + + + STATUS + PKA pipeline status. + 0 + 0 - NotLatched - Criteria has not been met - 0 + NotReady + PKA pipeline is not ready for a new OPCODE + 0x0 - Latched - Criteria has been met - 1 + Ready + PKA pipeline is ready for a new OPCODE + 0x1 + + + + PKA_DONE + Status register indicating if the PKA operation has been completed. + 0xB4 + read-only + 0x00000001 + 0x20 + - PIN16 - Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. - 16 - 16 + STATUS + PKA operation status. + 0 + 0 - NotLatched - Criteria has not been met - 0 + Processing + PKA operation is processing + 0x0 - Latched - Criteria has been met - 1 + Completed + PKA operation is completed and pipeline is empty + 0x1 + + + + PKA_VERSION + PKA engine HW version. Reset value holds the version. + 0xC4 + read-only + 0x16110215 + 0x20 + - PIN17 - Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. - 17 - 17 + PKA_VERSION + 0 + 31 + + + + + PKA_SRAM_WADDR + Start address in PKA SRAM for subsequent write transactions. + 0xD4 + write-only + 0x00000000 + 0x20 + + + ADDR + PKA SRAM start address for write transaction + 0 + 31 + + + + + PKA_SRAM_WDATA + Write data to PKA SRAM. Writing to this register triggers a DMA transaction writing data into PKA SRAM. The DMA address offset is automatically incremented during write. + 0xD8 + write-only + 0x00000000 + 0x20 + + + DATA + Data to write to PKA SRAM. + 0 + 31 + + + + + PKA_SRAM_RDATA + Read data from PKA SRAM. Reading from this register triggers a DMA transaction read data from PKA SRAM. The DMA address offset is automatically incremented during read. + 0xDC + read-only + 0x00000000 + 0x20 + + + DATA + Data to read from PKA SRAM + 0 + 31 + + + + + PKA_SRAM_WCLEAR + Register for clearing PKA SRAM write buffer. + 0xE0 + write-only + 0x00000000 + 0x20 + + + CLEAR + Clear the PKA SRAM write buffer. + 0 + 31 + + + + + PKA_SRAM_RADDR + Start address in PKA SRAM for subsequent read transactions. + 0xE4 + write-only + 0x00000000 + 0x20 + + + ADDR + PKA SRAM start address for read transaction + 0 + 31 + + + + + + + CC_RNG + CRYPTOCELL RNG engine + 0x5002B000 + CC_AES + + 0 + 0x1000 + registers + + CC_RNG + 0x20 + + + RNG_IMR + Interrupt mask register. Each bit of this register holds the mask of a single interrupt source. + 0x100 + read-write + 0x0000003F + 0x20 + + + EHR_VALID_MASK + See RNG_ISR for explanation on this interrupt. + 0 + 0 - NotLatched - Criteria has not been met - 0 + IRQEnable + Do not mask EHR interrupt i.e. interrupt is generated + 0x0 - Latched - Criteria has been met - 1 + IRQDisable + Mask EHR interrupt i.e. no interrupt is generated + 0x1 - PIN18 - Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. - 18 - 18 + AUTOCORR_ERR_MASK + See RNG_ISR for explanation on this interrupt. + 1 + 1 - NotLatched - Criteria has not been met - 0 + IRQEnable + Do not mask autocorrelation interrupt i.e. interrupt is generated + 0x0 - Latched - Criteria has been met - 1 + IRQDisable + Mask autocorrelation interrupt i.e. no interrupt is generated + 0x1 - PIN19 - Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. - 19 - 19 + CRNGT_ERR_MASK + See RNG_ISR for explanation on this interrupt. + 2 + 2 - NotLatched - Criteria has not been met - 0 + IRQEnable + Do not mask the CRNGT error interrupt i.e. interrupt is generated + 0x0 - Latched - Criteria has been met - 1 + IRQDisable + Mask the CRNGT error interrupt i.e. no interrupt is generated + 0x1 - PIN20 - Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. - 20 - 20 + VNC_ERR_MASK + See RNG_ISR for explanation on this interrupt. + 3 + 3 - NotLatched - Criteria has not been met - 0 + IRQEnable + Do not mask the von Neumann corrector error interrupt i.e. interrupt is generated + 0x0 - Latched - Criteria has been met - 1 + IRQDisable + Mask the von Neumann corrector error interrupt i.e. no interrupt is generated + 0x1 - PIN21 - Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. - 21 - 21 + WATCHDOG_MASK + See RNG_ISR for explanation on this interrupt. + 4 + 4 - NotLatched - Criteria has not been met - 0 + IRQEnable + Do not mask the watchdog interrupt i.e. interrupt is generated + 0x0 - Latched - Criteria has been met - 1 + IRQDisable + Mask the watchdog interrupt i.e. no interrupt is generated + 0x1 - PIN22 - Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. - 22 - 22 + DMA_DONE_MASK + See RNG_ISR for explanation on this interrupt. + 5 + 5 - NotLatched - Criteria has not been met - 0 + IRQEnable + Do not mask the RNG DMA completion interrupt i.e. interrupt is generated + 0x0 - Latched - Criteria has been met - 1 + IRQDisable + Mask the RNG DMA completion interrupt i.e. no interrupt is generated + 0x1 + + + + RNG_ISR + Interrupt status register. Each bit of this register holds the interrupt + status of a single interrupt source. If corresponding RNG_IMR bit is + unmasked, an interrupt is generated. + 0x104 + read-only + 0x00000000 + 0x20 + + + EHR_VALID_INT + 192-bits have been collected and are ready to be read. + 0 + 0 + - PIN23 - Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. - 23 - 23 + AUTOCORR_ERR_INT + Autocorrelation error. Failure occurs when autocorrelation test has failed four times in a row. Once set, the TRNG ceases to function until next reset. + 1 + 1 + + + CRNGT_ERR_INT + Continuous random number generator test error. Failure occurs when two consecutive blocks of 16 collected bits are equal. + 2 + 2 + + + VNC_ERR_INT + von Neumann corrector error. Failure occurs if 32 consecutive collected bits are identical, ZERO, or ONE. + 3 + 3 + + + WATCHDOG_INT + Maximum number of CPU clock cycles per sample have been exceeded. See RNG_WATCHDOG_VAL for more information. + 4 + 4 + + + DMA_DONE_INT + RNG DMA to SRAM is completed. + 5 + 5 + + + + + RNG_ICR + Interrupt clear register. Writing a 1 bit into a field in this register + will clear the corresponding bit in RNG_ISR. + 0x108 + write-only + 0x00000000 + 0x20 + + + EHR_VALID_CLEAR + Writing value '1' clears corresponding bit in RNG_ISR + 0 + 0 + + + AUTOCORR_ERR_CLEAR + Cannot be cleared by software! Only RNG reset clears this bit. + 1 + 1 + + + CRNGT_ERR_CLEAR + Writing value '1' clears corresponding bit in RNG_ISR + 2 + 2 + + + VNC_ERR_CLEAR + Writing value '1' clears corresponding bit in RNG_ISR + 3 + 3 + + + WATCHDOG_CLEAR + Writing value '1' clears corresponding bit in RNG_ISR + 4 + 4 + + + DMA_DONE_CLEAR + Writing value '1' clears corresponding bit in RNG_ISR + 5 + 5 + + + + + TRNG_CONFIG + TRNG ring oscillator length configuration + 0x10C + read-write + 0x00000000 + 0x20 + + + ROSC_LEN + Set the length of the oscillator ring (= the number of inverters) out of four possible configurations. + 0 + 1 - NotLatched - Criteria has not been met - 0 + ROSC1 + Use shortest ROSC1 ring oscillator configuration. + 0x0 + + + ROSC2 + Use ROSC2 ring oscillator configuration. + 0x1 + + + ROSC3 + Use ROSC3 ring oscillator configuration. + 0x2 - Latched - Criteria has been met - 1 + ROSC4 + Use longest ROSC4 ring oscillator configuration. + 0x3 + + + + TRNG_VALID + This register indicates if TRNG entropy collection is valid. + 0x110 + read-only + 0x00000000 + 0x20 + - PIN24 - Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. - 24 - 24 + EHR_DATA + A value of 1 indicates that collection of bits in the TRNG is completed, and data can be read from EHR_DATA registers. + 0 + 0 - NotLatched - Criteria has not been met - 0 + NotValid + Collection of bits not valid. + 0x0 - Latched - Criteria has been met - 1 + Valid + Collection of bits valid. + 0x1 + + + + 0x6 + 0x4 + EHR_DATA[%s] + Description collection: The entropy holding registers (EHR) hold 192-bits random data collected by the TRNG. The initial EHR_DATA[0] register holds the least significant bits [31:0] of the random data value. + 0x114 + read-only + 0x00000000 + 0x20 + + + VALUE + Random data value. + 0 + 31 + + + + + NOISE_SOURCE + This register controls the ring oscillator circuit used as a noise source. + 0x12C + read-write + 0x00000000 + 0x20 + - PIN25 - Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. - 25 - 25 + ENABLE + Enable or disable the noise source. + 0 + 0 - NotLatched - Criteria has not been met - 0 + Disabled + Noise source is disabled + 0x0 - Latched - Criteria has been met - 1 + Enabled + Noise source is enabled + 0x1 + + + + SAMPLE_CNT + Sample count defining the number of CPU clock cycles between two consecutive noise source samples. + 0x130 + read-write + 0x0000FFFF + 0x20 + + + VALUE + Number of CPU clock cycles between two consecutive noise source samples. + 0 + 31 + + + + + AUTOCORR_STATISTIC + Statistics counter for autocorrelation test activations. Statistics collection is stopped if one of the counters reach its limit of all ones. + 0x134 + read-write + 0x00000000 + 0x20 + - PIN26 - Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. - 26 - 26 + AUTOCORR_TRYS + Count each time an autocorrelation test starts. Any write to the field resets the counter. + 0 + 13 + + + AUTOCORR_FAILS + Count each time an autocorrelation test fails. Any write to the field resets the counter. + 14 + 21 + + + + + TRNG_DEBUG + Debug register for the TRNG. This register is used to bypass TRNG tests in hardware. + 0x138 + read-write + 0x00000000 + 0x20 + + + VNC_BYPASS + Bypass the von Neumann corrector post-processing test, including the 32 consecutive bits test. + 1 + 1 - NotLatched - Criteria has not been met - 0 + Disabled + von Neumann corrector post-processing is active + 0x0 - Latched - Criteria has been met - 1 + Enabled + Bypass the von Neumann corrector + 0x1 - PIN27 - Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. - 27 - 27 + CRNGT_BYPASS + Bypass the Continuous Random Number Generator Test (CRNGT). + 2 + 2 - NotLatched - Criteria has not been met - 0 + Disabled + CRNGT is active + 0x0 - Latched - Criteria has been met - 1 + Enabled + Bypass CRNGT + 0x1 - PIN28 - Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. - 28 - 28 + AUTOCORR_BYPASS + Bypass the autocorrelation test. + 3 + 3 - NotLatched - Criteria has not been met - 0 + Disabled + Autocorrelation test is active + 0x0 - Latched - Criteria has been met - 1 + Enabled + Bypass the autocorrelation test + 0x1 + + + + RNG_SW_RESET + Reset the RNG engine. + 0x140 + write-only + 0x00000000 + 0x20 + - PIN29 - Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. - 29 - 29 + RESET + Writing any value to this address resets the RNG engine. The reset takes 4 CPU clock cycles to complete. + 0 + 0 - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 + Enable + Reset RNG engine. + 0x1 + + + + RNG_BUSY + Status register for RNG engine activity. + 0x1B8 + read-only + 0x00000000 + 0x20 + - PIN30 - Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. - 30 - 30 + STATUS + RNG engine status. + 0 + 0 - NotLatched - Criteria has not been met - 0 + Idle + RNG engine is idle + 0x0 - Latched - Criteria has been met - 1 + Busy + RNG engine is busy + 0x1 - PIN31 - Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. - 31 - 31 + TRNG_STATUS + TRNG status. + 1 + 1 - NotLatched - Criteria has not been met - 0 + Idle + TRNG is idle + 0x0 - Latched - Criteria has been met - 1 + Busy + TRNG is busy + 0x1 - DETECTMODE - Select between default DETECT signal behaviour and LDETECT mode - 0x524 - read-write + TRNG_RESET + Reset the TRNG, including internal counter of collected bits and registers EHR_DATA and TRNG_VALID. + 0x1BC + write-only + 0x00000000 + 0x20 - DETECTMODE - Select between default DETECT signal behaviour and LDETECT mode + RESET + Writing any value to this address resets the internal bits counter and registers EHR_DATA and TRNG_VALID. Register NOISE_SOURCE must be disabled in order for the reset to take place. 0 0 - Default - DETECT directly connected to PIN DETECT signals - 0 - - - LDETECT - Use the latched LDETECT behaviour - 1 + Enable + Reset TRNG. + 0x1 - 32 - 0x4 - PIN_CNF[%s] - Description collection[n]: Configuration of GPIO pins - 0x700 - read-write - 0x00000002 + RNG_HW_FLAGS + Hardware configuration of RNG engine. Reset value holds the supported features. + 0x1C0 + read-only + 0x0000000F + 0x20 - DIR - Pin direction. Same physical register as DIR register + EHR_WIDTH + Data width supported by the entropy collector 0 0 - Input - Configure pin as an input pin - 0 + 128Bits + 128 bits EHR width + 0x0 - Output - Configure pin as an output pin - 1 + 192Bits + 192 bits EHR width + 0x1 - INPUT - Connect or disconnect input buffer + CRNGT_EXISTS + If this flag is set, the engine include support for continuous random number generator test. 1 1 - - - Connect - Connect input buffer - 0 - - - Disconnect - Disconnect input buffer - 1 - - - PULL - Pull configuration + AUTOCORR_EXISTS + If this flag is set, the engine include support for autocorrelation test. 2 + 2 + + + BYPASS_EXISTS + If this flag is set, the engine include support for bypassing TRNG tests. + 3 3 + + + PRNG_EXISTS + If this flag is set, the engine include a pseudo-random number generator. + 4 + 4 + + + KAT_EXISTS + If this flag is set, the engine include support for known answer tests. + 5 + 5 + + + RESEEDING_EXISTS + If this flag is set, the engine include support for automatic reseeding. + 6 + 6 + + + RNG_USE_5_SBOXES + 7 + 7 - Disabled - No pull - 0 - - - Pulldown - Pull down on pin - 1 + Disable + 20 SBOX AES + 0x0 - Pullup - Pull up on pin - 3 + Enable + 5 SBOX AES + 0x1 + + + + RNG_CLK + Control clock for the RNG engine. + 0x1C4 + write-only + 0x00000000 + 0x20 + - DRIVE - Drive configuration - 8 - 10 + ENABLE + Enables clock for the RNG engine. + 0 + 0 - S0S1 - Standard '0', standard '1' - 0 - - - H0S1 - High drive '0', standard '1' - 1 - - - S0H1 - Standard '0', high drive '1' - 2 - - - H0H1 - High drive '0', high 'drive '1'' - 3 - - - D0S1 - Disconnect '0' standard '1' (normally used for wired-or connections) - 4 - - - D0H1 - Disconnect '0', high drive '1' (normally used for wired-or connections) - 5 - - - S0D1 - Standard '0'. disconnect '1' (normally used for wired-and connections) - 6 + Disable + Disable clock for RNG engine. + 0x0 - H0D1 - High drive '0', disconnect '1' (normally used for wired-and connections) - 7 + Enable + Enable clock for RNG engine. + 0x1 + + + + RNG_DMA + Writing to this register enables the RNG DMA engine. + 0x1C8 + read-write + 0x00000000 + 0x20 + - SENSE - Pin sensing mechanism - 16 - 17 + ENABLE + 0 + 0 - Disabled - Disabled - 0 - - - High - Sense for high level - 2 + Disable + Disable RNG DMA engine + 0x0 - Low - Sense for low level - 3 + Enable + Enable RNG DMA engine This value is cleared when the RNG DMA engine completes its operation. + 0x1 - - - - P1 - GPIO Port 2 - 0x50000300 - P0 - - - CC_HOST_RGF - CRYPTOCELL HOST_RGF interface - 0x5002A000 - - 0 - 0x2000 - registers - - CC_HOST_RGF - 0x20 - - HOST_CRYPTOKEY_SEL - AES hardware key select - 0x1A38 + RNG_DMA_ROSC_LEN + This register defines which ring oscillator length configuration should be used when using the RNG DMA engine. + 0x1CC read-write 0x00000000 + 0x20 - HOST_CRYPTOKEY_SEL - Select the source of the HW key that is used by the AES engine + ROSC1 + Use shortest ROSC1 ring oscillator configuration. 0 + 0 + + + Disable + Disable ROSC1 + 0x0 + + + Enable + Enable ROSC1 + 0x1 + + + + + ROSC2 + Use ROSC2 ring oscillator configuration. + 1 1 - K_DR - Use device root key K_DR from CRYPTOCELL AO power domain - 0 + Disable + Disable ROSC2 + 0x0 - K_PRTL - Use hard-coded RTL key K_PRTL - 1 + Enable + Enable ROSC2 + 0x1 + + + + + ROSC3 + Use ROSC3 ring oscillator configuration. + 2 + 2 + + + Disable + Disable ROSC3 + 0x0 - Session - Use provided session key - 2 + Enable + Enable ROSC3 + 0x1 - - - - HOST_IOT_KPRTL_LOCK - This write-once register is the K_PRTL lock register. When this register is set, K_PRTL can not be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. - 0x1A4C - read-write - 0x00000000 - - HOST_IOT_KPRTL_LOCK - This register is the K_PRTL lock register. When this register is set, K_PRTL can not be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. - 0 - 0 + ROSC4 + Use longest ROSC4 ring oscillator configuration. + 3 + 3 - Disabled - K_PRTL can be selected for use from register HOST_CRYPTOKEY_SEL - 0 + Disable + Disable ROSC4 + 0x0 - Enabled - K_PRTL has been locked until next power-on reset (POR). If K_PRTL is selected anyway, a zeroed key will be used instead. - 1 + Enable + Enable ROSC4 + 0x1 - HOST_IOT_KDR0 - This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained. - 0x1A50 + RNG_DMA_SRAM_ADDR + This register defines the start address in TRNG SRAM for the TRNG data to be collected by the RNG DMA engine. + 0x1D0 read-write 0x00000000 + 0x20 - HOST_IOT_KDR0 - Write: K_DR bits 31:0 Read: 0x00000000 when 128-bit K_DR key value is not yet retained in the CRYPTOCELL AO power domain Read: 0x00000001 when 128-bit K_DR key value is successfully retained in the CRYPTOCELL AO power domain + RNG_SRAM_DMA_ADDR + Start address of the TRNG data in TRNG SRAM. 0 - 31 + 10 - HOST_IOT_KDR1 - This register holds bits 63:32 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. - 0x1A54 - write-only + RNG_DMA_SAMPLES_NUM + This register defines the number of 192-bits samples that the RNG DMA engine collects per run. + 0x1D4 + read-write 0x00000000 + 0x20 - HOST_IOT_KDR1 - K_DR bits 63:32 + RNG_SAMPLES_NUM + Defines the number of 192-bits samples that the DMA engine collects per run. 0 - 31 + 7 - HOST_IOT_KDR2 - This register holds bits 95:64 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. - 0x1A58 - write-only + RNG_WATCHDOG_VAL + This register defines the maximum number of CPU clock cycles per TRNG collection of 192-bits samples. If the number of cycles for a collection exceeds this threshold the WATCHDOG interrupt is triggered. + 0x1D8 + read-write 0x00000000 + 0x20 - HOST_IOT_KDR2 - K_DR bits 95:64 + RNG_WATCHDOG_VAL + Defines the maximum number of CPU clock cycles per TRNG collection of 192-bits samples. If the number of cycles for a collection exceeds this threshold the WATCHDOG interrupt is triggered. 0 31 - HOST_IOT_KDR3 - This register holds bits 127:96 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. - 0x1A5C - write-only + RNG_DMA_BUSY + Status register for RNG DMA engine activity. + 0x1DC + read-only 0x00000000 + 0x20 - HOST_IOT_KDR3 - K_DR bits 127:96 - 0 - 31 - - - - - HOST_IOT_LCS - Controls lifecycle state (LCS) for CRYPTOCELL subsystem - 0x1A60 - read-write - 0x00000002 - - - LCS - Lifecycle state value. This field is write-once per reset. + STATUS + RNG DMA engine status. 0 - 2 + 0 - Debug - CC310 operates in debug mode - 0 + Idle + RNG DMA engine is idle + 0x0 - Secure - CC310 operates in secure mode - 2 + Busy + RNG DMA engine is busy + 0x1 - LCS_IS_VALID - This field is read-only and indicates if CRYPTOCELL LCS has been successfully configured since last reset - 8 - 8 + ROSC_LEN + The active ring oscillator length configuration used by the RNG DMA engine. + 1 + 2 - Invalid - A valid LCS is not yet retained in the CRYPTOCELL AO power domain - 0 + ROSC1 + Shortest ROSC1 ring oscillator configuration used. + 0x0 - Valid - A valid LCS is successfully retained in the CRYPTOCELL AO power domain - 1 + ROSC2 + ROSC2 ring oscillator configuration used. + 0x1 + + + ROSC3 + ROSC3 ring oscillator configuration used. + 0x2 + + + ROSC4 + Longest ROSC4 ring oscillator configuration used. + 0x3 + + NUM_OF_SAMPLES + Number of samples already collected using the current ring oscillator configuration. + 3 + 10 + - CRYPTOCELL - ARM TrustZone CryptoCell register interface - 0x5002A000 - CC_HOST_RGF + CC_RNG_SRAM + CRYPTOCELL RNG SRAM interface + 0x5002B000 + CC_AES 0 - 0x2000 + 0x1000 registers - - CRYPTOCELL - 42 - - CRYPTOCELL + CC_RNG_SRAM 0x20 - ENABLE - Enable CRYPTOCELL subsystem - 0x500 + SRAM_DATA + Read/Write data from RNG SRAM + 0xF00 read-write 0x00000000 + 0x20 - ENABLE - Enable or disable the CRYPTOCELL subsystem + SRAM_DATA + 32 bits DMA read/write from/to RNG SRAM. A 'read' or 'write' operation to this register will trigger the DMA address to be automatically incremented. + 0 + 31 + + + + + SRAM_ADDR + First address given to RNG SRAM DMA for read/write transactions from/to RNG SRAM. + 0xF04 + write-only + 0x00000000 + 0x20 + + + SRAM_ADDR + RNG SRAM starting address + 0 + 14 + + + + + SRAM_DATA_READY + RNG SRAM DMA engine is ready to read/write from/to RNG SRAM. + 0xF08 + read-only + 0x00000001 + 0x20 + + + SRAM_READY + RNG SRAM DMA status. 0 0 - Disabled - CRYPTOCELL subsystem disabled - 0 + Busy + DMA is busy + 0x0 - Enabled - CRYPTOCELL subsystem enabled - 1 + Idle + DMA is idle + 0x1 @@ -52153,5 +60627,23 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ + + PWM3 + Pulse width modulation unit 3 + 0x4002D000 + + PWM3 + 45 + + + + SPIM3 + Serial Peripheral Interface Master with EasyDMA 3 + 0x4002F000 + + SPIM3 + 47 + + diff --git a/svd/nrf5340-app.svd b/svd/nrf5340-app.svd index 85fd1ae..805d9dc 100644 --- a/svd/nrf5340-app.svd +++ b/svd/nrf5340-app.svd @@ -1,59284 +1,59296 @@ - - - - Nordic Semiconductor - Nordic - nrf5340_application - nrf53 - 1 - nRF53 reference description for system-on-chip with dual ARM 32-bit Cortex-M33 microcontrollers - -Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - -3. Neither the name of Nordic Semiconductor ASA nor the names of its - contributors may be used to endorse or promote products derived from this - software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE -ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE -LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -POSSIBILITY OF SUCH DAMAGE. - - 8 - 32 - 32 - 0x00000000 - 0xFFFFFFFF - - CM33 - r0p4 - little - 1 - 1 - 3 - 0 - 69 - 0 - - system_nrf5340_application - NRF_ - - 240 - - - - CACHEDATA_S - CACHEDATA - 0x00F00000 - CACHEDATA - - - - 0 - 0x1000 - registers - - CACHEDATA - 0x20 - - - 256 - 0x020 - SET[%s] - Unspecified - CACHEDATA_SET - read-write - 0x0 - - 2 - 0x010 - WAY[%s] - Unspecified - CACHEDATA_SET_WAY - read-write - 0x0 - - DATA0 - Description cluster: Cache data bits [31:0] of SET[n], WAY[o]. - 0x0 - read-write - - - Data - Data - 0 - 31 - - - - - DATA1 - Description cluster: Cache data bits [63:32] of SET[n], WAY[o]. - 0x4 - read-write - - - Data - Data - 0 - 31 - - - - - DATA2 - Description cluster: Cache data bits [95:64] of SET[n], WAY[o]. - 0x8 - read-write - - - Data - Data - 0 - 31 - - - - - DATA3 - Description cluster: Cache data bits [127:96] of SET[n], WAY[o]. - 0xC - read-write - - - Data - Data - 0 - 31 - - - - - - - - - CACHEINFO_S - CACHEINFO - 0x00F08000 - CACHEINFO - - - - 0 - 0x1000 - registers - - CACHEINFO - 0x20 - - - 256 - 0x008 - SET[%s] - Unspecified - CACHEINFO_SET - read-write - 0x0 - - 0x2 - 0x4 - WAY[%s] - Description collection: Cache information for SET[n], WAY[o]. - 0x0 - read-write - - - TAG - Cache tag. - 0 - 16 - - - V - Valid bit - 30 - 30 - read-only - - - Invalid - Invalid cache line - 0 - - - Valid - Valid cache line - 1 - - - - - MRU - Most recently used way. - 31 - 31 - read-only - - - Way0 - Way0 was most recently used - 0 - - - Way1 - Way1 was most recently used - 1 - - - - - - - - - - FICR_S - Factory Information Configuration Registers - 0x00FF0000 - FICR - - - - 0 - 0x1000 - registers - - FICR - 0x20 - - - INFO - Device info - FICR_INFO - read-write - 0x200 - - CONFIGID - Configuration identifier - 0x000 - read-only - 0xFFFFFFFF - - - HWID - Identification number for the HW - 0 - 15 - - - - - 0x2 - 0x4 - DEVICEID[%s] - Description collection: Device identifier - 0x004 - read-only - 0xFFFFFFFF - - - DEVICEID - 64 bit unique device identifier - 0 - 31 - - - - - PART - Part code - 0x00C - read-only - 0x00005340 - - - PART - Part code - 0 - 31 - - - N5340 - nRF5340 - 0x5340 - - - Unspecified - Unspecified - 0xFFFFFFFF - - - - - - - VARIANT - Part Variant, Hardware version and Production configuration - 0x010 - read-only - 0xFFFFFFFF - - - VARIANT - Part Variant, Hardware version and Production configuration, encoded as ASCII - 0 - 31 - - - QKAA - QKAA - 0x514B4141 - - - Unspecified - Unspecified - 0xFFFFFFFF - - - - - - - PACKAGE - Package option - 0x014 - read-only - 0xFFFFFFFF - - - PACKAGE - Package option - 0 - 31 - - - QK - QKxx - 94-pin aQFN - 0x2000 - - - Unspecified - Unspecified - 0xFFFFFFFF - - - - - - - RAM - RAM variant - 0x018 - read-only - 0xFFFFFFFF - - - RAM - RAM variant - 0 - 31 - - - K16 - 16 kByte RAM - 0x10 - - - K32 - 32 kByte RAM - 0x20 - - - K64 - 64 kByte RAM - 0x40 - - - K128 - 128 kByte RAM - 0x80 - - - K256 - 256 kByte RAM - 0x100 - - - K512 - 512 kByte RAM - 0x200 - - - Unspecified - Unspecified - 0xFFFFFFFF - - - - - - - FLASH - Flash variant - 0x01C - read-only - 0xFFFFFFFF - - - FLASH - Flash variant - 0 - 31 - - - K128 - 128 kByte FLASH - 0x80 - - - K256 - 256 kByte FLASH - 0x100 - - - K512 - 512 kByte FLASH - 0x200 - - - K1024 - 1 MByte FLASH - 0x400 - - - K2048 - 2 MByte FLASH - 0x800 - - - Unspecified - Unspecified - 0xFFFFFFFF - - - - - - - CODEPAGESIZE - Code memory page size in bytes - 0x020 - read-only - 0x00001000 - - - CODEPAGESIZE - Code memory page size in bytes - 0 - 31 - - - K4096 - 4 kByte - 0x1000 - - - - - - - CODESIZE - Code memory size - 0x024 - read-only - 0x00000100 - - - CODESIZE - Code memory size in number of pages - 0 - 31 - - - P256 - 256 pages - 256 - - - - - - - DEVICETYPE - Device type - 0x028 - read-only - 0x00000000 - - - DEVICETYPE - Device type - 0 - 31 - - - Die - Device is an physical DIE - 0x0000000 - - - FPGA - Device is an FPGA - 0xFFFFFFFF - - - - - - - - 32 - 0x008 - TRIMCNF[%s] - Unspecified - FICR_TRIMCNF - read-write - 0x300 - - ADDR - Description cluster: Address of the PAR register which will be written - 0x000 - read-write - 0xFFFFFFFF - uint32_t * - - - Address - Address - 0 - 31 - - - - - DATA - Description cluster: Data - 0x004 - read-only - 0xFFFFFFFF - - - Data - Data to be written into the PAR register - 0 - 31 - - - - - - NFC - Unspecified - FICR_NFC - read-write - 0x450 - - TAGHEADER0 - Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. - 0x000 - read-only - 0xFFFFFF5F - - - MFGID - Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F - 0 - 7 - - - UD1 - Unique identifier byte 1 - 8 - 15 - - - UD2 - Unique identifier byte 2 - 16 - 23 - - - UD3 - Unique identifier byte 3 - 24 - 31 - - - - - TAGHEADER1 - Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. - 0x004 - read-only - 0xFFFFFFFF - - - UD4 - Unique identifier byte 4 - 0 - 7 - - - UD5 - Unique identifier byte 5 - 8 - 15 - - - UD6 - Unique identifier byte 6 - 16 - 23 - - - UD7 - Unique identifier byte 7 - 24 - 31 - - - - - TAGHEADER2 - Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. - 0x008 - read-only - 0xFFFFFFFF - - - UD8 - Unique identifier byte 8 - 0 - 7 - - - UD9 - Unique identifier byte 9 - 8 - 15 - - - UD10 - Unique identifier byte 10 - 16 - 23 - - - UD11 - Unique identifier byte 11 - 24 - 31 - - - - - TAGHEADER3 - Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. - 0x00C - read-only - 0xFFFFFFFF - - - UD12 - Unique identifier byte 12 - 0 - 7 - - - UD13 - Unique identifier byte 13 - 8 - 15 - - - UD14 - Unique identifier byte 14 - 16 - 23 - - - UD15 - Unique identifier byte 15 - 24 - 31 - - - - - - TRNG90B - NIST800-90B RNG calibration data - FICR_TRNG90B - read-write - 0xC00 - - BYTES - Amount of bytes for the required entropy bits - 0x000 - read-only - 0x00000210 - - - BYTES - Amount of bytes for the required entropy bits - 0 - 31 - - - - - RCCUTOFF - Repetition counter cutoff - 0x004 - read-only - 0xFFFFFFFF - - - RCCUTOFF - Repetition counter cutoff - 0 - 31 - - - - - APCUTOFF - Adaptive proportion cutoff - 0x008 - read-only - 0xFFFFFFFF - - - APCUTOFF - Adaptive proportion cutoff - 0 - 31 - - - - - STARTUP - Amount of bytes for the startup tests - 0x00C - read-only - 0xFFFFFFFF - - - STARTUP - Amount of bytes for the startup tests - 0 - 31 - - - - - ROSC1 - Sample count for ring oscillator 1 - 0x010 - read-only - 0xFFFFFFFF - - - ROSC1 - Sample count for ring oscillator 1 - 0 - 31 - - - - - ROSC2 - Sample count for ring oscillator 2 - 0x014 - read-only - 0xFFFFFFFF - - - ROSC2 - Sample count for ring oscillator 2 - 0 - 31 - - - - - ROSC3 - Sample count for ring oscillator 3 - 0x018 - read-only - 0xFFFFFFFF - - - ROSC3 - Sample count for ring oscillator 3 - 0 - 31 - - - - - ROSC4 - Sample count for ring oscillator 4 - 0x01C - read-only - 0xFFFFFFFF - - - ROSC4 - Sample count for ring oscillator 4 - 0 - 31 - - - - - - XOSC32MTRIM - XOSC32M capacitor selection trim values - 0xC20 - read-only - 0xFFFFFFFF - - - SLOPE - Slope trim factor on twos complement form - 0 - 4 - - - OFFSET - Offset trim factor on integer form - 5 - 9 - - - - - - - UICR_S - User Information Configuration Registers User information configuration registers - 0x00FF8000 - UICR - - - - 0 - 0x1000 - registers - - UICR - 0x20 - - - APPROTECT - Access port protection - 0x000 - read-write - 0x00000000 - - - PALL - Blocks debugger read/write access to all CPU registers and - memory mapped addresses. - 0 - 31 - - - Unprotected - Unprotected - 0x50FA50FA - - - Protected - Protected - 0x00000000 - - - - - - - VREGHVOUT - Output voltage from the high voltage (VREGH) regulator stage. The maximum output voltage from this stage is given as VDDH - VREGHDROP. - 0x010 - read-write - 0xFFFFFFFF - - - VREGHVOUT - VREGH regulator output voltage. - 0 - 2 - - - 1V8 - 1.8 V - 0 - - - 2V1 - 2.1 V - 1 - - - 2V4 - 2.4 V - 2 - - - 2V7 - 2.7 V - 3 - - - 3V0 - 3.0 V - 4 - - - 3V3 - 3.3 V - 5 - - - DEFAULT - Default voltage: 1.8 V - 7 - - - - - - - HFXOCNT - HFXO startup counter - 0x014 - read-write - 0xFFFFFFFF - - - HFXOCNT - HFXO startup counter. Total debounce time = HFXOCNT*64 us + 0.5 us - 0 - 7 - - - MinDebounceTime - Min debounce time = (0*64 us + 0.5 us) - 0 - - - MaxDebounceTime - Max debounce time = (254*64 us + 0.5 us) - 254 - - - DefaultDebounceTime - Default debounce time for erased UICR = 4*64 us + 0.5 us - 255 - - - - - - - SECUREAPPROTECT - Secure access port protection - 0x01C - read-write - 0x00000000 - - - PALL - Blocks debugger read/write access to all secure CPU registers and secure memory - mapped addresses. - 0 - 31 - - - Unprotected - Unprotected - 0x50FA50FA - - - Protected - Protected - 0x00000000 - - - - - - - ERASEPROTECT - Erase protection - 0x020 - read-write - 0x00000000 - - - PALL - Blocks NVMC ERASEALL and CTRLAP ERASEALL functionality. Using any value except Unprotected will lead to the protection being enabled. - 0 - 31 - - - Unprotected - Unprotected - 0xFFFFFFFF - - - Protected - Protected - 0x00000000 - - - - - - - TINSTANCE - SW-DP Target instance - 0x024 - read-write - 0xFFFFFFFF - - - TINSTANCE - TINSTANCE bits are negated and used in the SW-DP DLPIDR.TINSTANCE field. E.g. 0xF in this field is translated to 0x0 in DLPIDR.TINSTANCE field. - 28 - 31 - - - - - NFCPINS - Setting of pins dedicated to NFC functionality: NFC antenna or GPIO - 0x028 - read-write - 0xFFFFFFFF - - - PROTECT - Setting of pins dedicated to NFC functionality - 0 - 0 - - - Disabled - Operation as GPIO pins. Same protection as normal GPIO pins - 0 - - - NFC - Operation as NFC antenna pins. Configures the protection for NFC operation - 1 - - - - - - - 0xC0 - 0x4 - OTP[%s] - Description collection: One time programmable memory - 0x100 - read-write - 0xFFFFFFFF - - - LOWER - Lower half word - 0 - 15 - read-writeOnce - - - UPPER - Upper half word - 16 - 31 - read-writeOnce - - - - - KEYSLOT - Unspecified - UICR_KEYSLOT - read-write - 0x400 - - 128 - 0x008 - CONFIG[%s] - Unspecified - UICR_KEYSLOT_CONFIG - read-write - 0x000 - - DEST - Description cluster: Destination address where content of the key value registers (KEYSLOT.KEYn.VALUE[0-3]) - will be pushed by KMU. Note that this address must match that of a peripherals - APB mapped write-only key registers, else the KMU can push this key value into - an address range which the CPU can potentially read. - 0x000 - read-write - 0xFFFFFFFF - - - DEST - Secure APB destination address - 0 - 31 - - - - - PERM - Description cluster: Define permissions for the key slot. Bits 0-15 and 16-31 can only be written when equal to 0xFFFF. - 0x004 - read-write - 0xFFFFFFFF - - - WRITE - Write permission for key slot - 0 - 0 - - - Disabled - Disable write to the key value registers - 0 - - - Enabled - Enable write to the key value registers - 1 - - - - - READ - Read permission for key slot - 1 - 1 - - - Disabled - Disable read from key value registers - 0 - - - Enabled - Enable read from key value registers - 1 - - - - - PUSH - Push permission for key slot - 2 - 2 - - - Disabled - Disable pushing of key value registers over secure APB, but can be read if field READ is Enabled - 0 - - - Enabled - Enable pushing of key value registers over secure APB. Register KEYSLOT.CONFIGn.DEST must contain a valid destination address! - 1 - - - - - STATE - Revocation state for the key slot - 16 - 16 - - - Revoked - Key value registers can no longer be read or pushed - 0 - - - Active - Key value registers are readable (if enabled) and can be pushed (if enabled) - 1 - - - - - - - - 128 - 0x010 - KEY[%s] - Unspecified - UICR_KEYSLOT_KEY - read-write - 0x400 - - 0x4 - 0x4 - VALUE[%s] - Description collection: Define bits [31+o*32:0+o*32] of value assigned to KMU key slot. - 0x000 - read-write - 0xFFFFFFFF - - - VALUE - Define bits [31+o*32:0+o*32] of value assigned to KMU key slot - 0 - 31 - - - - - - - - - CTI_S - Cross-Trigger Interface control. NOTE: this is not a separate peripheral, but describes CM33 functionality. - 0xE0042000 - CTI - - - - 0 - 0x1000 - registers - - CTI - 0x20 - - - CTICONTROL - CTI Control register - 0x000 - read-write - 0x00000000 - - - GLBEN - Enables or disables the CTI. - 0 - 0 - - - Disabled - All cross-triggering mapping logic functionality is disabled. - 0 - - - Enabled - Cross-triggering mapping logic functionality is enabled. - 1 - - - - - - - CTIINTACK - CTI Interrupt Acknowledge register - 0x010 - write-only - 0x00000000 - - - DEBUGREQ - Processor debug request - 0 - 0 - - write - - Acknowledge - Clears the ctitrigout. - 1 - - - - - CPURESTART - Processor Restart - 1 - 1 - - write - - Acknowledge - Clears the ctitrigout. - 1 - - - - - UNUSED0 - N/A - 2 - 2 - - write - - Acknowledge - Clears the ctitrigout. - 1 - - - - - UNUSED1 - N/A - 3 - 3 - - write - - Acknowledge - Clears the ctitrigout. - 1 - - - - - ETMEVTIN0 - ETM Event Input 0 - 4 - 4 - - write - - Acknowledge - Clears the ctitrigout. - 1 - - - - - ETMEVTIN1 - ETM Event Input 1 - 5 - 5 - - write - - Acknowledge - Clears the ctitrigout. - 1 - - - - - ETMEVTIN2 - ETM Event Input 2 - 6 - 6 - - write - - Acknowledge - Clears the ctitrigout. - 1 - - - - - ETMEVTIN3 - ETM Event Input 3 - 7 - 7 - - write - - Acknowledge - Clears the ctitrigout. - 1 - - - - - - - CTIAPPSET - CTI Application Trigger Set register - 0x014 - read-write - 0x00000000 - - - APPSET_0 - Application trigger event for channel 0. - 0 - 0 - - read - - Inactive - Application trigger 0 is inactive. - 0 - - - Active - Application trigger 0 is active. - 1 - - - - write - - Activate - Generate channel event for channel 0. - 1 - - - - - APPSET_1 - Application trigger event for channel 1. - 1 - 1 - - read - - Inactive - Application trigger 1 is inactive. - 0 - - - Active - Application trigger 1 is active. - 1 - - - - write - - Activate - Generate channel event for channel 1. - 1 - - - - - APPSET_2 - Application trigger event for channel 2. - 2 - 2 - - read - - Inactive - Application trigger 2 is inactive. - 0 - - - Active - Application trigger 2 is active. - 1 - - - - write - - Activate - Generate channel event for channel 2. - 1 - - - - - APPSET_3 - Application trigger event for channel 3. - 3 - 3 - - read - - Inactive - Application trigger 3 is inactive. - 0 - - - Active - Application trigger 3 is active. - 1 - - - - write - - Activate - Generate channel event for channel 3. - 1 - - - - - - - CTIAPPCLEAR - CTI Application Trigger Clear register - 0x018 - write-only - 0x00000000 - - - APPCLEAR_0 - Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. - 0 - 0 - - write - - Clear - Clears the event for channel 0. - 1 - - - - - APPCLEAR_1 - Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. - 1 - 1 - - write - - Clear - Clears the event for channel 1. - 1 - - - - - APPCLEAR_2 - Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. - 2 - 2 - - write - - Clear - Clears the event for channel 2. - 1 - - - - - APPCLEAR_3 - Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. - 3 - 3 - - write - - Clear - Clears the event for channel 3. - 1 - - - - - - - CTIAPPPULSE - CTI Application Pulse register - 0x01C - write-only - 0x00000000 - - - APPULSE_0 - Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. - 0 - 0 - - write - - Generate - Generates an event pulse on channel 0. - 1 - - - - - APPULSE_1 - Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. - 1 - 1 - - write - - Generate - Generates an event pulse on channel 1. - 1 - - - - - APPULSE_2 - Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. - 2 - 2 - - write - - Generate - Generates an event pulse on channel 2. - 1 - - - - - APPULSE_3 - Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. - 3 - 3 - - write - - Generate - Generates an event pulse on channel 3. - 1 - - - - - - - 0x8 - 0x4 - CTIINEN[%s] - Description collection: CTI Trigger input - 0x020 - read-write - 0x00000000 - - - TRIGINEN_0 - Enables a cross trigger event to channel 0 when a ctitrigin input is activated. - 0 - 0 - - - Disabled - Input trigger n events are ignored by channel 0. - 0 - - - Enabled - When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 0. - 1 - - - - - TRIGINEN_1 - Enables a cross trigger event to channel 1 when a ctitrigin input is activated. - 1 - 1 - - - Disabled - Input trigger n events are ignored by channel 1. - 0 - - - Enabled - When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 1. - 1 - - - - - TRIGINEN_2 - Enables a cross trigger event to channel 2 when a ctitrigin input is activated. - 2 - 2 - - - Disabled - Input trigger n events are ignored by channel 2. - 0 - - - Enabled - When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 2. - 1 - - - - - TRIGINEN_3 - Enables a cross trigger event to channel 3 when a ctitrigin input is activated. - 3 - 3 - - - Disabled - Input trigger n events are ignored by channel 3. - 0 - - - Enabled - When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 3. - 1 - - - - - - - 0x8 - 0x4 - CTIOUTEN[%s] - Description collection: CTI Trigger output - 0x0A0 - read-write - 0x00000000 - - - TRIGOUTEN_0 - Enables a cross trigger event to ctitrigout when channel 0 is activated. - 0 - 0 - - - Disabled - Channel 0 is ignored by output trigger n. - 0 - - - Enabled - When an event occurs on channel 0, generate an event on output event n (ctitrigout[n]). - 1 - - - - - TRIGOUTEN_1 - Enables a cross trigger event to ctitrigout when channel 1 is activated. - 1 - 1 - - - Disabled - Channel 1 is ignored by output trigger n. - 0 - - - Enabled - When an event occurs on channel 1, generate an event on output event n (ctitrigout[n]). - 1 - - - - - TRIGOUTEN_2 - Enables a cross trigger event to ctitrigout when channel 2 is activated. - 2 - 2 - - - Disabled - Channel 2 is ignored by output trigger n. - 0 - - - Enabled - When an event occurs on channel 2, generate an event on output event n (ctitrigout[n]). - 1 - - - - - TRIGOUTEN_3 - Enables a cross trigger event to ctitrigout when channel 3 is activated. - 3 - 3 - - - Disabled - Channel 3 is ignored by output trigger n. - 0 - - - Enabled - When an event occurs on channel 3, generate an event on output event n (ctitrigout[n]). - 1 - - - - - - - CTITRIGINSTATUS - CTI Trigger In Status register - 0x130 - read-only - 0x00000000 - - - CPUHALTED - Processor Halted - 0 - 0 - - - Active - Ctitrigin 0 is active. - 1 - - - Inactive - Ctitrigin 0 is inactive. - 0 - - - - - DWTCOMPOUT0 - DWT Comparator Output 0 - 1 - 1 - - - Active - Ctitrigin 1 is active. - 1 - - - Inactive - Ctitrigin 1 is inactive. - 0 - - - - - DWTCOMPOUT1 - DWT Comparator Output 1 - 2 - 2 - - - Active - Ctitrigin 2 is active. - 1 - - - Inactive - Ctitrigin 2 is inactive. - 0 - - - - - DWTCOMPOUT2 - DWT Comparator Output 2 - 3 - 3 - - - Active - Ctitrigin 3 is active. - 1 - - - Inactive - Ctitrigin 3 is inactive. - 0 - - - - - ETMEVTOUT0 - ETM Event Output 0 - 4 - 4 - - - Active - Ctitrigin 4 is active. - 1 - - - Inactive - Ctitrigin 4 is inactive. - 0 - - - - - ETMEVTOUT1 - ETM Event Output 1 - 5 - 5 - - - Active - Ctitrigin 5 is active. - 1 - - - Inactive - Ctitrigin 5 is inactive. - 0 - - - - - UNUSED0 - N/A - 6 - 6 - - - Active - Ctitrigin 6 is active. - 1 - - - Inactive - Ctitrigin 6 is inactive. - 0 - - - - - UNUSED1 - N/A - 7 - 7 - - - Active - Ctitrigin 7 is active. - 1 - - - Inactive - Ctitrigin 7 is inactive. - 0 - - - - - - - CTITRIGOUTSTATUS - CTI Trigger Out Status register - 0x134 - read-only - 0x00000000 - - - DEBUGREQ - Processor debug request - 0 - 0 - - - Active - Ctitrigout 0 is active. - 1 - - - Inactive - Ctitrigout 0 is inactive. - 0 - - - - - CPURESTART - Processor Restart - 1 - 1 - - - Active - Ctitrigout 1 is active. - 1 - - - Inactive - Ctitrigout 1 is inactive. - 0 - - - - - UNUSED0 - N/A - 2 - 2 - - - Active - Ctitrigout 2 is active. - 1 - - - Inactive - Ctitrigout 2 is inactive. - 0 - - - - - UNUSED1 - N/A - 3 - 3 - - - Active - Ctitrigout 3 is active. - 1 - - - Inactive - Ctitrigout 3 is inactive. - 0 - - - - - ETMEVTIN0 - ETM Event Input 0 - 4 - 4 - - - Active - Ctitrigout 4 is active. - 1 - - - Inactive - Ctitrigout 4 is inactive. - 0 - - - - - ETMEVTIN1 - ETM Event Input 1 - 5 - 5 - - - Active - Ctitrigout 5 is active. - 1 - - - Inactive - Ctitrigout 5 is inactive. - 0 - - - - - ETMEVTIN2 - ETM Event Input 2 - 6 - 6 - - - Active - Ctitrigout 6 is active. - 1 - - - Inactive - Ctitrigout 6 is inactive. - 0 - - - - - ETMEVTIN3 - ETM Event Input 3 - 7 - 7 - - - Active - Ctitrigout 7 is active. - 1 - - - Inactive - Ctitrigout 7 is inactive. - 0 - - - - - - - CTICHINSTATUS - CTI Channel In Status register - 0x138 - read-only - 0x00000000 - - - CTICHINSTATUS_0 - Shows the status of the ctitrigin 0 input. - 0 - 0 - - - Active - Ctichin 0 is active. - 1 - - - Inactive - Ctichin 0 is inactive. - 0 - - - - - CTICHINSTATUS_1 - Shows the status of the ctitrigin 1 input. - 1 - 1 - - - Active - Ctichin 1 is active. - 1 - - - Inactive - Ctichin 1 is inactive. - 0 - - - - - CTICHINSTATUS_2 - Shows the status of the ctitrigin 2 input. - 2 - 2 - - - Active - Ctichin 2 is active. - 1 - - - Inactive - Ctichin 2 is inactive. - 0 - - - - - CTICHINSTATUS_3 - Shows the status of the ctitrigin 3 input. - 3 - 3 - - - Active - Ctichin 3 is active. - 1 - - - Inactive - Ctichin 3 is inactive. - 0 - - - - - - - CTIGATE - Enable CTI Channel Gate register - 0x140 - read-write - 0x0000000F - - - CTIGATEEN_0 - Enable ctichout0. - 0 - 0 - - - Enabled - Enable ctichout channel 0 propagation. - 1 - - - Disabled - Disable ctichout channel 0 propagation. - 0 - - - - - CTIGATEEN_1 - Enable ctichout1. - 1 - 1 - - - Enabled - Enable ctichout channel 1 propagation. - 1 - - - Disabled - Disable ctichout channel 1 propagation. - 0 - - - - - CTIGATEEN_2 - Enable ctichout2. - 2 - 2 - - - Enabled - Enable ctichout channel 2 propagation. - 1 - - - Disabled - Disable ctichout channel 2 propagation. - 0 - - - - - CTIGATEEN_3 - Enable ctichout3. - 3 - 3 - - - Enabled - Enable ctichout channel 3 propagation. - 1 - - - Disabled - Disable ctichout channel 3 propagation. - 0 - - - - - - - DEVARCH - Device Architecture register - 0xFBC - read-only - 0x47701A14 - - - Architecture - Contains the CTI device architecture. - 0 - 0 - - - - - DEVID - Device Configuration register - 0xFC8 - read-only - 0x00040800 - - - EXTMUXNUM - Indicates the number of multiplexers available on Trigger Inputs and Trigger Outputs that are using asicctl. - The default value of 0b00000 indicates that no multiplexing is present. - 0 - 4 - - - NUMTRIG - Number of ECT triggers available. - 8 - 15 - - - NUMCH - Number of ECT channels available. - 16 - 19 - - - - - DEVTYPE - Device Type Identifier register - 0xFCC - read-only - 0x00000014 - - - MAJOR - Major classification of the type of the debug component as specified in the Arm Architecture Specification for this - debug and trace component. - 0 - 3 - - - Controller - Indicates that this component allows a debugger to control other components in an Arm CoreSight SoC-400 system. - 4 - - - - - SUB - Sub-classification of the type of the debug component as specified in the Arm Architecture Specification within - the major classification as specified in the MAJOR field. - 4 - 7 - - - Crosstrigger - Indicates that this component is a sub-triggering component. - 1 - - - - - - - PIDR4 - Peripheral ID4 Register - 0xFD0 - read-only - 0x00000004 - - - DES_2 - Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. - 0 - 3 - - - Code - JEDEC continuation code. - 4 - - - - - SIZE - Always 0b0000. Indicates that the device only occupies 4KB of memory. - 4 - 7 - - - - - PIDR5 - Peripheral ID5 register - 0xFD4 - read-only - - - PIDR6 - Peripheral ID6 register - 0xFD8 - read-only - - - PIDR7 - Peripheral ID7 register - 0xFDC - read-only - - - PIDR0 - Peripheral ID0 Register - 0xFE0 - read-only - 0x00000021 - - - PART_0 - Bits[7:0] of the 12-bit part number of the component. The designer of the component assigns this part number. - 0 - 7 - - - PartnumberL - Indicates bits[7:0] of the part number of the component. - 0x21 - - - - - - - PIDR1 - Peripheral ID1 Register - 0xFE4 - read-only - 0x000000BD - - - PART_1 - Bits[11:8] of the 12-bit part number of the component. The designer of the component assigns this part number. - 0 - 3 - - - PartnumberH - Indicates bits[11:8] of the part number of the component. - 13 - - - - - DES_0 - Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. - 4 - 7 - - - Arm - Arm. Bits[3:0] of the JEDEC JEP106 Identity Code - 11 - - - - - - - PIDR2 - Peripheral ID2 Register - 0xFE8 - read-only - 0x0000000B - - - DES_1 - Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. - 0 - 2 - - - Arm - Arm. Bits[6:4] of the JEDEC JEP106 Identity Code - 3 - - - - - JEDEC - Always 1. Indicates that the JEDEC-assigned designer ID is used. - 3 - 3 - - - REVISION - Peripheral revision - 4 - 7 - - - Rev0p0 - This device is at r0p0 - 0 - - - - - - - PIDR3 - Peripheral ID3 Register - 0xFEC - read-only - 0x00000000 - - - CMOD - Customer Modified. Indicates whether the customer has modified the behavior of the component. In most cases, - this field is 0b0000. Customers change this value when they make authorized modifications to this component. - 0 - 3 - - - Unmodified - Indicates that the customer has not modified this component. - 0 - - - - - REVAND - Indicates minor errata fixes specific to the revision of the component being used, for example metal fixes after - implementation. In most cases, this field is 0b0000. Arm recommends that the component designers ensure that a - metal fix can change this field if required, for example, by driving it from registers that reset to 0b0000. - 4 - 7 - - - NoErrata - Indicates that there are no errata fixes to this component. - 0 - - - - - - - CIDR0 - Component ID0 Register - 0xFF0 - read-only - 0x0000000D - - - PRMBL_0 - Preamble[0]. Contains bits[7:0] of the component identification code. - 0 - 7 - - - Value - Bits[7:0] of the identification code. - 0x0D - - - - - - - CIDR1 - Component ID1 Register - 0xFF4 - read-only - 0x00000090 - - - PRMBL_1 - Preamble[1]. Contains bits[11:8] of the component identification code. - 0 - 3 - - - Value - Bits[11:8] of the identification code. - 0 - - - - - CLASS - Class of the component, for example, whether the component is a ROM table or a generic CoreSight component. - Contains bits[15:12] of the component identification code - 4 - 7 - - - Coresight - Indicates that the component is a CoreSight component. - 9 - - - - - - - CIDR2 - Component ID2 Register - 0xFF8 - read-only - 0x00000005 - - - PRMBL_2 - Preamble[2]. Contains bits[23:16] of the component identification code. - 0 - 7 - - - Value - Bits[23:16] of the identification code. - 0x05 - - - - - - - CIDR3 - Component ID3 Register - 0xFFC - read-only - 0x000000B1 - - - PRMBL_3 - Preamble[3]. Contains bits[31:24] of the component identification code. - 0 - 7 - - - Value - Bits[31:24] of the identification code. - 0xB1 - - - - - - - - - TAD_S - Trace and debug control - 0xE0080000 - TAD - - - - 0 - 0x1000 - registers - - TAD - 0x20 - - - CLOCKSTART - Start all trace and debug clocks. - 0x004 - write-only - - - START - 0 - 0 - - - Start - Start all trace and debug clocks. - 1 - - - - - - - CLOCKSTOP - Stop all trace and debug clocks. - 0x008 - write-only - - - STOP - 0 - 0 - - - Stop - Stop all trace and debug clocks. - 1 - - - - - - - ENABLE - Enable debug domain and aquire selected GPIOs - 0x500 - read-write - - - ENABLE - 0 - 0 - - - DISABLED - Disable debug domain and release selected GPIOs - 0 - - - ENABLED - Enable debug domain and aquire selected GPIOs - 1 - - - - - - - PSEL - Unspecified - TAD_PSEL - read-write - 0x504 - - TRACECLK - Pin configuration for TRACECLK - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - Traceclk - TRACECLK pin - 12 - - - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - TRACEDATA0 - Pin configuration for TRACEDATA[0] - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - Tracedata0 - TRACEDATA0 pin - 11 - - - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - TRACEDATA1 - Pin configuration for TRACEDATA[1] - 0x008 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - Tracedata1 - TRACEDATA1 pin - 10 - - - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - TRACEDATA2 - Pin configuration for TRACEDATA[2] - 0x00C - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - Tracedata2 - TRACEDATA2 pin - 9 - - - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - TRACEDATA3 - Pin configuration for TRACEDATA[3] - 0x010 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - Tracedata3 - TRACEDATA3 pin - 8 - - - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - TRACEPORTSPEED - Clocking options for the Trace Port debug interface Reset behavior is the same as debug components - 0x518 - read-write - 0x00000000 - - - TRACEPORTSPEED - Speed of Trace Port clock. Note that the TRACECLK pin output will be divided again by two from the Trace Port clock. - 0 - 1 - - - 64MHz - Trace Port clock is: 64MHz - 0 - - - 32MHz - Trace Port clock is: 32MHz - 1 - - - 16MHz - Trace Port clock is: 16MHz - 2 - - - 8MHz - Trace Port clock is: 8MHz - 3 - - - - - - - - - DCNF_NS - Domain configuration management 0 - 0x40000000 - DCNF - - - - 0 - 0x1000 - registers - - DCNF - 0x20 - - - CPUID - CPU ID of this subsystem - 0x420 - read-only - 0x00000000 - - - CPUID - CPU ID - 0 - 7 - - - - - 1 - 0x004 - EXTPERI[%s] - Unspecified - DCNF_EXTPERI - read-write - 0x440 - - PROTECT - Description cluster: Control access for master connected to AMLI master port EXTPERI[n] - 0x000 - read-write - - - SLAVE0 - Control access to slave 0 of master EXTPERI[n] - 0 - 0 - - - Allowed - Access to slave is allowed - 0 - - - Blocked - Access to slave is blocked - 1 - - - - - - - - 1 - 0x004 - EXTRAM[%s] - Unspecified - DCNF_EXTRAM - read-write - 0x460 - - PROTECT - Description cluster: Control access from master connected to AMLI master port EXTRAM[n] - 0x000 - read-write - - - SLAVE0 - Control access to slave 0 of master EXTRAM[n] - 0 - 0 - - - Allowed - Access to slave is allowed - 0 - - - Blocked - Access to slave is blocked - 1 - - - - - SLAVE1 - Control access to slave 1 of master EXTRAM[n] - 1 - 1 - - - Allowed - Access to slave is allowed - 0 - - - Blocked - Access to slave is blocked - 1 - - - - - SLAVE2 - Control access to slave 2 of master EXTRAM[n] - 2 - 2 - - - Allowed - Access to slave is allowed - 0 - - - Blocked - Access to slave is blocked - 1 - - - - - SLAVE3 - Control access to slave 3 of master EXTRAM[n] - 3 - 3 - - - Allowed - Access to slave is allowed - 0 - - - Blocked - Access to slave is blocked - 1 - - - - - SLAVE4 - Control access to slave 4 of master EXTRAM[n] - 4 - 4 - - - Allowed - Access to slave is allowed - 0 - - - Blocked - Access to slave is blocked - 1 - - - - - SLAVE5 - Control access to slave 5 of master EXTRAM[n] - 5 - 5 - - - Allowed - Access to slave is allowed - 0 - - - Blocked - Access to slave is blocked - 1 - - - - - SLAVE6 - Control access to slave 6 of master EXTRAM[n] - 6 - 6 - - - Allowed - Access to slave is allowed - 0 - - - Blocked - Access to slave is blocked - 1 - - - - - SLAVE7 - Control access to slave 7 of master EXTRAM[n] - 7 - 7 - - - Allowed - Access to slave is allowed - 0 - - - Blocked - Access to slave is blocked - 1 - - - - - - - - 1 - 0x004 - EXTCODE[%s] - Unspecified - DCNF_EXTCODE - read-write - 0x480 - - PROTECT - Description cluster: Control access from master connected to AMLI master port EXTCODE[n] - 0x000 - read-write - - - SLAVE0 - Control access to slave 0 of master EXTCODE[n] - 0 - 0 - - - Allowed - Access to slave is allowed - 0 - - - Blocked - Access to slave is blocked - 1 - - - - - - - - - - FPU_NS - FPU control peripheral 0 - 0x40000000 - DCNF_NS - FPU - - - - 0 - 0x1000 - registers - - - FPU - 0 - - FPU - 0x20 - - - EVENTS_INVALIDOPERATION - An FPUIOC exception triggered by an invalid operation has occurred in the FPU - 0x100 - read-write - - - EVENTS_INVALIDOPERATION - An FPUIOC exception triggered by an invalid operation has occurred in the FPU - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_DIVIDEBYZERO - An FPUDZC exception triggered by a floating-point divide-by-zero operation has occurred in the FPU - 0x104 - read-write - - - EVENTS_DIVIDEBYZERO - An FPUDZC exception triggered by a floating-point divide-by-zero operation has occurred in the FPU - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_OVERFLOW - An FPUOFC exception triggered by a floating-point overflow has occurred in the FPU - 0x108 - read-write - - - EVENTS_OVERFLOW - An FPUOFC exception triggered by a floating-point overflow has occurred in the FPU - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_UNDERFLOW - An FPUUFC exception triggered by a floating-point underflow has occurred in the FPU - 0x10C - read-write - - - EVENTS_UNDERFLOW - An FPUUFC exception triggered by a floating-point underflow has occurred in the FPU - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_INEXACT - An FPUIXC exception triggered by an inexact floating-point operation has occurred in the FPU - 0x110 - read-write - - - EVENTS_INEXACT - An FPUIXC exception triggered by an inexact floating-point operation has occurred in the FPU - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_DENORMALINPUT - An FPUIDC exception triggered by a denormal floating-point input has occurred in the FPU - 0x114 - read-write - - - EVENTS_DENORMALINPUT - An FPUIDC exception triggered by a denormal floating-point input has occurred in the FPU - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - - INVALIDOPERATION - Enable or disable interrupt for event INVALIDOPERATION - 0 - 0 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - DIVIDEBYZERO - Enable or disable interrupt for event DIVIDEBYZERO - 1 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - OVERFLOW - Enable or disable interrupt for event OVERFLOW - 2 - 2 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - UNDERFLOW - Enable or disable interrupt for event UNDERFLOW - 3 - 3 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - INEXACT - Enable or disable interrupt for event INEXACT - 4 - 4 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - DENORMALINPUT - Enable or disable interrupt for event DENORMALINPUT - 5 - 5 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - INVALIDOPERATION - Write '1' to enable interrupt for event INVALIDOPERATION - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - DIVIDEBYZERO - Write '1' to enable interrupt for event DIVIDEBYZERO - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - OVERFLOW - Write '1' to enable interrupt for event OVERFLOW - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - UNDERFLOW - Write '1' to enable interrupt for event UNDERFLOW - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - INEXACT - Write '1' to enable interrupt for event INEXACT - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - DENORMALINPUT - Write '1' to enable interrupt for event DENORMALINPUT - 5 - 5 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - INVALIDOPERATION - Write '1' to disable interrupt for event INVALIDOPERATION - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - DIVIDEBYZERO - Write '1' to disable interrupt for event DIVIDEBYZERO - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - OVERFLOW - Write '1' to disable interrupt for event OVERFLOW - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - UNDERFLOW - Write '1' to disable interrupt for event UNDERFLOW - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - INEXACT - Write '1' to disable interrupt for event INEXACT - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - DENORMALINPUT - Write '1' to disable interrupt for event DENORMALINPUT - 5 - 5 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - - - DCNF_S - Domain configuration management 1 - 0x50000000 - - - - - FPU_S - FPU control peripheral 1 - 0x50000000 - DCNF_S - - - - FPU - 0 - - - - CACHE_S - Cache - 0x50001000 - CACHE - - - - 0 - 0x1000 - registers - - - CACHE - 1 - - CACHE - 0x20 - - - 2 - 0x020 - PROFILING[%s] - Unspecified - CACHE_PROFILING - read-write - 0x400 - - IHIT - Description cluster: Instruction fetch cache hit counter for cache region n, where n=0 means Flash and n=1 means XIP. - 0x000 - read-only - - - HITS - Number of instruction cache hits - 0 - 31 - - - - - IMISS - Description cluster: Instruction fetch cache miss counter for cache region n, where n=0 means Flash and n=1 means XIP. - 0x004 - read-only - - - MISSES - Number of instruction cache misses - 0 - 31 - - - - - DHIT - Description cluster: Data fetch cache hit counter for cache region n, where n=0 means Flash and n=1 means XIP. - 0x008 - read-only - - - HITS - Number of data cache hits - 0 - 31 - - - - - DMISS - Description cluster: Data fetch cache miss counter for cache region n, where n=0 means Flash and n=1 means XIP. - 0x00C - read-only - - - MISSES - Number of data cache misses - 0 - 31 - - - - - - ENABLE - Enable cache. - 0x500 - read-write - - - ENABLE - Enable cache - 0 - 0 - - - Disabled - Disable cache - 0 - - - Enabled - Enable cache - 1 - - - - - - - INVALIDATE - Invalidate the cache. - 0x504 - write-only - - - INVALIDATE - Invalidate the cache - 0 - 0 - - - Invalidate - Invalidate the cache - 1 - - - - - - - ERASE - Erase the cache. - 0x508 - write-only - - - ERASE - Erase the cache - 0 - 0 - - - Erase - Erase cache - 1 - - - - - - - PROFILINGENABLE - Enable the profiling counters. - 0x50C - read-write - - - ENABLE - Enable the profiling counters - 0 - 0 - - - Disable - Disable profiling - 0 - - - Enable - Enable profiling - 1 - - - - - - - PROFILINGCLEAR - Clear the profiling counters. - 0x510 - write-only - - - CLEAR - Clearing the profiling counters - 0 - 0 - - - Clear - Clear the profiling counters - 1 - - - - - - - MODE - Cache mode. Switching from Cache to Ram mode causes the RAM to be cleared. Switching from RAM to Cache mode causes the cache to be invalidated. - 0x514 - read-write - - - MODE - Cache mode - 0 - 0 - - - Cache - Cache mode - 0 - - - Ram - RAM mode - 1 - - - - - - - DEBUGLOCK - Lock debug mode. - 0x518 - read-writeOnce - - - DEBUGLOCK - Lock debug mode - 0 - 0 - - - Unlocked - Debug mode unlocked - 0 - - - Locked - Debug mode locked - 1 - - - - - - - ERASESTATUS - Cache erase status. - 0x51C - read-write - - - ERASESTATUS - Cache erase status - 0 - 0 - - - Idle - Erase is not complete or hasn't started - 0 - - - Finished - Cache erase is finished - 1 - - - - - - - WRITELOCK - Lock cache updates. Prevents updating of cache content on cache misses, but will continue to lookup instruction/data fetches in content already present in the cache. Ignored in RAM mode. - 0x520 - read-write - - - WRITELOCK - Lock cache updates - 0 - 0 - - - Unlocked - Cache updates unlocked - 0 - - - Locked - Cache updates locked - 1 - - - - - - - - - SPU_S - System protection unit - 0x50003000 - SPU - - - - 0 - 0x1000 - registers - - - SPU - 3 - - SPU - 0x20 - - - EVENTS_RAMACCERR - A security violation has been detected for the RAM memory space - 0x100 - read-write - - - EVENTS_RAMACCERR - A security violation has been detected for the RAM memory space - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_FLASHACCERR - A security violation has been detected for the flash memory space - 0x104 - read-write - - - EVENTS_FLASHACCERR - A security violation has been detected for the flash memory space - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_PERIPHACCERR - A security violation has been detected on one or several peripherals - 0x108 - read-write - - - EVENTS_PERIPHACCERR - A security violation has been detected on one or several peripherals - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - PUBLISH_RAMACCERR - Publish configuration for event RAMACCERR - 0x180 - read-write - - - CHIDX - DPPI channel that event RAMACCERR will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_FLASHACCERR - Publish configuration for event FLASHACCERR - 0x184 - read-write - - - CHIDX - DPPI channel that event FLASHACCERR will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_PERIPHACCERR - Publish configuration for event PERIPHACCERR - 0x188 - read-write - - - CHIDX - DPPI channel that event PERIPHACCERR will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - - RAMACCERR - Enable or disable interrupt for event RAMACCERR - 0 - 0 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - FLASHACCERR - Enable or disable interrupt for event FLASHACCERR - 1 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - PERIPHACCERR - Enable or disable interrupt for event PERIPHACCERR - 2 - 2 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - RAMACCERR - Write '1' to enable interrupt for event RAMACCERR - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - FLASHACCERR - Write '1' to enable interrupt for event FLASHACCERR - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - PERIPHACCERR - Write '1' to enable interrupt for event PERIPHACCERR - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - RAMACCERR - Write '1' to disable interrupt for event RAMACCERR - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - FLASHACCERR - Write '1' to disable interrupt for event FLASHACCERR - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - PERIPHACCERR - Write '1' to disable interrupt for event PERIPHACCERR - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - CAP - Show implemented features for the current device - 0x400 - read-only - 0x00000001 - - - TZM - Show Arm TrustZone status - 0 - 0 - - - NotAvailable - Arm TrustZone support not available - 0 - - - Enabled - Arm TrustZone support is available - 1 - - - - - - - CPULOCK - Configure bits to lock down CPU features at runtime - 0x404 - read-write - 0x00000000 - oneToSet - - - LOCKSVTAIRCR - Write '1' to prevent updating the secure interrupt configuration until the next reset - 0 - 0 - - - Locked - Disables writes to the VTOR_S, AIRCR.PRIS, and AIRCR.BFHFNMINS registers - 1 - - - Unlocked - These registers can be updated - 0 - - - - - LOCKNSVTOR - Write '1' to prevent updating the non-secure vector table base address until the next reset - 1 - 1 - - - Locked - The address of the non-secure vector table is locked - 1 - - - Unlocked - The address of the non-secure vector table can be updated - 0 - - - - - LOCKSMPU - Write '1' to prevent updating the secure MPU regions until the next reset - 2 - 2 - - - Locked - Disables writes to the MPU_CTRL, MPU_RNR, MPU_RBAR, MPU_RLAR, MPU_RBAR_An and MPU_RLAR_An from software or from a debug agent connected to the processor in Secure state - 1 - - - Unlocked - These registers can be updated - 0 - - - - - LOCKNSMPU - Write '1' to prevent updating the Non-secure MPU regions until the next reset - 3 - 3 - - - Locked - Disables writes to the MPU_CTRL_NS, MPU_RNR_NS, MPU_RBAR_NS, MPU_RLAR_NS, MPU_RBAR_A_NSn and MPU_RLAR_A_NSn from software or from a debug agent connected to the processor - 1 - - - Unlocked - These registers can be updated - 0 - - - - - LOCKSAU - Write '1' to prevent updating the secure SAU regions until the next reset - 4 - 4 - - - Locked - Disables writes to the SAU_CTRL, SAU_RNR, SAU_RBAR and SAU_RLAR registers from software or from a debug agent connected to the processor - 1 - - - Unlocked - These registers can be updated - 0 - - - - - - - 1 - 0x004 - EXTDOMAIN[%s] - Unspecified - SPU_EXTDOMAIN - read-write - 0x440 - - PERM - Description cluster: Access for bus access generated from the external domain n List capabilities of the external domain n - 0x000 - read-write - 0x00000002 - - - SECUREMAPPING - Define configuration capabilities for TrustZone Cortex-M secure attribute - 0 - 1 - read-only - - - NonSecure - The bus access from this external domain always have the non-secure attribute set - 0 - - - Secure - The bus access from this external domain always have the secure attribute set - 1 - - - UserSelectable - Non-secure or secure attribute for bus access from this domain is defined by the EXTDOMAIN[n].PERM register - 2 - - - - - SECATTR - Peripheral security mapping - 4 - 4 - - - NonSecure - Bus accesses from this domain have the non-secure attribute set - 0 - - - Secure - Bus accesses from this domain have secure attribute set - 1 - - - - - LOCK - 8 - 8 - - - Unlocked - This register can be updated - 0 - - - Locked - The content of this register can't be changed until the next reset - 1 - - - - - - - - 1 - 0x008 - DPPI[%s] - Unspecified - SPU_DPPI - read-write - 0x480 - - PERM - Description cluster: Select between secure and non-secure attribute for the DPPI channels - 0x000 - read-write - 0xFFFFFFFF - - - CHANNEL0 - Select secure attribute - 0 - 0 - - - Secure - Channel 0 has its secure attribute set - 1 - - - NonSecure - Channel 0 has its non-secure attribute set - 0 - - - - - CHANNEL1 - Select secure attribute - 1 - 1 - - - Secure - Channel 1 has its secure attribute set - 1 - - - NonSecure - Channel 1 has its non-secure attribute set - 0 - - - - - CHANNEL2 - Select secure attribute - 2 - 2 - - - Secure - Channel 2 has its secure attribute set - 1 - - - NonSecure - Channel 2 has its non-secure attribute set - 0 - - - - - CHANNEL3 - Select secure attribute - 3 - 3 - - - Secure - Channel 3 has its secure attribute set - 1 - - - NonSecure - Channel 3 has its non-secure attribute set - 0 - - - - - CHANNEL4 - Select secure attribute - 4 - 4 - - - Secure - Channel 4 has its secure attribute set - 1 - - - NonSecure - Channel 4 has its non-secure attribute set - 0 - - - - - CHANNEL5 - Select secure attribute - 5 - 5 - - - Secure - Channel 5 has its secure attribute set - 1 - - - NonSecure - Channel 5 has its non-secure attribute set - 0 - - - - - CHANNEL6 - Select secure attribute - 6 - 6 - - - Secure - Channel 6 has its secure attribute set - 1 - - - NonSecure - Channel 6 has its non-secure attribute set - 0 - - - - - CHANNEL7 - Select secure attribute - 7 - 7 - - - Secure - Channel 7 has its secure attribute set - 1 - - - NonSecure - Channel 7 has its non-secure attribute set - 0 - - - - - CHANNEL8 - Select secure attribute - 8 - 8 - - - Secure - Channel 8 has its secure attribute set - 1 - - - NonSecure - Channel 8 has its non-secure attribute set - 0 - - - - - CHANNEL9 - Select secure attribute - 9 - 9 - - - Secure - Channel 9 has its secure attribute set - 1 - - - NonSecure - Channel 9 has its non-secure attribute set - 0 - - - - - CHANNEL10 - Select secure attribute - 10 - 10 - - - Secure - Channel 10 has its secure attribute set - 1 - - - NonSecure - Channel 10 has its non-secure attribute set - 0 - - - - - CHANNEL11 - Select secure attribute - 11 - 11 - - - Secure - Channel 11 has its secure attribute set - 1 - - - NonSecure - Channel 11 has its non-secure attribute set - 0 - - - - - CHANNEL12 - Select secure attribute - 12 - 12 - - - Secure - Channel 12 has its secure attribute set - 1 - - - NonSecure - Channel 12 has its non-secure attribute set - 0 - - - - - CHANNEL13 - Select secure attribute - 13 - 13 - - - Secure - Channel 13 has its secure attribute set - 1 - - - NonSecure - Channel 13 has its non-secure attribute set - 0 - - - - - CHANNEL14 - Select secure attribute - 14 - 14 - - - Secure - Channel 14 has its secure attribute set - 1 - - - NonSecure - Channel 14 has its non-secure attribute set - 0 - - - - - CHANNEL15 - Select secure attribute - 15 - 15 - - - Secure - Channel 15 has its secure attribute set - 1 - - - NonSecure - Channel 15 has its non-secure attribute set - 0 - - - - - CHANNEL16 - Select secure attribute - 16 - 16 - - - Secure - Channel 16 has its secure attribute set - 1 - - - NonSecure - Channel 16 has its non-secure attribute set - 0 - - - - - CHANNEL17 - Select secure attribute - 17 - 17 - - - Secure - Channel 17 has its secure attribute set - 1 - - - NonSecure - Channel 17 has its non-secure attribute set - 0 - - - - - CHANNEL18 - Select secure attribute - 18 - 18 - - - Secure - Channel 18 has its secure attribute set - 1 - - - NonSecure - Channel 18 has its non-secure attribute set - 0 - - - - - CHANNEL19 - Select secure attribute - 19 - 19 - - - Secure - Channel 19 has its secure attribute set - 1 - - - NonSecure - Channel 19 has its non-secure attribute set - 0 - - - - - CHANNEL20 - Select secure attribute - 20 - 20 - - - Secure - Channel 20 has its secure attribute set - 1 - - - NonSecure - Channel 20 has its non-secure attribute set - 0 - - - - - CHANNEL21 - Select secure attribute - 21 - 21 - - - Secure - Channel 21 has its secure attribute set - 1 - - - NonSecure - Channel 21 has its non-secure attribute set - 0 - - - - - CHANNEL22 - Select secure attribute - 22 - 22 - - - Secure - Channel 22 has its secure attribute set - 1 - - - NonSecure - Channel 22 has its non-secure attribute set - 0 - - - - - CHANNEL23 - Select secure attribute - 23 - 23 - - - Secure - Channel 23 has its secure attribute set - 1 - - - NonSecure - Channel 23 has its non-secure attribute set - 0 - - - - - CHANNEL24 - Select secure attribute - 24 - 24 - - - Secure - Channel 24 has its secure attribute set - 1 - - - NonSecure - Channel 24 has its non-secure attribute set - 0 - - - - - CHANNEL25 - Select secure attribute - 25 - 25 - - - Secure - Channel 25 has its secure attribute set - 1 - - - NonSecure - Channel 25 has its non-secure attribute set - 0 - - - - - CHANNEL26 - Select secure attribute - 26 - 26 - - - Secure - Channel 26 has its secure attribute set - 1 - - - NonSecure - Channel 26 has its non-secure attribute set - 0 - - - - - CHANNEL27 - Select secure attribute - 27 - 27 - - - Secure - Channel 27 has its secure attribute set - 1 - - - NonSecure - Channel 27 has its non-secure attribute set - 0 - - - - - CHANNEL28 - Select secure attribute - 28 - 28 - - - Secure - Channel 28 has its secure attribute set - 1 - - - NonSecure - Channel 28 has its non-secure attribute set - 0 - - - - - CHANNEL29 - Select secure attribute - 29 - 29 - - - Secure - Channel 29 has its secure attribute set - 1 - - - NonSecure - Channel 29 has its non-secure attribute set - 0 - - - - - CHANNEL30 - Select secure attribute - 30 - 30 - - - Secure - Channel 30 has its secure attribute set - 1 - - - NonSecure - Channel 30 has its non-secure attribute set - 0 - - - - - CHANNEL31 - Select secure attribute - 31 - 31 - - - Secure - Channel 31 has its secure attribute set - 1 - - - NonSecure - Channel 31 has its non-secure attribute set - 0 - - - - - - - LOCK - Description cluster: Prevent further modification of the corresponding PERM register - 0x004 - read-write - 0x00000000 - - - LOCK - 0 - 0 - - - Locked - DPPI[n].PERM register can't be changed until next reset - 1 - - - Unlocked - DPPI[n].PERM register content can be changed - 0 - - - - - - - - 2 - 0x008 - GPIOPORT[%s] - Unspecified - SPU_GPIOPORT - read-write - 0x4C0 - - PERM - Description cluster: Select between secure and non-secure attribute for pins 0 to 31 of port n - 0x000 - read-write - 0xFFFFFFFF - - - PIN0 - Select secure attribute attribute for PIN 0. - 0 - 0 - - - Secure - Pin 0 has its secure attribute set - 1 - - - NonSecure - Pin 0 has its non-secure attribute set - 0 - - - - - PIN1 - Select secure attribute attribute for PIN 1. - 1 - 1 - - - Secure - Pin 1 has its secure attribute set - 1 - - - NonSecure - Pin 1 has its non-secure attribute set - 0 - - - - - PIN2 - Select secure attribute attribute for PIN 2. - 2 - 2 - - - Secure - Pin 2 has its secure attribute set - 1 - - - NonSecure - Pin 2 has its non-secure attribute set - 0 - - - - - PIN3 - Select secure attribute attribute for PIN 3. - 3 - 3 - - - Secure - Pin 3 has its secure attribute set - 1 - - - NonSecure - Pin 3 has its non-secure attribute set - 0 - - - - - PIN4 - Select secure attribute attribute for PIN 4. - 4 - 4 - - - Secure - Pin 4 has its secure attribute set - 1 - - - NonSecure - Pin 4 has its non-secure attribute set - 0 - - - - - PIN5 - Select secure attribute attribute for PIN 5. - 5 - 5 - - - Secure - Pin 5 has its secure attribute set - 1 - - - NonSecure - Pin 5 has its non-secure attribute set - 0 - - - - - PIN6 - Select secure attribute attribute for PIN 6. - 6 - 6 - - - Secure - Pin 6 has its secure attribute set - 1 - - - NonSecure - Pin 6 has its non-secure attribute set - 0 - - - - - PIN7 - Select secure attribute attribute for PIN 7. - 7 - 7 - - - Secure - Pin 7 has its secure attribute set - 1 - - - NonSecure - Pin 7 has its non-secure attribute set - 0 - - - - - PIN8 - Select secure attribute attribute for PIN 8. - 8 - 8 - - - Secure - Pin 8 has its secure attribute set - 1 - - - NonSecure - Pin 8 has its non-secure attribute set - 0 - - - - - PIN9 - Select secure attribute attribute for PIN 9. - 9 - 9 - - - Secure - Pin 9 has its secure attribute set - 1 - - - NonSecure - Pin 9 has its non-secure attribute set - 0 - - - - - PIN10 - Select secure attribute attribute for PIN 10. - 10 - 10 - - - Secure - Pin 10 has its secure attribute set - 1 - - - NonSecure - Pin 10 has its non-secure attribute set - 0 - - - - - PIN11 - Select secure attribute attribute for PIN 11. - 11 - 11 - - - Secure - Pin 11 has its secure attribute set - 1 - - - NonSecure - Pin 11 has its non-secure attribute set - 0 - - - - - PIN12 - Select secure attribute attribute for PIN 12. - 12 - 12 - - - Secure - Pin 12 has its secure attribute set - 1 - - - NonSecure - Pin 12 has its non-secure attribute set - 0 - - - - - PIN13 - Select secure attribute attribute for PIN 13. - 13 - 13 - - - Secure - Pin 13 has its secure attribute set - 1 - - - NonSecure - Pin 13 has its non-secure attribute set - 0 - - - - - PIN14 - Select secure attribute attribute for PIN 14. - 14 - 14 - - - Secure - Pin 14 has its secure attribute set - 1 - - - NonSecure - Pin 14 has its non-secure attribute set - 0 - - - - - PIN15 - Select secure attribute attribute for PIN 15. - 15 - 15 - - - Secure - Pin 15 has its secure attribute set - 1 - - - NonSecure - Pin 15 has its non-secure attribute set - 0 - - - - - PIN16 - Select secure attribute attribute for PIN 16. - 16 - 16 - - - Secure - Pin 16 has its secure attribute set - 1 - - - NonSecure - Pin 16 has its non-secure attribute set - 0 - - - - - PIN17 - Select secure attribute attribute for PIN 17. - 17 - 17 - - - Secure - Pin 17 has its secure attribute set - 1 - - - NonSecure - Pin 17 has its non-secure attribute set - 0 - - - - - PIN18 - Select secure attribute attribute for PIN 18. - 18 - 18 - - - Secure - Pin 18 has its secure attribute set - 1 - - - NonSecure - Pin 18 has its non-secure attribute set - 0 - - - - - PIN19 - Select secure attribute attribute for PIN 19. - 19 - 19 - - - Secure - Pin 19 has its secure attribute set - 1 - - - NonSecure - Pin 19 has its non-secure attribute set - 0 - - - - - PIN20 - Select secure attribute attribute for PIN 20. - 20 - 20 - - - Secure - Pin 20 has its secure attribute set - 1 - - - NonSecure - Pin 20 has its non-secure attribute set - 0 - - - - - PIN21 - Select secure attribute attribute for PIN 21. - 21 - 21 - - - Secure - Pin 21 has its secure attribute set - 1 - - - NonSecure - Pin 21 has its non-secure attribute set - 0 - - - - - PIN22 - Select secure attribute attribute for PIN 22. - 22 - 22 - - - Secure - Pin 22 has its secure attribute set - 1 - - - NonSecure - Pin 22 has its non-secure attribute set - 0 - - - - - PIN23 - Select secure attribute attribute for PIN 23. - 23 - 23 - - - Secure - Pin 23 has its secure attribute set - 1 - - - NonSecure - Pin 23 has its non-secure attribute set - 0 - - - - - PIN24 - Select secure attribute attribute for PIN 24. - 24 - 24 - - - Secure - Pin 24 has its secure attribute set - 1 - - - NonSecure - Pin 24 has its non-secure attribute set - 0 - - - - - PIN25 - Select secure attribute attribute for PIN 25. - 25 - 25 - - - Secure - Pin 25 has its secure attribute set - 1 - - - NonSecure - Pin 25 has its non-secure attribute set - 0 - - - - - PIN26 - Select secure attribute attribute for PIN 26. - 26 - 26 - - - Secure - Pin 26 has its secure attribute set - 1 - - - NonSecure - Pin 26 has its non-secure attribute set - 0 - - - - - PIN27 - Select secure attribute attribute for PIN 27. - 27 - 27 - - - Secure - Pin 27 has its secure attribute set - 1 - - - NonSecure - Pin 27 has its non-secure attribute set - 0 - - - - - PIN28 - Select secure attribute attribute for PIN 28. - 28 - 28 - - - Secure - Pin 28 has its secure attribute set - 1 - - - NonSecure - Pin 28 has its non-secure attribute set - 0 - - - - - PIN29 - Select secure attribute attribute for PIN 29. - 29 - 29 - - - Secure - Pin 29 has its secure attribute set - 1 - - - NonSecure - Pin 29 has its non-secure attribute set - 0 - - - - - PIN30 - Select secure attribute attribute for PIN 30. - 30 - 30 - - - Secure - Pin 30 has its secure attribute set - 1 - - - NonSecure - Pin 30 has its non-secure attribute set - 0 - - - - - PIN31 - Select secure attribute attribute for PIN 31. - 31 - 31 - - - Secure - Pin 31 has its secure attribute set - 1 - - - NonSecure - Pin 31 has its non-secure attribute set - 0 - - - - - - - LOCK - Description cluster: Prevent further modification of the corresponding PERM register - 0x004 - read-write - 0x00000000 - - - LOCK - 0 - 0 - - - Locked - GPIOPORT[n].PERM register can't be changed until next reset - 1 - - - Unlocked - GPIOPORT[n].PERM register content can be changed - 0 - - - - - - - - 2 - 0x008 - FLASHNSC[%s] - Unspecified - SPU_FLASHNSC - read-write - 0x500 - - REGION - Description cluster: Define which flash region can contain the non-secure callable (NSC) region n - 0x000 - read-write - 0x00000000 - - - REGION - Region number - 0 - 5 - - - LOCK - 8 - 8 - - - Unlocked - This register can be updated - 0 - - - Locked - The content of this register can't be changed until the next reset - 1 - - - - - - - SIZE - Description cluster: Define the size of the non-secure callable (NSC) region n - 0x004 - read-write - 0x00000000 - - - SIZE - Size of the non-secure callable (NSC) region n - 0 - 3 - - - Disabled - The region n is not defined as a non-secure callable region. Normal security attributes (secure or non-secure) are enforced. - 0 - - - 32 - The region n is defined as non-secure callable with size 32 bytes - 1 - - - 64 - The region n is defined as non-secure callable with size 64 bytes - 2 - - - 128 - The region n is defined as non-secure callable with size 128 bytes - 3 - - - 256 - The region n is defined as non-secure callable with size 256 bytes - 4 - - - 512 - The region n is defined as non-secure callable with size 512 bytes - 5 - - - 1024 - The region n is defined as non-secure callable with size 1024 bytes - 6 - - - 2048 - The region n is defined as non-secure callable with size 2048 bytes - 7 - - - 4096 - The region n is defined as non-secure callable with size 4096 bytes - 8 - - - - - LOCK - 8 - 8 - - - Unlocked - This register can be updated - 0 - - - Locked - The content of this register can't be changed until the next reset - 1 - - - - - - - - 2 - 0x008 - RAMNSC[%s] - Unspecified - SPU_RAMNSC - read-write - 0x540 - - REGION - Description cluster: Define which RAM region can contain the non-secure callable (NSC) region n - 0x000 - read-write - 0x00000000 - - - REGION - Region number - 0 - 5 - - - LOCK - 8 - 8 - - - Unlocked - This register can be updated - 0 - - - Locked - The content of this register can't be changed until the next reset - 1 - - - - - - - SIZE - Description cluster: Define the size of the non-secure callable (NSC) region n - 0x004 - read-write - 0x00000000 - - - SIZE - Size of the non-secure callable (NSC) region n - 0 - 3 - - - Disabled - The region n is not defined as a non-secure callable region. Normal security attributes (secure or non-secure) are enforced. - 0 - - - 32 - The region n is defined as non-secure callable with size 32 bytes - 1 - - - 64 - The region n is defined as non-secure callable with size 64 bytes - 2 - - - 128 - The region n is defined as non-secure callable with size 128 bytes - 3 - - - 256 - The region n is defined as non-secure callable with size 256 bytes - 4 - - - 512 - The region n is defined as non-secure callable with size 512 bytes - 5 - - - 1024 - The region n is defined as non-secure callable with size 1024 bytes - 6 - - - 2048 - The region n is defined as non-secure callable with size 2048 bytes - 7 - - - 4096 - The region n is defined as non-secure callable with size 4096 bytes - 8 - - - - - LOCK - 8 - 8 - - - Unlocked - This register can be updated - 0 - - - Locked - The content of this register can't be changed until the next reset - 1 - - - - - - - - 64 - 0x004 - FLASHREGION[%s] - Unspecified - SPU_FLASHREGION - read-write - 0x600 - - PERM - Description cluster: Access permissions for flash region n - 0x000 - read-write - 0x00000017 - - - EXECUTE - Configure instruction fetch permissions from flash region n - 0 - 0 - - - Enable - Allow instruction fetches from flash region n - 1 - - - Disable - Block instruction fetches from flash region n - 0 - - - - - WRITE - Configure write permission for flash region n - 1 - 1 - - - Enable - Allow write operation to region n - 1 - - - Disable - Block write operation to region n - 0 - - - - - READ - Configure read permissions for flash region n - 2 - 2 - - - Enable - Allow read operation from flash region n - 1 - - - Disable - Block read operation from flash region n - 0 - - - - - SECATTR - Security attribute for flash region n - 4 - 4 - - - Non_Secure - Flash region n security attribute is non-secure - 0 - - - Secure - Flash region n security attribute is secure - 1 - - - - - LOCK - 8 - 8 - - - Unlocked - This register can be updated - 0 - - - Locked - The content of this register can't be changed until the next reset - 1 - - - - - - - - 64 - 0x004 - RAMREGION[%s] - Unspecified - SPU_RAMREGION - read-write - 0x700 - - PERM - Description cluster: Access permissions for RAM region n - 0x000 - read-write - 0x00000017 - - - EXECUTE - Configure instruction fetch permissions from RAM region n - 0 - 0 - - - Enable - Allow instruction fetches from RAM region n - 1 - - - Disable - Block instruction fetches from RAM region n - 0 - - - - - WRITE - Configure write permission for RAM region n - 1 - 1 - - - Enable - Allow write operation to RAM region n - 1 - - - Disable - Block write operation to RAM region n - 0 - - - - - READ - Configure read permissions for RAM region n - 2 - 2 - - - Enable - Allow read operation from RAM region n - 1 - - - Disable - Block read operation from RAM region n - 0 - - - - - SECATTR - Security attribute for RAM region n - 4 - 4 - - - Non_Secure - RAM region n security attribute is non-secure - 0 - - - Secure - RAM region n security attribute is secure - 1 - - - - - LOCK - 8 - 8 - - - Unlocked - This register can be updated - 0 - - - Locked - The content of this register can't be changed until the next reset - 1 - - - - - - - - 256 - 0x004 - PERIPHID[%s] - Unspecified - SPU_PERIPHID - read-write - 0x800 - - PERM - Description cluster: List capabilities and access permissions for the peripheral with ID n - 0x000 - read-write - 0x00000012 - - - SECUREMAPPING - Define configuration capabilities for Arm TrustZone Cortex-M secure attribute - 0 - 1 - read-only - - - NonSecure - This peripheral is always accessible as a non-secure peripheral - 0 - - - Secure - This peripheral is always accessible as a secure peripheral - 1 - - - UserSelectable - Non-secure or secure attribute for this peripheral is defined by the PERIPHID[n].PERM register - 2 - - - Split - This peripheral implements the split security mechanism. Non-secure or secure attribute for this peripheral is defined by the PERIPHID[n].PERM register. - 3 - - - - - DMA - Indicates if the peripheral has DMA capabilities and if DMA transfer can be assigned to a different security attribute than the peripheral itself - 2 - 3 - read-only - - - NoDMA - Peripheral has no DMA capability - 0 - - - NoSeparateAttribute - Peripheral has DMA and DMA transfers always have the same security attribute as assigned to the peripheral - 1 - - - SeparateAttribute - Peripheral has DMA and DMA transfers can have a different security attribute than the one assigned to the peripheral - 2 - - - - - SECATTR - Peripheral security mapping - 4 - 4 - - - Secure - Peripheral is mapped in secure peripheral address space - 1 - - - NonSecure - If SECUREMAPPING == UserSelectable: Peripheral is mapped in non-secure peripheral address space. If SECUREMAPPING == Split: Peripheral is mapped in non-secure and secure peripheral address space. - 0 - - - - - DMASEC - Security attribution for the DMA transfer - 5 - 5 - - - Secure - DMA transfers initiated by this peripheral have the secure attribute set - 1 - - - NonSecure - DMA transfers initiated by this peripheral have the non-secure attribute set - 0 - - - - - LOCK - 8 - 8 - - - Unlocked - This register can be updated - 0 - - - Locked - The content of this register can't be changed until the next reset - 1 - - - - - PRESENT - Indicate if a peripheral is present with ID n - 31 - 31 - read-only - - - NotPresent - Peripheral is not present - 0 - - - IsPresent - Peripheral is present - 1 - - - - - - - - - - OSCILLATORS_NS - Oscillator control 0 - 0x40004000 - OSCILLATORS - - - - 0 - 0x1000 - registers - - OSCILLATORS - 0x20 - - - XOSC32MCAPS - Programmable capacitance of XC1 and XC2 - 0x5C4 - read-write - - - CAPVALUE - Value representing capacitance, calculated using provided equation - 0 - 4 - - - ENABLE - Enable on-chip capacitors on XC1 and XC2 - 8 - 8 - - - Disabled - Capacitor disabled (use external caps) - 0 - - - Enabled - Capacitor enabled - 1 - - - - - - - XOSC32KI - Unspecified - OSCILLATORS_XOSC32KI - read-write - 0x6C0 - - BYPASS - Enable or disable bypass of LFCLK crystal oscillator with external clock source - 0x000 - read-write - - - BYPASS - Enable or disable bypass of LFCLK crystal oscillator with external clock source - 0 - 0 - - - Disabled - Disable (use with crystal or low-swing external source) - 0 - - - Enabled - Enable (use with rail-to-rail external source) - 1 - - - - - - - INTCAP - Control usage of internal load capacitors - 0x010 - read-write - - - INTCAP - Control usage of internal load capacitors - 0 - 1 - - - External - Use external load capacitors - 0 - - - C6PF - 6 pF internal load capacitance - 1 - - - C7PF - 7 pF internal load capacitance - 2 - - - C9PF - 9 pF internal load capacitance - 3 - - - - - - - - - - REGULATORS_NS - Voltage regulators 0 - 0x40004000 - OSCILLATORS_NS - REGULATORS - - - - 0 - 0x1000 - registers - - REGULATORS - 0x20 - - - MAINREGSTATUS - Main supply status - 0x428 - read-only - 0x00000000 - - - VREGH - VREGH status - 0 - 0 - - - Inactive - Normal voltage mode. Voltage supplied on VDD and VDDH. - 0 - - - Active - High voltage mode. Voltage supplied on VDDH. - 1 - - - - - - - SYSTEMOFF - System OFF register - 0x500 - write-only - - - SYSTEMOFF - Enable System OFF mode - 0 - 0 - - - Enter - Enable System OFF mode - 1 - - - - - - - POFCON - Power-fail comparator configuration - 0x510 - read-write - - - POF - Enable or disable power-fail comparator - 0 - 0 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - THRESHOLD - Power-fail comparator threshold setting - 1 - 4 - - - V19 - Set threshold to 1.9 V - 6 - - - V20 - Set threshold to 2.0 V - 7 - - - V21 - Set threshold to 2.1 V - 8 - - - V22 - Set threshold to 2.2 V - 9 - - - V23 - Set threshold to 2.3 V - 10 - - - V24 - Set threshold to 2.4 V - 11 - - - V25 - Set threshold to 2.5 V - 12 - - - V26 - Set threshold to 2.6 V - 13 - - - V27 - Set threshold to 2.7 V - 14 - - - V28 - Set threshold to 2.8 V - 15 - - - - - THRESHOLDVDDH - Power-fail comparator threshold setting for voltage supply on VDDH - 8 - 11 - - - V27 - Set threshold to 2.7 V - 0 - - - V28 - Set threshold to 2.8 V - 1 - - - V29 - Set threshold to 2.9 V - 2 - - - V30 - Set threshold to 3.0 V - 3 - - - V31 - Set threshold to 3.1 V - 4 - - - V32 - Set threshold to 3.2 V - 5 - - - V33 - Set threshold to 3.3 V - 6 - - - V34 - Set threshold to 3.4 V - 7 - - - V35 - Set threshold to 3.5 V - 8 - - - V36 - Set threshold to 3.6 V - 9 - - - V37 - Set threshold to 3.7 V - 10 - - - V38 - Set threshold to 3.8 V - 11 - - - V39 - Set threshold to 3.9 V - 12 - - - V40 - Set threshold to 4.0 V - 13 - - - V41 - Set threshold to 4.1 V - 14 - - - V42 - Set threshold to 4.2 V - 15 - - - - - - - VREGMAIN - Unspecified - REGULATORS_VREGMAIN - read-write - 0x704 - - DCDCEN - DC/DC enable register for VREGMAIN - 0x000 - read-write - 0x00000000 - - - DCDCEN - Enable or disable DC/DC converter - 0 - 0 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - - VREGRADIO - Unspecified - REGULATORS_VREGRADIO - read-write - 0x900 - - DCDCEN - DC/DC enable register for VREGRADIO - 0x004 - read-write - - - DCDCEN - Enable or disable DC/DC converter - 0 - 0 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - - VREGH - Unspecified - REGULATORS_VREGH - read-write - 0xB00 - - DCDCEN - DC/DC enable register for VREGH - 0x000 - read-write - - - DCDCEN - Enable or disable DC/DC converter - 0 - 0 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - - - - OSCILLATORS_S - Oscillator control 1 - 0x50004000 - - - - - REGULATORS_S - Voltage regulators 1 - 0x50004000 - OSCILLATORS_S - - - - - CLOCK_NS - Clock management 0 - 0x40005000 - CLOCK - - - - 0 - 0x1000 - registers - - - CLOCK_POWER - 5 - - CLOCK - 0x20 - - - TASKS_HFCLKSTART - Start HFCLK128M/HFCLK64M source as selected in HFCLKSRC - 0x000 - write-only - - - TASKS_HFCLKSTART - Start HFCLK128M/HFCLK64M source as selected in HFCLKSRC - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_HFCLKSTOP - Stop HFCLK128M/HFCLK64M source - 0x004 - write-only - - - TASKS_HFCLKSTOP - Stop HFCLK128M/HFCLK64M source - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_LFCLKSTART - Start LFCLK source as selected in LFCLKSRC - 0x008 - write-only - - - TASKS_LFCLKSTART - Start LFCLK source as selected in LFCLKSRC - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_LFCLKSTOP - Stop LFCLK source - 0x00C - write-only - - - TASKS_LFCLKSTOP - Stop LFCLK source - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_CAL - Start calibration of LFRC oscillator - 0x010 - write-only - - - TASKS_CAL - Start calibration of LFRC oscillator - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_HFCLKAUDIOSTART - Start HFCLKAUDIO source - 0x018 - write-only - - - TASKS_HFCLKAUDIOSTART - Start HFCLKAUDIO source - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_HFCLKAUDIOSTOP - Stop HFCLKAUDIO source - 0x01C - write-only - - - TASKS_HFCLKAUDIOSTOP - Stop HFCLKAUDIO source - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_HFCLK192MSTART - Start HFCLK192M source as selected in HFCLK192MSRC - 0x020 - write-only - - - TASKS_HFCLK192MSTART - Start HFCLK192M source as selected in HFCLK192MSRC - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_HFCLK192MSTOP - Stop HFCLK192M source - 0x024 - write-only - - - TASKS_HFCLK192MSTOP - Stop HFCLK192M source - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - SUBSCRIBE_HFCLKSTART - Subscribe configuration for task HFCLKSTART - 0x080 - read-write - - - CHIDX - DPPI channel that task HFCLKSTART will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_HFCLKSTOP - Subscribe configuration for task HFCLKSTOP - 0x084 - read-write - - - CHIDX - DPPI channel that task HFCLKSTOP will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_LFCLKSTART - Subscribe configuration for task LFCLKSTART - 0x088 - read-write - - - CHIDX - DPPI channel that task LFCLKSTART will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_LFCLKSTOP - Subscribe configuration for task LFCLKSTOP - 0x08C - read-write - - - CHIDX - DPPI channel that task LFCLKSTOP will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_CAL - Subscribe configuration for task CAL - 0x090 - read-write - - - CHIDX - DPPI channel that task CAL will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_HFCLKAUDIOSTART - Subscribe configuration for task HFCLKAUDIOSTART - 0x098 - read-write - - - CHIDX - DPPI channel that task HFCLKAUDIOSTART will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_HFCLKAUDIOSTOP - Subscribe configuration for task HFCLKAUDIOSTOP - 0x09C - read-write - - - CHIDX - DPPI channel that task HFCLKAUDIOSTOP will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_HFCLK192MSTART - Subscribe configuration for task HFCLK192MSTART - 0x0A0 - read-write - - - CHIDX - DPPI channel that task HFCLK192MSTART will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_HFCLK192MSTOP - Subscribe configuration for task HFCLK192MSTOP - 0x0A4 - read-write - - - CHIDX - DPPI channel that task HFCLK192MSTOP will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - EVENTS_HFCLKSTARTED - HFCLK128M/HFCLK64M source started - 0x100 - read-write - - - EVENTS_HFCLKSTARTED - HFCLK128M/HFCLK64M source started - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_LFCLKSTARTED - LFCLK source started - 0x104 - read-write - - - EVENTS_LFCLKSTARTED - LFCLK source started - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_DONE - Calibration of LFRC oscillator complete event - 0x11C - read-write - - - EVENTS_DONE - Calibration of LFRC oscillator complete event - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_HFCLKAUDIOSTARTED - HFCLKAUDIO source started - 0x120 - read-write - - - EVENTS_HFCLKAUDIOSTARTED - HFCLKAUDIO source started - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_HFCLK192MSTARTED - HFCLK192M source started - 0x124 - read-write - - - EVENTS_HFCLK192MSTARTED - HFCLK192M source started - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - PUBLISH_HFCLKSTARTED - Publish configuration for event HFCLKSTARTED - 0x180 - read-write - - - CHIDX - DPPI channel that event HFCLKSTARTED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_LFCLKSTARTED - Publish configuration for event LFCLKSTARTED - 0x184 - read-write - - - CHIDX - DPPI channel that event LFCLKSTARTED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_DONE - Publish configuration for event DONE - 0x19C - read-write - - - CHIDX - DPPI channel that event DONE will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_HFCLKAUDIOSTARTED - Publish configuration for event HFCLKAUDIOSTARTED - 0x1A0 - read-write - - - CHIDX - DPPI channel that event HFCLKAUDIOSTARTED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_HFCLK192MSTARTED - Publish configuration for event HFCLK192MSTARTED - 0x1A4 - read-write - - - CHIDX - DPPI channel that event HFCLK192MSTARTED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - - HFCLKSTARTED - Enable or disable interrupt for event HFCLKSTARTED - 0 - 0 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - LFCLKSTARTED - Enable or disable interrupt for event LFCLKSTARTED - 1 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - DONE - Enable or disable interrupt for event DONE - 7 - 7 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - HFCLKAUDIOSTARTED - Enable or disable interrupt for event HFCLKAUDIOSTARTED - 8 - 8 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - HFCLK192MSTARTED - Enable or disable interrupt for event HFCLK192MSTARTED - 9 - 9 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - HFCLKSTARTED - Write '1' to enable interrupt for event HFCLKSTARTED - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - LFCLKSTARTED - Write '1' to enable interrupt for event LFCLKSTARTED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - DONE - Write '1' to enable interrupt for event DONE - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - HFCLKAUDIOSTARTED - Write '1' to enable interrupt for event HFCLKAUDIOSTARTED - 8 - 8 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - HFCLK192MSTARTED - Write '1' to enable interrupt for event HFCLK192MSTARTED - 9 - 9 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - HFCLKSTARTED - Write '1' to disable interrupt for event HFCLKSTARTED - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - LFCLKSTARTED - Write '1' to disable interrupt for event LFCLKSTARTED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - DONE - Write '1' to disable interrupt for event DONE - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - HFCLKAUDIOSTARTED - Write '1' to disable interrupt for event HFCLKAUDIOSTARTED - 8 - 8 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - HFCLK192MSTARTED - Write '1' to disable interrupt for event HFCLK192MSTARTED - 9 - 9 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - INTPEND - Pending interrupts - 0x30C - read-only - - - HFCLKSTARTED - Read pending status of interrupt for event HFCLKSTARTED - 0 - 0 - - read - - NotPending - Read: Not pending - 0 - - - Pending - Read: Pending - 1 - - - - - LFCLKSTARTED - Read pending status of interrupt for event LFCLKSTARTED - 1 - 1 - - read - - NotPending - Read: Not pending - 0 - - - Pending - Read: Pending - 1 - - - - - DONE - Read pending status of interrupt for event DONE - 7 - 7 - - read - - NotPending - Read: Not pending - 0 - - - Pending - Read: Pending - 1 - - - - - HFCLKAUDIOSTARTED - Read pending status of interrupt for event HFCLKAUDIOSTARTED - 8 - 8 - - read - - NotPending - Read: Not pending - 0 - - - Pending - Read: Pending - 1 - - - - - HFCLK192MSTARTED - Read pending status of interrupt for event HFCLK192MSTARTED - 9 - 9 - - read - - NotPending - Read: Not pending - 0 - - - Pending - Read: Pending - 1 - - - - - - - HFCLKRUN - Status indicating that HFCLKSTART task has been triggered - 0x408 - read-only - - - STATUS - HFCLKSTART task triggered or not - 0 - 0 - - - NotTriggered - Task not triggered - 0 - - - Triggered - Task triggered - 1 - - - - - - - HFCLKSTAT - Status indicating which HFCLK128M/HFCLK64M source is running This register value in any CLOCK instance reflects status only due to configurations/actions in that CLOCK instance. - 0x40C - read-only - - - SRC - Active clock source - 0 - 0 - - - HFINT - Clock source: HFINT - 128 MHz on-chip oscillator - 0 - - - HFXO - Clock source: HFXO - 128 MHz clock derived from external 32 MHz crystal oscillator - 1 - - - - - ALWAYSRUNNING - ALWAYSRUN activated - 4 - 4 - - - NotRunning - Automatic clock control enabled - 0 - - - Running - Oscillator is always running - 1 - - - - - STATE - HFCLK state - 16 - 16 - - - NotRunning - HFCLK not running - 0 - - - Running - HFCLK running - 1 - - - - - - - LFCLKRUN - Status indicating that LFCLKSTART task has been triggered - 0x414 - read-only - - - STATUS - LFCLKSTART task triggered or not - 0 - 0 - - - NotTriggered - Task not triggered - 0 - - - Triggered - Task triggered - 1 - - - - - - - LFCLKSTAT - Status indicating which LFCLK source is running This register value in any CLOCK instance reflects status only due to configurations/actions in that CLOCK instance. - 0x418 - read-only - - - SRC - Active clock source - 0 - 1 - - - LFRC - 32.768 kHz RC oscillator - 1 - - - LFXO - 32.768 kHz crystal oscillator - 2 - - - LFSYNT - 32.768 kHz synthesized from HFCLK - 3 - - - - - ALWAYSRUNNING - ALWAYSRUN activated - 4 - 4 - - - NotRunning - Automatic clock control enabled - 0 - - - Running - Oscillator is always running - 1 - - - - - STATE - LFCLK state - 16 - 16 - - - NotRunning - LFCLK not running - 0 - - - Running - LFCLK running - 1 - - - - - - - LFCLKSRCCOPY - Copy of LFCLKSRC register, set when LFCLKSTART task was triggered - 0x41C - read-only - 0x00000001 - - - SRC - Clock source - 0 - 1 - - - LFRC - 32.768 kHz RC oscillator - 1 - - - LFXO - 32.768 kHz crystal oscillator - 2 - - - LFSYNT - 32.768 kHz synthesized from HFCLK - 3 - - - - - - - HFCLKAUDIORUN - Status indicating that HFCLKAUDIOSTART task has been triggered - 0x450 - read-only - - - STATUS - HFCLKAUDIOSTART task triggered or not - 0 - 0 - - - NotTriggered - Task not triggered - 0 - - - Triggered - Task triggered - 1 - - - - - - - HFCLKAUDIOSTAT - Status indicating which HFCLKAUDIO source is running - 0x454 - read-only - - - ALWAYSRUNNING - ALWAYSRUN activated - 4 - 4 - - - NotRunning - Automatic clock control enabled - 0 - - - Running - Oscillator is always running - 1 - - - - - STATE - HFCLKAUDIO state - 16 - 16 - - - NotRunning - HFCLKAUDIO not running - 0 - - - Running - HFCLKAUDIO running - 1 - - - - - - - HFCLK192MRUN - Status indicating that HFCLK192MSTART task has been triggered - 0x458 - read-only - - - STATUS - HFCLK192MSTART task triggered or not - 0 - 0 - - - NotTriggered - Task not triggered - 0 - - - Triggered - Task triggered - 1 - - - - - - - HFCLK192MSTAT - Status indicating which HFCLK192M source is running - 0x45C - read-only - - - SRC - Active clock source - 0 - 0 - - - HFINT - Clock source: HFINT - on-chip oscillator - 0 - - - HFXO - Clock source: HFXO - derived from external 32 MHz crystal oscillator - 1 - - - - - ALWAYSRUNNING - ALWAYSRUN activated - 4 - 4 - - - NotRunning - Automatic clock control enabled - 0 - - - Running - Oscillator is always running - 1 - - - - - STATE - HFCLK192M state - 16 - 16 - - - NotRunning - HFCLK192M not running - 0 - - - Running - HFCLK192M running - 1 - - - - - - - HFCLKSRC - Clock source for HFCLK128M/HFCLK64M - 0x514 - read-write - 0x00000001 - - - SRC - Select which HFCLK source is started by the HFCLKSTART task - 0 - 0 - - - HFINT - HFCLKSTART task starts HFINT oscillator - 0 - - - HFXO - HFCLKSTART task starts HFXO oscillator - 1 - - - - - - - LFCLKSRC - Clock source for LFCLK - 0x518 - read-write - 0x00000001 - - - SRC - Select which LFCLK source is started by the LFCLKSTART task - 0 - 1 - - - LFRC - 32.768 kHz RC oscillator - 1 - - - LFXO - 32.768 kHz crystal oscillator - 2 - - - LFSYNT - 32.768 kHz synthesized from HFCLK - 3 - - - - - - - HFCLKCTRL - HFCLK128M frequency configuration - 0x558 - read-write - 0x00000001 - - - HCLK - High frequency clock HCLK - 0 - 1 - - - Div1 - Divide HFCLK by 1 - 0 - - - Div2 - Divide HFCLK by 2 - 1 - - - - - - - HFCLKAUDIO - Unspecified - CLOCK_HFCLKAUDIO - read-write - 0x55C - - FREQUENCY - Audio PLL frequency in 11.176 MHz - 11.402 MHz or 12.165 MHz - 12.411 MHz frequency bands - 0x000 - read-write - 0x00009BAE - - - FREQUENCY - Frequency 0: 10.666 MHz 65535: 13.333 MHz - 0 - 15 - - - - - - HFCLKALWAYSRUN - Automatic or manual control of HFCLK128M/HFCLK64M - 0x570 - read-write - - - ALWAYSRUN - Ensure clock is always running - 0 - 0 - - - Automatic - Use automatic clock control - 0 - - - AlwaysRun - Ensure clock is always running - 1 - - - - - - - LFCLKALWAYSRUN - Automatic or manual control of LFCLK - 0x574 - read-write - - - ALWAYSRUN - Ensure clock is always running - 0 - 0 - - - Automatic - Use automatic clock control - 0 - - - AlwaysRun - Ensure clock is always running - 1 - - - - - - - HFCLKAUDIOALWAYSRUN - Automatic or manual control of HFCLKAUDIO - 0x57C - read-write - - - ALWAYSRUN - Ensure clock is always running - 0 - 0 - - - Automatic - Use automatic clock control - 0 - - - AlwaysRun - Ensure clock is always running - 1 - - - - - - - HFCLK192MSRC - Clock source for HFCLK192M - 0x580 - read-write - 0x00000001 - - - SRC - Select which HFCLK192M source is started by the HFCLK192MSTART task - 0 - 0 - - - HFINT - HFCLK192MSTART task starts HFINT oscillator - 0 - - - HFXO - HFCLK192MSTART task starts HFXO oscillator - 1 - - - - - - - HFCLK192MALWAYSRUN - Automatic or manual control of HFCLK192M - 0x584 - read-write - - - ALWAYSRUN - Ensure clock is always running - 0 - 0 - - - Automatic - Use automatic clock control - 0 - - - AlwaysRun - Ensure clock is always running - 1 - - - - - - - HFCLK192MCTRL - HFCLK192M frequency configuration - 0x5B8 - read-write - 0x00000002 - - - HCLK192M - High frequency clock HCLK192M - 0 - 1 - - - Div1 - Divide HFCLK192M by 1 - 0 - - - Div2 - Divide HFCLK192M by 2 - 1 - - - Div4 - Divide HFCLK192M by 4 - 2 - - - - - - - - - POWER_NS - Power control 0 - 0x40005000 - CLOCK_NS - POWER - - - - 0 - 0x1000 - registers - - - CLOCK_POWER - 5 - - POWER - 0x20 - - - TASKS_CONSTLAT - Enable Constant Latency mode - 0x78 - write-only - - - TASKS_CONSTLAT - Enable Constant Latency mode - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_LOWPWR - Enable Low-Power mode (variable latency) - 0x7C - write-only - - - TASKS_LOWPWR - Enable Low-Power mode (variable latency) - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - SUBSCRIBE_CONSTLAT - Subscribe configuration for task CONSTLAT - 0xF8 - read-write - - - CHIDX - DPPI channel that task CONSTLAT will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_LOWPWR - Subscribe configuration for task LOWPWR - 0xFC - read-write - - - CHIDX - DPPI channel that task LOWPWR will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - EVENTS_POFWARN - Power failure warning - 0x108 - read-write - - - EVENTS_POFWARN - Power failure warning - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_SLEEPENTER - CPU entered WFI/WFE sleep - 0x114 - read-write - - - EVENTS_SLEEPENTER - CPU entered WFI/WFE sleep - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_SLEEPEXIT - CPU exited WFI/WFE sleep - 0x118 - read-write - - - EVENTS_SLEEPEXIT - CPU exited WFI/WFE sleep - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - PUBLISH_POFWARN - Publish configuration for event POFWARN - 0x188 - read-write - - - CHIDX - DPPI channel that event POFWARN will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_SLEEPENTER - Publish configuration for event SLEEPENTER - 0x194 - read-write - - - CHIDX - DPPI channel that event SLEEPENTER will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_SLEEPEXIT - Publish configuration for event SLEEPEXIT - 0x198 - read-write - - - CHIDX - DPPI channel that event SLEEPEXIT will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - - POFWARN - Enable or disable interrupt for event POFWARN - 2 - 2 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - SLEEPENTER - Enable or disable interrupt for event SLEEPENTER - 5 - 5 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - SLEEPEXIT - Enable or disable interrupt for event SLEEPEXIT - 6 - 6 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - POFWARN - Write '1' to enable interrupt for event POFWARN - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - SLEEPENTER - Write '1' to enable interrupt for event SLEEPENTER - 5 - 5 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - SLEEPEXIT - Write '1' to enable interrupt for event SLEEPEXIT - 6 - 6 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - POFWARN - Write '1' to disable interrupt for event POFWARN - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - SLEEPENTER - Write '1' to disable interrupt for event SLEEPENTER - 5 - 5 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - SLEEPEXIT - Write '1' to disable interrupt for event SLEEPEXIT - 6 - 6 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - 0x2 - 0x4 - GPREGRET[%s] - Description collection: General purpose retention register - 0x51C - read-write - - - GPREGRET - General purpose retention register - 0 - 7 - - - - - - - RESET_NS - Reset control 0 - 0x40005000 - CLOCK_NS - RESET - - - - 0 - 0x1000 - registers - - RESET - 0x20 - - - RESETREAS - Reset reason - 0x400 - read-write - - - RESETPIN - Reset from pin reset detected - 0 - 0 - - - NotDetected - Not detected - 0 - - - Detected - Detected - 1 - - - - - DOG0 - Reset from application watchdog timer 0 detected - 1 - 1 - - - NotDetected - Not detected - 0 - - - Detected - Detected - 1 - - - - - CTRLAP - Reset from application CTRL-AP detected - 2 - 2 - - - NotDetected - Not detected - 0 - - - Detected - Detected - 1 - - - - - SREQ - Reset from application soft reset detected - 3 - 3 - - - NotDetected - Not detected - 0 - - - Detected - Detected - 1 - - - - - LOCKUP - Reset from application CPU lockup detected - 4 - 4 - - - NotDetected - Not detected - 0 - - - Detected - Detected - 1 - - - - - OFF - Reset due to wakeup from System OFF mode when wakeup is triggered by DETECT signal from GPIO - 5 - 5 - - - NotDetected - Not detected - 0 - - - Detected - Detected - 1 - - - - - LPCOMP - Reset due to wakeup from System OFF mode when wakeup is triggered by ANADETECT signal from LPCOMP - 6 - 6 - - - NotDetected - Not detected - 0 - - - Detected - Detected - 1 - - - - - DIF - Reset due to wakeup from System OFF mode when wakeup is triggered by entering the Debug Interface mode - 7 - 7 - - - NotDetected - Not detected - 0 - - - Detected - Detected - 1 - - - - - NFC - Reset after wakeup from System OFF mode due to NFC field being detected - 24 - 24 - - - NotDetected - Not detected - 0 - - - Detected - Detected - 1 - - - - - DOG1 - Reset from application watchdog timer 1 detected - 25 - 25 - - - NotDetected - Not detected - 0 - - - Detected - Detected - 1 - - - - - VBUS - Reset after wakeup from System OFF mode due to VBUS rising into valid range - 26 - 26 - - - NotDetected - Not detected - 0 - - - Detected - Detected - 1 - - - - - - - NETWORK - ULP network core control - RESET_NETWORK - read-write - 0x610 - - FORCEOFF - Force network core off - 0x004 - read-write - 0x00000001 - - - FORCEOFF - Force network core off - 0 - 0 - - - Release - Release Force-OFF - 0 - - - Hold - Hold Force-OFF - 1 - - - - - - - - - - CLOCK_S - Clock management 1 - 0x50005000 - - - - CLOCK_POWER - 5 - - - - POWER_S - Power control 1 - 0x50005000 - CLOCK_S - - - - CLOCK_POWER - 5 - - - - RESET_S - Reset control 1 - 0x50005000 - CLOCK_S - - - - - CTRLAP_NS - Control access port 0 - 0x40006000 - CTRLAPPERI - - - - 0 - 0x1000 - registers - - CTRLAPPERI - 0x20 - - - MAILBOX - Unspecified - CTRLAPPERI_MAILBOX - read-write - 0x400 - - RXDATA - Data sent from the debugger to the CPU. - 0x000 - read-only - 0x00000000 - - - RXDATA - Data received from debugger - 0 - 31 - - - - - RXSTATUS - This register shows a status that indicates if data sent from the debugger to the CPU has been read. - 0x004 - read-only - 0x00000000 - - - RXSTATUS - Status of data in register RXDATA - 0 - 0 - - - NoDataPending - No data pending in register RXDATA - 0 - - - DataPending - Data pending in register RXDATA - 1 - - - - - - - TXDATA - Data sent from the CPU to the debugger. - 0x80 - read-write - 0x00000000 - - - TXDATA - Data sent to debugger - 0 - 31 - - - - - TXSTATUS - This register shows a status that indicates if the data sent from the CPU to the debugger has been read. - 0x84 - read-only - 0x00000000 - - - TXSTATUS - Status of data in register TXDATA - 0 - 0 - - - NoDataPending - No data pending in register TXDATA - 0 - - - DataPending - Data pending in register TXDATA - 1 - - - - - - - - ERASEPROTECT - Unspecified - CTRLAPPERI_ERASEPROTECT - read-write - 0x500 - - LOCK - This register locks the ERASEPROTECT.DISABLE register from being written until next reset. - 0x000 - read-writeOnce - 0x00000000 - - - LOCK - Lock ERASEPROTECT.DISABLE register from being written until next reset - 0 - 0 - - - Unlocked - Register ERASEPROTECT.DISABLE is writeable - 0 - - - Locked - Register ERASEPROTECT.DISABLE is read-only - 1 - - - - - - - DISABLE - This register disables the ERASEPROTECT register and performs an ERASEALL operation. - 0x004 - read-writeOnce - 0x00000000 - - - KEY - The ERASEALL sequence is initiated if the value of the KEY fields are non-zero and the KEY fields match on both the CPU and debugger sides. - 0 - 31 - - - - - - APPROTECT - Unspecified - CTRLAPPERI_APPROTECT - read-write - 0x540 - - LOCK - This register locks the APPROTECT.DISABLE register from being written to until next reset. - 0x000 - read-writeOnce - 0x00000000 - - - LOCK - Lock the APPROTECT.DISABLE register from being written to until next reset - 0 - 0 - - - Unlocked - Register APPROTECT.DISABLE is writeable - 0 - - - Locked - Register APPROTECT.DISABLE is read-only - 1 - - - - - - - DISABLE - This register disables the APPROTECT register and enables debug access to non-secure mode. - 0x004 - read-write - 0x00000000 - - - KEY - If the value of the KEY field is non-zero, and the KEY fields match on both the - CPU and debugger sides, disable APPROTECT and enable debug access to non-secure mode until - the next pin reset, brown-out reset, power-on reset, or watchog timer reset. After reset the debugger side register has a fixed KEY value. To enable debug access, both CTRL-AP and UICR.APPROTECT protection needs to be disabled. - 0 - 31 - - - - - - SECUREAPPROTECT - Unspecified - CTRLAPPERI_SECUREAPPROTECT - read-write - 0x548 - - LOCK - This register locks the SECUREAPPROTECT.DISABLE register from being written until next reset. - 0x000 - read-writeOnce - 0x00000000 - - - LOCK - Lock register SECUREAPPROTECT.DISABLE from being written until next reset - 0 - 0 - - - Unlocked - Register SECUREAPPROTECT.DISABLE is writeable - 0 - - - Locked - Register SECUREAPPROTECT.DISABLE is read-only - 1 - - - - - - - DISABLE - This register disables the SECUREAPPROTECT register and enables debug access to secure mode. - 0x004 - read-write - 0x00000000 - - - KEY - If the value of the KEY field is non-zero, and the KEY fields match on both the - CPU and debugger sides, disable SECUREAPPROTECT and enable debug access to secure mode until - the next pin reset, brown-out reset, power-on reset, or watchog timer reset. After reset the debugger side register has a fixed KEY value. To enable debug access, both CTRL-AP and UICR.SECUREAPPROTECT protection needs to be disabled. - 0 - 31 - - - - - - STATUS - Status bits for CTRL-AP peripheral. - 0x600 - read-only - 0x00000000 - - - UICRAPPROTECT - Status bit for UICR part of access port protection at last reset. - 0 - 0 - - - Enabled - APPROTECT was enabled in UICR - 0 - - - Disabled - APPROTECT wasdisabled in UICR - 1 - - - - - UICRSECUREAPPROTECT - Status bit for UICR part of secure access port protection at last reset. - 1 - 1 - - - Enabled - SECUREAPPROTECT was enabled in UICR - 0 - - - Disabled - SECUREAPPROTECT was disabled in UICR - 1 - - - - - DBGIFACEMODE - Status bit for device debug interface mode - 2 - 2 - - - Disabled - No debugger attached - 0 - - - Enabled - Debugger is attached and device is in debug interface mode - 1 - - - - - - - - - CTRLAP_S - Control access port 1 - 0x50006000 - - - - - SPIM0_NS - Serial Peripheral Interface Master with EasyDMA 0 - 0x40008000 - SPIM - - - - 0 - 0x1000 - registers - - - SERIAL0 - 8 - - SPIM - 0x20 - - - TASKS_START - Start SPI transaction - 0x010 - write-only - - - TASKS_START - Start SPI transaction - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STOP - Stop SPI transaction - 0x014 - write-only - - - TASKS_STOP - Stop SPI transaction - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_SUSPEND - Suspend SPI transaction - 0x01C - write-only - - - TASKS_SUSPEND - Suspend SPI transaction - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_RESUME - Resume SPI transaction - 0x020 - write-only - - - TASKS_RESUME - Resume SPI transaction - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - SUBSCRIBE_START - Subscribe configuration for task START - 0x090 - read-write - - - CHIDX - DPPI channel that task START will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_STOP - Subscribe configuration for task STOP - 0x094 - read-write - - - CHIDX - DPPI channel that task STOP will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_SUSPEND - Subscribe configuration for task SUSPEND - 0x09C - read-write - - - CHIDX - DPPI channel that task SUSPEND will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_RESUME - Subscribe configuration for task RESUME - 0x0A0 - read-write - - - CHIDX - DPPI channel that task RESUME will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - EVENTS_STOPPED - SPI transaction has stopped - 0x104 - read-write - - - EVENTS_STOPPED - SPI transaction has stopped - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_ENDRX - End of RXD buffer reached - 0x110 - read-write - - - EVENTS_ENDRX - End of RXD buffer reached - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_END - End of RXD buffer and TXD buffer reached - 0x118 - read-write - - - EVENTS_END - End of RXD buffer and TXD buffer reached - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_ENDTX - End of TXD buffer reached - 0x120 - read-write - - - EVENTS_ENDTX - End of TXD buffer reached - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_STARTED - Transaction started - 0x14C - read-write - - - EVENTS_STARTED - Transaction started - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - PUBLISH_STOPPED - Publish configuration for event STOPPED - 0x184 - read-write - - - CHIDX - DPPI channel that event STOPPED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_ENDRX - Publish configuration for event ENDRX - 0x190 - read-write - - - CHIDX - DPPI channel that event ENDRX will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_END - Publish configuration for event END - 0x198 - read-write - - - CHIDX - DPPI channel that event END will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_ENDTX - Publish configuration for event ENDTX - 0x1A0 - read-write - - - CHIDX - DPPI channel that event ENDTX will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_STARTED - Publish configuration for event STARTED - 0x1CC - read-write - - - CHIDX - DPPI channel that event STARTED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - SHORTS - Shortcuts between local events and tasks - 0x200 - read-write - - - END_START - Shortcut between event END and task START - 17 - 17 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - STOPPED - Write '1' to enable interrupt for event STOPPED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ENDRX - Write '1' to enable interrupt for event ENDRX - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - END - Write '1' to enable interrupt for event END - 6 - 6 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ENDTX - Write '1' to enable interrupt for event ENDTX - 8 - 8 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - STARTED - Write '1' to enable interrupt for event STARTED - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - STOPPED - Write '1' to disable interrupt for event STOPPED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ENDRX - Write '1' to disable interrupt for event ENDRX - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - END - Write '1' to disable interrupt for event END - 6 - 6 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ENDTX - Write '1' to disable interrupt for event ENDTX - 8 - 8 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - STARTED - Write '1' to disable interrupt for event STARTED - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - STALLSTAT - Stall status for EasyDMA RAM accesses. The fields in this register are set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU. - 0x400 - read-write - 0x00000000 - - - TX - Stall status for EasyDMA RAM reads - 0 - 0 - - - NOSTALL - No stall - 0 - - - STALL - A stall has occurred - 1 - - - - - RX - Stall status for EasyDMA RAM writes - 1 - 1 - - - NOSTALL - No stall - 0 - - - STALL - A stall has occurred - 1 - - - - - - - ENABLE - Enable SPIM - 0x500 - read-write - - - ENABLE - Enable or disable SPIM - 0 - 3 - - - Disabled - Disable SPIM - 0 - - - Enabled - Enable SPIM - 7 - - - - - - - PSEL - Unspecified - SPIM_PSEL - read-write - 0x508 - - SCK - Pin select for SCK - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - MOSI - Pin select for MOSI signal - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - MISO - Pin select for MISO signal - 0x008 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - CSN - Pin select for CSN - 0x00C - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - FREQUENCY - SPI frequency. Accuracy depends on the HFCLK source selected. - 0x524 - read-write - 0x04000000 - - - FREQUENCY - SPI master data rate - 0 - 31 - - - K125 - 125 kbps - 0x02000000 - - - K250 - 250 kbps - 0x04000000 - - - K500 - 500 kbps - 0x08000000 - - - M1 - 1 Mbps - 0x10000000 - - - M2 - 2 Mbps - 0x20000000 - - - M4 - 4 Mbps - 0x40000000 - - - M8 - 8 Mbps - 0x80000000 - - - M16 - 16 Mbps - 0x0A000000 - - - M32 - 32 Mbps - 0x14000000 - - - - - - - RXD - RXD EasyDMA channel - SPIM_RXD - read-write - 0x534 - - PTR - Data pointer - 0x000 - read-write - - - PTR - Data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in receive buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in receive buffer - 0 - 15 - - - - - AMOUNT - Number of bytes transferred in the last transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last transaction - 0 - 15 - - - - - LIST - EasyDMA list type - 0x00C - read-write - - - LIST - List type - 0 - 1 - - - Disabled - Disable EasyDMA list - 0 - - - ArrayList - Use array list - 1 - - - - - - - - TXD - TXD EasyDMA channel - SPIM_TXD - read-write - 0x544 - - PTR - Data pointer - 0x000 - read-write - - - PTR - Data pointer - 0 - 31 - - - - - MAXCNT - Number of bytes in transmit buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in transmit buffer - 0 - 15 - - - - - AMOUNT - Number of bytes transferred in the last transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last transaction - 0 - 15 - - - - - LIST - EasyDMA list type - 0x00C - read-write - - - LIST - List type - 0 - 1 - - - Disabled - Disable EasyDMA list - 0 - - - ArrayList - Use array list - 1 - - - - - - - - CONFIG - Configuration register - 0x554 - read-write - - - ORDER - Bit order - 0 - 0 - - - MsbFirst - Most significant bit shifted out first - 0 - - - LsbFirst - Least significant bit shifted out first - 1 - - - - - CPHA - Serial clock (SCK) phase - 1 - 1 - - - Leading - Sample on leading edge of clock, shift serial data on trailing edge - 0 - - - Trailing - Sample on trailing edge of clock, shift serial data on leading edge - 1 - - - - - CPOL - Serial clock (SCK) polarity - 2 - 2 - - - ActiveHigh - Active high - 0 - - - ActiveLow - Active low - 1 - - - - - - - IFTIMING - Unspecified - SPIM_IFTIMING - read-write - 0x560 - - RXDELAY - Sample delay for input serial data on MISO - 0x000 - read-write - 0x00000002 - - - RXDELAY - Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK. - 0 - 2 - - - - - CSNDUR - Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions - 0x004 - read-write - 0x00000002 - - - CSNDUR - Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns). - 0 - 7 - - - - - - CSNPOL - Polarity of CSN output - 0x568 - read-write - 0x00000000 - - - CSNPOL - Polarity of CSN output - 0 - 0 - - - LOW - Active low (idle state high) - 0 - - - HIGH - Active high (idle state low) - 1 - - - - - - - PSELDCX - Pin select for DCX signal - 0x56C - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - DCXCNT - DCX configuration - 0x570 - read-write - - - DCXCNT - This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates that all bytes are command bytes. - 0 - 3 - - - - - ORC - Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT - 0x5C0 - read-write - - - ORC - Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT. - 0 - 7 - - - - - - - SPIS0_NS - SPI Slave 0 - 0x40008000 - SPIM0_NS - SPIS - - - - 0 - 0x1000 - registers - - - SERIAL0 - 8 - - SPIS - 0x20 - - - TASKS_ACQUIRE - Acquire SPI semaphore - 0x024 - write-only - - - TASKS_ACQUIRE - Acquire SPI semaphore - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_RELEASE - Release SPI semaphore, enabling the SPI slave to acquire it - 0x028 - write-only - - - TASKS_RELEASE - Release SPI semaphore, enabling the SPI slave to acquire it - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - SUBSCRIBE_ACQUIRE - Subscribe configuration for task ACQUIRE - 0x0A4 - read-write - - - CHIDX - DPPI channel that task ACQUIRE will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_RELEASE - Subscribe configuration for task RELEASE - 0x0A8 - read-write - - - CHIDX - DPPI channel that task RELEASE will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - EVENTS_END - Granted transaction completed - 0x104 - read-write - - - EVENTS_END - Granted transaction completed - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_ENDRX - End of RXD buffer reached - 0x110 - read-write - - - EVENTS_ENDRX - End of RXD buffer reached - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_ACQUIRED - Semaphore acquired - 0x128 - read-write - - - EVENTS_ACQUIRED - Semaphore acquired - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - PUBLISH_END - Publish configuration for event END - 0x184 - read-write - - - CHIDX - DPPI channel that event END will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_ENDRX - Publish configuration for event ENDRX - 0x190 - read-write - - - CHIDX - DPPI channel that event ENDRX will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_ACQUIRED - Publish configuration for event ACQUIRED - 0x1A8 - read-write - - - CHIDX - DPPI channel that event ACQUIRED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - SHORTS - Shortcuts between local events and tasks - 0x200 - read-write - - - END_ACQUIRE - Shortcut between event END and task ACQUIRE - 2 - 2 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - END - Write '1' to enable interrupt for event END - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ENDRX - Write '1' to enable interrupt for event ENDRX - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ACQUIRED - Write '1' to enable interrupt for event ACQUIRED - 10 - 10 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - END - Write '1' to disable interrupt for event END - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ENDRX - Write '1' to disable interrupt for event ENDRX - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ACQUIRED - Write '1' to disable interrupt for event ACQUIRED - 10 - 10 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - SEMSTAT - Semaphore status register - 0x400 - read-only - 0x00000001 - - - SEMSTAT - Semaphore status - 0 - 1 - - - Free - Semaphore is free - 0 - - - CPU - Semaphore is assigned to CPU - 1 - - - SPIS - Semaphore is assigned to SPI slave - 2 - - - CPUPending - Semaphore is assigned to SPI but a handover to the CPU is pending - 3 - - - - - - - STATUS - Status from last transaction - 0x440 - read-write - - - OVERREAD - TX buffer over-read detected, and prevented - 0 - 0 - - read - - NotPresent - Read: error not present - 0 - - - Present - Read: error present - 1 - - - - write - - Clear - Write: clear error on writing '1' - 1 - - - - - OVERFLOW - RX buffer overflow detected, and prevented - 1 - 1 - - read - - NotPresent - Read: error not present - 0 - - - Present - Read: error present - 1 - - - - write - - Clear - Write: clear error on writing '1' - 1 - - - - - - - ENABLE - Enable SPI slave - 0x500 - read-write - - - ENABLE - Enable or disable SPI slave - 0 - 3 - - - Disabled - Disable SPI slave - 0 - - - Enabled - Enable SPI slave - 2 - - - - - - - PSEL - Unspecified - SPIS_PSEL - read-write - 0x508 - - SCK - Pin select for SCK - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - MISO - Pin select for MISO signal - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - MOSI - Pin select for MOSI signal - 0x008 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - CSN - Pin select for CSN signal - 0x00C - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - RXD - Unspecified - SPIS_RXD - read-write - 0x534 - - PTR - RXD data pointer - 0x000 - read-write - - - PTR - RXD data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in receive buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in receive buffer - 0 - 15 - - - - - AMOUNT - Number of bytes received in last granted transaction - 0x008 - read-only - - - AMOUNT - Number of bytes received in the last granted transaction - 0 - 15 - - - - - LIST - EasyDMA list type - 0x00C - read-write - - - LIST - List type - 0 - 1 - - - Disabled - Disable EasyDMA list - 0 - - - ArrayList - Use array list - 1 - - - - - - - - TXD - Unspecified - SPIS_TXD - read-write - 0x544 - - PTR - TXD data pointer - 0x000 - read-write - - - PTR - TXD data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in transmit buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in transmit buffer - 0 - 15 - - - - - AMOUNT - Number of bytes transmitted in last granted transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transmitted in last granted transaction - 0 - 15 - - - - - LIST - EasyDMA list type - 0x00C - read-write - - - LIST - List type - 0 - 1 - - - Disabled - Disable EasyDMA list - 0 - - - ArrayList - Use array list - 1 - - - - - - - - CONFIG - Configuration register - 0x554 - read-write - - - ORDER - Bit order - 0 - 0 - - - MsbFirst - Most significant bit shifted out first - 0 - - - LsbFirst - Least significant bit shifted out first - 1 - - - - - CPHA - Serial clock (SCK) phase - 1 - 1 - - - Leading - Sample on leading edge of clock, shift serial data on trailing edge - 0 - - - Trailing - Sample on trailing edge of clock, shift serial data on leading edge - 1 - - - - - CPOL - Serial clock (SCK) polarity - 2 - 2 - - - ActiveHigh - Active high - 0 - - - ActiveLow - Active low - 1 - - - - - - - DEF - Default character. Character clocked out in case of an ignored transaction. - 0x55C - read-write - - - DEF - Default character. Character clocked out in case of an ignored transaction. - 0 - 7 - - - - - ORC - Over-read character - 0x5C0 - read-write - - - ORC - Over-read character. Character clocked out after an over-read of the transmit buffer. - 0 - 7 - - - - - - - TWIM0_NS - I2C compatible Two-Wire Master Interface with EasyDMA 0 - 0x40008000 - SPIM0_NS - TWIM - - - - 0 - 0x1000 - registers - - - SERIAL0 - 8 - - TWIM - 0x20 - - - TASKS_STARTRX - Start TWI receive sequence - 0x000 - write-only - - - TASKS_STARTRX - Start TWI receive sequence - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STARTTX - Start TWI transmit sequence - 0x008 - write-only - - - TASKS_STARTTX - Start TWI transmit sequence - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STOP - Stop TWI transaction. Must be issued while the TWI master is not suspended. - 0x014 - write-only - - - TASKS_STOP - Stop TWI transaction. Must be issued while the TWI master is not suspended. - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_SUSPEND - Suspend TWI transaction - 0x01C - write-only - - - TASKS_SUSPEND - Suspend TWI transaction - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_RESUME - Resume TWI transaction - 0x020 - write-only - - - TASKS_RESUME - Resume TWI transaction - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - SUBSCRIBE_STARTRX - Subscribe configuration for task STARTRX - 0x080 - read-write - - - CHIDX - DPPI channel that task STARTRX will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_STARTTX - Subscribe configuration for task STARTTX - 0x088 - read-write - - - CHIDX - DPPI channel that task STARTTX will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_STOP - Subscribe configuration for task STOP - 0x094 - read-write - - - CHIDX - DPPI channel that task STOP will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_SUSPEND - Subscribe configuration for task SUSPEND - 0x09C - read-write - - - CHIDX - DPPI channel that task SUSPEND will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_RESUME - Subscribe configuration for task RESUME - 0x0A0 - read-write - - - CHIDX - DPPI channel that task RESUME will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - EVENTS_STOPPED - TWI stopped - 0x104 - read-write - - - EVENTS_STOPPED - TWI stopped - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_ERROR - TWI error - 0x124 - read-write - - - EVENTS_ERROR - TWI error - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_SUSPENDED - SUSPEND task has been issued, TWI traffic is now suspended. - 0x148 - read-write - - - EVENTS_SUSPENDED - SUSPEND task has been issued, TWI traffic is now suspended. - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_RXSTARTED - Receive sequence started - 0x14C - read-write - - - EVENTS_RXSTARTED - Receive sequence started - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_TXSTARTED - Transmit sequence started - 0x150 - read-write - - - EVENTS_TXSTARTED - Transmit sequence started - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_LASTRX - Byte boundary, starting to receive the last byte - 0x15C - read-write - - - EVENTS_LASTRX - Byte boundary, starting to receive the last byte - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_LASTTX - Byte boundary, starting to transmit the last byte - 0x160 - read-write - - - EVENTS_LASTTX - Byte boundary, starting to transmit the last byte - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - PUBLISH_STOPPED - Publish configuration for event STOPPED - 0x184 - read-write - - - CHIDX - DPPI channel that event STOPPED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_ERROR - Publish configuration for event ERROR - 0x1A4 - read-write - - - CHIDX - DPPI channel that event ERROR will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_SUSPENDED - Publish configuration for event SUSPENDED - 0x1C8 - read-write - - - CHIDX - DPPI channel that event SUSPENDED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_RXSTARTED - Publish configuration for event RXSTARTED - 0x1CC - read-write - - - CHIDX - DPPI channel that event RXSTARTED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_TXSTARTED - Publish configuration for event TXSTARTED - 0x1D0 - read-write - - - CHIDX - DPPI channel that event TXSTARTED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_LASTRX - Publish configuration for event LASTRX - 0x1DC - read-write - - - CHIDX - DPPI channel that event LASTRX will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_LASTTX - Publish configuration for event LASTTX - 0x1E0 - read-write - - - CHIDX - DPPI channel that event LASTTX will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - SHORTS - Shortcuts between local events and tasks - 0x200 - read-write - - - LASTTX_STARTRX - Shortcut between event LASTTX and task STARTRX - 7 - 7 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - LASTTX_SUSPEND - Shortcut between event LASTTX and task SUSPEND - 8 - 8 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - LASTTX_STOP - Shortcut between event LASTTX and task STOP - 9 - 9 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - LASTRX_STARTTX - Shortcut between event LASTRX and task STARTTX - 10 - 10 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - LASTRX_STOP - Shortcut between event LASTRX and task STOP - 12 - 12 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - - STOPPED - Enable or disable interrupt for event STOPPED - 1 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ERROR - Enable or disable interrupt for event ERROR - 9 - 9 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - SUSPENDED - Enable or disable interrupt for event SUSPENDED - 18 - 18 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RXSTARTED - Enable or disable interrupt for event RXSTARTED - 19 - 19 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TXSTARTED - Enable or disable interrupt for event TXSTARTED - 20 - 20 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - LASTRX - Enable or disable interrupt for event LASTRX - 23 - 23 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - LASTTX - Enable or disable interrupt for event LASTTX - 24 - 24 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - STOPPED - Write '1' to enable interrupt for event STOPPED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ERROR - Write '1' to enable interrupt for event ERROR - 9 - 9 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - SUSPENDED - Write '1' to enable interrupt for event SUSPENDED - 18 - 18 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RXSTARTED - Write '1' to enable interrupt for event RXSTARTED - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TXSTARTED - Write '1' to enable interrupt for event TXSTARTED - 20 - 20 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - LASTRX - Write '1' to enable interrupt for event LASTRX - 23 - 23 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - LASTTX - Write '1' to enable interrupt for event LASTTX - 24 - 24 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - STOPPED - Write '1' to disable interrupt for event STOPPED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ERROR - Write '1' to disable interrupt for event ERROR - 9 - 9 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - SUSPENDED - Write '1' to disable interrupt for event SUSPENDED - 18 - 18 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RXSTARTED - Write '1' to disable interrupt for event RXSTARTED - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TXSTARTED - Write '1' to disable interrupt for event TXSTARTED - 20 - 20 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - LASTRX - Write '1' to disable interrupt for event LASTRX - 23 - 23 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - LASTTX - Write '1' to disable interrupt for event LASTTX - 24 - 24 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - ERRORSRC - Error source - 0x4C4 - read-write - oneToClear - - - OVERRUN - Overrun error - 0 - 0 - - - NotReceived - Error did not occur - 0 - - - Received - Error occurred - 1 - - - - - ANACK - NACK received after sending the address (write '1' to clear) - 1 - 1 - - - NotReceived - Error did not occur - 0 - - - Received - Error occurred - 1 - - - - - DNACK - NACK received after sending a data byte (write '1' to clear) - 2 - 2 - - - NotReceived - Error did not occur - 0 - - - Received - Error occurred - 1 - - - - - - - ENABLE - Enable TWIM - 0x500 - read-write - - - ENABLE - Enable or disable TWIM - 0 - 3 - - - Disabled - Disable TWIM - 0 - - - Enabled - Enable TWIM - 6 - - - - - - - PSEL - Unspecified - TWIM_PSEL - read-write - 0x508 - - SCL - Pin select for SCL signal - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - SDA - Pin select for SDA signal - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - FREQUENCY - TWI frequency. Accuracy depends on the HFCLK source selected. - 0x524 - read-write - 0x04000000 - - - FREQUENCY - TWI master clock frequency - 0 - 31 - - - K100 - 100 kbps - 0x01980000 - - - K250 - 250 kbps - 0x04000000 - - - K400 - 400 kbps - 0x06400000 - - - K1000 - 1000 kbps - 0x0FF00000 - - - - - - - RXD - RXD EasyDMA channel - TWIM_RXD - read-write - 0x534 - - PTR - Data pointer - 0x000 - read-write - - - PTR - Data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in receive buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in receive buffer - 0 - 15 - - - - - AMOUNT - Number of bytes transferred in the last transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. - 0 - 15 - - - - - LIST - EasyDMA list type - 0x00C - read-write - - - LIST - List type - 0 - 2 - - - Disabled - Disable EasyDMA list - 0 - - - ArrayList - Use array list - 1 - - - - - - - - TXD - TXD EasyDMA channel - TWIM_TXD - read-write - 0x544 - - PTR - Data pointer - 0x000 - read-write - - - PTR - Data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in transmit buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in transmit buffer - 0 - 15 - - - - - AMOUNT - Number of bytes transferred in the last transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. - 0 - 15 - - - - - LIST - EasyDMA list type - 0x00C - read-write - - - LIST - List type - 0 - 2 - - - Disabled - Disable EasyDMA list - 0 - - - ArrayList - Use array list - 1 - - - - - - - - ADDRESS - Address used in the TWI transfer - 0x588 - read-write - - - ADDRESS - Address used in the TWI transfer - 0 - 6 - - - - - - - TWIS0_NS - I2C compatible Two-Wire Slave Interface with EasyDMA 0 - 0x40008000 - SPIM0_NS - TWIS - - - - 0 - 0x1000 - registers - - - SERIAL0 - 8 - - TWIS - 0x20 - - - TASKS_STOP - Stop TWI transaction - 0x014 - write-only - - - TASKS_STOP - Stop TWI transaction - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_SUSPEND - Suspend TWI transaction - 0x01C - write-only - - - TASKS_SUSPEND - Suspend TWI transaction - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_RESUME - Resume TWI transaction - 0x020 - write-only - - - TASKS_RESUME - Resume TWI transaction - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_PREPARERX - Prepare the TWI slave to respond to a write command - 0x030 - write-only - - - TASKS_PREPARERX - Prepare the TWI slave to respond to a write command - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_PREPARETX - Prepare the TWI slave to respond to a read command - 0x034 - write-only - - - TASKS_PREPARETX - Prepare the TWI slave to respond to a read command - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - SUBSCRIBE_STOP - Subscribe configuration for task STOP - 0x094 - read-write - - - CHIDX - DPPI channel that task STOP will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_SUSPEND - Subscribe configuration for task SUSPEND - 0x09C - read-write - - - CHIDX - DPPI channel that task SUSPEND will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_RESUME - Subscribe configuration for task RESUME - 0x0A0 - read-write - - - CHIDX - DPPI channel that task RESUME will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_PREPARERX - Subscribe configuration for task PREPARERX - 0x0B0 - read-write - - - CHIDX - DPPI channel that task PREPARERX will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_PREPARETX - Subscribe configuration for task PREPARETX - 0x0B4 - read-write - - - CHIDX - DPPI channel that task PREPARETX will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - EVENTS_STOPPED - TWI stopped - 0x104 - read-write - - - EVENTS_STOPPED - TWI stopped - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_ERROR - TWI error - 0x124 - read-write - - - EVENTS_ERROR - TWI error - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_RXSTARTED - Receive sequence started - 0x14C - read-write - - - EVENTS_RXSTARTED - Receive sequence started - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_TXSTARTED - Transmit sequence started - 0x150 - read-write - - - EVENTS_TXSTARTED - Transmit sequence started - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_WRITE - Write command received - 0x164 - read-write - - - EVENTS_WRITE - Write command received - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_READ - Read command received - 0x168 - read-write - - - EVENTS_READ - Read command received - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - PUBLISH_STOPPED - Publish configuration for event STOPPED - 0x184 - read-write - - - CHIDX - DPPI channel that event STOPPED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_ERROR - Publish configuration for event ERROR - 0x1A4 - read-write - - - CHIDX - DPPI channel that event ERROR will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_RXSTARTED - Publish configuration for event RXSTARTED - 0x1CC - read-write - - - CHIDX - DPPI channel that event RXSTARTED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_TXSTARTED - Publish configuration for event TXSTARTED - 0x1D0 - read-write - - - CHIDX - DPPI channel that event TXSTARTED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_WRITE - Publish configuration for event WRITE - 0x1E4 - read-write - - - CHIDX - DPPI channel that event WRITE will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_READ - Publish configuration for event READ - 0x1E8 - read-write - - - CHIDX - DPPI channel that event READ will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - SHORTS - Shortcuts between local events and tasks - 0x200 - read-write - - - WRITE_SUSPEND - Shortcut between event WRITE and task SUSPEND - 13 - 13 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - READ_SUSPEND - Shortcut between event READ and task SUSPEND - 14 - 14 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - - STOPPED - Enable or disable interrupt for event STOPPED - 1 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ERROR - Enable or disable interrupt for event ERROR - 9 - 9 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RXSTARTED - Enable or disable interrupt for event RXSTARTED - 19 - 19 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TXSTARTED - Enable or disable interrupt for event TXSTARTED - 20 - 20 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - WRITE - Enable or disable interrupt for event WRITE - 25 - 25 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - READ - Enable or disable interrupt for event READ - 26 - 26 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - STOPPED - Write '1' to enable interrupt for event STOPPED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ERROR - Write '1' to enable interrupt for event ERROR - 9 - 9 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RXSTARTED - Write '1' to enable interrupt for event RXSTARTED - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TXSTARTED - Write '1' to enable interrupt for event TXSTARTED - 20 - 20 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - WRITE - Write '1' to enable interrupt for event WRITE - 25 - 25 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - READ - Write '1' to enable interrupt for event READ - 26 - 26 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - STOPPED - Write '1' to disable interrupt for event STOPPED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ERROR - Write '1' to disable interrupt for event ERROR - 9 - 9 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RXSTARTED - Write '1' to disable interrupt for event RXSTARTED - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TXSTARTED - Write '1' to disable interrupt for event TXSTARTED - 20 - 20 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - WRITE - Write '1' to disable interrupt for event WRITE - 25 - 25 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - READ - Write '1' to disable interrupt for event READ - 26 - 26 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - ERRORSRC - Error source - 0x4D0 - read-write - oneToClear - - - OVERFLOW - RX buffer overflow detected, and prevented - 0 - 0 - - - NotDetected - Error did not occur - 0 - - - Detected - Error occurred - 1 - - - - - DNACK - NACK sent after receiving a data byte - 2 - 2 - - - NotReceived - Error did not occur - 0 - - - Received - Error occurred - 1 - - - - - OVERREAD - TX buffer over-read detected, and prevented - 3 - 3 - - - NotDetected - Error did not occur - 0 - - - Detected - Error occurred - 1 - - - - - - - MATCH - Status register indicating which address had a match - 0x4D4 - read-only - - - MATCH - Indication of which address in {ADDRESS} that matched the incoming address - 0 - 0 - - - - - ENABLE - Enable TWIS - 0x500 - read-write - - - ENABLE - Enable or disable TWIS - 0 - 3 - - - Disabled - Disable TWIS - 0 - - - Enabled - Enable TWIS - 9 - - - - - - - PSEL - Unspecified - TWIS_PSEL - read-write - 0x508 - - SCL - Pin select for SCL signal - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - SDA - Pin select for SDA signal - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - RXD - RXD EasyDMA channel - TWIS_RXD - read-write - 0x534 - - PTR - RXD Data pointer - 0x000 - read-write - - - PTR - RXD Data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in RXD buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in RXD buffer - 0 - 15 - - - - - AMOUNT - Number of bytes transferred in the last RXD transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last RXD transaction - 0 - 15 - - - - - LIST - EasyDMA list type - 0x00C - read-write - - - LIST - List type - 0 - 1 - - - Disabled - Disable EasyDMA list - 0 - - - ArrayList - Use array list - 1 - - - - - - - - TXD - TXD EasyDMA channel - TWIS_TXD - read-write - 0x544 - - PTR - TXD Data pointer - 0x000 - read-write - - - PTR - TXD Data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in TXD buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in TXD buffer - 0 - 15 - - - - - AMOUNT - Number of bytes transferred in the last TXD transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last TXD transaction - 0 - 15 - - - - - LIST - EasyDMA list type - 0x00C - read-write - - - LIST - List type - 0 - 1 - - - Disabled - Disable EasyDMA list - 0 - - - ArrayList - Use array list - 1 - - - - - - - - 0x2 - 0x4 - ADDRESS[%s] - Description collection: TWI slave address n - 0x588 - read-write - - - ADDRESS - TWI slave address - 0 - 6 - - - - - CONFIG - Configuration register for the address match mechanism - 0x594 - read-write - 0x00000001 - - - ADDRESS0 - Enable or disable address matching on ADDRESS[0] - 0 - 0 - - - Disabled - Disabled - 0 - - - Enabled - Enabled - 1 - - - - - ADDRESS1 - Enable or disable address matching on ADDRESS[1] - 1 - 1 - - - Disabled - Disabled - 0 - - - Enabled - Enabled - 1 - - - - - - - ORC - Over-read character. Character sent out in case of an over-read of the transmit buffer. - 0x5C0 - read-write - - - ORC - Over-read character. Character sent out in case of an over-read of the transmit buffer. - 0 - 7 - - - - - - - UARTE0_NS - UART with EasyDMA 0 - 0x40008000 - SPIM0_NS - UARTE - - - - 0 - 0x1000 - registers - - - SERIAL0 - 8 - - UARTE - 0x20 - - - TASKS_STARTRX - Start UART receiver - 0x000 - write-only - - - TASKS_STARTRX - Start UART receiver - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STOPRX - Stop UART receiver - 0x004 - write-only - - - TASKS_STOPRX - Stop UART receiver - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STARTTX - Start UART transmitter - 0x008 - write-only - - - TASKS_STARTTX - Start UART transmitter - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STOPTX - Stop UART transmitter - 0x00C - write-only - - - TASKS_STOPTX - Stop UART transmitter - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_FLUSHRX - Flush RX FIFO into RX buffer - 0x02C - write-only - - - TASKS_FLUSHRX - Flush RX FIFO into RX buffer - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - SUBSCRIBE_STARTRX - Subscribe configuration for task STARTRX - 0x080 - read-write - - - CHIDX - DPPI channel that task STARTRX will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_STOPRX - Subscribe configuration for task STOPRX - 0x084 - read-write - - - CHIDX - DPPI channel that task STOPRX will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_STARTTX - Subscribe configuration for task STARTTX - 0x088 - read-write - - - CHIDX - DPPI channel that task STARTTX will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_STOPTX - Subscribe configuration for task STOPTX - 0x08C - read-write - - - CHIDX - DPPI channel that task STOPTX will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_FLUSHRX - Subscribe configuration for task FLUSHRX - 0x0AC - read-write - - - CHIDX - DPPI channel that task FLUSHRX will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - EVENTS_CTS - CTS is activated (set low). Clear To Send. - 0x100 - read-write - - - EVENTS_CTS - CTS is activated (set low). Clear To Send. - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_NCTS - CTS is deactivated (set high). Not Clear To Send. - 0x104 - read-write - - - EVENTS_NCTS - CTS is deactivated (set high). Not Clear To Send. - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_RXDRDY - Data received in RXD (but potentially not yet transferred to Data RAM) - 0x108 - read-write - - - EVENTS_RXDRDY - Data received in RXD (but potentially not yet transferred to Data RAM) - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_ENDRX - Receive buffer is filled up - 0x110 - read-write - - - EVENTS_ENDRX - Receive buffer is filled up - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_TXDRDY - Data sent from TXD - 0x11C - read-write - - - EVENTS_TXDRDY - Data sent from TXD - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_ENDTX - Last TX byte transmitted - 0x120 - read-write - - - EVENTS_ENDTX - Last TX byte transmitted - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_ERROR - Error detected - 0x124 - read-write - - - EVENTS_ERROR - Error detected - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_RXTO - Receiver timeout - 0x144 - read-write - - - EVENTS_RXTO - Receiver timeout - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_RXSTARTED - UART receiver has started - 0x14C - read-write - - - EVENTS_RXSTARTED - UART receiver has started - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_TXSTARTED - UART transmitter has started - 0x150 - read-write - - - EVENTS_TXSTARTED - UART transmitter has started - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_TXSTOPPED - Transmitter stopped - 0x158 - read-write - - - EVENTS_TXSTOPPED - Transmitter stopped - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - PUBLISH_CTS - Publish configuration for event CTS - 0x180 - read-write - - - CHIDX - DPPI channel that event CTS will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_NCTS - Publish configuration for event NCTS - 0x184 - read-write - - - CHIDX - DPPI channel that event NCTS will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_RXDRDY - Publish configuration for event RXDRDY - 0x188 - read-write - - - CHIDX - DPPI channel that event RXDRDY will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_ENDRX - Publish configuration for event ENDRX - 0x190 - read-write - - - CHIDX - DPPI channel that event ENDRX will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_TXDRDY - Publish configuration for event TXDRDY - 0x19C - read-write - - - CHIDX - DPPI channel that event TXDRDY will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_ENDTX - Publish configuration for event ENDTX - 0x1A0 - read-write - - - CHIDX - DPPI channel that event ENDTX will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_ERROR - Publish configuration for event ERROR - 0x1A4 - read-write - - - CHIDX - DPPI channel that event ERROR will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_RXTO - Publish configuration for event RXTO - 0x1C4 - read-write - - - CHIDX - DPPI channel that event RXTO will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_RXSTARTED - Publish configuration for event RXSTARTED - 0x1CC - read-write - - - CHIDX - DPPI channel that event RXSTARTED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_TXSTARTED - Publish configuration for event TXSTARTED - 0x1D0 - read-write - - - CHIDX - DPPI channel that event TXSTARTED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_TXSTOPPED - Publish configuration for event TXSTOPPED - 0x1D8 - read-write - - - CHIDX - DPPI channel that event TXSTOPPED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - SHORTS - Shortcuts between local events and tasks - 0x200 - read-write - - - ENDRX_STARTRX - Shortcut between event ENDRX and task STARTRX - 5 - 5 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - ENDRX_STOPRX - Shortcut between event ENDRX and task STOPRX - 6 - 6 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - - CTS - Enable or disable interrupt for event CTS - 0 - 0 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - NCTS - Enable or disable interrupt for event NCTS - 1 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RXDRDY - Enable or disable interrupt for event RXDRDY - 2 - 2 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ENDRX - Enable or disable interrupt for event ENDRX - 4 - 4 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TXDRDY - Enable or disable interrupt for event TXDRDY - 7 - 7 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ENDTX - Enable or disable interrupt for event ENDTX - 8 - 8 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ERROR - Enable or disable interrupt for event ERROR - 9 - 9 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RXTO - Enable or disable interrupt for event RXTO - 17 - 17 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RXSTARTED - Enable or disable interrupt for event RXSTARTED - 19 - 19 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TXSTARTED - Enable or disable interrupt for event TXSTARTED - 20 - 20 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TXSTOPPED - Enable or disable interrupt for event TXSTOPPED - 22 - 22 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - CTS - Write '1' to enable interrupt for event CTS - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - NCTS - Write '1' to enable interrupt for event NCTS - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RXDRDY - Write '1' to enable interrupt for event RXDRDY - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ENDRX - Write '1' to enable interrupt for event ENDRX - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TXDRDY - Write '1' to enable interrupt for event TXDRDY - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ENDTX - Write '1' to enable interrupt for event ENDTX - 8 - 8 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ERROR - Write '1' to enable interrupt for event ERROR - 9 - 9 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RXTO - Write '1' to enable interrupt for event RXTO - 17 - 17 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RXSTARTED - Write '1' to enable interrupt for event RXSTARTED - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TXSTARTED - Write '1' to enable interrupt for event TXSTARTED - 20 - 20 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TXSTOPPED - Write '1' to enable interrupt for event TXSTOPPED - 22 - 22 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - CTS - Write '1' to disable interrupt for event CTS - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - NCTS - Write '1' to disable interrupt for event NCTS - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RXDRDY - Write '1' to disable interrupt for event RXDRDY - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ENDRX - Write '1' to disable interrupt for event ENDRX - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TXDRDY - Write '1' to disable interrupt for event TXDRDY - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ENDTX - Write '1' to disable interrupt for event ENDTX - 8 - 8 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ERROR - Write '1' to disable interrupt for event ERROR - 9 - 9 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RXTO - Write '1' to disable interrupt for event RXTO - 17 - 17 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RXSTARTED - Write '1' to disable interrupt for event RXSTARTED - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TXSTARTED - Write '1' to disable interrupt for event TXSTARTED - 20 - 20 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TXSTOPPED - Write '1' to disable interrupt for event TXSTOPPED - 22 - 22 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - ERRORSRC - Error source - 0x480 - read-write - oneToClear - - - OVERRUN - Overrun error - 0 - 0 - - read - - NotPresent - Read: error not present - 0 - - - Present - Read: error present - 1 - - - - - PARITY - Parity error - 1 - 1 - - read - - NotPresent - Read: error not present - 0 - - - Present - Read: error present - 1 - - - - - FRAMING - Framing error occurred - 2 - 2 - - read - - NotPresent - Read: error not present - 0 - - - Present - Read: error present - 1 - - - - - BREAK - Break condition - 3 - 3 - - read - - NotPresent - Read: error not present - 0 - - - Present - Read: error present - 1 - - - - - - - ENABLE - Enable UART - 0x500 - read-write - - - ENABLE - Enable or disable UARTE - 0 - 3 - - - Disabled - Disable UARTE - 0 - - - Enabled - Enable UARTE - 8 - - - - - - - PSEL - Unspecified - UARTE_PSEL - read-write - 0x508 - - RTS - Pin select for RTS signal - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - TXD - Pin select for TXD signal - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - CTS - Pin select for CTS signal - 0x008 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - RXD - Pin select for RXD signal - 0x00C - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - BAUDRATE - Baud rate. Accuracy depends on the HFCLK source selected. - 0x524 - read-write - 0x04000000 - - - BAUDRATE - Baud rate - 0 - 31 - - - Baud1200 - 1200 baud (actual rate: 1205) - 0x0004F000 - - - Baud2400 - 2400 baud (actual rate: 2396) - 0x0009D000 - - - Baud4800 - 4800 baud (actual rate: 4808) - 0x0013B000 - - - Baud9600 - 9600 baud (actual rate: 9598) - 0x00275000 - - - Baud14400 - 14400 baud (actual rate: 14401) - 0x003AF000 - - - Baud19200 - 19200 baud (actual rate: 19208) - 0x004EA000 - - - Baud28800 - 28800 baud (actual rate: 28777) - 0x0075C000 - - - Baud31250 - 31250 baud - 0x00800000 - - - Baud38400 - 38400 baud (actual rate: 38369) - 0x009D0000 - - - Baud56000 - 56000 baud (actual rate: 55944) - 0x00E50000 - - - Baud57600 - 57600 baud (actual rate: 57554) - 0x00EB0000 - - - Baud76800 - 76800 baud (actual rate: 76923) - 0x013A9000 - - - Baud115200 - 115200 baud (actual rate: 115108) - 0x01D60000 - - - Baud230400 - 230400 baud (actual rate: 231884) - 0x03B00000 - - - Baud250000 - 250000 baud - 0x04000000 - - - Baud460800 - 460800 baud (actual rate: 457143) - 0x07400000 - - - Baud921600 - 921600 baud (actual rate: 941176) - 0x0F000000 - - - Baud1M - 1 megabaud - 0x10000000 - - - - - - - RXD - RXD EasyDMA channel - UARTE_RXD - read-write - 0x534 - - PTR - Data pointer - 0x000 - read-write - - - PTR - Data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in receive buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in receive buffer - 0 - 15 - - - - - AMOUNT - Number of bytes transferred in the last transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last transaction - 0 - 15 - - - - - - TXD - TXD EasyDMA channel - UARTE_TXD - read-write - 0x544 - - PTR - Data pointer - 0x000 - read-write - - - PTR - Data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in transmit buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in transmit buffer - 0 - 15 - - - - - AMOUNT - Number of bytes transferred in the last transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last transaction - 0 - 15 - - - - - - CONFIG - Configuration of parity and hardware flow control - 0x56C - read-write - - - HWFC - Hardware flow control - 0 - 0 - - - Disabled - Disabled - 0 - - - Enabled - Enabled - 1 - - - - - PARITY - Parity - 1 - 3 - - - Excluded - Exclude parity bit - 0x0 - - - Included - Include even parity bit - 0x7 - - - - - STOP - Stop bits - 4 - 4 - - - One - One stop bit - 0 - - - Two - Two stop bits - 1 - - - - - PARITYTYPE - Even or odd parity type - 8 - 8 - - - Even - Even parity - 0 - - - Odd - Odd parity - 1 - - - - - - - - - SPIM0_S - Serial Peripheral Interface Master with EasyDMA 1 - 0x50008000 - - - - SERIAL0 - 8 - - - - SPIS0_S - SPI Slave 1 - 0x50008000 - SPIM0_S - - - - SERIAL0 - 8 - - - - TWIM0_S - I2C compatible Two-Wire Master Interface with EasyDMA 1 - 0x50008000 - SPIM0_S - - - - SERIAL0 - 8 - - - - TWIS0_S - I2C compatible Two-Wire Slave Interface with EasyDMA 1 - 0x50008000 - SPIM0_S - - - - SERIAL0 - 8 - - - - UARTE0_S - UART with EasyDMA 1 - 0x50008000 - SPIM0_S - - - - SERIAL0 - 8 - - - - SPIM1_NS - Serial Peripheral Interface Master with EasyDMA 2 - 0x40009000 - - - - SERIAL1 - 9 - - - - SPIS1_NS - SPI Slave 2 - 0x40009000 - SPIM1_NS - - - - SERIAL1 - 9 - - - - TWIM1_NS - I2C compatible Two-Wire Master Interface with EasyDMA 2 - 0x40009000 - SPIM1_NS - - - - SERIAL1 - 9 - - - - TWIS1_NS - I2C compatible Two-Wire Slave Interface with EasyDMA 2 - 0x40009000 - SPIM1_NS - - - - SERIAL1 - 9 - - - - UARTE1_NS - UART with EasyDMA 2 - 0x40009000 - SPIM1_NS - - - - SERIAL1 - 9 - - - - SPIM1_S - Serial Peripheral Interface Master with EasyDMA 3 - 0x50009000 - - - - SERIAL1 - 9 - - - - SPIS1_S - SPI Slave 3 - 0x50009000 - SPIM1_S - - - - SERIAL1 - 9 - - - - TWIM1_S - I2C compatible Two-Wire Master Interface with EasyDMA 3 - 0x50009000 - SPIM1_S - - - - SERIAL1 - 9 - - - - TWIS1_S - I2C compatible Two-Wire Slave Interface with EasyDMA 3 - 0x50009000 - SPIM1_S - - - - SERIAL1 - 9 - - - - UARTE1_S - UART with EasyDMA 3 - 0x50009000 - SPIM1_S - - - - SERIAL1 - 9 - - - - SPIM4_NS - Serial Peripheral Interface Master with EasyDMA 4 - 0x4000A000 - - - - SPIM4 - 10 - - - - SPIM4_S - Serial Peripheral Interface Master with EasyDMA 5 - 0x5000A000 - - - - SPIM4 - 10 - - - - SPIM2_NS - Serial Peripheral Interface Master with EasyDMA 6 - 0x4000B000 - - - - SERIAL2 - 11 - - - - SPIS2_NS - SPI Slave 4 - 0x4000B000 - SPIM2_NS - - - - SERIAL2 - 11 - - - - TWIM2_NS - I2C compatible Two-Wire Master Interface with EasyDMA 4 - 0x4000B000 - SPIM2_NS - - - - SERIAL2 - 11 - - - - TWIS2_NS - I2C compatible Two-Wire Slave Interface with EasyDMA 4 - 0x4000B000 - SPIM2_NS - - - - SERIAL2 - 11 - - - - UARTE2_NS - UART with EasyDMA 4 - 0x4000B000 - SPIM2_NS - - - - SERIAL2 - 11 - - - - SPIM2_S - Serial Peripheral Interface Master with EasyDMA 7 - 0x5000B000 - - - - SERIAL2 - 11 - - - - SPIS2_S - SPI Slave 5 - 0x5000B000 - SPIM2_S - - - - SERIAL2 - 11 - - - - TWIM2_S - I2C compatible Two-Wire Master Interface with EasyDMA 5 - 0x5000B000 - SPIM2_S - - - - SERIAL2 - 11 - - - - TWIS2_S - I2C compatible Two-Wire Slave Interface with EasyDMA 5 - 0x5000B000 - SPIM2_S - - - - SERIAL2 - 11 - - - - UARTE2_S - UART with EasyDMA 5 - 0x5000B000 - SPIM2_S - - - - SERIAL2 - 11 - - - - SPIM3_NS - Serial Peripheral Interface Master with EasyDMA 8 - 0x4000C000 - - - - SERIAL3 - 12 - - - - SPIS3_NS - SPI Slave 6 - 0x4000C000 - SPIM3_NS - - - - SERIAL3 - 12 - - - - TWIM3_NS - I2C compatible Two-Wire Master Interface with EasyDMA 6 - 0x4000C000 - SPIM3_NS - - - - SERIAL3 - 12 - - - - TWIS3_NS - I2C compatible Two-Wire Slave Interface with EasyDMA 6 - 0x4000C000 - SPIM3_NS - - - - SERIAL3 - 12 - - - - UARTE3_NS - UART with EasyDMA 6 - 0x4000C000 - SPIM3_NS - - - - SERIAL3 - 12 - - - - SPIM3_S - Serial Peripheral Interface Master with EasyDMA 9 - 0x5000C000 - - - - SERIAL3 - 12 - - - - SPIS3_S - SPI Slave 7 - 0x5000C000 - SPIM3_S - - - - SERIAL3 - 12 - - - - TWIM3_S - I2C compatible Two-Wire Master Interface with EasyDMA 7 - 0x5000C000 - SPIM3_S - - - - SERIAL3 - 12 - - - - TWIS3_S - I2C compatible Two-Wire Slave Interface with EasyDMA 7 - 0x5000C000 - SPIM3_S - - - - SERIAL3 - 12 - - - - UARTE3_S - UART with EasyDMA 7 - 0x5000C000 - SPIM3_S - - - - SERIAL3 - 12 - - - - GPIOTE0_S - GPIO Tasks and Events 0 - 0x5000D000 - GPIOTE - - - - 0 - 0x1000 - registers - - - GPIOTE0 - 13 - - GPIOTE - 0x20 - - - 0x8 - 0x4 - TASKS_OUT[%s] - Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. - 0x000 - write-only - - - TASKS_OUT - Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - 0x8 - 0x4 - TASKS_SET[%s] - Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. - 0x030 - write-only - - - TASKS_SET - Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - 0x8 - 0x4 - TASKS_CLR[%s] - Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. - 0x060 - write-only - - - TASKS_CLR - Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - 0x8 - 0x4 - SUBSCRIBE_OUT[%s] - Description collection: Subscribe configuration for task OUT[n] - 0x080 - read-write - - - CHIDX - DPPI channel that task OUT[n] will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - 0x8 - 0x4 - SUBSCRIBE_SET[%s] - Description collection: Subscribe configuration for task SET[n] - 0x0B0 - read-write - - - CHIDX - DPPI channel that task SET[n] will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - 0x8 - 0x4 - SUBSCRIBE_CLR[%s] - Description collection: Subscribe configuration for task CLR[n] - 0x0E0 - read-write - - - CHIDX - DPPI channel that task CLR[n] will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - 0x8 - 0x4 - EVENTS_IN[%s] - Description collection: Event generated from pin specified in CONFIG[n].PSEL - 0x100 - read-write - - - EVENTS_IN - Event generated from pin specified in CONFIG[n].PSEL - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_PORT - Event generated from multiple input GPIO pins with SENSE mechanism enabled - 0x17C - read-write - - - EVENTS_PORT - Event generated from multiple input GPIO pins with SENSE mechanism enabled - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - 0x8 - 0x4 - PUBLISH_IN[%s] - Description collection: Publish configuration for event IN[n] - 0x180 - read-write - - - CHIDX - DPPI channel that event IN[n] will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_PORT - Publish configuration for event PORT - 0x1FC - read-write - - - CHIDX - DPPI channel that event PORT will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - IN0 - Write '1' to enable interrupt for event IN[0] - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - IN1 - Write '1' to enable interrupt for event IN[1] - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - IN2 - Write '1' to enable interrupt for event IN[2] - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - IN3 - Write '1' to enable interrupt for event IN[3] - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - IN4 - Write '1' to enable interrupt for event IN[4] - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - IN5 - Write '1' to enable interrupt for event IN[5] - 5 - 5 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - IN6 - Write '1' to enable interrupt for event IN[6] - 6 - 6 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - IN7 - Write '1' to enable interrupt for event IN[7] - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - PORT - Write '1' to enable interrupt for event PORT - 31 - 31 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - IN0 - Write '1' to disable interrupt for event IN[0] - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - IN1 - Write '1' to disable interrupt for event IN[1] - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - IN2 - Write '1' to disable interrupt for event IN[2] - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - IN3 - Write '1' to disable interrupt for event IN[3] - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - IN4 - Write '1' to disable interrupt for event IN[4] - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - IN5 - Write '1' to disable interrupt for event IN[5] - 5 - 5 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - IN6 - Write '1' to disable interrupt for event IN[6] - 6 - 6 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - IN7 - Write '1' to disable interrupt for event IN[7] - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - PORT - Write '1' to disable interrupt for event PORT - 31 - 31 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - LATENCY - Latency selection for Event mode (MODE=Event) with rising or falling edge detection on the pin. - 0x504 - read-write - 0x00000001 - - - LATENCY - Latency setting - 0 - 0 - - - LowPower - Low power setting, for signals with minimum hold time tGPIOTE,HOLD,LP; refer to Electrical specification section - 0 - - - LowLatency - Low latency setting, for signals with minimum hold time tGPIOTE,HOLD,LL; refer to Electrical specification section - 1 - - - - - - - 0x8 - 0x4 - CONFIG[%s] - Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event - 0x510 - read-write - - - MODE - Mode - 0 - 1 - - - Disabled - Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. - 0 - - - Event - Event mode - 1 - - - Task - Task mode - 3 - - - - - PSEL - GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event - 8 - 12 - - - PORT - Port number - 13 - 13 - - - POLARITY - When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. - 16 - 17 - - - None - Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. - 0 - - - LoToHi - Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. - 1 - - - HiToLo - Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. - 2 - - - Toggle - Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. - 3 - - - - - OUTINIT - When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. - 20 - 20 - - - Low - Task mode: Initial value of pin before task triggering is low - 0 - - - High - Task mode: Initial value of pin before task triggering is high - 1 - - - - - - - - - SAADC_NS - Analog to Digital Converter 0 - 0x4000E000 - SAADC - - - - 0 - 0x1000 - registers - - - SAADC - 14 - - SAADC - 0x20 - - - TASKS_START - Start the ADC and prepare the result buffer in RAM - 0x000 - write-only - - - TASKS_START - Start the ADC and prepare the result buffer in RAM - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_SAMPLE - Take one ADC sample, if scan is enabled all channels are sampled - 0x004 - write-only - - - TASKS_SAMPLE - Take one ADC sample, if scan is enabled all channels are sampled - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STOP - Stop the ADC and terminate any ongoing conversion - 0x008 - write-only - - - TASKS_STOP - Stop the ADC and terminate any ongoing conversion - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_CALIBRATEOFFSET - Starts offset auto-calibration - 0x00C - write-only - - - TASKS_CALIBRATEOFFSET - Starts offset auto-calibration - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - SUBSCRIBE_START - Subscribe configuration for task START - 0x080 - read-write - - - CHIDX - DPPI channel that task START will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_SAMPLE - Subscribe configuration for task SAMPLE - 0x084 - read-write - - - CHIDX - DPPI channel that task SAMPLE will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_STOP - Subscribe configuration for task STOP - 0x088 - read-write - - - CHIDX - DPPI channel that task STOP will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_CALIBRATEOFFSET - Subscribe configuration for task CALIBRATEOFFSET - 0x08C - read-write - - - CHIDX - DPPI channel that task CALIBRATEOFFSET will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - EVENTS_STARTED - The ADC has started - 0x100 - read-write - - - EVENTS_STARTED - The ADC has started - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_END - The ADC has filled up the Result buffer - 0x104 - read-write - - - EVENTS_END - The ADC has filled up the Result buffer - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_DONE - A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. - 0x108 - read-write - - - EVENTS_DONE - A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_RESULTDONE - A result is ready to get transferred to RAM - 0x10C - read-write - - - EVENTS_RESULTDONE - A result is ready to get transferred to RAM - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_CALIBRATEDONE - Calibration is complete - 0x110 - read-write - - - EVENTS_CALIBRATEDONE - Calibration is complete - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_STOPPED - The ADC has stopped - 0x114 - read-write - - - EVENTS_STOPPED - The ADC has stopped - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - 8 - 0x008 - EVENTS_CH[%s] - Peripheral events. - SAADC_EVENTS_CH - read-write - 0x118 - - LIMITH - Description cluster: Last results is equal or above CH[n].LIMIT.HIGH - 0x000 - read-write - - - LIMITH - Last results is equal or above CH[n].LIMIT.HIGH - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - LIMITL - Description cluster: Last results is equal or below CH[n].LIMIT.LOW - 0x004 - read-write - - - LIMITL - Last results is equal or below CH[n].LIMIT.LOW - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - - PUBLISH_STARTED - Publish configuration for event STARTED - 0x180 - read-write - - - CHIDX - DPPI channel that event STARTED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_END - Publish configuration for event END - 0x184 - read-write - - - CHIDX - DPPI channel that event END will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_DONE - Publish configuration for event DONE - 0x188 - read-write - - - CHIDX - DPPI channel that event DONE will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_RESULTDONE - Publish configuration for event RESULTDONE - 0x18C - read-write - - - CHIDX - DPPI channel that event RESULTDONE will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_CALIBRATEDONE - Publish configuration for event CALIBRATEDONE - 0x190 - read-write - - - CHIDX - DPPI channel that event CALIBRATEDONE will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_STOPPED - Publish configuration for event STOPPED - 0x194 - read-write - - - CHIDX - DPPI channel that event STOPPED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - 8 - 0x008 - PUBLISH_CH[%s] - Publish configuration for events - SAADC_PUBLISH_CH - read-write - 0x198 - - LIMITH - Description cluster: Publish configuration for event CH[n].LIMITH - 0x000 - read-write - - - CHIDX - DPPI channel that event CH[n].LIMITH will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - LIMITL - Description cluster: Publish configuration for event CH[n].LIMITL - 0x004 - read-write - - - CHIDX - DPPI channel that event CH[n].LIMITL will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - - STARTED - Enable or disable interrupt for event STARTED - 0 - 0 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - END - Enable or disable interrupt for event END - 1 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - DONE - Enable or disable interrupt for event DONE - 2 - 2 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RESULTDONE - Enable or disable interrupt for event RESULTDONE - 3 - 3 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - CALIBRATEDONE - Enable or disable interrupt for event CALIBRATEDONE - 4 - 4 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - STOPPED - Enable or disable interrupt for event STOPPED - 5 - 5 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - CH0LIMITH - Enable or disable interrupt for event CH0LIMITH - 6 - 6 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - CH0LIMITL - Enable or disable interrupt for event CH0LIMITL - 7 - 7 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - CH1LIMITH - Enable or disable interrupt for event CH1LIMITH - 8 - 8 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - CH1LIMITL - Enable or disable interrupt for event CH1LIMITL - 9 - 9 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - CH2LIMITH - Enable or disable interrupt for event CH2LIMITH - 10 - 10 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - CH2LIMITL - Enable or disable interrupt for event CH2LIMITL - 11 - 11 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - CH3LIMITH - Enable or disable interrupt for event CH3LIMITH - 12 - 12 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - CH3LIMITL - Enable or disable interrupt for event CH3LIMITL - 13 - 13 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - CH4LIMITH - Enable or disable interrupt for event CH4LIMITH - 14 - 14 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - CH4LIMITL - Enable or disable interrupt for event CH4LIMITL - 15 - 15 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - CH5LIMITH - Enable or disable interrupt for event CH5LIMITH - 16 - 16 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - CH5LIMITL - Enable or disable interrupt for event CH5LIMITL - 17 - 17 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - CH6LIMITH - Enable or disable interrupt for event CH6LIMITH - 18 - 18 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - CH6LIMITL - Enable or disable interrupt for event CH6LIMITL - 19 - 19 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - CH7LIMITH - Enable or disable interrupt for event CH7LIMITH - 20 - 20 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - CH7LIMITL - Enable or disable interrupt for event CH7LIMITL - 21 - 21 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - STARTED - Write '1' to enable interrupt for event STARTED - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - END - Write '1' to enable interrupt for event END - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - DONE - Write '1' to enable interrupt for event DONE - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RESULTDONE - Write '1' to enable interrupt for event RESULTDONE - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CALIBRATEDONE - Write '1' to enable interrupt for event CALIBRATEDONE - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - STOPPED - Write '1' to enable interrupt for event STOPPED - 5 - 5 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CH0LIMITH - Write '1' to enable interrupt for event CH0LIMITH - 6 - 6 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CH0LIMITL - Write '1' to enable interrupt for event CH0LIMITL - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CH1LIMITH - Write '1' to enable interrupt for event CH1LIMITH - 8 - 8 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CH1LIMITL - Write '1' to enable interrupt for event CH1LIMITL - 9 - 9 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CH2LIMITH - Write '1' to enable interrupt for event CH2LIMITH - 10 - 10 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CH2LIMITL - Write '1' to enable interrupt for event CH2LIMITL - 11 - 11 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CH3LIMITH - Write '1' to enable interrupt for event CH3LIMITH - 12 - 12 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CH3LIMITL - Write '1' to enable interrupt for event CH3LIMITL - 13 - 13 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CH4LIMITH - Write '1' to enable interrupt for event CH4LIMITH - 14 - 14 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CH4LIMITL - Write '1' to enable interrupt for event CH4LIMITL - 15 - 15 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CH5LIMITH - Write '1' to enable interrupt for event CH5LIMITH - 16 - 16 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CH5LIMITL - Write '1' to enable interrupt for event CH5LIMITL - 17 - 17 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CH6LIMITH - Write '1' to enable interrupt for event CH6LIMITH - 18 - 18 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CH6LIMITL - Write '1' to enable interrupt for event CH6LIMITL - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CH7LIMITH - Write '1' to enable interrupt for event CH7LIMITH - 20 - 20 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CH7LIMITL - Write '1' to enable interrupt for event CH7LIMITL - 21 - 21 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - STARTED - Write '1' to disable interrupt for event STARTED - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - END - Write '1' to disable interrupt for event END - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - DONE - Write '1' to disable interrupt for event DONE - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RESULTDONE - Write '1' to disable interrupt for event RESULTDONE - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CALIBRATEDONE - Write '1' to disable interrupt for event CALIBRATEDONE - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - STOPPED - Write '1' to disable interrupt for event STOPPED - 5 - 5 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CH0LIMITH - Write '1' to disable interrupt for event CH0LIMITH - 6 - 6 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CH0LIMITL - Write '1' to disable interrupt for event CH0LIMITL - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CH1LIMITH - Write '1' to disable interrupt for event CH1LIMITH - 8 - 8 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CH1LIMITL - Write '1' to disable interrupt for event CH1LIMITL - 9 - 9 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CH2LIMITH - Write '1' to disable interrupt for event CH2LIMITH - 10 - 10 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CH2LIMITL - Write '1' to disable interrupt for event CH2LIMITL - 11 - 11 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CH3LIMITH - Write '1' to disable interrupt for event CH3LIMITH - 12 - 12 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CH3LIMITL - Write '1' to disable interrupt for event CH3LIMITL - 13 - 13 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CH4LIMITH - Write '1' to disable interrupt for event CH4LIMITH - 14 - 14 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CH4LIMITL - Write '1' to disable interrupt for event CH4LIMITL - 15 - 15 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CH5LIMITH - Write '1' to disable interrupt for event CH5LIMITH - 16 - 16 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CH5LIMITL - Write '1' to disable interrupt for event CH5LIMITL - 17 - 17 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CH6LIMITH - Write '1' to disable interrupt for event CH6LIMITH - 18 - 18 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CH6LIMITL - Write '1' to disable interrupt for event CH6LIMITL - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CH7LIMITH - Write '1' to disable interrupt for event CH7LIMITH - 20 - 20 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CH7LIMITL - Write '1' to disable interrupt for event CH7LIMITL - 21 - 21 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - STATUS - Status - 0x400 - read-only - - - STATUS - Status - 0 - 0 - - - Ready - ADC is ready. No ongoing conversion. - 0 - - - Busy - ADC is busy. Single conversion in progress. - 1 - - - - - - - ENABLE - Enable or disable ADC - 0x500 - read-write - - - ENABLE - Enable or disable ADC - 0 - 0 - - - Disabled - Disable ADC - 0 - - - Enabled - Enable ADC - 1 - - - - - - - 8 - 0x010 - CH[%s] - Unspecified - SAADC_CH - read-write - 0x510 - - PSELP - Description cluster: Input positive pin selection for CH[n] - 0x000 - read-write - 0x00000000 - - - PSELP - Analog positive input channel - 0 - 4 - - - NC - Not connected - 0 - - - AnalogInput0 - AIN0 - 1 - - - AnalogInput1 - AIN1 - 2 - - - AnalogInput2 - AIN2 - 3 - - - AnalogInput3 - AIN3 - 4 - - - AnalogInput4 - AIN4 - 5 - - - AnalogInput5 - AIN5 - 6 - - - AnalogInput6 - AIN6 - 7 - - - AnalogInput7 - AIN7 - 8 - - - VDD - VDD - 9 - - - VDDHDIV5 - VDDH/5 - 0xD - - - - - - - PSELN - Description cluster: Input negative pin selection for CH[n] - 0x004 - read-write - 0x00000000 - - - PSELN - Analog negative input, enables differential channel - 0 - 4 - - - NC - Not connected - 0 - - - AnalogInput0 - AIN0 - 1 - - - AnalogInput1 - AIN1 - 2 - - - AnalogInput2 - AIN2 - 3 - - - AnalogInput3 - AIN3 - 4 - - - AnalogInput4 - AIN4 - 5 - - - AnalogInput5 - AIN5 - 6 - - - AnalogInput6 - AIN6 - 7 - - - AnalogInput7 - AIN7 - 8 - - - VDD - VDD - 9 - - - VDDHDIV5 - VDDH/5 - 0xD - - - - - - - CONFIG - Description cluster: Input configuration for CH[n] - 0x008 - read-write - 0x00020000 - - - RESP - Positive channel resistor control - 0 - 1 - - - Bypass - Bypass resistor ladder - 0 - - - Pulldown - Pull-down to GND - 1 - - - Pullup - Pull-up to VDD - 2 - - - VDD1_2 - Set input at VDD/2 - 3 - - - - - RESN - Negative channel resistor control - 4 - 5 - - - Bypass - Bypass resistor ladder - 0 - - - Pulldown - Pull-down to GND - 1 - - - Pullup - Pull-up to VDD - 2 - - - VDD1_2 - Set input at VDD/2 - 3 - - - - - GAIN - Gain control - 8 - 10 - - - Gain1_6 - 1/6 - 0 - - - Gain1_5 - 1/5 - 1 - - - Gain1_4 - 1/4 - 2 - - - Gain1_3 - 1/3 - 3 - - - Gain1_2 - 1/2 - 4 - - - Gain1 - 1 - 5 - - - Gain2 - 2 - 6 - - - Gain4 - 4 - 7 - - - - - REFSEL - Reference control - 12 - 12 - - - Internal - Internal reference (0.6 V) - 0 - - - VDD1_4 - VDD/4 as reference - 1 - - - - - TACQ - Acquisition time, the time the ADC uses to sample the input voltage - 16 - 18 - - - 3us - 3 us - 0 - - - 5us - 5 us - 1 - - - 10us - 10 us - 2 - - - 15us - 15 us - 3 - - - 20us - 20 us - 4 - - - 40us - 40 us - 5 - - - - - MODE - Enable differential mode - 20 - 20 - - - SE - Single-ended, PSELN will be ignored, negative input to ADC shorted to GND - 0 - - - Diff - Differential - 1 - - - - - BURST - Enable burst mode - 24 - 24 - - - Disabled - Burst mode is disabled (normal operation) - 0 - - - Enabled - Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. - 1 - - - - - - - LIMIT - Description cluster: High/low limits for event monitoring a channel - 0x00C - read-write - 0x7FFF8000 - - - LOW - Low level limit - 0 - 15 - - - HIGH - High level limit - 16 - 31 - - - - - - RESOLUTION - Resolution configuration - 0x5F0 - read-write - 0x00000001 - - - VAL - Set the resolution - 0 - 2 - - - 8bit - 8 bit - 0 - - - 10bit - 10 bit - 1 - - - 12bit - 12 bit - 2 - - - 14bit - 14 bit - 3 - - - - - - - OVERSAMPLE - Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. - 0x5F4 - read-write - - - OVERSAMPLE - Oversample control - 0 - 3 - - - Bypass - Bypass oversampling - 0 - - - Over2x - Oversample 2x - 1 - - - Over4x - Oversample 4x - 2 - - - Over8x - Oversample 8x - 3 - - - Over16x - Oversample 16x - 4 - - - Over32x - Oversample 32x - 5 - - - Over64x - Oversample 64x - 6 - - - Over128x - Oversample 128x - 7 - - - Over256x - Oversample 256x - 8 - - - - - - - SAMPLERATE - Controls normal or continuous sample rate - 0x5F8 - read-write - - - CC - Capture and compare value; sample rate is 16 MHz/CC - 0 - 10 - - - MODE - Select mode for sample rate control - 12 - 12 - - - Task - Rate is controlled from SAMPLE task - 0 - - - Timers - Rate is controlled from local timer (use CC to control the rate) - 1 - - - - - - - RESULT - RESULT EasyDMA channel - SAADC_RESULT - read-write - 0x62C - - PTR - Data pointer - 0x000 - read-write - - - PTR - Data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of buffer words to transfer - 0x004 - read-write - - - MAXCNT - Maximum number of buffer words to transfer - 0 - 14 - - - - - AMOUNT - Number of buffer words transferred since last START - 0x008 - read-only - - - AMOUNT - Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. - 0 - 14 - - - - - - - - SAADC_S - Analog to Digital Converter 1 - 0x5000E000 - - - - SAADC - 14 - - - - TIMER0_NS - Timer/Counter 0 - 0x4000F000 - TIMER - - - - 0 - 0x1000 - registers - - - TIMER0 - 15 - - TIMER - 0x20 - - - TASKS_START - Start Timer - 0x000 - write-only - - - TASKS_START - Start Timer - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STOP - Stop Timer - 0x004 - write-only - - - TASKS_STOP - Stop Timer - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_COUNT - Increment Timer (Counter mode only) - 0x008 - write-only - - - TASKS_COUNT - Increment Timer (Counter mode only) - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_CLEAR - Clear time - 0x00C - write-only - - - TASKS_CLEAR - Clear time - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_SHUTDOWN - Deprecated register - Shut down timer - 0x010 - write-only - - - TASKS_SHUTDOWN - Deprecated field - Shut down timer - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - 0x6 - 0x4 - TASKS_CAPTURE[%s] - Description collection: Capture Timer value to CC[n] register - 0x040 - write-only - - - TASKS_CAPTURE - Capture Timer value to CC[n] register - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - SUBSCRIBE_START - Subscribe configuration for task START - 0x080 - read-write - - - CHIDX - DPPI channel that task START will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_STOP - Subscribe configuration for task STOP - 0x084 - read-write - - - CHIDX - DPPI channel that task STOP will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_COUNT - Subscribe configuration for task COUNT - 0x088 - read-write - - - CHIDX - DPPI channel that task COUNT will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_CLEAR - Subscribe configuration for task CLEAR - 0x08C - read-write - - - CHIDX - DPPI channel that task CLEAR will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_SHUTDOWN - Deprecated register - Subscribe configuration for task SHUTDOWN - 0x090 - read-write - - - CHIDX - DPPI channel that task SHUTDOWN will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - 0x6 - 0x4 - SUBSCRIBE_CAPTURE[%s] - Description collection: Subscribe configuration for task CAPTURE[n] - 0x0C0 - read-write - - - CHIDX - DPPI channel that task CAPTURE[n] will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - 0x6 - 0x4 - EVENTS_COMPARE[%s] - Description collection: Compare event on CC[n] match - 0x140 - read-write - - - EVENTS_COMPARE - Compare event on CC[n] match - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - 0x6 - 0x4 - PUBLISH_COMPARE[%s] - Description collection: Publish configuration for event COMPARE[n] - 0x1C0 - read-write - - - CHIDX - DPPI channel that event COMPARE[n] will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - SHORTS - Shortcuts between local events and tasks - 0x200 - read-write - - - COMPARE0_CLEAR - Shortcut between event COMPARE[0] and task CLEAR - 0 - 0 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - COMPARE1_CLEAR - Shortcut between event COMPARE[1] and task CLEAR - 1 - 1 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - COMPARE2_CLEAR - Shortcut between event COMPARE[2] and task CLEAR - 2 - 2 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - COMPARE3_CLEAR - Shortcut between event COMPARE[3] and task CLEAR - 3 - 3 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - COMPARE4_CLEAR - Shortcut between event COMPARE[4] and task CLEAR - 4 - 4 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - COMPARE5_CLEAR - Shortcut between event COMPARE[5] and task CLEAR - 5 - 5 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - COMPARE0_STOP - Shortcut between event COMPARE[0] and task STOP - 16 - 16 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - COMPARE1_STOP - Shortcut between event COMPARE[1] and task STOP - 17 - 17 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - COMPARE2_STOP - Shortcut between event COMPARE[2] and task STOP - 18 - 18 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - COMPARE3_STOP - Shortcut between event COMPARE[3] and task STOP - 19 - 19 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - COMPARE4_STOP - Shortcut between event COMPARE[4] and task STOP - 20 - 20 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - COMPARE5_STOP - Shortcut between event COMPARE[5] and task STOP - 21 - 21 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - - COMPARE0 - Enable or disable interrupt for event COMPARE[0] - 16 - 16 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - COMPARE1 - Enable or disable interrupt for event COMPARE[1] - 17 - 17 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - COMPARE2 - Enable or disable interrupt for event COMPARE[2] - 18 - 18 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - COMPARE3 - Enable or disable interrupt for event COMPARE[3] - 19 - 19 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - COMPARE4 - Enable or disable interrupt for event COMPARE[4] - 20 - 20 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - COMPARE5 - Enable or disable interrupt for event COMPARE[5] - 21 - 21 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - COMPARE0 - Write '1' to enable interrupt for event COMPARE[0] - 16 - 16 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - COMPARE1 - Write '1' to enable interrupt for event COMPARE[1] - 17 - 17 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - COMPARE2 - Write '1' to enable interrupt for event COMPARE[2] - 18 - 18 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - COMPARE3 - Write '1' to enable interrupt for event COMPARE[3] - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - COMPARE4 - Write '1' to enable interrupt for event COMPARE[4] - 20 - 20 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - COMPARE5 - Write '1' to enable interrupt for event COMPARE[5] - 21 - 21 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - COMPARE0 - Write '1' to disable interrupt for event COMPARE[0] - 16 - 16 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - COMPARE1 - Write '1' to disable interrupt for event COMPARE[1] - 17 - 17 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - COMPARE2 - Write '1' to disable interrupt for event COMPARE[2] - 18 - 18 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - COMPARE3 - Write '1' to disable interrupt for event COMPARE[3] - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - COMPARE4 - Write '1' to disable interrupt for event COMPARE[4] - 20 - 20 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - COMPARE5 - Write '1' to disable interrupt for event COMPARE[5] - 21 - 21 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - MODE - Timer mode selection - 0x504 - read-write - - - MODE - Timer mode - 0 - 1 - - - Timer - Select Timer mode - 0 - - - Counter - Deprecated enumerator - Select Counter mode - 1 - - - LowPowerCounter - Select Low Power Counter mode - 2 - - - - - - - BITMODE - Configure the number of bits used by the TIMER - 0x508 - read-write - - - BITMODE - Timer bit width - 0 - 1 - - - 16Bit - 16 bit timer bit width - 0 - - - 08Bit - 8 bit timer bit width - 1 - - - 24Bit - 24 bit timer bit width - 2 - - - 32Bit - 32 bit timer bit width - 3 - - - - - - - PRESCALER - Timer prescaler register - 0x510 - read-write - 0x00000004 - - - PRESCALER - Prescaler value - 0 - 3 - - - - - 0x6 - 0x4 - CC[%s] - Description collection: Capture/Compare register n - 0x540 - read-write - - - CC - Capture/Compare value - 0 - 31 - - - - - 0x6 - 0x4 - ONESHOTEN[%s] - Description collection: Enable one-shot operation for Capture/Compare channel n - 0x580 - read-write - - - ONESHOTEN - Enable one-shot operation - 0 - 0 - - - Disable - Disable one-shot operation - 0 - - - Enable - Enable one-shot operation - 1 - - - - - - - - - TIMER0_S - Timer/Counter 1 - 0x5000F000 - - - - TIMER0 - 15 - - - - TIMER1_NS - Timer/Counter 2 - 0x40010000 - - - - TIMER1 - 16 - - - - TIMER1_S - Timer/Counter 3 - 0x50010000 - - - - TIMER1 - 16 - - - - TIMER2_NS - Timer/Counter 4 - 0x40011000 - - - - TIMER2 - 17 - - - - TIMER2_S - Timer/Counter 5 - 0x50011000 - - - - TIMER2 - 17 - - - - RTC0_NS - Real-time counter 0 - 0x40014000 - RTC - - - - 0 - 0x1000 - registers - - - RTC0 - 20 - - RTC - 0x20 - - - TASKS_START - Start RTC counter - 0x000 - write-only - - - TASKS_START - Start RTC counter - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STOP - Stop RTC counter - 0x004 - write-only - - - TASKS_STOP - Stop RTC counter - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_CLEAR - Clear RTC counter - 0x008 - write-only - - - TASKS_CLEAR - Clear RTC counter - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_TRIGOVRFLW - Set counter to 0xFFFFF0 - 0x00C - write-only - - - TASKS_TRIGOVRFLW - Set counter to 0xFFFFF0 - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - 0x4 - 0x4 - TASKS_CAPTURE[%s] - Description collection: Capture RTC counter to CC[n] register - 0x040 - write-only - - - TASKS_CAPTURE - Capture RTC counter to CC[n] register - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - SUBSCRIBE_START - Subscribe configuration for task START - 0x080 - read-write - - - CHIDX - DPPI channel that task START will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_STOP - Subscribe configuration for task STOP - 0x084 - read-write - - - CHIDX - DPPI channel that task STOP will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_CLEAR - Subscribe configuration for task CLEAR - 0x088 - read-write - - - CHIDX - DPPI channel that task CLEAR will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_TRIGOVRFLW - Subscribe configuration for task TRIGOVRFLW - 0x08C - read-write - - - CHIDX - DPPI channel that task TRIGOVRFLW will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - 0x4 - 0x4 - SUBSCRIBE_CAPTURE[%s] - Description collection: Subscribe configuration for task CAPTURE[n] - 0x0C0 - read-write - - - CHIDX - DPPI channel that task CAPTURE[n] will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - EVENTS_TICK - Event on counter increment - 0x100 - read-write - - - EVENTS_TICK - Event on counter increment - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_OVRFLW - Event on counter overflow - 0x104 - read-write - - - EVENTS_OVRFLW - Event on counter overflow - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - 0x4 - 0x4 - EVENTS_COMPARE[%s] - Description collection: Compare event on CC[n] match - 0x140 - read-write - - - EVENTS_COMPARE - Compare event on CC[n] match - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - PUBLISH_TICK - Publish configuration for event TICK - 0x180 - read-write - - - CHIDX - DPPI channel that event TICK will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_OVRFLW - Publish configuration for event OVRFLW - 0x184 - read-write - - - CHIDX - DPPI channel that event OVRFLW will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - 0x4 - 0x4 - PUBLISH_COMPARE[%s] - Description collection: Publish configuration for event COMPARE[n] - 0x1C0 - read-write - - - CHIDX - DPPI channel that event COMPARE[n] will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - SHORTS - Shortcuts between local events and tasks - 0x200 - read-write - - - COMPARE0_CLEAR - Shortcut between event COMPARE[0] and task CLEAR - 0 - 0 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - COMPARE1_CLEAR - Shortcut between event COMPARE[1] and task CLEAR - 1 - 1 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - COMPARE2_CLEAR - Shortcut between event COMPARE[2] and task CLEAR - 2 - 2 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - COMPARE3_CLEAR - Shortcut between event COMPARE[3] and task CLEAR - 3 - 3 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - TICK - Write '1' to enable interrupt for event TICK - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - OVRFLW - Write '1' to enable interrupt for event OVRFLW - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - COMPARE0 - Write '1' to enable interrupt for event COMPARE[0] - 16 - 16 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - COMPARE1 - Write '1' to enable interrupt for event COMPARE[1] - 17 - 17 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - COMPARE2 - Write '1' to enable interrupt for event COMPARE[2] - 18 - 18 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - COMPARE3 - Write '1' to enable interrupt for event COMPARE[3] - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - TICK - Write '1' to disable interrupt for event TICK - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - OVRFLW - Write '1' to disable interrupt for event OVRFLW - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - COMPARE0 - Write '1' to disable interrupt for event COMPARE[0] - 16 - 16 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - COMPARE1 - Write '1' to disable interrupt for event COMPARE[1] - 17 - 17 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - COMPARE2 - Write '1' to disable interrupt for event COMPARE[2] - 18 - 18 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - COMPARE3 - Write '1' to disable interrupt for event COMPARE[3] - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - EVTEN - Enable or disable event routing - 0x340 - read-write - - - TICK - Enable or disable event routing for event TICK - 0 - 0 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - OVRFLW - Enable or disable event routing for event OVRFLW - 1 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - COMPARE0 - Enable or disable event routing for event COMPARE[0] - 16 - 16 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - COMPARE1 - Enable or disable event routing for event COMPARE[1] - 17 - 17 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - COMPARE2 - Enable or disable event routing for event COMPARE[2] - 18 - 18 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - COMPARE3 - Enable or disable event routing for event COMPARE[3] - 19 - 19 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - EVTENSET - Enable event routing - 0x344 - read-write - - - TICK - Write '1' to enable event routing for event TICK - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - OVRFLW - Write '1' to enable event routing for event OVRFLW - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - COMPARE0 - Write '1' to enable event routing for event COMPARE[0] - 16 - 16 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - COMPARE1 - Write '1' to enable event routing for event COMPARE[1] - 17 - 17 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - COMPARE2 - Write '1' to enable event routing for event COMPARE[2] - 18 - 18 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - COMPARE3 - Write '1' to enable event routing for event COMPARE[3] - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - EVTENCLR - Disable event routing - 0x348 - read-write - - - TICK - Write '1' to disable event routing for event TICK - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - OVRFLW - Write '1' to disable event routing for event OVRFLW - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - COMPARE0 - Write '1' to disable event routing for event COMPARE[0] - 16 - 16 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - COMPARE1 - Write '1' to disable event routing for event COMPARE[1] - 17 - 17 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - COMPARE2 - Write '1' to disable event routing for event COMPARE[2] - 18 - 18 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - COMPARE3 - Write '1' to disable event routing for event COMPARE[3] - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - COUNTER - Current counter value - 0x504 - read-only - - - COUNTER - Counter value - 0 - 23 - - - - - PRESCALER - 12-bit prescaler for counter frequency (32768 / (PRESCALER + 1)). Must be written when RTC is stopped. - 0x508 - read-write - - - PRESCALER - Prescaler value - 0 - 11 - - - - - 0x4 - 0x4 - CC[%s] - Description collection: Compare register n - 0x540 - read-write - - - COMPARE - Compare value - 0 - 23 - - - - - - - RTC0_S - Real-time counter 1 - 0x50014000 - - - - RTC0 - 20 - - - - RTC1_NS - Real-time counter 2 - 0x40015000 - - - - RTC1 - 21 - - - - RTC1_S - Real-time counter 3 - 0x50015000 - - - - RTC1 - 21 - - - - DPPIC_NS - Distributed programmable peripheral interconnect controller 0 - 0x40017000 - DPPIC - - - - 0 - 0x1000 - registers - - DPPIC - 0x20 - - - 6 - 0x008 - TASKS_CHG[%s] - Channel group tasks - DPPIC_TASKS_CHG - write-only - 0x000 - - EN - Description cluster: Enable channel group n - 0x000 - write-only - - - EN - Enable channel group n - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - DIS - Description cluster: Disable channel group n - 0x004 - write-only - - - DIS - Disable channel group n - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - - 6 - 0x008 - SUBSCRIBE_CHG[%s] - Subscribe configuration for tasks - DPPIC_SUBSCRIBE_CHG - read-write - 0x080 - - EN - Description cluster: Subscribe configuration for task CHG[n].EN - 0x000 - read-write - - - CHIDX - DPPI channel that task CHG[n].EN will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - DIS - Description cluster: Subscribe configuration for task CHG[n].DIS - 0x004 - read-write - - - CHIDX - DPPI channel that task CHG[n].DIS will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - - CHEN - Channel enable register - 0x500 - read-write - - - CH0 - Enable or disable channel 0 - 0 - 0 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH1 - Enable or disable channel 1 - 1 - 1 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH2 - Enable or disable channel 2 - 2 - 2 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH3 - Enable or disable channel 3 - 3 - 3 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH4 - Enable or disable channel 4 - 4 - 4 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH5 - Enable or disable channel 5 - 5 - 5 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH6 - Enable or disable channel 6 - 6 - 6 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH7 - Enable or disable channel 7 - 7 - 7 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH8 - Enable or disable channel 8 - 8 - 8 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH9 - Enable or disable channel 9 - 9 - 9 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH10 - Enable or disable channel 10 - 10 - 10 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH11 - Enable or disable channel 11 - 11 - 11 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH12 - Enable or disable channel 12 - 12 - 12 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH13 - Enable or disable channel 13 - 13 - 13 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH14 - Enable or disable channel 14 - 14 - 14 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH15 - Enable or disable channel 15 - 15 - 15 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH16 - Enable or disable channel 16 - 16 - 16 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH17 - Enable or disable channel 17 - 17 - 17 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH18 - Enable or disable channel 18 - 18 - 18 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH19 - Enable or disable channel 19 - 19 - 19 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH20 - Enable or disable channel 20 - 20 - 20 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH21 - Enable or disable channel 21 - 21 - 21 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH22 - Enable or disable channel 22 - 22 - 22 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH23 - Enable or disable channel 23 - 23 - 23 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH24 - Enable or disable channel 24 - 24 - 24 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH25 - Enable or disable channel 25 - 25 - 25 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH26 - Enable or disable channel 26 - 26 - 26 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH27 - Enable or disable channel 27 - 27 - 27 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH28 - Enable or disable channel 28 - 28 - 28 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH29 - Enable or disable channel 29 - 29 - 29 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH30 - Enable or disable channel 30 - 30 - 30 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH31 - Enable or disable channel 31 - 31 - 31 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - - - CHENSET - Channel enable set register - 0x504 - read-write - oneToSet - - - CH0 - Channel 0 enable set register. Writing 0 has no effect. - 0 - 0 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH1 - Channel 1 enable set register. Writing 0 has no effect. - 1 - 1 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH2 - Channel 2 enable set register. Writing 0 has no effect. - 2 - 2 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH3 - Channel 3 enable set register. Writing 0 has no effect. - 3 - 3 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH4 - Channel 4 enable set register. Writing 0 has no effect. - 4 - 4 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH5 - Channel 5 enable set register. Writing 0 has no effect. - 5 - 5 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH6 - Channel 6 enable set register. Writing 0 has no effect. - 6 - 6 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH7 - Channel 7 enable set register. Writing 0 has no effect. - 7 - 7 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH8 - Channel 8 enable set register. Writing 0 has no effect. - 8 - 8 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH9 - Channel 9 enable set register. Writing 0 has no effect. - 9 - 9 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH10 - Channel 10 enable set register. Writing 0 has no effect. - 10 - 10 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH11 - Channel 11 enable set register. Writing 0 has no effect. - 11 - 11 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH12 - Channel 12 enable set register. Writing 0 has no effect. - 12 - 12 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH13 - Channel 13 enable set register. Writing 0 has no effect. - 13 - 13 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH14 - Channel 14 enable set register. Writing 0 has no effect. - 14 - 14 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH15 - Channel 15 enable set register. Writing 0 has no effect. - 15 - 15 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH16 - Channel 16 enable set register. Writing 0 has no effect. - 16 - 16 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH17 - Channel 17 enable set register. Writing 0 has no effect. - 17 - 17 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH18 - Channel 18 enable set register. Writing 0 has no effect. - 18 - 18 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH19 - Channel 19 enable set register. Writing 0 has no effect. - 19 - 19 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH20 - Channel 20 enable set register. Writing 0 has no effect. - 20 - 20 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH21 - Channel 21 enable set register. Writing 0 has no effect. - 21 - 21 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH22 - Channel 22 enable set register. Writing 0 has no effect. - 22 - 22 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH23 - Channel 23 enable set register. Writing 0 has no effect. - 23 - 23 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH24 - Channel 24 enable set register. Writing 0 has no effect. - 24 - 24 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH25 - Channel 25 enable set register. Writing 0 has no effect. - 25 - 25 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH26 - Channel 26 enable set register. Writing 0 has no effect. - 26 - 26 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH27 - Channel 27 enable set register. Writing 0 has no effect. - 27 - 27 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH28 - Channel 28 enable set register. Writing 0 has no effect. - 28 - 28 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH29 - Channel 29 enable set register. Writing 0 has no effect. - 29 - 29 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH30 - Channel 30 enable set register. Writing 0 has no effect. - 30 - 30 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH31 - Channel 31 enable set register. Writing 0 has no effect. - 31 - 31 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - - - CHENCLR - Channel enable clear register - 0x508 - read-write - oneToClear - - - CH0 - Channel 0 enable clear register. Writing 0 has no effect. - 0 - 0 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Clear - Write: Disable channel - 1 - - - - - CH1 - Channel 1 enable clear register. Writing 0 has no effect. - 1 - 1 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Clear - Write: Disable channel - 1 - - - - - CH2 - Channel 2 enable clear register. Writing 0 has no effect. - 2 - 2 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Clear - Write: Disable channel - 1 - - - - - CH3 - Channel 3 enable clear register. Writing 0 has no effect. - 3 - 3 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Clear - Write: Disable channel - 1 - - - - - CH4 - Channel 4 enable clear register. Writing 0 has no effect. - 4 - 4 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Clear - Write: Disable channel - 1 - - - - - CH5 - Channel 5 enable clear register. Writing 0 has no effect. - 5 - 5 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Clear - Write: Disable channel - 1 - - - - - CH6 - Channel 6 enable clear register. Writing 0 has no effect. - 6 - 6 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Clear - Write: Disable channel - 1 - - - - - CH7 - Channel 7 enable clear register. Writing 0 has no effect. - 7 - 7 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Clear - Write: Disable channel - 1 - - - - - CH8 - Channel 8 enable clear register. Writing 0 has no effect. - 8 - 8 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Clear - Write: Disable channel - 1 - - - - - CH9 - Channel 9 enable clear register. Writing 0 has no effect. - 9 - 9 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Clear - Write: Disable channel - 1 - - - - - CH10 - Channel 10 enable clear register. Writing 0 has no effect. - 10 - 10 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Clear - Write: Disable channel - 1 - - - - - CH11 - Channel 11 enable clear register. Writing 0 has no effect. - 11 - 11 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Clear - Write: Disable channel - 1 - - - - - CH12 - Channel 12 enable clear register. Writing 0 has no effect. - 12 - 12 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Clear - Write: Disable channel - 1 - - - - - CH13 - Channel 13 enable clear register. Writing 0 has no effect. - 13 - 13 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Clear - Write: Disable channel - 1 - - - - - CH14 - Channel 14 enable clear register. Writing 0 has no effect. - 14 - 14 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Clear - Write: Disable channel - 1 - - - - - CH15 - Channel 15 enable clear register. Writing 0 has no effect. - 15 - 15 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Clear - Write: Disable channel - 1 - - - - - CH16 - Channel 16 enable clear register. Writing 0 has no effect. - 16 - 16 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Clear - Write: Disable channel - 1 - - - - - CH17 - Channel 17 enable clear register. Writing 0 has no effect. - 17 - 17 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Clear - Write: Disable channel - 1 - - - - - CH18 - Channel 18 enable clear register. Writing 0 has no effect. - 18 - 18 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Clear - Write: Disable channel - 1 - - - - - CH19 - Channel 19 enable clear register. Writing 0 has no effect. - 19 - 19 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Clear - Write: Disable channel - 1 - - - - - CH20 - Channel 20 enable clear register. Writing 0 has no effect. - 20 - 20 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Clear - Write: Disable channel - 1 - - - - - CH21 - Channel 21 enable clear register. Writing 0 has no effect. - 21 - 21 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Clear - Write: Disable channel - 1 - - - - - CH22 - Channel 22 enable clear register. Writing 0 has no effect. - 22 - 22 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Clear - Write: Disable channel - 1 - - - - - CH23 - Channel 23 enable clear register. Writing 0 has no effect. - 23 - 23 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Clear - Write: Disable channel - 1 - - - - - CH24 - Channel 24 enable clear register. Writing 0 has no effect. - 24 - 24 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Clear - Write: Disable channel - 1 - - - - - CH25 - Channel 25 enable clear register. Writing 0 has no effect. - 25 - 25 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Clear - Write: Disable channel - 1 - - - - - CH26 - Channel 26 enable clear register. Writing 0 has no effect. - 26 - 26 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Clear - Write: Disable channel - 1 - - - - - CH27 - Channel 27 enable clear register. Writing 0 has no effect. - 27 - 27 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Clear - Write: Disable channel - 1 - - - - - CH28 - Channel 28 enable clear register. Writing 0 has no effect. - 28 - 28 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Clear - Write: Disable channel - 1 - - - - - CH29 - Channel 29 enable clear register. Writing 0 has no effect. - 29 - 29 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Clear - Write: Disable channel - 1 - - - - - CH30 - Channel 30 enable clear register. Writing 0 has no effect. - 30 - 30 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Clear - Write: Disable channel - 1 - - - - - CH31 - Channel 31 enable clear register. Writing 0 has no effect. - 31 - 31 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Clear - Write: Disable channel - 1 - - - - - - - 0x6 - 0x4 - CHG[%s] - Description collection: Channel group n Note: Writes to this register are ignored if either SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS is enabled - 0x800 - read-write - - - CH0 - Include or exclude channel 0 - 0 - 0 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH1 - Include or exclude channel 1 - 1 - 1 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH2 - Include or exclude channel 2 - 2 - 2 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH3 - Include or exclude channel 3 - 3 - 3 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH4 - Include or exclude channel 4 - 4 - 4 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH5 - Include or exclude channel 5 - 5 - 5 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH6 - Include or exclude channel 6 - 6 - 6 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH7 - Include or exclude channel 7 - 7 - 7 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH8 - Include or exclude channel 8 - 8 - 8 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH9 - Include or exclude channel 9 - 9 - 9 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH10 - Include or exclude channel 10 - 10 - 10 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH11 - Include or exclude channel 11 - 11 - 11 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH12 - Include or exclude channel 12 - 12 - 12 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH13 - Include or exclude channel 13 - 13 - 13 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH14 - Include or exclude channel 14 - 14 - 14 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH15 - Include or exclude channel 15 - 15 - 15 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH16 - Include or exclude channel 16 - 16 - 16 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH17 - Include or exclude channel 17 - 17 - 17 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH18 - Include or exclude channel 18 - 18 - 18 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH19 - Include or exclude channel 19 - 19 - 19 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH20 - Include or exclude channel 20 - 20 - 20 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH21 - Include or exclude channel 21 - 21 - 21 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH22 - Include or exclude channel 22 - 22 - 22 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH23 - Include or exclude channel 23 - 23 - 23 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH24 - Include or exclude channel 24 - 24 - 24 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH25 - Include or exclude channel 25 - 25 - 25 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH26 - Include or exclude channel 26 - 26 - 26 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH27 - Include or exclude channel 27 - 27 - 27 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH28 - Include or exclude channel 28 - 28 - 28 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH29 - Include or exclude channel 29 - 29 - 29 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH30 - Include or exclude channel 30 - 30 - 30 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH31 - Include or exclude channel 31 - 31 - 31 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - - - - - DPPIC_S - Distributed programmable peripheral interconnect controller 1 - 0x50017000 - - - - - WDT0_NS - Watchdog Timer 0 - 0x40018000 - WDT - - - - 0 - 0x1000 - registers - - - WDT0 - 24 - - WDT - 0x20 - - - TASKS_START - Start WDT - 0x000 - write-only - - - TASKS_START - Start WDT - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STOP - Stop WDT - 0x004 - write-only - - - TASKS_STOP - Stop WDT - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - SUBSCRIBE_START - Subscribe configuration for task START - 0x080 - read-write - - - CHIDX - DPPI channel that task START will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_STOP - Subscribe configuration for task STOP - 0x084 - read-write - - - CHIDX - DPPI channel that task STOP will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - EVENTS_TIMEOUT - Watchdog timeout - 0x100 - read-write - - - EVENTS_TIMEOUT - Watchdog timeout - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_STOPPED - Watchdog stopped - 0x104 - read-write - - - EVENTS_STOPPED - Watchdog stopped - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - PUBLISH_TIMEOUT - Publish configuration for event TIMEOUT - 0x180 - read-write - - - CHIDX - DPPI channel that event TIMEOUT will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_STOPPED - Publish configuration for event STOPPED - 0x184 - read-write - - - CHIDX - DPPI channel that event STOPPED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - TIMEOUT - Write '1' to enable interrupt for event TIMEOUT - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - STOPPED - Write '1' to enable interrupt for event STOPPED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - TIMEOUT - Write '1' to disable interrupt for event TIMEOUT - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - STOPPED - Write '1' to disable interrupt for event STOPPED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - NMIENSET - Enable interrupt - 0x324 - read-write - - - TIMEOUT - Write '1' to enable interrupt for event TIMEOUT - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - STOPPED - Write '1' to enable interrupt for event STOPPED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - NMIENCLR - Disable interrupt - 0x328 - read-write - - - TIMEOUT - Write '1' to disable interrupt for event TIMEOUT - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - STOPPED - Write '1' to disable interrupt for event STOPPED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - RUNSTATUS - Run status - 0x400 - read-only - - - RUNSTATUSWDT - Indicates whether or not WDT is running - 0 - 0 - - - NotRunning - Watchdog is not running - 0 - - - Running - Watchdog is running - 1 - - - - - - - REQSTATUS - Request status - 0x404 - read-only - 0x00000001 - - - RR0 - Request status for RR[0] register - 0 - 0 - - - DisabledOrRequested - RR[0] register is not enabled, or are already requesting reload - 0 - - - EnabledAndUnrequested - RR[0] register is enabled, and are not yet requesting reload - 1 - - - - - RR1 - Request status for RR[1] register - 1 - 1 - - - DisabledOrRequested - RR[1] register is not enabled, or are already requesting reload - 0 - - - EnabledAndUnrequested - RR[1] register is enabled, and are not yet requesting reload - 1 - - - - - RR2 - Request status for RR[2] register - 2 - 2 - - - DisabledOrRequested - RR[2] register is not enabled, or are already requesting reload - 0 - - - EnabledAndUnrequested - RR[2] register is enabled, and are not yet requesting reload - 1 - - - - - RR3 - Request status for RR[3] register - 3 - 3 - - - DisabledOrRequested - RR[3] register is not enabled, or are already requesting reload - 0 - - - EnabledAndUnrequested - RR[3] register is enabled, and are not yet requesting reload - 1 - - - - - RR4 - Request status for RR[4] register - 4 - 4 - - - DisabledOrRequested - RR[4] register is not enabled, or are already requesting reload - 0 - - - EnabledAndUnrequested - RR[4] register is enabled, and are not yet requesting reload - 1 - - - - - RR5 - Request status for RR[5] register - 5 - 5 - - - DisabledOrRequested - RR[5] register is not enabled, or are already requesting reload - 0 - - - EnabledAndUnrequested - RR[5] register is enabled, and are not yet requesting reload - 1 - - - - - RR6 - Request status for RR[6] register - 6 - 6 - - - DisabledOrRequested - RR[6] register is not enabled, or are already requesting reload - 0 - - - EnabledAndUnrequested - RR[6] register is enabled, and are not yet requesting reload - 1 - - - - - RR7 - Request status for RR[7] register - 7 - 7 - - - DisabledOrRequested - RR[7] register is not enabled, or are already requesting reload - 0 - - - EnabledAndUnrequested - RR[7] register is enabled, and are not yet requesting reload - 1 - - - - - - - CRV - Counter reload value - 0x504 - read-write - 0xFFFFFFFF - - - CRV - Counter reload value in number of cycles of the 32.768 kHz clock - 0 - 31 - - - - - RREN - Enable register for reload request registers - 0x508 - read-write - 0x00000001 - - - RR0 - Enable or disable RR[0] register - 0 - 0 - - - Disabled - Disable RR[0] register - 0 - - - Enabled - Enable RR[0] register - 1 - - - - - RR1 - Enable or disable RR[1] register - 1 - 1 - - - Disabled - Disable RR[1] register - 0 - - - Enabled - Enable RR[1] register - 1 - - - - - RR2 - Enable or disable RR[2] register - 2 - 2 - - - Disabled - Disable RR[2] register - 0 - - - Enabled - Enable RR[2] register - 1 - - - - - RR3 - Enable or disable RR[3] register - 3 - 3 - - - Disabled - Disable RR[3] register - 0 - - - Enabled - Enable RR[3] register - 1 - - - - - RR4 - Enable or disable RR[4] register - 4 - 4 - - - Disabled - Disable RR[4] register - 0 - - - Enabled - Enable RR[4] register - 1 - - - - - RR5 - Enable or disable RR[5] register - 5 - 5 - - - Disabled - Disable RR[5] register - 0 - - - Enabled - Enable RR[5] register - 1 - - - - - RR6 - Enable or disable RR[6] register - 6 - 6 - - - Disabled - Disable RR[6] register - 0 - - - Enabled - Enable RR[6] register - 1 - - - - - RR7 - Enable or disable RR[7] register - 7 - 7 - - - Disabled - Disable RR[7] register - 0 - - - Enabled - Enable RR[7] register - 1 - - - - - - - CONFIG - Configuration register - 0x50C - read-write - 0x00000001 - - - SLEEP - Configure WDT to either be paused, or kept running, while the CPU is sleeping - 0 - 0 - - - Pause - Pause WDT while the CPU is sleeping - 0 - - - Run - Keep WDT running while the CPU is sleeping - 1 - - - - - HALT - Configure WDT to either be paused, or kept running, while the CPU is halted by the debugger - 3 - 3 - - - Pause - Pause WDT while the CPU is halted by the debugger - 0 - - - Run - Keep WDT running while the CPU is halted by the debugger - 1 - - - - - STOPEN - Allow stopping WDT - 6 - 6 - - - Disable - Do not allow stopping WDT - 0 - - - Enable - Allow stopping WDT - 1 - - - - - - - TSEN - Task stop enable - 0x520 - write-only - 0x00000000 - - - TSEN - Allow stopping WDT - 0 - 31 - - - Enable - Value to allow stopping WDT - 0x6E524635 - - - - - - - 0x8 - 0x4 - RR[%s] - Description collection: Reload request n - 0x600 - write-only - - - RR - Reload request register - 0 - 31 - - - Reload - Value to request a reload of the watchdog timer - 0x6E524635 - - - - - - - - - WDT0_S - Watchdog Timer 1 - 0x50018000 - - - - WDT0 - 24 - - - - WDT1_NS - Watchdog Timer 2 - 0x40019000 - - - - WDT1 - 25 - - - - WDT1_S - Watchdog Timer 3 - 0x50019000 - - - - WDT1 - 25 - - - - COMP_NS - Comparator 0 - 0x4001A000 - COMP - - - - 0 - 0x1000 - registers - - - COMP_LPCOMP - 26 - - COMP - 0x20 - - - TASKS_START - Start comparator - 0x000 - write-only - - - TASKS_START - Start comparator - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STOP - Stop comparator - 0x004 - write-only - - - TASKS_STOP - Stop comparator - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_SAMPLE - Sample comparator value - 0x008 - write-only - - - TASKS_SAMPLE - Sample comparator value - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - SUBSCRIBE_START - Subscribe configuration for task START - 0x080 - read-write - - - CHIDX - DPPI channel that task START will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_STOP - Subscribe configuration for task STOP - 0x084 - read-write - - - CHIDX - DPPI channel that task STOP will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_SAMPLE - Subscribe configuration for task SAMPLE - 0x088 - read-write - - - CHIDX - DPPI channel that task SAMPLE will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - EVENTS_READY - COMP is ready and output is valid - 0x100 - read-write - - - EVENTS_READY - COMP is ready and output is valid - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_DOWN - Downward crossing - 0x104 - read-write - - - EVENTS_DOWN - Downward crossing - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_UP - Upward crossing - 0x108 - read-write - - - EVENTS_UP - Upward crossing - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_CROSS - Downward or upward crossing - 0x10C - read-write - - - EVENTS_CROSS - Downward or upward crossing - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - PUBLISH_READY - Publish configuration for event READY - 0x180 - read-write - - - CHIDX - DPPI channel that event READY will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_DOWN - Publish configuration for event DOWN - 0x184 - read-write - - - CHIDX - DPPI channel that event DOWN will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_UP - Publish configuration for event UP - 0x188 - read-write - - - CHIDX - DPPI channel that event UP will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_CROSS - Publish configuration for event CROSS - 0x18C - read-write - - - CHIDX - DPPI channel that event CROSS will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - SHORTS - Shortcuts between local events and tasks - 0x200 - read-write - - - READY_SAMPLE - Shortcut between event READY and task SAMPLE - 0 - 0 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - READY_STOP - Shortcut between event READY and task STOP - 1 - 1 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - DOWN_STOP - Shortcut between event DOWN and task STOP - 2 - 2 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - UP_STOP - Shortcut between event UP and task STOP - 3 - 3 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - CROSS_STOP - Shortcut between event CROSS and task STOP - 4 - 4 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - - READY - Enable or disable interrupt for event READY - 0 - 0 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - DOWN - Enable or disable interrupt for event DOWN - 1 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - UP - Enable or disable interrupt for event UP - 2 - 2 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - CROSS - Enable or disable interrupt for event CROSS - 3 - 3 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - READY - Write '1' to enable interrupt for event READY - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - DOWN - Write '1' to enable interrupt for event DOWN - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - UP - Write '1' to enable interrupt for event UP - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CROSS - Write '1' to enable interrupt for event CROSS - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - READY - Write '1' to disable interrupt for event READY - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - DOWN - Write '1' to disable interrupt for event DOWN - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - UP - Write '1' to disable interrupt for event UP - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CROSS - Write '1' to disable interrupt for event CROSS - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - RESULT - Compare result - 0x400 - read-only - - - RESULT - Result of last compare. Decision point SAMPLE task. - 0 - 0 - - - Below - Input voltage is below the threshold (VIN+ &lt; VIN-) - 0 - - - Above - Input voltage is above the threshold (VIN+ &gt; VIN-) - 1 - - - - - - - ENABLE - COMP enable - 0x500 - read-write - - - ENABLE - Enable or disable COMP - 0 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 2 - - - - - - - PSEL - Pin select - 0x504 - read-write - - - PSEL - Analog pin select - 0 - 2 - - - AnalogInput0 - AIN0 selected as analog input - 0 - - - AnalogInput1 - AIN1 selected as analog input - 1 - - - AnalogInput2 - AIN2 selected as analog input - 2 - - - AnalogInput3 - AIN3 selected as analog input - 3 - - - AnalogInput4 - AIN4 selected as analog input - 4 - - - AnalogInput5 - AIN5 selected as analog input - 5 - - - AnalogInput6 - AIN6 selected as analog input - 6 - - - AnalogInput7 - AIN7 selected as analog input - 7 - - - - - - - REFSEL - Reference source select for single-ended mode - 0x508 - read-write - 0x00000004 - - - REFSEL - Reference select - 0 - 2 - - - Int1V2 - VREF = internal 1.2 V reference (VDD &gt;= 1.7 V) - 0 - - - Int1V8 - VREF = internal 1.8 V reference (VDD &gt;= VREF + 0.2 V) - 1 - - - Int2V4 - VREF = internal 2.4 V reference (VDD &gt;= VREF + 0.2 V) - 2 - - - VDD - VREF = VDD - 4 - - - ARef - VREF = AREF - 5 - - - - - - - EXTREFSEL - External reference select - 0x50C - read-write - - - EXTREFSEL - External analog reference select - 0 - 2 - - - AnalogReference0 - Use AIN0 as external analog reference - 0 - - - AnalogReference1 - Use AIN1 as external analog reference - 1 - - - AnalogReference2 - Use AIN2 as external analog reference - 2 - - - AnalogReference3 - Use AIN3 as external analog reference - 3 - - - AnalogReference4 - Use AIN4 as external analog reference - 4 - - - AnalogReference5 - Use AIN5 as external analog reference - 5 - - - AnalogReference6 - Use AIN6 as external analog reference - 6 - - - AnalogReference7 - Use AIN7 as external analog reference - 7 - - - - - - - TH - Threshold configuration for hysteresis unit - 0x530 - read-write - 0x00000000 - - - THDOWN - VDOWN = (THDOWN+1)/64*VREF - 0 - 5 - - - THUP - VUP = (THUP+1)/64*VREF - 8 - 13 - - - - - MODE - Mode configuration - 0x534 - read-write - - - SP - Speed and power modes - 0 - 1 - - - Low - Low-power mode - 0 - - - Normal - Normal mode - 1 - - - High - High-speed mode - 2 - - - - - MAIN - Main operation modes - 8 - 8 - - - SE - Single-ended mode - 0 - - - Diff - Differential mode - 1 - - - - - - - HYST - Comparator hysteresis enable - 0x538 - read-write - - - HYST - Comparator hysteresis - 0 - 0 - - - NoHyst - Comparator hysteresis disabled - 0 - - - Hyst50mV - Comparator hysteresis enabled - 1 - - - - - - - ISOURCE - Current source select on analog input - 0x53C - read-write - - - ISOURCE - Comparator hysteresis - 0 - 1 - - - Off - Current source disabled - 0 - - - Ien2mA5 - Current source enabled (+/- 2.5 uA) - 1 - - - Ien5mA - Current source enabled (+/- 5 uA) - 2 - - - Ien10mA - Current source enabled (+/- 10 uA) - 3 - - - - - - - - - LPCOMP_NS - Low-power comparator 0 - 0x4001A000 - COMP_NS - LPCOMP - - - - 0 - 0x1000 - registers - - - COMP_LPCOMP - 26 - - LPCOMP - 0x20 - - - TASKS_START - Start comparator - 0x000 - write-only - - - TASKS_START - Start comparator - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STOP - Stop comparator - 0x004 - write-only - - - TASKS_STOP - Stop comparator - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_SAMPLE - Sample comparator value - 0x008 - write-only - - - TASKS_SAMPLE - Sample comparator value - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - SUBSCRIBE_START - Subscribe configuration for task START - 0x080 - read-write - - - CHIDX - DPPI channel that task START will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_STOP - Subscribe configuration for task STOP - 0x084 - read-write - - - CHIDX - DPPI channel that task STOP will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_SAMPLE - Subscribe configuration for task SAMPLE - 0x088 - read-write - - - CHIDX - DPPI channel that task SAMPLE will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - EVENTS_READY - LPCOMP is ready and output is valid - 0x100 - read-write - - - EVENTS_READY - LPCOMP is ready and output is valid - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_DOWN - Downward crossing - 0x104 - read-write - - - EVENTS_DOWN - Downward crossing - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_UP - Upward crossing - 0x108 - read-write - - - EVENTS_UP - Upward crossing - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_CROSS - Downward or upward crossing - 0x10C - read-write - - - EVENTS_CROSS - Downward or upward crossing - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - PUBLISH_READY - Publish configuration for event READY - 0x180 - read-write - - - CHIDX - DPPI channel that event READY will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_DOWN - Publish configuration for event DOWN - 0x184 - read-write - - - CHIDX - DPPI channel that event DOWN will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_UP - Publish configuration for event UP - 0x188 - read-write - - - CHIDX - DPPI channel that event UP will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_CROSS - Publish configuration for event CROSS - 0x18C - read-write - - - CHIDX - DPPI channel that event CROSS will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - SHORTS - Shortcuts between local events and tasks - 0x200 - read-write - - - READY_SAMPLE - Shortcut between event READY and task SAMPLE - 0 - 0 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - READY_STOP - Shortcut between event READY and task STOP - 1 - 1 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - DOWN_STOP - Shortcut between event DOWN and task STOP - 2 - 2 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - UP_STOP - Shortcut between event UP and task STOP - 3 - 3 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - CROSS_STOP - Shortcut between event CROSS and task STOP - 4 - 4 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - READY - Write '1' to enable interrupt for event READY - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - DOWN - Write '1' to enable interrupt for event DOWN - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - UP - Write '1' to enable interrupt for event UP - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CROSS - Write '1' to enable interrupt for event CROSS - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - READY - Write '1' to disable interrupt for event READY - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - DOWN - Write '1' to disable interrupt for event DOWN - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - UP - Write '1' to disable interrupt for event UP - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CROSS - Write '1' to disable interrupt for event CROSS - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - RESULT - Compare result - 0x400 - read-only - - - RESULT - Result of last compare. Decision point SAMPLE task. - 0 - 0 - - - Below - Input voltage is below the reference threshold (VIN+ &lt; VIN-) - 0 - - - Above - Input voltage is above the reference threshold (VIN+ &gt; VIN-) - 1 - - - - - - - ENABLE - Enable LPCOMP - 0x500 - read-write - - - ENABLE - Enable or disable LPCOMP - 0 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - PSEL - Input pin select - 0x504 - read-write - - - PSEL - Analog pin select - 0 - 2 - - - AnalogInput0 - AIN0 selected as analog input - 0 - - - AnalogInput1 - AIN1 selected as analog input - 1 - - - AnalogInput2 - AIN2 selected as analog input - 2 - - - AnalogInput3 - AIN3 selected as analog input - 3 - - - AnalogInput4 - AIN4 selected as analog input - 4 - - - AnalogInput5 - AIN5 selected as analog input - 5 - - - AnalogInput6 - AIN6 selected as analog input - 6 - - - AnalogInput7 - AIN7 selected as analog input - 7 - - - - - - - REFSEL - Reference select - 0x508 - read-write - 0x00000004 - - - REFSEL - Reference select - 0 - 3 - - - Ref1_8Vdd - VDD * 1/8 selected as reference - 0 - - - Ref2_8Vdd - VDD * 2/8 selected as reference - 1 - - - Ref3_8Vdd - VDD * 3/8 selected as reference - 2 - - - Ref4_8Vdd - VDD * 4/8 selected as reference - 3 - - - Ref5_8Vdd - VDD * 5/8 selected as reference - 4 - - - Ref6_8Vdd - VDD * 6/8 selected as reference - 5 - - - Ref7_8Vdd - VDD * 7/8 selected as reference - 6 - - - ARef - External analog reference selected - 7 - - - Ref1_16Vdd - VDD * 1/16 selected as reference - 8 - - - Ref3_16Vdd - VDD * 3/16 selected as reference - 9 - - - Ref5_16Vdd - VDD * 5/16 selected as reference - 10 - - - Ref7_16Vdd - VDD * 7/16 selected as reference - 11 - - - Ref9_16Vdd - VDD * 9/16 selected as reference - 12 - - - Ref11_16Vdd - VDD * 11/16 selected as reference - 13 - - - Ref13_16Vdd - VDD * 13/16 selected as reference - 14 - - - Ref15_16Vdd - VDD * 15/16 selected as reference - 15 - - - - - - - EXTREFSEL - External reference select - 0x50C - read-write - - - EXTREFSEL - External analog reference select - 0 - 0 - - - AnalogReference0 - Use AIN0 as external analog reference - 0 - - - AnalogReference1 - Use AIN1 as external analog reference - 1 - - - - - - - ANADETECT - Analog detect configuration - 0x520 - read-write - - - ANADETECT - Analog detect configuration - 0 - 1 - - - Cross - Generate ANADETECT on crossing, both upward crossing and downward crossing - 0 - - - Up - Generate ANADETECT on upward crossing only - 1 - - - Down - Generate ANADETECT on downward crossing only - 2 - - - - - - - HYST - Comparator hysteresis enable - 0x538 - read-write - - - HYST - Comparator hysteresis enable - 0 - 0 - - - Disabled - Comparator hysteresis disabled - 0 - - - Enabled - Comparator hysteresis enabled - 1 - - - - - - - - - COMP_S - Comparator 1 - 0x5001A000 - - - - COMP_LPCOMP - 26 - - - - LPCOMP_S - Low-power comparator 1 - 0x5001A000 - COMP_S - - - - COMP_LPCOMP - 26 - - - - EGU0_NS - Event generator unit 0 - 0x4001B000 - EGU - - - - 0 - 0x1000 - registers - - - EGU0 - 27 - - EGU - 0x20 - - - 0x10 - 0x4 - TASKS_TRIGGER[%s] - Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event - 0x000 - write-only - - - TASKS_TRIGGER - Trigger n for triggering the corresponding TRIGGERED[n] event - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - 0x10 - 0x4 - SUBSCRIBE_TRIGGER[%s] - Description collection: Subscribe configuration for task TRIGGER[n] - 0x080 - read-write - - - CHIDX - DPPI channel that task TRIGGER[n] will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - 0x10 - 0x4 - EVENTS_TRIGGERED[%s] - Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task - 0x100 - read-write - - - EVENTS_TRIGGERED - Event number n generated by triggering the corresponding TRIGGER[n] task - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - 0x10 - 0x4 - PUBLISH_TRIGGERED[%s] - Description collection: Publish configuration for event TRIGGERED[n] - 0x180 - read-write - - - CHIDX - DPPI channel that event TRIGGERED[n] will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - - TRIGGERED0 - Enable or disable interrupt for event TRIGGERED[0] - 0 - 0 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED1 - Enable or disable interrupt for event TRIGGERED[1] - 1 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED2 - Enable or disable interrupt for event TRIGGERED[2] - 2 - 2 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED3 - Enable or disable interrupt for event TRIGGERED[3] - 3 - 3 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED4 - Enable or disable interrupt for event TRIGGERED[4] - 4 - 4 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED5 - Enable or disable interrupt for event TRIGGERED[5] - 5 - 5 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED6 - Enable or disable interrupt for event TRIGGERED[6] - 6 - 6 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED7 - Enable or disable interrupt for event TRIGGERED[7] - 7 - 7 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED8 - Enable or disable interrupt for event TRIGGERED[8] - 8 - 8 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED9 - Enable or disable interrupt for event TRIGGERED[9] - 9 - 9 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED10 - Enable or disable interrupt for event TRIGGERED[10] - 10 - 10 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED11 - Enable or disable interrupt for event TRIGGERED[11] - 11 - 11 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED12 - Enable or disable interrupt for event TRIGGERED[12] - 12 - 12 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED13 - Enable or disable interrupt for event TRIGGERED[13] - 13 - 13 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED14 - Enable or disable interrupt for event TRIGGERED[14] - 14 - 14 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED15 - Enable or disable interrupt for event TRIGGERED[15] - 15 - 15 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - TRIGGERED0 - Write '1' to enable interrupt for event TRIGGERED[0] - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TRIGGERED1 - Write '1' to enable interrupt for event TRIGGERED[1] - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TRIGGERED2 - Write '1' to enable interrupt for event TRIGGERED[2] - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TRIGGERED3 - Write '1' to enable interrupt for event TRIGGERED[3] - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TRIGGERED4 - Write '1' to enable interrupt for event TRIGGERED[4] - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TRIGGERED5 - Write '1' to enable interrupt for event TRIGGERED[5] - 5 - 5 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TRIGGERED6 - Write '1' to enable interrupt for event TRIGGERED[6] - 6 - 6 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TRIGGERED7 - Write '1' to enable interrupt for event TRIGGERED[7] - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TRIGGERED8 - Write '1' to enable interrupt for event TRIGGERED[8] - 8 - 8 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TRIGGERED9 - Write '1' to enable interrupt for event TRIGGERED[9] - 9 - 9 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TRIGGERED10 - Write '1' to enable interrupt for event TRIGGERED[10] - 10 - 10 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TRIGGERED11 - Write '1' to enable interrupt for event TRIGGERED[11] - 11 - 11 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TRIGGERED12 - Write '1' to enable interrupt for event TRIGGERED[12] - 12 - 12 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TRIGGERED13 - Write '1' to enable interrupt for event TRIGGERED[13] - 13 - 13 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TRIGGERED14 - Write '1' to enable interrupt for event TRIGGERED[14] - 14 - 14 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TRIGGERED15 - Write '1' to enable interrupt for event TRIGGERED[15] - 15 - 15 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - TRIGGERED0 - Write '1' to disable interrupt for event TRIGGERED[0] - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TRIGGERED1 - Write '1' to disable interrupt for event TRIGGERED[1] - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TRIGGERED2 - Write '1' to disable interrupt for event TRIGGERED[2] - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TRIGGERED3 - Write '1' to disable interrupt for event TRIGGERED[3] - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TRIGGERED4 - Write '1' to disable interrupt for event TRIGGERED[4] - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TRIGGERED5 - Write '1' to disable interrupt for event TRIGGERED[5] - 5 - 5 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TRIGGERED6 - Write '1' to disable interrupt for event TRIGGERED[6] - 6 - 6 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TRIGGERED7 - Write '1' to disable interrupt for event TRIGGERED[7] - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TRIGGERED8 - Write '1' to disable interrupt for event TRIGGERED[8] - 8 - 8 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TRIGGERED9 - Write '1' to disable interrupt for event TRIGGERED[9] - 9 - 9 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TRIGGERED10 - Write '1' to disable interrupt for event TRIGGERED[10] - 10 - 10 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TRIGGERED11 - Write '1' to disable interrupt for event TRIGGERED[11] - 11 - 11 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TRIGGERED12 - Write '1' to disable interrupt for event TRIGGERED[12] - 12 - 12 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TRIGGERED13 - Write '1' to disable interrupt for event TRIGGERED[13] - 13 - 13 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TRIGGERED14 - Write '1' to disable interrupt for event TRIGGERED[14] - 14 - 14 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TRIGGERED15 - Write '1' to disable interrupt for event TRIGGERED[15] - 15 - 15 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - - - EGU0_S - Event generator unit 1 - 0x5001B000 - - - - EGU0 - 27 - - - - EGU1_NS - Event generator unit 2 - 0x4001C000 - - - - EGU1 - 28 - - - - EGU1_S - Event generator unit 3 - 0x5001C000 - - - - EGU1 - 28 - - - - EGU2_NS - Event generator unit 4 - 0x4001D000 - - - - EGU2 - 29 - - - - EGU2_S - Event generator unit 5 - 0x5001D000 - - - - EGU2 - 29 - - - - EGU3_NS - Event generator unit 6 - 0x4001E000 - - - - EGU3 - 30 - - - - EGU3_S - Event generator unit 7 - 0x5001E000 - - - - EGU3 - 30 - - - - EGU4_NS - Event generator unit 8 - 0x4001F000 - - - - EGU4 - 31 - - - - EGU4_S - Event generator unit 9 - 0x5001F000 - - - - EGU4 - 31 - - - - EGU5_NS - Event generator unit 10 - 0x40020000 - - - - EGU5 - 32 - - - - EGU5_S - Event generator unit 11 - 0x50020000 - - - - EGU5 - 32 - - - - PWM0_NS - Pulse width modulation unit 0 - 0x40021000 - PWM - - - - 0 - 0x1000 - registers - - - PWM0 - 33 - - PWM - 0x20 - - - TASKS_STOP - Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback - 0x004 - write-only - - - TASKS_STOP - Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - 0x2 - 0x4 - TASKS_SEQSTART[%s] - Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. - 0x008 - write-only - - - TASKS_SEQSTART - Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_NEXTSTEP - Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. - 0x010 - write-only - - - TASKS_NEXTSTEP - Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - SUBSCRIBE_STOP - Subscribe configuration for task STOP - 0x084 - read-write - - - CHIDX - DPPI channel that task STOP will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - 0x2 - 0x4 - SUBSCRIBE_SEQSTART[%s] - Description collection: Subscribe configuration for task SEQSTART[n] - 0x088 - read-write - - - CHIDX - DPPI channel that task SEQSTART[n] will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_NEXTSTEP - Subscribe configuration for task NEXTSTEP - 0x090 - read-write - - - CHIDX - DPPI channel that task NEXTSTEP will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - EVENTS_STOPPED - Response to STOP task, emitted when PWM pulses are no longer generated - 0x104 - read-write - - - EVENTS_STOPPED - Response to STOP task, emitted when PWM pulses are no longer generated - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - 0x2 - 0x4 - EVENTS_SEQSTARTED[%s] - Description collection: First PWM period started on sequence n - 0x108 - read-write - - - EVENTS_SEQSTARTED - First PWM period started on sequence n - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - 0x2 - 0x4 - EVENTS_SEQEND[%s] - Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter - 0x110 - read-write - - - EVENTS_SEQEND - Emitted at end of every sequence n, when last value from RAM has been applied to wave counter - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_PWMPERIODEND - Emitted at the end of each PWM period - 0x118 - read-write - - - EVENTS_PWMPERIODEND - Emitted at the end of each PWM period - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_LOOPSDONE - Concatenated sequences have been played the amount of times defined in LOOP.CNT - 0x11C - read-write - - - EVENTS_LOOPSDONE - Concatenated sequences have been played the amount of times defined in LOOP.CNT - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - PUBLISH_STOPPED - Publish configuration for event STOPPED - 0x184 - read-write - - - CHIDX - DPPI channel that event STOPPED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - 0x2 - 0x4 - PUBLISH_SEQSTARTED[%s] - Description collection: Publish configuration for event SEQSTARTED[n] - 0x188 - read-write - - - CHIDX - DPPI channel that event SEQSTARTED[n] will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - 0x2 - 0x4 - PUBLISH_SEQEND[%s] - Description collection: Publish configuration for event SEQEND[n] - 0x190 - read-write - - - CHIDX - DPPI channel that event SEQEND[n] will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_PWMPERIODEND - Publish configuration for event PWMPERIODEND - 0x198 - read-write - - - CHIDX - DPPI channel that event PWMPERIODEND will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_LOOPSDONE - Publish configuration for event LOOPSDONE - 0x19C - read-write - - - CHIDX - DPPI channel that event LOOPSDONE will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - SHORTS - Shortcuts between local events and tasks - 0x200 - read-write - - - SEQEND0_STOP - Shortcut between event SEQEND[0] and task STOP - 0 - 0 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - SEQEND1_STOP - Shortcut between event SEQEND[1] and task STOP - 1 - 1 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - LOOPSDONE_SEQSTART0 - Shortcut between event LOOPSDONE and task SEQSTART[0] - 2 - 2 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - LOOPSDONE_SEQSTART1 - Shortcut between event LOOPSDONE and task SEQSTART[1] - 3 - 3 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - LOOPSDONE_STOP - Shortcut between event LOOPSDONE and task STOP - 4 - 4 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - - STOPPED - Enable or disable interrupt for event STOPPED - 1 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - SEQSTARTED0 - Enable or disable interrupt for event SEQSTARTED[0] - 2 - 2 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - SEQSTARTED1 - Enable or disable interrupt for event SEQSTARTED[1] - 3 - 3 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - SEQEND0 - Enable or disable interrupt for event SEQEND[0] - 4 - 4 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - SEQEND1 - Enable or disable interrupt for event SEQEND[1] - 5 - 5 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - PWMPERIODEND - Enable or disable interrupt for event PWMPERIODEND - 6 - 6 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - LOOPSDONE - Enable or disable interrupt for event LOOPSDONE - 7 - 7 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - STOPPED - Write '1' to enable interrupt for event STOPPED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - SEQSTARTED0 - Write '1' to enable interrupt for event SEQSTARTED[0] - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - SEQSTARTED1 - Write '1' to enable interrupt for event SEQSTARTED[1] - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - SEQEND0 - Write '1' to enable interrupt for event SEQEND[0] - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - SEQEND1 - Write '1' to enable interrupt for event SEQEND[1] - 5 - 5 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - PWMPERIODEND - Write '1' to enable interrupt for event PWMPERIODEND - 6 - 6 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - LOOPSDONE - Write '1' to enable interrupt for event LOOPSDONE - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - STOPPED - Write '1' to disable interrupt for event STOPPED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - SEQSTARTED0 - Write '1' to disable interrupt for event SEQSTARTED[0] - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - SEQSTARTED1 - Write '1' to disable interrupt for event SEQSTARTED[1] - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - SEQEND0 - Write '1' to disable interrupt for event SEQEND[0] - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - SEQEND1 - Write '1' to disable interrupt for event SEQEND[1] - 5 - 5 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - PWMPERIODEND - Write '1' to disable interrupt for event PWMPERIODEND - 6 - 6 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - LOOPSDONE - Write '1' to disable interrupt for event LOOPSDONE - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - ENABLE - PWM module enable register - 0x500 - read-write - 0x00000000 - - - ENABLE - Enable or disable PWM module - 0 - 0 - - - Disabled - Disabled - 0 - - - Enabled - Enable - 1 - - - - - - - MODE - Selects operating mode of the wave counter - 0x504 - read-write - 0x00000000 - - - UPDOWN - Selects up mode or up-and-down mode for the counter - 0 - 0 - - - Up - Up counter, edge-aligned PWM duty cycle - 0 - - - UpAndDown - Up and down counter, center-aligned PWM duty cycle - 1 - - - - - - - COUNTERTOP - Value up to which the pulse generator counter counts - 0x508 - read-write - 0x000003FF - - - COUNTERTOP - Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. - 0 - 14 - - - - - PRESCALER - Configuration for PWM_CLK - 0x50C - read-write - 0x00000000 - - - PRESCALER - Prescaler of PWM_CLK - 0 - 2 - - - DIV_1 - Divide by 1 (16 MHz) - 0 - - - DIV_2 - Divide by 2 (8 MHz) - 1 - - - DIV_4 - Divide by 4 (4 MHz) - 2 - - - DIV_8 - Divide by 8 (2 MHz) - 3 - - - DIV_16 - Divide by 16 (1 MHz) - 4 - - - DIV_32 - Divide by 32 (500 kHz) - 5 - - - DIV_64 - Divide by 64 (250 kHz) - 6 - - - DIV_128 - Divide by 128 (125 kHz) - 7 - - - - - - - DECODER - Configuration of the decoder - 0x510 - read-write - 0x00000000 - - - LOAD - How a sequence is read from RAM and spread to the compare register - 0 - 1 - - - Common - 1st half word (16-bit) used in all PWM channels 0..3 - 0 - - - Grouped - 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 - 1 - - - Individual - 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 - 2 - - - WaveForm - 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP - 3 - - - - - MODE - Selects source for advancing the active sequence - 8 - 8 - - - RefreshCount - SEQ[n].REFRESH is used to determine loading internal compare registers - 0 - - - NextStep - NEXTSTEP task causes a new value to be loaded to internal compare registers - 1 - - - - - - - LOOP - Number of playbacks of a loop - 0x514 - read-write - 0x00000000 - - - CNT - Number of playbacks of pattern cycles - 0 - 15 - - - Disabled - Looping disabled (stop at the end of the sequence) - 0 - - - - - - - 2 - 0x020 - SEQ[%s] - Unspecified - PWM_SEQ - read-write - 0x520 - - PTR - Description cluster: Beginning address in RAM of this sequence - 0x000 - read-write - 0x00000000 - - - PTR - Beginning address in RAM of this sequence - 0 - 31 - - - - - CNT - Description cluster: Number of values (duty cycles) in this sequence - 0x004 - read-write - 0x00000000 - - - CNT - Number of values (duty cycles) in this sequence - 0 - 14 - - - Disabled - Sequence is disabled, and shall not be started as it is empty - 0 - - - - - - - REFRESH - Description cluster: Number of additional PWM periods between samples loaded into compare register - 0x008 - read-write - 0x00000001 - - - CNT - Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) - 0 - 23 - - - Continuous - Update every PWM period - 0 - - - - - - - ENDDELAY - Description cluster: Time added after the sequence - 0x00C - read-write - 0x00000000 - - - CNT - Time added after the sequence in PWM periods - 0 - 23 - - - - - - PSEL - Unspecified - PWM_PSEL - read-write - 0x560 - - 0x4 - 0x4 - OUT[%s] - Description collection: Output pin select for PWM channel n - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - - - PWM0_S - Pulse width modulation unit 1 - 0x50021000 - - - - PWM0 - 33 - - - - PWM1_NS - Pulse width modulation unit 2 - 0x40022000 - - - - PWM1 - 34 - - - - PWM1_S - Pulse width modulation unit 3 - 0x50022000 - - - - PWM1 - 34 - - - - PWM2_NS - Pulse width modulation unit 4 - 0x40023000 - - - - PWM2 - 35 - - - - PWM2_S - Pulse width modulation unit 5 - 0x50023000 - - - - PWM2 - 35 - - - - PWM3_NS - Pulse width modulation unit 6 - 0x40024000 - - - - PWM3 - 36 - - - - PWM3_S - Pulse width modulation unit 7 - 0x50024000 - - - - PWM3 - 36 - - - - PDM0_NS - Pulse Density Modulation (Digital Microphone) Interface 0 - 0x40026000 - PDM - - - - 0 - 0x1000 - registers - - - PDM0 - 38 - - PDM - 0x20 - - - TASKS_START - Starts continuous PDM transfer - 0x000 - write-only - - - TASKS_START - Starts continuous PDM transfer - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STOP - Stops PDM transfer - 0x004 - write-only - - - TASKS_STOP - Stops PDM transfer - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - SUBSCRIBE_START - Subscribe configuration for task START - 0x080 - read-write - - - CHIDX - DPPI channel that task START will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_STOP - Subscribe configuration for task STOP - 0x084 - read-write - - - CHIDX - DPPI channel that task STOP will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - EVENTS_STARTED - PDM transfer has started - 0x100 - read-write - - - EVENTS_STARTED - PDM transfer has started - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_STOPPED - PDM transfer has finished - 0x104 - read-write - - - EVENTS_STOPPED - PDM transfer has finished - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_END - The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM - 0x108 - read-write - - - EVENTS_END - The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - PUBLISH_STARTED - Publish configuration for event STARTED - 0x180 - read-write - - - CHIDX - DPPI channel that event STARTED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_STOPPED - Publish configuration for event STOPPED - 0x184 - read-write - - - CHIDX - DPPI channel that event STOPPED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_END - Publish configuration for event END - 0x188 - read-write - - - CHIDX - DPPI channel that event END will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - - STARTED - Enable or disable interrupt for event STARTED - 0 - 0 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - STOPPED - Enable or disable interrupt for event STOPPED - 1 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - END - Enable or disable interrupt for event END - 2 - 2 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - STARTED - Write '1' to enable interrupt for event STARTED - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - STOPPED - Write '1' to enable interrupt for event STOPPED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - END - Write '1' to enable interrupt for event END - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - STARTED - Write '1' to disable interrupt for event STARTED - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - STOPPED - Write '1' to disable interrupt for event STOPPED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - END - Write '1' to disable interrupt for event END - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - ENABLE - PDM module enable register - 0x500 - read-write - 0x00000000 - - - ENABLE - Enable or disable PDM module - 0 - 0 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - PDMCLKCTRL - PDM clock generator control - 0x504 - read-write - 0x08400000 - - - FREQ - PDM_CLK frequency configuration. Enumerations are deprecated, use - PDMCLKCTRL equation to find the register value. The 12 least significant bits of the - register are ignored and shall be set to zero. - 0 - 31 - - - 1000K - PDM_CLK = 32 MHz / 32 = 1.000 MHz - 0x08000000 - - - Default - PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64. - 0x08400000 - - - 1067K - PDM_CLK = 32 MHz / 30 = 1.067 MHz - 0x08800000 - - - 1231K - PDM_CLK = 32 MHz / 26 = 1.231 MHz - 0x09800000 - - - 1280K - PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80. - 0x0A000000 - - - 1333K - PDM_CLK = 32 MHz / 24 = 1.333 MHz - 0x0A800000 - - - - - - - MODE - Defines the routing of the connected PDM microphones' signals - 0x508 - read-write - 0x00000000 - - - OPERATION - Mono or stereo operation - 0 - 0 - - - Stereo - Sample and store one pair (left + right) of 16-bit samples per RAM word R=[31:16]; L=[15:0] - 0 - - - Mono - Sample and store two successive left samples (16 bits each) per RAM word L1=[31:16]; L0=[15:0] - 1 - - - - - EDGE - Defines on which PDM_CLK edge left (or mono) is sampled - 1 - 1 - - - LeftFalling - Left (or mono) is sampled on falling edge of PDM_CLK - 0 - - - LeftRising - Left (or mono) is sampled on rising edge of PDM_CLK - 1 - - - - - - - GAINL - Left output gain adjustment - 0x518 - read-write - 0x00000028 - - - GAINL - Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust - 0 - 6 - - - MinGain - -20 dB gain adjustment (minimum) - 0x00 - - - DefaultGain - 0 dB gain adjustment - 0x28 - - - MaxGain - +20 dB gain adjustment (maximum) - 0x50 - - - - - - - GAINR - Right output gain adjustment - 0x51C - read-write - 0x00000028 - - - GAINR - Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) - 0 - 6 - - - MinGain - -20 dB gain adjustment (minimum) - 0x00 - - - DefaultGain - 0 dB gain adjustment - 0x28 - - - MaxGain - +20 dB gain adjustment (maximum) - 0x50 - - - - - - - RATIO - Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. - 0x520 - read-write - 0x00000000 - - - RATIO - Selects the ratio between PDM_CLK and output sample rate - 0 - 0 - - - Ratio64 - Ratio of 64 - 0 - - - Ratio80 - Ratio of 80 - 1 - - - - - - - PSEL - Unspecified - PDM_PSEL - read-write - 0x540 - - CLK - Pin number configuration for PDM CLK signal - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - DIN - Pin number configuration for PDM DIN signal - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - MCLKCONFIG - Master clock generator configuration - 0x54C - read-write - 0x00000000 - - - SRC - Master clock source selection - 0 - 0 - - - PCLK32M - 32 MHz peripheral clock - 0 - - - ACLK - Audio PLL clock - 1 - - - - - - - SAMPLE - Unspecified - PDM_SAMPLE - read-write - 0x560 - - PTR - RAM address pointer to write samples to with EasyDMA - 0x000 - read-write - - - SAMPLEPTR - Address to write PDM samples to over DMA - 0 - 31 - - - - - MAXCNT - Number of samples to allocate memory for in EasyDMA mode - 0x004 - read-write - - - BUFFSIZE - Length of DMA RAM allocation in number of samples - 0 - 14 - - - - - - - - PDM0_S - Pulse Density Modulation (Digital Microphone) Interface 1 - 0x50026000 - - - - PDM0 - 38 - - - - I2S0_NS - Inter-IC Sound 0 - 0x40028000 - I2S - - - - 0 - 0x1000 - registers - - - I2S0 - 40 - - I2S - 0x20 - - - TASKS_START - Starts continuous I2S transfer. Also starts MCK generator when this is enabled - 0x000 - write-only - - - TASKS_START - Starts continuous I2S transfer. Also starts MCK generator when this is enabled - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STOP - Stops I2S transfer and MCK generator. Triggering this task will cause the event STOPPED to be generated. - 0x004 - write-only - - - TASKS_STOP - Stops I2S transfer and MCK generator. Triggering this task will cause the event STOPPED to be generated. - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - SUBSCRIBE_START - Subscribe configuration for task START - 0x080 - read-write - - - CHIDX - DPPI channel that task START will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_STOP - Subscribe configuration for task STOP - 0x084 - read-write - - - CHIDX - DPPI channel that task STOP will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - EVENTS_RXPTRUPD - The RXD.PTR register has been copied to internal double-buffers. - When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words received on the SDIN pin. - 0x104 - read-write - - - EVENTS_RXPTRUPD - The RXD.PTR register has been copied to internal double-buffers. - When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words received on the SDIN pin. - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_STOPPED - I2S transfer stopped. - 0x108 - read-write - - - EVENTS_STOPPED - I2S transfer stopped. - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_TXPTRUPD - The TDX.PTR register has been copied to internal double-buffers. - When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. - 0x114 - read-write - - - EVENTS_TXPTRUPD - The TDX.PTR register has been copied to internal double-buffers. - When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_FRAMESTART - Frame start event, generated on the active edge of LRCK - 0x11C - read-write - - - EVENTS_FRAMESTART - Frame start event, generated on the active edge of LRCK - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - PUBLISH_RXPTRUPD - Publish configuration for event RXPTRUPD - 0x184 - read-write - - - CHIDX - DPPI channel that event RXPTRUPD will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_STOPPED - Publish configuration for event STOPPED - 0x188 - read-write - - - CHIDX - DPPI channel that event STOPPED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_TXPTRUPD - Publish configuration for event TXPTRUPD - 0x194 - read-write - - - CHIDX - DPPI channel that event TXPTRUPD will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_FRAMESTART - Publish configuration for event FRAMESTART - 0x19C - read-write - - - CHIDX - DPPI channel that event FRAMESTART will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - - RXPTRUPD - Enable or disable interrupt for event RXPTRUPD - 1 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - STOPPED - Enable or disable interrupt for event STOPPED - 2 - 2 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TXPTRUPD - Enable or disable interrupt for event TXPTRUPD - 5 - 5 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - FRAMESTART - Enable or disable interrupt for event FRAMESTART - 7 - 7 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - RXPTRUPD - Write '1' to enable interrupt for event RXPTRUPD - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - STOPPED - Write '1' to enable interrupt for event STOPPED - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TXPTRUPD - Write '1' to enable interrupt for event TXPTRUPD - 5 - 5 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - FRAMESTART - Write '1' to enable interrupt for event FRAMESTART - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - RXPTRUPD - Write '1' to disable interrupt for event RXPTRUPD - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - STOPPED - Write '1' to disable interrupt for event STOPPED - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TXPTRUPD - Write '1' to disable interrupt for event TXPTRUPD - 5 - 5 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - FRAMESTART - Write '1' to disable interrupt for event FRAMESTART - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - ENABLE - Enable I2S module - 0x500 - read-write - 0x00000000 - - - ENABLE - Enable I2S module - 0 - 0 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - CONFIG - Unspecified - I2S_CONFIG - read-write - 0x504 - - MODE - I2S mode - 0x000 - read-write - 0x00000000 - - - MODE - I2S mode - 0 - 0 - - - Master - Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. - 0 - - - Slave - Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx - 1 - - - - - - - RXEN - Reception (RX) enable - 0x004 - read-write - 0x00000000 - - - RXEN - Reception (RX) enable - 0 - 0 - - - Disabled - Reception disabled and now data will be written to the RXD.PTR address. - 0 - - - Enabled - Reception enabled. - 1 - - - - - - - TXEN - Transmission (TX) enable - 0x008 - read-write - 0x00000001 - - - TXEN - Transmission (TX) enable - 0 - 0 - - - Disabled - Transmission disabled and now data will be read from the RXD.TXD address. - 0 - - - Enabled - Transmission enabled. - 1 - - - - - - - MCKEN - Master clock generator enable - 0x00C - read-write - 0x00000001 - - - MCKEN - Master clock generator enable - 0 - 0 - - - Disabled - Master clock generator disabled and PSEL.MCK not connected(available as GPIO). - 0 - - - Enabled - Master clock generator running and MCK output on PSEL.MCK. - 1 - - - - - - - MCKFREQ - I2S clock generator control - 0x010 - read-write - 0x20000000 - - - MCKFREQ - I2S MCK frequency configuration NOTE: Enumerations are deprecated, use MCKFREQ equation. NOTE: The 12 least significant bits of the register are ignored and shall be set to zero. - 0 - 31 - - - 32MDIV2 - 32 MHz / 2 = 16.0 MHz Deprecated, use MCKFREQ equation. - 0x80000000 - - - 32MDIV3 - 32 MHz / 3 = 10.6666667 MHz Deprecated, use MCKFREQ equation. - 0x50000000 - - - 32MDIV4 - 32 MHz / 4 = 8.0 MHz Deprecated, use MCKFREQ equation. - 0x40000000 - - - 32MDIV5 - 32 MHz / 5 = 6.4 MHz Deprecated, use MCKFREQ equation. - 0x30000000 - - - 32MDIV6 - 32 MHz / 6 = 5.3333333 MHz Deprecated, use MCKFREQ equation. - 0x28000000 - - - 32MDIV8 - 32 MHz / 8 = 4.0 MHz Deprecated, use MCKFREQ equation. - 0x20000000 - - - 32MDIV10 - 32 MHz / 10 = 3.2 MHz Deprecated, use MCKFREQ equation. - 0x18000000 - - - 32MDIV11 - 32 MHz / 11 = 2.9090909 MHz Deprecated, use MCKFREQ equation. - 0x16000000 - - - 32MDIV15 - 32 MHz / 15 = 2.1333333 MHz Deprecated, use MCKFREQ equation. - 0x11000000 - - - 32MDIV16 - 32 MHz / 16 = 2.0 MHz Deprecated, use MCKFREQ equation. - 0x10000000 - - - 32MDIV21 - 32 MHz / 21 = 1.5238095 MHz Deprecated, use MCKFREQ equation. - 0x0C000000 - - - 32MDIV23 - 32 MHz / 23 = 1.3913043 MHz Deprecated, use MCKFREQ equation. - 0x0B000000 - - - 32MDIV30 - 32 MHz / 30 = 1.0666667 MHz Deprecated, use MCKFREQ equation. - 0x08800000 - - - 32MDIV31 - 32 MHz / 31 = 1.0322581 MHz Deprecated, use MCKFREQ equation. - 0x08400000 - - - 32MDIV32 - 32 MHz / 32 = 1.0 MHz Deprecated, use MCKFREQ equation. - 0x08000000 - - - 32MDIV42 - 32 MHz / 42 = 0.7619048 MHz Deprecated, use MCKFREQ equation. - 0x06000000 - - - 32MDIV63 - 32 MHz / 63 = 0.5079365 MHz Deprecated, use MCKFREQ equation. - 0x04100000 - - - 32MDIV125 - 32 MHz / 125 = 0.256 MHz Deprecated, use MCKFREQ equation. - 0x020C0000 - - - - - - - RATIO - MCK / LRCK ratio - 0x014 - read-write - 0x00000006 - - - RATIO - MCK / LRCK ratio - 0 - 3 - - - 32X - LRCK = MCK / 32 - 0 - - - 48X - LRCK = MCK / 48 - 1 - - - 64X - LRCK = MCK / 64 - 2 - - - 96X - LRCK = MCK / 96 - 3 - - - 128X - LRCK = MCK / 128 - 4 - - - 192X - LRCK = MCK / 192 - 5 - - - 256X - LRCK = MCK / 256 - 6 - - - 384X - LRCK = MCK / 384 - 7 - - - 512X - LRCK = MCK / 512 - 8 - - - - - - - SWIDTH - Sample width - 0x018 - read-write - 0x00000001 - - - SWIDTH - Sample and half-frame width - 0 - 2 - - - 8Bit - 8 bit sample. - 0 - - - 16Bit - 16 bit sample. - 1 - - - 24Bit - 24 bit sample. - 2 - - - 32Bit - 32 bit sample. - 3 - - - 8BitIn16 - 8 bit sample in a 16-bit half-frame. - 4 - - - 8BitIn32 - 8 bit sample in a 32-bit half-frame. - 5 - - - 16BitIn32 - 16 bit sample in a 32-bit half-frame. - 6 - - - 24BitIn32 - 24 bit sample in a 32-bit half-frame. - 7 - - - - - - - ALIGN - Alignment of sample within a frame - 0x01C - read-write - 0x00000000 - - - ALIGN - Alignment of sample within a frame - 0 - 0 - - - Left - Left-aligned. - 0 - - - Right - Right-aligned. - 1 - - - - - - - FORMAT - Frame format - 0x020 - read-write - 0x00000000 - - - FORMAT - Frame format - 0 - 0 - - - I2S - Original I2S format. - 0 - - - Aligned - Alternate (left- or right-aligned) format. - 1 - - - - - - - CHANNELS - Enable channels - 0x024 - read-write - 0x00000000 - - - CHANNELS - Enable channels - 0 - 1 - - - Stereo - Stereo. - 0 - - - Left - Left only. - 1 - - - Right - Right only. - 2 - - - - - - - CLKCONFIG - Clock source selection for the I2S module - 0x028 - read-write - 0x00000000 - - - CLKSRC - Clock source selection - 0 - 0 - - - PCLK32M - 32MHz peripheral clock - 0 - - - ACLK - Audio PLL clock - 1 - - - - - BYPASS - Bypass clock generator. MCK will be equal to source input. If bypass is enabled the MCKFREQ setting has no effect. - 8 - 8 - - - Disable - Disable bypass - 0 - - - Enable - Enable bypass - 1 - - - - - - - - RXD - Unspecified - I2S_RXD - read-write - 0x538 - - PTR - Receive buffer RAM start address. - 0x000 - read-write - 0x00000000 - - - PTR - Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. - 0 - 31 - - - - - - TXD - Unspecified - I2S_TXD - read-write - 0x540 - - PTR - Transmit buffer RAM start address - 0x000 - read-write - 0x00000000 - - - PTR - Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. - 0 - 31 - - - - - - RXTXD - Unspecified - I2S_RXTXD - read-write - 0x550 - - MAXCNT - Size of RXD and TXD buffers - 0x000 - read-write - 0x00000000 - - - MAXCNT - Size of RXD and TXD buffers in number of 32 bit words - 0 - 13 - - - - - - PSEL - Unspecified - I2S_PSEL - read-write - 0x560 - - MCK - Pin select for MCK signal - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - SCK - Pin select for SCK signal - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - LRCK - Pin select for LRCK signal - 0x008 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - SDIN - Pin select for SDIN signal - 0x00C - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - SDOUT - Pin select for SDOUT signal - 0x010 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - - - I2S0_S - Inter-IC Sound 1 - 0x50028000 - - - - I2S0 - 40 - - - - IPC_NS - Interprocessor communication 0 - 0x4002A000 - IPC - - - - 0 - 0x1000 - registers - - - IPC - 42 - - IPC - 0x20 - - - 0x10 - 0x4 - TASKS_SEND[%s] - Description collection: Trigger events on IPC channel enabled in SEND_CNF[n] - 0x000 - write-only - - - TASKS_SEND - Trigger events on IPC channel enabled in SEND_CNF[n] - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - 0x10 - 0x4 - SUBSCRIBE_SEND[%s] - Description collection: Subscribe configuration for task SEND[n] - 0x080 - read-write - - - CHIDX - DPPI channel that task SEND[n] will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - 0x10 - 0x4 - EVENTS_RECEIVE[%s] - Description collection: Event received on one or more of the enabled IPC channels in RECEIVE_CNF[n] - 0x100 - read-write - - - EVENTS_RECEIVE - Event received on one or more of the enabled IPC channels in RECEIVE_CNF[n] - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - 0x10 - 0x4 - PUBLISH_RECEIVE[%s] - Description collection: Publish configuration for event RECEIVE[n] - 0x180 - read-write - - - CHIDX - DPPI channel that event RECEIVE[n] will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - - RECEIVE0 - Enable or disable interrupt for event RECEIVE[0] - 0 - 0 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RECEIVE1 - Enable or disable interrupt for event RECEIVE[1] - 1 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RECEIVE2 - Enable or disable interrupt for event RECEIVE[2] - 2 - 2 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RECEIVE3 - Enable or disable interrupt for event RECEIVE[3] - 3 - 3 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RECEIVE4 - Enable or disable interrupt for event RECEIVE[4] - 4 - 4 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RECEIVE5 - Enable or disable interrupt for event RECEIVE[5] - 5 - 5 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RECEIVE6 - Enable or disable interrupt for event RECEIVE[6] - 6 - 6 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RECEIVE7 - Enable or disable interrupt for event RECEIVE[7] - 7 - 7 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RECEIVE8 - Enable or disable interrupt for event RECEIVE[8] - 8 - 8 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RECEIVE9 - Enable or disable interrupt for event RECEIVE[9] - 9 - 9 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RECEIVE10 - Enable or disable interrupt for event RECEIVE[10] - 10 - 10 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RECEIVE11 - Enable or disable interrupt for event RECEIVE[11] - 11 - 11 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RECEIVE12 - Enable or disable interrupt for event RECEIVE[12] - 12 - 12 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RECEIVE13 - Enable or disable interrupt for event RECEIVE[13] - 13 - 13 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RECEIVE14 - Enable or disable interrupt for event RECEIVE[14] - 14 - 14 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RECEIVE15 - Enable or disable interrupt for event RECEIVE[15] - 15 - 15 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - RECEIVE0 - Write '1' to enable interrupt for event RECEIVE[0] - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RECEIVE1 - Write '1' to enable interrupt for event RECEIVE[1] - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RECEIVE2 - Write '1' to enable interrupt for event RECEIVE[2] - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RECEIVE3 - Write '1' to enable interrupt for event RECEIVE[3] - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RECEIVE4 - Write '1' to enable interrupt for event RECEIVE[4] - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RECEIVE5 - Write '1' to enable interrupt for event RECEIVE[5] - 5 - 5 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RECEIVE6 - Write '1' to enable interrupt for event RECEIVE[6] - 6 - 6 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RECEIVE7 - Write '1' to enable interrupt for event RECEIVE[7] - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RECEIVE8 - Write '1' to enable interrupt for event RECEIVE[8] - 8 - 8 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RECEIVE9 - Write '1' to enable interrupt for event RECEIVE[9] - 9 - 9 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RECEIVE10 - Write '1' to enable interrupt for event RECEIVE[10] - 10 - 10 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RECEIVE11 - Write '1' to enable interrupt for event RECEIVE[11] - 11 - 11 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RECEIVE12 - Write '1' to enable interrupt for event RECEIVE[12] - 12 - 12 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RECEIVE13 - Write '1' to enable interrupt for event RECEIVE[13] - 13 - 13 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RECEIVE14 - Write '1' to enable interrupt for event RECEIVE[14] - 14 - 14 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RECEIVE15 - Write '1' to enable interrupt for event RECEIVE[15] - 15 - 15 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - RECEIVE0 - Write '1' to disable interrupt for event RECEIVE[0] - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RECEIVE1 - Write '1' to disable interrupt for event RECEIVE[1] - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RECEIVE2 - Write '1' to disable interrupt for event RECEIVE[2] - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RECEIVE3 - Write '1' to disable interrupt for event RECEIVE[3] - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RECEIVE4 - Write '1' to disable interrupt for event RECEIVE[4] - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RECEIVE5 - Write '1' to disable interrupt for event RECEIVE[5] - 5 - 5 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RECEIVE6 - Write '1' to disable interrupt for event RECEIVE[6] - 6 - 6 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RECEIVE7 - Write '1' to disable interrupt for event RECEIVE[7] - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RECEIVE8 - Write '1' to disable interrupt for event RECEIVE[8] - 8 - 8 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RECEIVE9 - Write '1' to disable interrupt for event RECEIVE[9] - 9 - 9 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RECEIVE10 - Write '1' to disable interrupt for event RECEIVE[10] - 10 - 10 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RECEIVE11 - Write '1' to disable interrupt for event RECEIVE[11] - 11 - 11 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RECEIVE12 - Write '1' to disable interrupt for event RECEIVE[12] - 12 - 12 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RECEIVE13 - Write '1' to disable interrupt for event RECEIVE[13] - 13 - 13 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RECEIVE14 - Write '1' to disable interrupt for event RECEIVE[14] - 14 - 14 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RECEIVE15 - Write '1' to disable interrupt for event RECEIVE[15] - 15 - 15 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - INTPEND - Pending interrupts - 0x30C - read-only - - - RECEIVE0 - Read pending status of interrupt for event RECEIVE[0] - 0 - 0 - - read - - NotPending - Read: Not pending - 0 - - - Pending - Read: Pending - 1 - - - - - RECEIVE1 - Read pending status of interrupt for event RECEIVE[1] - 1 - 1 - - read - - NotPending - Read: Not pending - 0 - - - Pending - Read: Pending - 1 - - - - - RECEIVE2 - Read pending status of interrupt for event RECEIVE[2] - 2 - 2 - - read - - NotPending - Read: Not pending - 0 - - - Pending - Read: Pending - 1 - - - - - RECEIVE3 - Read pending status of interrupt for event RECEIVE[3] - 3 - 3 - - read - - NotPending - Read: Not pending - 0 - - - Pending - Read: Pending - 1 - - - - - RECEIVE4 - Read pending status of interrupt for event RECEIVE[4] - 4 - 4 - - read - - NotPending - Read: Not pending - 0 - - - Pending - Read: Pending - 1 - - - - - RECEIVE5 - Read pending status of interrupt for event RECEIVE[5] - 5 - 5 - - read - - NotPending - Read: Not pending - 0 - - - Pending - Read: Pending - 1 - - - - - RECEIVE6 - Read pending status of interrupt for event RECEIVE[6] - 6 - 6 - - read - - NotPending - Read: Not pending - 0 - - - Pending - Read: Pending - 1 - - - - - RECEIVE7 - Read pending status of interrupt for event RECEIVE[7] - 7 - 7 - - read - - NotPending - Read: Not pending - 0 - - - Pending - Read: Pending - 1 - - - - - RECEIVE8 - Read pending status of interrupt for event RECEIVE[8] - 8 - 8 - - read - - NotPending - Read: Not pending - 0 - - - Pending - Read: Pending - 1 - - - - - RECEIVE9 - Read pending status of interrupt for event RECEIVE[9] - 9 - 9 - - read - - NotPending - Read: Not pending - 0 - - - Pending - Read: Pending - 1 - - - - - RECEIVE10 - Read pending status of interrupt for event RECEIVE[10] - 10 - 10 - - read - - NotPending - Read: Not pending - 0 - - - Pending - Read: Pending - 1 - - - - - RECEIVE11 - Read pending status of interrupt for event RECEIVE[11] - 11 - 11 - - read - - NotPending - Read: Not pending - 0 - - - Pending - Read: Pending - 1 - - - - - RECEIVE12 - Read pending status of interrupt for event RECEIVE[12] - 12 - 12 - - read - - NotPending - Read: Not pending - 0 - - - Pending - Read: Pending - 1 - - - - - RECEIVE13 - Read pending status of interrupt for event RECEIVE[13] - 13 - 13 - - read - - NotPending - Read: Not pending - 0 - - - Pending - Read: Pending - 1 - - - - - RECEIVE14 - Read pending status of interrupt for event RECEIVE[14] - 14 - 14 - - read - - NotPending - Read: Not pending - 0 - - - Pending - Read: Pending - 1 - - - - - RECEIVE15 - Read pending status of interrupt for event RECEIVE[15] - 15 - 15 - - read - - NotPending - Read: Not pending - 0 - - - Pending - Read: Pending - 1 - - - - - - - 0x10 - 0x4 - SEND_CNF[%s] - Description collection: Send event configuration for TASKS_SEND[n] - 0x510 - read-write - 0x00000000 - - - CHEN0 - Enable broadcasting on IPC channel 0 - 0 - 0 - - - Disable - Disable broadcast - 0 - - - Enable - Enable broadcast - 1 - - - - - CHEN1 - Enable broadcasting on IPC channel 1 - 1 - 1 - - - Disable - Disable broadcast - 0 - - - Enable - Enable broadcast - 1 - - - - - CHEN2 - Enable broadcasting on IPC channel 2 - 2 - 2 - - - Disable - Disable broadcast - 0 - - - Enable - Enable broadcast - 1 - - - - - CHEN3 - Enable broadcasting on IPC channel 3 - 3 - 3 - - - Disable - Disable broadcast - 0 - - - Enable - Enable broadcast - 1 - - - - - CHEN4 - Enable broadcasting on IPC channel 4 - 4 - 4 - - - Disable - Disable broadcast - 0 - - - Enable - Enable broadcast - 1 - - - - - CHEN5 - Enable broadcasting on IPC channel 5 - 5 - 5 - - - Disable - Disable broadcast - 0 - - - Enable - Enable broadcast - 1 - - - - - CHEN6 - Enable broadcasting on IPC channel 6 - 6 - 6 - - - Disable - Disable broadcast - 0 - - - Enable - Enable broadcast - 1 - - - - - CHEN7 - Enable broadcasting on IPC channel 7 - 7 - 7 - - - Disable - Disable broadcast - 0 - - - Enable - Enable broadcast - 1 - - - - - CHEN8 - Enable broadcasting on IPC channel 8 - 8 - 8 - - - Disable - Disable broadcast - 0 - - - Enable - Enable broadcast - 1 - - - - - CHEN9 - Enable broadcasting on IPC channel 9 - 9 - 9 - - - Disable - Disable broadcast - 0 - - - Enable - Enable broadcast - 1 - - - - - CHEN10 - Enable broadcasting on IPC channel 10 - 10 - 10 - - - Disable - Disable broadcast - 0 - - - Enable - Enable broadcast - 1 - - - - - CHEN11 - Enable broadcasting on IPC channel 11 - 11 - 11 - - - Disable - Disable broadcast - 0 - - - Enable - Enable broadcast - 1 - - - - - CHEN12 - Enable broadcasting on IPC channel 12 - 12 - 12 - - - Disable - Disable broadcast - 0 - - - Enable - Enable broadcast - 1 - - - - - CHEN13 - Enable broadcasting on IPC channel 13 - 13 - 13 - - - Disable - Disable broadcast - 0 - - - Enable - Enable broadcast - 1 - - - - - CHEN14 - Enable broadcasting on IPC channel 14 - 14 - 14 - - - Disable - Disable broadcast - 0 - - - Enable - Enable broadcast - 1 - - - - - CHEN15 - Enable broadcasting on IPC channel 15 - 15 - 15 - - - Disable - Disable broadcast - 0 - - - Enable - Enable broadcast - 1 - - - - - - - 0x10 - 0x4 - RECEIVE_CNF[%s] - Description collection: Receive event configuration for EVENTS_RECEIVE[n] - 0x590 - read-write - 0x00000000 - - - CHEN0 - Enable subscription to IPC channel 0 - 0 - 0 - - - Disable - Disable events - 0 - - - Enable - Enable events - 1 - - - - - CHEN1 - Enable subscription to IPC channel 1 - 1 - 1 - - - Disable - Disable events - 0 - - - Enable - Enable events - 1 - - - - - CHEN2 - Enable subscription to IPC channel 2 - 2 - 2 - - - Disable - Disable events - 0 - - - Enable - Enable events - 1 - - - - - CHEN3 - Enable subscription to IPC channel 3 - 3 - 3 - - - Disable - Disable events - 0 - - - Enable - Enable events - 1 - - - - - CHEN4 - Enable subscription to IPC channel 4 - 4 - 4 - - - Disable - Disable events - 0 - - - Enable - Enable events - 1 - - - - - CHEN5 - Enable subscription to IPC channel 5 - 5 - 5 - - - Disable - Disable events - 0 - - - Enable - Enable events - 1 - - - - - CHEN6 - Enable subscription to IPC channel 6 - 6 - 6 - - - Disable - Disable events - 0 - - - Enable - Enable events - 1 - - - - - CHEN7 - Enable subscription to IPC channel 7 - 7 - 7 - - - Disable - Disable events - 0 - - - Enable - Enable events - 1 - - - - - CHEN8 - Enable subscription to IPC channel 8 - 8 - 8 - - - Disable - Disable events - 0 - - - Enable - Enable events - 1 - - - - - CHEN9 - Enable subscription to IPC channel 9 - 9 - 9 - - - Disable - Disable events - 0 - - - Enable - Enable events - 1 - - - - - CHEN10 - Enable subscription to IPC channel 10 - 10 - 10 - - - Disable - Disable events - 0 - - - Enable - Enable events - 1 - - - - - CHEN11 - Enable subscription to IPC channel 11 - 11 - 11 - - - Disable - Disable events - 0 - - - Enable - Enable events - 1 - - - - - CHEN12 - Enable subscription to IPC channel 12 - 12 - 12 - - - Disable - Disable events - 0 - - - Enable - Enable events - 1 - - - - - CHEN13 - Enable subscription to IPC channel 13 - 13 - 13 - - - Disable - Disable events - 0 - - - Enable - Enable events - 1 - - - - - CHEN14 - Enable subscription to IPC channel 14 - 14 - 14 - - - Disable - Disable events - 0 - - - Enable - Enable events - 1 - - - - - CHEN15 - Enable subscription to IPC channel 15 - 15 - 15 - - - Disable - Disable events - 0 - - - Enable - Enable events - 1 - - - - - - - 0x2 - 0x4 - GPMEM[%s] - Description collection: General purpose memory - 0x610 - read-write - 0x00000000 - - - GPMEM - General purpose memory - 0 - 31 - - - - - - - IPC_S - Interprocessor communication 1 - 0x5002A000 - - - - IPC - 42 - - - - QSPI_NS - External flash interface 0 - 0x4002B000 - QSPI - - - - 0 - 0x1000 - registers - - - QSPI - 43 - - QSPI - 0x20 - - - TASKS_ACTIVATE - Activate QSPI interface - 0x000 - write-only - - - TASKS_ACTIVATE - Activate QSPI interface - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_READSTART - Start transfer from external flash memory to internal RAM - 0x004 - write-only - - - TASKS_READSTART - Start transfer from external flash memory to internal RAM - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_WRITESTART - Start transfer from internal RAM to external flash memory - 0x008 - write-only - - - TASKS_WRITESTART - Start transfer from internal RAM to external flash memory - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_ERASESTART - Start external flash memory erase operation - 0x00C - write-only - - - TASKS_ERASESTART - Start external flash memory erase operation - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_DEACTIVATE - Deactivate QSPI interface - 0x010 - write-only - - - TASKS_DEACTIVATE - Deactivate QSPI interface - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - SUBSCRIBE_ACTIVATE - Subscribe configuration for task ACTIVATE - 0x080 - read-write - - - CHIDX - DPPI channel that task ACTIVATE will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_READSTART - Subscribe configuration for task READSTART - 0x084 - read-write - - - CHIDX - DPPI channel that task READSTART will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_WRITESTART - Subscribe configuration for task WRITESTART - 0x088 - read-write - - - CHIDX - DPPI channel that task WRITESTART will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_ERASESTART - Subscribe configuration for task ERASESTART - 0x08C - read-write - - - CHIDX - DPPI channel that task ERASESTART will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_DEACTIVATE - Subscribe configuration for task DEACTIVATE - 0x090 - read-write - - - CHIDX - DPPI channel that task DEACTIVATE will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - EVENTS_READY - QSPI peripheral is ready. This event will be generated as a response to all QSPI tasks except DEACTIVATE. - 0x100 - read-write - - - EVENTS_READY - QSPI peripheral is ready. This event will be generated as a response to all QSPI tasks except DEACTIVATE. - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - PUBLISH_READY - Publish configuration for event READY - 0x180 - read-write - - - CHIDX - DPPI channel that event READY will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - - READY - Enable or disable interrupt for event READY - 0 - 0 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - READY - Write '1' to enable interrupt for event READY - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - READY - Write '1' to disable interrupt for event READY - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - ENABLE - Enable QSPI peripheral and acquire the pins selected in PSELn registers - 0x500 - read-write - - - ENABLE - Enable or disable QSPI - 0 - 0 - - - Disabled - Disable QSPI - 0 - - - Enabled - Enable QSPI - 1 - - - - - - - READ - Unspecified - QSPI_READ - read-write - 0x504 - - SRC - Flash memory source address - 0x000 - read-write - - - SRC - Word-aligned flash memory source address. - 0 - 31 - - - - - DST - RAM destination address - 0x004 - read-write - - - DST - Word-aligned RAM destination address. - 0 - 31 - - - - - CNT - Read transfer length - 0x008 - read-write - - - CNT - Read transfer length in number of bytes. The length must be a multiple of 4 bytes. - 0 - 20 - - - - - - WRITE - Unspecified - QSPI_WRITE - read-write - 0x510 - - DST - Flash destination address - 0x000 - read-write - - - DST - Word-aligned flash destination address. - 0 - 31 - - - - - SRC - RAM source address - 0x004 - read-write - - - SRC - Word-aligned RAM source address. - 0 - 31 - - - - - CNT - Write transfer length - 0x008 - read-write - - - CNT - Write transfer length in number of bytes. The length must be a multiple of 4 bytes. - 0 - 20 - - - - - - ERASE - Unspecified - QSPI_ERASE - read-write - 0x51C - - PTR - Start address of flash block to be erased - 0x000 - read-write - - - PTR - Word-aligned start address of block to be erased. - 0 - 31 - - - - - LEN - Size of block to be erased. - 0x004 - read-write - - - LEN - LEN - 0 - 1 - - - 4KB - Erase 4 kB block (flash command 0x20) - 0 - - - 64KB - Erase 64 kB block (flash command 0xD8) - 1 - - - All - Erase all (flash command 0xC7) - 2 - - - - - - - - PSEL - Unspecified - QSPI_PSEL - read-write - 0x524 - - SCK - Pin select for serial clock SCK - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - CSN - Pin select for chip select signal CSN. - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - IO0 - Pin select for serial data MOSI/IO0. - 0x00C - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - IO1 - Pin select for serial data MISO/IO1. - 0x010 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - IO2 - Pin select for serial data WP/IO2. - 0x014 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - IO3 - Pin select for serial data HOLD/IO3. - 0x018 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - XIPOFFSET - Address offset into the external memory for Execute in Place operation. - 0x540 - read-write - - - XIPOFFSET - Address offset into the external memory for Execute in Place operation. Value must be a multiple of 4. - 0 - 31 - - - - - IFCONFIG0 - Interface configuration. - 0x544 - read-write - - - READOC - Configure number of data lines and opcode used for reading. - 0 - 2 - - - FASTREAD - Single data line SPI. FAST_READ (opcode 0x0B). - 0 - - - READ2O - Dual data line SPI. READ2O (opcode 0x3B). - 1 - - - READ2IO - Dual data line SPI. READ2IO (opcode 0xBB). - 2 - - - READ4O - Quad data line SPI. READ4O (opcode 0x6B). - 3 - - - READ4IO - Quad data line SPI. READ4IO (opcode 0xEB). - 4 - - - - - WRITEOC - Configure number of data lines and opcode used for writing. - 3 - 5 - - - PP - Single data line SPI. PP (opcode 0x02). - 0 - - - PP2O - Dual data line SPI. PP2O (opcode 0xA2). - 1 - - - PP4O - Quad data line SPI. PP4O (opcode 0x32). - 2 - - - PP4IO - Quad data line SPI. PP4IO (opcode 0x38). - 3 - - - - - ADDRMODE - Addressing mode. - 6 - 6 - - - 24BIT - 24-bit addressing. - 0 - - - 32BIT - 32-bit addressing. - 1 - - - - - DPMENABLE - Enable deep power-down mode (DPM) feature. - 7 - 7 - - - Disable - Disable DPM feature. - 0 - - - Enable - Enable DPM feature. - 1 - - - - - PPSIZE - Page size for commands PP, PP2O, PP4O and PP4IO. - 12 - 12 - - - 256Bytes - 256 bytes. - 0 - - - 512Bytes - 512 bytes. - 1 - - - - - - - XIPEN - Enable Execute in Place operation. - 0x54C - read-write - 0x00000001 - - - XIPEN - Enable XIP AHB Slave interface and access to XIP memory range - 0 - 0 - - - Disable - Disable XIP interface - 0 - - - Enable - Enable XIP interface - 1 - - - - - - - XIP_ENC - Unspecified - QSPI_XIP_ENC - read-write - 0x560 - - KEY0 - Bits 31:0 of XIP AES KEY - 0x000 - write-only - 0x00000000 - - - KEY0 - Bits 31:0 of XIP AES KEY - 0 - 31 - - - - - KEY1 - Bits 63:32 of XIP AES KEY - 0x004 - write-only - 0x00000000 - - - KEY1 - Bits 63:32 of XIP AES KEY - 0 - 31 - - - - - KEY2 - Bits 95:64 of XIP AES KEY - 0x008 - write-only - 0x00000000 - - - KEY2 - Bits 95:64 of XIP AES KEY - 0 - 31 - - - - - KEY3 - Bits 127:96 of XIP AES KEY - 0x00C - write-only - 0x00000000 - - - KEY3 - Bits 127:96 of XIP AES KEY - 0 - 31 - - - - - NONCE0 - Bits 31:0 of XIP NONCE - 0x010 - write-only - 0x00000000 - - - NONCE0 - Bits 31:0 of XIP NONCE - 0 - 31 - - - - - NONCE1 - Bits 63:32 of XIP NONCE - 0x014 - write-only - 0x00000000 - - - NONCE1 - Bits 63:32 of XIP NONCE - 0 - 31 - - - - - NONCE2 - Bits 95:64 of XIP NONCE - 0x018 - write-only - 0x00000000 - - - NONCE2 - Bits 95:64 of XIP NONCE - 0 - 31 - - - - - ENABLE - Enable stream cipher for XIP - 0x01C - read-write - - - ENABLE - Enable or disable stream cipher for XIP - 0 - 0 - - - Disabled - Disable stream cipher for QSPI XIP - 0 - - - Enabled - Enable stream cipher for QSPI XIP - 1 - - - - - - - - DMA_ENC - Unspecified - QSPI_DMA_ENC - read-write - 0x580 - - KEY0 - Bits 31:0 of DMA AES KEY - 0x000 - write-only - 0x00000000 - - - KEY0 - Bits 31:0 of DMA AES KEY - 0 - 31 - - - - - KEY1 - Bits 63:32 of DMA AES KEY - 0x004 - write-only - 0x00000000 - - - KEY1 - Bits 63:32 of DMA AES KEY - 0 - 31 - - - - - KEY2 - Bits 95:64 of DMA AES KEY - 0x008 - write-only - 0x00000000 - - - KEY2 - Bits 95:64 of DMA AES KEY - 0 - 31 - - - - - KEY3 - Bits 127:96 of DMA AES KEY - 0x00C - write-only - 0x00000000 - - - KEY3 - Bits 127:96 of DMA AES KEY - 0 - 31 - - - - - NONCE0 - Bits 31:0 of DMA NONCE - 0x010 - write-only - 0x00000000 - - - NONCE0 - Bits 31:0 of DMA NONCE - 0 - 31 - - - - - NONCE1 - Bits 63:32 of DMA NONCE - 0x014 - write-only - 0x00000000 - - - NONCE1 - Bits 63:32 of DMA NONCE - 0 - 31 - - - - - NONCE2 - Bits 95:64 of DMA NONCE - 0x018 - write-only - 0x00000000 - - - NONCE2 - Bits 95:64 of DMA NONCE - 0 - 31 - - - - - ENABLE - Enable stream cipher for EasyDMA - 0x01C - read-write - - - ENABLE - Enable or disable stream cipher for EasyDMA - 0 - 0 - - - Disabled - Disable stream cipher for QSPI EasyDMA - 0 - - - Enabled - Enable stream cipher for QSPI EasyDMA - 1 - - - - - - - - IFCONFIG1 - Interface configuration. - 0x600 - read-write - 0x00040480 - - - SCKDELAY - Minimum amount of time that the CSN pin must stay high before it can go low again. Value is specified in number of 16 MHz periods (62.5 ns). - 0 - 7 - - - DPMEN - Enter/exit deep power-down mode (DPM) for external flash memory. - 24 - 24 - - - Exit - Exit DPM. - 0 - - - Enter - Enter DPM. - 1 - - - - - SPIMODE - Select SPI mode. - 25 - 25 - - - MODE0 - Mode 0: Data are captured on the clock rising edge and data is output on a falling edge. Base level of clock is 0 (CPOL=0, CPHA=0). - 0 - - - MODE3 - Mode 3: Data are captured on the clock rising edge and data is output on a falling edge. Base level of clock is 1 (CPOL=1, CPHA=1). - 1 - - - - - SCKFREQ - SCK frequency is derived from PCLK192M with SCK frequency = PCLK192M / (2*(SCKFREQ + 1)). - 28 - 31 - - - - - STATUS - Status register. - 0x604 - read-only - - - DPM - Deep power-down mode (DPM) status of external flash. - 2 - 2 - - - Disabled - External flash is not in DPM. - 0 - - - Enabled - External flash is in DPM. - 1 - - - - - READY - Ready status. - 3 - 3 - - - READY - QSPI peripheral is ready. It is allowed to trigger new tasks, writing custom instructions or enter/exit DPM. - 1 - - - BUSY - QSPI peripheral is busy. It is not allowed to trigger any new tasks, writing custom instructions or enter/exit DPM. - 0 - - - - - SREG - Value of external flash device Status Register. When the external flash has two bytes status register this field includes the value of the low byte. - 24 - 31 - - - - - DPMDUR - Set the duration required to enter/exit deep power-down mode (DPM). - 0x614 - read-write - 0xFFFFFFFF - - - ENTER - Duration needed by external flash to enter DPM. Duration is given as ENTER * 256 * 62.5 ns. - 0 - 15 - - - EXIT - Duration needed by external flash to exit DPM. Duration is given as EXIT * 256 * 62.5 ns. - 16 - 31 - - - - - ADDRCONF - Extended address configuration. - 0x624 - read-write - 0x000000B7 - - - OPCODE - Opcode that enters the 32-bit addressing mode. - 0 - 7 - - - BYTE0 - Byte 0 following opcode. - 8 - 15 - - - BYTE1 - Byte 1 following byte 0. - 16 - 23 - - - MODE - Extended addressing mode. - 24 - 25 - - - NoInstr - Do not send any instruction. - 0 - - - Opcode - Send opcode. - 1 - - - OpByte0 - Send opcode, BYTE0. - 2 - - - All - Send opcode, BYTE0, BYTE1. - 3 - - - - - WIPWAIT - Wait for write complete before sending command. - 26 - 26 - - - Disable - No wait. - 0 - - - Enable - Wait. - 1 - - - - - WREN - Send WREN (write enable opcode 0x06) before instruction. - 27 - 27 - - - Disable - Do not send WREN. - 0 - - - Enable - Send WREN. - 1 - - - - - - - CINSTRCONF - Custom instruction configuration register. - 0x634 - read-write - 0x00002000 - - - OPCODE - Opcode of Custom instruction. - 0 - 7 - - - LENGTH - Length of custom instruction in number of bytes. - 8 - 11 - - - 1B - Send opcode only. - 1 - - - 2B - Send opcode, CINSTRDAT0.BYTE0. - 2 - - - 3B - Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT0.BYTE1. - 3 - - - 4B - Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT0.BYTE2. - 4 - - - 5B - Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT0.BYTE3. - 5 - - - 6B - Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE4. - 6 - - - 7B - Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE5. - 7 - - - 8B - Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE6. - 8 - - - 9B - Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE7. - 9 - - - - - LIO2 - Level of the IO2 pin (if connected) during transmission of custom instruction. - 12 - 12 - - - LIO3 - Level of the IO3 pin (if connected) during transmission of custom instruction. - 13 - 13 - - - WIPWAIT - Wait for write complete before sending command. - 14 - 14 - - - Disable - No wait. - 0 - - - Enable - Wait. - 1 - - - - - WREN - Send WREN (write enable opcode 0x06) before instruction. - 15 - 15 - - - Disable - Do not send WREN. - 0 - - - Enable - Send WREN. - 1 - - - - - LFEN - Enable Long frame mode. When enabled, a custom instruction transaction has to be ended by writing the LFSTOP field. - 16 - 16 - - - Disable - Long frame mode disabled - 0 - - - Enable - Long frame mode enabled - 1 - - - - - LFSTOP - Stop (finalize) long frame transaction - 17 - 17 - - - Stop - Stop - 1 - - - - - - - CINSTRDAT0 - Custom instruction data register 0. - 0x638 - read-write - - - BYTE0 - Data byte 0 - 0 - 7 - - - BYTE1 - Data byte 1 - 8 - 15 - - - BYTE2 - Data byte 2 - 16 - 23 - - - BYTE3 - Data byte 3 - 24 - 31 - - - - - CINSTRDAT1 - Custom instruction data register 1. - 0x63C - read-write - - - BYTE4 - Data byte 4 - 0 - 7 - - - BYTE5 - Data byte 5 - 8 - 15 - - - BYTE6 - Data byte 6 - 16 - 23 - - - BYTE7 - Data byte 7 - 24 - 31 - - - - - IFTIMING - SPI interface timing. - 0x640 - read-write - 0x00000200 - - - RXDELAY - Timing related to sampling of the input serial data. The value of RXDELAY specifies the number of prescaled 192 MHz cycles delay from the the rising edge of the SPI Clock (SCK) until the input serial data is sampled. For example, if RXDELAY is set to 0, the input serial data is sampled on the rising edge of SCK. - 8 - 10 - - - - - - - QSPI_S - External flash interface 1 - 0x5002B000 - - - - QSPI - 43 - - - - NFCT_NS - NFC-A compatible radio 0 - 0x4002D000 - NFCT - - - - 0 - 0x1000 - registers - - - NFCT - 45 - - NFCT - 0x20 - - - TASKS_ACTIVATE - Activate NFCT peripheral for incoming and outgoing frames, change state to activated - 0x000 - write-only - - - TASKS_ACTIVATE - Activate NFCT peripheral for incoming and outgoing frames, change state to activated - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_DISABLE - Disable NFCT peripheral - 0x004 - write-only - - - TASKS_DISABLE - Disable NFCT peripheral - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_SENSE - Enable NFC sense field mode, change state to sense mode - 0x008 - write-only - - - TASKS_SENSE - Enable NFC sense field mode, change state to sense mode - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STARTTX - Start transmission of an outgoing frame, change state to transmit - 0x00C - write-only - - - TASKS_STARTTX - Start transmission of an outgoing frame, change state to transmit - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_ENABLERXDATA - Initializes the EasyDMA for receive. - 0x01C - write-only - - - TASKS_ENABLERXDATA - Initializes the EasyDMA for receive. - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_GOIDLE - Force state machine to IDLE state - 0x024 - write-only - - - TASKS_GOIDLE - Force state machine to IDLE state - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_GOSLEEP - Force state machine to SLEEP_A state - 0x028 - write-only - - - TASKS_GOSLEEP - Force state machine to SLEEP_A state - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - SUBSCRIBE_ACTIVATE - Subscribe configuration for task ACTIVATE - 0x080 - read-write - - - CHIDX - DPPI channel that task ACTIVATE will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_DISABLE - Subscribe configuration for task DISABLE - 0x084 - read-write - - - CHIDX - DPPI channel that task DISABLE will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_SENSE - Subscribe configuration for task SENSE - 0x088 - read-write - - - CHIDX - DPPI channel that task SENSE will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_STARTTX - Subscribe configuration for task STARTTX - 0x08C - read-write - - - CHIDX - DPPI channel that task STARTTX will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_ENABLERXDATA - Subscribe configuration for task ENABLERXDATA - 0x09C - read-write - - - CHIDX - DPPI channel that task ENABLERXDATA will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_GOIDLE - Subscribe configuration for task GOIDLE - 0x0A4 - read-write - - - CHIDX - DPPI channel that task GOIDLE will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_GOSLEEP - Subscribe configuration for task GOSLEEP - 0x0A8 - read-write - - - CHIDX - DPPI channel that task GOSLEEP will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - EVENTS_READY - The NFCT peripheral is ready to receive and send frames - 0x100 - read-write - - - EVENTS_READY - The NFCT peripheral is ready to receive and send frames - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_FIELDDETECTED - Remote NFC field detected - 0x104 - read-write - - - EVENTS_FIELDDETECTED - Remote NFC field detected - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_FIELDLOST - Remote NFC field lost - 0x108 - read-write - - - EVENTS_FIELDLOST - Remote NFC field lost - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_TXFRAMESTART - Marks the start of the first symbol of a transmitted frame - 0x10C - read-write - - - EVENTS_TXFRAMESTART - Marks the start of the first symbol of a transmitted frame - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_TXFRAMEEND - Marks the end of the last transmitted on-air symbol of a frame - 0x110 - read-write - - - EVENTS_TXFRAMEEND - Marks the end of the last transmitted on-air symbol of a frame - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_RXFRAMESTART - Marks the end of the first symbol of a received frame - 0x114 - read-write - - - EVENTS_RXFRAMESTART - Marks the end of the first symbol of a received frame - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_RXFRAMEEND - Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer - 0x118 - read-write - - - EVENTS_RXFRAMEEND - Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_ERROR - NFC error reported. The ERRORSTATUS register contains details on the source of the error. - 0x11C - read-write - - - EVENTS_ERROR - NFC error reported. The ERRORSTATUS register contains details on the source of the error. - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_RXERROR - NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. - 0x128 - read-write - - - EVENTS_RXERROR - NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_ENDRX - RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. - 0x12C - read-write - - - EVENTS_ENDRX - RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_ENDTX - Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer - 0x130 - read-write - - - EVENTS_ENDTX - Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_AUTOCOLRESSTARTED - Auto collision resolution process has started - 0x138 - read-write - - - EVENTS_AUTOCOLRESSTARTED - Auto collision resolution process has started - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_COLLISION - NFC auto collision resolution error reported. - 0x148 - read-write - - - EVENTS_COLLISION - NFC auto collision resolution error reported. - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_SELECTED - NFC auto collision resolution successfully completed - 0x14C - read-write - - - EVENTS_SELECTED - NFC auto collision resolution successfully completed - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_STARTED - EasyDMA is ready to receive or send frames. - 0x150 - read-write - - - EVENTS_STARTED - EasyDMA is ready to receive or send frames. - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - PUBLISH_READY - Publish configuration for event READY - 0x180 - read-write - - - CHIDX - DPPI channel that event READY will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_FIELDDETECTED - Publish configuration for event FIELDDETECTED - 0x184 - read-write - - - CHIDX - DPPI channel that event FIELDDETECTED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_FIELDLOST - Publish configuration for event FIELDLOST - 0x188 - read-write - - - CHIDX - DPPI channel that event FIELDLOST will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_TXFRAMESTART - Publish configuration for event TXFRAMESTART - 0x18C - read-write - - - CHIDX - DPPI channel that event TXFRAMESTART will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_TXFRAMEEND - Publish configuration for event TXFRAMEEND - 0x190 - read-write - - - CHIDX - DPPI channel that event TXFRAMEEND will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_RXFRAMESTART - Publish configuration for event RXFRAMESTART - 0x194 - read-write - - - CHIDX - DPPI channel that event RXFRAMESTART will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_RXFRAMEEND - Publish configuration for event RXFRAMEEND - 0x198 - read-write - - - CHIDX - DPPI channel that event RXFRAMEEND will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_ERROR - Publish configuration for event ERROR - 0x19C - read-write - - - CHIDX - DPPI channel that event ERROR will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_RXERROR - Publish configuration for event RXERROR - 0x1A8 - read-write - - - CHIDX - DPPI channel that event RXERROR will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_ENDRX - Publish configuration for event ENDRX - 0x1AC - read-write - - - CHIDX - DPPI channel that event ENDRX will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_ENDTX - Publish configuration for event ENDTX - 0x1B0 - read-write - - - CHIDX - DPPI channel that event ENDTX will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_AUTOCOLRESSTARTED - Publish configuration for event AUTOCOLRESSTARTED - 0x1B8 - read-write - - - CHIDX - DPPI channel that event AUTOCOLRESSTARTED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_COLLISION - Publish configuration for event COLLISION - 0x1C8 - read-write - - - CHIDX - DPPI channel that event COLLISION will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_SELECTED - Publish configuration for event SELECTED - 0x1CC - read-write - - - CHIDX - DPPI channel that event SELECTED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_STARTED - Publish configuration for event STARTED - 0x1D0 - read-write - - - CHIDX - DPPI channel that event STARTED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - SHORTS - Shortcuts between local events and tasks - 0x200 - read-write - - - FIELDDETECTED_ACTIVATE - Shortcut between event FIELDDETECTED and task ACTIVATE - 0 - 0 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - FIELDLOST_SENSE - Shortcut between event FIELDLOST and task SENSE - 1 - 1 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - TXFRAMEEND_ENABLERXDATA - Shortcut between event TXFRAMEEND and task ENABLERXDATA - 5 - 5 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - - READY - Enable or disable interrupt for event READY - 0 - 0 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - FIELDDETECTED - Enable or disable interrupt for event FIELDDETECTED - 1 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - FIELDLOST - Enable or disable interrupt for event FIELDLOST - 2 - 2 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TXFRAMESTART - Enable or disable interrupt for event TXFRAMESTART - 3 - 3 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TXFRAMEEND - Enable or disable interrupt for event TXFRAMEEND - 4 - 4 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RXFRAMESTART - Enable or disable interrupt for event RXFRAMESTART - 5 - 5 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RXFRAMEEND - Enable or disable interrupt for event RXFRAMEEND - 6 - 6 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ERROR - Enable or disable interrupt for event ERROR - 7 - 7 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RXERROR - Enable or disable interrupt for event RXERROR - 10 - 10 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ENDRX - Enable or disable interrupt for event ENDRX - 11 - 11 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ENDTX - Enable or disable interrupt for event ENDTX - 12 - 12 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - AUTOCOLRESSTARTED - Enable or disable interrupt for event AUTOCOLRESSTARTED - 14 - 14 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - COLLISION - Enable or disable interrupt for event COLLISION - 18 - 18 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - SELECTED - Enable or disable interrupt for event SELECTED - 19 - 19 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - STARTED - Enable or disable interrupt for event STARTED - 20 - 20 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - READY - Write '1' to enable interrupt for event READY - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - FIELDDETECTED - Write '1' to enable interrupt for event FIELDDETECTED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - FIELDLOST - Write '1' to enable interrupt for event FIELDLOST - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TXFRAMESTART - Write '1' to enable interrupt for event TXFRAMESTART - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TXFRAMEEND - Write '1' to enable interrupt for event TXFRAMEEND - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RXFRAMESTART - Write '1' to enable interrupt for event RXFRAMESTART - 5 - 5 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RXFRAMEEND - Write '1' to enable interrupt for event RXFRAMEEND - 6 - 6 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ERROR - Write '1' to enable interrupt for event ERROR - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RXERROR - Write '1' to enable interrupt for event RXERROR - 10 - 10 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ENDRX - Write '1' to enable interrupt for event ENDRX - 11 - 11 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ENDTX - Write '1' to enable interrupt for event ENDTX - 12 - 12 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - AUTOCOLRESSTARTED - Write '1' to enable interrupt for event AUTOCOLRESSTARTED - 14 - 14 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - COLLISION - Write '1' to enable interrupt for event COLLISION - 18 - 18 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - SELECTED - Write '1' to enable interrupt for event SELECTED - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - STARTED - Write '1' to enable interrupt for event STARTED - 20 - 20 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - READY - Write '1' to disable interrupt for event READY - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - FIELDDETECTED - Write '1' to disable interrupt for event FIELDDETECTED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - FIELDLOST - Write '1' to disable interrupt for event FIELDLOST - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TXFRAMESTART - Write '1' to disable interrupt for event TXFRAMESTART - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TXFRAMEEND - Write '1' to disable interrupt for event TXFRAMEEND - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RXFRAMESTART - Write '1' to disable interrupt for event RXFRAMESTART - 5 - 5 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RXFRAMEEND - Write '1' to disable interrupt for event RXFRAMEEND - 6 - 6 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ERROR - Write '1' to disable interrupt for event ERROR - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RXERROR - Write '1' to disable interrupt for event RXERROR - 10 - 10 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ENDRX - Write '1' to disable interrupt for event ENDRX - 11 - 11 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ENDTX - Write '1' to disable interrupt for event ENDTX - 12 - 12 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - AUTOCOLRESSTARTED - Write '1' to disable interrupt for event AUTOCOLRESSTARTED - 14 - 14 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - COLLISION - Write '1' to disable interrupt for event COLLISION - 18 - 18 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - SELECTED - Write '1' to disable interrupt for event SELECTED - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - STARTED - Write '1' to disable interrupt for event STARTED - 20 - 20 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - ERRORSTATUS - NFC Error Status register - 0x404 - read-write - oneToClear - - - FRAMEDELAYTIMEOUT - No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX - 0 - 0 - - - - - FRAMESTATUS - Unspecified - NFCT_FRAMESTATUS - read-write - 0x40C - - RX - Result of last incoming frame - 0x000 - read-write - oneToClear - - - CRCERROR - No valid end of frame (EoF) detected - 0 - 0 - - - CRCCorrect - Valid CRC detected - 0 - - - CRCError - CRC received does not match local check - 1 - - - - - PARITYSTATUS - Parity status of received frame - 2 - 2 - - - ParityOK - Frame received with parity OK - 0 - - - ParityError - Frame received with parity error - 1 - - - - - OVERRUN - Overrun detected - 3 - 3 - - - NoOverrun - No overrun detected - 0 - - - Overrun - Overrun error - 1 - - - - - - - - NFCTAGSTATE - Current operating state of NFC tag - 0x410 - read-only - - - NFCTAGSTATE - NfcTag state - 0 - 2 - - - Disabled - Disabled or sense - 0 - - - RampUp - RampUp - 2 - - - Idle - Idle - 3 - - - Receive - Receive - 4 - - - FrameDelay - FrameDelay - 5 - - - Transmit - Transmit - 6 - - - - - - - SLEEPSTATE - Sleep state during automatic collision resolution - 0x420 - read-only - 0x00000000 - - - SLEEPSTATE - Reflects the sleep state during automatic collision resolution. Set to IDLE - by a GOIDLE task. Set to SLEEP_A when a valid SLEEP_REQ frame is received or by a - GOSLEEP task. - 0 - 0 - - - Idle - State is IDLE. - 0 - - - SleepA - State is SLEEP_A. - 1 - - - - - - - FIELDPRESENT - Indicates the presence or not of a valid field - 0x43C - read-only - - - FIELDPRESENT - Indicates if a valid field is present. Available only in the activated state. - 0 - 0 - - - NoField - No valid field detected - 0 - - - FieldPresent - Valid field detected - 1 - - - - - LOCKDETECT - Indicates if the low level has locked to the field - 1 - 1 - - - NotLocked - Not locked to field - 0 - - - Locked - Locked to field - 1 - - - - - - - FRAMEDELAYMIN - Minimum frame delay - 0x504 - read-write - 0x00000480 - - - FRAMEDELAYMIN - Minimum frame delay in number of 13.56 MHz clock cycles - 0 - 15 - - - - - FRAMEDELAYMAX - Maximum frame delay - 0x508 - read-write - 0x00001000 - - - FRAMEDELAYMAX - Maximum frame delay in number of 13.56 MHz clock cycles - 0 - 19 - - - - - FRAMEDELAYMODE - Configuration register for the Frame Delay Timer - 0x50C - read-write - 0x00000001 - - - FRAMEDELAYMODE - Configuration register for the Frame Delay Timer - 0 - 1 - - - FreeRun - Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. - 0 - - - Window - Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX - 1 - - - ExactVal - Frame is transmitted exactly at FRAMEDELAYMAX - 2 - - - WindowGrid - Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX - 3 - - - - - - - PACKETPTR - Packet pointer for TXD and RXD data storage in Data RAM - 0x510 - read-write - 0x00000000 - - - PTR - Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte-aligned RAM address. - 0 - 31 - - - - - MAXLEN - Size of the RAM buffer allocated to TXD and RXD data storage each - 0x514 - read-write - - - MAXLEN - Size of the RAM buffer allocated to TXD and RXD data storage each - 0 - 8 - - - - - TXD - Unspecified - NFCT_TXD - read-write - 0x518 - - FRAMECONFIG - Configuration of outgoing frames - 0x000 - read-write - 0x00000017 - - - PARITY - Indicates if parity is added to the frame - 0 - 0 - - - NoParity - Parity is not added to TX frames - 0 - - - Parity - Parity is added to TX frames - 1 - - - - - DISCARDMODE - Discarding unused bits at start or end of a frame - 1 - 1 - - - DiscardEnd - Unused bits are discarded at end of frame (EoF) - 0 - - - DiscardStart - Unused bits are discarded at start of frame (SoF) - 1 - - - - - SOF - Adding SoF or not in TX frames - 2 - 2 - - - NoSoF - SoF symbol not added - 0 - - - SoF - SoF symbol added - 1 - - - - - CRCMODETX - CRC mode for outgoing frames - 4 - 4 - - - NoCRCTX - CRC is not added to the frame - 0 - - - CRC16TX - 16 bit CRC added to the frame based on all the data read from RAM that is used in the frame - 1 - - - - - - - AMOUNT - Size of outgoing frame - 0x004 - read-write - - - TXDATABITS - Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit). - 0 - 2 - - - TXDATABYTES - Number of complete bytes that shall be included in the frame, excluding CRC, parity, and framing. - 3 - 11 - - - - - - RXD - Unspecified - NFCT_RXD - read-write - 0x520 - - FRAMECONFIG - Configuration of incoming frames - 0x000 - read-write - 0x00000015 - - - PARITY - Indicates if parity expected in RX frame - 0 - 0 - - - NoParity - Parity is not expected in RX frames - 0 - - - Parity - Parity is expected in RX frames - 1 - - - - - SOF - SoF expected or not in RX frames - 2 - 2 - - - NoSoF - SoF symbol is not expected in RX frames - 0 - - - SoF - SoF symbol is expected in RX frames - 1 - - - - - CRCMODERX - CRC mode for incoming frames - 4 - 4 - - - NoCRCRX - CRC is not expected in RX frames - 0 - - - CRC16RX - Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated - 1 - - - - - - - AMOUNT - Size of last incoming frame - 0x004 - read-only - - - RXDATABITS - Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing). - 0 - 2 - - - RXDATABYTES - Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing) - 3 - 11 - - - - - - MODULATIONCTRL - Enables the modulation output to a GPIO pin which can be connected to a second external antenna. - 0x52C - read-write - 0x00000001 - - - MODULATIONCTRL - Configuration of modulation control. - 0 - 1 - - - Invalid - Invalid, defaults to same behaviour as for Internal - 0x0 - - - Internal - Use internal modulator only - 0x1 - - - ModToGpio - Output digital modulation signal to a GPIO pin. - 0x2 - - - InternalAndModToGpio - Use internal modulator and output digital modulation signal to a GPIO pin. - 0x3 - - - - - - - MODULATIONPSEL - Pin select for Modulation control - 0x538 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - NFCID1_LAST - Last NFCID1 part (4, 7 or 10 bytes ID) - 0x590 - read-write - 0x00006363 - - - NFCID1_Z - NFCID1 byte Z (very last byte sent) - 0 - 7 - - - NFCID1_Y - NFCID1 byte Y - 8 - 15 - - - NFCID1_X - NFCID1 byte X - 16 - 23 - - - NFCID1_W - NFCID1 byte W - 24 - 31 - - - - - NFCID1_2ND_LAST - Second last NFCID1 part (7 or 10 bytes ID) - 0x594 - read-write - - - NFCID1_V - NFCID1 byte V - 0 - 7 - - - NFCID1_U - NFCID1 byte U - 8 - 15 - - - NFCID1_T - NFCID1 byte T - 16 - 23 - - - - - NFCID1_3RD_LAST - Third last NFCID1 part (10 bytes ID) - 0x598 - read-write - - - NFCID1_S - NFCID1 byte S - 0 - 7 - - - NFCID1_R - NFCID1 byte R - 8 - 15 - - - NFCID1_Q - NFCID1 byte Q - 16 - 23 - - - - - AUTOCOLRESCONFIG - Controls the auto collision resolution function. This setting must be done before the NFCT peripheral is activated. - 0x59C - read-write - 0x00000002 - - - MODE - Enables/disables auto collision resolution - 0 - 0 - - - Enabled - Auto collision resolution enabled - 0 - - - Disabled - Auto collision resolution disabled - 1 - - - - - - - SENSRES - NFC-A SENS_RES auto-response settings - 0x5A0 - read-write - 0x00000001 - - - BITFRAMESDD - Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification - 0 - 4 - - - SDD00000 - SDD pattern 00000 - 0 - - - SDD00001 - SDD pattern 00001 - 1 - - - SDD00010 - SDD pattern 00010 - 2 - - - SDD00100 - SDD pattern 00100 - 4 - - - SDD01000 - SDD pattern 01000 - 8 - - - SDD10000 - SDD pattern 10000 - 16 - - - - - RFU5 - Reserved for future use. Shall be 0. - 5 - 5 - - - NFCIDSIZE - NFCID1 size. This value is used by the auto collision resolution engine. - 6 - 7 - - - NFCID1Single - NFCID1 size: single (4 bytes) - 0 - - - NFCID1Double - NFCID1 size: double (7 bytes) - 1 - - - NFCID1Triple - NFCID1 size: triple (10 bytes) - 2 - - - - - PLATFCONFIG - Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification - 8 - 11 - - - RFU74 - Reserved for future use. Shall be 0. - 12 - 15 - - - - - SELRES - NFC-A SEL_RES auto-response settings - 0x5A4 - read-write - - - RFU10 - Reserved for future use. Shall be 0. - 0 - 1 - - - CASCADE - Cascade as defined by the b3 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification (controlled by hardware, shall be 0) - 2 - 2 - - - RFU43 - Reserved for future use. Shall be 0. - 3 - 4 - - - PROTOCOL - Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification - 5 - 6 - - - RFU7 - Reserved for future use. Shall be 0. - 7 - 7 - - - - - - - NFCT_S - NFC-A compatible radio 1 - 0x5002D000 - - - - NFCT - 45 - - - - GPIOTE1_NS - GPIO Tasks and Events 1 - 0x4002F000 - - - - GPIOTE1 - 47 - - - - MUTEX_NS - MUTEX 0 - 0x40030000 - MUTEX - - - - 0 - 0x1000 - registers - - MUTEX - 0x20 - - - 0x10 - 0x4 - MUTEX[%s] - Description collection: Mutex register - 0x400 - read-write - - - MUTEX - Mutex register n - 0 - 0 - - - Unlocked - Mutex n is in unlocked state - 0 - - - Locked - Mutex n is in locked state - 1 - - - - - - - - - MUTEX_S - MUTEX 1 - 0x50030000 - - - - - QDEC0_NS - Quadrature Decoder 0 - 0x40033000 - QDEC - - - - 0 - 0x1000 - registers - - - QDEC0 - 51 - - QDEC - 0x20 - - - TASKS_START - Task starting the quadrature decoder - 0x000 - write-only - - - TASKS_START - Task starting the quadrature decoder - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STOP - Task stopping the quadrature decoder - 0x004 - write-only - - - TASKS_STOP - Task stopping the quadrature decoder - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_READCLRACC - Read and clear ACC and ACCDBL - 0x008 - write-only - - - TASKS_READCLRACC - Read and clear ACC and ACCDBL - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_RDCLRACC - Read and clear ACC - 0x00C - write-only - - - TASKS_RDCLRACC - Read and clear ACC - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_RDCLRDBL - Read and clear ACCDBL - 0x010 - write-only - - - TASKS_RDCLRDBL - Read and clear ACCDBL - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - SUBSCRIBE_START - Subscribe configuration for task START - 0x080 - read-write - - - CHIDX - DPPI channel that task START will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_STOP - Subscribe configuration for task STOP - 0x084 - read-write - - - CHIDX - DPPI channel that task STOP will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_READCLRACC - Subscribe configuration for task READCLRACC - 0x088 - read-write - - - CHIDX - DPPI channel that task READCLRACC will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_RDCLRACC - Subscribe configuration for task RDCLRACC - 0x08C - read-write - - - CHIDX - DPPI channel that task RDCLRACC will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_RDCLRDBL - Subscribe configuration for task RDCLRDBL - 0x090 - read-write - - - CHIDX - DPPI channel that task RDCLRDBL will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - EVENTS_SAMPLERDY - Event being generated for every new sample value written to the SAMPLE register - 0x100 - read-write - - - EVENTS_SAMPLERDY - Event being generated for every new sample value written to the SAMPLE register - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_REPORTRDY - Non-null report ready - 0x104 - read-write - - - EVENTS_REPORTRDY - Non-null report ready - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_ACCOF - ACC or ACCDBL register overflow - 0x108 - read-write - - - EVENTS_ACCOF - ACC or ACCDBL register overflow - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_DBLRDY - Double displacement(s) detected - 0x10C - read-write - - - EVENTS_DBLRDY - Double displacement(s) detected - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_STOPPED - QDEC has been stopped - 0x110 - read-write - - - EVENTS_STOPPED - QDEC has been stopped - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - PUBLISH_SAMPLERDY - Publish configuration for event SAMPLERDY - 0x180 - read-write - - - CHIDX - DPPI channel that event SAMPLERDY will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_REPORTRDY - Publish configuration for event REPORTRDY - 0x184 - read-write - - - CHIDX - DPPI channel that event REPORTRDY will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_ACCOF - Publish configuration for event ACCOF - 0x188 - read-write - - - CHIDX - DPPI channel that event ACCOF will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_DBLRDY - Publish configuration for event DBLRDY - 0x18C - read-write - - - CHIDX - DPPI channel that event DBLRDY will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_STOPPED - Publish configuration for event STOPPED - 0x190 - read-write - - - CHIDX - DPPI channel that event STOPPED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - SHORTS - Shortcuts between local events and tasks - 0x200 - read-write - - - REPORTRDY_READCLRACC - Shortcut between event REPORTRDY and task READCLRACC - 0 - 0 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - SAMPLERDY_STOP - Shortcut between event SAMPLERDY and task STOP - 1 - 1 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - REPORTRDY_RDCLRACC - Shortcut between event REPORTRDY and task RDCLRACC - 2 - 2 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - REPORTRDY_STOP - Shortcut between event REPORTRDY and task STOP - 3 - 3 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - DBLRDY_RDCLRDBL - Shortcut between event DBLRDY and task RDCLRDBL - 4 - 4 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - DBLRDY_STOP - Shortcut between event DBLRDY and task STOP - 5 - 5 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - SAMPLERDY_READCLRACC - Shortcut between event SAMPLERDY and task READCLRACC - 6 - 6 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - SAMPLERDY - Write '1' to enable interrupt for event SAMPLERDY - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - REPORTRDY - Write '1' to enable interrupt for event REPORTRDY - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ACCOF - Write '1' to enable interrupt for event ACCOF - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - DBLRDY - Write '1' to enable interrupt for event DBLRDY - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - STOPPED - Write '1' to enable interrupt for event STOPPED - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - SAMPLERDY - Write '1' to disable interrupt for event SAMPLERDY - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - REPORTRDY - Write '1' to disable interrupt for event REPORTRDY - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ACCOF - Write '1' to disable interrupt for event ACCOF - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - DBLRDY - Write '1' to disable interrupt for event DBLRDY - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - STOPPED - Write '1' to disable interrupt for event STOPPED - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - ENABLE - Enable the quadrature decoder - 0x500 - read-write - - - ENABLE - Enable or disable the quadrature decoder - 0 - 0 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - LEDPOL - LED output pin polarity - 0x504 - read-write - - - LEDPOL - LED output pin polarity - 0 - 0 - - - ActiveLow - Led active on output pin low - 0 - - - ActiveHigh - Led active on output pin high - 1 - - - - - - - SAMPLEPER - Sample period - 0x508 - read-write - - - SAMPLEPER - Sample period. The SAMPLE register will be updated for every new sample - 0 - 3 - - - 128us - 128 us - 0 - - - 256us - 256 us - 1 - - - 512us - 512 us - 2 - - - 1024us - 1024 us - 3 - - - 2048us - 2048 us - 4 - - - 4096us - 4096 us - 5 - - - 8192us - 8192 us - 6 - - - 16384us - 16384 us - 7 - - - 32ms - 32768 us - 8 - - - 65ms - 65536 us - 9 - - - 131ms - 131072 us - 10 - - - - - - - SAMPLE - Motion sample value - 0x50C - read-only - int32_t - - - SAMPLE - Last motion sample - 0 - 31 - - - - - REPORTPER - Number of samples to be taken before REPORTRDY and DBLRDY events can be generated - 0x510 - read-write - - - REPORTPER - Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated. - 0 - 3 - - - 10Smpl - 10 samples/report - 0 - - - 40Smpl - 40 samples/report - 1 - - - 80Smpl - 80 samples/report - 2 - - - 120Smpl - 120 samples/report - 3 - - - 160Smpl - 160 samples/report - 4 - - - 200Smpl - 200 samples/report - 5 - - - 240Smpl - 240 samples/report - 6 - - - 280Smpl - 280 samples/report - 7 - - - 1Smpl - 1 sample/report - 8 - - - - - - - ACC - Register accumulating the valid transitions - 0x514 - read-only - int32_t - - - ACC - Register accumulating all valid samples (not double transition) read from the SAMPLE register. - 0 - 31 - - - - - ACCREAD - Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task - 0x518 - read-only - int32_t - - - ACCREAD - Snapshot of the ACC register. - 0 - 31 - - - - - PSEL - Unspecified - QDEC_PSEL - read-write - 0x51C - - LED - Pin select for LED signal - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - A - Pin select for A signal - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - B - Pin select for B signal - 0x008 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - DBFEN - Enable input debounce filters - 0x528 - read-write - - - DBFEN - Enable input debounce filters - 0 - 0 - - - Disabled - Debounce input filters disabled - 0 - - - Enabled - Debounce input filters enabled - 1 - - - - - - - LEDPRE - Time period the LED is switched ON prior to sampling - 0x540 - read-write - 0x00000010 - - - LEDPRE - Period in us the LED is switched on prior to sampling - 0 - 8 - - - - - ACCDBL - Register accumulating the number of detected double transitions - 0x544 - read-only - - - ACCDBL - Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). - 0 - 3 - - - - - ACCDBLREAD - Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task - 0x548 - read-only - - - ACCDBLREAD - Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. - 0 - 3 - - - - - - - QDEC0_S - Quadrature Decoder 1 - 0x50033000 - - - - QDEC0 - 51 - - - - QDEC1_NS - Quadrature Decoder 2 - 0x40034000 - - - - QDEC1 - 52 - - - - QDEC1_S - Quadrature Decoder 3 - 0x50034000 - - - - QDEC1 - 52 - - - - USBD_NS - Universal serial bus device 0 - 0x40036000 - USBD - - - - 0 - 0x1000 - registers - - - USBD - 54 - - USBD - 0x20 - - - 0x8 - 0x4 - TASKS_STARTEPIN[%s] - Description collection: Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host - 0x004 - write-only - - - TASKS_STARTEPIN - Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STARTISOIN - Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint - 0x024 - write-only - - - TASKS_STARTISOIN - Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - 0x8 - 0x4 - TASKS_STARTEPOUT[%s] - Description collection: Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host - 0x028 - write-only - - - TASKS_STARTEPOUT - Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STARTISOOUT - Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint - 0x048 - write-only - - - TASKS_STARTISOOUT - Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_EP0RCVOUT - Allows OUT data stage on control endpoint 0 - 0x04C - write-only - - - TASKS_EP0RCVOUT - Allows OUT data stage on control endpoint 0 - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_EP0STATUS - Allows status stage on control endpoint 0 - 0x050 - write-only - - - TASKS_EP0STATUS - Allows status stage on control endpoint 0 - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_EP0STALL - Stalls data and status stage on control endpoint 0 - 0x054 - write-only - - - TASKS_EP0STALL - Stalls data and status stage on control endpoint 0 - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_DPDMDRIVE - Forces D+ and D- lines into the state defined in the DPDMVALUE register - 0x058 - write-only - - - TASKS_DPDMDRIVE - Forces D+ and D- lines into the state defined in the DPDMVALUE register - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_DPDMNODRIVE - Stops forcing D+ and D- lines into any state (USB engine takes control) - 0x05C - write-only - - - TASKS_DPDMNODRIVE - Stops forcing D+ and D- lines into any state (USB engine takes control) - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - 0x8 - 0x4 - SUBSCRIBE_STARTEPIN[%s] - Description collection: Subscribe configuration for task STARTEPIN[n] - 0x084 - read-write - - - CHIDX - DPPI channel that task STARTEPIN[n] will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_STARTISOIN - Subscribe configuration for task STARTISOIN - 0x0A4 - read-write - - - CHIDX - DPPI channel that task STARTISOIN will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - 0x8 - 0x4 - SUBSCRIBE_STARTEPOUT[%s] - Description collection: Subscribe configuration for task STARTEPOUT[n] - 0x0A8 - read-write - - - CHIDX - DPPI channel that task STARTEPOUT[n] will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_STARTISOOUT - Subscribe configuration for task STARTISOOUT - 0x0C8 - read-write - - - CHIDX - DPPI channel that task STARTISOOUT will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_EP0RCVOUT - Subscribe configuration for task EP0RCVOUT - 0x0CC - read-write - - - CHIDX - DPPI channel that task EP0RCVOUT will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_EP0STATUS - Subscribe configuration for task EP0STATUS - 0x0D0 - read-write - - - CHIDX - DPPI channel that task EP0STATUS will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_EP0STALL - Subscribe configuration for task EP0STALL - 0x0D4 - read-write - - - CHIDX - DPPI channel that task EP0STALL will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_DPDMDRIVE - Subscribe configuration for task DPDMDRIVE - 0x0D8 - read-write - - - CHIDX - DPPI channel that task DPDMDRIVE will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_DPDMNODRIVE - Subscribe configuration for task DPDMNODRIVE - 0x0DC - read-write - - - CHIDX - DPPI channel that task DPDMNODRIVE will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - EVENTS_USBRESET - Signals that a USB reset condition has been detected on USB lines - 0x100 - read-write - - - EVENTS_USBRESET - Signals that a USB reset condition has been detected on USB lines - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_STARTED - Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register - 0x104 - read-write - - - EVENTS_STARTED - Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - 0x8 - 0x4 - EVENTS_ENDEPIN[%s] - Description collection: The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software. - 0x108 - read-write - - - EVENTS_ENDEPIN - The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software. - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_EP0DATADONE - An acknowledged data transfer has taken place on the control endpoint - 0x128 - read-write - - - EVENTS_EP0DATADONE - An acknowledged data transfer has taken place on the control endpoint - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_ENDISOIN - The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software. - 0x12C - read-write - - - EVENTS_ENDISOIN - The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software. - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - 0x8 - 0x4 - EVENTS_ENDEPOUT[%s] - Description collection: The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software. - 0x130 - read-write - - - EVENTS_ENDEPOUT - The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software. - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_ENDISOOUT - The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software. - 0x150 - read-write - - - EVENTS_ENDISOOUT - The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software. - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_SOF - Signals that a SOF (start of frame) condition has been detected on USB lines - 0x154 - read-write - - - EVENTS_SOF - Signals that a SOF (start of frame) condition has been detected on USB lines - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_USBEVENT - An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. - 0x158 - read-write - - - EVENTS_USBEVENT - An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_EP0SETUP - A valid SETUP token has been received (and acknowledged) on the control endpoint - 0x15C - read-write - - - EVENTS_EP0SETUP - A valid SETUP token has been received (and acknowledged) on the control endpoint - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_EPDATA - A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register - 0x160 - read-write - - - EVENTS_EPDATA - A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - PUBLISH_USBRESET - Publish configuration for event USBRESET - 0x180 - read-write - - - CHIDX - DPPI channel that event USBRESET will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_STARTED - Publish configuration for event STARTED - 0x184 - read-write - - - CHIDX - DPPI channel that event STARTED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - 0x8 - 0x4 - PUBLISH_ENDEPIN[%s] - Description collection: Publish configuration for event ENDEPIN[n] - 0x188 - read-write - - - CHIDX - DPPI channel that event ENDEPIN[n] will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_EP0DATADONE - Publish configuration for event EP0DATADONE - 0x1A8 - read-write - - - CHIDX - DPPI channel that event EP0DATADONE will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_ENDISOIN - Publish configuration for event ENDISOIN - 0x1AC - read-write - - - CHIDX - DPPI channel that event ENDISOIN will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - 0x8 - 0x4 - PUBLISH_ENDEPOUT[%s] - Description collection: Publish configuration for event ENDEPOUT[n] - 0x1B0 - read-write - - - CHIDX - DPPI channel that event ENDEPOUT[n] will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_ENDISOOUT - Publish configuration for event ENDISOOUT - 0x1D0 - read-write - - - CHIDX - DPPI channel that event ENDISOOUT will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_SOF - Publish configuration for event SOF - 0x1D4 - read-write - - - CHIDX - DPPI channel that event SOF will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_USBEVENT - Publish configuration for event USBEVENT - 0x1D8 - read-write - - - CHIDX - DPPI channel that event USBEVENT will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_EP0SETUP - Publish configuration for event EP0SETUP - 0x1DC - read-write - - - CHIDX - DPPI channel that event EP0SETUP will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_EPDATA - Publish configuration for event EPDATA - 0x1E0 - read-write - - - CHIDX - DPPI channel that event EPDATA will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - SHORTS - Shortcuts between local events and tasks - 0x200 - read-write - - - EP0DATADONE_STARTEPIN0 - Shortcut between event EP0DATADONE and task STARTEPIN[0] - 0 - 0 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - EP0DATADONE_STARTEPOUT0 - Shortcut between event EP0DATADONE and task STARTEPOUT[0] - 1 - 1 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - EP0DATADONE_EP0STATUS - Shortcut between event EP0DATADONE and task EP0STATUS - 2 - 2 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - ENDEPOUT0_EP0STATUS - Shortcut between event ENDEPOUT[0] and task EP0STATUS - 3 - 3 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - ENDEPOUT0_EP0RCVOUT - Shortcut between event ENDEPOUT[0] and task EP0RCVOUT - 4 - 4 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - - USBRESET - Enable or disable interrupt for event USBRESET - 0 - 0 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - STARTED - Enable or disable interrupt for event STARTED - 1 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ENDEPIN0 - Enable or disable interrupt for event ENDEPIN[0] - 2 - 2 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ENDEPIN1 - Enable or disable interrupt for event ENDEPIN[1] - 3 - 3 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ENDEPIN2 - Enable or disable interrupt for event ENDEPIN[2] - 4 - 4 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ENDEPIN3 - Enable or disable interrupt for event ENDEPIN[3] - 5 - 5 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ENDEPIN4 - Enable or disable interrupt for event ENDEPIN[4] - 6 - 6 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ENDEPIN5 - Enable or disable interrupt for event ENDEPIN[5] - 7 - 7 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ENDEPIN6 - Enable or disable interrupt for event ENDEPIN[6] - 8 - 8 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ENDEPIN7 - Enable or disable interrupt for event ENDEPIN[7] - 9 - 9 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - EP0DATADONE - Enable or disable interrupt for event EP0DATADONE - 10 - 10 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ENDISOIN - Enable or disable interrupt for event ENDISOIN - 11 - 11 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ENDEPOUT0 - Enable or disable interrupt for event ENDEPOUT[0] - 12 - 12 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ENDEPOUT1 - Enable or disable interrupt for event ENDEPOUT[1] - 13 - 13 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ENDEPOUT2 - Enable or disable interrupt for event ENDEPOUT[2] - 14 - 14 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ENDEPOUT3 - Enable or disable interrupt for event ENDEPOUT[3] - 15 - 15 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ENDEPOUT4 - Enable or disable interrupt for event ENDEPOUT[4] - 16 - 16 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ENDEPOUT5 - Enable or disable interrupt for event ENDEPOUT[5] - 17 - 17 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ENDEPOUT6 - Enable or disable interrupt for event ENDEPOUT[6] - 18 - 18 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ENDEPOUT7 - Enable or disable interrupt for event ENDEPOUT[7] - 19 - 19 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ENDISOOUT - Enable or disable interrupt for event ENDISOOUT - 20 - 20 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - SOF - Enable or disable interrupt for event SOF - 21 - 21 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - USBEVENT - Enable or disable interrupt for event USBEVENT - 22 - 22 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - EP0SETUP - Enable or disable interrupt for event EP0SETUP - 23 - 23 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - EPDATA - Enable or disable interrupt for event EPDATA - 24 - 24 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - USBRESET - Write '1' to enable interrupt for event USBRESET - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - STARTED - Write '1' to enable interrupt for event STARTED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ENDEPIN0 - Write '1' to enable interrupt for event ENDEPIN[0] - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ENDEPIN1 - Write '1' to enable interrupt for event ENDEPIN[1] - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ENDEPIN2 - Write '1' to enable interrupt for event ENDEPIN[2] - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ENDEPIN3 - Write '1' to enable interrupt for event ENDEPIN[3] - 5 - 5 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ENDEPIN4 - Write '1' to enable interrupt for event ENDEPIN[4] - 6 - 6 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ENDEPIN5 - Write '1' to enable interrupt for event ENDEPIN[5] - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ENDEPIN6 - Write '1' to enable interrupt for event ENDEPIN[6] - 8 - 8 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ENDEPIN7 - Write '1' to enable interrupt for event ENDEPIN[7] - 9 - 9 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - EP0DATADONE - Write '1' to enable interrupt for event EP0DATADONE - 10 - 10 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ENDISOIN - Write '1' to enable interrupt for event ENDISOIN - 11 - 11 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ENDEPOUT0 - Write '1' to enable interrupt for event ENDEPOUT[0] - 12 - 12 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ENDEPOUT1 - Write '1' to enable interrupt for event ENDEPOUT[1] - 13 - 13 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ENDEPOUT2 - Write '1' to enable interrupt for event ENDEPOUT[2] - 14 - 14 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ENDEPOUT3 - Write '1' to enable interrupt for event ENDEPOUT[3] - 15 - 15 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ENDEPOUT4 - Write '1' to enable interrupt for event ENDEPOUT[4] - 16 - 16 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ENDEPOUT5 - Write '1' to enable interrupt for event ENDEPOUT[5] - 17 - 17 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ENDEPOUT6 - Write '1' to enable interrupt for event ENDEPOUT[6] - 18 - 18 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ENDEPOUT7 - Write '1' to enable interrupt for event ENDEPOUT[7] - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ENDISOOUT - Write '1' to enable interrupt for event ENDISOOUT - 20 - 20 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - SOF - Write '1' to enable interrupt for event SOF - 21 - 21 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - USBEVENT - Write '1' to enable interrupt for event USBEVENT - 22 - 22 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - EP0SETUP - Write '1' to enable interrupt for event EP0SETUP - 23 - 23 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - EPDATA - Write '1' to enable interrupt for event EPDATA - 24 - 24 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - USBRESET - Write '1' to disable interrupt for event USBRESET - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - STARTED - Write '1' to disable interrupt for event STARTED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ENDEPIN0 - Write '1' to disable interrupt for event ENDEPIN[0] - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ENDEPIN1 - Write '1' to disable interrupt for event ENDEPIN[1] - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ENDEPIN2 - Write '1' to disable interrupt for event ENDEPIN[2] - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ENDEPIN3 - Write '1' to disable interrupt for event ENDEPIN[3] - 5 - 5 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ENDEPIN4 - Write '1' to disable interrupt for event ENDEPIN[4] - 6 - 6 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ENDEPIN5 - Write '1' to disable interrupt for event ENDEPIN[5] - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ENDEPIN6 - Write '1' to disable interrupt for event ENDEPIN[6] - 8 - 8 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ENDEPIN7 - Write '1' to disable interrupt for event ENDEPIN[7] - 9 - 9 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - EP0DATADONE - Write '1' to disable interrupt for event EP0DATADONE - 10 - 10 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ENDISOIN - Write '1' to disable interrupt for event ENDISOIN - 11 - 11 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ENDEPOUT0 - Write '1' to disable interrupt for event ENDEPOUT[0] - 12 - 12 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ENDEPOUT1 - Write '1' to disable interrupt for event ENDEPOUT[1] - 13 - 13 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ENDEPOUT2 - Write '1' to disable interrupt for event ENDEPOUT[2] - 14 - 14 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ENDEPOUT3 - Write '1' to disable interrupt for event ENDEPOUT[3] - 15 - 15 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ENDEPOUT4 - Write '1' to disable interrupt for event ENDEPOUT[4] - 16 - 16 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ENDEPOUT5 - Write '1' to disable interrupt for event ENDEPOUT[5] - 17 - 17 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ENDEPOUT6 - Write '1' to disable interrupt for event ENDEPOUT[6] - 18 - 18 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ENDEPOUT7 - Write '1' to disable interrupt for event ENDEPOUT[7] - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ENDISOOUT - Write '1' to disable interrupt for event ENDISOOUT - 20 - 20 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - SOF - Write '1' to disable interrupt for event SOF - 21 - 21 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - USBEVENT - Write '1' to disable interrupt for event USBEVENT - 22 - 22 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - EP0SETUP - Write '1' to disable interrupt for event EP0SETUP - 23 - 23 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - EPDATA - Write '1' to disable interrupt for event EPDATA - 24 - 24 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - EVENTCAUSE - Details on what caused the USBEVENT event - 0x400 - read-write - oneToClear - - - ISOOUTCRC - CRC error was detected on isochronous OUT endpoint 8. Write '1' to clear. - 0 - 0 - - - NotDetected - No error detected - 0 - - - Detected - Error detected - 1 - - - - - SUSPEND - Signals that USB lines have been idle long enough for the device to enter suspend. Write '1' to clear. - 8 - 8 - - - NotDetected - Suspend not detected - 0 - - - Detected - Suspend detected - 1 - - - - - RESUME - Signals that a RESUME condition (K state or activity restart) has been detected on USB lines. Write '1' to clear. - 9 - 9 - - - NotDetected - Resume not detected - 0 - - - Detected - Resume detected - 1 - - - - - USBWUALLOWED - USB MAC has been woken up and operational. Write '1' to clear. - 10 - 10 - - - NotAllowed - Wake up not allowed - 0 - - - Allowed - Wake up allowed - 1 - - - - - READY - USB device is ready for normal operation. Write '1' to clear. - 11 - 11 - - - NotDetected - USBEVENT was not issued due to USBD peripheral ready - 0 - - - Ready - USBD peripheral is ready - 1 - - - - - - - HALTED - Unspecified - USBD_HALTED - read-write - 0x420 - - 0x8 - 0x4 - EPIN[%s] - Description collection: IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. - 0x000 - read-only - - - GETSTATUS - IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. - 0 - 15 - - - NotHalted - Endpoint is not halted - 0 - - - Halted - Endpoint is halted - 1 - - - - - - - 0x8 - 0x4 - EPOUT[%s] - Description collection: OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. - 0x024 - read-only - - - GETSTATUS - OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. - 0 - 15 - - - NotHalted - Endpoint is not halted - 0 - - - Halted - Endpoint is halted - 1 - - - - - - - - EPSTATUS - Provides information on which endpoint's EasyDMA registers have been captured - 0x468 - read-write - oneToClear - - - EPIN0 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. - 0 - 0 - - - NoData - EasyDMA registers have not been captured for this endpoint - 0 - - - DataDone - EasyDMA registers have been captured for this endpoint - 1 - - - - - EPIN1 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. - 1 - 1 - - - NoData - EasyDMA registers have not been captured for this endpoint - 0 - - - DataDone - EasyDMA registers have been captured for this endpoint - 1 - - - - - EPIN2 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. - 2 - 2 - - - NoData - EasyDMA registers have not been captured for this endpoint - 0 - - - DataDone - EasyDMA registers have been captured for this endpoint - 1 - - - - - EPIN3 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. - 3 - 3 - - - NoData - EasyDMA registers have not been captured for this endpoint - 0 - - - DataDone - EasyDMA registers have been captured for this endpoint - 1 - - - - - EPIN4 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. - 4 - 4 - - - NoData - EasyDMA registers have not been captured for this endpoint - 0 - - - DataDone - EasyDMA registers have been captured for this endpoint - 1 - - - - - EPIN5 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. - 5 - 5 - - - NoData - EasyDMA registers have not been captured for this endpoint - 0 - - - DataDone - EasyDMA registers have been captured for this endpoint - 1 - - - - - EPIN6 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. - 6 - 6 - - - NoData - EasyDMA registers have not been captured for this endpoint - 0 - - - DataDone - EasyDMA registers have been captured for this endpoint - 1 - - - - - EPIN7 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. - 7 - 7 - - - NoData - EasyDMA registers have not been captured for this endpoint - 0 - - - DataDone - EasyDMA registers have been captured for this endpoint - 1 - - - - - EPIN8 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. - 8 - 8 - - - NoData - EasyDMA registers have not been captured for this endpoint - 0 - - - DataDone - EasyDMA registers have been captured for this endpoint - 1 - - - - - EPOUT0 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. - 16 - 16 - - - NoData - EasyDMA registers have not been captured for this endpoint - 0 - - - DataDone - EasyDMA registers have been captured for this endpoint - 1 - - - - - EPOUT1 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. - 17 - 17 - - - NoData - EasyDMA registers have not been captured for this endpoint - 0 - - - DataDone - EasyDMA registers have been captured for this endpoint - 1 - - - - - EPOUT2 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. - 18 - 18 - - - NoData - EasyDMA registers have not been captured for this endpoint - 0 - - - DataDone - EasyDMA registers have been captured for this endpoint - 1 - - - - - EPOUT3 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. - 19 - 19 - - - NoData - EasyDMA registers have not been captured for this endpoint - 0 - - - DataDone - EasyDMA registers have been captured for this endpoint - 1 - - - - - EPOUT4 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. - 20 - 20 - - - NoData - EasyDMA registers have not been captured for this endpoint - 0 - - - DataDone - EasyDMA registers have been captured for this endpoint - 1 - - - - - EPOUT5 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. - 21 - 21 - - - NoData - EasyDMA registers have not been captured for this endpoint - 0 - - - DataDone - EasyDMA registers have been captured for this endpoint - 1 - - - - - EPOUT6 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. - 22 - 22 - - - NoData - EasyDMA registers have not been captured for this endpoint - 0 - - - DataDone - EasyDMA registers have been captured for this endpoint - 1 - - - - - EPOUT7 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. - 23 - 23 - - - NoData - EasyDMA registers have not been captured for this endpoint - 0 - - - DataDone - EasyDMA registers have been captured for this endpoint - 1 - - - - - EPOUT8 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. - 24 - 24 - - - NoData - EasyDMA registers have not been captured for this endpoint - 0 - - - DataDone - EasyDMA registers have been captured for this endpoint - 1 - - - - - - - EPDATASTATUS - Provides information on which endpoint(s) an acknowledged data transfer has occurred (EPDATA event) - 0x46C - read-write - oneToClear - - - EPIN1 - Acknowledged data transfer on this IN endpoint. Write '1' to clear. - 1 - 1 - - - NotDone - No acknowledged data transfer on this endpoint - 0 - - - DataDone - Acknowledged data transfer on this endpoint has occurred - 1 - - - - - EPIN2 - Acknowledged data transfer on this IN endpoint. Write '1' to clear. - 2 - 2 - - - NotDone - No acknowledged data transfer on this endpoint - 0 - - - DataDone - Acknowledged data transfer on this endpoint has occurred - 1 - - - - - EPIN3 - Acknowledged data transfer on this IN endpoint. Write '1' to clear. - 3 - 3 - - - NotDone - No acknowledged data transfer on this endpoint - 0 - - - DataDone - Acknowledged data transfer on this endpoint has occurred - 1 - - - - - EPIN4 - Acknowledged data transfer on this IN endpoint. Write '1' to clear. - 4 - 4 - - - NotDone - No acknowledged data transfer on this endpoint - 0 - - - DataDone - Acknowledged data transfer on this endpoint has occurred - 1 - - - - - EPIN5 - Acknowledged data transfer on this IN endpoint. Write '1' to clear. - 5 - 5 - - - NotDone - No acknowledged data transfer on this endpoint - 0 - - - DataDone - Acknowledged data transfer on this endpoint has occurred - 1 - - - - - EPIN6 - Acknowledged data transfer on this IN endpoint. Write '1' to clear. - 6 - 6 - - - NotDone - No acknowledged data transfer on this endpoint - 0 - - - DataDone - Acknowledged data transfer on this endpoint has occurred - 1 - - - - - EPIN7 - Acknowledged data transfer on this IN endpoint. Write '1' to clear. - 7 - 7 - - - NotDone - No acknowledged data transfer on this endpoint - 0 - - - DataDone - Acknowledged data transfer on this endpoint has occurred - 1 - - - - - EPOUT1 - Acknowledged data transfer on this OUT endpoint. Write '1' to clear. - 17 - 17 - - - NotStarted - No acknowledged data transfer on this endpoint - 0 - - - Started - Acknowledged data transfer on this endpoint has occurred - 1 - - - - - EPOUT2 - Acknowledged data transfer on this OUT endpoint. Write '1' to clear. - 18 - 18 - - - NotStarted - No acknowledged data transfer on this endpoint - 0 - - - Started - Acknowledged data transfer on this endpoint has occurred - 1 - - - - - EPOUT3 - Acknowledged data transfer on this OUT endpoint. Write '1' to clear. - 19 - 19 - - - NotStarted - No acknowledged data transfer on this endpoint - 0 - - - Started - Acknowledged data transfer on this endpoint has occurred - 1 - - - - - EPOUT4 - Acknowledged data transfer on this OUT endpoint. Write '1' to clear. - 20 - 20 - - - NotStarted - No acknowledged data transfer on this endpoint - 0 - - - Started - Acknowledged data transfer on this endpoint has occurred - 1 - - - - - EPOUT5 - Acknowledged data transfer on this OUT endpoint. Write '1' to clear. - 21 - 21 - - - NotStarted - No acknowledged data transfer on this endpoint - 0 - - - Started - Acknowledged data transfer on this endpoint has occurred - 1 - - - - - EPOUT6 - Acknowledged data transfer on this OUT endpoint. Write '1' to clear. - 22 - 22 - - - NotStarted - No acknowledged data transfer on this endpoint - 0 - - - Started - Acknowledged data transfer on this endpoint has occurred - 1 - - - - - EPOUT7 - Acknowledged data transfer on this OUT endpoint. Write '1' to clear. - 23 - 23 - - - NotStarted - No acknowledged data transfer on this endpoint - 0 - - - Started - Acknowledged data transfer on this endpoint has occurred - 1 - - - - - - - USBADDR - Device USB address - 0x470 - read-only - - - ADDR - Device USB address - 0 - 6 - - - - - BMREQUESTTYPE - SETUP data, byte 0, bmRequestType - 0x480 - read-only - 0x00000000 - - - RECIPIENT - Data transfer type - 0 - 4 - - - Device - Device - 0 - - - Interface - Interface - 1 - - - Endpoint - Endpoint - 2 - - - Other - Other - 3 - - - - - TYPE - Data transfer type - 5 - 6 - - - Standard - Standard - 0 - - - Class - Class - 1 - - - Vendor - Vendor - 2 - - - - - DIRECTION - Data transfer direction - 7 - 7 - - - HostToDevice - Host-to-device - 0 - - - DeviceToHost - Device-to-host - 1 - - - - - - - BREQUEST - SETUP data, byte 1, bRequest - 0x484 - read-only - 0x00000000 - - - BREQUEST - SETUP data, byte 1, bRequest. Values provided for standard requests only, user must implement class and vendor values. - 0 - 7 - - - STD_GET_STATUS - Standard request GET_STATUS - 0 - - - STD_CLEAR_FEATURE - Standard request CLEAR_FEATURE - 1 - - - STD_SET_FEATURE - Standard request SET_FEATURE - 3 - - - STD_SET_ADDRESS - Standard request SET_ADDRESS - 5 - - - STD_GET_DESCRIPTOR - Standard request GET_DESCRIPTOR - 6 - - - STD_SET_DESCRIPTOR - Standard request SET_DESCRIPTOR - 7 - - - STD_GET_CONFIGURATION - Standard request GET_CONFIGURATION - 8 - - - STD_SET_CONFIGURATION - Standard request SET_CONFIGURATION - 9 - - - STD_GET_INTERFACE - Standard request GET_INTERFACE - 10 - - - STD_SET_INTERFACE - Standard request SET_INTERFACE - 11 - - - STD_SYNCH_FRAME - Standard request SYNCH_FRAME - 12 - - - - - - - WVALUEL - SETUP data, byte 2, LSB of wValue - 0x488 - read-only - 0x00000000 - - - WVALUEL - SETUP data, byte 2, LSB of wValue - 0 - 7 - - - - - WVALUEH - SETUP data, byte 3, MSB of wValue - 0x48C - read-only - 0x00000000 - - - WVALUEH - SETUP data, byte 3, MSB of wValue - 0 - 7 - - - - - WINDEXL - SETUP data, byte 4, LSB of wIndex - 0x490 - read-only - 0x00000000 - - - WINDEXL - SETUP data, byte 4, LSB of wIndex - 0 - 7 - - - - - WINDEXH - SETUP data, byte 5, MSB of wIndex - 0x494 - read-only - 0x00000000 - - - WINDEXH - SETUP data, byte 5, MSB of wIndex - 0 - 7 - - - - - WLENGTHL - SETUP data, byte 6, LSB of wLength - 0x498 - read-only - 0x00000000 - - - WLENGTHL - SETUP data, byte 6, LSB of wLength - 0 - 7 - - - - - WLENGTHH - SETUP data, byte 7, MSB of wLength - 0x49C - read-only - 0x00000000 - - - WLENGTHH - SETUP data, byte 7, MSB of wLength - 0 - 7 - - - - - SIZE - Unspecified - USBD_SIZE - read-write - 0x4A0 - - 0x8 - 0x4 - EPOUT[%s] - Description collection: Number of bytes received last in the data stage of this OUT endpoint - 0x000 - read-write - zeroToClear - - - SIZE - Number of bytes received last in the data stage of this OUT endpoint - 0 - 6 - - - - - ISOOUT - Number of bytes received last on this ISO OUT data endpoint - 0x020 - read-only - 0x00010000 - - - SIZE - Number of bytes received last on this ISO OUT data endpoint - 0 - 9 - - - ZERO - Zero-length data packet received - 16 - 16 - - - Normal - No zero-length data received, use value in SIZE - 0 - - - ZeroData - Zero-length data received, ignore value in SIZE - 1 - - - - - - - - ENABLE - Enable USB - 0x500 - read-write - - - ENABLE - Enable USB - 0 - 0 - - - Disabled - USB peripheral is disabled - 0 - - - Enabled - USB peripheral is enabled - 1 - - - - - - - USBPULLUP - Control of the USB pull-up - 0x504 - read-write - - - CONNECT - Control of the USB pull-up on the D+ line - 0 - 0 - - - Disabled - Pull-up is disconnected - 0 - - - Enabled - Pull-up is connected to D+ - 1 - - - - - - - DPDMVALUE - State D+ and D- lines will be forced into by the DPDMDRIVE task. The DPDMNODRIVE task reverts the control of the lines to MAC IP (no forcing). - 0x508 - read-write - - - STATE - State D+ and D- lines will be forced into by the DPDMDRIVE task - 0 - 4 - - - Resume - D+ forced low, D- forced high (K state) for a timing preset in hardware (50 us or 5 ms, depending on bus state) - 1 - - - J - D+ forced high, D- forced low (J state) - 2 - - - K - D+ forced low, D- forced high (K state) - 4 - - - - - - - DTOGGLE - Data toggle control and status - 0x50C - read-write - 0x00000100 - - - EP - Select bulk endpoint number - 0 - 2 - - - IO - Selects IN or OUT endpoint - 7 - 7 - - - Out - Selects OUT endpoint - 0 - - - In - Selects IN endpoint - 1 - - - - - VALUE - Data toggle value - 8 - 9 - - - Nop - No action on data toggle when writing the register with this value - 0 - - - Data0 - Data toggle is DATA0 on endpoint set by EP and IO - 1 - - - Data1 - Data toggle is DATA1 on endpoint set by EP and IO - 2 - - - - - - - EPINEN - Endpoint IN enable - 0x510 - read-write - 0x00000001 - - - IN0 - Enable IN endpoint 0 - 0 - 0 - - - Disable - Disable endpoint IN 0 (no response to IN tokens) - 0 - - - Enable - Enable endpoint IN 0 (response to IN tokens) - 1 - - - - - IN1 - Enable IN endpoint 1 - 1 - 1 - - - Disable - Disable endpoint IN 1 (no response to IN tokens) - 0 - - - Enable - Enable endpoint IN 1 (response to IN tokens) - 1 - - - - - IN2 - Enable IN endpoint 2 - 2 - 2 - - - Disable - Disable endpoint IN 2 (no response to IN tokens) - 0 - - - Enable - Enable endpoint IN 2 (response to IN tokens) - 1 - - - - - IN3 - Enable IN endpoint 3 - 3 - 3 - - - Disable - Disable endpoint IN 3 (no response to IN tokens) - 0 - - - Enable - Enable endpoint IN 3 (response to IN tokens) - 1 - - - - - IN4 - Enable IN endpoint 4 - 4 - 4 - - - Disable - Disable endpoint IN 4 (no response to IN tokens) - 0 - - - Enable - Enable endpoint IN 4 (response to IN tokens) - 1 - - - - - IN5 - Enable IN endpoint 5 - 5 - 5 - - - Disable - Disable endpoint IN 5 (no response to IN tokens) - 0 - - - Enable - Enable endpoint IN 5 (response to IN tokens) - 1 - - - - - IN6 - Enable IN endpoint 6 - 6 - 6 - - - Disable - Disable endpoint IN 6 (no response to IN tokens) - 0 - - - Enable - Enable endpoint IN 6 (response to IN tokens) - 1 - - - - - IN7 - Enable IN endpoint 7 - 7 - 7 - - - Disable - Disable endpoint IN 7 (no response to IN tokens) - 0 - - - Enable - Enable endpoint IN 7 (response to IN tokens) - 1 - - - - - ISOIN - Enable ISO IN endpoint - 8 - 8 - - - Disable - Disable ISO IN endpoint 8 - 0 - - - Enable - Enable ISO IN endpoint 8 - 1 - - - - - - - EPOUTEN - Endpoint OUT enable - 0x514 - read-write - 0x00000001 - - - OUT0 - Enable OUT endpoint 0 - 0 - 0 - - - Disable - Disable endpoint OUT 0 (no response to OUT tokens) - 0 - - - Enable - Enable endpoint OUT 0 (response to OUT tokens) - 1 - - - - - OUT1 - Enable OUT endpoint 1 - 1 - 1 - - - Disable - Disable endpoint OUT 1 (no response to OUT tokens) - 0 - - - Enable - Enable endpoint OUT 1 (response to OUT tokens) - 1 - - - - - OUT2 - Enable OUT endpoint 2 - 2 - 2 - - - Disable - Disable endpoint OUT 2 (no response to OUT tokens) - 0 - - - Enable - Enable endpoint OUT 2 (response to OUT tokens) - 1 - - - - - OUT3 - Enable OUT endpoint 3 - 3 - 3 - - - Disable - Disable endpoint OUT 3 (no response to OUT tokens) - 0 - - - Enable - Enable endpoint OUT 3 (response to OUT tokens) - 1 - - - - - OUT4 - Enable OUT endpoint 4 - 4 - 4 - - - Disable - Disable endpoint OUT 4 (no response to OUT tokens) - 0 - - - Enable - Enable endpoint OUT 4 (response to OUT tokens) - 1 - - - - - OUT5 - Enable OUT endpoint 5 - 5 - 5 - - - Disable - Disable endpoint OUT 5 (no response to OUT tokens) - 0 - - - Enable - Enable endpoint OUT 5 (response to OUT tokens) - 1 - - - - - OUT6 - Enable OUT endpoint 6 - 6 - 6 - - - Disable - Disable endpoint OUT 6 (no response to OUT tokens) - 0 - - - Enable - Enable endpoint OUT 6 (response to OUT tokens) - 1 - - - - - OUT7 - Enable OUT endpoint 7 - 7 - 7 - - - Disable - Disable endpoint OUT 7 (no response to OUT tokens) - 0 - - - Enable - Enable endpoint OUT 7 (response to OUT tokens) - 1 - - - - - ISOOUT - Enable ISO OUT endpoint 8 - 8 - 8 - - - Disable - Disable ISO OUT endpoint 8 - 0 - - - Enable - Enable ISO OUT endpoint 8 - 1 - - - - - - - EPSTALL - STALL endpoints - 0x518 - write-only - 0x00000000 - modifyExternal - - - EP - Select endpoint number - 0 - 2 - - - IO - Selects IN or OUT endpoint - 7 - 7 - - - Out - Selects OUT endpoint - 0 - - - In - Selects IN endpoint - 1 - - - - - STALL - Stall selected endpoint - 8 - 8 - - - UnStall - Don't stall selected endpoint - 0 - - - Stall - Stall selected endpoint - 1 - - - - - - - ISOSPLIT - Controls the split of ISO buffers - 0x51C - read-write - - - SPLIT - Controls the split of ISO buffers - 0 - 15 - - - OneDir - Full buffer dedicated to either ISO IN or OUT - 0x0000 - - - HalfIN - Lower half for IN, upper half for OUT - 0x0080 - - - - - - - FRAMECNTR - Returns the current value of the start of frame counter - 0x520 - read-only - - - FRAMECNTR - Returns the current value of the start of frame counter - 0 - 10 - - - - - LOWPOWER - Controls USBD peripheral low power mode during USB suspend - 0x52C - read-write - 0x00000000 - - - LOWPOWER - Controls USBD peripheral low-power mode during USB suspend - 0 - 0 - - - ForceNormal - Software must write this value to exit low power mode and before performing a remote wake-up - 0 - - - LowPower - Software must write this value to enter low power mode after DMA and software have finished interacting with the USB peripheral - 1 - - - - - - - ISOINCONFIG - Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent - 0x530 - read-write - - - RESPONSE - Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent - 0 - 0 - - - NoResp - Endpoint does not respond in that case - 0 - - - ZeroData - Endpoint responds with a zero-length data packet in that case - 1 - - - - - - - 8 - 0x014 - EPIN[%s] - Unspecified - USBD_EPIN - read-write - 0x600 - - PTR - Description cluster: Data pointer - 0x000 - read-write - - - PTR - Data pointer - 0 - 31 - - - - - MAXCNT - Description cluster: Maximum number of bytes to transfer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes to transfer - 0 - 6 - - - - - AMOUNT - Description cluster: Number of bytes transferred in the last transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last transaction - 0 - 6 - - - - - - ISOIN - Unspecified - USBD_ISOIN - read-write - 0x6A0 - - PTR - Data pointer - 0x000 - read-write - - - PTR - Data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes to transfer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes to transfer - 0 - 9 - - - - - AMOUNT - Number of bytes transferred in the last transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last transaction - 0 - 9 - - - - - - 8 - 0x014 - EPOUT[%s] - Unspecified - USBD_EPOUT - read-write - 0x700 - - PTR - Description cluster: Data pointer - 0x000 - read-write - - - PTR - Data pointer - 0 - 31 - - - - - MAXCNT - Description cluster: Maximum number of bytes to transfer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes to transfer - 0 - 6 - - - - - AMOUNT - Description cluster: Number of bytes transferred in the last transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last transaction - 0 - 6 - - - - - - ISOOUT - Unspecified - USBD_ISOOUT - read-write - 0x7A0 - - PTR - Data pointer - 0x000 - read-write - - - PTR - Data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes to transfer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes to transfer - 0 - 9 - - - - - AMOUNT - Number of bytes transferred in the last transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last transaction - 0 - 9 - - - - - - - - USBD_S - Universal serial bus device 1 - 0x50036000 - - - - USBD - 54 - - - - USBREGULATOR_NS - USB Regulator 0 - 0x40037000 - USBREG - - - - 0 - 0x1000 - registers - - - USBREGULATOR - 55 - - USBREG - 0x20 - - - EVENTS_USBDETECTED - Voltage supply detected on VBUS - 0x100 - read-write - - - EVENTS_USBDETECTED - Voltage supply detected on VBUS - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_USBREMOVED - Voltage supply removed from VBUS - 0x104 - read-write - - - EVENTS_USBREMOVED - Voltage supply removed from VBUS - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_USBPWRRDY - USB 3.3 V supply ready - 0x108 - read-write - - - EVENTS_USBPWRRDY - USB 3.3 V supply ready - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - PUBLISH_USBDETECTED - Publish configuration for event USBDETECTED - 0x180 - read-write - - - CHIDX - DPPI channel that event USBDETECTED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_USBREMOVED - Publish configuration for event USBREMOVED - 0x184 - read-write - - - CHIDX - DPPI channel that event USBREMOVED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_USBPWRRDY - Publish configuration for event USBPWRRDY - 0x188 - read-write - - - CHIDX - DPPI channel that event USBPWRRDY will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - - USBDETECTED - Enable or disable interrupt for event USBDETECTED - 0 - 0 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - USBREMOVED - Enable or disable interrupt for event USBREMOVED - 1 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - USBPWRRDY - Enable or disable interrupt for event USBPWRRDY - 2 - 2 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - USBDETECTED - Write '1' to enable interrupt for event USBDETECTED - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - USBREMOVED - Write '1' to enable interrupt for event USBREMOVED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - USBPWRRDY - Write '1' to enable interrupt for event USBPWRRDY - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - USBDETECTED - Write '1' to disable interrupt for event USBDETECTED - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - USBREMOVED - Write '1' to disable interrupt for event USBREMOVED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - USBPWRRDY - Write '1' to disable interrupt for event USBPWRRDY - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - USBREGSTATUS - USB supply status - 0x400 - read-only - 0x00000000 - - - VBUSDETECT - VBUS input detection status (USBDETECTED and USBREMOVED events are derived from this information) - 0 - 0 - - - NoVbus - VBUS voltage below valid threshold - 0 - - - VbusPresent - VBUS voltage above valid threshold - 1 - - - - - OUTPUTRDY - USB supply output settling time elapsed - 1 - 1 - - - NotReady - USBREG output settling time not elapsed - 0 - - - Ready - USBREG output settling time elapsed (same information as USBPWRRDY event) - 1 - - - - - - - - - USBREGULATOR_S - USB Regulator 1 - 0x50037000 - - - - USBREGULATOR - 55 - - - - KMU_NS - Key management unit 0 - 0x40039000 - KMU - - - - 0 - 0x1000 - registers - - - KMU - 57 - - KMU - 0x20 - - - TASKS_PUSH_KEYSLOT - Push a key slot over secure APB - 0x0000 - write-only - - - TASKS_PUSH_KEYSLOT - Push a key slot over secure APB - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - EVENTS_KEYSLOT_PUSHED - Key slot successfully pushed over secure APB - 0x100 - read-write - - - EVENTS_KEYSLOT_PUSHED - Key slot successfully pushed over secure APB - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_KEYSLOT_REVOKED - Key slot has been revoked and cannot be tasked for selection - 0x104 - read-write - - - EVENTS_KEYSLOT_REVOKED - Key slot has been revoked and cannot be tasked for selection - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_KEYSLOT_ERROR - No key slot selected, no destination address defined, or error during push operation - 0x108 - read-write - - - EVENTS_KEYSLOT_ERROR - No key slot selected, no destination address defined, or error during push operation - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - - KEYSLOT_PUSHED - Enable or disable interrupt for event KEYSLOT_PUSHED - 0 - 0 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - KEYSLOT_REVOKED - Enable or disable interrupt for event KEYSLOT_REVOKED - 1 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - KEYSLOT_ERROR - Enable or disable interrupt for event KEYSLOT_ERROR - 2 - 2 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - KEYSLOT_PUSHED - Write '1' to enable interrupt for event KEYSLOT_PUSHED - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - KEYSLOT_REVOKED - Write '1' to enable interrupt for event KEYSLOT_REVOKED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - KEYSLOT_ERROR - Write '1' to enable interrupt for event KEYSLOT_ERROR - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - KEYSLOT_PUSHED - Write '1' to disable interrupt for event KEYSLOT_PUSHED - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - KEYSLOT_REVOKED - Write '1' to disable interrupt for event KEYSLOT_REVOKED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - KEYSLOT_ERROR - Write '1' to disable interrupt for event KEYSLOT_ERROR - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - INTPEND - Pending interrupts - 0x30C - read-only - - - KEYSLOT_PUSHED - Read pending status of interrupt for event KEYSLOT_PUSHED - 0 - 0 - - read - - NotPending - Read: Not pending - 0 - - - Pending - Read: Pending - 1 - - - - - KEYSLOT_REVOKED - Read pending status of interrupt for event KEYSLOT_REVOKED - 1 - 1 - - read - - NotPending - Read: Not pending - 0 - - - Pending - Read: Pending - 1 - - - - - KEYSLOT_ERROR - Read pending status of interrupt for event KEYSLOT_ERROR - 2 - 2 - - read - - NotPending - Read: Not pending - 0 - - - Pending - Read: Pending - 1 - - - - - - - STATUS - Status bits for KMU operation - 0x40C - read-only - 0x00000000 - - - SELECTED - Key slot ID successfully selected by the KMU - 0 - 0 - - - Disabled - No key slot ID selected by KMU - 0 - - - Enabled - Key slot ID successfully selected by KMU - 1 - - - - - BLOCKED - Violation status - 1 - 1 - - - Disabled - No access violation detected - 0 - - - Enabled - Access violation detected and blocked - 1 - - - - - - - SELECTKEYSLOT - Select key slot to be read over AHB or pushed over secure APB when TASKS_PUSH_KEYSLOT is started - 0x500 - read-write - 0x00000000 - - - ID - Select key slot ID to be read over AHB, or pushed over secure APB, when TASKS_PUSH_KEYSLOT is started. NOTE: ID=0 is not a valid key slot ID. The 0 ID should be used when the KMU is idle or not in use. NOTE: Index N in UICR-&gt;KEYSLOT.KEY[N] and UICR-&gt;KEYSLOT.CONFIG[N] corresponds to KMU key slot ID=N+1. - 0 - 7 - - - - - - - NVMC_NS - Non-volatile memory controller 0 - 0x40039000 - KMU_NS - NVMC - - - - 0 - 0x1000 - registers - - NVMC - 0x20 - - - READY - Ready flag - 0x400 - read-only - 0x00000001 - - - READY - NVMC is ready or busy - 0 - 0 - - - Busy - NVMC is busy (ongoing write or erase operation) - 0 - - - Ready - NVMC is ready - 1 - - - - - - - READYNEXT - Ready flag - 0x408 - read-only - 0x00000001 - - - READYNEXT - NVMC can accept a new write operation - 0 - 0 - - - Busy - NVMC cannot accept any write operation - 0 - - - Ready - NVMC is ready - 1 - - - - - - - CONFIG - Configuration register - 0x504 - read-write - - - - WEN - Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. - 0 - 2 - - - Ren - Read only access - 0 - - - Wen - Write enabled - 1 - - - Een - Erase enabled - 2 - - - PEen - Partial erase enabled - 4 - - - - - - - ERASEALL - Register for erasing all non-volatile user memory - 0x50C - write-only - - - - ERASEALL - Erase all non-volatile memory including UICR registers. Before the non-volatile memory can be erased, erasing must be enabled by setting CONFIG.WEN=Een. - 0 - 0 - - - NoOperation - No operation - 0 - - - Erase - Start chip erase - 1 - - - - - - - ERASEPAGEPARTIALCFG - Register for partial erase configuration - 0x51C - read-write - 0x0000000A - - - - DURATION - Duration of the partial erase in milliseconds - 0 - 6 - - - - - CONFIGNS - Non-secure configuration register - 0x584 - read-write - - - WEN - Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. - 0 - 1 - - - Ren - Read only access - 0 - - - Wen - Write enabled - 1 - - - Een - Erase enabled - 2 - - - - - - - WRITEUICRNS - Non-secure APPROTECT enable register - 0x588 - write-only - - - SET - Allow non-secure code to set APPROTECT - 0 - 0 - - - Set - Set value - 1 - - - - - KEY - Key to write in order to validate the write operation - 4 - 31 - - - Keyvalid - Key value - 0xAFBE5A7 - - - - - - - - - KMU_S - Key management unit 1 - 0x50039000 - - - - KMU - 57 - - - - NVMC_S - Non-volatile memory controller 1 - 0x50039000 - KMU_S - - - - - P0_NS - GPIO Port 0 - 0x40842500 - GPIO - - - - 0 - 0x300 - registers - - GPIO - 0x20 - - - OUT - Write GPIO port - 0x004 - read-write - - - PIN0 - Pin 0 - 0 - 0 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN1 - Pin 1 - 1 - 1 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN2 - Pin 2 - 2 - 2 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN3 - Pin 3 - 3 - 3 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN4 - Pin 4 - 4 - 4 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN5 - Pin 5 - 5 - 5 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN6 - Pin 6 - 6 - 6 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN7 - Pin 7 - 7 - 7 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN8 - Pin 8 - 8 - 8 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN9 - Pin 9 - 9 - 9 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN10 - Pin 10 - 10 - 10 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN11 - Pin 11 - 11 - 11 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN12 - Pin 12 - 12 - 12 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN13 - Pin 13 - 13 - 13 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN14 - Pin 14 - 14 - 14 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN15 - Pin 15 - 15 - 15 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN16 - Pin 16 - 16 - 16 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN17 - Pin 17 - 17 - 17 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN18 - Pin 18 - 18 - 18 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN19 - Pin 19 - 19 - 19 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN20 - Pin 20 - 20 - 20 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN21 - Pin 21 - 21 - 21 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN22 - Pin 22 - 22 - 22 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN23 - Pin 23 - 23 - 23 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN24 - Pin 24 - 24 - 24 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN25 - Pin 25 - 25 - 25 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN26 - Pin 26 - 26 - 26 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN27 - Pin 27 - 27 - 27 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN28 - Pin 28 - 28 - 28 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN29 - Pin 29 - 29 - 29 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN30 - Pin 30 - 30 - 30 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN31 - Pin 31 - 31 - 31 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - - - OUTSET - Set individual bits in GPIO port - 0x008 - read-write - oneToSet - - - PIN0 - Pin 0 - 0 - 0 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN1 - Pin 1 - 1 - 1 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN2 - Pin 2 - 2 - 2 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN3 - Pin 3 - 3 - 3 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN4 - Pin 4 - 4 - 4 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN5 - Pin 5 - 5 - 5 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN6 - Pin 6 - 6 - 6 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN7 - Pin 7 - 7 - 7 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN8 - Pin 8 - 8 - 8 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN9 - Pin 9 - 9 - 9 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN10 - Pin 10 - 10 - 10 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN11 - Pin 11 - 11 - 11 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN12 - Pin 12 - 12 - 12 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN13 - Pin 13 - 13 - 13 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN14 - Pin 14 - 14 - 14 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN15 - Pin 15 - 15 - 15 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN16 - Pin 16 - 16 - 16 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN17 - Pin 17 - 17 - 17 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN18 - Pin 18 - 18 - 18 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN19 - Pin 19 - 19 - 19 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN20 - Pin 20 - 20 - 20 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN21 - Pin 21 - 21 - 21 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN22 - Pin 22 - 22 - 22 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN23 - Pin 23 - 23 - 23 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN24 - Pin 24 - 24 - 24 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN25 - Pin 25 - 25 - 25 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN26 - Pin 26 - 26 - 26 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN27 - Pin 27 - 27 - 27 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN28 - Pin 28 - 28 - 28 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN29 - Pin 29 - 29 - 29 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN30 - Pin 30 - 30 - 30 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN31 - Pin 31 - 31 - 31 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - - - OUTCLR - Clear individual bits in GPIO port - 0x00C - read-write - oneToClear - - - PIN0 - Pin 0 - 0 - 0 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN1 - Pin 1 - 1 - 1 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN2 - Pin 2 - 2 - 2 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN3 - Pin 3 - 3 - 3 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN4 - Pin 4 - 4 - 4 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN5 - Pin 5 - 5 - 5 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN6 - Pin 6 - 6 - 6 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN7 - Pin 7 - 7 - 7 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN8 - Pin 8 - 8 - 8 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN9 - Pin 9 - 9 - 9 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN10 - Pin 10 - 10 - 10 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN11 - Pin 11 - 11 - 11 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN12 - Pin 12 - 12 - 12 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN13 - Pin 13 - 13 - 13 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN14 - Pin 14 - 14 - 14 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN15 - Pin 15 - 15 - 15 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN16 - Pin 16 - 16 - 16 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN17 - Pin 17 - 17 - 17 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN18 - Pin 18 - 18 - 18 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN19 - Pin 19 - 19 - 19 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN20 - Pin 20 - 20 - 20 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN21 - Pin 21 - 21 - 21 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN22 - Pin 22 - 22 - 22 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN23 - Pin 23 - 23 - 23 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN24 - Pin 24 - 24 - 24 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN25 - Pin 25 - 25 - 25 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN26 - Pin 26 - 26 - 26 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN27 - Pin 27 - 27 - 27 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN28 - Pin 28 - 28 - 28 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN29 - Pin 29 - 29 - 29 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN30 - Pin 30 - 30 - 30 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN31 - Pin 31 - 31 - 31 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - - - IN - Read GPIO port - 0x010 - read-only - - - PIN0 - Pin 0 - 0 - 0 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN1 - Pin 1 - 1 - 1 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN2 - Pin 2 - 2 - 2 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN3 - Pin 3 - 3 - 3 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN4 - Pin 4 - 4 - 4 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN5 - Pin 5 - 5 - 5 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN6 - Pin 6 - 6 - 6 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN7 - Pin 7 - 7 - 7 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN8 - Pin 8 - 8 - 8 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN9 - Pin 9 - 9 - 9 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN10 - Pin 10 - 10 - 10 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN11 - Pin 11 - 11 - 11 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN12 - Pin 12 - 12 - 12 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN13 - Pin 13 - 13 - 13 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN14 - Pin 14 - 14 - 14 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN15 - Pin 15 - 15 - 15 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN16 - Pin 16 - 16 - 16 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN17 - Pin 17 - 17 - 17 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN18 - Pin 18 - 18 - 18 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN19 - Pin 19 - 19 - 19 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN20 - Pin 20 - 20 - 20 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN21 - Pin 21 - 21 - 21 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN22 - Pin 22 - 22 - 22 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN23 - Pin 23 - 23 - 23 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN24 - Pin 24 - 24 - 24 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN25 - Pin 25 - 25 - 25 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN26 - Pin 26 - 26 - 26 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN27 - Pin 27 - 27 - 27 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN28 - Pin 28 - 28 - 28 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN29 - Pin 29 - 29 - 29 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN30 - Pin 30 - 30 - 30 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN31 - Pin 31 - 31 - 31 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - - - DIR - Direction of GPIO pins - 0x014 - read-write - - - PIN0 - Pin 0 - 0 - 0 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN1 - Pin 1 - 1 - 1 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN2 - Pin 2 - 2 - 2 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN3 - Pin 3 - 3 - 3 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN4 - Pin 4 - 4 - 4 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN5 - Pin 5 - 5 - 5 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN6 - Pin 6 - 6 - 6 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN7 - Pin 7 - 7 - 7 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN8 - Pin 8 - 8 - 8 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN9 - Pin 9 - 9 - 9 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN10 - Pin 10 - 10 - 10 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN11 - Pin 11 - 11 - 11 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN12 - Pin 12 - 12 - 12 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN13 - Pin 13 - 13 - 13 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN14 - Pin 14 - 14 - 14 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN15 - Pin 15 - 15 - 15 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN16 - Pin 16 - 16 - 16 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN17 - Pin 17 - 17 - 17 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN18 - Pin 18 - 18 - 18 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN19 - Pin 19 - 19 - 19 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN20 - Pin 20 - 20 - 20 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN21 - Pin 21 - 21 - 21 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN22 - Pin 22 - 22 - 22 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN23 - Pin 23 - 23 - 23 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN24 - Pin 24 - 24 - 24 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN25 - Pin 25 - 25 - 25 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN26 - Pin 26 - 26 - 26 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN27 - Pin 27 - 27 - 27 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN28 - Pin 28 - 28 - 28 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN29 - Pin 29 - 29 - 29 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN30 - Pin 30 - 30 - 30 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN31 - Pin 31 - 31 - 31 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - - - DIRSET - DIR set register - 0x018 - read-write - oneToSet - - - PIN0 - Set as output pin 0 - 0 - 0 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN1 - Set as output pin 1 - 1 - 1 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN2 - Set as output pin 2 - 2 - 2 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN3 - Set as output pin 3 - 3 - 3 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN4 - Set as output pin 4 - 4 - 4 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN5 - Set as output pin 5 - 5 - 5 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN6 - Set as output pin 6 - 6 - 6 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN7 - Set as output pin 7 - 7 - 7 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN8 - Set as output pin 8 - 8 - 8 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN9 - Set as output pin 9 - 9 - 9 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN10 - Set as output pin 10 - 10 - 10 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN11 - Set as output pin 11 - 11 - 11 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN12 - Set as output pin 12 - 12 - 12 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN13 - Set as output pin 13 - 13 - 13 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN14 - Set as output pin 14 - 14 - 14 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN15 - Set as output pin 15 - 15 - 15 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN16 - Set as output pin 16 - 16 - 16 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN17 - Set as output pin 17 - 17 - 17 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN18 - Set as output pin 18 - 18 - 18 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN19 - Set as output pin 19 - 19 - 19 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN20 - Set as output pin 20 - 20 - 20 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN21 - Set as output pin 21 - 21 - 21 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN22 - Set as output pin 22 - 22 - 22 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN23 - Set as output pin 23 - 23 - 23 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN24 - Set as output pin 24 - 24 - 24 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN25 - Set as output pin 25 - 25 - 25 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN26 - Set as output pin 26 - 26 - 26 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN27 - Set as output pin 27 - 27 - 27 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN28 - Set as output pin 28 - 28 - 28 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN29 - Set as output pin 29 - 29 - 29 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN30 - Set as output pin 30 - 30 - 30 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN31 - Set as output pin 31 - 31 - 31 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - - - DIRCLR - DIR clear register - 0x01C - read-write - oneToClear - - - PIN0 - Set as input pin 0 - 0 - 0 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN1 - Set as input pin 1 - 1 - 1 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN2 - Set as input pin 2 - 2 - 2 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN3 - Set as input pin 3 - 3 - 3 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN4 - Set as input pin 4 - 4 - 4 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN5 - Set as input pin 5 - 5 - 5 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN6 - Set as input pin 6 - 6 - 6 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN7 - Set as input pin 7 - 7 - 7 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN8 - Set as input pin 8 - 8 - 8 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN9 - Set as input pin 9 - 9 - 9 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN10 - Set as input pin 10 - 10 - 10 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN11 - Set as input pin 11 - 11 - 11 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN12 - Set as input pin 12 - 12 - 12 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN13 - Set as input pin 13 - 13 - 13 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN14 - Set as input pin 14 - 14 - 14 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN15 - Set as input pin 15 - 15 - 15 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN16 - Set as input pin 16 - 16 - 16 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN17 - Set as input pin 17 - 17 - 17 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN18 - Set as input pin 18 - 18 - 18 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN19 - Set as input pin 19 - 19 - 19 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN20 - Set as input pin 20 - 20 - 20 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN21 - Set as input pin 21 - 21 - 21 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN22 - Set as input pin 22 - 22 - 22 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN23 - Set as input pin 23 - 23 - 23 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN24 - Set as input pin 24 - 24 - 24 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN25 - Set as input pin 25 - 25 - 25 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN26 - Set as input pin 26 - 26 - 26 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN27 - Set as input pin 27 - 27 - 27 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN28 - Set as input pin 28 - 28 - 28 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN29 - Set as input pin 29 - 29 - 29 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN30 - Set as input pin 30 - 30 - 30 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN31 - Set as input pin 31 - 31 - 31 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - - - LATCH - Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers - 0x020 - read-write - - - PIN0 - Status on whether PIN[0] has met criteria set in PIN_CNF[0].SENSE register. Write '1' to clear. - 0 - 0 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN1 - Status on whether PIN[1] has met criteria set in PIN_CNF[1].SENSE register. Write '1' to clear. - 1 - 1 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN2 - Status on whether PIN[2] has met criteria set in PIN_CNF[2].SENSE register. Write '1' to clear. - 2 - 2 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN3 - Status on whether PIN[3] has met criteria set in PIN_CNF[3].SENSE register. Write '1' to clear. - 3 - 3 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN4 - Status on whether PIN[4] has met criteria set in PIN_CNF[4].SENSE register. Write '1' to clear. - 4 - 4 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN5 - Status on whether PIN[5] has met criteria set in PIN_CNF[5].SENSE register. Write '1' to clear. - 5 - 5 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN6 - Status on whether PIN[6] has met criteria set in PIN_CNF[6].SENSE register. Write '1' to clear. - 6 - 6 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN7 - Status on whether PIN[7] has met criteria set in PIN_CNF[7].SENSE register. Write '1' to clear. - 7 - 7 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN8 - Status on whether PIN[8] has met criteria set in PIN_CNF[8].SENSE register. Write '1' to clear. - 8 - 8 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN9 - Status on whether PIN[9] has met criteria set in PIN_CNF[9].SENSE register. Write '1' to clear. - 9 - 9 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN10 - Status on whether PIN[10] has met criteria set in PIN_CNF[10].SENSE register. Write '1' to clear. - 10 - 10 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN11 - Status on whether PIN[11] has met criteria set in PIN_CNF[11].SENSE register. Write '1' to clear. - 11 - 11 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN12 - Status on whether PIN[12] has met criteria set in PIN_CNF[12].SENSE register. Write '1' to clear. - 12 - 12 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN13 - Status on whether PIN[13] has met criteria set in PIN_CNF[13].SENSE register. Write '1' to clear. - 13 - 13 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN14 - Status on whether PIN[14] has met criteria set in PIN_CNF[14].SENSE register. Write '1' to clear. - 14 - 14 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN15 - Status on whether PIN[15] has met criteria set in PIN_CNF[15].SENSE register. Write '1' to clear. - 15 - 15 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN16 - Status on whether PIN[16] has met criteria set in PIN_CNF[16].SENSE register. Write '1' to clear. - 16 - 16 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN17 - Status on whether PIN[17] has met criteria set in PIN_CNF[17].SENSE register. Write '1' to clear. - 17 - 17 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN18 - Status on whether PIN[18] has met criteria set in PIN_CNF[18].SENSE register. Write '1' to clear. - 18 - 18 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN19 - Status on whether PIN[19] has met criteria set in PIN_CNF[19].SENSE register. Write '1' to clear. - 19 - 19 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN20 - Status on whether PIN[20] has met criteria set in PIN_CNF[20].SENSE register. Write '1' to clear. - 20 - 20 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN21 - Status on whether PIN[21] has met criteria set in PIN_CNF[21].SENSE register. Write '1' to clear. - 21 - 21 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN22 - Status on whether PIN[22] has met criteria set in PIN_CNF[22].SENSE register. Write '1' to clear. - 22 - 22 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN23 - Status on whether PIN[23] has met criteria set in PIN_CNF[23].SENSE register. Write '1' to clear. - 23 - 23 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN24 - Status on whether PIN[24] has met criteria set in PIN_CNF[24].SENSE register. Write '1' to clear. - 24 - 24 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN25 - Status on whether PIN[25] has met criteria set in PIN_CNF[25].SENSE register. Write '1' to clear. - 25 - 25 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN26 - Status on whether PIN[26] has met criteria set in PIN_CNF[26].SENSE register. Write '1' to clear. - 26 - 26 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN27 - Status on whether PIN[27] has met criteria set in PIN_CNF[27].SENSE register. Write '1' to clear. - 27 - 27 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN28 - Status on whether PIN[28] has met criteria set in PIN_CNF[28].SENSE register. Write '1' to clear. - 28 - 28 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN29 - Status on whether PIN[29] has met criteria set in PIN_CNF[29].SENSE register. Write '1' to clear. - 29 - 29 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN30 - Status on whether PIN[30] has met criteria set in PIN_CNF[30].SENSE register. Write '1' to clear. - 30 - 30 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN31 - Status on whether PIN[31] has met criteria set in PIN_CNF[31].SENSE register. Write '1' to clear. - 31 - 31 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - - - DETECTMODE - Select between default DETECT signal behavior and LDETECT mode (For non-secure pin only) - 0x024 - read-write - - - DETECTMODE - Select between default DETECT signal behavior and LDETECT mode - 0 - 0 - - - Default - DETECT directly connected to PIN DETECT signals - 0 - - - LDETECT - Use the latched LDETECT behavior - 1 - - - - - - - DETECTMODE_SEC - Select between default DETECT signal behavior and LDETECT mode (For secure pin only) - 0x028 - read-write - - - DETECTMODE - Select between default DETECT signal behavior and LDETECT mode - 0 - 0 - - - Default - DETECT directly connected to PIN DETECT signals - 0 - - - LDETECT - Use the latched LDETECT behavior - 1 - - - - - - - 0x20 - 0x4 - PIN_CNF[%s] - Description collection: Configuration of GPIO pins - 0x200 - read-write - 0x00000002 - - - DIR - Pin direction. Same physical register as DIR register - 0 - 0 - - - Input - Configure pin as an input pin - 0 - - - Output - Configure pin as an output pin - 1 - - - - - INPUT - Connect or disconnect input buffer - 1 - 1 - - - Connect - Connect input buffer - 0 - - - Disconnect - Disconnect input buffer - 1 - - - - - PULL - Pull configuration - 2 - 3 - - - Disabled - No pull - 0 - - - Pulldown - Pull down on pin - 1 - - - Pullup - Pull up on pin - 3 - - - - - DRIVE - Drive configuration - 8 - 11 - - - S0S1 - Standard '0', standard '1' - 0 - - - H0S1 - High drive '0', standard '1' - 1 - - - S0H1 - Standard '0', high drive '1' - 2 - - - H0H1 - High drive '0', high 'drive '1'' - 3 - - - D0S1 - Disconnect '0', standard '1' (normally used for wired-or connections) - 4 - - - D0H1 - Disconnect '0', high drive '1' (normally used for wired-or connections) - 5 - - - S0D1 - Standard '0', disconnect '1' (normally used for wired-and connections) - 6 - - - H0D1 - High drive '0', disconnect '1' (normally used for wired-and connections) - 7 - - - E0E1 - Extra high drive '0', extra high drive '1' - 11 - - - - - SENSE - Pin sensing mechanism - 16 - 17 - - - Disabled - Disabled - 0 - - - High - Sense for high level - 2 - - - Low - Sense for low level - 3 - - - - - MCUSEL - Select which MCU/Subsystem controls this pin Note: this field is only accessible from secure code. - 28 - 30 - - - AppMCU - Application MCU - 0x0 - - - NetworkMCU - Network MCU - 0x1 - - - Peripheral - Peripheral with dedicated pins - 0x3 - - - TND - Trace and Debug Subsystem - 0x7 - - - - - - - - - P1_NS - GPIO Port 1 - 0x40842800 - - - - - P0_S - GPIO Port 2 - 0x50842500 - - - - - P1_S - GPIO Port 3 - 0x50842800 - - - - - CRYPTOCELL_S - ARM TrustZone CryptoCell register interface - 0x50844000 - CRYPTOCELL - - - - 0 - 0x1000 - registers - - - CRYPTOCELL - 68 - - CRYPTOCELL - 0x20 - - - ENABLE - Enable CRYPTOCELL subsystem. - 0x500 - read-write - 0x00000000 - - - ENABLE - Enable or disable the CRYPTOCELL subsystem. - 0 - 0 - - - Disabled - CRYPTOCELL subsystem disabled. - 0 - - - Enabled - CRYPTOCELL subsystem enabled. - 1 - - - - - - - - - VMC_NS - Volatile Memory controller 0 - 0x40081000 - VMC - - - - 0 - 0x1000 - registers - - VMC - 0x20 - - - 8 - 0x010 - RAM[%s] - Unspecified - VMC_RAM - read-write - 0x600 - - POWER - Description cluster: RAM[n] power control register - 0x000 - read-write - 0x0000FFFF - - - S0POWER - Keep RAM section S0 of RAM[n] on or off in System ON mode - 0 - 0 - - - Off - Off - 0 - - - On - On - 1 - - - - - S1POWER - Keep RAM section S1 of RAM[n] on or off in System ON mode - 1 - 1 - - - Off - Off - 0 - - - On - On - 1 - - - - - S2POWER - Keep RAM section S2 of RAM[n] on or off in System ON mode - 2 - 2 - - - Off - Off - 0 - - - On - On - 1 - - - - - S3POWER - Keep RAM section S3 of RAM[n] on or off in System ON mode - 3 - 3 - - - Off - Off - 0 - - - On - On - 1 - - - - - S4POWER - Keep RAM section S4 of RAM[n] on or off in System ON mode - 4 - 4 - - - Off - Off - 0 - - - On - On - 1 - - - - - S5POWER - Keep RAM section S5 of RAM[n] on or off in System ON mode - 5 - 5 - - - Off - Off - 0 - - - On - On - 1 - - - - - S6POWER - Keep RAM section S6 of RAM[n] on or off in System ON mode - 6 - 6 - - - Off - Off - 0 - - - On - On - 1 - - - - - S7POWER - Keep RAM section S7 of RAM[n] on or off in System ON mode - 7 - 7 - - - Off - Off - 0 - - - On - On - 1 - - - - - S8POWER - Keep RAM section S8 of RAM[n] on or off in System ON mode - 8 - 8 - - - Off - Off - 0 - - - On - On - 1 - - - - - S9POWER - Keep RAM section S9 of RAM[n] on or off in System ON mode - 9 - 9 - - - Off - Off - 0 - - - On - On - 1 - - - - - S10POWER - Keep RAM section S10 of RAM[n] on or off in System ON mode - 10 - 10 - - - Off - Off - 0 - - - On - On - 1 - - - - - S11POWER - Keep RAM section S11 of RAM[n] on or off in System ON mode - 11 - 11 - - - Off - Off - 0 - - - On - On - 1 - - - - - S12POWER - Keep RAM section S12 of RAM[n] on or off in System ON mode - 12 - 12 - - - Off - Off - 0 - - - On - On - 1 - - - - - S13POWER - Keep RAM section S13 of RAM[n] on or off in System ON mode - 13 - 13 - - - Off - Off - 0 - - - On - On - 1 - - - - - S14POWER - Keep RAM section S14 of RAM[n] on or off in System ON mode - 14 - 14 - - - Off - Off - 0 - - - On - On - 1 - - - - - S15POWER - Keep RAM section S15 of RAM[n] on or off in System ON mode - 15 - 15 - - - Off - Off - 0 - - - On - On - 1 - - - - - S0RETENTION - Keep retention on RAM section S0 of RAM[n] when RAM section is switched off - 16 - 16 - - - Off - Off - 0 - - - On - On - 1 - - - - - S1RETENTION - Keep retention on RAM section S1 of RAM[n] when RAM section is switched off - 17 - 17 - - - Off - Off - 0 - - - On - On - 1 - - - - - S2RETENTION - Keep retention on RAM section S2 of RAM[n] when RAM section is switched off - 18 - 18 - - - Off - Off - 0 - - - On - On - 1 - - - - - S3RETENTION - Keep retention on RAM section S3 of RAM[n] when RAM section is switched off - 19 - 19 - - - Off - Off - 0 - - - On - On - 1 - - - - - S4RETENTION - Keep retention on RAM section S4 of RAM[n] when RAM section is switched off - 20 - 20 - - - Off - Off - 0 - - - On - On - 1 - - - - - S5RETENTION - Keep retention on RAM section S5 of RAM[n] when RAM section is switched off - 21 - 21 - - - Off - Off - 0 - - - On - On - 1 - - - - - S6RETENTION - Keep retention on RAM section S6 of RAM[n] when RAM section is switched off - 22 - 22 - - - Off - Off - 0 - - - On - On - 1 - - - - - S7RETENTION - Keep retention on RAM section S7 of RAM[n] when RAM section is switched off - 23 - 23 - - - Off - Off - 0 - - - On - On - 1 - - - - - S8RETENTION - Keep retention on RAM section S8 of RAM[n] when RAM section is switched off - 24 - 24 - - - Off - Off - 0 - - - On - On - 1 - - - - - S9RETENTION - Keep retention on RAM section S9 of RAM[n] when RAM section is switched off - 25 - 25 - - - Off - Off - 0 - - - On - On - 1 - - - - - S10RETENTION - Keep retention on RAM section S10 of RAM[n] when RAM section is switched off - 26 - 26 - - - Off - Off - 0 - - - On - On - 1 - - - - - S11RETENTION - Keep retention on RAM section S11 of RAM[n] when RAM section is switched off - 27 - 27 - - - Off - Off - 0 - - - On - On - 1 - - - - - S12RETENTION - Keep retention on RAM section S12 of RAM[n] when RAM section is switched off - 28 - 28 - - - Off - Off - 0 - - - On - On - 1 - - - - - S13RETENTION - Keep retention on RAM section S13 of RAM[n] when RAM section is switched off - 29 - 29 - - - Off - Off - 0 - - - On - On - 1 - - - - - S14RETENTION - Keep retention on RAM section S14 of RAM[n] when RAM section is switched off - 30 - 30 - - - Off - Off - 0 - - - On - On - 1 - - - - - S15RETENTION - Keep retention on RAM section S15 of RAM[n] when RAM section is switched off - 31 - 31 - - - Off - Off - 0 - - - On - On - 1 - - - - - - - POWERSET - Description cluster: RAM[n] power control set register - 0x004 - read-write - 0x0000FFFF - - - S0POWER - Keep RAM section S0 of RAM[n] on or off in System ON mode - 0 - 0 - - - On - On - 1 - - - - - S1POWER - Keep RAM section S1 of RAM[n] on or off in System ON mode - 1 - 1 - - - On - On - 1 - - - - - S2POWER - Keep RAM section S2 of RAM[n] on or off in System ON mode - 2 - 2 - - - On - On - 1 - - - - - S3POWER - Keep RAM section S3 of RAM[n] on or off in System ON mode - 3 - 3 - - - On - On - 1 - - - - - S4POWER - Keep RAM section S4 of RAM[n] on or off in System ON mode - 4 - 4 - - - On - On - 1 - - - - - S5POWER - Keep RAM section S5 of RAM[n] on or off in System ON mode - 5 - 5 - - - On - On - 1 - - - - - S6POWER - Keep RAM section S6 of RAM[n] on or off in System ON mode - 6 - 6 - - - On - On - 1 - - - - - S7POWER - Keep RAM section S7 of RAM[n] on or off in System ON mode - 7 - 7 - - - On - On - 1 - - - - - S8POWER - Keep RAM section S8 of RAM[n] on or off in System ON mode - 8 - 8 - - - On - On - 1 - - - - - S9POWER - Keep RAM section S9 of RAM[n] on or off in System ON mode - 9 - 9 - - - On - On - 1 - - - - - S10POWER - Keep RAM section S10 of RAM[n] on or off in System ON mode - 10 - 10 - - - On - On - 1 - - - - - S11POWER - Keep RAM section S11 of RAM[n] on or off in System ON mode - 11 - 11 - - - On - On - 1 - - - - - S12POWER - Keep RAM section S12 of RAM[n] on or off in System ON mode - 12 - 12 - - - On - On - 1 - - - - - S13POWER - Keep RAM section S13 of RAM[n] on or off in System ON mode - 13 - 13 - - - On - On - 1 - - - - - S14POWER - Keep RAM section S14 of RAM[n] on or off in System ON mode - 14 - 14 - - - On - On - 1 - - - - - S15POWER - Keep RAM section S15 of RAM[n] on or off in System ON mode - 15 - 15 - - - On - On - 1 - - - - - S0RETENTION - Keep retention on RAM section S0 of RAM[n] when RAM section is switched off - 16 - 16 - - - On - On - 1 - - - - - S1RETENTION - Keep retention on RAM section S1 of RAM[n] when RAM section is switched off - 17 - 17 - - - On - On - 1 - - - - - S2RETENTION - Keep retention on RAM section S2 of RAM[n] when RAM section is switched off - 18 - 18 - - - On - On - 1 - - - - - S3RETENTION - Keep retention on RAM section S3 of RAM[n] when RAM section is switched off - 19 - 19 - - - On - On - 1 - - - - - S4RETENTION - Keep retention on RAM section S4 of RAM[n] when RAM section is switched off - 20 - 20 - - - On - On - 1 - - - - - S5RETENTION - Keep retention on RAM section S5 of RAM[n] when RAM section is switched off - 21 - 21 - - - On - On - 1 - - - - - S6RETENTION - Keep retention on RAM section S6 of RAM[n] when RAM section is switched off - 22 - 22 - - - On - On - 1 - - - - - S7RETENTION - Keep retention on RAM section S7 of RAM[n] when RAM section is switched off - 23 - 23 - - - On - On - 1 - - - - - S8RETENTION - Keep retention on RAM section S8 of RAM[n] when RAM section is switched off - 24 - 24 - - - On - On - 1 - - - - - S9RETENTION - Keep retention on RAM section S9 of RAM[n] when RAM section is switched off - 25 - 25 - - - On - On - 1 - - - - - S10RETENTION - Keep retention on RAM section S10 of RAM[n] when RAM section is switched off - 26 - 26 - - - On - On - 1 - - - - - S11RETENTION - Keep retention on RAM section S11 of RAM[n] when RAM section is switched off - 27 - 27 - - - On - On - 1 - - - - - S12RETENTION - Keep retention on RAM section S12 of RAM[n] when RAM section is switched off - 28 - 28 - - - On - On - 1 - - - - - S13RETENTION - Keep retention on RAM section S13 of RAM[n] when RAM section is switched off - 29 - 29 - - - On - On - 1 - - - - - S14RETENTION - Keep retention on RAM section S14 of RAM[n] when RAM section is switched off - 30 - 30 - - - On - On - 1 - - - - - S15RETENTION - Keep retention on RAM section S15 of RAM[n] when RAM section is switched off - 31 - 31 - - - On - On - 1 - - - - - - - POWERCLR - Description cluster: RAM[n] power control clear register - 0x008 - read-write - 0x0000FFFF - - - S0POWER - Keep RAM section S0 of RAM[n] on or off in System ON mode - 0 - 0 - - - Off - Off - 1 - - - - - S1POWER - Keep RAM section S1 of RAM[n] on or off in System ON mode - 1 - 1 - - - Off - Off - 1 - - - - - S2POWER - Keep RAM section S2 of RAM[n] on or off in System ON mode - 2 - 2 - - - Off - Off - 1 - - - - - S3POWER - Keep RAM section S3 of RAM[n] on or off in System ON mode - 3 - 3 - - - Off - Off - 1 - - - - - S4POWER - Keep RAM section S4 of RAM[n] on or off in System ON mode - 4 - 4 - - - Off - Off - 1 - - - - - S5POWER - Keep RAM section S5 of RAM[n] on or off in System ON mode - 5 - 5 - - - Off - Off - 1 - - - - - S6POWER - Keep RAM section S6 of RAM[n] on or off in System ON mode - 6 - 6 - - - Off - Off - 1 - - - - - S7POWER - Keep RAM section S7 of RAM[n] on or off in System ON mode - 7 - 7 - - - Off - Off - 1 - - - - - S8POWER - Keep RAM section S8 of RAM[n] on or off in System ON mode - 8 - 8 - - - Off - Off - 1 - - - - - S9POWER - Keep RAM section S9 of RAM[n] on or off in System ON mode - 9 - 9 - - - Off - Off - 1 - - - - - S10POWER - Keep RAM section S10 of RAM[n] on or off in System ON mode - 10 - 10 - - - Off - Off - 1 - - - - - S11POWER - Keep RAM section S11 of RAM[n] on or off in System ON mode - 11 - 11 - - - Off - Off - 1 - - - - - S12POWER - Keep RAM section S12 of RAM[n] on or off in System ON mode - 12 - 12 - - - Off - Off - 1 - - - - - S13POWER - Keep RAM section S13 of RAM[n] on or off in System ON mode - 13 - 13 - - - Off - Off - 1 - - - - - S14POWER - Keep RAM section S14 of RAM[n] on or off in System ON mode - 14 - 14 - - - Off - Off - 1 - - - - - S15POWER - Keep RAM section S15 of RAM[n] on or off in System ON mode - 15 - 15 - - - Off - Off - 1 - - - - - S0RETENTION - Keep retention on RAM section S0 of RAM[n] when RAM section is switched off - 16 - 16 - - - Off - Off - 1 - - - - - S1RETENTION - Keep retention on RAM section S1 of RAM[n] when RAM section is switched off - 17 - 17 - - - Off - Off - 1 - - - - - S2RETENTION - Keep retention on RAM section S2 of RAM[n] when RAM section is switched off - 18 - 18 - - - Off - Off - 1 - - - - - S3RETENTION - Keep retention on RAM section S3 of RAM[n] when RAM section is switched off - 19 - 19 - - - Off - Off - 1 - - - - - S4RETENTION - Keep retention on RAM section S4 of RAM[n] when RAM section is switched off - 20 - 20 - - - Off - Off - 1 - - - - - S5RETENTION - Keep retention on RAM section S5 of RAM[n] when RAM section is switched off - 21 - 21 - - - Off - Off - 1 - - - - - S6RETENTION - Keep retention on RAM section S6 of RAM[n] when RAM section is switched off - 22 - 22 - - - Off - Off - 1 - - - - - S7RETENTION - Keep retention on RAM section S7 of RAM[n] when RAM section is switched off - 23 - 23 - - - Off - Off - 1 - - - - - S8RETENTION - Keep retention on RAM section S8 of RAM[n] when RAM section is switched off - 24 - 24 - - - Off - Off - 1 - - - - - S9RETENTION - Keep retention on RAM section S9 of RAM[n] when RAM section is switched off - 25 - 25 - - - Off - Off - 1 - - - - - S10RETENTION - Keep retention on RAM section S10 of RAM[n] when RAM section is switched off - 26 - 26 - - - Off - Off - 1 - - - - - S11RETENTION - Keep retention on RAM section S11 of RAM[n] when RAM section is switched off - 27 - 27 - - - Off - Off - 1 - - - - - S12RETENTION - Keep retention on RAM section S12 of RAM[n] when RAM section is switched off - 28 - 28 - - - Off - Off - 1 - - - - - S13RETENTION - Keep retention on RAM section S13 of RAM[n] when RAM section is switched off - 29 - 29 - - - Off - Off - 1 - - - - - S14RETENTION - Keep retention on RAM section S14 of RAM[n] when RAM section is switched off - 30 - 30 - - - Off - Off - 1 - - - - - S15RETENTION - Keep retention on RAM section S15 of RAM[n] when RAM section is switched off - 31 - 31 - - - Off - Off - 1 - - - - - - - - - - VMC_S - Volatile Memory controller 1 - 0x50081000 - - - - - \ No newline at end of file + + + + Nordic Semiconductor + Nordic + nrf5340_application + nrf53 + 1 + nRF53 reference description for system-on-chip with dual ARM 32-bit Cortex-M33 microcontrollers + +Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + + 8 + 32 + 32 + 0x00000000 + 0xFFFFFFFF + + CM33 + r0p4 + little + 1 + 1 + 3 + 0 + 69 + 0 + + system_nrf53 + NRF_ + + 240 + + + + CACHEDATA_S + CACHEDATA + 0x00F00000 + CACHEDATA + + + + 0 + 0x1000 + registers + + CACHEDATA + 0x20 + + + 256 + 0x020 + SET[%s] + Unspecified + CACHEDATA_SET + read-write + 0x0 + + 2 + 0x010 + WAY[%s] + Unspecified + CACHEDATA_SET_WAY + read-write + 0x0 + + DATA0 + Description cluster: Cache data bits [31:0] of SET[n], WAY[o]. + 0x0 + read-write + + + Data + Data + 0 + 31 + + + + + DATA1 + Description cluster: Cache data bits [63:32] of SET[n], WAY[o]. + 0x4 + read-write + + + Data + Data + 0 + 31 + + + + + DATA2 + Description cluster: Cache data bits [95:64] of SET[n], WAY[o]. + 0x8 + read-write + + + Data + Data + 0 + 31 + + + + + DATA3 + Description cluster: Cache data bits [127:96] of SET[n], WAY[o]. + 0xC + read-write + + + Data + Data + 0 + 31 + + + + + + + + + CACHEINFO_S + CACHEINFO + 0x00F08000 + CACHEINFO + + + + 0 + 0x1000 + registers + + CACHEINFO + 0x20 + + + 256 + 0x008 + SET[%s] + Unspecified + CACHEINFO_SET + read-write + 0x0 + + 0x2 + 0x4 + WAY[%s] + Description collection: Cache information for SET[n], WAY[o]. + 0x0 + read-write + + + TAG + Cache tag. + 0 + 16 + + + V + Valid bit + 30 + 30 + read-only + + + Invalid + Invalid cache line + 0 + + + Valid + Valid cache line + 1 + + + + + MRU + Most recently used way. + 31 + 31 + read-only + + + Way0 + Way0 was most recently used + 0 + + + Way1 + Way1 was most recently used + 1 + + + + + + + + + + FICR_S + Factory Information Configuration Registers + 0x00FF0000 + FICR + + + + 0 + 0x1000 + registers + + FICR + 0x20 + + + INFO + Device info + FICR_INFO + read-write + 0x200 + + CONFIGID + Configuration identifier + 0x000 + read-only + 0xFFFFFFFF + + + HWID + Identification number for the HW + 0 + 15 + + + + + 0x2 + 0x4 + DEVICEID[%s] + Description collection: Device identifier + 0x004 + read-only + 0xFFFFFFFF + + + DEVICEID + 64 bit unique device identifier + 0 + 31 + + + + + PART + Part code + 0x00C + read-only + 0x00005340 + + + PART + Part code + 0 + 31 + + + N5340 + nRF5340 + 0x5340 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + VARIANT + Part Variant, Hardware version and Production configuration + 0x010 + read-only + 0xFFFFFFFF + + + VARIANT + Part Variant, Hardware version and Production configuration, encoded as ASCII + 0 + 31 + + + QKAA + QKAA + 0x514B4141 + + + CLAA + CLAA + 0x434C4141 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + PACKAGE + Package option + 0x014 + read-only + 0xFFFFFFFF + + + PACKAGE + Package option + 0 + 31 + + + QK + QKxx - 94-pin aQFN + 0x2000 + + + CL + CLxx - WLCSP + 0x2005 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + RAM + RAM variant + 0x018 + read-only + 0xFFFFFFFF + + + RAM + RAM variant + 0 + 31 + + + K16 + 16 kByte RAM + 0x10 + + + K32 + 32 kByte RAM + 0x20 + + + K64 + 64 kByte RAM + 0x40 + + + K128 + 128 kByte RAM + 0x80 + + + K256 + 256 kByte RAM + 0x100 + + + K512 + 512 kByte RAM + 0x200 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + FLASH + Flash variant + 0x01C + read-only + 0xFFFFFFFF + + + FLASH + Flash variant + 0 + 31 + + + K128 + 128 kByte FLASH + 0x80 + + + K256 + 256 kByte FLASH + 0x100 + + + K512 + 512 kByte FLASH + 0x200 + + + K1024 + 1 MByte FLASH + 0x400 + + + K2048 + 2 MByte FLASH + 0x800 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + CODEPAGESIZE + Code memory page size in bytes + 0x020 + read-only + 0x00001000 + + + CODEPAGESIZE + Code memory page size in bytes + 0 + 31 + + + K4096 + 4 kByte + 0x1000 + + + + + + + CODESIZE + Code memory size + 0x024 + read-only + 0x00000100 + + + CODESIZE + Code memory size in number of pages + 0 + 31 + + + P256 + 256 pages + 256 + + + + + + + DEVICETYPE + Device type + 0x028 + read-only + 0x00000000 + + + DEVICETYPE + Device type + 0 + 31 + + + Die + Device is an physical DIE + 0x0000000 + + + FPGA + Device is an FPGA + 0xFFFFFFFF + + + + + + + + 32 + 0x008 + TRIMCNF[%s] + Unspecified + FICR_TRIMCNF + read-write + 0x300 + + ADDR + Description cluster: Address of the PAR register which will be written + 0x000 + read-only + 0xFFFFFFFF + uint32_t + + + Address + Address + 0 + 31 + + + + + DATA + Description cluster: Data + 0x004 + read-only + 0xFFFFFFFF + + + Data + Data to be written into the PAR register + 0 + 31 + + + + + + NFC + Unspecified + FICR_NFC + read-write + 0x450 + + TAGHEADER0 + Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. + 0x000 + read-only + 0xFFFFFF5F + + + MFGID + Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F + 0 + 7 + + + UD1 + Unique identifier byte 1 + 8 + 15 + + + UD2 + Unique identifier byte 2 + 16 + 23 + + + UD3 + Unique identifier byte 3 + 24 + 31 + + + + + TAGHEADER1 + Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. + 0x004 + read-only + 0xFFFFFFFF + + + UD4 + Unique identifier byte 4 + 0 + 7 + + + UD5 + Unique identifier byte 5 + 8 + 15 + + + UD6 + Unique identifier byte 6 + 16 + 23 + + + UD7 + Unique identifier byte 7 + 24 + 31 + + + + + TAGHEADER2 + Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. + 0x008 + read-only + 0xFFFFFFFF + + + UD8 + Unique identifier byte 8 + 0 + 7 + + + UD9 + Unique identifier byte 9 + 8 + 15 + + + UD10 + Unique identifier byte 10 + 16 + 23 + + + UD11 + Unique identifier byte 11 + 24 + 31 + + + + + TAGHEADER3 + Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. + 0x00C + read-only + 0xFFFFFFFF + + + UD12 + Unique identifier byte 12 + 0 + 7 + + + UD13 + Unique identifier byte 13 + 8 + 15 + + + UD14 + Unique identifier byte 14 + 16 + 23 + + + UD15 + Unique identifier byte 15 + 24 + 31 + + + + + + TRNG90B + NIST800-90B RNG calibration data + FICR_TRNG90B + read-write + 0xC00 + + BYTES + Amount of bytes for the required entropy bits + 0x000 + read-only + 0x00000210 + + + BYTES + Amount of bytes for the required entropy bits + 0 + 31 + + + + + RCCUTOFF + Repetition counter cutoff + 0x004 + read-only + 0xFFFFFFFF + + + RCCUTOFF + Repetition counter cutoff + 0 + 31 + + + + + APCUTOFF + Adaptive proportion cutoff + 0x008 + read-only + 0xFFFFFFFF + + + APCUTOFF + Adaptive proportion cutoff + 0 + 31 + + + + + STARTUP + Amount of bytes for the startup tests + 0x00C + read-only + 0xFFFFFFFF + + + STARTUP + Amount of bytes for the startup tests + 0 + 31 + + + + + ROSC1 + Sample count for ring oscillator 1 + 0x010 + read-only + 0xFFFFFFFF + + + ROSC1 + Sample count for ring oscillator 1 + 0 + 31 + + + + + ROSC2 + Sample count for ring oscillator 2 + 0x014 + read-only + 0xFFFFFFFF + + + ROSC2 + Sample count for ring oscillator 2 + 0 + 31 + + + + + ROSC3 + Sample count for ring oscillator 3 + 0x018 + read-only + 0xFFFFFFFF + + + ROSC3 + Sample count for ring oscillator 3 + 0 + 31 + + + + + ROSC4 + Sample count for ring oscillator 4 + 0x01C + read-only + 0xFFFFFFFF + + + ROSC4 + Sample count for ring oscillator 4 + 0 + 31 + + + + + + XOSC32MTRIM + XOSC32M capacitor selection trim values + 0xC20 + read-only + 0xFFFFFFFF + + + SLOPE + Slope trim factor on twos complement form + 0 + 4 + + + OFFSET + Offset trim factor on integer form + 5 + 9 + + + + + + + UICR_S + User Information Configuration Registers User information configuration registers + 0x00FF8000 + UICR + + + + 0 + 0x1000 + registers + + UICR + 0x20 + + + APPROTECT + Access port protection + 0x000 + read-write + 0x00000000 + + + PALL + Blocks debugger read/write access to all CPU registers and + memory mapped addresses. + 0 + 31 + + + Unprotected + Unprotected + 0x50FA50FA + + + Protected + Protected + 0x00000000 + + + + + + + VREGHVOUT + Output voltage from the high voltage (VREGH) regulator stage. The maximum output voltage from this stage is given as VDDH - VREGHDROP. + 0x010 + read-write + 0xFFFFFFFF + + + VREGHVOUT + VREGH regulator output voltage. + 0 + 2 + + + 1V8 + 1.8 V + 0 + + + 2V1 + 2.1 V + 1 + + + 2V4 + 2.4 V + 2 + + + 2V7 + 2.7 V + 3 + + + 3V0 + 3.0 V + 4 + + + 3V3 + 3.3 V + 5 + + + DEFAULT + Default voltage: 1.8 V + 7 + + + + + + + HFXOCNT + HFXO startup counter + 0x014 + read-write + 0xFFFFFFFF + + + HFXOCNT + HFXO startup counter. Total debounce time = HFXOCNT*64 us + 0.5 us + 0 + 7 + + + MinDebounceTime + Min debounce time = (0*64 us + 0.5 us) + 0 + + + MaxDebounceTime + Max debounce time = (254*64 us + 0.5 us) + 254 + + + DefaultDebounceTime + Default debounce time for erased UICR = 4*64 us + 0.5 us + 255 + + + + + + + SECUREAPPROTECT + Secure access port protection + 0x01C + read-write + 0x00000000 + + + PALL + Blocks debugger read/write access to all secure CPU registers and secure memory + mapped addresses. + 0 + 31 + + + Unprotected + Unprotected + 0x50FA50FA + + + Protected + Protected + 0x00000000 + + + + + + + ERASEPROTECT + Erase protection + 0x020 + read-write + 0x00000000 + + + PALL + Blocks NVMC ERASEALL and CTRLAP ERASEALL functionality. Using any value except Unprotected will lead to the protection being enabled. + 0 + 31 + + + Unprotected + Unprotected + 0xFFFFFFFF + + + Protected + Protected + 0x00000000 + + + + + + + TINSTANCE + SW-DP Target instance + 0x024 + read-write + 0xFFFFFFFF + + + TINSTANCE + TINSTANCE bits are negated and used in the SW-DP DLPIDR.TINSTANCE field. E.g. 0xF in this field is translated to 0x0 in DLPIDR.TINSTANCE field. + 28 + 31 + + + + + NFCPINS + Setting of pins dedicated to NFC functionality: NFC antenna or GPIO + 0x028 + read-write + 0xFFFFFFFF + + + PROTECT + Setting of pins dedicated to NFC functionality + 0 + 0 + + + Disabled + Operation as GPIO pins. Same protection as normal GPIO pins + 0 + + + NFC + Operation as NFC antenna pins. Configures the protection for NFC operation + 1 + + + + + + + 0xC0 + 0x4 + OTP[%s] + Description collection: One time programmable memory + 0x100 + read-write + 0xFFFFFFFF + + + LOWER + Lower half word + 0 + 15 + read-writeOnce + + + UPPER + Upper half word + 16 + 31 + read-writeOnce + + + + + KEYSLOT + Unspecified + UICR_KEYSLOT + read-write + 0x400 + + 128 + 0x008 + CONFIG[%s] + Unspecified + UICR_KEYSLOT_CONFIG + read-write + 0x000 + + DEST + Description cluster: Destination address where content of the key value registers (KEYSLOT.KEYn.VALUE[0-3]) + will be pushed by KMU. Note that this address must match that of a peripherals + APB mapped write-only key registers, else the KMU can push this key value into + an address range which the CPU can potentially read. + 0x000 + read-write + 0xFFFFFFFF + + + DEST + Secure APB destination address + 0 + 31 + + + + + PERM + Description cluster: Define permissions for the key slot. Bits 0-15 and 16-31 can only be written when equal to 0xFFFF. + 0x004 + read-write + 0xFFFFFFFF + + + WRITE + Write permission for key slot + 0 + 0 + + + Disabled + Disable write to the key value registers + 0 + + + Enabled + Enable write to the key value registers + 1 + + + + + READ + Read permission for key slot + 1 + 1 + + + Disabled + Disable read from key value registers + 0 + + + Enabled + Enable read from key value registers + 1 + + + + + PUSH + Push permission for key slot + 2 + 2 + + + Disabled + Disable pushing of key value registers over secure APB, but can be read if field READ is Enabled + 0 + + + Enabled + Enable pushing of key value registers over secure APB. Register KEYSLOT.CONFIGn.DEST must contain a valid destination address! + 1 + + + + + STATE + Revocation state for the key slot + 16 + 16 + + + Revoked + Key value registers can no longer be read or pushed + 0 + + + Active + Key value registers are readable (if enabled) and can be pushed (if enabled) + 1 + + + + + + + + 128 + 0x010 + KEY[%s] + Unspecified + UICR_KEYSLOT_KEY + read-write + 0x400 + + 0x4 + 0x4 + VALUE[%s] + Description collection: Define bits [31+o*32:0+o*32] of value assigned to KMU key slot. + 0x000 + read-write + 0xFFFFFFFF + + + VALUE + Define bits [31+o*32:0+o*32] of value assigned to KMU key slot + 0 + 31 + + + + + + + + + CTI_S + Cross-Trigger Interface control. NOTE: this is not a separate peripheral, but describes CM33 functionality. + 0xE0042000 + CTI + + + + 0 + 0x1000 + registers + + CTI + 0x20 + + + CTICONTROL + CTI Control register + 0x000 + read-write + 0x00000000 + + + GLBEN + Enables or disables the CTI. + 0 + 0 + + + Disabled + All cross-triggering mapping logic functionality is disabled. + 0 + + + Enabled + Cross-triggering mapping logic functionality is enabled. + 1 + + + + + + + CTIINTACK + CTI Interrupt Acknowledge register + 0x010 + write-only + 0x00000000 + + + DEBUGREQ + Processor debug request + 0 + 0 + + write + + Acknowledge + Clears the ctitrigout. + 1 + + + + + CPURESTART + Processor Restart + 1 + 1 + + write + + Acknowledge + Clears the ctitrigout. + 1 + + + + + UNUSED0 + N/A + 2 + 2 + + write + + Acknowledge + Clears the ctitrigout. + 1 + + + + + UNUSED1 + N/A + 3 + 3 + + write + + Acknowledge + Clears the ctitrigout. + 1 + + + + + ETMEVTIN0 + ETM Event Input 0 + 4 + 4 + + write + + Acknowledge + Clears the ctitrigout. + 1 + + + + + ETMEVTIN1 + ETM Event Input 1 + 5 + 5 + + write + + Acknowledge + Clears the ctitrigout. + 1 + + + + + ETMEVTIN2 + ETM Event Input 2 + 6 + 6 + + write + + Acknowledge + Clears the ctitrigout. + 1 + + + + + ETMEVTIN3 + ETM Event Input 3 + 7 + 7 + + write + + Acknowledge + Clears the ctitrigout. + 1 + + + + + + + CTIAPPSET + CTI Application Trigger Set register + 0x014 + read-write + 0x00000000 + + + APPSET_0 + Application trigger event for channel 0. + 0 + 0 + + read + + Inactive + Application trigger 0 is inactive. + 0 + + + Active + Application trigger 0 is active. + 1 + + + + write + + Activate + Generate channel event for channel 0. + 1 + + + + + APPSET_1 + Application trigger event for channel 1. + 1 + 1 + + read + + Inactive + Application trigger 1 is inactive. + 0 + + + Active + Application trigger 1 is active. + 1 + + + + write + + Activate + Generate channel event for channel 1. + 1 + + + + + APPSET_2 + Application trigger event for channel 2. + 2 + 2 + + read + + Inactive + Application trigger 2 is inactive. + 0 + + + Active + Application trigger 2 is active. + 1 + + + + write + + Activate + Generate channel event for channel 2. + 1 + + + + + APPSET_3 + Application trigger event for channel 3. + 3 + 3 + + read + + Inactive + Application trigger 3 is inactive. + 0 + + + Active + Application trigger 3 is active. + 1 + + + + write + + Activate + Generate channel event for channel 3. + 1 + + + + + + + CTIAPPCLEAR + CTI Application Trigger Clear register + 0x018 + write-only + 0x00000000 + + + APPCLEAR_0 + Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. + 0 + 0 + + write + + Clear + Clears the event for channel 0. + 1 + + + + + APPCLEAR_1 + Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. + 1 + 1 + + write + + Clear + Clears the event for channel 1. + 1 + + + + + APPCLEAR_2 + Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. + 2 + 2 + + write + + Clear + Clears the event for channel 2. + 1 + + + + + APPCLEAR_3 + Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. + 3 + 3 + + write + + Clear + Clears the event for channel 3. + 1 + + + + + + + CTIAPPPULSE + CTI Application Pulse register + 0x01C + write-only + 0x00000000 + + + APPULSE_0 + Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. + 0 + 0 + + write + + Generate + Generates an event pulse on channel 0. + 1 + + + + + APPULSE_1 + Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. + 1 + 1 + + write + + Generate + Generates an event pulse on channel 1. + 1 + + + + + APPULSE_2 + Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. + 2 + 2 + + write + + Generate + Generates an event pulse on channel 2. + 1 + + + + + APPULSE_3 + Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. + 3 + 3 + + write + + Generate + Generates an event pulse on channel 3. + 1 + + + + + + + 0x8 + 0x4 + CTIINEN[%s] + Description collection: CTI Trigger input + 0x020 + read-write + 0x00000000 + + + TRIGINEN_0 + Enables a cross trigger event to channel 0 when a ctitrigin input is activated. + 0 + 0 + + + Disabled + Input trigger n events are ignored by channel 0. + 0 + + + Enabled + When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 0. + 1 + + + + + TRIGINEN_1 + Enables a cross trigger event to channel 1 when a ctitrigin input is activated. + 1 + 1 + + + Disabled + Input trigger n events are ignored by channel 1. + 0 + + + Enabled + When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 1. + 1 + + + + + TRIGINEN_2 + Enables a cross trigger event to channel 2 when a ctitrigin input is activated. + 2 + 2 + + + Disabled + Input trigger n events are ignored by channel 2. + 0 + + + Enabled + When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 2. + 1 + + + + + TRIGINEN_3 + Enables a cross trigger event to channel 3 when a ctitrigin input is activated. + 3 + 3 + + + Disabled + Input trigger n events are ignored by channel 3. + 0 + + + Enabled + When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 3. + 1 + + + + + + + 0x8 + 0x4 + CTIOUTEN[%s] + Description collection: CTI Trigger output + 0x0A0 + read-write + 0x00000000 + + + TRIGOUTEN_0 + Enables a cross trigger event to ctitrigout when channel 0 is activated. + 0 + 0 + + + Disabled + Channel 0 is ignored by output trigger n. + 0 + + + Enabled + When an event occurs on channel 0, generate an event on output event n (ctitrigout[n]). + 1 + + + + + TRIGOUTEN_1 + Enables a cross trigger event to ctitrigout when channel 1 is activated. + 1 + 1 + + + Disabled + Channel 1 is ignored by output trigger n. + 0 + + + Enabled + When an event occurs on channel 1, generate an event on output event n (ctitrigout[n]). + 1 + + + + + TRIGOUTEN_2 + Enables a cross trigger event to ctitrigout when channel 2 is activated. + 2 + 2 + + + Disabled + Channel 2 is ignored by output trigger n. + 0 + + + Enabled + When an event occurs on channel 2, generate an event on output event n (ctitrigout[n]). + 1 + + + + + TRIGOUTEN_3 + Enables a cross trigger event to ctitrigout when channel 3 is activated. + 3 + 3 + + + Disabled + Channel 3 is ignored by output trigger n. + 0 + + + Enabled + When an event occurs on channel 3, generate an event on output event n (ctitrigout[n]). + 1 + + + + + + + CTITRIGINSTATUS + CTI Trigger In Status register + 0x130 + read-only + 0x00000000 + + + CPUHALTED + Processor Halted + 0 + 0 + + + Active + Ctitrigin 0 is active. + 1 + + + Inactive + Ctitrigin 0 is inactive. + 0 + + + + + DWTCOMPOUT0 + DWT Comparator Output 0 + 1 + 1 + + + Active + Ctitrigin 1 is active. + 1 + + + Inactive + Ctitrigin 1 is inactive. + 0 + + + + + DWTCOMPOUT1 + DWT Comparator Output 1 + 2 + 2 + + + Active + Ctitrigin 2 is active. + 1 + + + Inactive + Ctitrigin 2 is inactive. + 0 + + + + + DWTCOMPOUT2 + DWT Comparator Output 2 + 3 + 3 + + + Active + Ctitrigin 3 is active. + 1 + + + Inactive + Ctitrigin 3 is inactive. + 0 + + + + + ETMEVTOUT0 + ETM Event Output 0 + 4 + 4 + + + Active + Ctitrigin 4 is active. + 1 + + + Inactive + Ctitrigin 4 is inactive. + 0 + + + + + ETMEVTOUT1 + ETM Event Output 1 + 5 + 5 + + + Active + Ctitrigin 5 is active. + 1 + + + Inactive + Ctitrigin 5 is inactive. + 0 + + + + + UNUSED0 + N/A + 6 + 6 + + + Active + Ctitrigin 6 is active. + 1 + + + Inactive + Ctitrigin 6 is inactive. + 0 + + + + + UNUSED1 + N/A + 7 + 7 + + + Active + Ctitrigin 7 is active. + 1 + + + Inactive + Ctitrigin 7 is inactive. + 0 + + + + + + + CTITRIGOUTSTATUS + CTI Trigger Out Status register + 0x134 + read-only + 0x00000000 + + + DEBUGREQ + Processor debug request + 0 + 0 + + + Active + Ctitrigout 0 is active. + 1 + + + Inactive + Ctitrigout 0 is inactive. + 0 + + + + + CPURESTART + Processor Restart + 1 + 1 + + + Active + Ctitrigout 1 is active. + 1 + + + Inactive + Ctitrigout 1 is inactive. + 0 + + + + + UNUSED0 + N/A + 2 + 2 + + + Active + Ctitrigout 2 is active. + 1 + + + Inactive + Ctitrigout 2 is inactive. + 0 + + + + + UNUSED1 + N/A + 3 + 3 + + + Active + Ctitrigout 3 is active. + 1 + + + Inactive + Ctitrigout 3 is inactive. + 0 + + + + + ETMEVTIN0 + ETM Event Input 0 + 4 + 4 + + + Active + Ctitrigout 4 is active. + 1 + + + Inactive + Ctitrigout 4 is inactive. + 0 + + + + + ETMEVTIN1 + ETM Event Input 1 + 5 + 5 + + + Active + Ctitrigout 5 is active. + 1 + + + Inactive + Ctitrigout 5 is inactive. + 0 + + + + + ETMEVTIN2 + ETM Event Input 2 + 6 + 6 + + + Active + Ctitrigout 6 is active. + 1 + + + Inactive + Ctitrigout 6 is inactive. + 0 + + + + + ETMEVTIN3 + ETM Event Input 3 + 7 + 7 + + + Active + Ctitrigout 7 is active. + 1 + + + Inactive + Ctitrigout 7 is inactive. + 0 + + + + + + + CTICHINSTATUS + CTI Channel In Status register + 0x138 + read-only + 0x00000000 + + + CTICHINSTATUS_0 + Shows the status of the ctitrigin 0 input. + 0 + 0 + + + Active + Ctichin 0 is active. + 1 + + + Inactive + Ctichin 0 is inactive. + 0 + + + + + CTICHINSTATUS_1 + Shows the status of the ctitrigin 1 input. + 1 + 1 + + + Active + Ctichin 1 is active. + 1 + + + Inactive + Ctichin 1 is inactive. + 0 + + + + + CTICHINSTATUS_2 + Shows the status of the ctitrigin 2 input. + 2 + 2 + + + Active + Ctichin 2 is active. + 1 + + + Inactive + Ctichin 2 is inactive. + 0 + + + + + CTICHINSTATUS_3 + Shows the status of the ctitrigin 3 input. + 3 + 3 + + + Active + Ctichin 3 is active. + 1 + + + Inactive + Ctichin 3 is inactive. + 0 + + + + + + + CTIGATE + Enable CTI Channel Gate register + 0x140 + read-write + 0x0000000F + + + CTIGATEEN_0 + Enable ctichout0. + 0 + 0 + + + Enabled + Enable ctichout channel 0 propagation. + 1 + + + Disabled + Disable ctichout channel 0 propagation. + 0 + + + + + CTIGATEEN_1 + Enable ctichout1. + 1 + 1 + + + Enabled + Enable ctichout channel 1 propagation. + 1 + + + Disabled + Disable ctichout channel 1 propagation. + 0 + + + + + CTIGATEEN_2 + Enable ctichout2. + 2 + 2 + + + Enabled + Enable ctichout channel 2 propagation. + 1 + + + Disabled + Disable ctichout channel 2 propagation. + 0 + + + + + CTIGATEEN_3 + Enable ctichout3. + 3 + 3 + + + Enabled + Enable ctichout channel 3 propagation. + 1 + + + Disabled + Disable ctichout channel 3 propagation. + 0 + + + + + + + DEVARCH + Device Architecture register + 0xFBC + read-only + 0x47701A14 + + + Architecture + Contains the CTI device architecture. + 0 + 0 + + + + + DEVID + Device Configuration register + 0xFC8 + read-only + 0x00040800 + + + EXTMUXNUM + Indicates the number of multiplexers available on Trigger Inputs and Trigger Outputs that are using asicctl. + The default value of 0b00000 indicates that no multiplexing is present. + 0 + 4 + + + NUMTRIG + Number of ECT triggers available. + 8 + 15 + + + NUMCH + Number of ECT channels available. + 16 + 19 + + + + + DEVTYPE + Device Type Identifier register + 0xFCC + read-only + 0x00000014 + + + MAJOR + Major classification of the type of the debug component as specified in the Arm Architecture Specification for this + debug and trace component. + 0 + 3 + + + Controller + Indicates that this component allows a debugger to control other components in an Arm CoreSight SoC-400 system. + 4 + + + + + SUB + Sub-classification of the type of the debug component as specified in the Arm Architecture Specification within + the major classification as specified in the MAJOR field. + 4 + 7 + + + Crosstrigger + Indicates that this component is a sub-triggering component. + 1 + + + + + + + PIDR4 + Peripheral ID4 Register + 0xFD0 + read-only + 0x00000004 + + + DES_2 + Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. + 0 + 3 + + + Code + JEDEC continuation code. + 4 + + + + + SIZE + Always 0b0000. Indicates that the device only occupies 4KB of memory. + 4 + 7 + + + + + PIDR5 + Peripheral ID5 register + 0xFD4 + read-only + + + PIDR6 + Peripheral ID6 register + 0xFD8 + read-only + + + PIDR7 + Peripheral ID7 register + 0xFDC + read-only + + + PIDR0 + Peripheral ID0 Register + 0xFE0 + read-only + 0x00000021 + + + PART_0 + Bits[7:0] of the 12-bit part number of the component. The designer of the component assigns this part number. + 0 + 7 + + + PartnumberL + Indicates bits[7:0] of the part number of the component. + 0x21 + + + + + + + PIDR1 + Peripheral ID1 Register + 0xFE4 + read-only + 0x000000BD + + + PART_1 + Bits[11:8] of the 12-bit part number of the component. The designer of the component assigns this part number. + 0 + 3 + + + PartnumberH + Indicates bits[11:8] of the part number of the component. + 13 + + + + + DES_0 + Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. + 4 + 7 + + + Arm + Arm. Bits[3:0] of the JEDEC JEP106 Identity Code + 11 + + + + + + + PIDR2 + Peripheral ID2 Register + 0xFE8 + read-only + 0x0000000B + + + DES_1 + Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. + 0 + 2 + + + Arm + Arm. Bits[6:4] of the JEDEC JEP106 Identity Code + 3 + + + + + JEDEC + Always 1. Indicates that the JEDEC-assigned designer ID is used. + 3 + 3 + + + REVISION + Peripheral revision + 4 + 7 + + + Rev0p0 + This device is at r0p0 + 0 + + + + + + + PIDR3 + Peripheral ID3 Register + 0xFEC + read-only + 0x00000000 + + + CMOD + Customer Modified. Indicates whether the customer has modified the behavior of the component. In most cases, + this field is 0b0000. Customers change this value when they make authorized modifications to this component. + 0 + 3 + + + Unmodified + Indicates that the customer has not modified this component. + 0 + + + + + REVAND + Indicates minor errata fixes specific to the revision of the component being used, for example metal fixes after + implementation. In most cases, this field is 0b0000. Arm recommends that the component designers ensure that a + metal fix can change this field if required, for example, by driving it from registers that reset to 0b0000. + 4 + 7 + + + NoErrata + Indicates that there are no errata fixes to this component. + 0 + + + + + + + CIDR0 + Component ID0 Register + 0xFF0 + read-only + 0x0000000D + + + PRMBL_0 + Preamble[0]. Contains bits[7:0] of the component identification code. + 0 + 7 + + + Value + Bits[7:0] of the identification code. + 0x0D + + + + + + + CIDR1 + Component ID1 Register + 0xFF4 + read-only + 0x00000090 + + + PRMBL_1 + Preamble[1]. Contains bits[11:8] of the component identification code. + 0 + 3 + + + Value + Bits[11:8] of the identification code. + 0 + + + + + CLASS + Class of the component, for example, whether the component is a ROM table or a generic CoreSight component. + Contains bits[15:12] of the component identification code + 4 + 7 + + + Coresight + Indicates that the component is a CoreSight component. + 9 + + + + + + + CIDR2 + Component ID2 Register + 0xFF8 + read-only + 0x00000005 + + + PRMBL_2 + Preamble[2]. Contains bits[23:16] of the component identification code. + 0 + 7 + + + Value + Bits[23:16] of the identification code. + 0x05 + + + + + + + CIDR3 + Component ID3 Register + 0xFFC + read-only + 0x000000B1 + + + PRMBL_3 + Preamble[3]. Contains bits[31:24] of the component identification code. + 0 + 7 + + + Value + Bits[31:24] of the identification code. + 0xB1 + + + + + + + + + TAD_S + Trace and debug control + 0xE0080000 + TAD + + + + 0 + 0x1000 + registers + + TAD + 0x20 + + + CLOCKSTART + Start all trace and debug clocks. + 0x004 + write-only + + + START + 0 + 0 + + + Start + Start all trace and debug clocks. + 1 + + + + + + + CLOCKSTOP + Stop all trace and debug clocks. + 0x008 + write-only + + + STOP + 0 + 0 + + + Stop + Stop all trace and debug clocks. + 1 + + + + + + + ENABLE + Enable debug domain and aquire selected GPIOs + 0x500 + read-write + + + ENABLE + 0 + 0 + + + DISABLED + Disable debug domain and release selected GPIOs + 0 + + + ENABLED + Enable debug domain and aquire selected GPIOs + 1 + + + + + + + PSEL + Unspecified + TAD_PSEL + read-write + 0x504 + + TRACECLK + Pin configuration for TRACECLK + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + Traceclk + TRACECLK pin + 12 + + + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + TRACEDATA0 + Pin configuration for TRACEDATA[0] + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + Tracedata0 + TRACEDATA0 pin + 11 + + + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + TRACEDATA1 + Pin configuration for TRACEDATA[1] + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + Tracedata1 + TRACEDATA1 pin + 10 + + + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + TRACEDATA2 + Pin configuration for TRACEDATA[2] + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + Tracedata2 + TRACEDATA2 pin + 9 + + + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + TRACEDATA3 + Pin configuration for TRACEDATA[3] + 0x010 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + Tracedata3 + TRACEDATA3 pin + 8 + + + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + TRACEPORTSPEED + Clocking options for the Trace Port debug interface Reset behavior is the same as debug components + 0x518 + read-write + 0x00000000 + + + TRACEPORTSPEED + Speed of Trace Port clock. Note that the TRACECLK pin output will be divided again by two from the Trace Port clock. + 0 + 1 + + + 64MHz + Trace Port clock is: 64MHz + 0 + + + 32MHz + Trace Port clock is: 32MHz + 1 + + + 16MHz + Trace Port clock is: 16MHz + 2 + + + 8MHz + Trace Port clock is: 8MHz + 3 + + + + + + + + + DCNF_NS + Domain configuration management 0 + 0x40000000 + DCNF + + + + 0 + 0x1000 + registers + + DCNF + 0x20 + + + CPUID + CPU ID of this subsystem + 0x420 + read-only + 0x00000000 + + + CPUID + CPU ID + 0 + 7 + + + + + 1 + 0x004 + EXTPERI[%s] + Unspecified + DCNF_EXTPERI + read-write + 0x440 + + PROTECT + Description cluster: Control access for master connected to AMLI master port EXTPERI[n] + 0x000 + read-write + + + SLAVE0 + Control access to slave 0 of master EXTPERI[n] + 0 + 0 + + + Allowed + Access to slave is allowed + 0 + + + Blocked + Access to slave is blocked + 1 + + + + + + + + 1 + 0x004 + EXTRAM[%s] + Unspecified + DCNF_EXTRAM + read-write + 0x460 + + PROTECT + Description cluster: Control access from master connected to AMLI master port EXTRAM[n] + 0x000 + read-write + + + SLAVE0 + Control access to slave 0 of master EXTRAM[n] + 0 + 0 + + + Allowed + Access to slave is allowed + 0 + + + Blocked + Access to slave is blocked + 1 + + + + + SLAVE1 + Control access to slave 1 of master EXTRAM[n] + 1 + 1 + + + Allowed + Access to slave is allowed + 0 + + + Blocked + Access to slave is blocked + 1 + + + + + SLAVE2 + Control access to slave 2 of master EXTRAM[n] + 2 + 2 + + + Allowed + Access to slave is allowed + 0 + + + Blocked + Access to slave is blocked + 1 + + + + + SLAVE3 + Control access to slave 3 of master EXTRAM[n] + 3 + 3 + + + Allowed + Access to slave is allowed + 0 + + + Blocked + Access to slave is blocked + 1 + + + + + SLAVE4 + Control access to slave 4 of master EXTRAM[n] + 4 + 4 + + + Allowed + Access to slave is allowed + 0 + + + Blocked + Access to slave is blocked + 1 + + + + + SLAVE5 + Control access to slave 5 of master EXTRAM[n] + 5 + 5 + + + Allowed + Access to slave is allowed + 0 + + + Blocked + Access to slave is blocked + 1 + + + + + SLAVE6 + Control access to slave 6 of master EXTRAM[n] + 6 + 6 + + + Allowed + Access to slave is allowed + 0 + + + Blocked + Access to slave is blocked + 1 + + + + + SLAVE7 + Control access to slave 7 of master EXTRAM[n] + 7 + 7 + + + Allowed + Access to slave is allowed + 0 + + + Blocked + Access to slave is blocked + 1 + + + + + + + + 1 + 0x004 + EXTCODE[%s] + Unspecified + DCNF_EXTCODE + read-write + 0x480 + + PROTECT + Description cluster: Control access from master connected to AMLI master port EXTCODE[n] + 0x000 + read-write + + + SLAVE0 + Control access to slave 0 of master EXTCODE[n] + 0 + 0 + + + Allowed + Access to slave is allowed + 0 + + + Blocked + Access to slave is blocked + 1 + + + + + + + + + + FPU_NS + FPU control peripheral 0 + 0x40000000 + DCNF_NS + FPU + + + + 0 + 0x1000 + registers + + + FPU + 0 + + FPU + 0x20 + + + EVENTS_INVALIDOPERATION + An FPUIOC exception triggered by an invalid operation has occurred in the FPU + 0x100 + read-write + + + EVENTS_INVALIDOPERATION + An FPUIOC exception triggered by an invalid operation has occurred in the FPU + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DIVIDEBYZERO + An FPUDZC exception triggered by a floating-point divide-by-zero operation has occurred in the FPU + 0x104 + read-write + + + EVENTS_DIVIDEBYZERO + An FPUDZC exception triggered by a floating-point divide-by-zero operation has occurred in the FPU + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_OVERFLOW + An FPUOFC exception triggered by a floating-point overflow has occurred in the FPU + 0x108 + read-write + + + EVENTS_OVERFLOW + An FPUOFC exception triggered by a floating-point overflow has occurred in the FPU + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_UNDERFLOW + An FPUUFC exception triggered by a floating-point underflow has occurred in the FPU + 0x10C + read-write + + + EVENTS_UNDERFLOW + An FPUUFC exception triggered by a floating-point underflow has occurred in the FPU + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_INEXACT + An FPUIXC exception triggered by an inexact floating-point operation has occurred in the FPU + 0x110 + read-write + + + EVENTS_INEXACT + An FPUIXC exception triggered by an inexact floating-point operation has occurred in the FPU + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DENORMALINPUT + An FPUIDC exception triggered by a denormal floating-point input has occurred in the FPU + 0x114 + read-write + + + EVENTS_DENORMALINPUT + An FPUIDC exception triggered by a denormal floating-point input has occurred in the FPU + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + INVALIDOPERATION + Enable or disable interrupt for event INVALIDOPERATION + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + DIVIDEBYZERO + Enable or disable interrupt for event DIVIDEBYZERO + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + OVERFLOW + Enable or disable interrupt for event OVERFLOW + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + UNDERFLOW + Enable or disable interrupt for event UNDERFLOW + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + INEXACT + Enable or disable interrupt for event INEXACT + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + DENORMALINPUT + Enable or disable interrupt for event DENORMALINPUT + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + INVALIDOPERATION + Write '1' to enable interrupt for event INVALIDOPERATION + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DIVIDEBYZERO + Write '1' to enable interrupt for event DIVIDEBYZERO + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + OVERFLOW + Write '1' to enable interrupt for event OVERFLOW + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + UNDERFLOW + Write '1' to enable interrupt for event UNDERFLOW + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + INEXACT + Write '1' to enable interrupt for event INEXACT + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DENORMALINPUT + Write '1' to enable interrupt for event DENORMALINPUT + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + INVALIDOPERATION + Write '1' to disable interrupt for event INVALIDOPERATION + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DIVIDEBYZERO + Write '1' to disable interrupt for event DIVIDEBYZERO + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + OVERFLOW + Write '1' to disable interrupt for event OVERFLOW + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + UNDERFLOW + Write '1' to disable interrupt for event UNDERFLOW + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + INEXACT + Write '1' to disable interrupt for event INEXACT + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DENORMALINPUT + Write '1' to disable interrupt for event DENORMALINPUT + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + + + DCNF_S + Domain configuration management 1 + 0x50000000 + + + + + FPU_S + FPU control peripheral 1 + 0x50000000 + DCNF_S + + + + FPU + 0 + + + + CACHE_S + Cache + 0x50001000 + CACHE + + + + 0 + 0x1000 + registers + + + CACHE + 1 + + CACHE + 0x20 + + + 2 + 0x020 + PROFILING[%s] + Unspecified + CACHE_PROFILING + read-write + 0x400 + + IHIT + Description cluster: Instruction fetch cache hit counter for cache region n, where n=0 means Flash and n=1 means XIP. + 0x000 + read-only + + + HITS + Number of instruction cache hits + 0 + 31 + + + + + IMISS + Description cluster: Instruction fetch cache miss counter for cache region n, where n=0 means Flash and n=1 means XIP. + 0x004 + read-only + + + MISSES + Number of instruction cache misses + 0 + 31 + + + + + DHIT + Description cluster: Data fetch cache hit counter for cache region n, where n=0 means Flash and n=1 means XIP. + 0x008 + read-only + + + HITS + Number of data cache hits + 0 + 31 + + + + + DMISS + Description cluster: Data fetch cache miss counter for cache region n, where n=0 means Flash and n=1 means XIP. + 0x00C + read-only + + + MISSES + Number of data cache misses + 0 + 31 + + + + + + ENABLE + Enable cache. + 0x500 + read-write + + + ENABLE + Enable cache + 0 + 0 + + + Disabled + Disable cache + 0 + + + Enabled + Enable cache + 1 + + + + + + + INVALIDATE + Invalidate the cache. + 0x504 + write-only + + + INVALIDATE + Invalidate the cache + 0 + 0 + + + Invalidate + Invalidate the cache + 1 + + + + + + + ERASE + Erase the cache. + 0x508 + write-only + + + ERASE + Erase the cache + 0 + 0 + + + Erase + Erase cache + 1 + + + + + + + PROFILINGENABLE + Enable the profiling counters. + 0x50C + read-write + + + ENABLE + Enable the profiling counters + 0 + 0 + + + Disable + Disable profiling + 0 + + + Enable + Enable profiling + 1 + + + + + + + PROFILINGCLEAR + Clear the profiling counters. + 0x510 + write-only + + + CLEAR + Clearing the profiling counters + 0 + 0 + + + Clear + Clear the profiling counters + 1 + + + + + + + MODE + Cache mode. Switching from Cache to Ram mode causes the RAM to be cleared. Switching from RAM to Cache mode causes the cache to be invalidated. + 0x514 + read-write + + + MODE + Cache mode + 0 + 0 + + + Cache + Cache mode + 0 + + + Ram + RAM mode + 1 + + + + + + + DEBUGLOCK + Lock debug mode. + 0x518 + read-writeOnce + + + DEBUGLOCK + Lock debug mode + 0 + 0 + + + Unlocked + Debug mode unlocked + 0 + + + Locked + Debug mode locked + 1 + + + + + + + ERASESTATUS + Cache erase status. + 0x51C + read-write + + + ERASESTATUS + Cache erase status + 0 + 0 + + + Idle + Erase is not complete or hasn't started + 0 + + + Finished + Cache erase is finished + 1 + + + + + + + WRITELOCK + Lock cache updates. Prevents updating of cache content on cache misses, but will continue to lookup instruction/data fetches in content already present in the cache. Ignored in RAM mode. + 0x520 + read-write + + + WRITELOCK + Lock cache updates + 0 + 0 + + + Unlocked + Cache updates unlocked + 0 + + + Locked + Cache updates locked + 1 + + + + + + + + + SPU_S + System protection unit + 0x50003000 + SPU + + + + 0 + 0x1000 + registers + + + SPU + 3 + + SPU + 0x20 + + + EVENTS_RAMACCERR + A security violation has been detected for the RAM memory space + 0x100 + read-write + + + EVENTS_RAMACCERR + A security violation has been detected for the RAM memory space + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_FLASHACCERR + A security violation has been detected for the flash memory space + 0x104 + read-write + + + EVENTS_FLASHACCERR + A security violation has been detected for the flash memory space + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_PERIPHACCERR + A security violation has been detected on one or several peripherals + 0x108 + read-write + + + EVENTS_PERIPHACCERR + A security violation has been detected on one or several peripherals + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_RAMACCERR + Publish configuration for event RAMACCERR + 0x180 + read-write + + + CHIDX + DPPI channel that event RAMACCERR will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_FLASHACCERR + Publish configuration for event FLASHACCERR + 0x184 + read-write + + + CHIDX + DPPI channel that event FLASHACCERR will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_PERIPHACCERR + Publish configuration for event PERIPHACCERR + 0x188 + read-write + + + CHIDX + DPPI channel that event PERIPHACCERR will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + RAMACCERR + Enable or disable interrupt for event RAMACCERR + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + FLASHACCERR + Enable or disable interrupt for event FLASHACCERR + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + PERIPHACCERR + Enable or disable interrupt for event PERIPHACCERR + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + RAMACCERR + Write '1' to enable interrupt for event RAMACCERR + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + FLASHACCERR + Write '1' to enable interrupt for event FLASHACCERR + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PERIPHACCERR + Write '1' to enable interrupt for event PERIPHACCERR + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + RAMACCERR + Write '1' to disable interrupt for event RAMACCERR + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + FLASHACCERR + Write '1' to disable interrupt for event FLASHACCERR + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PERIPHACCERR + Write '1' to disable interrupt for event PERIPHACCERR + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + CAP + Show implemented features for the current device + 0x400 + read-only + 0x00000001 + + + TZM + Show Arm TrustZone status + 0 + 0 + + + NotAvailable + Arm TrustZone support not available + 0 + + + Enabled + Arm TrustZone support is available + 1 + + + + + + + CPULOCK + Configure bits to lock down CPU features at runtime + 0x404 + read-write + 0x00000000 + oneToSet + + + LOCKSVTAIRCR + Write '1' to prevent updating the secure interrupt configuration until the next reset + 0 + 0 + + + Locked + Disables writes to the VTOR_S, AIRCR.PRIS, and AIRCR.BFHFNMINS registers + 1 + + + Unlocked + These registers can be updated + 0 + + + + + LOCKNSVTOR + Write '1' to prevent updating the non-secure vector table base address until the next reset + 1 + 1 + + + Locked + The address of the non-secure vector table is locked + 1 + + + Unlocked + The address of the non-secure vector table can be updated + 0 + + + + + LOCKSMPU + Write '1' to prevent updating the secure MPU regions until the next reset + 2 + 2 + + + Locked + Disables writes to the MPU_CTRL, MPU_RNR, MPU_RBAR, MPU_RLAR, MPU_RBAR_An and MPU_RLAR_An from software or from a debug agent connected to the processor in Secure state + 1 + + + Unlocked + These registers can be updated + 0 + + + + + LOCKNSMPU + Write '1' to prevent updating the Non-secure MPU regions until the next reset + 3 + 3 + + + Locked + Disables writes to the MPU_CTRL_NS, MPU_RNR_NS, MPU_RBAR_NS, MPU_RLAR_NS, MPU_RBAR_A_NSn and MPU_RLAR_A_NSn from software or from a debug agent connected to the processor + 1 + + + Unlocked + These registers can be updated + 0 + + + + + LOCKSAU + Write '1' to prevent updating the secure SAU regions until the next reset + 4 + 4 + + + Locked + Disables writes to the SAU_CTRL, SAU_RNR, SAU_RBAR and SAU_RLAR registers from software or from a debug agent connected to the processor + 1 + + + Unlocked + These registers can be updated + 0 + + + + + + + 1 + 0x004 + EXTDOMAIN[%s] + Unspecified + SPU_EXTDOMAIN + read-write + 0x440 + + PERM + Description cluster: Access for bus access generated from the external domain n List capabilities of the external domain n + 0x000 + read-write + 0x00000002 + + + SECUREMAPPING + Define configuration capabilities for TrustZone Cortex-M secure attribute + 0 + 1 + read-only + + + NonSecure + The bus access from this external domain always have the non-secure attribute set + 0 + + + Secure + The bus access from this external domain always have the secure attribute set + 1 + + + UserSelectable + Non-secure or secure attribute for bus access from this domain is defined by the EXTDOMAIN[n].PERM register + 2 + + + + + SECATTR + Peripheral security mapping + 4 + 4 + + + NonSecure + Bus accesses from this domain have the non-secure attribute set + 0 + + + Secure + Bus accesses from this domain have secure attribute set + 1 + + + + + LOCK + 8 + 8 + + + Unlocked + This register can be updated + 0 + + + Locked + The content of this register can't be changed until the next reset + 1 + + + + + + + + 1 + 0x008 + DPPI[%s] + Unspecified + SPU_DPPI + read-write + 0x480 + + PERM + Description cluster: Select between secure and non-secure attribute for the DPPI channels + 0x000 + read-write + 0xFFFFFFFF + + + CHANNEL0 + Select secure attribute + 0 + 0 + + + Secure + Channel 0 has its secure attribute set + 1 + + + NonSecure + Channel 0 has its non-secure attribute set + 0 + + + + + CHANNEL1 + Select secure attribute + 1 + 1 + + + Secure + Channel 1 has its secure attribute set + 1 + + + NonSecure + Channel 1 has its non-secure attribute set + 0 + + + + + CHANNEL2 + Select secure attribute + 2 + 2 + + + Secure + Channel 2 has its secure attribute set + 1 + + + NonSecure + Channel 2 has its non-secure attribute set + 0 + + + + + CHANNEL3 + Select secure attribute + 3 + 3 + + + Secure + Channel 3 has its secure attribute set + 1 + + + NonSecure + Channel 3 has its non-secure attribute set + 0 + + + + + CHANNEL4 + Select secure attribute + 4 + 4 + + + Secure + Channel 4 has its secure attribute set + 1 + + + NonSecure + Channel 4 has its non-secure attribute set + 0 + + + + + CHANNEL5 + Select secure attribute + 5 + 5 + + + Secure + Channel 5 has its secure attribute set + 1 + + + NonSecure + Channel 5 has its non-secure attribute set + 0 + + + + + CHANNEL6 + Select secure attribute + 6 + 6 + + + Secure + Channel 6 has its secure attribute set + 1 + + + NonSecure + Channel 6 has its non-secure attribute set + 0 + + + + + CHANNEL7 + Select secure attribute + 7 + 7 + + + Secure + Channel 7 has its secure attribute set + 1 + + + NonSecure + Channel 7 has its non-secure attribute set + 0 + + + + + CHANNEL8 + Select secure attribute + 8 + 8 + + + Secure + Channel 8 has its secure attribute set + 1 + + + NonSecure + Channel 8 has its non-secure attribute set + 0 + + + + + CHANNEL9 + Select secure attribute + 9 + 9 + + + Secure + Channel 9 has its secure attribute set + 1 + + + NonSecure + Channel 9 has its non-secure attribute set + 0 + + + + + CHANNEL10 + Select secure attribute + 10 + 10 + + + Secure + Channel 10 has its secure attribute set + 1 + + + NonSecure + Channel 10 has its non-secure attribute set + 0 + + + + + CHANNEL11 + Select secure attribute + 11 + 11 + + + Secure + Channel 11 has its secure attribute set + 1 + + + NonSecure + Channel 11 has its non-secure attribute set + 0 + + + + + CHANNEL12 + Select secure attribute + 12 + 12 + + + Secure + Channel 12 has its secure attribute set + 1 + + + NonSecure + Channel 12 has its non-secure attribute set + 0 + + + + + CHANNEL13 + Select secure attribute + 13 + 13 + + + Secure + Channel 13 has its secure attribute set + 1 + + + NonSecure + Channel 13 has its non-secure attribute set + 0 + + + + + CHANNEL14 + Select secure attribute + 14 + 14 + + + Secure + Channel 14 has its secure attribute set + 1 + + + NonSecure + Channel 14 has its non-secure attribute set + 0 + + + + + CHANNEL15 + Select secure attribute + 15 + 15 + + + Secure + Channel 15 has its secure attribute set + 1 + + + NonSecure + Channel 15 has its non-secure attribute set + 0 + + + + + CHANNEL16 + Select secure attribute + 16 + 16 + + + Secure + Channel 16 has its secure attribute set + 1 + + + NonSecure + Channel 16 has its non-secure attribute set + 0 + + + + + CHANNEL17 + Select secure attribute + 17 + 17 + + + Secure + Channel 17 has its secure attribute set + 1 + + + NonSecure + Channel 17 has its non-secure attribute set + 0 + + + + + CHANNEL18 + Select secure attribute + 18 + 18 + + + Secure + Channel 18 has its secure attribute set + 1 + + + NonSecure + Channel 18 has its non-secure attribute set + 0 + + + + + CHANNEL19 + Select secure attribute + 19 + 19 + + + Secure + Channel 19 has its secure attribute set + 1 + + + NonSecure + Channel 19 has its non-secure attribute set + 0 + + + + + CHANNEL20 + Select secure attribute + 20 + 20 + + + Secure + Channel 20 has its secure attribute set + 1 + + + NonSecure + Channel 20 has its non-secure attribute set + 0 + + + + + CHANNEL21 + Select secure attribute + 21 + 21 + + + Secure + Channel 21 has its secure attribute set + 1 + + + NonSecure + Channel 21 has its non-secure attribute set + 0 + + + + + CHANNEL22 + Select secure attribute + 22 + 22 + + + Secure + Channel 22 has its secure attribute set + 1 + + + NonSecure + Channel 22 has its non-secure attribute set + 0 + + + + + CHANNEL23 + Select secure attribute + 23 + 23 + + + Secure + Channel 23 has its secure attribute set + 1 + + + NonSecure + Channel 23 has its non-secure attribute set + 0 + + + + + CHANNEL24 + Select secure attribute + 24 + 24 + + + Secure + Channel 24 has its secure attribute set + 1 + + + NonSecure + Channel 24 has its non-secure attribute set + 0 + + + + + CHANNEL25 + Select secure attribute + 25 + 25 + + + Secure + Channel 25 has its secure attribute set + 1 + + + NonSecure + Channel 25 has its non-secure attribute set + 0 + + + + + CHANNEL26 + Select secure attribute + 26 + 26 + + + Secure + Channel 26 has its secure attribute set + 1 + + + NonSecure + Channel 26 has its non-secure attribute set + 0 + + + + + CHANNEL27 + Select secure attribute + 27 + 27 + + + Secure + Channel 27 has its secure attribute set + 1 + + + NonSecure + Channel 27 has its non-secure attribute set + 0 + + + + + CHANNEL28 + Select secure attribute + 28 + 28 + + + Secure + Channel 28 has its secure attribute set + 1 + + + NonSecure + Channel 28 has its non-secure attribute set + 0 + + + + + CHANNEL29 + Select secure attribute + 29 + 29 + + + Secure + Channel 29 has its secure attribute set + 1 + + + NonSecure + Channel 29 has its non-secure attribute set + 0 + + + + + CHANNEL30 + Select secure attribute + 30 + 30 + + + Secure + Channel 30 has its secure attribute set + 1 + + + NonSecure + Channel 30 has its non-secure attribute set + 0 + + + + + CHANNEL31 + Select secure attribute + 31 + 31 + + + Secure + Channel 31 has its secure attribute set + 1 + + + NonSecure + Channel 31 has its non-secure attribute set + 0 + + + + + + + LOCK + Description cluster: Prevent further modification of the corresponding PERM register + 0x004 + read-write + 0x00000000 + + + LOCK + 0 + 0 + + + Locked + DPPI[n].PERM register can't be changed until next reset + 1 + + + Unlocked + DPPI[n].PERM register content can be changed + 0 + + + + + + + + 2 + 0x008 + GPIOPORT[%s] + Unspecified + SPU_GPIOPORT + read-write + 0x4C0 + + PERM + Description cluster: Select between secure and non-secure attribute for pins 0 to 31 of port n + 0x000 + read-write + 0xFFFFFFFF + + + PIN0 + Select secure attribute attribute for PIN 0. + 0 + 0 + + + Secure + Pin 0 has its secure attribute set + 1 + + + NonSecure + Pin 0 has its non-secure attribute set + 0 + + + + + PIN1 + Select secure attribute attribute for PIN 1. + 1 + 1 + + + Secure + Pin 1 has its secure attribute set + 1 + + + NonSecure + Pin 1 has its non-secure attribute set + 0 + + + + + PIN2 + Select secure attribute attribute for PIN 2. + 2 + 2 + + + Secure + Pin 2 has its secure attribute set + 1 + + + NonSecure + Pin 2 has its non-secure attribute set + 0 + + + + + PIN3 + Select secure attribute attribute for PIN 3. + 3 + 3 + + + Secure + Pin 3 has its secure attribute set + 1 + + + NonSecure + Pin 3 has its non-secure attribute set + 0 + + + + + PIN4 + Select secure attribute attribute for PIN 4. + 4 + 4 + + + Secure + Pin 4 has its secure attribute set + 1 + + + NonSecure + Pin 4 has its non-secure attribute set + 0 + + + + + PIN5 + Select secure attribute attribute for PIN 5. + 5 + 5 + + + Secure + Pin 5 has its secure attribute set + 1 + + + NonSecure + Pin 5 has its non-secure attribute set + 0 + + + + + PIN6 + Select secure attribute attribute for PIN 6. + 6 + 6 + + + Secure + Pin 6 has its secure attribute set + 1 + + + NonSecure + Pin 6 has its non-secure attribute set + 0 + + + + + PIN7 + Select secure attribute attribute for PIN 7. + 7 + 7 + + + Secure + Pin 7 has its secure attribute set + 1 + + + NonSecure + Pin 7 has its non-secure attribute set + 0 + + + + + PIN8 + Select secure attribute attribute for PIN 8. + 8 + 8 + + + Secure + Pin 8 has its secure attribute set + 1 + + + NonSecure + Pin 8 has its non-secure attribute set + 0 + + + + + PIN9 + Select secure attribute attribute for PIN 9. + 9 + 9 + + + Secure + Pin 9 has its secure attribute set + 1 + + + NonSecure + Pin 9 has its non-secure attribute set + 0 + + + + + PIN10 + Select secure attribute attribute for PIN 10. + 10 + 10 + + + Secure + Pin 10 has its secure attribute set + 1 + + + NonSecure + Pin 10 has its non-secure attribute set + 0 + + + + + PIN11 + Select secure attribute attribute for PIN 11. + 11 + 11 + + + Secure + Pin 11 has its secure attribute set + 1 + + + NonSecure + Pin 11 has its non-secure attribute set + 0 + + + + + PIN12 + Select secure attribute attribute for PIN 12. + 12 + 12 + + + Secure + Pin 12 has its secure attribute set + 1 + + + NonSecure + Pin 12 has its non-secure attribute set + 0 + + + + + PIN13 + Select secure attribute attribute for PIN 13. + 13 + 13 + + + Secure + Pin 13 has its secure attribute set + 1 + + + NonSecure + Pin 13 has its non-secure attribute set + 0 + + + + + PIN14 + Select secure attribute attribute for PIN 14. + 14 + 14 + + + Secure + Pin 14 has its secure attribute set + 1 + + + NonSecure + Pin 14 has its non-secure attribute set + 0 + + + + + PIN15 + Select secure attribute attribute for PIN 15. + 15 + 15 + + + Secure + Pin 15 has its secure attribute set + 1 + + + NonSecure + Pin 15 has its non-secure attribute set + 0 + + + + + PIN16 + Select secure attribute attribute for PIN 16. + 16 + 16 + + + Secure + Pin 16 has its secure attribute set + 1 + + + NonSecure + Pin 16 has its non-secure attribute set + 0 + + + + + PIN17 + Select secure attribute attribute for PIN 17. + 17 + 17 + + + Secure + Pin 17 has its secure attribute set + 1 + + + NonSecure + Pin 17 has its non-secure attribute set + 0 + + + + + PIN18 + Select secure attribute attribute for PIN 18. + 18 + 18 + + + Secure + Pin 18 has its secure attribute set + 1 + + + NonSecure + Pin 18 has its non-secure attribute set + 0 + + + + + PIN19 + Select secure attribute attribute for PIN 19. + 19 + 19 + + + Secure + Pin 19 has its secure attribute set + 1 + + + NonSecure + Pin 19 has its non-secure attribute set + 0 + + + + + PIN20 + Select secure attribute attribute for PIN 20. + 20 + 20 + + + Secure + Pin 20 has its secure attribute set + 1 + + + NonSecure + Pin 20 has its non-secure attribute set + 0 + + + + + PIN21 + Select secure attribute attribute for PIN 21. + 21 + 21 + + + Secure + Pin 21 has its secure attribute set + 1 + + + NonSecure + Pin 21 has its non-secure attribute set + 0 + + + + + PIN22 + Select secure attribute attribute for PIN 22. + 22 + 22 + + + Secure + Pin 22 has its secure attribute set + 1 + + + NonSecure + Pin 22 has its non-secure attribute set + 0 + + + + + PIN23 + Select secure attribute attribute for PIN 23. + 23 + 23 + + + Secure + Pin 23 has its secure attribute set + 1 + + + NonSecure + Pin 23 has its non-secure attribute set + 0 + + + + + PIN24 + Select secure attribute attribute for PIN 24. + 24 + 24 + + + Secure + Pin 24 has its secure attribute set + 1 + + + NonSecure + Pin 24 has its non-secure attribute set + 0 + + + + + PIN25 + Select secure attribute attribute for PIN 25. + 25 + 25 + + + Secure + Pin 25 has its secure attribute set + 1 + + + NonSecure + Pin 25 has its non-secure attribute set + 0 + + + + + PIN26 + Select secure attribute attribute for PIN 26. + 26 + 26 + + + Secure + Pin 26 has its secure attribute set + 1 + + + NonSecure + Pin 26 has its non-secure attribute set + 0 + + + + + PIN27 + Select secure attribute attribute for PIN 27. + 27 + 27 + + + Secure + Pin 27 has its secure attribute set + 1 + + + NonSecure + Pin 27 has its non-secure attribute set + 0 + + + + + PIN28 + Select secure attribute attribute for PIN 28. + 28 + 28 + + + Secure + Pin 28 has its secure attribute set + 1 + + + NonSecure + Pin 28 has its non-secure attribute set + 0 + + + + + PIN29 + Select secure attribute attribute for PIN 29. + 29 + 29 + + + Secure + Pin 29 has its secure attribute set + 1 + + + NonSecure + Pin 29 has its non-secure attribute set + 0 + + + + + PIN30 + Select secure attribute attribute for PIN 30. + 30 + 30 + + + Secure + Pin 30 has its secure attribute set + 1 + + + NonSecure + Pin 30 has its non-secure attribute set + 0 + + + + + PIN31 + Select secure attribute attribute for PIN 31. + 31 + 31 + + + Secure + Pin 31 has its secure attribute set + 1 + + + NonSecure + Pin 31 has its non-secure attribute set + 0 + + + + + + + LOCK + Description cluster: Prevent further modification of the corresponding PERM register + 0x004 + read-write + 0x00000000 + + + LOCK + 0 + 0 + + + Locked + GPIOPORT[n].PERM register can't be changed until next reset + 1 + + + Unlocked + GPIOPORT[n].PERM register content can be changed + 0 + + + + + + + + 2 + 0x008 + FLASHNSC[%s] + Unspecified + SPU_FLASHNSC + read-write + 0x500 + + REGION + Description cluster: Define which flash region can contain the non-secure callable (NSC) region n + 0x000 + read-write + 0x00000000 + + + REGION + Region number + 0 + 5 + + + LOCK + 8 + 8 + + + Unlocked + This register can be updated + 0 + + + Locked + The content of this register can't be changed until the next reset + 1 + + + + + + + SIZE + Description cluster: Define the size of the non-secure callable (NSC) region n + 0x004 + read-write + 0x00000000 + + + SIZE + Size of the non-secure callable (NSC) region n + 0 + 3 + + + Disabled + The region n is not defined as a non-secure callable region. Normal security attributes (secure or non-secure) are enforced. + 0 + + + 32 + The region n is defined as non-secure callable with size 32 bytes + 1 + + + 64 + The region n is defined as non-secure callable with size 64 bytes + 2 + + + 128 + The region n is defined as non-secure callable with size 128 bytes + 3 + + + 256 + The region n is defined as non-secure callable with size 256 bytes + 4 + + + 512 + The region n is defined as non-secure callable with size 512 bytes + 5 + + + 1024 + The region n is defined as non-secure callable with size 1024 bytes + 6 + + + 2048 + The region n is defined as non-secure callable with size 2048 bytes + 7 + + + 4096 + The region n is defined as non-secure callable with size 4096 bytes + 8 + + + + + LOCK + 8 + 8 + + + Unlocked + This register can be updated + 0 + + + Locked + The content of this register can't be changed until the next reset + 1 + + + + + + + + 2 + 0x008 + RAMNSC[%s] + Unspecified + SPU_RAMNSC + read-write + 0x540 + + REGION + Description cluster: Define which RAM region can contain the non-secure callable (NSC) region n + 0x000 + read-write + 0x00000000 + + + REGION + Region number + 0 + 5 + + + LOCK + 8 + 8 + + + Unlocked + This register can be updated + 0 + + + Locked + The content of this register can't be changed until the next reset + 1 + + + + + + + SIZE + Description cluster: Define the size of the non-secure callable (NSC) region n + 0x004 + read-write + 0x00000000 + + + SIZE + Size of the non-secure callable (NSC) region n + 0 + 3 + + + Disabled + The region n is not defined as a non-secure callable region. Normal security attributes (secure or non-secure) are enforced. + 0 + + + 32 + The region n is defined as non-secure callable with size 32 bytes + 1 + + + 64 + The region n is defined as non-secure callable with size 64 bytes + 2 + + + 128 + The region n is defined as non-secure callable with size 128 bytes + 3 + + + 256 + The region n is defined as non-secure callable with size 256 bytes + 4 + + + 512 + The region n is defined as non-secure callable with size 512 bytes + 5 + + + 1024 + The region n is defined as non-secure callable with size 1024 bytes + 6 + + + 2048 + The region n is defined as non-secure callable with size 2048 bytes + 7 + + + 4096 + The region n is defined as non-secure callable with size 4096 bytes + 8 + + + + + LOCK + 8 + 8 + + + Unlocked + This register can be updated + 0 + + + Locked + The content of this register can't be changed until the next reset + 1 + + + + + + + + 64 + 0x004 + FLASHREGION[%s] + Unspecified + SPU_FLASHREGION + read-write + 0x600 + + PERM + Description cluster: Access permissions for flash region n + 0x000 + read-write + 0x00000017 + + + EXECUTE + Configure instruction fetch permissions from flash region n + 0 + 0 + + + Enable + Allow instruction fetches from flash region n + 1 + + + Disable + Block instruction fetches from flash region n + 0 + + + + + WRITE + Configure write permission for flash region n + 1 + 1 + + + Enable + Allow write operation to region n + 1 + + + Disable + Block write operation to region n + 0 + + + + + READ + Configure read permissions for flash region n + 2 + 2 + + + Enable + Allow read operation from flash region n + 1 + + + Disable + Block read operation from flash region n + 0 + + + + + SECATTR + Security attribute for flash region n + 4 + 4 + + + Non_Secure + Flash region n security attribute is non-secure + 0 + + + Secure + Flash region n security attribute is secure + 1 + + + + + LOCK + 8 + 8 + + + Unlocked + This register can be updated + 0 + + + Locked + The content of this register can't be changed until the next reset + 1 + + + + + + + + 64 + 0x004 + RAMREGION[%s] + Unspecified + SPU_RAMREGION + read-write + 0x700 + + PERM + Description cluster: Access permissions for RAM region n + 0x000 + read-write + 0x00000017 + + + EXECUTE + Configure instruction fetch permissions from RAM region n + 0 + 0 + + + Enable + Allow instruction fetches from RAM region n + 1 + + + Disable + Block instruction fetches from RAM region n + 0 + + + + + WRITE + Configure write permission for RAM region n + 1 + 1 + + + Enable + Allow write operation to RAM region n + 1 + + + Disable + Block write operation to RAM region n + 0 + + + + + READ + Configure read permissions for RAM region n + 2 + 2 + + + Enable + Allow read operation from RAM region n + 1 + + + Disable + Block read operation from RAM region n + 0 + + + + + SECATTR + Security attribute for RAM region n + 4 + 4 + + + Non_Secure + RAM region n security attribute is non-secure + 0 + + + Secure + RAM region n security attribute is secure + 1 + + + + + LOCK + 8 + 8 + + + Unlocked + This register can be updated + 0 + + + Locked + The content of this register can't be changed until the next reset + 1 + + + + + + + + 256 + 0x004 + PERIPHID[%s] + Unspecified + SPU_PERIPHID + read-write + 0x800 + + PERM + Description cluster: List capabilities and access permissions for the peripheral with ID n + 0x000 + read-write + 0x00000012 + + + SECUREMAPPING + Define configuration capabilities for Arm TrustZone Cortex-M secure attribute + 0 + 1 + read-only + + + NonSecure + This peripheral is always accessible as a non-secure peripheral + 0 + + + Secure + This peripheral is always accessible as a secure peripheral + 1 + + + UserSelectable + Non-secure or secure attribute for this peripheral is defined by the PERIPHID[n].PERM register + 2 + + + Split + This peripheral implements the split security mechanism. Non-secure or secure attribute for this peripheral is defined by the PERIPHID[n].PERM register. + 3 + + + + + DMA + Indicates if the peripheral has DMA capabilities and if DMA transfer can be assigned to a different security attribute than the peripheral itself + 2 + 3 + read-only + + + NoDMA + Peripheral has no DMA capability + 0 + + + NoSeparateAttribute + Peripheral has DMA and DMA transfers always have the same security attribute as assigned to the peripheral + 1 + + + SeparateAttribute + Peripheral has DMA and DMA transfers can have a different security attribute than the one assigned to the peripheral + 2 + + + + + SECATTR + Peripheral security mapping + 4 + 4 + + + Secure + Peripheral is mapped in secure peripheral address space + 1 + + + NonSecure + If SECUREMAPPING == UserSelectable: Peripheral is mapped in non-secure peripheral address space. If SECUREMAPPING == Split: Peripheral is mapped in non-secure and secure peripheral address space. + 0 + + + + + DMASEC + Security attribution for the DMA transfer + 5 + 5 + + + Secure + DMA transfers initiated by this peripheral have the secure attribute set + 1 + + + NonSecure + DMA transfers initiated by this peripheral have the non-secure attribute set + 0 + + + + + LOCK + 8 + 8 + + + Unlocked + This register can be updated + 0 + + + Locked + The content of this register can't be changed until the next reset + 1 + + + + + PRESENT + Indicate if a peripheral is present with ID n + 31 + 31 + read-only + + + NotPresent + Peripheral is not present + 0 + + + IsPresent + Peripheral is present + 1 + + + + + + + + + + OSCILLATORS_NS + Oscillator control 0 + 0x40004000 + OSCILLATORS + + + + 0 + 0x1000 + registers + + OSCILLATORS + 0x20 + + + XOSC32MCAPS + Programmable capacitance of XC1 and XC2 + 0x5C4 + read-write + + + CAPVALUE + Value representing capacitance, calculated using provided equation + 0 + 4 + + + ENABLE + Enable on-chip capacitors on XC1 and XC2 + 8 + 8 + + + Disabled + Capacitor disabled (use external caps) + 0 + + + Enabled + Capacitor enabled + 1 + + + + + + + XOSC32KI + Unspecified + OSCILLATORS_XOSC32KI + read-write + 0x6C0 + + BYPASS + Enable or disable bypass of LFCLK crystal oscillator with external clock source + 0x000 + read-write + + + BYPASS + Enable or disable bypass of LFCLK crystal oscillator with external clock source + 0 + 0 + + + Disabled + Disable (use with crystal or low-swing external source) + 0 + + + Enabled + Enable (use with rail-to-rail external source) + 1 + + + + + + + INTCAP + Control usage of internal load capacitors + 0x010 + read-write + + + INTCAP + Control usage of internal load capacitors + 0 + 1 + + + External + Use external load capacitors + 0 + + + C6PF + 6 pF internal load capacitance + 1 + + + C7PF + 7 pF internal load capacitance + 2 + + + C9PF + 9 pF internal load capacitance + 3 + + + + + + + + + + REGULATORS_NS + Voltage regulators 0 + 0x40004000 + OSCILLATORS_NS + REGULATORS + + + + 0 + 0x1000 + registers + + REGULATORS + 0x20 + + + MAINREGSTATUS + Main supply status + 0x428 + read-only + 0x00000000 + + + VREGH + VREGH status + 0 + 0 + + + Inactive + Normal voltage mode. Voltage supplied on VDD and VDDH. + 0 + + + Active + High voltage mode. Voltage supplied on VDDH. + 1 + + + + + + + SYSTEMOFF + System OFF register + 0x500 + write-only + + + SYSTEMOFF + Enable System OFF mode + 0 + 0 + + + Enter + Enable System OFF mode + 1 + + + + + + + POFCON + Power-fail comparator configuration + 0x510 + read-write + + + POF + Enable or disable power-fail comparator + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + THRESHOLD + Power-fail comparator threshold setting + 1 + 4 + + + V19 + Set threshold to 1.9 V + 6 + + + V20 + Set threshold to 2.0 V + 7 + + + V21 + Set threshold to 2.1 V + 8 + + + V22 + Set threshold to 2.2 V + 9 + + + V23 + Set threshold to 2.3 V + 10 + + + V24 + Set threshold to 2.4 V + 11 + + + V25 + Set threshold to 2.5 V + 12 + + + V26 + Set threshold to 2.6 V + 13 + + + V27 + Set threshold to 2.7 V + 14 + + + V28 + Set threshold to 2.8 V + 15 + + + + + THRESHOLDVDDH + Power-fail comparator threshold setting for voltage supply on VDDH + 8 + 11 + + + V27 + Set threshold to 2.7 V + 0 + + + V28 + Set threshold to 2.8 V + 1 + + + V29 + Set threshold to 2.9 V + 2 + + + V30 + Set threshold to 3.0 V + 3 + + + V31 + Set threshold to 3.1 V + 4 + + + V32 + Set threshold to 3.2 V + 5 + + + V33 + Set threshold to 3.3 V + 6 + + + V34 + Set threshold to 3.4 V + 7 + + + V35 + Set threshold to 3.5 V + 8 + + + V36 + Set threshold to 3.6 V + 9 + + + V37 + Set threshold to 3.7 V + 10 + + + V38 + Set threshold to 3.8 V + 11 + + + V39 + Set threshold to 3.9 V + 12 + + + V40 + Set threshold to 4.0 V + 13 + + + V41 + Set threshold to 4.1 V + 14 + + + V42 + Set threshold to 4.2 V + 15 + + + + + + + VREGMAIN + Unspecified + REGULATORS_VREGMAIN + read-write + 0x704 + + DCDCEN + DC/DC enable register for VREGMAIN + 0x000 + read-write + 0x00000000 + + + DCDCEN + Enable or disable DC/DC converter + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + + VREGRADIO + Unspecified + REGULATORS_VREGRADIO + read-write + 0x900 + + DCDCEN + DC/DC enable register for VREGRADIO + 0x004 + read-write + + + DCDCEN + Enable or disable DC/DC converter + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + + VREGH + Unspecified + REGULATORS_VREGH + read-write + 0xB00 + + DCDCEN + DC/DC enable register for VREGH + 0x000 + read-write + + + DCDCEN + Enable or disable DC/DC converter + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + + + + OSCILLATORS_S + Oscillator control 1 + 0x50004000 + + + + + REGULATORS_S + Voltage regulators 1 + 0x50004000 + OSCILLATORS_S + + + + + CLOCK_NS + Clock management 0 + 0x40005000 + CLOCK + + + + 0 + 0x1000 + registers + + + CLOCK_POWER + 5 + + CLOCK + 0x20 + + + TASKS_HFCLKSTART + Start HFCLK128M/HFCLK64M source as selected in HFCLKSRC + 0x000 + write-only + + + TASKS_HFCLKSTART + Start HFCLK128M/HFCLK64M source as selected in HFCLKSRC + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_HFCLKSTOP + Stop HFCLK128M/HFCLK64M source + 0x004 + write-only + + + TASKS_HFCLKSTOP + Stop HFCLK128M/HFCLK64M source + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_LFCLKSTART + Start LFCLK source as selected in LFCLKSRC + 0x008 + write-only + + + TASKS_LFCLKSTART + Start LFCLK source as selected in LFCLKSRC + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_LFCLKSTOP + Stop LFCLK source + 0x00C + write-only + + + TASKS_LFCLKSTOP + Stop LFCLK source + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CAL + Start calibration of LFRC oscillator + 0x010 + write-only + + + TASKS_CAL + Start calibration of LFRC oscillator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_HFCLKAUDIOSTART + Start HFCLKAUDIO source + 0x018 + write-only + + + TASKS_HFCLKAUDIOSTART + Start HFCLKAUDIO source + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_HFCLKAUDIOSTOP + Stop HFCLKAUDIO source + 0x01C + write-only + + + TASKS_HFCLKAUDIOSTOP + Stop HFCLKAUDIO source + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_HFCLK192MSTART + Start HFCLK192M source as selected in HFCLK192MSRC + 0x020 + write-only + + + TASKS_HFCLK192MSTART + Start HFCLK192M source as selected in HFCLK192MSRC + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_HFCLK192MSTOP + Stop HFCLK192M source + 0x024 + write-only + + + TASKS_HFCLK192MSTOP + Stop HFCLK192M source + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_HFCLKSTART + Subscribe configuration for task HFCLKSTART + 0x080 + read-write + + + CHIDX + DPPI channel that task HFCLKSTART will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_HFCLKSTOP + Subscribe configuration for task HFCLKSTOP + 0x084 + read-write + + + CHIDX + DPPI channel that task HFCLKSTOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_LFCLKSTART + Subscribe configuration for task LFCLKSTART + 0x088 + read-write + + + CHIDX + DPPI channel that task LFCLKSTART will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_LFCLKSTOP + Subscribe configuration for task LFCLKSTOP + 0x08C + read-write + + + CHIDX + DPPI channel that task LFCLKSTOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_CAL + Subscribe configuration for task CAL + 0x090 + read-write + + + CHIDX + DPPI channel that task CAL will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_HFCLKAUDIOSTART + Subscribe configuration for task HFCLKAUDIOSTART + 0x098 + read-write + + + CHIDX + DPPI channel that task HFCLKAUDIOSTART will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_HFCLKAUDIOSTOP + Subscribe configuration for task HFCLKAUDIOSTOP + 0x09C + read-write + + + CHIDX + DPPI channel that task HFCLKAUDIOSTOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_HFCLK192MSTART + Subscribe configuration for task HFCLK192MSTART + 0x0A0 + read-write + + + CHIDX + DPPI channel that task HFCLK192MSTART will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_HFCLK192MSTOP + Subscribe configuration for task HFCLK192MSTOP + 0x0A4 + read-write + + + CHIDX + DPPI channel that task HFCLK192MSTOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_HFCLKSTARTED + HFCLK128M/HFCLK64M source started + 0x100 + read-write + + + EVENTS_HFCLKSTARTED + HFCLK128M/HFCLK64M source started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_LFCLKSTARTED + LFCLK source started + 0x104 + read-write + + + EVENTS_LFCLKSTARTED + LFCLK source started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DONE + Calibration of LFRC oscillator complete event + 0x11C + read-write + + + EVENTS_DONE + Calibration of LFRC oscillator complete event + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_HFCLKAUDIOSTARTED + HFCLKAUDIO source started + 0x120 + read-write + + + EVENTS_HFCLKAUDIOSTARTED + HFCLKAUDIO source started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_HFCLK192MSTARTED + HFCLK192M source started + 0x124 + read-write + + + EVENTS_HFCLK192MSTARTED + HFCLK192M source started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_HFCLKSTARTED + Publish configuration for event HFCLKSTARTED + 0x180 + read-write + + + CHIDX + DPPI channel that event HFCLKSTARTED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_LFCLKSTARTED + Publish configuration for event LFCLKSTARTED + 0x184 + read-write + + + CHIDX + DPPI channel that event LFCLKSTARTED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_DONE + Publish configuration for event DONE + 0x19C + read-write + + + CHIDX + DPPI channel that event DONE will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_HFCLKAUDIOSTARTED + Publish configuration for event HFCLKAUDIOSTARTED + 0x1A0 + read-write + + + CHIDX + DPPI channel that event HFCLKAUDIOSTARTED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_HFCLK192MSTARTED + Publish configuration for event HFCLK192MSTARTED + 0x1A4 + read-write + + + CHIDX + DPPI channel that event HFCLK192MSTARTED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + HFCLKSTARTED + Enable or disable interrupt for event HFCLKSTARTED + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + LFCLKSTARTED + Enable or disable interrupt for event LFCLKSTARTED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + DONE + Enable or disable interrupt for event DONE + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + HFCLKAUDIOSTARTED + Enable or disable interrupt for event HFCLKAUDIOSTARTED + 8 + 8 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + HFCLK192MSTARTED + Enable or disable interrupt for event HFCLK192MSTARTED + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + HFCLKSTARTED + Write '1' to enable interrupt for event HFCLKSTARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + LFCLKSTARTED + Write '1' to enable interrupt for event LFCLKSTARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DONE + Write '1' to enable interrupt for event DONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + HFCLKAUDIOSTARTED + Write '1' to enable interrupt for event HFCLKAUDIOSTARTED + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + HFCLK192MSTARTED + Write '1' to enable interrupt for event HFCLK192MSTARTED + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + HFCLKSTARTED + Write '1' to disable interrupt for event HFCLKSTARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + LFCLKSTARTED + Write '1' to disable interrupt for event LFCLKSTARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DONE + Write '1' to disable interrupt for event DONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + HFCLKAUDIOSTARTED + Write '1' to disable interrupt for event HFCLKAUDIOSTARTED + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + HFCLK192MSTARTED + Write '1' to disable interrupt for event HFCLK192MSTARTED + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + + + HFCLKSTARTED + Read pending status of interrupt for event HFCLKSTARTED + 0 + 0 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + LFCLKSTARTED + Read pending status of interrupt for event LFCLKSTARTED + 1 + 1 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + DONE + Read pending status of interrupt for event DONE + 7 + 7 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + HFCLKAUDIOSTARTED + Read pending status of interrupt for event HFCLKAUDIOSTARTED + 8 + 8 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + HFCLK192MSTARTED + Read pending status of interrupt for event HFCLK192MSTARTED + 9 + 9 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + + + HFCLKRUN + Status indicating that HFCLKSTART task has been triggered + 0x408 + read-only + + + STATUS + HFCLKSTART task triggered or not + 0 + 0 + + + NotTriggered + Task not triggered + 0 + + + Triggered + Task triggered + 1 + + + + + + + HFCLKSTAT + Status indicating which HFCLK128M/HFCLK64M source is running This register value in any CLOCK instance reflects status only due to configurations/actions in that CLOCK instance. + 0x40C + read-only + + + SRC + Active clock source + 0 + 0 + + + HFINT + Clock source: HFINT - 128 MHz on-chip oscillator + 0 + + + HFXO + Clock source: HFXO - 128 MHz clock derived from external 32 MHz crystal oscillator + 1 + + + + + ALWAYSRUNNING + ALWAYSRUN activated + 4 + 4 + + + NotRunning + Automatic clock control enabled + 0 + + + Running + Oscillator is always running + 1 + + + + + STATE + HFCLK state + 16 + 16 + + + NotRunning + HFCLK not running + 0 + + + Running + HFCLK running + 1 + + + + + + + LFCLKRUN + Status indicating that LFCLKSTART task has been triggered + 0x414 + read-only + + + STATUS + LFCLKSTART task triggered or not + 0 + 0 + + + NotTriggered + Task not triggered + 0 + + + Triggered + Task triggered + 1 + + + + + + + LFCLKSTAT + Status indicating which LFCLK source is running This register value in any CLOCK instance reflects status only due to configurations/actions in that CLOCK instance. + 0x418 + read-only + + + SRC + Active clock source + 0 + 1 + + + LFRC + 32.768 kHz RC oscillator + 1 + + + LFXO + 32.768 kHz crystal oscillator + 2 + + + LFSYNT + 32.768 kHz synthesized from HFCLK + 3 + + + + + ALWAYSRUNNING + ALWAYSRUN activated + 4 + 4 + + + NotRunning + Automatic clock control enabled + 0 + + + Running + Oscillator is always running + 1 + + + + + STATE + LFCLK state + 16 + 16 + + + NotRunning + LFCLK not running + 0 + + + Running + LFCLK running + 1 + + + + + + + LFCLKSRCCOPY + Copy of LFCLKSRC register, set when LFCLKSTART task was triggered + 0x41C + read-only + 0x00000001 + + + SRC + Clock source + 0 + 1 + + + LFRC + 32.768 kHz RC oscillator + 1 + + + LFXO + 32.768 kHz crystal oscillator + 2 + + + LFSYNT + 32.768 kHz synthesized from HFCLK + 3 + + + + + + + HFCLKAUDIORUN + Status indicating that HFCLKAUDIOSTART task has been triggered + 0x450 + read-only + + + STATUS + HFCLKAUDIOSTART task triggered or not + 0 + 0 + + + NotTriggered + Task not triggered + 0 + + + Triggered + Task triggered + 1 + + + + + + + HFCLKAUDIOSTAT + Status indicating which HFCLKAUDIO source is running + 0x454 + read-only + + + ALWAYSRUNNING + ALWAYSRUN activated + 4 + 4 + + + NotRunning + Automatic clock control enabled + 0 + + + Running + Oscillator is always running + 1 + + + + + STATE + HFCLKAUDIO state + 16 + 16 + + + NotRunning + HFCLKAUDIO not running + 0 + + + Running + HFCLKAUDIO running + 1 + + + + + + + HFCLK192MRUN + Status indicating that HFCLK192MSTART task has been triggered + 0x458 + read-only + + + STATUS + HFCLK192MSTART task triggered or not + 0 + 0 + + + NotTriggered + Task not triggered + 0 + + + Triggered + Task triggered + 1 + + + + + + + HFCLK192MSTAT + Status indicating which HFCLK192M source is running + 0x45C + read-only + + + SRC + Active clock source + 0 + 0 + + + HFINT + Clock source: HFINT - on-chip oscillator + 0 + + + HFXO + Clock source: HFXO - derived from external 32 MHz crystal oscillator + 1 + + + + + ALWAYSRUNNING + ALWAYSRUN activated + 4 + 4 + + + NotRunning + Automatic clock control enabled + 0 + + + Running + Oscillator is always running + 1 + + + + + STATE + HFCLK192M state + 16 + 16 + + + NotRunning + HFCLK192M not running + 0 + + + Running + HFCLK192M running + 1 + + + + + + + HFCLKSRC + Clock source for HFCLK128M/HFCLK64M + 0x514 + read-write + 0x00000001 + + + SRC + Select which HFCLK source is started by the HFCLKSTART task + 0 + 0 + + + HFINT + HFCLKSTART task starts HFINT oscillator + 0 + + + HFXO + HFCLKSTART task starts HFXO oscillator + 1 + + + + + + + LFCLKSRC + Clock source for LFCLK + 0x518 + read-write + 0x00000001 + + + SRC + Select which LFCLK source is started by the LFCLKSTART task + 0 + 1 + + + LFRC + 32.768 kHz RC oscillator + 1 + + + LFXO + 32.768 kHz crystal oscillator + 2 + + + LFSYNT + 32.768 kHz synthesized from HFCLK + 3 + + + + + + + HFCLKCTRL + HFCLK128M frequency configuration + 0x558 + read-write + 0x00000001 + + + HCLK + High frequency clock HCLK + 0 + 1 + + + Div1 + Divide HFCLK by 1 + 0 + + + Div2 + Divide HFCLK by 2 + 1 + + + + + + + HFCLKAUDIO + Unspecified + CLOCK_HFCLKAUDIO + read-write + 0x55C + + FREQUENCY + Audio PLL frequency in 11.176 MHz - 11.402 MHz or 12.165 MHz - 12.411 MHz frequency bands + 0x000 + read-write + 0x00009BAE + + + FREQUENCY + Frequency 0: 10.666 MHz 65535: 13.333 MHz + 0 + 15 + + + + + + HFCLKALWAYSRUN + Automatic or manual control of HFCLK128M/HFCLK64M + 0x570 + read-write + + + ALWAYSRUN + Ensure clock is always running + 0 + 0 + + + Automatic + Use automatic clock control + 0 + + + AlwaysRun + Ensure clock is always running + 1 + + + + + + + LFCLKALWAYSRUN + Automatic or manual control of LFCLK + 0x574 + read-write + + + ALWAYSRUN + Ensure clock is always running + 0 + 0 + + + Automatic + Use automatic clock control + 0 + + + AlwaysRun + Ensure clock is always running + 1 + + + + + + + HFCLKAUDIOALWAYSRUN + Automatic or manual control of HFCLKAUDIO + 0x57C + read-write + + + ALWAYSRUN + Ensure clock is always running + 0 + 0 + + + Automatic + Use automatic clock control + 0 + + + AlwaysRun + Ensure clock is always running + 1 + + + + + + + HFCLK192MSRC + Clock source for HFCLK192M + 0x580 + read-write + 0x00000001 + + + SRC + Select which HFCLK192M source is started by the HFCLK192MSTART task + 0 + 0 + + + HFINT + HFCLK192MSTART task starts HFINT oscillator + 0 + + + HFXO + HFCLK192MSTART task starts HFXO oscillator + 1 + + + + + + + HFCLK192MALWAYSRUN + Automatic or manual control of HFCLK192M + 0x584 + read-write + + + ALWAYSRUN + Ensure clock is always running + 0 + 0 + + + Automatic + Use automatic clock control + 0 + + + AlwaysRun + Ensure clock is always running + 1 + + + + + + + HFCLK192MCTRL + HFCLK192M frequency configuration + 0x5B8 + read-write + 0x00000002 + + + HCLK192M + High frequency clock HCLK192M + 0 + 1 + + + Div1 + Divide HFCLK192M by 1 + 0 + + + Div2 + Divide HFCLK192M by 2 + 1 + + + Div4 + Divide HFCLK192M by 4 + 2 + + + + + + + + + POWER_NS + Power control 0 + 0x40005000 + CLOCK_NS + POWER + + + + 0 + 0x1000 + registers + + + CLOCK_POWER + 5 + + POWER + 0x20 + + + TASKS_CONSTLAT + Enable Constant Latency mode + 0x78 + write-only + + + TASKS_CONSTLAT + Enable Constant Latency mode + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_LOWPWR + Enable Low-Power mode (variable latency) + 0x7C + write-only + + + TASKS_LOWPWR + Enable Low-Power mode (variable latency) + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_CONSTLAT + Subscribe configuration for task CONSTLAT + 0xF8 + read-write + + + CHIDX + DPPI channel that task CONSTLAT will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_LOWPWR + Subscribe configuration for task LOWPWR + 0xFC + read-write + + + CHIDX + DPPI channel that task LOWPWR will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_POFWARN + Power failure warning + 0x108 + read-write + + + EVENTS_POFWARN + Power failure warning + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SLEEPENTER + CPU entered WFI/WFE sleep + 0x114 + read-write + + + EVENTS_SLEEPENTER + CPU entered WFI/WFE sleep + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SLEEPEXIT + CPU exited WFI/WFE sleep + 0x118 + read-write + + + EVENTS_SLEEPEXIT + CPU exited WFI/WFE sleep + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_POFWARN + Publish configuration for event POFWARN + 0x188 + read-write + + + CHIDX + DPPI channel that event POFWARN will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_SLEEPENTER + Publish configuration for event SLEEPENTER + 0x194 + read-write + + + CHIDX + DPPI channel that event SLEEPENTER will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_SLEEPEXIT + Publish configuration for event SLEEPEXIT + 0x198 + read-write + + + CHIDX + DPPI channel that event SLEEPEXIT will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + POFWARN + Enable or disable interrupt for event POFWARN + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SLEEPENTER + Enable or disable interrupt for event SLEEPENTER + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SLEEPEXIT + Enable or disable interrupt for event SLEEPEXIT + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + POFWARN + Write '1' to enable interrupt for event POFWARN + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SLEEPENTER + Write '1' to enable interrupt for event SLEEPENTER + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SLEEPEXIT + Write '1' to enable interrupt for event SLEEPEXIT + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + POFWARN + Write '1' to disable interrupt for event POFWARN + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SLEEPENTER + Write '1' to disable interrupt for event SLEEPENTER + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SLEEPEXIT + Write '1' to disable interrupt for event SLEEPEXIT + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + 0x2 + 0x4 + GPREGRET[%s] + Description collection: General purpose retention register + 0x51C + read-write + + + GPREGRET + General purpose retention register + 0 + 7 + + + + + + + RESET_NS + Reset control 0 + 0x40005000 + CLOCK_NS + RESET + + + + 0 + 0x1000 + registers + + RESET + 0x20 + + + RESETREAS + Reset reason + 0x400 + read-write + + + RESETPIN + Reset from pin reset detected + 0 + 0 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + DOG0 + Reset from application watchdog timer 0 detected + 1 + 1 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + CTRLAP + Reset from application CTRL-AP detected + 2 + 2 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + SREQ + Reset from application soft reset detected + 3 + 3 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + LOCKUP + Reset from application CPU lockup detected + 4 + 4 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + OFF + Reset due to wakeup from System OFF mode when wakeup is triggered by DETECT signal from GPIO + 5 + 5 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + LPCOMP + Reset due to wakeup from System OFF mode when wakeup is triggered by ANADETECT signal from LPCOMP + 6 + 6 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + DIF + Reset due to wakeup from System OFF mode when wakeup is triggered by entering the Debug Interface mode + 7 + 7 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + NFC + Reset after wakeup from System OFF mode due to NFC field being detected + 24 + 24 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + DOG1 + Reset from application watchdog timer 1 detected + 25 + 25 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + VBUS + Reset after wakeup from System OFF mode due to VBUS rising into valid range + 26 + 26 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + + + NETWORK + ULP network core control + RESET_NETWORK + read-write + 0x610 + + FORCEOFF + Force network core off + 0x004 + read-write + 0x00000001 + + + FORCEOFF + Force network core off + 0 + 0 + + + Release + Release Force-OFF + 0 + + + Hold + Hold Force-OFF + 1 + + + + + + + + + + CLOCK_S + Clock management 1 + 0x50005000 + + + + CLOCK_POWER + 5 + + + + POWER_S + Power control 1 + 0x50005000 + CLOCK_S + + + + CLOCK_POWER + 5 + + + + RESET_S + Reset control 1 + 0x50005000 + CLOCK_S + + + + + CTRLAP_NS + Control access port 0 + 0x40006000 + CTRLAPPERI + + + + 0 + 0x1000 + registers + + CTRLAPPERI + 0x20 + + + MAILBOX + Unspecified + CTRLAPPERI_MAILBOX + read-write + 0x400 + + RXDATA + Data sent from the debugger to the CPU. + 0x000 + read-only + 0x00000000 + + + RXDATA + Data received from debugger + 0 + 31 + + + + + RXSTATUS + This register shows a status that indicates if data sent from the debugger to the CPU has been read. + 0x004 + read-only + 0x00000000 + + + RXSTATUS + Status of data in register RXDATA + 0 + 0 + + + NoDataPending + No data pending in register RXDATA + 0 + + + DataPending + Data pending in register RXDATA + 1 + + + + + + + TXDATA + Data sent from the CPU to the debugger. + 0x80 + read-write + 0x00000000 + + + TXDATA + Data sent to debugger + 0 + 31 + + + + + TXSTATUS + This register shows a status that indicates if the data sent from the CPU to the debugger has been read. + 0x84 + read-only + 0x00000000 + + + TXSTATUS + Status of data in register TXDATA + 0 + 0 + + + NoDataPending + No data pending in register TXDATA + 0 + + + DataPending + Data pending in register TXDATA + 1 + + + + + + + + ERASEPROTECT + Unspecified + CTRLAPPERI_ERASEPROTECT + read-write + 0x500 + + LOCK + This register locks the ERASEPROTECT.DISABLE register from being written until next reset. + 0x000 + read-writeOnce + 0x00000000 + + + LOCK + Lock ERASEPROTECT.DISABLE register from being written until next reset + 0 + 0 + + + Unlocked + Register ERASEPROTECT.DISABLE is writeable + 0 + + + Locked + Register ERASEPROTECT.DISABLE is read-only + 1 + + + + + + + DISABLE + This register disables the ERASEPROTECT register and performs an ERASEALL operation. + 0x004 + read-writeOnce + 0x00000000 + + + KEY + The ERASEALL sequence is initiated if the value of the KEY fields are non-zero and the KEY fields match on both the CPU and debugger sides. + 0 + 31 + + + + + + APPROTECT + Unspecified + CTRLAPPERI_APPROTECT + read-write + 0x540 + + LOCK + This register locks the APPROTECT.DISABLE register from being written to until next reset. + 0x000 + read-writeOnce + 0x00000000 + + + LOCK + Lock the APPROTECT.DISABLE register from being written to until next reset + 0 + 0 + + + Unlocked + Register APPROTECT.DISABLE is writeable + 0 + + + Locked + Register APPROTECT.DISABLE is read-only + 1 + + + + + + + DISABLE + This register disables the APPROTECT register and enables debug access to non-secure mode. + 0x004 + read-write + 0x00000000 + + + KEY + If the value of the KEY field is non-zero, and the KEY fields match on both the + CPU and debugger sides, disable APPROTECT and enable debug access to non-secure mode until + the next pin reset, brown-out reset, power-on reset, or watchog timer reset. After reset the debugger side register has a fixed KEY value. To enable debug access, both CTRL-AP and UICR.APPROTECT protection needs to be disabled. + 0 + 31 + + + + + + SECUREAPPROTECT + Unspecified + CTRLAPPERI_SECUREAPPROTECT + read-write + 0x548 + + LOCK + This register locks the SECUREAPPROTECT.DISABLE register from being written until next reset. + 0x000 + read-writeOnce + 0x00000000 + + + LOCK + Lock register SECUREAPPROTECT.DISABLE from being written until next reset + 0 + 0 + + + Unlocked + Register SECUREAPPROTECT.DISABLE is writeable + 0 + + + Locked + Register SECUREAPPROTECT.DISABLE is read-only + 1 + + + + + + + DISABLE + This register disables the SECUREAPPROTECT register and enables debug access to secure mode. + 0x004 + read-write + 0x00000000 + + + KEY + If the value of the KEY field is non-zero, and the KEY fields match on both the + CPU and debugger sides, disable SECUREAPPROTECT and enable debug access to secure mode until + the next pin reset, brown-out reset, power-on reset, or watchog timer reset. After reset the debugger side register has a fixed KEY value. To enable debug access, both CTRL-AP and UICR.SECUREAPPROTECT protection needs to be disabled. + 0 + 31 + + + + + + STATUS + Status bits for CTRL-AP peripheral. + 0x600 + read-only + 0x00000000 + + + UICRAPPROTECT + Status bit for UICR part of access port protection at last reset. + 0 + 0 + + + Enabled + APPROTECT was enabled in UICR + 0 + + + Disabled + APPROTECT wasdisabled in UICR + 1 + + + + + UICRSECUREAPPROTECT + Status bit for UICR part of secure access port protection at last reset. + 1 + 1 + + + Enabled + SECUREAPPROTECT was enabled in UICR + 0 + + + Disabled + SECUREAPPROTECT was disabled in UICR + 1 + + + + + DBGIFACEMODE + Status bit for device debug interface mode + 2 + 2 + + + Disabled + No debugger attached + 0 + + + Enabled + Debugger is attached and device is in debug interface mode + 1 + + + + + + + + + CTRLAP_S + Control access port 1 + 0x50006000 + + + + + SPIM0_NS + Serial Peripheral Interface Master with EasyDMA 0 + 0x40008000 + SPIM + + + + 0 + 0x1000 + registers + + + SERIAL0 + 8 + + SPIM + 0x20 + + + TASKS_START + Start SPI transaction + 0x010 + write-only + + + TASKS_START + Start SPI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop SPI transaction + 0x014 + write-only + + + TASKS_STOP + Stop SPI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SUSPEND + Suspend SPI transaction + 0x01C + write-only + + + TASKS_SUSPEND + Suspend SPI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RESUME + Resume SPI transaction + 0x020 + write-only + + + TASKS_RESUME + Resume SPI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x090 + read-write + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x094 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_SUSPEND + Subscribe configuration for task SUSPEND + 0x09C + read-write + + + CHIDX + DPPI channel that task SUSPEND will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_RESUME + Subscribe configuration for task RESUME + 0x0A0 + read-write + + + CHIDX + DPPI channel that task RESUME will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_STOPPED + SPI transaction has stopped + 0x104 + read-write + + + EVENTS_STOPPED + SPI transaction has stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDRX + End of RXD buffer reached + 0x110 + read-write + + + EVENTS_ENDRX + End of RXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_END + End of RXD buffer and TXD buffer reached + 0x118 + read-write + + + EVENTS_END + End of RXD buffer and TXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDTX + End of TXD buffer reached + 0x120 + read-write + + + EVENTS_ENDTX + End of TXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STARTED + Transaction started + 0x14C + read-write + + + EVENTS_STARTED + Transaction started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + + + CHIDX + DPPI channel that event STOPPED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ENDRX + Publish configuration for event ENDRX + 0x190 + read-write + + + CHIDX + DPPI channel that event ENDRX will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x198 + read-write + + + CHIDX + DPPI channel that event END will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ENDTX + Publish configuration for event ENDTX + 0x1A0 + read-write + + + CHIDX + DPPI channel that event ENDTX will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_STARTED + Publish configuration for event STARTED + 0x1CC + read-write + + + CHIDX + DPPI channel that event STARTED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + END_START + Shortcut between event END and task START + 17 + 17 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDRX + Write '1' to enable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + END + Write '1' to enable interrupt for event END + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDTX + Write '1' to enable interrupt for event ENDTX + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STARTED + Write '1' to enable interrupt for event STARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDRX + Write '1' to disable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + END + Write '1' to disable interrupt for event END + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDTX + Write '1' to disable interrupt for event ENDTX + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STARTED + Write '1' to disable interrupt for event STARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + STALLSTAT + Stall status for EasyDMA RAM accesses. The fields in this register are set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU. + 0x400 + read-write + 0x00000000 + + + TX + Stall status for EasyDMA RAM reads + 0 + 0 + + + NOSTALL + No stall + 0 + + + STALL + A stall has occurred + 1 + + + + + RX + Stall status for EasyDMA RAM writes + 1 + 1 + + + NOSTALL + No stall + 0 + + + STALL + A stall has occurred + 1 + + + + + + + ENABLE + Enable SPIM + 0x500 + read-write + + + ENABLE + Enable or disable SPIM + 0 + 3 + + + Disabled + Disable SPIM + 0 + + + Enabled + Enable SPIM + 7 + + + + + + + PSEL + Unspecified + SPIM_PSEL + read-write + 0x508 + + SCK + Pin select for SCK + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MOSI + Pin select for MOSI signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MISO + Pin select for MISO signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + CSN + Pin select for CSN + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + FREQUENCY + SPI frequency. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + FREQUENCY + SPI master data rate + 0 + 31 + + + K125 + 125 kbps + 0x02000000 + + + K250 + 250 kbps + 0x04000000 + + + K500 + 500 kbps + 0x08000000 + + + M1 + 1 Mbps + 0x10000000 + + + M2 + 2 Mbps + 0x20000000 + + + M4 + 4 Mbps + 0x40000000 + + + M8 + 8 Mbps + 0x80000000 + + + M16 + 16 Mbps + 0x0A000000 + + + M32 + 32 Mbps + 0x14000000 + + + + + + + RXD + RXD EasyDMA channel + SPIM_RXD + read-write + 0x534 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + TXD + TXD EasyDMA channel + SPIM_TXD + read-write + 0x544 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + CONFIG + Configuration register + 0x554 + read-write + + + ORDER + Bit order + 0 + 0 + + + MsbFirst + Most significant bit shifted out first + 0 + + + LsbFirst + Least significant bit shifted out first + 1 + + + + + CPHA + Serial clock (SCK) phase + 1 + 1 + + + Leading + Sample on leading edge of clock, shift serial data on trailing edge + 0 + + + Trailing + Sample on trailing edge of clock, shift serial data on leading edge + 1 + + + + + CPOL + Serial clock (SCK) polarity + 2 + 2 + + + ActiveHigh + Active high + 0 + + + ActiveLow + Active low + 1 + + + + + + + IFTIMING + Unspecified + SPIM_IFTIMING + read-write + 0x560 + + RXDELAY + Sample delay for input serial data on MISO + 0x000 + read-write + 0x00000002 + + + RXDELAY + Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK. + 0 + 2 + + + + + CSNDUR + Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, this is also the minimum duration CSN must stay high between transactions. + 0x004 + read-write + 0x00000002 + + + CSNDUR + Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, this is the minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns). + 0 + 7 + + + + + + CSNPOL + Polarity of CSN output + 0x568 + read-write + 0x00000000 + + + CSNPOL + Polarity of CSN output + 0 + 0 + + + LOW + Active low (idle state high) + 0 + + + HIGH + Active high (idle state low) + 1 + + + + + + + PSELDCX + Pin select for DCX signal + 0x56C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + DCXCNT + DCX configuration + 0x570 + read-write + + + DCXCNT + This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates that all bytes are command bytes. + 0 + 3 + + + + + ORC + Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT + 0x5C0 + read-write + + + ORC + Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT. + 0 + 7 + + + + + + + SPIS0_NS + SPI Slave 0 + 0x40008000 + SPIM0_NS + SPIS + + + + 0 + 0x1000 + registers + + + SERIAL0 + 8 + + SPIS + 0x20 + + + TASKS_ACQUIRE + Acquire SPI semaphore + 0x024 + write-only + + + TASKS_ACQUIRE + Acquire SPI semaphore + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RELEASE + Release SPI semaphore, enabling the SPI slave to acquire it + 0x028 + write-only + + + TASKS_RELEASE + Release SPI semaphore, enabling the SPI slave to acquire it + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_ACQUIRE + Subscribe configuration for task ACQUIRE + 0x0A4 + read-write + + + CHIDX + DPPI channel that task ACQUIRE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_RELEASE + Subscribe configuration for task RELEASE + 0x0A8 + read-write + + + CHIDX + DPPI channel that task RELEASE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_END + Granted transaction completed + 0x104 + read-write + + + EVENTS_END + Granted transaction completed + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDRX + End of RXD buffer reached + 0x110 + read-write + + + EVENTS_ENDRX + End of RXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ACQUIRED + Semaphore acquired + 0x128 + read-write + + + EVENTS_ACQUIRED + Semaphore acquired + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x184 + read-write + + + CHIDX + DPPI channel that event END will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ENDRX + Publish configuration for event ENDRX + 0x190 + read-write + + + CHIDX + DPPI channel that event ENDRX will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ACQUIRED + Publish configuration for event ACQUIRED + 0x1A8 + read-write + + + CHIDX + DPPI channel that event ACQUIRED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + END_ACQUIRE + Shortcut between event END and task ACQUIRE + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + END + Write '1' to enable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDRX + Write '1' to enable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ACQUIRED + Write '1' to enable interrupt for event ACQUIRED + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + END + Write '1' to disable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDRX + Write '1' to disable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ACQUIRED + Write '1' to disable interrupt for event ACQUIRED + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + SEMSTAT + Semaphore status register + 0x400 + read-only + 0x00000001 + + + SEMSTAT + Semaphore status + 0 + 1 + + + Free + Semaphore is free + 0 + + + CPU + Semaphore is assigned to CPU + 1 + + + SPIS + Semaphore is assigned to SPI slave + 2 + + + CPUPending + Semaphore is assigned to SPI but a handover to the CPU is pending + 3 + + + + + + + STATUS + Status from last transaction + 0x440 + read-write + + + OVERREAD + TX buffer over-read detected, and prevented + 0 + 0 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + write + + Clear + Write: clear error on writing '1' + 1 + + + + + OVERFLOW + RX buffer overflow detected, and prevented + 1 + 1 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + write + + Clear + Write: clear error on writing '1' + 1 + + + + + + + ENABLE + Enable SPI slave + 0x500 + read-write + + + ENABLE + Enable or disable SPI slave + 0 + 3 + + + Disabled + Disable SPI slave + 0 + + + Enabled + Enable SPI slave + 2 + + + + + + + PSEL + Unspecified + SPIS_PSEL + read-write + 0x508 + + SCK + Pin select for SCK + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MISO + Pin select for MISO signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MOSI + Pin select for MOSI signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + CSN + Pin select for CSN signal + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + RXD + Unspecified + SPIS_RXD + read-write + 0x534 + + PTR + RXD data pointer + 0x000 + read-write + + + PTR + RXD data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 15 + + + + + AMOUNT + Number of bytes received in last granted transaction + 0x008 + read-only + + + AMOUNT + Number of bytes received in the last granted transaction + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + TXD + Unspecified + SPIS_TXD + read-write + 0x544 + + PTR + TXD data pointer + 0x000 + read-write + + + PTR + TXD data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transmitted in last granted transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transmitted in last granted transaction + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + CONFIG + Configuration register + 0x554 + read-write + + + ORDER + Bit order + 0 + 0 + + + MsbFirst + Most significant bit shifted out first + 0 + + + LsbFirst + Least significant bit shifted out first + 1 + + + + + CPHA + Serial clock (SCK) phase + 1 + 1 + + + Leading + Sample on leading edge of clock, shift serial data on trailing edge + 0 + + + Trailing + Sample on trailing edge of clock, shift serial data on leading edge + 1 + + + + + CPOL + Serial clock (SCK) polarity + 2 + 2 + + + ActiveHigh + Active high + 0 + + + ActiveLow + Active low + 1 + + + + + + + DEF + Default character. Character clocked out in case of an ignored transaction. + 0x55C + read-write + + + DEF + Default character. Character clocked out in case of an ignored transaction. + 0 + 7 + + + + + ORC + Over-read character + 0x5C0 + read-write + + + ORC + Over-read character. Character clocked out after an over-read of the transmit buffer. + 0 + 7 + + + + + + + TWIM0_NS + I2C compatible Two-Wire Master Interface with EasyDMA 0 + 0x40008000 + SPIM0_NS + TWIM + + + + 0 + 0x1000 + registers + + + SERIAL0 + 8 + + TWIM + 0x20 + + + TASKS_STARTRX + Start TWI receive sequence + 0x000 + write-only + + + TASKS_STARTRX + Start TWI receive sequence + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTTX + Start TWI transmit sequence + 0x008 + write-only + + + TASKS_STARTTX + Start TWI transmit sequence + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop TWI transaction. Must be issued while the TWI master is not suspended. + 0x014 + write-only + + + TASKS_STOP + Stop TWI transaction. Must be issued while the TWI master is not suspended. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SUSPEND + Suspend TWI transaction + 0x01C + write-only + + + TASKS_SUSPEND + Suspend TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RESUME + Resume TWI transaction + 0x020 + write-only + + + TASKS_RESUME + Resume TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_STARTRX + Subscribe configuration for task STARTRX + 0x080 + read-write + + + CHIDX + DPPI channel that task STARTRX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STARTTX + Subscribe configuration for task STARTTX + 0x088 + read-write + + + CHIDX + DPPI channel that task STARTTX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x094 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_SUSPEND + Subscribe configuration for task SUSPEND + 0x09C + read-write + + + CHIDX + DPPI channel that task SUSPEND will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_RESUME + Subscribe configuration for task RESUME + 0x0A0 + read-write + + + CHIDX + DPPI channel that task RESUME will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_STOPPED + TWI stopped + 0x104 + read-write + + + EVENTS_STOPPED + TWI stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + TWI error + 0x124 + read-write + + + EVENTS_ERROR + TWI error + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SUSPENDED + SUSPEND task has been issued, TWI traffic is now suspended. + 0x148 + read-write + + + EVENTS_SUSPENDED + SUSPEND task has been issued, TWI traffic is now suspended. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXSTARTED + Receive sequence started + 0x14C + read-write + + + EVENTS_RXSTARTED + Receive sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXSTARTED + Transmit sequence started + 0x150 + read-write + + + EVENTS_TXSTARTED + Transmit sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_LASTRX + Byte boundary, starting to receive the last byte + 0x15C + read-write + + + EVENTS_LASTRX + Byte boundary, starting to receive the last byte + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_LASTTX + Byte boundary, starting to transmit the last byte + 0x160 + read-write + + + EVENTS_LASTTX + Byte boundary, starting to transmit the last byte + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + + + CHIDX + DPPI channel that event STOPPED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ERROR + Publish configuration for event ERROR + 0x1A4 + read-write + + + CHIDX + DPPI channel that event ERROR will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_SUSPENDED + Publish configuration for event SUSPENDED + 0x1C8 + read-write + + + CHIDX + DPPI channel that event SUSPENDED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_RXSTARTED + Publish configuration for event RXSTARTED + 0x1CC + read-write + + + CHIDX + DPPI channel that event RXSTARTED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_TXSTARTED + Publish configuration for event TXSTARTED + 0x1D0 + read-write + + + CHIDX + DPPI channel that event TXSTARTED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_LASTRX + Publish configuration for event LASTRX + 0x1DC + read-write + + + CHIDX + DPPI channel that event LASTRX will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_LASTTX + Publish configuration for event LASTTX + 0x1E0 + read-write + + + CHIDX + DPPI channel that event LASTTX will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + LASTTX_STARTRX + Shortcut between event LASTTX and task STARTRX + 7 + 7 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTTX_SUSPEND + Shortcut between event LASTTX and task SUSPEND + 8 + 8 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTTX_STOP + Shortcut between event LASTTX and task STOP + 9 + 9 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTRX_STARTTX + Shortcut between event LASTRX and task STARTTX + 10 + 10 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTRX_STOP + Shortcut between event LASTRX and task STOP + 12 + 12 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SUSPENDED + Enable or disable interrupt for event SUSPENDED + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXSTARTED + Enable or disable interrupt for event RXSTARTED + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTARTED + Enable or disable interrupt for event TXSTARTED + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + LASTRX + Enable or disable interrupt for event LASTRX + 23 + 23 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + LASTTX + Enable or disable interrupt for event LASTTX + 24 + 24 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SUSPENDED + Write '1' to enable interrupt for event SUSPENDED + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXSTARTED + Write '1' to enable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTARTED + Write '1' to enable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + LASTRX + Write '1' to enable interrupt for event LASTRX + 23 + 23 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + LASTTX + Write '1' to enable interrupt for event LASTTX + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SUSPENDED + Write '1' to disable interrupt for event SUSPENDED + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXSTARTED + Write '1' to disable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXSTARTED + Write '1' to disable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + LASTRX + Write '1' to disable interrupt for event LASTRX + 23 + 23 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + LASTTX + Write '1' to disable interrupt for event LASTTX + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source + 0x4C4 + read-write + oneToClear + + + OVERRUN + Overrun error + 0 + 0 + + + NotReceived + Error did not occur + 0 + + + Received + Error occurred + 1 + + + + + ANACK + NACK received after sending the address (write '1' to clear) + 1 + 1 + + + NotReceived + Error did not occur + 0 + + + Received + Error occurred + 1 + + + + + DNACK + NACK received after sending a data byte (write '1' to clear) + 2 + 2 + + + NotReceived + Error did not occur + 0 + + + Received + Error occurred + 1 + + + + + + + ENABLE + Enable TWIM + 0x500 + read-write + + + ENABLE + Enable or disable TWIM + 0 + 3 + + + Disabled + Disable TWIM + 0 + + + Enabled + Enable TWIM + 6 + + + + + + + PSEL + Unspecified + TWIM_PSEL + read-write + 0x508 + + SCL + Pin select for SCL signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDA + Pin select for SDA signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + FREQUENCY + TWI frequency. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + FREQUENCY + TWI master clock frequency + 0 + 31 + + + K100 + 100 kbps + 0x01980000 + + + K250 + 250 kbps + 0x04000000 + + + K400 + 400 kbps + 0x06400000 + + + K1000 + 1000 kbps + 0x0FF00000 + + + + + + + RXD + RXD EasyDMA channel + TWIM_RXD + read-write + 0x534 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + TXD + TXD EasyDMA channel + TWIM_TXD + read-write + 0x544 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + ADDRESS + Address used in the TWI transfer + 0x588 + read-write + + + ADDRESS + Address used in the TWI transfer + 0 + 6 + + + + + + + TWIS0_NS + I2C compatible Two-Wire Slave Interface with EasyDMA 0 + 0x40008000 + SPIM0_NS + TWIS + + + + 0 + 0x1000 + registers + + + SERIAL0 + 8 + + TWIS + 0x20 + + + TASKS_STOP + Stop TWI transaction + 0x014 + write-only + + + TASKS_STOP + Stop TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SUSPEND + Suspend TWI transaction + 0x01C + write-only + + + TASKS_SUSPEND + Suspend TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RESUME + Resume TWI transaction + 0x020 + write-only + + + TASKS_RESUME + Resume TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_PREPARERX + Prepare the TWI slave to respond to a write command + 0x030 + write-only + + + TASKS_PREPARERX + Prepare the TWI slave to respond to a write command + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_PREPARETX + Prepare the TWI slave to respond to a read command + 0x034 + write-only + + + TASKS_PREPARETX + Prepare the TWI slave to respond to a read command + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x094 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_SUSPEND + Subscribe configuration for task SUSPEND + 0x09C + read-write + + + CHIDX + DPPI channel that task SUSPEND will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_RESUME + Subscribe configuration for task RESUME + 0x0A0 + read-write + + + CHIDX + DPPI channel that task RESUME will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_PREPARERX + Subscribe configuration for task PREPARERX + 0x0B0 + read-write + + + CHIDX + DPPI channel that task PREPARERX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_PREPARETX + Subscribe configuration for task PREPARETX + 0x0B4 + read-write + + + CHIDX + DPPI channel that task PREPARETX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_STOPPED + TWI stopped + 0x104 + read-write + + + EVENTS_STOPPED + TWI stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + TWI error + 0x124 + read-write + + + EVENTS_ERROR + TWI error + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXSTARTED + Receive sequence started + 0x14C + read-write + + + EVENTS_RXSTARTED + Receive sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXSTARTED + Transmit sequence started + 0x150 + read-write + + + EVENTS_TXSTARTED + Transmit sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_WRITE + Write command received + 0x164 + read-write + + + EVENTS_WRITE + Write command received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_READ + Read command received + 0x168 + read-write + + + EVENTS_READ + Read command received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + + + CHIDX + DPPI channel that event STOPPED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ERROR + Publish configuration for event ERROR + 0x1A4 + read-write + + + CHIDX + DPPI channel that event ERROR will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_RXSTARTED + Publish configuration for event RXSTARTED + 0x1CC + read-write + + + CHIDX + DPPI channel that event RXSTARTED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_TXSTARTED + Publish configuration for event TXSTARTED + 0x1D0 + read-write + + + CHIDX + DPPI channel that event TXSTARTED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_WRITE + Publish configuration for event WRITE + 0x1E4 + read-write + + + CHIDX + DPPI channel that event WRITE will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_READ + Publish configuration for event READ + 0x1E8 + read-write + + + CHIDX + DPPI channel that event READ will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + WRITE_SUSPEND + Shortcut between event WRITE and task SUSPEND + 13 + 13 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + READ_SUSPEND + Shortcut between event READ and task SUSPEND + 14 + 14 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXSTARTED + Enable or disable interrupt for event RXSTARTED + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTARTED + Enable or disable interrupt for event TXSTARTED + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + WRITE + Enable or disable interrupt for event WRITE + 25 + 25 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + READ + Enable or disable interrupt for event READ + 26 + 26 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXSTARTED + Write '1' to enable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTARTED + Write '1' to enable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + WRITE + Write '1' to enable interrupt for event WRITE + 25 + 25 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + READ + Write '1' to enable interrupt for event READ + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXSTARTED + Write '1' to disable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXSTARTED + Write '1' to disable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + WRITE + Write '1' to disable interrupt for event WRITE + 25 + 25 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + READ + Write '1' to disable interrupt for event READ + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source + 0x4D0 + read-write + oneToClear + + + OVERFLOW + RX buffer overflow detected, and prevented + 0 + 0 + + + NotDetected + Error did not occur + 0 + + + Detected + Error occurred + 1 + + + + + DNACK + NACK sent after receiving a data byte + 2 + 2 + + + NotReceived + Error did not occur + 0 + + + Received + Error occurred + 1 + + + + + OVERREAD + TX buffer over-read detected, and prevented + 3 + 3 + + + NotDetected + Error did not occur + 0 + + + Detected + Error occurred + 1 + + + + + + + MATCH + Status register indicating which address had a match + 0x4D4 + read-only + + + MATCH + Indication of which address in {ADDRESS} that matched the incoming address + 0 + 0 + + + + + ENABLE + Enable TWIS + 0x500 + read-write + + + ENABLE + Enable or disable TWIS + 0 + 3 + + + Disabled + Disable TWIS + 0 + + + Enabled + Enable TWIS + 9 + + + + + + + PSEL + Unspecified + TWIS_PSEL + read-write + 0x508 + + SCL + Pin select for SCL signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDA + Pin select for SDA signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + RXD + RXD EasyDMA channel + TWIS_RXD + read-write + 0x534 + + PTR + RXD Data pointer + 0x000 + read-write + + + PTR + RXD Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in RXD buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in RXD buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last RXD transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last RXD transaction + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + TXD + TXD EasyDMA channel + TWIS_TXD + read-write + 0x544 + + PTR + TXD Data pointer + 0x000 + read-write + + + PTR + TXD Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in TXD buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in TXD buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last TXD transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last TXD transaction + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + 0x2 + 0x4 + ADDRESS[%s] + Description collection: TWI slave address n + 0x588 + read-write + + + ADDRESS + TWI slave address + 0 + 6 + + + + + CONFIG + Configuration register for the address match mechanism + 0x594 + read-write + 0x00000001 + + + ADDRESS0 + Enable or disable address matching on ADDRESS[0] + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ADDRESS1 + Enable or disable address matching on ADDRESS[1] + 1 + 1 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + + + ORC + Over-read character. Character sent out in case of an over-read of the transmit buffer. + 0x5C0 + read-write + + + ORC + Over-read character. Character sent out in case of an over-read of the transmit buffer. + 0 + 7 + + + + + + + UARTE0_NS + UART with EasyDMA 0 + 0x40008000 + SPIM0_NS + UARTE + + + + 0 + 0x1000 + registers + + + SERIAL0 + 8 + + UARTE + 0x20 + + + TASKS_STARTRX + Start UART receiver + 0x000 + write-only + + + TASKS_STARTRX + Start UART receiver + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOPRX + Stop UART receiver + 0x004 + write-only + + + TASKS_STOPRX + Stop UART receiver + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTTX + Start UART transmitter + 0x008 + write-only + + + TASKS_STARTTX + Start UART transmitter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOPTX + Stop UART transmitter + 0x00C + write-only + + + TASKS_STOPTX + Stop UART transmitter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_FLUSHRX + Flush RX FIFO into RX buffer + 0x02C + write-only + + + TASKS_FLUSHRX + Flush RX FIFO into RX buffer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_STARTRX + Subscribe configuration for task STARTRX + 0x080 + read-write + + + CHIDX + DPPI channel that task STARTRX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOPRX + Subscribe configuration for task STOPRX + 0x084 + read-write + + + CHIDX + DPPI channel that task STOPRX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STARTTX + Subscribe configuration for task STARTTX + 0x088 + read-write + + + CHIDX + DPPI channel that task STARTTX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOPTX + Subscribe configuration for task STOPTX + 0x08C + read-write + + + CHIDX + DPPI channel that task STOPTX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_FLUSHRX + Subscribe configuration for task FLUSHRX + 0x0AC + read-write + + + CHIDX + DPPI channel that task FLUSHRX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0x100 + read-write + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0x104 + read-write + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXDRDY + Data received in RXD (but potentially not yet transferred to Data RAM) + 0x108 + read-write + + + EVENTS_RXDRDY + Data received in RXD (but potentially not yet transferred to Data RAM) + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDRX + Receive buffer is filled up + 0x110 + read-write + + + EVENTS_ENDRX + Receive buffer is filled up + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXDRDY + Data sent from TXD + 0x11C + read-write + + + EVENTS_TXDRDY + Data sent from TXD + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDTX + Last TX byte transmitted + 0x120 + read-write + + + EVENTS_ENDTX + Last TX byte transmitted + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + Error detected + 0x124 + read-write + + + EVENTS_ERROR + Error detected + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXTO + Receiver timeout + 0x144 + read-write + + + EVENTS_RXTO + Receiver timeout + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXSTARTED + UART receiver has started + 0x14C + read-write + + + EVENTS_RXSTARTED + UART receiver has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXSTARTED + UART transmitter has started + 0x150 + read-write + + + EVENTS_TXSTARTED + UART transmitter has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXSTOPPED + Transmitter stopped + 0x158 + read-write + + + EVENTS_TXSTOPPED + Transmitter stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_CTS + Publish configuration for event CTS + 0x180 + read-write + + + CHIDX + DPPI channel that event CTS will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_NCTS + Publish configuration for event NCTS + 0x184 + read-write + + + CHIDX + DPPI channel that event NCTS will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_RXDRDY + Publish configuration for event RXDRDY + 0x188 + read-write + + + CHIDX + DPPI channel that event RXDRDY will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ENDRX + Publish configuration for event ENDRX + 0x190 + read-write + + + CHIDX + DPPI channel that event ENDRX will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_TXDRDY + Publish configuration for event TXDRDY + 0x19C + read-write + + + CHIDX + DPPI channel that event TXDRDY will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ENDTX + Publish configuration for event ENDTX + 0x1A0 + read-write + + + CHIDX + DPPI channel that event ENDTX will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ERROR + Publish configuration for event ERROR + 0x1A4 + read-write + + + CHIDX + DPPI channel that event ERROR will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_RXTO + Publish configuration for event RXTO + 0x1C4 + read-write + + + CHIDX + DPPI channel that event RXTO will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_RXSTARTED + Publish configuration for event RXSTARTED + 0x1CC + read-write + + + CHIDX + DPPI channel that event RXSTARTED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_TXSTARTED + Publish configuration for event TXSTARTED + 0x1D0 + read-write + + + CHIDX + DPPI channel that event TXSTARTED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_TXSTOPPED + Publish configuration for event TXSTOPPED + 0x1D8 + read-write + + + CHIDX + DPPI channel that event TXSTOPPED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + ENDRX_STARTRX + Shortcut between event ENDRX and task STARTRX + 5 + 5 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + ENDRX_STOPRX + Shortcut between event ENDRX and task STOPRX + 6 + 6 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + CTS + Enable or disable interrupt for event CTS + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + NCTS + Enable or disable interrupt for event NCTS + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXDRDY + Enable or disable interrupt for event RXDRDY + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDRX + Enable or disable interrupt for event ENDRX + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXDRDY + Enable or disable interrupt for event TXDRDY + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDTX + Enable or disable interrupt for event ENDTX + 8 + 8 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXTO + Enable or disable interrupt for event RXTO + 17 + 17 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXSTARTED + Enable or disable interrupt for event RXSTARTED + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTARTED + Enable or disable interrupt for event TXSTARTED + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTOPPED + Enable or disable interrupt for event TXSTOPPED + 22 + 22 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + CTS + Write '1' to enable interrupt for event CTS + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + NCTS + Write '1' to enable interrupt for event NCTS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXDRDY + Write '1' to enable interrupt for event RXDRDY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDRX + Write '1' to enable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXDRDY + Write '1' to enable interrupt for event TXDRDY + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDTX + Write '1' to enable interrupt for event ENDTX + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXTO + Write '1' to enable interrupt for event RXTO + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXSTARTED + Write '1' to enable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTARTED + Write '1' to enable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTOPPED + Write '1' to enable interrupt for event TXSTOPPED + 22 + 22 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + CTS + Write '1' to disable interrupt for event CTS + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + NCTS + Write '1' to disable interrupt for event NCTS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXDRDY + Write '1' to disable interrupt for event RXDRDY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDRX + Write '1' to disable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXDRDY + Write '1' to disable interrupt for event TXDRDY + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDTX + Write '1' to disable interrupt for event ENDTX + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXTO + Write '1' to disable interrupt for event RXTO + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXSTARTED + Write '1' to disable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXSTARTED + Write '1' to disable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXSTOPPED + Write '1' to disable interrupt for event TXSTOPPED + 22 + 22 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source + 0x480 + read-write + oneToClear + + + OVERRUN + Overrun error + 0 + 0 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + PARITY + Parity error + 1 + 1 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + FRAMING + Framing error occurred + 2 + 2 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + BREAK + Break condition + 3 + 3 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + + + ENABLE + Enable UART + 0x500 + read-write + + + ENABLE + Enable or disable UARTE + 0 + 3 + + + Disabled + Disable UARTE + 0 + + + Enabled + Enable UARTE + 8 + + + + + + + PSEL + Unspecified + UARTE_PSEL + read-write + 0x508 + + RTS + Pin select for RTS signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + TXD + Pin select for TXD signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + CTS + Pin select for CTS signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + RXD + Pin select for RXD signal + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + BAUDRATE + Baud rate. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + BAUDRATE + Baud rate + 0 + 31 + + + Baud1200 + 1200 baud (actual rate: 1205) + 0x0004F000 + + + Baud2400 + 2400 baud (actual rate: 2396) + 0x0009D000 + + + Baud4800 + 4800 baud (actual rate: 4808) + 0x0013B000 + + + Baud9600 + 9600 baud (actual rate: 9598) + 0x00275000 + + + Baud14400 + 14400 baud (actual rate: 14401) + 0x003AF000 + + + Baud19200 + 19200 baud (actual rate: 19208) + 0x004EA000 + + + Baud28800 + 28800 baud (actual rate: 28777) + 0x0075C000 + + + Baud31250 + 31250 baud + 0x00800000 + + + Baud38400 + 38400 baud (actual rate: 38369) + 0x009D0000 + + + Baud56000 + 56000 baud (actual rate: 55944) + 0x00E50000 + + + Baud57600 + 57600 baud (actual rate: 57554) + 0x00EB0000 + + + Baud76800 + 76800 baud (actual rate: 76923) + 0x013A9000 + + + Baud115200 + 115200 baud (actual rate: 115108) + 0x01D60000 + + + Baud230400 + 230400 baud (actual rate: 231884) + 0x03B00000 + + + Baud250000 + 250000 baud + 0x04000000 + + + Baud460800 + 460800 baud (actual rate: 457143) + 0x07400000 + + + Baud921600 + 921600 baud (actual rate: 941176) + 0x0F000000 + + + Baud1M + 1 megabaud + 0x10000000 + + + + + + + RXD + RXD EasyDMA channel + UARTE_RXD + read-write + 0x534 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 15 + + + + + + TXD + TXD EasyDMA channel + UARTE_TXD + read-write + 0x544 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 15 + + + + + + CONFIG + Configuration of parity and hardware flow control + 0x56C + read-write + + + HWFC + Hardware flow control + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + PARITY + Parity + 1 + 3 + + + Excluded + Exclude parity bit + 0x0 + + + Included + Include even parity bit + 0x7 + + + + + STOP + Stop bits + 4 + 4 + + + One + One stop bit + 0 + + + Two + Two stop bits + 1 + + + + + PARITYTYPE + Even or odd parity type + 8 + 8 + + + Even + Even parity + 0 + + + Odd + Odd parity + 1 + + + + + + + + + SPIM0_S + Serial Peripheral Interface Master with EasyDMA 1 + 0x50008000 + + + + SERIAL0 + 8 + + + + SPIS0_S + SPI Slave 1 + 0x50008000 + SPIM0_S + + + + SERIAL0 + 8 + + + + TWIM0_S + I2C compatible Two-Wire Master Interface with EasyDMA 1 + 0x50008000 + SPIM0_S + + + + SERIAL0 + 8 + + + + TWIS0_S + I2C compatible Two-Wire Slave Interface with EasyDMA 1 + 0x50008000 + SPIM0_S + + + + SERIAL0 + 8 + + + + UARTE0_S + UART with EasyDMA 1 + 0x50008000 + SPIM0_S + + + + SERIAL0 + 8 + + + + SPIM1_NS + Serial Peripheral Interface Master with EasyDMA 2 + 0x40009000 + + + + SERIAL1 + 9 + + + + SPIS1_NS + SPI Slave 2 + 0x40009000 + SPIM1_NS + + + + SERIAL1 + 9 + + + + TWIM1_NS + I2C compatible Two-Wire Master Interface with EasyDMA 2 + 0x40009000 + SPIM1_NS + + + + SERIAL1 + 9 + + + + TWIS1_NS + I2C compatible Two-Wire Slave Interface with EasyDMA 2 + 0x40009000 + SPIM1_NS + + + + SERIAL1 + 9 + + + + UARTE1_NS + UART with EasyDMA 2 + 0x40009000 + SPIM1_NS + + + + SERIAL1 + 9 + + + + SPIM1_S + Serial Peripheral Interface Master with EasyDMA 3 + 0x50009000 + + + + SERIAL1 + 9 + + + + SPIS1_S + SPI Slave 3 + 0x50009000 + SPIM1_S + + + + SERIAL1 + 9 + + + + TWIM1_S + I2C compatible Two-Wire Master Interface with EasyDMA 3 + 0x50009000 + SPIM1_S + + + + SERIAL1 + 9 + + + + TWIS1_S + I2C compatible Two-Wire Slave Interface with EasyDMA 3 + 0x50009000 + SPIM1_S + + + + SERIAL1 + 9 + + + + UARTE1_S + UART with EasyDMA 3 + 0x50009000 + SPIM1_S + + + + SERIAL1 + 9 + + + + SPIM4_NS + Serial Peripheral Interface Master with EasyDMA 4 + 0x4000A000 + + + + SPIM4 + 10 + + + + SPIM4_S + Serial Peripheral Interface Master with EasyDMA 5 + 0x5000A000 + + + + SPIM4 + 10 + + + + SPIM2_NS + Serial Peripheral Interface Master with EasyDMA 6 + 0x4000B000 + + + + SERIAL2 + 11 + + + + SPIS2_NS + SPI Slave 4 + 0x4000B000 + SPIM2_NS + + + + SERIAL2 + 11 + + + + TWIM2_NS + I2C compatible Two-Wire Master Interface with EasyDMA 4 + 0x4000B000 + SPIM2_NS + + + + SERIAL2 + 11 + + + + TWIS2_NS + I2C compatible Two-Wire Slave Interface with EasyDMA 4 + 0x4000B000 + SPIM2_NS + + + + SERIAL2 + 11 + + + + UARTE2_NS + UART with EasyDMA 4 + 0x4000B000 + SPIM2_NS + + + + SERIAL2 + 11 + + + + SPIM2_S + Serial Peripheral Interface Master with EasyDMA 7 + 0x5000B000 + + + + SERIAL2 + 11 + + + + SPIS2_S + SPI Slave 5 + 0x5000B000 + SPIM2_S + + + + SERIAL2 + 11 + + + + TWIM2_S + I2C compatible Two-Wire Master Interface with EasyDMA 5 + 0x5000B000 + SPIM2_S + + + + SERIAL2 + 11 + + + + TWIS2_S + I2C compatible Two-Wire Slave Interface with EasyDMA 5 + 0x5000B000 + SPIM2_S + + + + SERIAL2 + 11 + + + + UARTE2_S + UART with EasyDMA 5 + 0x5000B000 + SPIM2_S + + + + SERIAL2 + 11 + + + + SPIM3_NS + Serial Peripheral Interface Master with EasyDMA 8 + 0x4000C000 + + + + SERIAL3 + 12 + + + + SPIS3_NS + SPI Slave 6 + 0x4000C000 + SPIM3_NS + + + + SERIAL3 + 12 + + + + TWIM3_NS + I2C compatible Two-Wire Master Interface with EasyDMA 6 + 0x4000C000 + SPIM3_NS + + + + SERIAL3 + 12 + + + + TWIS3_NS + I2C compatible Two-Wire Slave Interface with EasyDMA 6 + 0x4000C000 + SPIM3_NS + + + + SERIAL3 + 12 + + + + UARTE3_NS + UART with EasyDMA 6 + 0x4000C000 + SPIM3_NS + + + + SERIAL3 + 12 + + + + SPIM3_S + Serial Peripheral Interface Master with EasyDMA 9 + 0x5000C000 + + + + SERIAL3 + 12 + + + + SPIS3_S + SPI Slave 7 + 0x5000C000 + SPIM3_S + + + + SERIAL3 + 12 + + + + TWIM3_S + I2C compatible Two-Wire Master Interface with EasyDMA 7 + 0x5000C000 + SPIM3_S + + + + SERIAL3 + 12 + + + + TWIS3_S + I2C compatible Two-Wire Slave Interface with EasyDMA 7 + 0x5000C000 + SPIM3_S + + + + SERIAL3 + 12 + + + + UARTE3_S + UART with EasyDMA 7 + 0x5000C000 + SPIM3_S + + + + SERIAL3 + 12 + + + + GPIOTE0_S + GPIO Tasks and Events 0 + 0x5000D000 + GPIOTE + + + + 0 + 0x1000 + registers + + + GPIOTE0 + 13 + + GPIOTE + 0x20 + + + 0x8 + 0x4 + TASKS_OUT[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. + 0x000 + write-only + + + TASKS_OUT + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x8 + 0x4 + TASKS_SET[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. + 0x030 + write-only + + + TASKS_SET + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x8 + 0x4 + TASKS_CLR[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. + 0x060 + write-only + + + TASKS_CLR + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_OUT[%s] + Description collection: Subscribe configuration for task OUT[n] + 0x080 + read-write + + + CHIDX + DPPI channel that task OUT[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_SET[%s] + Description collection: Subscribe configuration for task SET[n] + 0x0B0 + read-write + + + CHIDX + DPPI channel that task SET[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_CLR[%s] + Description collection: Subscribe configuration for task CLR[n] + 0x0E0 + read-write + + + CHIDX + DPPI channel that task CLR[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + 0x8 + 0x4 + EVENTS_IN[%s] + Description collection: Event generated from pin specified in CONFIG[n].PSEL + 0x100 + read-write + + + EVENTS_IN + Event generated from pin specified in CONFIG[n].PSEL + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_PORT + Event generated from multiple input GPIO pins with SENSE mechanism enabled + 0x17C + read-write + + + EVENTS_PORT + Event generated from multiple input GPIO pins with SENSE mechanism enabled + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x8 + 0x4 + PUBLISH_IN[%s] + Description collection: Publish configuration for event IN[n] + 0x180 + read-write + + + CHIDX + DPPI channel that event IN[n] will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_PORT + Publish configuration for event PORT + 0x1FC + read-write + + + CHIDX + DPPI channel that event PORT will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + IN0 + Write '1' to enable interrupt for event IN[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN1 + Write '1' to enable interrupt for event IN[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN2 + Write '1' to enable interrupt for event IN[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN3 + Write '1' to enable interrupt for event IN[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN4 + Write '1' to enable interrupt for event IN[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN5 + Write '1' to enable interrupt for event IN[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN6 + Write '1' to enable interrupt for event IN[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN7 + Write '1' to enable interrupt for event IN[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PORT + Write '1' to enable interrupt for event PORT + 31 + 31 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + IN0 + Write '1' to disable interrupt for event IN[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN1 + Write '1' to disable interrupt for event IN[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN2 + Write '1' to disable interrupt for event IN[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN3 + Write '1' to disable interrupt for event IN[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN4 + Write '1' to disable interrupt for event IN[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN5 + Write '1' to disable interrupt for event IN[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN6 + Write '1' to disable interrupt for event IN[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN7 + Write '1' to disable interrupt for event IN[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PORT + Write '1' to disable interrupt for event PORT + 31 + 31 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + LATENCY + Latency selection for Event mode (MODE=Event) with rising or falling edge detection on the pin. + 0x504 + read-write + 0x00000001 + + + LATENCY + Latency setting + 0 + 0 + + + LowPower + Low power setting, for signals with minimum hold time tGPIOTE,HOLD,LP; refer to Electrical specification section + 0 + + + LowLatency + Low latency setting, for signals with minimum hold time tGPIOTE,HOLD,LL; refer to Electrical specification section + 1 + + + + + + + 0x8 + 0x4 + CONFIG[%s] + Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event + 0x510 + read-write + + + MODE + Mode + 0 + 1 + + + Disabled + Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. + 0 + + + Event + Event mode + 1 + + + Task + Task mode + 3 + + + + + PSEL + GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event + 8 + 12 + + + PORT + Port number + 13 + 13 + + + POLARITY + When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. + 16 + 17 + + + None + Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. + 0 + + + LoToHi + Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. + 1 + + + HiToLo + Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. + 2 + + + Toggle + Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. + 3 + + + + + OUTINIT + When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. + 20 + 20 + + + Low + Task mode: Initial value of pin before task triggering is low + 0 + + + High + Task mode: Initial value of pin before task triggering is high + 1 + + + + + + + + + SAADC_NS + Analog to Digital Converter 0 + 0x4000E000 + SAADC + + + + 0 + 0x1000 + registers + + + SAADC + 14 + + SAADC + 0x20 + + + TASKS_START + Start the ADC and prepare the result buffer in RAM + 0x000 + write-only + + + TASKS_START + Start the ADC and prepare the result buffer in RAM + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SAMPLE + Take one ADC sample, if scan is enabled all channels are sampled + 0x004 + write-only + + + TASKS_SAMPLE + Take one ADC sample, if scan is enabled all channels are sampled + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop the ADC and terminate any ongoing conversion + 0x008 + write-only + + + TASKS_STOP + Stop the ADC and terminate any ongoing conversion + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CALIBRATEOFFSET + Starts offset auto-calibration + 0x00C + write-only + + + TASKS_CALIBRATEOFFSET + Starts offset auto-calibration + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_SAMPLE + Subscribe configuration for task SAMPLE + 0x084 + read-write + + + CHIDX + DPPI channel that task SAMPLE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x088 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_CALIBRATEOFFSET + Subscribe configuration for task CALIBRATEOFFSET + 0x08C + read-write + + + CHIDX + DPPI channel that task CALIBRATEOFFSET will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_STARTED + The ADC has started + 0x100 + read-write + + + EVENTS_STARTED + The ADC has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_END + The ADC has filled up the Result buffer + 0x104 + read-write + + + EVENTS_END + The ADC has filled up the Result buffer + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DONE + A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. + 0x108 + read-write + + + EVENTS_DONE + A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RESULTDONE + A result is ready to get transferred to RAM + 0x10C + read-write + + + EVENTS_RESULTDONE + A result is ready to get transferred to RAM + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CALIBRATEDONE + Calibration is complete + 0x110 + read-write + + + EVENTS_CALIBRATEDONE + Calibration is complete + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STOPPED + The ADC has stopped + 0x114 + read-write + + + EVENTS_STOPPED + The ADC has stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 8 + 0x008 + EVENTS_CH[%s] + Peripheral events. + SAADC_EVENTS_CH + read-write + 0x118 + + LIMITH + Description cluster: Last results is equal or above CH[n].LIMIT.HIGH + 0x000 + read-write + + + LIMITH + Last results is equal or above CH[n].LIMIT.HIGH + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + LIMITL + Description cluster: Last results is equal or below CH[n].LIMIT.LOW + 0x004 + read-write + + + LIMITL + Last results is equal or below CH[n].LIMIT.LOW + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + + PUBLISH_STARTED + Publish configuration for event STARTED + 0x180 + read-write + + + CHIDX + DPPI channel that event STARTED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x184 + read-write + + + CHIDX + DPPI channel that event END will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_DONE + Publish configuration for event DONE + 0x188 + read-write + + + CHIDX + DPPI channel that event DONE will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_RESULTDONE + Publish configuration for event RESULTDONE + 0x18C + read-write + + + CHIDX + DPPI channel that event RESULTDONE will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_CALIBRATEDONE + Publish configuration for event CALIBRATEDONE + 0x190 + read-write + + + CHIDX + DPPI channel that event CALIBRATEDONE will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x194 + read-write + + + CHIDX + DPPI channel that event STOPPED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + 8 + 0x008 + PUBLISH_CH[%s] + Publish configuration for events + SAADC_PUBLISH_CH + read-write + 0x198 + + LIMITH + Description cluster: Publish configuration for event CH[n].LIMITH + 0x000 + read-write + + + CHIDX + DPPI channel that event CH[n].LIMITH will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + LIMITL + Description cluster: Publish configuration for event CH[n].LIMITL + 0x004 + read-write + + + CHIDX + DPPI channel that event CH[n].LIMITL will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STARTED + Enable or disable interrupt for event STARTED + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + END + Enable or disable interrupt for event END + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + DONE + Enable or disable interrupt for event DONE + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RESULTDONE + Enable or disable interrupt for event RESULTDONE + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CALIBRATEDONE + Enable or disable interrupt for event CALIBRATEDONE + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + STOPPED + Enable or disable interrupt for event STOPPED + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH0LIMITH + Enable or disable interrupt for event CH0LIMITH + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH0LIMITL + Enable or disable interrupt for event CH0LIMITL + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH1LIMITH + Enable or disable interrupt for event CH1LIMITH + 8 + 8 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH1LIMITL + Enable or disable interrupt for event CH1LIMITL + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH2LIMITH + Enable or disable interrupt for event CH2LIMITH + 10 + 10 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH2LIMITL + Enable or disable interrupt for event CH2LIMITL + 11 + 11 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH3LIMITH + Enable or disable interrupt for event CH3LIMITH + 12 + 12 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH3LIMITL + Enable or disable interrupt for event CH3LIMITL + 13 + 13 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH4LIMITH + Enable or disable interrupt for event CH4LIMITH + 14 + 14 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH4LIMITL + Enable or disable interrupt for event CH4LIMITL + 15 + 15 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH5LIMITH + Enable or disable interrupt for event CH5LIMITH + 16 + 16 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH5LIMITL + Enable or disable interrupt for event CH5LIMITL + 17 + 17 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH6LIMITH + Enable or disable interrupt for event CH6LIMITH + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH6LIMITL + Enable or disable interrupt for event CH6LIMITL + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH7LIMITH + Enable or disable interrupt for event CH7LIMITH + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH7LIMITL + Enable or disable interrupt for event CH7LIMITL + 21 + 21 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STARTED + Write '1' to enable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + END + Write '1' to enable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DONE + Write '1' to enable interrupt for event DONE + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RESULTDONE + Write '1' to enable interrupt for event RESULTDONE + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CALIBRATEDONE + Write '1' to enable interrupt for event CALIBRATEDONE + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH0LIMITH + Write '1' to enable interrupt for event CH0LIMITH + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH0LIMITL + Write '1' to enable interrupt for event CH0LIMITL + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH1LIMITH + Write '1' to enable interrupt for event CH1LIMITH + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH1LIMITL + Write '1' to enable interrupt for event CH1LIMITL + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH2LIMITH + Write '1' to enable interrupt for event CH2LIMITH + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH2LIMITL + Write '1' to enable interrupt for event CH2LIMITL + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH3LIMITH + Write '1' to enable interrupt for event CH3LIMITH + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH3LIMITL + Write '1' to enable interrupt for event CH3LIMITL + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH4LIMITH + Write '1' to enable interrupt for event CH4LIMITH + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH4LIMITL + Write '1' to enable interrupt for event CH4LIMITL + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH5LIMITH + Write '1' to enable interrupt for event CH5LIMITH + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH5LIMITL + Write '1' to enable interrupt for event CH5LIMITL + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH6LIMITH + Write '1' to enable interrupt for event CH6LIMITH + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH6LIMITL + Write '1' to enable interrupt for event CH6LIMITL + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH7LIMITH + Write '1' to enable interrupt for event CH7LIMITH + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH7LIMITL + Write '1' to enable interrupt for event CH7LIMITL + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STARTED + Write '1' to disable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + END + Write '1' to disable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DONE + Write '1' to disable interrupt for event DONE + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RESULTDONE + Write '1' to disable interrupt for event RESULTDONE + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CALIBRATEDONE + Write '1' to disable interrupt for event CALIBRATEDONE + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH0LIMITH + Write '1' to disable interrupt for event CH0LIMITH + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH0LIMITL + Write '1' to disable interrupt for event CH0LIMITL + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH1LIMITH + Write '1' to disable interrupt for event CH1LIMITH + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH1LIMITL + Write '1' to disable interrupt for event CH1LIMITL + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH2LIMITH + Write '1' to disable interrupt for event CH2LIMITH + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH2LIMITL + Write '1' to disable interrupt for event CH2LIMITL + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH3LIMITH + Write '1' to disable interrupt for event CH3LIMITH + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH3LIMITL + Write '1' to disable interrupt for event CH3LIMITL + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH4LIMITH + Write '1' to disable interrupt for event CH4LIMITH + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH4LIMITL + Write '1' to disable interrupt for event CH4LIMITL + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH5LIMITH + Write '1' to disable interrupt for event CH5LIMITH + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH5LIMITL + Write '1' to disable interrupt for event CH5LIMITL + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH6LIMITH + Write '1' to disable interrupt for event CH6LIMITH + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH6LIMITL + Write '1' to disable interrupt for event CH6LIMITL + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH7LIMITH + Write '1' to disable interrupt for event CH7LIMITH + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH7LIMITL + Write '1' to disable interrupt for event CH7LIMITL + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + STATUS + Status + 0x400 + read-only + + + STATUS + Status + 0 + 0 + + + Ready + ADC is ready. No ongoing conversion. + 0 + + + Busy + ADC is busy. Single conversion in progress. + 1 + + + + + + + ENABLE + Enable or disable ADC + 0x500 + read-write + + + ENABLE + Enable or disable ADC + 0 + 0 + + + Disabled + Disable ADC + 0 + + + Enabled + Enable ADC + 1 + + + + + + + 8 + 0x010 + CH[%s] + Unspecified + SAADC_CH + read-write + 0x510 + + PSELP + Description cluster: Input positive pin selection for CH[n] + 0x000 + read-write + 0x00000000 + + + PSELP + Analog positive input channel + 0 + 4 + + + NC + Not connected + 0 + + + AnalogInput0 + AIN0 + 1 + + + AnalogInput1 + AIN1 + 2 + + + AnalogInput2 + AIN2 + 3 + + + AnalogInput3 + AIN3 + 4 + + + AnalogInput4 + AIN4 + 5 + + + AnalogInput5 + AIN5 + 6 + + + AnalogInput6 + AIN6 + 7 + + + AnalogInput7 + AIN7 + 8 + + + VDD + VDD + 9 + + + VDDHDIV5 + VDDH/5 + 0xD + + + + + + + PSELN + Description cluster: Input negative pin selection for CH[n] + 0x004 + read-write + 0x00000000 + + + PSELN + Analog negative input, enables differential channel + 0 + 4 + + + NC + Not connected + 0 + + + AnalogInput0 + AIN0 + 1 + + + AnalogInput1 + AIN1 + 2 + + + AnalogInput2 + AIN2 + 3 + + + AnalogInput3 + AIN3 + 4 + + + AnalogInput4 + AIN4 + 5 + + + AnalogInput5 + AIN5 + 6 + + + AnalogInput6 + AIN6 + 7 + + + AnalogInput7 + AIN7 + 8 + + + VDD + VDD + 9 + + + VDDHDIV5 + VDDH/5 + 0xD + + + + + + + CONFIG + Description cluster: Input configuration for CH[n] + 0x008 + read-write + 0x00020000 + + + RESP + Positive channel resistor control + 0 + 1 + + + Bypass + Bypass resistor ladder + 0 + + + Pulldown + Pull-down to GND + 1 + + + Pullup + Pull-up to VDD + 2 + + + VDD1_2 + Set input at VDD/2 + 3 + + + + + RESN + Negative channel resistor control + 4 + 5 + + + Bypass + Bypass resistor ladder + 0 + + + Pulldown + Pull-down to GND + 1 + + + Pullup + Pull-up to VDD + 2 + + + VDD1_2 + Set input at VDD/2 + 3 + + + + + GAIN + Gain control + 8 + 10 + + + Gain1_6 + 1/6 + 0 + + + Gain1_5 + 1/5 + 1 + + + Gain1_4 + 1/4 + 2 + + + Gain1_3 + 1/3 + 3 + + + Gain1_2 + 1/2 + 4 + + + Gain1 + 1 + 5 + + + Gain2 + 2 + 6 + + + Gain4 + 4 + 7 + + + + + REFSEL + Reference control + 12 + 12 + + + Internal + Internal reference (0.6 V) + 0 + + + VDD1_4 + VDD/4 as reference + 1 + + + + + TACQ + Acquisition time, the time the ADC uses to sample the input voltage + 16 + 18 + + + 3us + 3 us + 0 + + + 5us + 5 us + 1 + + + 10us + 10 us + 2 + + + 15us + 15 us + 3 + + + 20us + 20 us + 4 + + + 40us + 40 us + 5 + + + + + MODE + Enable differential mode + 20 + 20 + + + SE + Single-ended, PSELN will be ignored, negative input to ADC shorted to GND + 0 + + + Diff + Differential + 1 + + + + + BURST + Enable burst mode + 24 + 24 + + + Disabled + Burst mode is disabled (normal operation) + 0 + + + Enabled + Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. + 1 + + + + + + + LIMIT + Description cluster: High/low limits for event monitoring a channel + 0x00C + read-write + 0x7FFF8000 + + + LOW + Low level limit + 0 + 15 + + + HIGH + High level limit + 16 + 31 + + + + + + RESOLUTION + Resolution configuration + 0x5F0 + read-write + 0x00000001 + + + VAL + Set the resolution + 0 + 2 + + + 8bit + 8 bit + 0 + + + 10bit + 10 bit + 1 + + + 12bit + 12 bit + 2 + + + 14bit + 14 bit + 3 + + + + + + + OVERSAMPLE + Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. + 0x5F4 + read-write + + + OVERSAMPLE + Oversample control + 0 + 3 + + + Bypass + Bypass oversampling + 0 + + + Over2x + Oversample 2x + 1 + + + Over4x + Oversample 4x + 2 + + + Over8x + Oversample 8x + 3 + + + Over16x + Oversample 16x + 4 + + + Over32x + Oversample 32x + 5 + + + Over64x + Oversample 64x + 6 + + + Over128x + Oversample 128x + 7 + + + Over256x + Oversample 256x + 8 + + + + + + + SAMPLERATE + Controls normal or continuous sample rate + 0x5F8 + read-write + + + CC + Capture and compare value; sample rate is 16 MHz/CC + 0 + 10 + + + MODE + Select mode for sample rate control + 12 + 12 + + + Task + Rate is controlled from SAMPLE task + 0 + + + Timers + Rate is controlled from local timer (use CC to control the rate) + 1 + + + + + + + RESULT + RESULT EasyDMA channel + SAADC_RESULT + read-write + 0x62C + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of buffer words to transfer + 0x004 + read-write + + + MAXCNT + Maximum number of buffer words to transfer + 0 + 14 + + + + + AMOUNT + Number of buffer words transferred since last START + 0x008 + read-only + + + AMOUNT + Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. + 0 + 14 + + + + + + + + SAADC_S + Analog to Digital Converter 1 + 0x5000E000 + + + + SAADC + 14 + + + + TIMER0_NS + Timer/Counter 0 + 0x4000F000 + TIMER + + + + 0 + 0x1000 + registers + + + TIMER0 + 15 + + TIMER + 0x20 + + + TASKS_START + Start Timer + 0x000 + write-only + + + TASKS_START + Start Timer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop Timer + 0x004 + write-only + + + TASKS_STOP + Stop Timer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_COUNT + Increment Timer (Counter mode only) + 0x008 + write-only + + + TASKS_COUNT + Increment Timer (Counter mode only) + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CLEAR + Clear time + 0x00C + write-only + + + TASKS_CLEAR + Clear time + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SHUTDOWN + Deprecated register - Shut down timer + 0x010 + write-only + + + TASKS_SHUTDOWN + Deprecated field - Shut down timer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x6 + 0x4 + TASKS_CAPTURE[%s] + Description collection: Capture Timer value to CC[n] register + 0x040 + write-only + + + TASKS_CAPTURE + Capture Timer value to CC[n] register + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_COUNT + Subscribe configuration for task COUNT + 0x088 + read-write + + + CHIDX + DPPI channel that task COUNT will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_CLEAR + Subscribe configuration for task CLEAR + 0x08C + read-write + + + CHIDX + DPPI channel that task CLEAR will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_SHUTDOWN + Deprecated register - Subscribe configuration for task SHUTDOWN + 0x090 + read-write + + + CHIDX + DPPI channel that task SHUTDOWN will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + 0x6 + 0x4 + SUBSCRIBE_CAPTURE[%s] + Description collection: Subscribe configuration for task CAPTURE[n] + 0x0C0 + read-write + + + CHIDX + DPPI channel that task CAPTURE[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + 0x6 + 0x4 + EVENTS_COMPARE[%s] + Description collection: Compare event on CC[n] match + 0x140 + read-write + + + EVENTS_COMPARE + Compare event on CC[n] match + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x6 + 0x4 + PUBLISH_COMPARE[%s] + Description collection: Publish configuration for event COMPARE[n] + 0x1C0 + read-write + + + CHIDX + DPPI channel that event COMPARE[n] will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + COMPARE0_CLEAR + Shortcut between event COMPARE[0] and task CLEAR + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE1_CLEAR + Shortcut between event COMPARE[1] and task CLEAR + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE2_CLEAR + Shortcut between event COMPARE[2] and task CLEAR + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE3_CLEAR + Shortcut between event COMPARE[3] and task CLEAR + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE4_CLEAR + Shortcut between event COMPARE[4] and task CLEAR + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE5_CLEAR + Shortcut between event COMPARE[5] and task CLEAR + 5 + 5 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE0_STOP + Shortcut between event COMPARE[0] and task STOP + 16 + 16 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE1_STOP + Shortcut between event COMPARE[1] and task STOP + 17 + 17 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE2_STOP + Shortcut between event COMPARE[2] and task STOP + 18 + 18 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE3_STOP + Shortcut between event COMPARE[3] and task STOP + 19 + 19 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE4_STOP + Shortcut between event COMPARE[4] and task STOP + 20 + 20 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE5_STOP + Shortcut between event COMPARE[5] and task STOP + 21 + 21 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 16 + 16 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 17 + 17 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 21 + 21 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + MODE + Timer mode selection + 0x504 + read-write + + + MODE + Timer mode + 0 + 1 + + + Timer + Select Timer mode + 0 + + + Counter + Deprecated enumerator - Select Counter mode + 1 + + + LowPowerCounter + Select Low Power Counter mode + 2 + + + + + + + BITMODE + Configure the number of bits used by the TIMER + 0x508 + read-write + + + BITMODE + Timer bit width + 0 + 1 + + + 16Bit + 16 bit timer bit width + 0 + + + 08Bit + 8 bit timer bit width + 1 + + + 24Bit + 24 bit timer bit width + 2 + + + 32Bit + 32 bit timer bit width + 3 + + + + + + + PRESCALER + Timer prescaler register + 0x510 + read-write + 0x00000004 + + + PRESCALER + Prescaler value + 0 + 3 + + + + + 0x6 + 0x4 + CC[%s] + Description collection: Capture/Compare register n + 0x540 + read-write + + + CC + Capture/Compare value + 0 + 31 + + + + + 0x6 + 0x4 + ONESHOTEN[%s] + Description collection: Enable one-shot operation for Capture/Compare channel n + 0x580 + read-write + + + ONESHOTEN + Enable one-shot operation + 0 + 0 + + + Disable + Disable one-shot operation + 0 + + + Enable + Enable one-shot operation + 1 + + + + + + + + + TIMER0_S + Timer/Counter 1 + 0x5000F000 + + + + TIMER0 + 15 + + + + TIMER1_NS + Timer/Counter 2 + 0x40010000 + + + + TIMER1 + 16 + + + + TIMER1_S + Timer/Counter 3 + 0x50010000 + + + + TIMER1 + 16 + + + + TIMER2_NS + Timer/Counter 4 + 0x40011000 + + + + TIMER2 + 17 + + + + TIMER2_S + Timer/Counter 5 + 0x50011000 + + + + TIMER2 + 17 + + + + RTC0_NS + Real-time counter 0 + 0x40014000 + RTC + + + + 0 + 0x1000 + registers + + + RTC0 + 20 + + RTC + 0x20 + + + TASKS_START + Start RTC counter + 0x000 + write-only + + + TASKS_START + Start RTC counter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop RTC counter + 0x004 + write-only + + + TASKS_STOP + Stop RTC counter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CLEAR + Clear RTC counter + 0x008 + write-only + + + TASKS_CLEAR + Clear RTC counter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_TRIGOVRFLW + Set counter to 0xFFFFF0 + 0x00C + write-only + + + TASKS_TRIGOVRFLW + Set counter to 0xFFFFF0 + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x4 + 0x4 + TASKS_CAPTURE[%s] + Description collection: Capture RTC counter to CC[n] register + 0x040 + write-only + + + TASKS_CAPTURE + Capture RTC counter to CC[n] register + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_CLEAR + Subscribe configuration for task CLEAR + 0x088 + read-write + + + CHIDX + DPPI channel that task CLEAR will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_TRIGOVRFLW + Subscribe configuration for task TRIGOVRFLW + 0x08C + read-write + + + CHIDX + DPPI channel that task TRIGOVRFLW will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + 0x4 + 0x4 + SUBSCRIBE_CAPTURE[%s] + Description collection: Subscribe configuration for task CAPTURE[n] + 0x0C0 + read-write + + + CHIDX + DPPI channel that task CAPTURE[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_TICK + Event on counter increment + 0x100 + read-write + + + EVENTS_TICK + Event on counter increment + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_OVRFLW + Event on counter overflow + 0x104 + read-write + + + EVENTS_OVRFLW + Event on counter overflow + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x4 + 0x4 + EVENTS_COMPARE[%s] + Description collection: Compare event on CC[n] match + 0x140 + read-write + + + EVENTS_COMPARE + Compare event on CC[n] match + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_TICK + Publish configuration for event TICK + 0x180 + read-write + + + CHIDX + DPPI channel that event TICK will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_OVRFLW + Publish configuration for event OVRFLW + 0x184 + read-write + + + CHIDX + DPPI channel that event OVRFLW will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + 0x4 + 0x4 + PUBLISH_COMPARE[%s] + Description collection: Publish configuration for event COMPARE[n] + 0x1C0 + read-write + + + CHIDX + DPPI channel that event COMPARE[n] will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + COMPARE0_CLEAR + Shortcut between event COMPARE[0] and task CLEAR + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE1_CLEAR + Shortcut between event COMPARE[1] and task CLEAR + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE2_CLEAR + Shortcut between event COMPARE[2] and task CLEAR + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE3_CLEAR + Shortcut between event COMPARE[3] and task CLEAR + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + TICK + Write '1' to enable interrupt for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + OVRFLW + Write '1' to enable interrupt for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + TICK + Write '1' to disable interrupt for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + OVRFLW + Write '1' to disable interrupt for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + EVTEN + Enable or disable event routing + 0x340 + read-write + + + TICK + Enable or disable event routing for event TICK + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + OVRFLW + Enable or disable event routing for event OVRFLW + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COMPARE0 + Enable or disable event routing for event COMPARE[0] + 16 + 16 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COMPARE1 + Enable or disable event routing for event COMPARE[1] + 17 + 17 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COMPARE2 + Enable or disable event routing for event COMPARE[2] + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COMPARE3 + Enable or disable event routing for event COMPARE[3] + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + EVTENSET + Enable event routing + 0x344 + read-write + + + TICK + Write '1' to enable event routing for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + OVRFLW + Write '1' to enable event routing for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE0 + Write '1' to enable event routing for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE1 + Write '1' to enable event routing for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE2 + Write '1' to enable event routing for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE3 + Write '1' to enable event routing for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + EVTENCLR + Disable event routing + 0x348 + read-write + + + TICK + Write '1' to disable event routing for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + OVRFLW + Write '1' to disable event routing for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE0 + Write '1' to disable event routing for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE1 + Write '1' to disable event routing for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE2 + Write '1' to disable event routing for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE3 + Write '1' to disable event routing for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + COUNTER + Current counter value + 0x504 + read-only + + + COUNTER + Counter value + 0 + 23 + + + + + PRESCALER + 12-bit prescaler for counter frequency (32768 / (PRESCALER + 1)). Must be written when RTC is stopped. + 0x508 + read-write + + + PRESCALER + Prescaler value + 0 + 11 + + + + + 0x4 + 0x4 + CC[%s] + Description collection: Compare register n + 0x540 + read-write + + + COMPARE + Compare value + 0 + 23 + + + + + + + RTC0_S + Real-time counter 1 + 0x50014000 + + + + RTC0 + 20 + + + + RTC1_NS + Real-time counter 2 + 0x40015000 + + + + RTC1 + 21 + + + + RTC1_S + Real-time counter 3 + 0x50015000 + + + + RTC1 + 21 + + + + DPPIC_NS + Distributed programmable peripheral interconnect controller 0 + 0x40017000 + DPPIC + + + + 0 + 0x1000 + registers + + DPPIC + 0x20 + + + 6 + 0x008 + TASKS_CHG[%s] + Channel group tasks + DPPIC_TASKS_CHG + write-only + 0x000 + + EN + Description cluster: Enable channel group n + 0x000 + write-only + + + EN + Enable channel group n + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + DIS + Description cluster: Disable channel group n + 0x004 + write-only + + + DIS + Disable channel group n + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + + 6 + 0x008 + SUBSCRIBE_CHG[%s] + Subscribe configuration for tasks + DPPIC_SUBSCRIBE_CHG + read-write + 0x080 + + EN + Description cluster: Subscribe configuration for task CHG[n].EN + 0x000 + read-write + + + CHIDX + DPPI channel that task CHG[n].EN will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + DIS + Description cluster: Subscribe configuration for task CHG[n].DIS + 0x004 + read-write + + + CHIDX + DPPI channel that task CHG[n].DIS will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + + CHEN + Channel enable register + 0x500 + read-write + + + CH0 + Enable or disable channel 0 + 0 + 0 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH1 + Enable or disable channel 1 + 1 + 1 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH2 + Enable or disable channel 2 + 2 + 2 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH3 + Enable or disable channel 3 + 3 + 3 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH4 + Enable or disable channel 4 + 4 + 4 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH5 + Enable or disable channel 5 + 5 + 5 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH6 + Enable or disable channel 6 + 6 + 6 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH7 + Enable or disable channel 7 + 7 + 7 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH8 + Enable or disable channel 8 + 8 + 8 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH9 + Enable or disable channel 9 + 9 + 9 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH10 + Enable or disable channel 10 + 10 + 10 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH11 + Enable or disable channel 11 + 11 + 11 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH12 + Enable or disable channel 12 + 12 + 12 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH13 + Enable or disable channel 13 + 13 + 13 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH14 + Enable or disable channel 14 + 14 + 14 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH15 + Enable or disable channel 15 + 15 + 15 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH16 + Enable or disable channel 16 + 16 + 16 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH17 + Enable or disable channel 17 + 17 + 17 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH18 + Enable or disable channel 18 + 18 + 18 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH19 + Enable or disable channel 19 + 19 + 19 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH20 + Enable or disable channel 20 + 20 + 20 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH21 + Enable or disable channel 21 + 21 + 21 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH22 + Enable or disable channel 22 + 22 + 22 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH23 + Enable or disable channel 23 + 23 + 23 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH24 + Enable or disable channel 24 + 24 + 24 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH25 + Enable or disable channel 25 + 25 + 25 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH26 + Enable or disable channel 26 + 26 + 26 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH27 + Enable or disable channel 27 + 27 + 27 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH28 + Enable or disable channel 28 + 28 + 28 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH29 + Enable or disable channel 29 + 29 + 29 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH30 + Enable or disable channel 30 + 30 + 30 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH31 + Enable or disable channel 31 + 31 + 31 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + + + CHENSET + Channel enable set register + 0x504 + read-write + oneToSet + + + CH0 + Channel 0 enable set register. Writing 0 has no effect. + 0 + 0 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH1 + Channel 1 enable set register. Writing 0 has no effect. + 1 + 1 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH2 + Channel 2 enable set register. Writing 0 has no effect. + 2 + 2 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH3 + Channel 3 enable set register. Writing 0 has no effect. + 3 + 3 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH4 + Channel 4 enable set register. Writing 0 has no effect. + 4 + 4 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH5 + Channel 5 enable set register. Writing 0 has no effect. + 5 + 5 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH6 + Channel 6 enable set register. Writing 0 has no effect. + 6 + 6 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH7 + Channel 7 enable set register. Writing 0 has no effect. + 7 + 7 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH8 + Channel 8 enable set register. Writing 0 has no effect. + 8 + 8 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH9 + Channel 9 enable set register. Writing 0 has no effect. + 9 + 9 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH10 + Channel 10 enable set register. Writing 0 has no effect. + 10 + 10 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH11 + Channel 11 enable set register. Writing 0 has no effect. + 11 + 11 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH12 + Channel 12 enable set register. Writing 0 has no effect. + 12 + 12 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH13 + Channel 13 enable set register. Writing 0 has no effect. + 13 + 13 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH14 + Channel 14 enable set register. Writing 0 has no effect. + 14 + 14 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH15 + Channel 15 enable set register. Writing 0 has no effect. + 15 + 15 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH16 + Channel 16 enable set register. Writing 0 has no effect. + 16 + 16 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH17 + Channel 17 enable set register. Writing 0 has no effect. + 17 + 17 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH18 + Channel 18 enable set register. Writing 0 has no effect. + 18 + 18 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH19 + Channel 19 enable set register. Writing 0 has no effect. + 19 + 19 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH20 + Channel 20 enable set register. Writing 0 has no effect. + 20 + 20 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH21 + Channel 21 enable set register. Writing 0 has no effect. + 21 + 21 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH22 + Channel 22 enable set register. Writing 0 has no effect. + 22 + 22 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH23 + Channel 23 enable set register. Writing 0 has no effect. + 23 + 23 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH24 + Channel 24 enable set register. Writing 0 has no effect. + 24 + 24 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH25 + Channel 25 enable set register. Writing 0 has no effect. + 25 + 25 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH26 + Channel 26 enable set register. Writing 0 has no effect. + 26 + 26 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH27 + Channel 27 enable set register. Writing 0 has no effect. + 27 + 27 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH28 + Channel 28 enable set register. Writing 0 has no effect. + 28 + 28 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH29 + Channel 29 enable set register. Writing 0 has no effect. + 29 + 29 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH30 + Channel 30 enable set register. Writing 0 has no effect. + 30 + 30 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH31 + Channel 31 enable set register. Writing 0 has no effect. + 31 + 31 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + + + CHENCLR + Channel enable clear register + 0x508 + read-write + oneToClear + + + CH0 + Channel 0 enable clear register. Writing 0 has no effect. + 0 + 0 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH1 + Channel 1 enable clear register. Writing 0 has no effect. + 1 + 1 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH2 + Channel 2 enable clear register. Writing 0 has no effect. + 2 + 2 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH3 + Channel 3 enable clear register. Writing 0 has no effect. + 3 + 3 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH4 + Channel 4 enable clear register. Writing 0 has no effect. + 4 + 4 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH5 + Channel 5 enable clear register. Writing 0 has no effect. + 5 + 5 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH6 + Channel 6 enable clear register. Writing 0 has no effect. + 6 + 6 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH7 + Channel 7 enable clear register. Writing 0 has no effect. + 7 + 7 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH8 + Channel 8 enable clear register. Writing 0 has no effect. + 8 + 8 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH9 + Channel 9 enable clear register. Writing 0 has no effect. + 9 + 9 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH10 + Channel 10 enable clear register. Writing 0 has no effect. + 10 + 10 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH11 + Channel 11 enable clear register. Writing 0 has no effect. + 11 + 11 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH12 + Channel 12 enable clear register. Writing 0 has no effect. + 12 + 12 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH13 + Channel 13 enable clear register. Writing 0 has no effect. + 13 + 13 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH14 + Channel 14 enable clear register. Writing 0 has no effect. + 14 + 14 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH15 + Channel 15 enable clear register. Writing 0 has no effect. + 15 + 15 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH16 + Channel 16 enable clear register. Writing 0 has no effect. + 16 + 16 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH17 + Channel 17 enable clear register. Writing 0 has no effect. + 17 + 17 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH18 + Channel 18 enable clear register. Writing 0 has no effect. + 18 + 18 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH19 + Channel 19 enable clear register. Writing 0 has no effect. + 19 + 19 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH20 + Channel 20 enable clear register. Writing 0 has no effect. + 20 + 20 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH21 + Channel 21 enable clear register. Writing 0 has no effect. + 21 + 21 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH22 + Channel 22 enable clear register. Writing 0 has no effect. + 22 + 22 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH23 + Channel 23 enable clear register. Writing 0 has no effect. + 23 + 23 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH24 + Channel 24 enable clear register. Writing 0 has no effect. + 24 + 24 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH25 + Channel 25 enable clear register. Writing 0 has no effect. + 25 + 25 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH26 + Channel 26 enable clear register. Writing 0 has no effect. + 26 + 26 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH27 + Channel 27 enable clear register. Writing 0 has no effect. + 27 + 27 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH28 + Channel 28 enable clear register. Writing 0 has no effect. + 28 + 28 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH29 + Channel 29 enable clear register. Writing 0 has no effect. + 29 + 29 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH30 + Channel 30 enable clear register. Writing 0 has no effect. + 30 + 30 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH31 + Channel 31 enable clear register. Writing 0 has no effect. + 31 + 31 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + + + 0x6 + 0x4 + CHG[%s] + Description collection: Channel group n Note: Writes to this register are ignored if either SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS is enabled + 0x800 + read-write + + + CH0 + Include or exclude channel 0 + 0 + 0 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH1 + Include or exclude channel 1 + 1 + 1 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH2 + Include or exclude channel 2 + 2 + 2 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH3 + Include or exclude channel 3 + 3 + 3 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH4 + Include or exclude channel 4 + 4 + 4 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH5 + Include or exclude channel 5 + 5 + 5 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH6 + Include or exclude channel 6 + 6 + 6 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH7 + Include or exclude channel 7 + 7 + 7 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH8 + Include or exclude channel 8 + 8 + 8 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH9 + Include or exclude channel 9 + 9 + 9 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH10 + Include or exclude channel 10 + 10 + 10 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH11 + Include or exclude channel 11 + 11 + 11 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH12 + Include or exclude channel 12 + 12 + 12 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH13 + Include or exclude channel 13 + 13 + 13 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH14 + Include or exclude channel 14 + 14 + 14 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH15 + Include or exclude channel 15 + 15 + 15 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH16 + Include or exclude channel 16 + 16 + 16 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH17 + Include or exclude channel 17 + 17 + 17 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH18 + Include or exclude channel 18 + 18 + 18 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH19 + Include or exclude channel 19 + 19 + 19 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH20 + Include or exclude channel 20 + 20 + 20 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH21 + Include or exclude channel 21 + 21 + 21 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH22 + Include or exclude channel 22 + 22 + 22 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH23 + Include or exclude channel 23 + 23 + 23 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH24 + Include or exclude channel 24 + 24 + 24 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH25 + Include or exclude channel 25 + 25 + 25 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH26 + Include or exclude channel 26 + 26 + 26 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH27 + Include or exclude channel 27 + 27 + 27 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH28 + Include or exclude channel 28 + 28 + 28 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH29 + Include or exclude channel 29 + 29 + 29 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH30 + Include or exclude channel 30 + 30 + 30 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH31 + Include or exclude channel 31 + 31 + 31 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + + + + + DPPIC_S + Distributed programmable peripheral interconnect controller 1 + 0x50017000 + + + + + WDT0_NS + Watchdog Timer 0 + 0x40018000 + WDT + + + + 0 + 0x1000 + registers + + + WDT0 + 24 + + WDT + 0x20 + + + TASKS_START + Start WDT + 0x000 + write-only + + + TASKS_START + Start WDT + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop WDT + 0x004 + write-only + + + TASKS_STOP + Stop WDT + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_TIMEOUT + Watchdog timeout + 0x100 + read-write + + + EVENTS_TIMEOUT + Watchdog timeout + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STOPPED + Watchdog stopped + 0x104 + read-write + + + EVENTS_STOPPED + Watchdog stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_TIMEOUT + Publish configuration for event TIMEOUT + 0x180 + read-write + + + CHIDX + DPPI channel that event TIMEOUT will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + + + CHIDX + DPPI channel that event STOPPED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + TIMEOUT + Write '1' to enable interrupt for event TIMEOUT + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + TIMEOUT + Write '1' to disable interrupt for event TIMEOUT + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + NMIENSET + Enable interrupt + 0x324 + read-write + + + TIMEOUT + Write '1' to enable interrupt for event TIMEOUT + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + NMIENCLR + Disable interrupt + 0x328 + read-write + + + TIMEOUT + Write '1' to disable interrupt for event TIMEOUT + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + RUNSTATUS + Run status + 0x400 + read-only + + + RUNSTATUSWDT + Indicates whether or not WDT is running + 0 + 0 + + + NotRunning + Watchdog is not running + 0 + + + Running + Watchdog is running + 1 + + + + + + + REQSTATUS + Request status + 0x404 + read-only + 0x00000001 + + + RR0 + Request status for RR[0] register + 0 + 0 + + + DisabledOrRequested + RR[0] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[0] register is enabled, and are not yet requesting reload + 1 + + + + + RR1 + Request status for RR[1] register + 1 + 1 + + + DisabledOrRequested + RR[1] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[1] register is enabled, and are not yet requesting reload + 1 + + + + + RR2 + Request status for RR[2] register + 2 + 2 + + + DisabledOrRequested + RR[2] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[2] register is enabled, and are not yet requesting reload + 1 + + + + + RR3 + Request status for RR[3] register + 3 + 3 + + + DisabledOrRequested + RR[3] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[3] register is enabled, and are not yet requesting reload + 1 + + + + + RR4 + Request status for RR[4] register + 4 + 4 + + + DisabledOrRequested + RR[4] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[4] register is enabled, and are not yet requesting reload + 1 + + + + + RR5 + Request status for RR[5] register + 5 + 5 + + + DisabledOrRequested + RR[5] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[5] register is enabled, and are not yet requesting reload + 1 + + + + + RR6 + Request status for RR[6] register + 6 + 6 + + + DisabledOrRequested + RR[6] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[6] register is enabled, and are not yet requesting reload + 1 + + + + + RR7 + Request status for RR[7] register + 7 + 7 + + + DisabledOrRequested + RR[7] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[7] register is enabled, and are not yet requesting reload + 1 + + + + + + + CRV + Counter reload value + 0x504 + read-write + 0xFFFFFFFF + + + CRV + Counter reload value in number of cycles of the 32.768 kHz clock + 0 + 31 + + + + + RREN + Enable register for reload request registers + 0x508 + read-write + 0x00000001 + + + RR0 + Enable or disable RR[0] register + 0 + 0 + + + Disabled + Disable RR[0] register + 0 + + + Enabled + Enable RR[0] register + 1 + + + + + RR1 + Enable or disable RR[1] register + 1 + 1 + + + Disabled + Disable RR[1] register + 0 + + + Enabled + Enable RR[1] register + 1 + + + + + RR2 + Enable or disable RR[2] register + 2 + 2 + + + Disabled + Disable RR[2] register + 0 + + + Enabled + Enable RR[2] register + 1 + + + + + RR3 + Enable or disable RR[3] register + 3 + 3 + + + Disabled + Disable RR[3] register + 0 + + + Enabled + Enable RR[3] register + 1 + + + + + RR4 + Enable or disable RR[4] register + 4 + 4 + + + Disabled + Disable RR[4] register + 0 + + + Enabled + Enable RR[4] register + 1 + + + + + RR5 + Enable or disable RR[5] register + 5 + 5 + + + Disabled + Disable RR[5] register + 0 + + + Enabled + Enable RR[5] register + 1 + + + + + RR6 + Enable or disable RR[6] register + 6 + 6 + + + Disabled + Disable RR[6] register + 0 + + + Enabled + Enable RR[6] register + 1 + + + + + RR7 + Enable or disable RR[7] register + 7 + 7 + + + Disabled + Disable RR[7] register + 0 + + + Enabled + Enable RR[7] register + 1 + + + + + + + CONFIG + Configuration register + 0x50C + read-write + 0x00000001 + + + SLEEP + Configure WDT to either be paused, or kept running, while the CPU is sleeping + 0 + 0 + + + Pause + Pause WDT while the CPU is sleeping + 0 + + + Run + Keep WDT running while the CPU is sleeping + 1 + + + + + HALT + Configure WDT to either be paused, or kept running, while the CPU is halted by the debugger + 3 + 3 + + + Pause + Pause WDT while the CPU is halted by the debugger + 0 + + + Run + Keep WDT running while the CPU is halted by the debugger + 1 + + + + + STOPEN + Allow stopping WDT + 6 + 6 + + + Disable + Do not allow stopping WDT + 0 + + + Enable + Allow stopping WDT + 1 + + + + + + + TSEN + Task stop enable + 0x520 + write-only + 0x00000000 + + + TSEN + Allow stopping WDT + 0 + 31 + + + Enable + Value to allow stopping WDT + 0x6E524635 + + + + + + + 0x8 + 0x4 + RR[%s] + Description collection: Reload request n + 0x600 + write-only + + + RR + Reload request register + 0 + 31 + + + Reload + Value to request a reload of the watchdog timer + 0x6E524635 + + + + + + + + + WDT0_S + Watchdog Timer 1 + 0x50018000 + + + + WDT0 + 24 + + + + WDT1_NS + Watchdog Timer 2 + 0x40019000 + + + + WDT1 + 25 + + + + WDT1_S + Watchdog Timer 3 + 0x50019000 + + + + WDT1 + 25 + + + + COMP_NS + Comparator 0 + 0x4001A000 + COMP + + + + 0 + 0x1000 + registers + + + COMP_LPCOMP + 26 + + COMP + 0x20 + + + TASKS_START + Start comparator + 0x000 + write-only + + + TASKS_START + Start comparator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop comparator + 0x004 + write-only + + + TASKS_STOP + Stop comparator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SAMPLE + Sample comparator value + 0x008 + write-only + + + TASKS_SAMPLE + Sample comparator value + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_SAMPLE + Subscribe configuration for task SAMPLE + 0x088 + read-write + + + CHIDX + DPPI channel that task SAMPLE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_READY + COMP is ready and output is valid + 0x100 + read-write + + + EVENTS_READY + COMP is ready and output is valid + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DOWN + Downward crossing + 0x104 + read-write + + + EVENTS_DOWN + Downward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_UP + Upward crossing + 0x108 + read-write + + + EVENTS_UP + Upward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CROSS + Downward or upward crossing + 0x10C + read-write + + + EVENTS_CROSS + Downward or upward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_READY + Publish configuration for event READY + 0x180 + read-write + + + CHIDX + DPPI channel that event READY will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_DOWN + Publish configuration for event DOWN + 0x184 + read-write + + + CHIDX + DPPI channel that event DOWN will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_UP + Publish configuration for event UP + 0x188 + read-write + + + CHIDX + DPPI channel that event UP will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_CROSS + Publish configuration for event CROSS + 0x18C + read-write + + + CHIDX + DPPI channel that event CROSS will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + READY_SAMPLE + Shortcut between event READY and task SAMPLE + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + READY_STOP + Shortcut between event READY and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DOWN_STOP + Shortcut between event DOWN and task STOP + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + UP_STOP + Shortcut between event UP and task STOP + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + CROSS_STOP + Shortcut between event CROSS and task STOP + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + READY + Enable or disable interrupt for event READY + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + DOWN + Enable or disable interrupt for event DOWN + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + UP + Enable or disable interrupt for event UP + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CROSS + Enable or disable interrupt for event CROSS + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + READY + Write '1' to enable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DOWN + Write '1' to enable interrupt for event DOWN + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + UP + Write '1' to enable interrupt for event UP + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CROSS + Write '1' to enable interrupt for event CROSS + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + READY + Write '1' to disable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DOWN + Write '1' to disable interrupt for event DOWN + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + UP + Write '1' to disable interrupt for event UP + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CROSS + Write '1' to disable interrupt for event CROSS + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + RESULT + Compare result + 0x400 + read-only + + + RESULT + Result of last compare. Decision point SAMPLE task. + 0 + 0 + + + Below + Input voltage is below the threshold (VIN+ &lt; VIN-) + 0 + + + Above + Input voltage is above the threshold (VIN+ &gt; VIN-) + 1 + + + + + + + ENABLE + COMP enable + 0x500 + read-write + + + ENABLE + Enable or disable COMP + 0 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 2 + + + + + + + PSEL + Pin select + 0x504 + read-write + + + PSEL + Analog pin select + 0 + 2 + + + AnalogInput0 + AIN0 selected as analog input + 0 + + + AnalogInput1 + AIN1 selected as analog input + 1 + + + AnalogInput2 + AIN2 selected as analog input + 2 + + + AnalogInput3 + AIN3 selected as analog input + 3 + + + AnalogInput4 + AIN4 selected as analog input + 4 + + + AnalogInput5 + AIN5 selected as analog input + 5 + + + AnalogInput6 + AIN6 selected as analog input + 6 + + + AnalogInput7 + AIN7 selected as analog input + 7 + + + + + + + REFSEL + Reference source select for single-ended mode + 0x508 + read-write + 0x00000004 + + + REFSEL + Reference select + 0 + 2 + + + Int1V2 + VREF = internal 1.2 V reference (VDD &gt;= 1.7 V) + 0 + + + Int1V8 + VREF = internal 1.8 V reference (VDD &gt;= VREF + 0.2 V) + 1 + + + Int2V4 + VREF = internal 2.4 V reference (VDD &gt;= VREF + 0.2 V) + 2 + + + VDD + VREF = VDD + 4 + + + ARef + VREF = AREF + 5 + + + + + + + EXTREFSEL + External reference select + 0x50C + read-write + + + EXTREFSEL + External analog reference select + 0 + 2 + + + AnalogReference0 + Use AIN0 as external analog reference + 0 + + + AnalogReference1 + Use AIN1 as external analog reference + 1 + + + AnalogReference2 + Use AIN2 as external analog reference + 2 + + + AnalogReference3 + Use AIN3 as external analog reference + 3 + + + AnalogReference4 + Use AIN4 as external analog reference + 4 + + + AnalogReference5 + Use AIN5 as external analog reference + 5 + + + AnalogReference6 + Use AIN6 as external analog reference + 6 + + + AnalogReference7 + Use AIN7 as external analog reference + 7 + + + + + + + TH + Threshold configuration for hysteresis unit + 0x530 + read-write + 0x00000000 + + + THDOWN + VDOWN = (THDOWN+1)/64*VREF + 0 + 5 + + + THUP + VUP = (THUP+1)/64*VREF + 8 + 13 + + + + + MODE + Mode configuration + 0x534 + read-write + + + SP + Speed and power modes + 0 + 1 + + + Low + Low-power mode + 0 + + + Normal + Normal mode + 1 + + + High + High-speed mode + 2 + + + + + MAIN + Main operation modes + 8 + 8 + + + SE + Single-ended mode + 0 + + + Diff + Differential mode + 1 + + + + + + + HYST + Comparator hysteresis enable + 0x538 + read-write + + + HYST + Comparator hysteresis + 0 + 0 + + + NoHyst + Comparator hysteresis disabled + 0 + + + Hyst50mV + Comparator hysteresis enabled + 1 + + + + + + + ISOURCE + Current source select on analog input + 0x53C + read-write + + + ISOURCE + Comparator hysteresis + 0 + 1 + + + Off + Current source disabled + 0 + + + Ien2mA5 + Current source enabled (+/- 2.5 uA) + 1 + + + Ien5mA + Current source enabled (+/- 5 uA) + 2 + + + Ien10mA + Current source enabled (+/- 10 uA) + 3 + + + + + + + + + LPCOMP_NS + Low-power comparator 0 + 0x4001A000 + COMP_NS + LPCOMP + + + + 0 + 0x1000 + registers + + + COMP_LPCOMP + 26 + + LPCOMP + 0x20 + + + TASKS_START + Start comparator + 0x000 + write-only + + + TASKS_START + Start comparator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop comparator + 0x004 + write-only + + + TASKS_STOP + Stop comparator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SAMPLE + Sample comparator value + 0x008 + write-only + + + TASKS_SAMPLE + Sample comparator value + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_SAMPLE + Subscribe configuration for task SAMPLE + 0x088 + read-write + + + CHIDX + DPPI channel that task SAMPLE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_READY + LPCOMP is ready and output is valid + 0x100 + read-write + + + EVENTS_READY + LPCOMP is ready and output is valid + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DOWN + Downward crossing + 0x104 + read-write + + + EVENTS_DOWN + Downward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_UP + Upward crossing + 0x108 + read-write + + + EVENTS_UP + Upward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CROSS + Downward or upward crossing + 0x10C + read-write + + + EVENTS_CROSS + Downward or upward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_READY + Publish configuration for event READY + 0x180 + read-write + + + CHIDX + DPPI channel that event READY will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_DOWN + Publish configuration for event DOWN + 0x184 + read-write + + + CHIDX + DPPI channel that event DOWN will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_UP + Publish configuration for event UP + 0x188 + read-write + + + CHIDX + DPPI channel that event UP will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_CROSS + Publish configuration for event CROSS + 0x18C + read-write + + + CHIDX + DPPI channel that event CROSS will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + READY_SAMPLE + Shortcut between event READY and task SAMPLE + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + READY_STOP + Shortcut between event READY and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DOWN_STOP + Shortcut between event DOWN and task STOP + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + UP_STOP + Shortcut between event UP and task STOP + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + CROSS_STOP + Shortcut between event CROSS and task STOP + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + READY + Write '1' to enable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DOWN + Write '1' to enable interrupt for event DOWN + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + UP + Write '1' to enable interrupt for event UP + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CROSS + Write '1' to enable interrupt for event CROSS + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + READY + Write '1' to disable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DOWN + Write '1' to disable interrupt for event DOWN + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + UP + Write '1' to disable interrupt for event UP + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CROSS + Write '1' to disable interrupt for event CROSS + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + RESULT + Compare result + 0x400 + read-only + + + RESULT + Result of last compare. Decision point SAMPLE task. + 0 + 0 + + + Below + Input voltage is below the reference threshold (VIN+ &lt; VIN-) + 0 + + + Above + Input voltage is above the reference threshold (VIN+ &gt; VIN-) + 1 + + + + + + + ENABLE + Enable LPCOMP + 0x500 + read-write + + + ENABLE + Enable or disable LPCOMP + 0 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + PSEL + Input pin select + 0x504 + read-write + + + PSEL + Analog pin select + 0 + 2 + + + AnalogInput0 + AIN0 selected as analog input + 0 + + + AnalogInput1 + AIN1 selected as analog input + 1 + + + AnalogInput2 + AIN2 selected as analog input + 2 + + + AnalogInput3 + AIN3 selected as analog input + 3 + + + AnalogInput4 + AIN4 selected as analog input + 4 + + + AnalogInput5 + AIN5 selected as analog input + 5 + + + AnalogInput6 + AIN6 selected as analog input + 6 + + + AnalogInput7 + AIN7 selected as analog input + 7 + + + + + + + REFSEL + Reference select + 0x508 + read-write + 0x00000004 + + + REFSEL + Reference select + 0 + 3 + + + Ref1_8Vdd + VDD * 1/8 selected as reference + 0 + + + Ref2_8Vdd + VDD * 2/8 selected as reference + 1 + + + Ref3_8Vdd + VDD * 3/8 selected as reference + 2 + + + Ref4_8Vdd + VDD * 4/8 selected as reference + 3 + + + Ref5_8Vdd + VDD * 5/8 selected as reference + 4 + + + Ref6_8Vdd + VDD * 6/8 selected as reference + 5 + + + Ref7_8Vdd + VDD * 7/8 selected as reference + 6 + + + ARef + External analog reference selected + 7 + + + Ref1_16Vdd + VDD * 1/16 selected as reference + 8 + + + Ref3_16Vdd + VDD * 3/16 selected as reference + 9 + + + Ref5_16Vdd + VDD * 5/16 selected as reference + 10 + + + Ref7_16Vdd + VDD * 7/16 selected as reference + 11 + + + Ref9_16Vdd + VDD * 9/16 selected as reference + 12 + + + Ref11_16Vdd + VDD * 11/16 selected as reference + 13 + + + Ref13_16Vdd + VDD * 13/16 selected as reference + 14 + + + Ref15_16Vdd + VDD * 15/16 selected as reference + 15 + + + + + + + EXTREFSEL + External reference select + 0x50C + read-write + + + EXTREFSEL + External analog reference select + 0 + 0 + + + AnalogReference0 + Use AIN0 as external analog reference + 0 + + + AnalogReference1 + Use AIN1 as external analog reference + 1 + + + + + + + ANADETECT + Analog detect configuration + 0x520 + read-write + + + ANADETECT + Analog detect configuration + 0 + 1 + + + Cross + Generate ANADETECT on crossing, both upward crossing and downward crossing + 0 + + + Up + Generate ANADETECT on upward crossing only + 1 + + + Down + Generate ANADETECT on downward crossing only + 2 + + + + + + + HYST + Comparator hysteresis enable + 0x538 + read-write + + + HYST + Comparator hysteresis enable + 0 + 0 + + + Disabled + Comparator hysteresis disabled + 0 + + + Enabled + Comparator hysteresis enabled + 1 + + + + + + + + + COMP_S + Comparator 1 + 0x5001A000 + + + + COMP_LPCOMP + 26 + + + + LPCOMP_S + Low-power comparator 1 + 0x5001A000 + COMP_S + + + + COMP_LPCOMP + 26 + + + + EGU0_NS + Event generator unit 0 + 0x4001B000 + EGU + + + + 0 + 0x1000 + registers + + + EGU0 + 27 + + EGU + 0x20 + + + 0x10 + 0x4 + TASKS_TRIGGER[%s] + Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event + 0x000 + write-only + + + TASKS_TRIGGER + Trigger n for triggering the corresponding TRIGGERED[n] event + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x10 + 0x4 + SUBSCRIBE_TRIGGER[%s] + Description collection: Subscribe configuration for task TRIGGER[n] + 0x080 + read-write + + + CHIDX + DPPI channel that task TRIGGER[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + 0x10 + 0x4 + EVENTS_TRIGGERED[%s] + Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task + 0x100 + read-write + + + EVENTS_TRIGGERED + Event number n generated by triggering the corresponding TRIGGER[n] task + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x10 + 0x4 + PUBLISH_TRIGGERED[%s] + Description collection: Publish configuration for event TRIGGERED[n] + 0x180 + read-write + + + CHIDX + DPPI channel that event TRIGGERED[n] will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + TRIGGERED0 + Enable or disable interrupt for event TRIGGERED[0] + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED1 + Enable or disable interrupt for event TRIGGERED[1] + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED2 + Enable or disable interrupt for event TRIGGERED[2] + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED3 + Enable or disable interrupt for event TRIGGERED[3] + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED4 + Enable or disable interrupt for event TRIGGERED[4] + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED5 + Enable or disable interrupt for event TRIGGERED[5] + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED6 + Enable or disable interrupt for event TRIGGERED[6] + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED7 + Enable or disable interrupt for event TRIGGERED[7] + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED8 + Enable or disable interrupt for event TRIGGERED[8] + 8 + 8 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED9 + Enable or disable interrupt for event TRIGGERED[9] + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED10 + Enable or disable interrupt for event TRIGGERED[10] + 10 + 10 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED11 + Enable or disable interrupt for event TRIGGERED[11] + 11 + 11 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED12 + Enable or disable interrupt for event TRIGGERED[12] + 12 + 12 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED13 + Enable or disable interrupt for event TRIGGERED[13] + 13 + 13 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED14 + Enable or disable interrupt for event TRIGGERED[14] + 14 + 14 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED15 + Enable or disable interrupt for event TRIGGERED[15] + 15 + 15 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + TRIGGERED0 + Write '1' to enable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED1 + Write '1' to enable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED2 + Write '1' to enable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED3 + Write '1' to enable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED4 + Write '1' to enable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED5 + Write '1' to enable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED6 + Write '1' to enable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED7 + Write '1' to enable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED8 + Write '1' to enable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED9 + Write '1' to enable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED10 + Write '1' to enable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED11 + Write '1' to enable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED12 + Write '1' to enable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED13 + Write '1' to enable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED14 + Write '1' to enable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED15 + Write '1' to enable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + TRIGGERED0 + Write '1' to disable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED1 + Write '1' to disable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED2 + Write '1' to disable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED3 + Write '1' to disable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED4 + Write '1' to disable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED5 + Write '1' to disable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED6 + Write '1' to disable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED7 + Write '1' to disable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED8 + Write '1' to disable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED9 + Write '1' to disable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED10 + Write '1' to disable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED11 + Write '1' to disable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED12 + Write '1' to disable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED13 + Write '1' to disable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED14 + Write '1' to disable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED15 + Write '1' to disable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + + + EGU0_S + Event generator unit 1 + 0x5001B000 + + + + EGU0 + 27 + + + + EGU1_NS + Event generator unit 2 + 0x4001C000 + + + + EGU1 + 28 + + + + EGU1_S + Event generator unit 3 + 0x5001C000 + + + + EGU1 + 28 + + + + EGU2_NS + Event generator unit 4 + 0x4001D000 + + + + EGU2 + 29 + + + + EGU2_S + Event generator unit 5 + 0x5001D000 + + + + EGU2 + 29 + + + + EGU3_NS + Event generator unit 6 + 0x4001E000 + + + + EGU3 + 30 + + + + EGU3_S + Event generator unit 7 + 0x5001E000 + + + + EGU3 + 30 + + + + EGU4_NS + Event generator unit 8 + 0x4001F000 + + + + EGU4 + 31 + + + + EGU4_S + Event generator unit 9 + 0x5001F000 + + + + EGU4 + 31 + + + + EGU5_NS + Event generator unit 10 + 0x40020000 + + + + EGU5 + 32 + + + + EGU5_S + Event generator unit 11 + 0x50020000 + + + + EGU5 + 32 + + + + PWM0_NS + Pulse width modulation unit 0 + 0x40021000 + PWM + + + + 0 + 0x1000 + registers + + + PWM0 + 33 + + PWM + 0x20 + + + TASKS_STOP + Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback + 0x004 + write-only + + + TASKS_STOP + Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x2 + 0x4 + TASKS_SEQSTART[%s] + Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. + 0x008 + write-only + + + TASKS_SEQSTART + Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_NEXTSTEP + Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. + 0x010 + write-only + + + TASKS_NEXTSTEP + Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + 0x2 + 0x4 + SUBSCRIBE_SEQSTART[%s] + Description collection: Subscribe configuration for task SEQSTART[n] + 0x088 + read-write + + + CHIDX + DPPI channel that task SEQSTART[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_NEXTSTEP + Subscribe configuration for task NEXTSTEP + 0x090 + read-write + + + CHIDX + DPPI channel that task NEXTSTEP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_STOPPED + Response to STOP task, emitted when PWM pulses are no longer generated + 0x104 + read-write + + + EVENTS_STOPPED + Response to STOP task, emitted when PWM pulses are no longer generated + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x2 + 0x4 + EVENTS_SEQSTARTED[%s] + Description collection: First PWM period started on sequence n + 0x108 + read-write + + + EVENTS_SEQSTARTED + First PWM period started on sequence n + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x2 + 0x4 + EVENTS_SEQEND[%s] + Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter + 0x110 + read-write + + + EVENTS_SEQEND + Emitted at end of every sequence n, when last value from RAM has been applied to wave counter + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_PWMPERIODEND + Emitted at the end of each PWM period + 0x118 + read-write + + + EVENTS_PWMPERIODEND + Emitted at the end of each PWM period + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_LOOPSDONE + Concatenated sequences have been played the amount of times defined in LOOP.CNT + 0x11C + read-write + + + EVENTS_LOOPSDONE + Concatenated sequences have been played the amount of times defined in LOOP.CNT + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + + + CHIDX + DPPI channel that event STOPPED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + 0x2 + 0x4 + PUBLISH_SEQSTARTED[%s] + Description collection: Publish configuration for event SEQSTARTED[n] + 0x188 + read-write + + + CHIDX + DPPI channel that event SEQSTARTED[n] will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + 0x2 + 0x4 + PUBLISH_SEQEND[%s] + Description collection: Publish configuration for event SEQEND[n] + 0x190 + read-write + + + CHIDX + DPPI channel that event SEQEND[n] will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_PWMPERIODEND + Publish configuration for event PWMPERIODEND + 0x198 + read-write + + + CHIDX + DPPI channel that event PWMPERIODEND will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_LOOPSDONE + Publish configuration for event LOOPSDONE + 0x19C + read-write + + + CHIDX + DPPI channel that event LOOPSDONE will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + SEQEND0_STOP + Shortcut between event SEQEND[0] and task STOP + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + SEQEND1_STOP + Shortcut between event SEQEND[1] and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LOOPSDONE_SEQSTART0 + Shortcut between event LOOPSDONE and task SEQSTART[0] + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LOOPSDONE_SEQSTART1 + Shortcut between event LOOPSDONE and task SEQSTART[1] + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LOOPSDONE_STOP + Shortcut between event LOOPSDONE and task STOP + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SEQSTARTED0 + Enable or disable interrupt for event SEQSTARTED[0] + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SEQSTARTED1 + Enable or disable interrupt for event SEQSTARTED[1] + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SEQEND0 + Enable or disable interrupt for event SEQEND[0] + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SEQEND1 + Enable or disable interrupt for event SEQEND[1] + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + LOOPSDONE + Enable or disable interrupt for event LOOPSDONE + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SEQSTARTED0 + Write '1' to enable interrupt for event SEQSTARTED[0] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SEQSTARTED1 + Write '1' to enable interrupt for event SEQSTARTED[1] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SEQEND0 + Write '1' to enable interrupt for event SEQEND[0] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SEQEND1 + Write '1' to enable interrupt for event SEQEND[1] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + LOOPSDONE + Write '1' to enable interrupt for event LOOPSDONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SEQSTARTED0 + Write '1' to disable interrupt for event SEQSTARTED[0] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SEQSTARTED1 + Write '1' to disable interrupt for event SEQSTARTED[1] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SEQEND0 + Write '1' to disable interrupt for event SEQEND[0] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SEQEND1 + Write '1' to disable interrupt for event SEQEND[1] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + LOOPSDONE + Write '1' to disable interrupt for event LOOPSDONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + PWM module enable register + 0x500 + read-write + 0x00000000 + + + ENABLE + Enable or disable PWM module + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enable + 1 + + + + + + + MODE + Selects operating mode of the wave counter + 0x504 + read-write + 0x00000000 + + + UPDOWN + Selects up mode or up-and-down mode for the counter + 0 + 0 + + + Up + Up counter, edge-aligned PWM duty cycle + 0 + + + UpAndDown + Up and down counter, center-aligned PWM duty cycle + 1 + + + + + + + COUNTERTOP + Value up to which the pulse generator counter counts + 0x508 + read-write + 0x000003FF + + + COUNTERTOP + Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. + 0 + 14 + + + + + PRESCALER + Configuration for PWM_CLK + 0x50C + read-write + 0x00000000 + + + PRESCALER + Prescaler of PWM_CLK + 0 + 2 + + + DIV_1 + Divide by 1 (16 MHz) + 0 + + + DIV_2 + Divide by 2 (8 MHz) + 1 + + + DIV_4 + Divide by 4 (4 MHz) + 2 + + + DIV_8 + Divide by 8 (2 MHz) + 3 + + + DIV_16 + Divide by 16 (1 MHz) + 4 + + + DIV_32 + Divide by 32 (500 kHz) + 5 + + + DIV_64 + Divide by 64 (250 kHz) + 6 + + + DIV_128 + Divide by 128 (125 kHz) + 7 + + + + + + + DECODER + Configuration of the decoder + 0x510 + read-write + 0x00000000 + + + LOAD + How a sequence is read from RAM and spread to the compare register + 0 + 1 + + + Common + 1st half word (16-bit) used in all PWM channels 0..3 + 0 + + + Grouped + 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 + 1 + + + Individual + 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 + 2 + + + WaveForm + 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP + 3 + + + + + MODE + Selects source for advancing the active sequence + 8 + 8 + + + RefreshCount + SEQ[n].REFRESH is used to determine loading internal compare registers + 0 + + + NextStep + NEXTSTEP task causes a new value to be loaded to internal compare registers + 1 + + + + + + + LOOP + Number of playbacks of a loop + 0x514 + read-write + 0x00000000 + + + CNT + Number of playbacks of pattern cycles + 0 + 15 + + + Disabled + Looping disabled (stop at the end of the sequence) + 0 + + + + + + + 2 + 0x020 + SEQ[%s] + Unspecified + PWM_SEQ + read-write + 0x520 + + PTR + Description cluster: Beginning address in RAM of this sequence + 0x000 + read-write + 0x00000000 + + + PTR + Beginning address in RAM of this sequence + 0 + 31 + + + + + CNT + Description cluster: Number of values (duty cycles) in this sequence + 0x004 + read-write + 0x00000000 + + + CNT + Number of values (duty cycles) in this sequence + 0 + 14 + + + Disabled + Sequence is disabled, and shall not be started as it is empty + 0 + + + + + + + REFRESH + Description cluster: Number of additional PWM periods between samples loaded into compare register + 0x008 + read-write + 0x00000001 + + + CNT + Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) + 0 + 23 + + + Continuous + Update every PWM period + 0 + + + + + + + ENDDELAY + Description cluster: Time added after the sequence + 0x00C + read-write + 0x00000000 + + + CNT + Time added after the sequence in PWM periods + 0 + 23 + + + + + + PSEL + Unspecified + PWM_PSEL + read-write + 0x560 + + 0x4 + 0x4 + OUT[%s] + Description collection: Output pin select for PWM channel n + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + + + PWM0_S + Pulse width modulation unit 1 + 0x50021000 + + + + PWM0 + 33 + + + + PWM1_NS + Pulse width modulation unit 2 + 0x40022000 + + + + PWM1 + 34 + + + + PWM1_S + Pulse width modulation unit 3 + 0x50022000 + + + + PWM1 + 34 + + + + PWM2_NS + Pulse width modulation unit 4 + 0x40023000 + + + + PWM2 + 35 + + + + PWM2_S + Pulse width modulation unit 5 + 0x50023000 + + + + PWM2 + 35 + + + + PWM3_NS + Pulse width modulation unit 6 + 0x40024000 + + + + PWM3 + 36 + + + + PWM3_S + Pulse width modulation unit 7 + 0x50024000 + + + + PWM3 + 36 + + + + PDM0_NS + Pulse Density Modulation (Digital Microphone) Interface 0 + 0x40026000 + PDM + + + + 0 + 0x1000 + registers + + + PDM0 + 38 + + PDM + 0x20 + + + TASKS_START + Starts continuous PDM transfer + 0x000 + write-only + + + TASKS_START + Starts continuous PDM transfer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stops PDM transfer + 0x004 + write-only + + + TASKS_STOP + Stops PDM transfer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_STARTED + PDM transfer has started + 0x100 + read-write + + + EVENTS_STARTED + PDM transfer has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STOPPED + PDM transfer has finished + 0x104 + read-write + + + EVENTS_STOPPED + PDM transfer has finished + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_END + The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM + 0x108 + read-write + + + EVENTS_END + The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_STARTED + Publish configuration for event STARTED + 0x180 + read-write + + + CHIDX + DPPI channel that event STARTED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + + + CHIDX + DPPI channel that event STOPPED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x188 + read-write + + + CHIDX + DPPI channel that event END will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STARTED + Enable or disable interrupt for event STARTED + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + END + Enable or disable interrupt for event END + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STARTED + Write '1' to enable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + END + Write '1' to enable interrupt for event END + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STARTED + Write '1' to disable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + END + Write '1' to disable interrupt for event END + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + PDM module enable register + 0x500 + read-write + 0x00000000 + + + ENABLE + Enable or disable PDM module + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + PDMCLKCTRL + PDM clock generator control + 0x504 + read-write + 0x08400000 + + + FREQ + PDM_CLK frequency configuration. Enumerations are deprecated, use + PDMCLKCTRL equation to find the register value. The 12 least significant bits of the + register are ignored and shall be set to zero. + 0 + 31 + + + 1000K + PDM_CLK = 32 MHz / 32 = 1.000 MHz + 0x08000000 + + + Default + PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64. + 0x08400000 + + + 1067K + PDM_CLK = 32 MHz / 30 = 1.067 MHz + 0x08800000 + + + 1231K + PDM_CLK = 32 MHz / 26 = 1.231 MHz + 0x09800000 + + + 1280K + PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80. + 0x0A000000 + + + 1333K + PDM_CLK = 32 MHz / 24 = 1.333 MHz + 0x0A800000 + + + + + + + MODE + Defines the routing of the connected PDM microphones' signals + 0x508 + read-write + 0x00000000 + + + OPERATION + Mono or stereo operation + 0 + 0 + + + Stereo + Sample and store one pair (left + right) of 16-bit samples per RAM word R=[31:16]; L=[15:0] + 0 + + + Mono + Sample and store two successive left samples (16 bits each) per RAM word L1=[31:16]; L0=[15:0] + 1 + + + + + EDGE + Defines on which PDM_CLK edge left (or mono) is sampled + 1 + 1 + + + LeftFalling + Left (or mono) is sampled on falling edge of PDM_CLK + 0 + + + LeftRising + Left (or mono) is sampled on rising edge of PDM_CLK + 1 + + + + + + + GAINL + Left output gain adjustment + 0x518 + read-write + 0x00000028 + + + GAINL + Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust + 0 + 6 + + + MinGain + -20 dB gain adjustment (minimum) + 0x00 + + + DefaultGain + 0 dB gain adjustment + 0x28 + + + MaxGain + +20 dB gain adjustment (maximum) + 0x50 + + + + + + + GAINR + Right output gain adjustment + 0x51C + read-write + 0x00000028 + + + GAINR + Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) + 0 + 6 + + + MinGain + -20 dB gain adjustment (minimum) + 0x00 + + + DefaultGain + 0 dB gain adjustment + 0x28 + + + MaxGain + +20 dB gain adjustment (maximum) + 0x50 + + + + + + + RATIO + Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. + 0x520 + read-write + 0x00000000 + + + RATIO + Selects the ratio between PDM_CLK and output sample rate + 0 + 0 + + + Ratio64 + Ratio of 64 + 0 + + + Ratio80 + Ratio of 80 + 1 + + + + + + + PSEL + Unspecified + PDM_PSEL + read-write + 0x540 + + CLK + Pin number configuration for PDM CLK signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + DIN + Pin number configuration for PDM DIN signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + MCLKCONFIG + Master clock generator configuration + 0x54C + read-write + 0x00000000 + + + SRC + Master clock source selection + 0 + 0 + + + PCLK32M + 32 MHz peripheral clock + 0 + + + ACLK + Audio PLL clock + 1 + + + + + + + SAMPLE + Unspecified + PDM_SAMPLE + read-write + 0x560 + + PTR + RAM address pointer to write samples to with EasyDMA + 0x000 + read-write + + + SAMPLEPTR + Address to write PDM samples to over DMA + 0 + 31 + + + + + MAXCNT + Number of samples to allocate memory for in EasyDMA mode + 0x004 + read-write + + + BUFFSIZE + Length of DMA RAM allocation in number of samples + 0 + 14 + + + + + + + + PDM0_S + Pulse Density Modulation (Digital Microphone) Interface 1 + 0x50026000 + + + + PDM0 + 38 + + + + I2S0_NS + Inter-IC Sound 0 + 0x40028000 + I2S + + + + 0 + 0x1000 + registers + + + I2S0 + 40 + + I2S + 0x20 + + + TASKS_START + Starts continuous I2S transfer. Also starts MCK generator when this is enabled + 0x000 + write-only + + + TASKS_START + Starts continuous I2S transfer. Also starts MCK generator when this is enabled + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stops I2S transfer and MCK generator. Triggering this task will cause the event STOPPED to be generated. + 0x004 + write-only + + + TASKS_STOP + Stops I2S transfer and MCK generator. Triggering this task will cause the event STOPPED to be generated. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_RXPTRUPD + The RXD.PTR register has been copied to internal double-buffers. + When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words received on the SDIN pin. + 0x104 + read-write + + + EVENTS_RXPTRUPD + The RXD.PTR register has been copied to internal double-buffers. + When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words received on the SDIN pin. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STOPPED + I2S transfer stopped. + 0x108 + read-write + + + EVENTS_STOPPED + I2S transfer stopped. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXPTRUPD + The TDX.PTR register has been copied to internal double-buffers. + When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. + 0x114 + read-write + + + EVENTS_TXPTRUPD + The TDX.PTR register has been copied to internal double-buffers. + When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_FRAMESTART + Frame start event, generated on the active edge of LRCK + 0x11C + read-write + + + EVENTS_FRAMESTART + Frame start event, generated on the active edge of LRCK + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_RXPTRUPD + Publish configuration for event RXPTRUPD + 0x184 + read-write + + + CHIDX + DPPI channel that event RXPTRUPD will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x188 + read-write + + + CHIDX + DPPI channel that event STOPPED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_TXPTRUPD + Publish configuration for event TXPTRUPD + 0x194 + read-write + + + CHIDX + DPPI channel that event TXPTRUPD will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_FRAMESTART + Publish configuration for event FRAMESTART + 0x19C + read-write + + + CHIDX + DPPI channel that event FRAMESTART will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + RXPTRUPD + Enable or disable interrupt for event RXPTRUPD + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + STOPPED + Enable or disable interrupt for event STOPPED + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXPTRUPD + Enable or disable interrupt for event TXPTRUPD + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + FRAMESTART + Enable or disable interrupt for event FRAMESTART + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + RXPTRUPD + Write '1' to enable interrupt for event RXPTRUPD + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXPTRUPD + Write '1' to enable interrupt for event TXPTRUPD + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + FRAMESTART + Write '1' to enable interrupt for event FRAMESTART + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + RXPTRUPD + Write '1' to disable interrupt for event RXPTRUPD + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXPTRUPD + Write '1' to disable interrupt for event TXPTRUPD + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + FRAMESTART + Write '1' to disable interrupt for event FRAMESTART + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + Enable I2S module + 0x500 + read-write + 0x00000000 + + + ENABLE + Enable I2S module + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + CONFIG + Unspecified + I2S_CONFIG + read-write + 0x504 + + MODE + I2S mode + 0x000 + read-write + 0x00000000 + + + MODE + I2S mode + 0 + 0 + + + Master + Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. + 0 + + + Slave + Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx + 1 + + + + + + + RXEN + Reception (RX) enable + 0x004 + read-write + 0x00000000 + + + RXEN + Reception (RX) enable + 0 + 0 + + + Disabled + Reception disabled and now data will be written to the RXD.PTR address. + 0 + + + Enabled + Reception enabled. + 1 + + + + + + + TXEN + Transmission (TX) enable + 0x008 + read-write + 0x00000001 + + + TXEN + Transmission (TX) enable + 0 + 0 + + + Disabled + Transmission disabled and now data will be read from the RXD.TXD address. + 0 + + + Enabled + Transmission enabled. + 1 + + + + + + + MCKEN + Master clock generator enable + 0x00C + read-write + 0x00000001 + + + MCKEN + Master clock generator enable + 0 + 0 + + + Disabled + Master clock generator disabled and PSEL.MCK not connected(available as GPIO). + 0 + + + Enabled + Master clock generator running and MCK output on PSEL.MCK. + 1 + + + + + + + MCKFREQ + I2S clock generator control + 0x010 + read-write + 0x20000000 + + + MCKFREQ + I2S MCK frequency configuration NOTE: Enumerations are deprecated, use MCKFREQ equation. NOTE: The 12 least significant bits of the register are ignored and shall be set to zero. + 0 + 31 + + + 32MDIV2 + 32 MHz / 2 = 16.0 MHz Deprecated, use MCKFREQ equation. + 0x80000000 + + + 32MDIV3 + 32 MHz / 3 = 10.6666667 MHz Deprecated, use MCKFREQ equation. + 0x50000000 + + + 32MDIV4 + 32 MHz / 4 = 8.0 MHz Deprecated, use MCKFREQ equation. + 0x40000000 + + + 32MDIV5 + 32 MHz / 5 = 6.4 MHz Deprecated, use MCKFREQ equation. + 0x30000000 + + + 32MDIV6 + 32 MHz / 6 = 5.3333333 MHz Deprecated, use MCKFREQ equation. + 0x28000000 + + + 32MDIV8 + 32 MHz / 8 = 4.0 MHz Deprecated, use MCKFREQ equation. + 0x20000000 + + + 32MDIV10 + 32 MHz / 10 = 3.2 MHz Deprecated, use MCKFREQ equation. + 0x18000000 + + + 32MDIV11 + 32 MHz / 11 = 2.9090909 MHz Deprecated, use MCKFREQ equation. + 0x16000000 + + + 32MDIV15 + 32 MHz / 15 = 2.1333333 MHz Deprecated, use MCKFREQ equation. + 0x11000000 + + + 32MDIV16 + 32 MHz / 16 = 2.0 MHz Deprecated, use MCKFREQ equation. + 0x10000000 + + + 32MDIV21 + 32 MHz / 21 = 1.5238095 MHz Deprecated, use MCKFREQ equation. + 0x0C000000 + + + 32MDIV23 + 32 MHz / 23 = 1.3913043 MHz Deprecated, use MCKFREQ equation. + 0x0B000000 + + + 32MDIV30 + 32 MHz / 30 = 1.0666667 MHz Deprecated, use MCKFREQ equation. + 0x08800000 + + + 32MDIV31 + 32 MHz / 31 = 1.0322581 MHz Deprecated, use MCKFREQ equation. + 0x08400000 + + + 32MDIV32 + 32 MHz / 32 = 1.0 MHz Deprecated, use MCKFREQ equation. + 0x08000000 + + + 32MDIV42 + 32 MHz / 42 = 0.7619048 MHz Deprecated, use MCKFREQ equation. + 0x06000000 + + + 32MDIV63 + 32 MHz / 63 = 0.5079365 MHz Deprecated, use MCKFREQ equation. + 0x04100000 + + + 32MDIV125 + 32 MHz / 125 = 0.256 MHz Deprecated, use MCKFREQ equation. + 0x020C0000 + + + + + + + RATIO + MCK / LRCK ratio + 0x014 + read-write + 0x00000006 + + + RATIO + MCK / LRCK ratio + 0 + 3 + + + 32X + LRCK = MCK / 32 + 0 + + + 48X + LRCK = MCK / 48 + 1 + + + 64X + LRCK = MCK / 64 + 2 + + + 96X + LRCK = MCK / 96 + 3 + + + 128X + LRCK = MCK / 128 + 4 + + + 192X + LRCK = MCK / 192 + 5 + + + 256X + LRCK = MCK / 256 + 6 + + + 384X + LRCK = MCK / 384 + 7 + + + 512X + LRCK = MCK / 512 + 8 + + + + + + + SWIDTH + Sample width + 0x018 + read-write + 0x00000001 + + + SWIDTH + Sample and half-frame width + 0 + 2 + + + 8Bit + 8 bit sample. + 0 + + + 16Bit + 16 bit sample. + 1 + + + 24Bit + 24 bit sample. + 2 + + + 32Bit + 32 bit sample. + 3 + + + 8BitIn16 + 8 bit sample in a 16-bit half-frame. + 4 + + + 8BitIn32 + 8 bit sample in a 32-bit half-frame. + 5 + + + 16BitIn32 + 16 bit sample in a 32-bit half-frame. + 6 + + + 24BitIn32 + 24 bit sample in a 32-bit half-frame. + 7 + + + + + + + ALIGN + Alignment of sample within a frame + 0x01C + read-write + 0x00000000 + + + ALIGN + Alignment of sample within a frame + 0 + 0 + + + Left + Left-aligned. + 0 + + + Right + Right-aligned. + 1 + + + + + + + FORMAT + Frame format + 0x020 + read-write + 0x00000000 + + + FORMAT + Frame format + 0 + 0 + + + I2S + Original I2S format. + 0 + + + Aligned + Alternate (left- or right-aligned) format. + 1 + + + + + + + CHANNELS + Enable channels + 0x024 + read-write + 0x00000000 + + + CHANNELS + Enable channels + 0 + 1 + + + Stereo + Stereo. + 0 + + + Left + Left only. + 1 + + + Right + Right only. + 2 + + + + + + + CLKCONFIG + Clock source selection for the I2S module + 0x028 + read-write + 0x00000000 + + + CLKSRC + Clock source selection + 0 + 0 + + + PCLK32M + 32MHz peripheral clock + 0 + + + ACLK + Audio PLL clock + 1 + + + + + BYPASS + Bypass clock generator. MCK will be equal to source input. If bypass is enabled the MCKFREQ setting has no effect. + 8 + 8 + + + Disable + Disable bypass + 0 + + + Enable + Enable bypass + 1 + + + + + + + + RXD + Unspecified + I2S_RXD + read-write + 0x538 + + PTR + Receive buffer RAM start address. + 0x000 + read-write + 0x00000000 + + + PTR + Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. + 0 + 31 + + + + + + TXD + Unspecified + I2S_TXD + read-write + 0x540 + + PTR + Transmit buffer RAM start address + 0x000 + read-write + 0x00000000 + + + PTR + Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. + 0 + 31 + + + + + + RXTXD + Unspecified + I2S_RXTXD + read-write + 0x550 + + MAXCNT + Size of RXD and TXD buffers + 0x000 + read-write + 0x00000000 + + + MAXCNT + Size of RXD and TXD buffers in number of 32 bit words + 0 + 13 + + + + + + PSEL + Unspecified + I2S_PSEL + read-write + 0x560 + + MCK + Pin select for MCK signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SCK + Pin select for SCK signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + LRCK + Pin select for LRCK signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDIN + Pin select for SDIN signal + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDOUT + Pin select for SDOUT signal + 0x010 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + + + I2S0_S + Inter-IC Sound 1 + 0x50028000 + + + + I2S0 + 40 + + + + IPC_NS + Interprocessor communication 0 + 0x4002A000 + IPC + + + + 0 + 0x1000 + registers + + + IPC + 42 + + IPC + 0x20 + + + 0x10 + 0x4 + TASKS_SEND[%s] + Description collection: Trigger events on IPC channel enabled in SEND_CNF[n] + 0x000 + write-only + + + TASKS_SEND + Trigger events on IPC channel enabled in SEND_CNF[n] + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x10 + 0x4 + SUBSCRIBE_SEND[%s] + Description collection: Subscribe configuration for task SEND[n] + 0x080 + read-write + + + CHIDX + DPPI channel that task SEND[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + 0x10 + 0x4 + EVENTS_RECEIVE[%s] + Description collection: Event received on one or more of the enabled IPC channels in RECEIVE_CNF[n] + 0x100 + read-write + + + EVENTS_RECEIVE + Event received on one or more of the enabled IPC channels in RECEIVE_CNF[n] + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x10 + 0x4 + PUBLISH_RECEIVE[%s] + Description collection: Publish configuration for event RECEIVE[n] + 0x180 + read-write + + + CHIDX + DPPI channel that event RECEIVE[n] will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + RECEIVE0 + Enable or disable interrupt for event RECEIVE[0] + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE1 + Enable or disable interrupt for event RECEIVE[1] + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE2 + Enable or disable interrupt for event RECEIVE[2] + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE3 + Enable or disable interrupt for event RECEIVE[3] + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE4 + Enable or disable interrupt for event RECEIVE[4] + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE5 + Enable or disable interrupt for event RECEIVE[5] + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE6 + Enable or disable interrupt for event RECEIVE[6] + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE7 + Enable or disable interrupt for event RECEIVE[7] + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE8 + Enable or disable interrupt for event RECEIVE[8] + 8 + 8 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE9 + Enable or disable interrupt for event RECEIVE[9] + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE10 + Enable or disable interrupt for event RECEIVE[10] + 10 + 10 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE11 + Enable or disable interrupt for event RECEIVE[11] + 11 + 11 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE12 + Enable or disable interrupt for event RECEIVE[12] + 12 + 12 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE13 + Enable or disable interrupt for event RECEIVE[13] + 13 + 13 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE14 + Enable or disable interrupt for event RECEIVE[14] + 14 + 14 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE15 + Enable or disable interrupt for event RECEIVE[15] + 15 + 15 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + RECEIVE0 + Write '1' to enable interrupt for event RECEIVE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE1 + Write '1' to enable interrupt for event RECEIVE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE2 + Write '1' to enable interrupt for event RECEIVE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE3 + Write '1' to enable interrupt for event RECEIVE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE4 + Write '1' to enable interrupt for event RECEIVE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE5 + Write '1' to enable interrupt for event RECEIVE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE6 + Write '1' to enable interrupt for event RECEIVE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE7 + Write '1' to enable interrupt for event RECEIVE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE8 + Write '1' to enable interrupt for event RECEIVE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE9 + Write '1' to enable interrupt for event RECEIVE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE10 + Write '1' to enable interrupt for event RECEIVE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE11 + Write '1' to enable interrupt for event RECEIVE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE12 + Write '1' to enable interrupt for event RECEIVE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE13 + Write '1' to enable interrupt for event RECEIVE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE14 + Write '1' to enable interrupt for event RECEIVE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE15 + Write '1' to enable interrupt for event RECEIVE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + RECEIVE0 + Write '1' to disable interrupt for event RECEIVE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE1 + Write '1' to disable interrupt for event RECEIVE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE2 + Write '1' to disable interrupt for event RECEIVE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE3 + Write '1' to disable interrupt for event RECEIVE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE4 + Write '1' to disable interrupt for event RECEIVE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE5 + Write '1' to disable interrupt for event RECEIVE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE6 + Write '1' to disable interrupt for event RECEIVE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE7 + Write '1' to disable interrupt for event RECEIVE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE8 + Write '1' to disable interrupt for event RECEIVE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE9 + Write '1' to disable interrupt for event RECEIVE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE10 + Write '1' to disable interrupt for event RECEIVE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE11 + Write '1' to disable interrupt for event RECEIVE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE12 + Write '1' to disable interrupt for event RECEIVE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE13 + Write '1' to disable interrupt for event RECEIVE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE14 + Write '1' to disable interrupt for event RECEIVE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE15 + Write '1' to disable interrupt for event RECEIVE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + + + RECEIVE0 + Read pending status of interrupt for event RECEIVE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE1 + Read pending status of interrupt for event RECEIVE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE2 + Read pending status of interrupt for event RECEIVE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE3 + Read pending status of interrupt for event RECEIVE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE4 + Read pending status of interrupt for event RECEIVE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE5 + Read pending status of interrupt for event RECEIVE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE6 + Read pending status of interrupt for event RECEIVE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE7 + Read pending status of interrupt for event RECEIVE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE8 + Read pending status of interrupt for event RECEIVE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE9 + Read pending status of interrupt for event RECEIVE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE10 + Read pending status of interrupt for event RECEIVE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE11 + Read pending status of interrupt for event RECEIVE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE12 + Read pending status of interrupt for event RECEIVE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE13 + Read pending status of interrupt for event RECEIVE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE14 + Read pending status of interrupt for event RECEIVE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE15 + Read pending status of interrupt for event RECEIVE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + + + 0x10 + 0x4 + SEND_CNF[%s] + Description collection: Send event configuration for TASKS_SEND[n] + 0x510 + read-write + 0x00000000 + + + CHEN0 + Enable broadcasting on IPC channel 0 + 0 + 0 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN1 + Enable broadcasting on IPC channel 1 + 1 + 1 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN2 + Enable broadcasting on IPC channel 2 + 2 + 2 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN3 + Enable broadcasting on IPC channel 3 + 3 + 3 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN4 + Enable broadcasting on IPC channel 4 + 4 + 4 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN5 + Enable broadcasting on IPC channel 5 + 5 + 5 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN6 + Enable broadcasting on IPC channel 6 + 6 + 6 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN7 + Enable broadcasting on IPC channel 7 + 7 + 7 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN8 + Enable broadcasting on IPC channel 8 + 8 + 8 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN9 + Enable broadcasting on IPC channel 9 + 9 + 9 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN10 + Enable broadcasting on IPC channel 10 + 10 + 10 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN11 + Enable broadcasting on IPC channel 11 + 11 + 11 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN12 + Enable broadcasting on IPC channel 12 + 12 + 12 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN13 + Enable broadcasting on IPC channel 13 + 13 + 13 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN14 + Enable broadcasting on IPC channel 14 + 14 + 14 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN15 + Enable broadcasting on IPC channel 15 + 15 + 15 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + + + 0x10 + 0x4 + RECEIVE_CNF[%s] + Description collection: Receive event configuration for EVENTS_RECEIVE[n] + 0x590 + read-write + 0x00000000 + + + CHEN0 + Enable subscription to IPC channel 0 + 0 + 0 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN1 + Enable subscription to IPC channel 1 + 1 + 1 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN2 + Enable subscription to IPC channel 2 + 2 + 2 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN3 + Enable subscription to IPC channel 3 + 3 + 3 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN4 + Enable subscription to IPC channel 4 + 4 + 4 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN5 + Enable subscription to IPC channel 5 + 5 + 5 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN6 + Enable subscription to IPC channel 6 + 6 + 6 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN7 + Enable subscription to IPC channel 7 + 7 + 7 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN8 + Enable subscription to IPC channel 8 + 8 + 8 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN9 + Enable subscription to IPC channel 9 + 9 + 9 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN10 + Enable subscription to IPC channel 10 + 10 + 10 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN11 + Enable subscription to IPC channel 11 + 11 + 11 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN12 + Enable subscription to IPC channel 12 + 12 + 12 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN13 + Enable subscription to IPC channel 13 + 13 + 13 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN14 + Enable subscription to IPC channel 14 + 14 + 14 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN15 + Enable subscription to IPC channel 15 + 15 + 15 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + + + 0x2 + 0x4 + GPMEM[%s] + Description collection: General purpose memory + 0x610 + read-write + 0x00000000 + + + GPMEM + General purpose memory + 0 + 31 + + + + + + + IPC_S + Interprocessor communication 1 + 0x5002A000 + + + + IPC + 42 + + + + QSPI_NS + External flash interface 0 + 0x4002B000 + QSPI + + + + 0 + 0x1000 + registers + + + QSPI + 43 + + QSPI + 0x20 + + + TASKS_ACTIVATE + Activate QSPI interface + 0x000 + write-only + + + TASKS_ACTIVATE + Activate QSPI interface + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_READSTART + Start transfer from external flash memory to internal RAM + 0x004 + write-only + + + TASKS_READSTART + Start transfer from external flash memory to internal RAM + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_WRITESTART + Start transfer from internal RAM to external flash memory + 0x008 + write-only + + + TASKS_WRITESTART + Start transfer from internal RAM to external flash memory + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_ERASESTART + Start external flash memory erase operation + 0x00C + write-only + + + TASKS_ERASESTART + Start external flash memory erase operation + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_DEACTIVATE + Deactivate QSPI interface + 0x010 + write-only + + + TASKS_DEACTIVATE + Deactivate QSPI interface + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_ACTIVATE + Subscribe configuration for task ACTIVATE + 0x080 + read-write + + + CHIDX + DPPI channel that task ACTIVATE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_READSTART + Subscribe configuration for task READSTART + 0x084 + read-write + + + CHIDX + DPPI channel that task READSTART will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_WRITESTART + Subscribe configuration for task WRITESTART + 0x088 + read-write + + + CHIDX + DPPI channel that task WRITESTART will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_ERASESTART + Subscribe configuration for task ERASESTART + 0x08C + read-write + + + CHIDX + DPPI channel that task ERASESTART will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_DEACTIVATE + Subscribe configuration for task DEACTIVATE + 0x090 + read-write + + + CHIDX + DPPI channel that task DEACTIVATE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_READY + QSPI peripheral is ready. This event will be generated as a response to all QSPI tasks except DEACTIVATE. + 0x100 + read-write + + + EVENTS_READY + QSPI peripheral is ready. This event will be generated as a response to all QSPI tasks except DEACTIVATE. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_READY + Publish configuration for event READY + 0x180 + read-write + + + CHIDX + DPPI channel that event READY will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + READY + Enable or disable interrupt for event READY + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + READY + Write '1' to enable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + READY + Write '1' to disable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + Enable QSPI peripheral and acquire the pins selected in PSELn registers + 0x500 + read-write + + + ENABLE + Enable or disable QSPI + 0 + 0 + + + Disabled + Disable QSPI + 0 + + + Enabled + Enable QSPI + 1 + + + + + + + READ + Unspecified + QSPI_READ + read-write + 0x504 + + SRC + Flash memory source address + 0x000 + read-write + + + SRC + Word-aligned flash memory source address. + 0 + 31 + + + + + DST + RAM destination address + 0x004 + read-write + + + DST + Word-aligned RAM destination address. + 0 + 31 + + + + + CNT + Read transfer length + 0x008 + read-write + + + CNT + Read transfer length in number of bytes. The length must be a multiple of 4 bytes. + 0 + 20 + + + + + + WRITE + Unspecified + QSPI_WRITE + read-write + 0x510 + + DST + Flash destination address + 0x000 + read-write + + + DST + Word-aligned flash destination address. + 0 + 31 + + + + + SRC + RAM source address + 0x004 + read-write + + + SRC + Word-aligned RAM source address. + 0 + 31 + + + + + CNT + Write transfer length + 0x008 + read-write + + + CNT + Write transfer length in number of bytes. The length must be a multiple of 4 bytes. + 0 + 20 + + + + + + ERASE + Unspecified + QSPI_ERASE + read-write + 0x51C + + PTR + Start address of flash block to be erased + 0x000 + read-write + + + PTR + Word-aligned start address of block to be erased. + 0 + 31 + + + + + LEN + Size of block to be erased. + 0x004 + read-write + + + LEN + LEN + 0 + 1 + + + 4KB + Erase 4 kB block (flash command 0x20) + 0 + + + 64KB + Erase 64 kB block (flash command 0xD8) + 1 + + + All + Erase all (flash command 0xC7) + 2 + + + + + + + + PSEL + Unspecified + QSPI_PSEL + read-write + 0x524 + + SCK + Pin select for serial clock SCK + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + CSN + Pin select for chip select signal CSN. + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + IO0 + Pin select for serial data MOSI/IO0. + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + IO1 + Pin select for serial data MISO/IO1. + 0x010 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + IO2 + Pin select for serial data WP/IO2. + 0x014 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + IO3 + Pin select for serial data HOLD/IO3. + 0x018 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + XIPOFFSET + Address offset into the external memory for Execute in Place operation. + 0x540 + read-write + + + XIPOFFSET + Address offset into the external memory for Execute in Place operation. Value must be a multiple of 4. + 0 + 31 + + + + + IFCONFIG0 + Interface configuration. + 0x544 + read-write + + + READOC + Configure number of data lines and opcode used for reading. + 0 + 2 + + + FASTREAD + Single data line SPI. FAST_READ (opcode 0x0B). + 0 + + + READ2O + Dual data line SPI. READ2O (opcode 0x3B). + 1 + + + READ2IO + Dual data line SPI. READ2IO (opcode 0xBB). + 2 + + + READ4O + Quad data line SPI. READ4O (opcode 0x6B). + 3 + + + READ4IO + Quad data line SPI. READ4IO (opcode 0xEB). + 4 + + + + + WRITEOC + Configure number of data lines and opcode used for writing. + 3 + 5 + + + PP + Single data line SPI. PP (opcode 0x02). + 0 + + + PP2O + Dual data line SPI. PP2O (opcode 0xA2). + 1 + + + PP4O + Quad data line SPI. PP4O (opcode 0x32). + 2 + + + PP4IO + Quad data line SPI. PP4IO (opcode 0x38). + 3 + + + + + ADDRMODE + Addressing mode. + 6 + 6 + + + 24BIT + 24-bit addressing. + 0 + + + 32BIT + 32-bit addressing. + 1 + + + + + DPMENABLE + Enable deep power-down mode (DPM) feature. + 7 + 7 + + + Disable + Disable DPM feature. + 0 + + + Enable + Enable DPM feature. + 1 + + + + + PPSIZE + Page size for commands PP, PP2O, PP4O and PP4IO. + 12 + 12 + + + 256Bytes + 256 bytes. + 0 + + + 512Bytes + 512 bytes. + 1 + + + + + + + XIPEN + Enable Execute in Place operation. + 0x54C + read-write + 0x00000001 + + + XIPEN + Enable XIP AHB Slave interface and access to XIP memory range + 0 + 0 + + + Disable + Disable XIP interface + 0 + + + Enable + Enable XIP interface + 1 + + + + + + + XIP_ENC + Unspecified + QSPI_XIP_ENC + read-write + 0x560 + + KEY0 + Bits 31:0 of XIP AES KEY + 0x000 + write-only + 0x00000000 + + + KEY0 + Bits 31:0 of XIP AES KEY + 0 + 31 + + + + + KEY1 + Bits 63:32 of XIP AES KEY + 0x004 + write-only + 0x00000000 + + + KEY1 + Bits 63:32 of XIP AES KEY + 0 + 31 + + + + + KEY2 + Bits 95:64 of XIP AES KEY + 0x008 + write-only + 0x00000000 + + + KEY2 + Bits 95:64 of XIP AES KEY + 0 + 31 + + + + + KEY3 + Bits 127:96 of XIP AES KEY + 0x00C + write-only + 0x00000000 + + + KEY3 + Bits 127:96 of XIP AES KEY + 0 + 31 + + + + + NONCE0 + Bits 31:0 of XIP NONCE + 0x010 + write-only + 0x00000000 + + + NONCE0 + Bits 31:0 of XIP NONCE + 0 + 31 + + + + + NONCE1 + Bits 63:32 of XIP NONCE + 0x014 + write-only + 0x00000000 + + + NONCE1 + Bits 63:32 of XIP NONCE + 0 + 31 + + + + + NONCE2 + Bits 95:64 of XIP NONCE + 0x018 + write-only + 0x00000000 + + + NONCE2 + Bits 95:64 of XIP NONCE + 0 + 31 + + + + + ENABLE + Enable stream cipher for XIP + 0x01C + read-write + + + ENABLE + Enable or disable stream cipher for XIP + 0 + 0 + + + Disabled + Disable stream cipher for QSPI XIP + 0 + + + Enabled + Enable stream cipher for QSPI XIP + 1 + + + + + + + + DMA_ENC + Unspecified + QSPI_DMA_ENC + read-write + 0x580 + + KEY0 + Bits 31:0 of DMA AES KEY + 0x000 + write-only + 0x00000000 + + + KEY0 + Bits 31:0 of DMA AES KEY + 0 + 31 + + + + + KEY1 + Bits 63:32 of DMA AES KEY + 0x004 + write-only + 0x00000000 + + + KEY1 + Bits 63:32 of DMA AES KEY + 0 + 31 + + + + + KEY2 + Bits 95:64 of DMA AES KEY + 0x008 + write-only + 0x00000000 + + + KEY2 + Bits 95:64 of DMA AES KEY + 0 + 31 + + + + + KEY3 + Bits 127:96 of DMA AES KEY + 0x00C + write-only + 0x00000000 + + + KEY3 + Bits 127:96 of DMA AES KEY + 0 + 31 + + + + + NONCE0 + Bits 31:0 of DMA NONCE + 0x010 + write-only + 0x00000000 + + + NONCE0 + Bits 31:0 of DMA NONCE + 0 + 31 + + + + + NONCE1 + Bits 63:32 of DMA NONCE + 0x014 + write-only + 0x00000000 + + + NONCE1 + Bits 63:32 of DMA NONCE + 0 + 31 + + + + + NONCE2 + Bits 95:64 of DMA NONCE + 0x018 + write-only + 0x00000000 + + + NONCE2 + Bits 95:64 of DMA NONCE + 0 + 31 + + + + + ENABLE + Enable stream cipher for EasyDMA + 0x01C + read-write + + + ENABLE + Enable or disable stream cipher for EasyDMA + 0 + 0 + + + Disabled + Disable stream cipher for QSPI EasyDMA + 0 + + + Enabled + Enable stream cipher for QSPI EasyDMA + 1 + + + + + + + + IFCONFIG1 + Interface configuration. + 0x600 + read-write + 0x00040480 + + + SCKDELAY + Minimum amount of time that the CSN pin must stay high before it can go low again. Value is specified in number of 32 MHz periods (31.25 ns). + 0 + 7 + + + DPMEN + Enter/exit deep power-down mode (DPM) for external flash memory. + 24 + 24 + + + Exit + Exit DPM. + 0 + + + Enter + Enter DPM. + 1 + + + + + SPIMODE + Select SPI mode. + 25 + 25 + + + MODE0 + Mode 0: Data are captured on the clock rising edge and data is output on a falling edge. Base level of clock is 0 (CPOL=0, CPHA=0). + 0 + + + MODE3 + Mode 3: Data are captured on the clock rising edge and data is output on a falling edge. Base level of clock is 1 (CPOL=1, CPHA=1). + 1 + + + + + SCKFREQ + SCK frequency is derived from PCLK192M with SCK frequency = PCLK192M / (2*(SCKFREQ + 1)). + 28 + 31 + + + + + STATUS + Status register. + 0x604 + read-only + + + DPM + Deep power-down mode (DPM) status of external flash. + 2 + 2 + + + Disabled + External flash is not in DPM. + 0 + + + Enabled + External flash is in DPM. + 1 + + + + + READY + Ready status. + 3 + 3 + + + READY + QSPI peripheral is ready. It is allowed to trigger new tasks, writing custom instructions or enter/exit DPM. + 1 + + + BUSY + QSPI peripheral is busy. It is not allowed to trigger any new tasks, writing custom instructions or enter/exit DPM. + 0 + + + + + SREG + Value of external flash device Status Register. When the external flash has two bytes status register this field includes the value of the low byte. + 24 + 31 + + + + + DPMDUR + Set the duration required to enter/exit deep power-down mode (DPM). + 0x614 + read-write + 0xFFFFFFFF + + + ENTER + Duration needed by external flash to enter DPM. Duration is given as ENTER * 256 * 31.25 ns + 0 + 15 + + + EXIT + Duration needed by external flash to exit DPM. Duration is given as EXIT * 256 * 31.25 ns. + 16 + 31 + + + + + ADDRCONF + Extended address configuration. + 0x624 + read-write + 0x000000B7 + + + OPCODE + Opcode that enters the 32-bit addressing mode. + 0 + 7 + + + BYTE0 + Byte 0 following opcode. + 8 + 15 + + + BYTE1 + Byte 1 following byte 0. + 16 + 23 + + + MODE + Extended addressing mode. + 24 + 25 + + + NoInstr + Do not send any instruction. + 0 + + + Opcode + Send opcode. + 1 + + + OpByte0 + Send opcode, BYTE0. + 2 + + + All + Send opcode, BYTE0, BYTE1. + 3 + + + + + WIPWAIT + Wait for write complete before sending command. + 26 + 26 + + + Disable + No wait. + 0 + + + Enable + Wait. + 1 + + + + + WREN + Send WREN (write enable opcode 0x06) before instruction. + 27 + 27 + + + Disable + Do not send WREN. + 0 + + + Enable + Send WREN. + 1 + + + + + + + CINSTRCONF + Custom instruction configuration register. + 0x634 + read-write + 0x00002000 + + + OPCODE + Opcode of Custom instruction. + 0 + 7 + + + LENGTH + Length of custom instruction in number of bytes. + 8 + 11 + + + 1B + Send opcode only. + 1 + + + 2B + Send opcode, CINSTRDAT0.BYTE0. + 2 + + + 3B + Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT0.BYTE1. + 3 + + + 4B + Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT0.BYTE2. + 4 + + + 5B + Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT0.BYTE3. + 5 + + + 6B + Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE4. + 6 + + + 7B + Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE5. + 7 + + + 8B + Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE6. + 8 + + + 9B + Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE7. + 9 + + + + + LIO2 + Level of the IO2 pin (if connected) during transmission of custom instruction. + 12 + 12 + + + LIO3 + Level of the IO3 pin (if connected) during transmission of custom instruction. + 13 + 13 + + + WIPWAIT + Wait for write complete before sending command. + 14 + 14 + + + Disable + No wait. + 0 + + + Enable + Wait. + 1 + + + + + WREN + Send WREN (write enable opcode 0x06) before instruction. + 15 + 15 + + + Disable + Do not send WREN. + 0 + + + Enable + Send WREN. + 1 + + + + + LFEN + Enable Long frame mode. When enabled, a custom instruction transaction has to be ended by writing the LFSTOP field. + 16 + 16 + + + Disable + Long frame mode disabled + 0 + + + Enable + Long frame mode enabled + 1 + + + + + LFSTOP + Stop (finalize) long frame transaction + 17 + 17 + + + Stop + Stop + 1 + + + + + + + CINSTRDAT0 + Custom instruction data register 0. + 0x638 + read-write + + + BYTE0 + Data byte 0 + 0 + 7 + + + BYTE1 + Data byte 1 + 8 + 15 + + + BYTE2 + Data byte 2 + 16 + 23 + + + BYTE3 + Data byte 3 + 24 + 31 + + + + + CINSTRDAT1 + Custom instruction data register 1. + 0x63C + read-write + + + BYTE4 + Data byte 4 + 0 + 7 + + + BYTE5 + Data byte 5 + 8 + 15 + + + BYTE6 + Data byte 6 + 16 + 23 + + + BYTE7 + Data byte 7 + 24 + 31 + + + + + IFTIMING + SPI interface timing. + 0x640 + read-write + 0x00000200 + + + RXDELAY + Timing related to sampling of the input serial data. The value of RXDELAY specifies the number of prescaled 192 MHz cycles delay from the the rising edge of the SPI Clock (SCK) until the input serial data is sampled. For example, if RXDELAY is set to 0, the input serial data is sampled on the rising edge of SCK. + 8 + 10 + + + + + + + QSPI_S + External flash interface 1 + 0x5002B000 + + + + QSPI + 43 + + + + NFCT_NS + NFC-A compatible radio 0 + 0x4002D000 + NFCT + + + + 0 + 0x1000 + registers + + + NFCT + 45 + + NFCT + 0x20 + + + TASKS_ACTIVATE + Activate NFCT peripheral for incoming and outgoing frames, change state to activated + 0x000 + write-only + + + TASKS_ACTIVATE + Activate NFCT peripheral for incoming and outgoing frames, change state to activated + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_DISABLE + Disable NFCT peripheral + 0x004 + write-only + + + TASKS_DISABLE + Disable NFCT peripheral + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SENSE + Enable NFC sense field mode, change state to sense mode + 0x008 + write-only + + + TASKS_SENSE + Enable NFC sense field mode, change state to sense mode + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTTX + Start transmission of an outgoing frame, change state to transmit + 0x00C + write-only + + + TASKS_STARTTX + Start transmission of an outgoing frame, change state to transmit + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_ENABLERXDATA + Initializes the EasyDMA for receive. + 0x01C + write-only + + + TASKS_ENABLERXDATA + Initializes the EasyDMA for receive. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_GOIDLE + Force state machine to IDLE state + 0x024 + write-only + + + TASKS_GOIDLE + Force state machine to IDLE state + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_GOSLEEP + Force state machine to SLEEP_A state + 0x028 + write-only + + + TASKS_GOSLEEP + Force state machine to SLEEP_A state + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_ACTIVATE + Subscribe configuration for task ACTIVATE + 0x080 + read-write + + + CHIDX + DPPI channel that task ACTIVATE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_DISABLE + Subscribe configuration for task DISABLE + 0x084 + read-write + + + CHIDX + DPPI channel that task DISABLE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_SENSE + Subscribe configuration for task SENSE + 0x088 + read-write + + + CHIDX + DPPI channel that task SENSE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STARTTX + Subscribe configuration for task STARTTX + 0x08C + read-write + + + CHIDX + DPPI channel that task STARTTX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_ENABLERXDATA + Subscribe configuration for task ENABLERXDATA + 0x09C + read-write + + + CHIDX + DPPI channel that task ENABLERXDATA will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_GOIDLE + Subscribe configuration for task GOIDLE + 0x0A4 + read-write + + + CHIDX + DPPI channel that task GOIDLE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_GOSLEEP + Subscribe configuration for task GOSLEEP + 0x0A8 + read-write + + + CHIDX + DPPI channel that task GOSLEEP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_READY + The NFCT peripheral is ready to receive and send frames + 0x100 + read-write + + + EVENTS_READY + The NFCT peripheral is ready to receive and send frames + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_FIELDDETECTED + Remote NFC field detected + 0x104 + read-write + + + EVENTS_FIELDDETECTED + Remote NFC field detected + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_FIELDLOST + Remote NFC field lost + 0x108 + read-write + + + EVENTS_FIELDLOST + Remote NFC field lost + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXFRAMESTART + Marks the start of the first symbol of a transmitted frame + 0x10C + read-write + + + EVENTS_TXFRAMESTART + Marks the start of the first symbol of a transmitted frame + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXFRAMEEND + Marks the end of the last transmitted on-air symbol of a frame + 0x110 + read-write + + + EVENTS_TXFRAMEEND + Marks the end of the last transmitted on-air symbol of a frame + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXFRAMESTART + Marks the end of the first symbol of a received frame + 0x114 + read-write + + + EVENTS_RXFRAMESTART + Marks the end of the first symbol of a received frame + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXFRAMEEND + Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer + 0x118 + read-write + + + EVENTS_RXFRAMEEND + Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + NFC error reported. The ERRORSTATUS register contains details on the source of the error. + 0x11C + read-write + + + EVENTS_ERROR + NFC error reported. The ERRORSTATUS register contains details on the source of the error. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXERROR + NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. + 0x128 + read-write + + + EVENTS_RXERROR + NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDRX + RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. + 0x12C + read-write + + + EVENTS_ENDRX + RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDTX + Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer + 0x130 + read-write + + + EVENTS_ENDTX + Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_AUTOCOLRESSTARTED + Auto collision resolution process has started + 0x138 + read-write + + + EVENTS_AUTOCOLRESSTARTED + Auto collision resolution process has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_COLLISION + NFC auto collision resolution error reported. + 0x148 + read-write + + + EVENTS_COLLISION + NFC auto collision resolution error reported. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SELECTED + NFC auto collision resolution successfully completed + 0x14C + read-write + + + EVENTS_SELECTED + NFC auto collision resolution successfully completed + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STARTED + EasyDMA is ready to receive or send frames. + 0x150 + read-write + + + EVENTS_STARTED + EasyDMA is ready to receive or send frames. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_READY + Publish configuration for event READY + 0x180 + read-write + + + CHIDX + DPPI channel that event READY will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_FIELDDETECTED + Publish configuration for event FIELDDETECTED + 0x184 + read-write + + + CHIDX + DPPI channel that event FIELDDETECTED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_FIELDLOST + Publish configuration for event FIELDLOST + 0x188 + read-write + + + CHIDX + DPPI channel that event FIELDLOST will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_TXFRAMESTART + Publish configuration for event TXFRAMESTART + 0x18C + read-write + + + CHIDX + DPPI channel that event TXFRAMESTART will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_TXFRAMEEND + Publish configuration for event TXFRAMEEND + 0x190 + read-write + + + CHIDX + DPPI channel that event TXFRAMEEND will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_RXFRAMESTART + Publish configuration for event RXFRAMESTART + 0x194 + read-write + + + CHIDX + DPPI channel that event RXFRAMESTART will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_RXFRAMEEND + Publish configuration for event RXFRAMEEND + 0x198 + read-write + + + CHIDX + DPPI channel that event RXFRAMEEND will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ERROR + Publish configuration for event ERROR + 0x19C + read-write + + + CHIDX + DPPI channel that event ERROR will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_RXERROR + Publish configuration for event RXERROR + 0x1A8 + read-write + + + CHIDX + DPPI channel that event RXERROR will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ENDRX + Publish configuration for event ENDRX + 0x1AC + read-write + + + CHIDX + DPPI channel that event ENDRX will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ENDTX + Publish configuration for event ENDTX + 0x1B0 + read-write + + + CHIDX + DPPI channel that event ENDTX will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_AUTOCOLRESSTARTED + Publish configuration for event AUTOCOLRESSTARTED + 0x1B8 + read-write + + + CHIDX + DPPI channel that event AUTOCOLRESSTARTED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_COLLISION + Publish configuration for event COLLISION + 0x1C8 + read-write + + + CHIDX + DPPI channel that event COLLISION will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_SELECTED + Publish configuration for event SELECTED + 0x1CC + read-write + + + CHIDX + DPPI channel that event SELECTED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_STARTED + Publish configuration for event STARTED + 0x1D0 + read-write + + + CHIDX + DPPI channel that event STARTED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + FIELDDETECTED_ACTIVATE + Shortcut between event FIELDDETECTED and task ACTIVATE + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + FIELDLOST_SENSE + Shortcut between event FIELDLOST and task SENSE + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + TXFRAMEEND_ENABLERXDATA + Shortcut between event TXFRAMEEND and task ENABLERXDATA + 5 + 5 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + READY + Enable or disable interrupt for event READY + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + FIELDDETECTED + Enable or disable interrupt for event FIELDDETECTED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + FIELDLOST + Enable or disable interrupt for event FIELDLOST + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXFRAMESTART + Enable or disable interrupt for event TXFRAMESTART + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXFRAMEEND + Enable or disable interrupt for event TXFRAMEEND + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXFRAMESTART + Enable or disable interrupt for event RXFRAMESTART + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXFRAMEEND + Enable or disable interrupt for event RXFRAMEEND + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXERROR + Enable or disable interrupt for event RXERROR + 10 + 10 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDRX + Enable or disable interrupt for event ENDRX + 11 + 11 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDTX + Enable or disable interrupt for event ENDTX + 12 + 12 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + AUTOCOLRESSTARTED + Enable or disable interrupt for event AUTOCOLRESSTARTED + 14 + 14 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COLLISION + Enable or disable interrupt for event COLLISION + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SELECTED + Enable or disable interrupt for event SELECTED + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + STARTED + Enable or disable interrupt for event STARTED + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + READY + Write '1' to enable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + FIELDDETECTED + Write '1' to enable interrupt for event FIELDDETECTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + FIELDLOST + Write '1' to enable interrupt for event FIELDLOST + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXFRAMESTART + Write '1' to enable interrupt for event TXFRAMESTART + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXFRAMEEND + Write '1' to enable interrupt for event TXFRAMEEND + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXFRAMESTART + Write '1' to enable interrupt for event RXFRAMESTART + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXFRAMEEND + Write '1' to enable interrupt for event RXFRAMEEND + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXERROR + Write '1' to enable interrupt for event RXERROR + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDRX + Write '1' to enable interrupt for event ENDRX + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDTX + Write '1' to enable interrupt for event ENDTX + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + AUTOCOLRESSTARTED + Write '1' to enable interrupt for event AUTOCOLRESSTARTED + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COLLISION + Write '1' to enable interrupt for event COLLISION + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SELECTED + Write '1' to enable interrupt for event SELECTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STARTED + Write '1' to enable interrupt for event STARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + READY + Write '1' to disable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + FIELDDETECTED + Write '1' to disable interrupt for event FIELDDETECTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + FIELDLOST + Write '1' to disable interrupt for event FIELDLOST + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXFRAMESTART + Write '1' to disable interrupt for event TXFRAMESTART + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXFRAMEEND + Write '1' to disable interrupt for event TXFRAMEEND + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXFRAMESTART + Write '1' to disable interrupt for event RXFRAMESTART + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXFRAMEEND + Write '1' to disable interrupt for event RXFRAMEEND + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXERROR + Write '1' to disable interrupt for event RXERROR + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDRX + Write '1' to disable interrupt for event ENDRX + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDTX + Write '1' to disable interrupt for event ENDTX + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + AUTOCOLRESSTARTED + Write '1' to disable interrupt for event AUTOCOLRESSTARTED + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COLLISION + Write '1' to disable interrupt for event COLLISION + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SELECTED + Write '1' to disable interrupt for event SELECTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STARTED + Write '1' to disable interrupt for event STARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSTATUS + NFC Error Status register + 0x404 + read-write + oneToClear + + + FRAMEDELAYTIMEOUT + No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX + 0 + 0 + + + + + FRAMESTATUS + Unspecified + NFCT_FRAMESTATUS + read-write + 0x40C + + RX + Result of last incoming frame + 0x000 + read-write + oneToClear + + + CRCERROR + No valid end of frame (EoF) detected + 0 + 0 + + + CRCCorrect + Valid CRC detected + 0 + + + CRCError + CRC received does not match local check + 1 + + + + + PARITYSTATUS + Parity status of received frame + 2 + 2 + + + ParityOK + Frame received with parity OK + 0 + + + ParityError + Frame received with parity error + 1 + + + + + OVERRUN + Overrun detected + 3 + 3 + + + NoOverrun + No overrun detected + 0 + + + Overrun + Overrun error + 1 + + + + + + + + NFCTAGSTATE + Current operating state of NFC tag + 0x410 + read-only + + + NFCTAGSTATE + NfcTag state + 0 + 2 + + + Disabled + Disabled or sense + 0 + + + RampUp + RampUp + 2 + + + Idle + Idle + 3 + + + Receive + Receive + 4 + + + FrameDelay + FrameDelay + 5 + + + Transmit + Transmit + 6 + + + + + + + SLEEPSTATE + Sleep state during automatic collision resolution + 0x420 + read-only + 0x00000000 + + + SLEEPSTATE + Reflects the sleep state during automatic collision resolution. Set to IDLE + by a GOIDLE task. Set to SLEEP_A when a valid SLEEP_REQ frame is received or by a + GOSLEEP task. + 0 + 0 + + + Idle + State is IDLE. + 0 + + + SleepA + State is SLEEP_A. + 1 + + + + + + + FIELDPRESENT + Indicates the presence or not of a valid field + 0x43C + read-only + + + FIELDPRESENT + Indicates if a valid field is present. Available only in the activated state. + 0 + 0 + + + NoField + No valid field detected + 0 + + + FieldPresent + Valid field detected + 1 + + + + + LOCKDETECT + Indicates if the low level has locked to the field + 1 + 1 + + + NotLocked + Not locked to field + 0 + + + Locked + Locked to field + 1 + + + + + + + FRAMEDELAYMIN + Minimum frame delay + 0x504 + read-write + 0x00000480 + + + FRAMEDELAYMIN + Minimum frame delay in number of 13.56 MHz clock cycles + 0 + 15 + + + + + FRAMEDELAYMAX + Maximum frame delay + 0x508 + read-write + 0x00001000 + + + FRAMEDELAYMAX + Maximum frame delay in number of 13.56 MHz clock cycles + 0 + 19 + + + + + FRAMEDELAYMODE + Configuration register for the Frame Delay Timer + 0x50C + read-write + 0x00000001 + + + FRAMEDELAYMODE + Configuration register for the Frame Delay Timer + 0 + 1 + + + FreeRun + Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. + 0 + + + Window + Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX + 1 + + + ExactVal + Frame is transmitted exactly at FRAMEDELAYMAX + 2 + + + WindowGrid + Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX + 3 + + + + + + + PACKETPTR + Packet pointer for TXD and RXD data storage in Data RAM + 0x510 + read-write + 0x00000000 + + + PTR + Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte-aligned RAM address. + 0 + 31 + + + + + MAXLEN + Size of the RAM buffer allocated to TXD and RXD data storage each + 0x514 + read-write + + + MAXLEN + Size of the RAM buffer allocated to TXD and RXD data storage each + 0 + 8 + + + + + TXD + Unspecified + NFCT_TXD + read-write + 0x518 + + FRAMECONFIG + Configuration of outgoing frames + 0x000 + read-write + 0x00000017 + + + PARITY + Indicates if parity is added to the frame + 0 + 0 + + + NoParity + Parity is not added to TX frames + 0 + + + Parity + Parity is added to TX frames + 1 + + + + + DISCARDMODE + Discarding unused bits at start or end of a frame + 1 + 1 + + + DiscardEnd + Unused bits are discarded at end of frame (EoF) + 0 + + + DiscardStart + Unused bits are discarded at start of frame (SoF) + 1 + + + + + SOF + Adding SoF or not in TX frames + 2 + 2 + + + NoSoF + SoF symbol not added + 0 + + + SoF + SoF symbol added + 1 + + + + + CRCMODETX + CRC mode for outgoing frames + 4 + 4 + + + NoCRCTX + CRC is not added to the frame + 0 + + + CRC16TX + 16 bit CRC added to the frame based on all the data read from RAM that is used in the frame + 1 + + + + + + + AMOUNT + Size of outgoing frame + 0x004 + read-write + + + TXDATABITS + Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit). + 0 + 2 + + + TXDATABYTES + Number of complete bytes that shall be included in the frame, excluding CRC, parity, and framing. + 3 + 11 + + + + + + RXD + Unspecified + NFCT_RXD + read-write + 0x520 + + FRAMECONFIG + Configuration of incoming frames + 0x000 + read-write + 0x00000015 + + + PARITY + Indicates if parity expected in RX frame + 0 + 0 + + + NoParity + Parity is not expected in RX frames + 0 + + + Parity + Parity is expected in RX frames + 1 + + + + + SOF + SoF expected or not in RX frames + 2 + 2 + + + NoSoF + SoF symbol is not expected in RX frames + 0 + + + SoF + SoF symbol is expected in RX frames + 1 + + + + + CRCMODERX + CRC mode for incoming frames + 4 + 4 + + + NoCRCRX + CRC is not expected in RX frames + 0 + + + CRC16RX + Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated + 1 + + + + + + + AMOUNT + Size of last incoming frame + 0x004 + read-only + + + RXDATABITS + Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing). + 0 + 2 + + + RXDATABYTES + Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing) + 3 + 11 + + + + + + MODULATIONCTRL + Enables the modulation output to a GPIO pin which can be connected to a second external antenna. + 0x52C + read-write + 0x00000001 + + + MODULATIONCTRL + Configuration of modulation control. + 0 + 1 + + + Invalid + Invalid, defaults to same behaviour as for Internal + 0x0 + + + Internal + Use internal modulator only + 0x1 + + + ModToGpio + Output digital modulation signal to a GPIO pin. + 0x2 + + + InternalAndModToGpio + Use internal modulator and output digital modulation signal to a GPIO pin. + 0x3 + + + + + + + MODULATIONPSEL + Pin select for Modulation control + 0x538 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + NFCID1_LAST + Last NFCID1 part (4, 7 or 10 bytes ID) + 0x590 + read-write + 0x00006363 + + + NFCID1_Z + NFCID1 byte Z (very last byte sent) + 0 + 7 + + + NFCID1_Y + NFCID1 byte Y + 8 + 15 + + + NFCID1_X + NFCID1 byte X + 16 + 23 + + + NFCID1_W + NFCID1 byte W + 24 + 31 + + + + + NFCID1_2ND_LAST + Second last NFCID1 part (7 or 10 bytes ID) + 0x594 + read-write + + + NFCID1_V + NFCID1 byte V + 0 + 7 + + + NFCID1_U + NFCID1 byte U + 8 + 15 + + + NFCID1_T + NFCID1 byte T + 16 + 23 + + + + + NFCID1_3RD_LAST + Third last NFCID1 part (10 bytes ID) + 0x598 + read-write + + + NFCID1_S + NFCID1 byte S + 0 + 7 + + + NFCID1_R + NFCID1 byte R + 8 + 15 + + + NFCID1_Q + NFCID1 byte Q + 16 + 23 + + + + + AUTOCOLRESCONFIG + Controls the auto collision resolution function. This setting must be done before the NFCT peripheral is activated. + 0x59C + read-write + 0x00000002 + + + MODE + Enables/disables auto collision resolution + 0 + 0 + + + Enabled + Auto collision resolution enabled + 0 + + + Disabled + Auto collision resolution disabled + 1 + + + + + + + SENSRES + NFC-A SENS_RES auto-response settings + 0x5A0 + read-write + 0x00000001 + + + BITFRAMESDD + Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification + 0 + 4 + + + SDD00000 + SDD pattern 00000 + 0 + + + SDD00001 + SDD pattern 00001 + 1 + + + SDD00010 + SDD pattern 00010 + 2 + + + SDD00100 + SDD pattern 00100 + 4 + + + SDD01000 + SDD pattern 01000 + 8 + + + SDD10000 + SDD pattern 10000 + 16 + + + + + RFU5 + Reserved for future use. Shall be 0. + 5 + 5 + + + NFCIDSIZE + NFCID1 size. This value is used by the auto collision resolution engine. + 6 + 7 + + + NFCID1Single + NFCID1 size: single (4 bytes) + 0 + + + NFCID1Double + NFCID1 size: double (7 bytes) + 1 + + + NFCID1Triple + NFCID1 size: triple (10 bytes) + 2 + + + + + PLATFCONFIG + Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification + 8 + 11 + + + RFU74 + Reserved for future use. Shall be 0. + 12 + 15 + + + + + SELRES + NFC-A SEL_RES auto-response settings + 0x5A4 + read-write + + + RFU10 + Reserved for future use. Shall be 0. + 0 + 1 + + + CASCADE + Cascade as defined by the b3 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification (controlled by hardware, shall be 0) + 2 + 2 + + + RFU43 + Reserved for future use. Shall be 0. + 3 + 4 + + + PROTOCOL + Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification + 5 + 6 + + + RFU7 + Reserved for future use. Shall be 0. + 7 + 7 + + + + + + + NFCT_S + NFC-A compatible radio 1 + 0x5002D000 + + + + NFCT + 45 + + + + GPIOTE1_NS + GPIO Tasks and Events 1 + 0x4002F000 + + + + GPIOTE1 + 47 + + + + MUTEX_NS + MUTEX 0 + 0x40030000 + MUTEX + + + + 0 + 0x1000 + registers + + MUTEX + 0x20 + + + 0x10 + 0x4 + MUTEX[%s] + Description collection: Mutex register + 0x400 + read-write + + + MUTEX + Mutex register n + 0 + 0 + + + Unlocked + Mutex n is in unlocked state + 0 + + + Locked + Mutex n is in locked state + 1 + + + + + + + + + MUTEX_S + MUTEX 1 + 0x50030000 + + + + + QDEC0_NS + Quadrature Decoder 0 + 0x40033000 + QDEC + + + + 0 + 0x1000 + registers + + + QDEC0 + 51 + + QDEC + 0x20 + + + TASKS_START + Task starting the quadrature decoder + 0x000 + write-only + + + TASKS_START + Task starting the quadrature decoder + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Task stopping the quadrature decoder + 0x004 + write-only + + + TASKS_STOP + Task stopping the quadrature decoder + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_READCLRACC + Read and clear ACC and ACCDBL + 0x008 + write-only + + + TASKS_READCLRACC + Read and clear ACC and ACCDBL + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RDCLRACC + Read and clear ACC + 0x00C + write-only + + + TASKS_RDCLRACC + Read and clear ACC + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RDCLRDBL + Read and clear ACCDBL + 0x010 + write-only + + + TASKS_RDCLRDBL + Read and clear ACCDBL + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_READCLRACC + Subscribe configuration for task READCLRACC + 0x088 + read-write + + + CHIDX + DPPI channel that task READCLRACC will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_RDCLRACC + Subscribe configuration for task RDCLRACC + 0x08C + read-write + + + CHIDX + DPPI channel that task RDCLRACC will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_RDCLRDBL + Subscribe configuration for task RDCLRDBL + 0x090 + read-write + + + CHIDX + DPPI channel that task RDCLRDBL will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_SAMPLERDY + Event being generated for every new sample value written to the SAMPLE register + 0x100 + read-write + + + EVENTS_SAMPLERDY + Event being generated for every new sample value written to the SAMPLE register + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_REPORTRDY + Non-null report ready + 0x104 + read-write + + + EVENTS_REPORTRDY + Non-null report ready + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ACCOF + ACC or ACCDBL register overflow + 0x108 + read-write + + + EVENTS_ACCOF + ACC or ACCDBL register overflow + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DBLRDY + Double displacement(s) detected + 0x10C + read-write + + + EVENTS_DBLRDY + Double displacement(s) detected + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STOPPED + QDEC has been stopped + 0x110 + read-write + + + EVENTS_STOPPED + QDEC has been stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_SAMPLERDY + Publish configuration for event SAMPLERDY + 0x180 + read-write + + + CHIDX + DPPI channel that event SAMPLERDY will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_REPORTRDY + Publish configuration for event REPORTRDY + 0x184 + read-write + + + CHIDX + DPPI channel that event REPORTRDY will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ACCOF + Publish configuration for event ACCOF + 0x188 + read-write + + + CHIDX + DPPI channel that event ACCOF will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_DBLRDY + Publish configuration for event DBLRDY + 0x18C + read-write + + + CHIDX + DPPI channel that event DBLRDY will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x190 + read-write + + + CHIDX + DPPI channel that event STOPPED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + REPORTRDY_READCLRACC + Shortcut between event REPORTRDY and task READCLRACC + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + SAMPLERDY_STOP + Shortcut between event SAMPLERDY and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + REPORTRDY_RDCLRACC + Shortcut between event REPORTRDY and task RDCLRACC + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + REPORTRDY_STOP + Shortcut between event REPORTRDY and task STOP + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DBLRDY_RDCLRDBL + Shortcut between event DBLRDY and task RDCLRDBL + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DBLRDY_STOP + Shortcut between event DBLRDY and task STOP + 5 + 5 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + SAMPLERDY_READCLRACC + Shortcut between event SAMPLERDY and task READCLRACC + 6 + 6 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + SAMPLERDY + Write '1' to enable interrupt for event SAMPLERDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + REPORTRDY + Write '1' to enable interrupt for event REPORTRDY + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ACCOF + Write '1' to enable interrupt for event ACCOF + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DBLRDY + Write '1' to enable interrupt for event DBLRDY + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + SAMPLERDY + Write '1' to disable interrupt for event SAMPLERDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REPORTRDY + Write '1' to disable interrupt for event REPORTRDY + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ACCOF + Write '1' to disable interrupt for event ACCOF + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DBLRDY + Write '1' to disable interrupt for event DBLRDY + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + Enable the quadrature decoder + 0x500 + read-write + + + ENABLE + Enable or disable the quadrature decoder + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + LEDPOL + LED output pin polarity + 0x504 + read-write + + + LEDPOL + LED output pin polarity + 0 + 0 + + + ActiveLow + Led active on output pin low + 0 + + + ActiveHigh + Led active on output pin high + 1 + + + + + + + SAMPLEPER + Sample period + 0x508 + read-write + + + SAMPLEPER + Sample period. The SAMPLE register will be updated for every new sample + 0 + 3 + + + 128us + 128 us + 0 + + + 256us + 256 us + 1 + + + 512us + 512 us + 2 + + + 1024us + 1024 us + 3 + + + 2048us + 2048 us + 4 + + + 4096us + 4096 us + 5 + + + 8192us + 8192 us + 6 + + + 16384us + 16384 us + 7 + + + 32ms + 32768 us + 8 + + + 65ms + 65536 us + 9 + + + 131ms + 131072 us + 10 + + + + + + + SAMPLE + Motion sample value + 0x50C + read-only + int32_t + + + SAMPLE + Last motion sample + 0 + 31 + + + + + REPORTPER + Number of samples to be taken before REPORTRDY and DBLRDY events can be generated + 0x510 + read-write + + + REPORTPER + Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated. + 0 + 3 + + + 10Smpl + 10 samples/report + 0 + + + 40Smpl + 40 samples/report + 1 + + + 80Smpl + 80 samples/report + 2 + + + 120Smpl + 120 samples/report + 3 + + + 160Smpl + 160 samples/report + 4 + + + 200Smpl + 200 samples/report + 5 + + + 240Smpl + 240 samples/report + 6 + + + 280Smpl + 280 samples/report + 7 + + + 1Smpl + 1 sample/report + 8 + + + + + + + ACC + Register accumulating the valid transitions + 0x514 + read-only + int32_t + + + ACC + Register accumulating all valid samples (not double transition) read from the SAMPLE register. + 0 + 31 + + + + + ACCREAD + Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task + 0x518 + read-only + int32_t + + + ACCREAD + Snapshot of the ACC register. + 0 + 31 + + + + + PSEL + Unspecified + QDEC_PSEL + read-write + 0x51C + + LED + Pin select for LED signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + A + Pin select for A signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + B + Pin select for B signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + DBFEN + Enable input debounce filters + 0x528 + read-write + + + DBFEN + Enable input debounce filters + 0 + 0 + + + Disabled + Debounce input filters disabled + 0 + + + Enabled + Debounce input filters enabled + 1 + + + + + + + LEDPRE + Time period the LED is switched ON prior to sampling + 0x540 + read-write + 0x00000010 + + + LEDPRE + Period in us the LED is switched on prior to sampling + 0 + 8 + + + + + ACCDBL + Register accumulating the number of detected double transitions + 0x544 + read-only + + + ACCDBL + Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). + 0 + 3 + + + + + ACCDBLREAD + Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task + 0x548 + read-only + + + ACCDBLREAD + Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. + 0 + 3 + + + + + + + QDEC0_S + Quadrature Decoder 1 + 0x50033000 + + + + QDEC0 + 51 + + + + QDEC1_NS + Quadrature Decoder 2 + 0x40034000 + + + + QDEC1 + 52 + + + + QDEC1_S + Quadrature Decoder 3 + 0x50034000 + + + + QDEC1 + 52 + + + + USBD_NS + Universal serial bus device 0 + 0x40036000 + USBD + + + + 0 + 0x1000 + registers + + + USBD + 54 + + USBD + 0x20 + + + 0x8 + 0x4 + TASKS_STARTEPIN[%s] + Description collection: Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host + 0x004 + write-only + + + TASKS_STARTEPIN + Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTISOIN + Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint + 0x024 + write-only + + + TASKS_STARTISOIN + Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x8 + 0x4 + TASKS_STARTEPOUT[%s] + Description collection: Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host + 0x028 + write-only + + + TASKS_STARTEPOUT + Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTISOOUT + Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint + 0x048 + write-only + + + TASKS_STARTISOOUT + Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_EP0RCVOUT + Allows OUT data stage on control endpoint 0 + 0x04C + write-only + + + TASKS_EP0RCVOUT + Allows OUT data stage on control endpoint 0 + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_EP0STATUS + Allows status stage on control endpoint 0 + 0x050 + write-only + + + TASKS_EP0STATUS + Allows status stage on control endpoint 0 + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_EP0STALL + Stalls data and status stage on control endpoint 0 + 0x054 + write-only + + + TASKS_EP0STALL + Stalls data and status stage on control endpoint 0 + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_DPDMDRIVE + Forces D+ and D- lines into the state defined in the DPDMVALUE register + 0x058 + write-only + + + TASKS_DPDMDRIVE + Forces D+ and D- lines into the state defined in the DPDMVALUE register + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_DPDMNODRIVE + Stops forcing D+ and D- lines into any state (USB engine takes control) + 0x05C + write-only + + + TASKS_DPDMNODRIVE + Stops forcing D+ and D- lines into any state (USB engine takes control) + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_STARTEPIN[%s] + Description collection: Subscribe configuration for task STARTEPIN[n] + 0x084 + read-write + + + CHIDX + DPPI channel that task STARTEPIN[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STARTISOIN + Subscribe configuration for task STARTISOIN + 0x0A4 + read-write + + + CHIDX + DPPI channel that task STARTISOIN will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_STARTEPOUT[%s] + Description collection: Subscribe configuration for task STARTEPOUT[n] + 0x0A8 + read-write + + + CHIDX + DPPI channel that task STARTEPOUT[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STARTISOOUT + Subscribe configuration for task STARTISOOUT + 0x0C8 + read-write + + + CHIDX + DPPI channel that task STARTISOOUT will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_EP0RCVOUT + Subscribe configuration for task EP0RCVOUT + 0x0CC + read-write + + + CHIDX + DPPI channel that task EP0RCVOUT will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_EP0STATUS + Subscribe configuration for task EP0STATUS + 0x0D0 + read-write + + + CHIDX + DPPI channel that task EP0STATUS will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_EP0STALL + Subscribe configuration for task EP0STALL + 0x0D4 + read-write + + + CHIDX + DPPI channel that task EP0STALL will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_DPDMDRIVE + Subscribe configuration for task DPDMDRIVE + 0x0D8 + read-write + + + CHIDX + DPPI channel that task DPDMDRIVE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_DPDMNODRIVE + Subscribe configuration for task DPDMNODRIVE + 0x0DC + read-write + + + CHIDX + DPPI channel that task DPDMNODRIVE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_USBRESET + Signals that a USB reset condition has been detected on USB lines + 0x100 + read-write + + + EVENTS_USBRESET + Signals that a USB reset condition has been detected on USB lines + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STARTED + Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register + 0x104 + read-write + + + EVENTS_STARTED + Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x8 + 0x4 + EVENTS_ENDEPIN[%s] + Description collection: The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software. + 0x108 + read-write + + + EVENTS_ENDEPIN + The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_EP0DATADONE + An acknowledged data transfer has taken place on the control endpoint + 0x128 + read-write + + + EVENTS_EP0DATADONE + An acknowledged data transfer has taken place on the control endpoint + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDISOIN + The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software. + 0x12C + read-write + + + EVENTS_ENDISOIN + The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x8 + 0x4 + EVENTS_ENDEPOUT[%s] + Description collection: The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software. + 0x130 + read-write + + + EVENTS_ENDEPOUT + The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDISOOUT + The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software. + 0x150 + read-write + + + EVENTS_ENDISOOUT + The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SOF + Signals that a SOF (start of frame) condition has been detected on USB lines + 0x154 + read-write + + + EVENTS_SOF + Signals that a SOF (start of frame) condition has been detected on USB lines + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_USBEVENT + An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. + 0x158 + read-write + + + EVENTS_USBEVENT + An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_EP0SETUP + A valid SETUP token has been received (and acknowledged) on the control endpoint + 0x15C + read-write + + + EVENTS_EP0SETUP + A valid SETUP token has been received (and acknowledged) on the control endpoint + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_EPDATA + A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register + 0x160 + read-write + + + EVENTS_EPDATA + A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_USBRESET + Publish configuration for event USBRESET + 0x180 + read-write + + + CHIDX + DPPI channel that event USBRESET will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_STARTED + Publish configuration for event STARTED + 0x184 + read-write + + + CHIDX + DPPI channel that event STARTED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + 0x8 + 0x4 + PUBLISH_ENDEPIN[%s] + Description collection: Publish configuration for event ENDEPIN[n] + 0x188 + read-write + + + CHIDX + DPPI channel that event ENDEPIN[n] will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_EP0DATADONE + Publish configuration for event EP0DATADONE + 0x1A8 + read-write + + + CHIDX + DPPI channel that event EP0DATADONE will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ENDISOIN + Publish configuration for event ENDISOIN + 0x1AC + read-write + + + CHIDX + DPPI channel that event ENDISOIN will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + 0x8 + 0x4 + PUBLISH_ENDEPOUT[%s] + Description collection: Publish configuration for event ENDEPOUT[n] + 0x1B0 + read-write + + + CHIDX + DPPI channel that event ENDEPOUT[n] will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ENDISOOUT + Publish configuration for event ENDISOOUT + 0x1D0 + read-write + + + CHIDX + DPPI channel that event ENDISOOUT will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_SOF + Publish configuration for event SOF + 0x1D4 + read-write + + + CHIDX + DPPI channel that event SOF will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_USBEVENT + Publish configuration for event USBEVENT + 0x1D8 + read-write + + + CHIDX + DPPI channel that event USBEVENT will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_EP0SETUP + Publish configuration for event EP0SETUP + 0x1DC + read-write + + + CHIDX + DPPI channel that event EP0SETUP will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_EPDATA + Publish configuration for event EPDATA + 0x1E0 + read-write + + + CHIDX + DPPI channel that event EPDATA will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + EP0DATADONE_STARTEPIN0 + Shortcut between event EP0DATADONE and task STARTEPIN[0] + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + EP0DATADONE_STARTEPOUT0 + Shortcut between event EP0DATADONE and task STARTEPOUT[0] + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + EP0DATADONE_EP0STATUS + Shortcut between event EP0DATADONE and task EP0STATUS + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + ENDEPOUT0_EP0STATUS + Shortcut between event ENDEPOUT[0] and task EP0STATUS + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + ENDEPOUT0_EP0RCVOUT + Shortcut between event ENDEPOUT[0] and task EP0RCVOUT + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + USBRESET + Enable or disable interrupt for event USBRESET + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + STARTED + Enable or disable interrupt for event STARTED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPIN0 + Enable or disable interrupt for event ENDEPIN[0] + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPIN1 + Enable or disable interrupt for event ENDEPIN[1] + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPIN2 + Enable or disable interrupt for event ENDEPIN[2] + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPIN3 + Enable or disable interrupt for event ENDEPIN[3] + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPIN4 + Enable or disable interrupt for event ENDEPIN[4] + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPIN5 + Enable or disable interrupt for event ENDEPIN[5] + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPIN6 + Enable or disable interrupt for event ENDEPIN[6] + 8 + 8 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPIN7 + Enable or disable interrupt for event ENDEPIN[7] + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + EP0DATADONE + Enable or disable interrupt for event EP0DATADONE + 10 + 10 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDISOIN + Enable or disable interrupt for event ENDISOIN + 11 + 11 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPOUT0 + Enable or disable interrupt for event ENDEPOUT[0] + 12 + 12 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPOUT1 + Enable or disable interrupt for event ENDEPOUT[1] + 13 + 13 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPOUT2 + Enable or disable interrupt for event ENDEPOUT[2] + 14 + 14 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPOUT3 + Enable or disable interrupt for event ENDEPOUT[3] + 15 + 15 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPOUT4 + Enable or disable interrupt for event ENDEPOUT[4] + 16 + 16 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPOUT5 + Enable or disable interrupt for event ENDEPOUT[5] + 17 + 17 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPOUT6 + Enable or disable interrupt for event ENDEPOUT[6] + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPOUT7 + Enable or disable interrupt for event ENDEPOUT[7] + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDISOOUT + Enable or disable interrupt for event ENDISOOUT + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SOF + Enable or disable interrupt for event SOF + 21 + 21 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + USBEVENT + Enable or disable interrupt for event USBEVENT + 22 + 22 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + EP0SETUP + Enable or disable interrupt for event EP0SETUP + 23 + 23 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + EPDATA + Enable or disable interrupt for event EPDATA + 24 + 24 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + USBRESET + Write '1' to enable interrupt for event USBRESET + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STARTED + Write '1' to enable interrupt for event STARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPIN0 + Write '1' to enable interrupt for event ENDEPIN[0] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPIN1 + Write '1' to enable interrupt for event ENDEPIN[1] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPIN2 + Write '1' to enable interrupt for event ENDEPIN[2] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPIN3 + Write '1' to enable interrupt for event ENDEPIN[3] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPIN4 + Write '1' to enable interrupt for event ENDEPIN[4] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPIN5 + Write '1' to enable interrupt for event ENDEPIN[5] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPIN6 + Write '1' to enable interrupt for event ENDEPIN[6] + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPIN7 + Write '1' to enable interrupt for event ENDEPIN[7] + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + EP0DATADONE + Write '1' to enable interrupt for event EP0DATADONE + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDISOIN + Write '1' to enable interrupt for event ENDISOIN + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPOUT0 + Write '1' to enable interrupt for event ENDEPOUT[0] + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPOUT1 + Write '1' to enable interrupt for event ENDEPOUT[1] + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPOUT2 + Write '1' to enable interrupt for event ENDEPOUT[2] + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPOUT3 + Write '1' to enable interrupt for event ENDEPOUT[3] + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPOUT4 + Write '1' to enable interrupt for event ENDEPOUT[4] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPOUT5 + Write '1' to enable interrupt for event ENDEPOUT[5] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPOUT6 + Write '1' to enable interrupt for event ENDEPOUT[6] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPOUT7 + Write '1' to enable interrupt for event ENDEPOUT[7] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDISOOUT + Write '1' to enable interrupt for event ENDISOOUT + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SOF + Write '1' to enable interrupt for event SOF + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + USBEVENT + Write '1' to enable interrupt for event USBEVENT + 22 + 22 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + EP0SETUP + Write '1' to enable interrupt for event EP0SETUP + 23 + 23 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + EPDATA + Write '1' to enable interrupt for event EPDATA + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + USBRESET + Write '1' to disable interrupt for event USBRESET + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STARTED + Write '1' to disable interrupt for event STARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPIN0 + Write '1' to disable interrupt for event ENDEPIN[0] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPIN1 + Write '1' to disable interrupt for event ENDEPIN[1] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPIN2 + Write '1' to disable interrupt for event ENDEPIN[2] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPIN3 + Write '1' to disable interrupt for event ENDEPIN[3] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPIN4 + Write '1' to disable interrupt for event ENDEPIN[4] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPIN5 + Write '1' to disable interrupt for event ENDEPIN[5] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPIN6 + Write '1' to disable interrupt for event ENDEPIN[6] + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPIN7 + Write '1' to disable interrupt for event ENDEPIN[7] + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + EP0DATADONE + Write '1' to disable interrupt for event EP0DATADONE + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDISOIN + Write '1' to disable interrupt for event ENDISOIN + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPOUT0 + Write '1' to disable interrupt for event ENDEPOUT[0] + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPOUT1 + Write '1' to disable interrupt for event ENDEPOUT[1] + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPOUT2 + Write '1' to disable interrupt for event ENDEPOUT[2] + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPOUT3 + Write '1' to disable interrupt for event ENDEPOUT[3] + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPOUT4 + Write '1' to disable interrupt for event ENDEPOUT[4] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPOUT5 + Write '1' to disable interrupt for event ENDEPOUT[5] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPOUT6 + Write '1' to disable interrupt for event ENDEPOUT[6] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPOUT7 + Write '1' to disable interrupt for event ENDEPOUT[7] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDISOOUT + Write '1' to disable interrupt for event ENDISOOUT + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SOF + Write '1' to disable interrupt for event SOF + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + USBEVENT + Write '1' to disable interrupt for event USBEVENT + 22 + 22 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + EP0SETUP + Write '1' to disable interrupt for event EP0SETUP + 23 + 23 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + EPDATA + Write '1' to disable interrupt for event EPDATA + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + EVENTCAUSE + Details on what caused the USBEVENT event + 0x400 + read-write + oneToClear + + + ISOOUTCRC + CRC error was detected on isochronous OUT endpoint 8. Write '1' to clear. + 0 + 0 + + + NotDetected + No error detected + 0 + + + Detected + Error detected + 1 + + + + + SUSPEND + Signals that USB lines have been idle long enough for the device to enter suspend. Write '1' to clear. + 8 + 8 + + + NotDetected + Suspend not detected + 0 + + + Detected + Suspend detected + 1 + + + + + RESUME + Signals that a RESUME condition (K state or activity restart) has been detected on USB lines. Write '1' to clear. + 9 + 9 + + + NotDetected + Resume not detected + 0 + + + Detected + Resume detected + 1 + + + + + USBWUALLOWED + USB MAC has been woken up and operational. Write '1' to clear. + 10 + 10 + + + NotAllowed + Wake up not allowed + 0 + + + Allowed + Wake up allowed + 1 + + + + + READY + USB device is ready for normal operation. Write '1' to clear. + 11 + 11 + + + NotDetected + USBEVENT was not issued due to USBD peripheral ready + 0 + + + Ready + USBD peripheral is ready + 1 + + + + + + + HALTED + Unspecified + USBD_HALTED + read-write + 0x420 + + 0x8 + 0x4 + EPIN[%s] + Description collection: IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. + 0x000 + read-only + + + GETSTATUS + IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. + 0 + 15 + + + NotHalted + Endpoint is not halted + 0 + + + Halted + Endpoint is halted + 1 + + + + + + + 0x8 + 0x4 + EPOUT[%s] + Description collection: OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. + 0x024 + read-only + + + GETSTATUS + OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. + 0 + 15 + + + NotHalted + Endpoint is not halted + 0 + + + Halted + Endpoint is halted + 1 + + + + + + + + EPSTATUS + Provides information on which endpoint's EasyDMA registers have been captured + 0x468 + read-write + oneToClear + + + EPIN0 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 0 + 0 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPIN1 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 1 + 1 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPIN2 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 2 + 2 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPIN3 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 3 + 3 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPIN4 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 4 + 4 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPIN5 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 5 + 5 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPIN6 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 6 + 6 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPIN7 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 7 + 7 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPIN8 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 8 + 8 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPOUT0 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 16 + 16 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPOUT1 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 17 + 17 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPOUT2 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 18 + 18 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPOUT3 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 19 + 19 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPOUT4 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 20 + 20 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPOUT5 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 21 + 21 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPOUT6 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 22 + 22 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPOUT7 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 23 + 23 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPOUT8 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 24 + 24 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + + + EPDATASTATUS + Provides information on which endpoint(s) an acknowledged data transfer has occurred (EPDATA event) + 0x46C + read-write + oneToClear + + + EPIN1 + Acknowledged data transfer on this IN endpoint. Write '1' to clear. + 1 + 1 + + + NotDone + No acknowledged data transfer on this endpoint + 0 + + + DataDone + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPIN2 + Acknowledged data transfer on this IN endpoint. Write '1' to clear. + 2 + 2 + + + NotDone + No acknowledged data transfer on this endpoint + 0 + + + DataDone + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPIN3 + Acknowledged data transfer on this IN endpoint. Write '1' to clear. + 3 + 3 + + + NotDone + No acknowledged data transfer on this endpoint + 0 + + + DataDone + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPIN4 + Acknowledged data transfer on this IN endpoint. Write '1' to clear. + 4 + 4 + + + NotDone + No acknowledged data transfer on this endpoint + 0 + + + DataDone + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPIN5 + Acknowledged data transfer on this IN endpoint. Write '1' to clear. + 5 + 5 + + + NotDone + No acknowledged data transfer on this endpoint + 0 + + + DataDone + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPIN6 + Acknowledged data transfer on this IN endpoint. Write '1' to clear. + 6 + 6 + + + NotDone + No acknowledged data transfer on this endpoint + 0 + + + DataDone + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPIN7 + Acknowledged data transfer on this IN endpoint. Write '1' to clear. + 7 + 7 + + + NotDone + No acknowledged data transfer on this endpoint + 0 + + + DataDone + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPOUT1 + Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + 17 + 17 + + + NotStarted + No acknowledged data transfer on this endpoint + 0 + + + Started + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPOUT2 + Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + 18 + 18 + + + NotStarted + No acknowledged data transfer on this endpoint + 0 + + + Started + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPOUT3 + Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + 19 + 19 + + + NotStarted + No acknowledged data transfer on this endpoint + 0 + + + Started + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPOUT4 + Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + 20 + 20 + + + NotStarted + No acknowledged data transfer on this endpoint + 0 + + + Started + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPOUT5 + Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + 21 + 21 + + + NotStarted + No acknowledged data transfer on this endpoint + 0 + + + Started + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPOUT6 + Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + 22 + 22 + + + NotStarted + No acknowledged data transfer on this endpoint + 0 + + + Started + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPOUT7 + Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + 23 + 23 + + + NotStarted + No acknowledged data transfer on this endpoint + 0 + + + Started + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + + + USBADDR + Device USB address + 0x470 + read-only + + + ADDR + Device USB address + 0 + 6 + + + + + BMREQUESTTYPE + SETUP data, byte 0, bmRequestType + 0x480 + read-only + 0x00000000 + + + RECIPIENT + Data transfer type + 0 + 4 + + + Device + Device + 0 + + + Interface + Interface + 1 + + + Endpoint + Endpoint + 2 + + + Other + Other + 3 + + + + + TYPE + Data transfer type + 5 + 6 + + + Standard + Standard + 0 + + + Class + Class + 1 + + + Vendor + Vendor + 2 + + + + + DIRECTION + Data transfer direction + 7 + 7 + + + HostToDevice + Host-to-device + 0 + + + DeviceToHost + Device-to-host + 1 + + + + + + + BREQUEST + SETUP data, byte 1, bRequest + 0x484 + read-only + 0x00000000 + + + BREQUEST + SETUP data, byte 1, bRequest. Values provided for standard requests only, user must implement class and vendor values. + 0 + 7 + + + STD_GET_STATUS + Standard request GET_STATUS + 0 + + + STD_CLEAR_FEATURE + Standard request CLEAR_FEATURE + 1 + + + STD_SET_FEATURE + Standard request SET_FEATURE + 3 + + + STD_SET_ADDRESS + Standard request SET_ADDRESS + 5 + + + STD_GET_DESCRIPTOR + Standard request GET_DESCRIPTOR + 6 + + + STD_SET_DESCRIPTOR + Standard request SET_DESCRIPTOR + 7 + + + STD_GET_CONFIGURATION + Standard request GET_CONFIGURATION + 8 + + + STD_SET_CONFIGURATION + Standard request SET_CONFIGURATION + 9 + + + STD_GET_INTERFACE + Standard request GET_INTERFACE + 10 + + + STD_SET_INTERFACE + Standard request SET_INTERFACE + 11 + + + STD_SYNCH_FRAME + Standard request SYNCH_FRAME + 12 + + + + + + + WVALUEL + SETUP data, byte 2, LSB of wValue + 0x488 + read-only + 0x00000000 + + + WVALUEL + SETUP data, byte 2, LSB of wValue + 0 + 7 + + + + + WVALUEH + SETUP data, byte 3, MSB of wValue + 0x48C + read-only + 0x00000000 + + + WVALUEH + SETUP data, byte 3, MSB of wValue + 0 + 7 + + + + + WINDEXL + SETUP data, byte 4, LSB of wIndex + 0x490 + read-only + 0x00000000 + + + WINDEXL + SETUP data, byte 4, LSB of wIndex + 0 + 7 + + + + + WINDEXH + SETUP data, byte 5, MSB of wIndex + 0x494 + read-only + 0x00000000 + + + WINDEXH + SETUP data, byte 5, MSB of wIndex + 0 + 7 + + + + + WLENGTHL + SETUP data, byte 6, LSB of wLength + 0x498 + read-only + 0x00000000 + + + WLENGTHL + SETUP data, byte 6, LSB of wLength + 0 + 7 + + + + + WLENGTHH + SETUP data, byte 7, MSB of wLength + 0x49C + read-only + 0x00000000 + + + WLENGTHH + SETUP data, byte 7, MSB of wLength + 0 + 7 + + + + + SIZE + Unspecified + USBD_SIZE + read-write + 0x4A0 + + 0x8 + 0x4 + EPOUT[%s] + Description collection: Number of bytes received last in the data stage of this OUT endpoint + 0x000 + read-write + zeroToClear + + + SIZE + Number of bytes received last in the data stage of this OUT endpoint + 0 + 6 + + + + + ISOOUT + Number of bytes received last on this ISO OUT data endpoint + 0x020 + read-only + 0x00010000 + + + SIZE + Number of bytes received last on this ISO OUT data endpoint + 0 + 9 + + + ZERO + Zero-length data packet received + 16 + 16 + + + Normal + No zero-length data received, use value in SIZE + 0 + + + ZeroData + Zero-length data received, ignore value in SIZE + 1 + + + + + + + + ENABLE + Enable USB + 0x500 + read-write + + + ENABLE + Enable USB + 0 + 0 + + + Disabled + USB peripheral is disabled + 0 + + + Enabled + USB peripheral is enabled + 1 + + + + + + + USBPULLUP + Control of the USB pull-up + 0x504 + read-write + + + CONNECT + Control of the USB pull-up on the D+ line + 0 + 0 + + + Disabled + Pull-up is disconnected + 0 + + + Enabled + Pull-up is connected to D+ + 1 + + + + + + + DPDMVALUE + State D+ and D- lines will be forced into by the DPDMDRIVE task. The DPDMNODRIVE task reverts the control of the lines to MAC IP (no forcing). + 0x508 + read-write + + + STATE + State D+ and D- lines will be forced into by the DPDMDRIVE task + 0 + 4 + + + Resume + D+ forced low, D- forced high (K state) for a timing preset in hardware (50 us or 5 ms, depending on bus state) + 1 + + + J + D+ forced high, D- forced low (J state) + 2 + + + K + D+ forced low, D- forced high (K state) + 4 + + + + + + + DTOGGLE + Data toggle control and status + 0x50C + read-write + 0x00000100 + + + EP + Select bulk endpoint number + 0 + 2 + + + IO + Selects IN or OUT endpoint + 7 + 7 + + + Out + Selects OUT endpoint + 0 + + + In + Selects IN endpoint + 1 + + + + + VALUE + Data toggle value + 8 + 9 + + + Nop + No action on data toggle when writing the register with this value + 0 + + + Data0 + Data toggle is DATA0 on endpoint set by EP and IO + 1 + + + Data1 + Data toggle is DATA1 on endpoint set by EP and IO + 2 + + + + + + + EPINEN + Endpoint IN enable + 0x510 + read-write + 0x00000001 + + + IN0 + Enable IN endpoint 0 + 0 + 0 + + + Disable + Disable endpoint IN 0 (no response to IN tokens) + 0 + + + Enable + Enable endpoint IN 0 (response to IN tokens) + 1 + + + + + IN1 + Enable IN endpoint 1 + 1 + 1 + + + Disable + Disable endpoint IN 1 (no response to IN tokens) + 0 + + + Enable + Enable endpoint IN 1 (response to IN tokens) + 1 + + + + + IN2 + Enable IN endpoint 2 + 2 + 2 + + + Disable + Disable endpoint IN 2 (no response to IN tokens) + 0 + + + Enable + Enable endpoint IN 2 (response to IN tokens) + 1 + + + + + IN3 + Enable IN endpoint 3 + 3 + 3 + + + Disable + Disable endpoint IN 3 (no response to IN tokens) + 0 + + + Enable + Enable endpoint IN 3 (response to IN tokens) + 1 + + + + + IN4 + Enable IN endpoint 4 + 4 + 4 + + + Disable + Disable endpoint IN 4 (no response to IN tokens) + 0 + + + Enable + Enable endpoint IN 4 (response to IN tokens) + 1 + + + + + IN5 + Enable IN endpoint 5 + 5 + 5 + + + Disable + Disable endpoint IN 5 (no response to IN tokens) + 0 + + + Enable + Enable endpoint IN 5 (response to IN tokens) + 1 + + + + + IN6 + Enable IN endpoint 6 + 6 + 6 + + + Disable + Disable endpoint IN 6 (no response to IN tokens) + 0 + + + Enable + Enable endpoint IN 6 (response to IN tokens) + 1 + + + + + IN7 + Enable IN endpoint 7 + 7 + 7 + + + Disable + Disable endpoint IN 7 (no response to IN tokens) + 0 + + + Enable + Enable endpoint IN 7 (response to IN tokens) + 1 + + + + + ISOIN + Enable ISO IN endpoint + 8 + 8 + + + Disable + Disable ISO IN endpoint 8 + 0 + + + Enable + Enable ISO IN endpoint 8 + 1 + + + + + + + EPOUTEN + Endpoint OUT enable + 0x514 + read-write + 0x00000001 + + + OUT0 + Enable OUT endpoint 0 + 0 + 0 + + + Disable + Disable endpoint OUT 0 (no response to OUT tokens) + 0 + + + Enable + Enable endpoint OUT 0 (response to OUT tokens) + 1 + + + + + OUT1 + Enable OUT endpoint 1 + 1 + 1 + + + Disable + Disable endpoint OUT 1 (no response to OUT tokens) + 0 + + + Enable + Enable endpoint OUT 1 (response to OUT tokens) + 1 + + + + + OUT2 + Enable OUT endpoint 2 + 2 + 2 + + + Disable + Disable endpoint OUT 2 (no response to OUT tokens) + 0 + + + Enable + Enable endpoint OUT 2 (response to OUT tokens) + 1 + + + + + OUT3 + Enable OUT endpoint 3 + 3 + 3 + + + Disable + Disable endpoint OUT 3 (no response to OUT tokens) + 0 + + + Enable + Enable endpoint OUT 3 (response to OUT tokens) + 1 + + + + + OUT4 + Enable OUT endpoint 4 + 4 + 4 + + + Disable + Disable endpoint OUT 4 (no response to OUT tokens) + 0 + + + Enable + Enable endpoint OUT 4 (response to OUT tokens) + 1 + + + + + OUT5 + Enable OUT endpoint 5 + 5 + 5 + + + Disable + Disable endpoint OUT 5 (no response to OUT tokens) + 0 + + + Enable + Enable endpoint OUT 5 (response to OUT tokens) + 1 + + + + + OUT6 + Enable OUT endpoint 6 + 6 + 6 + + + Disable + Disable endpoint OUT 6 (no response to OUT tokens) + 0 + + + Enable + Enable endpoint OUT 6 (response to OUT tokens) + 1 + + + + + OUT7 + Enable OUT endpoint 7 + 7 + 7 + + + Disable + Disable endpoint OUT 7 (no response to OUT tokens) + 0 + + + Enable + Enable endpoint OUT 7 (response to OUT tokens) + 1 + + + + + ISOOUT + Enable ISO OUT endpoint 8 + 8 + 8 + + + Disable + Disable ISO OUT endpoint 8 + 0 + + + Enable + Enable ISO OUT endpoint 8 + 1 + + + + + + + EPSTALL + STALL endpoints + 0x518 + write-only + 0x00000000 + modifyExternal + + + EP + Select endpoint number + 0 + 2 + + + IO + Selects IN or OUT endpoint + 7 + 7 + + + Out + Selects OUT endpoint + 0 + + + In + Selects IN endpoint + 1 + + + + + STALL + Stall selected endpoint + 8 + 8 + + + UnStall + Don't stall selected endpoint + 0 + + + Stall + Stall selected endpoint + 1 + + + + + + + ISOSPLIT + Controls the split of ISO buffers + 0x51C + read-write + + + SPLIT + Controls the split of ISO buffers + 0 + 15 + + + OneDir + Full buffer dedicated to either ISO IN or OUT + 0x0000 + + + HalfIN + Lower half for IN, upper half for OUT + 0x0080 + + + + + + + FRAMECNTR + Returns the current value of the start of frame counter + 0x520 + read-only + + + FRAMECNTR + Returns the current value of the start of frame counter + 0 + 10 + + + + + LOWPOWER + Controls USBD peripheral low power mode during USB suspend + 0x52C + read-write + 0x00000000 + + + LOWPOWER + Controls USBD peripheral low-power mode during USB suspend + 0 + 0 + + + ForceNormal + Software must write this value to exit low power mode and before performing a remote wake-up + 0 + + + LowPower + Software must write this value to enter low power mode after DMA and software have finished interacting with the USB peripheral + 1 + + + + + + + ISOINCONFIG + Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent + 0x530 + read-write + + + RESPONSE + Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent + 0 + 0 + + + NoResp + Endpoint does not respond in that case + 0 + + + ZeroData + Endpoint responds with a zero-length data packet in that case + 1 + + + + + + + 8 + 0x014 + EPIN[%s] + Unspecified + USBD_EPIN + read-write + 0x600 + + PTR + Description cluster: Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Description cluster: Maximum number of bytes to transfer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes to transfer + 0 + 6 + + + + + AMOUNT + Description cluster: Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 6 + + + + + + ISOIN + Unspecified + USBD_ISOIN + read-write + 0x6A0 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes to transfer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes to transfer + 0 + 9 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 9 + + + + + + 8 + 0x014 + EPOUT[%s] + Unspecified + USBD_EPOUT + read-write + 0x700 + + PTR + Description cluster: Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Description cluster: Maximum number of bytes to transfer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes to transfer + 0 + 6 + + + + + AMOUNT + Description cluster: Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 6 + + + + + + ISOOUT + Unspecified + USBD_ISOOUT + read-write + 0x7A0 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes to transfer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes to transfer + 0 + 9 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 9 + + + + + + + + USBD_S + Universal serial bus device 1 + 0x50036000 + + + + USBD + 54 + + + + USBREGULATOR_NS + USB Regulator 0 + 0x40037000 + USBREG + + + + 0 + 0x1000 + registers + + + USBREGULATOR + 55 + + USBREG + 0x20 + + + EVENTS_USBDETECTED + Voltage supply detected on VBUS + 0x100 + read-write + + + EVENTS_USBDETECTED + Voltage supply detected on VBUS + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_USBREMOVED + Voltage supply removed from VBUS + 0x104 + read-write + + + EVENTS_USBREMOVED + Voltage supply removed from VBUS + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_USBPWRRDY + USB 3.3 V supply ready + 0x108 + read-write + + + EVENTS_USBPWRRDY + USB 3.3 V supply ready + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_USBDETECTED + Publish configuration for event USBDETECTED + 0x180 + read-write + + + CHIDX + DPPI channel that event USBDETECTED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_USBREMOVED + Publish configuration for event USBREMOVED + 0x184 + read-write + + + CHIDX + DPPI channel that event USBREMOVED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_USBPWRRDY + Publish configuration for event USBPWRRDY + 0x188 + read-write + + + CHIDX + DPPI channel that event USBPWRRDY will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + USBDETECTED + Enable or disable interrupt for event USBDETECTED + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + USBREMOVED + Enable or disable interrupt for event USBREMOVED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + USBPWRRDY + Enable or disable interrupt for event USBPWRRDY + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + USBDETECTED + Write '1' to enable interrupt for event USBDETECTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + USBREMOVED + Write '1' to enable interrupt for event USBREMOVED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + USBPWRRDY + Write '1' to enable interrupt for event USBPWRRDY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + USBDETECTED + Write '1' to disable interrupt for event USBDETECTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + USBREMOVED + Write '1' to disable interrupt for event USBREMOVED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + USBPWRRDY + Write '1' to disable interrupt for event USBPWRRDY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + USBREGSTATUS + USB supply status + 0x400 + read-only + 0x00000000 + + + VBUSDETECT + VBUS input detection status (USBDETECTED and USBREMOVED events are derived from this information) + 0 + 0 + + + NoVbus + VBUS voltage below valid threshold + 0 + + + VbusPresent + VBUS voltage above valid threshold + 1 + + + + + OUTPUTRDY + USB supply output settling time elapsed + 1 + 1 + + + NotReady + USBREG output settling time not elapsed + 0 + + + Ready + USBREG output settling time elapsed (same information as USBPWRRDY event) + 1 + + + + + + + + + USBREGULATOR_S + USB Regulator 1 + 0x50037000 + + + + USBREGULATOR + 55 + + + + KMU_NS + Key management unit 0 + 0x40039000 + KMU + + + + 0 + 0x1000 + registers + + + KMU + 57 + + KMU + 0x20 + + + TASKS_PUSH_KEYSLOT + Push a key slot over secure APB + 0x0000 + write-only + + + TASKS_PUSH_KEYSLOT + Push a key slot over secure APB + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_KEYSLOT_PUSHED + Key slot successfully pushed over secure APB + 0x100 + read-write + + + EVENTS_KEYSLOT_PUSHED + Key slot successfully pushed over secure APB + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_KEYSLOT_REVOKED + Key slot has been revoked and cannot be tasked for selection + 0x104 + read-write + + + EVENTS_KEYSLOT_REVOKED + Key slot has been revoked and cannot be tasked for selection + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_KEYSLOT_ERROR + No key slot selected, no destination address defined, or error during push operation + 0x108 + read-write + + + EVENTS_KEYSLOT_ERROR + No key slot selected, no destination address defined, or error during push operation + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + KEYSLOT_PUSHED + Enable or disable interrupt for event KEYSLOT_PUSHED + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + KEYSLOT_REVOKED + Enable or disable interrupt for event KEYSLOT_REVOKED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + KEYSLOT_ERROR + Enable or disable interrupt for event KEYSLOT_ERROR + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + KEYSLOT_PUSHED + Write '1' to enable interrupt for event KEYSLOT_PUSHED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + KEYSLOT_REVOKED + Write '1' to enable interrupt for event KEYSLOT_REVOKED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + KEYSLOT_ERROR + Write '1' to enable interrupt for event KEYSLOT_ERROR + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + KEYSLOT_PUSHED + Write '1' to disable interrupt for event KEYSLOT_PUSHED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + KEYSLOT_REVOKED + Write '1' to disable interrupt for event KEYSLOT_REVOKED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + KEYSLOT_ERROR + Write '1' to disable interrupt for event KEYSLOT_ERROR + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + + + KEYSLOT_PUSHED + Read pending status of interrupt for event KEYSLOT_PUSHED + 0 + 0 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + KEYSLOT_REVOKED + Read pending status of interrupt for event KEYSLOT_REVOKED + 1 + 1 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + KEYSLOT_ERROR + Read pending status of interrupt for event KEYSLOT_ERROR + 2 + 2 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + + + STATUS + Status bits for KMU operation + 0x40C + read-only + 0x00000000 + + + SELECTED + Key slot ID successfully selected by the KMU + 0 + 0 + + + Disabled + No key slot ID selected by KMU + 0 + + + Enabled + Key slot ID successfully selected by KMU + 1 + + + + + BLOCKED + Violation status + 1 + 1 + + + Disabled + No access violation detected + 0 + + + Enabled + Access violation detected and blocked + 1 + + + + + + + SELECTKEYSLOT + Select key slot to be read over AHB or pushed over secure APB when TASKS_PUSH_KEYSLOT is started + 0x500 + read-write + 0x00000000 + + + ID + Select key slot ID to be read over AHB, or pushed over secure APB, when TASKS_PUSH_KEYSLOT is started. NOTE: ID=0 is not a valid key slot ID. The 0 ID should be used when the KMU is idle or not in use. NOTE: Index N in UICR-&gt;KEYSLOT.KEY[N] and UICR-&gt;KEYSLOT.CONFIG[N] corresponds to KMU key slot ID=N+1. + 0 + 7 + + + + + + + NVMC_NS + Non-volatile memory controller 0 + 0x40039000 + KMU_NS + NVMC + + + + 0 + 0x1000 + registers + + NVMC + 0x20 + + + READY + Ready flag + 0x400 + read-only + 0x00000001 + + + READY + NVMC is ready or busy + 0 + 0 + + + Busy + NVMC is busy (ongoing write or erase operation) + 0 + + + Ready + NVMC is ready + 1 + + + + + + + READYNEXT + Ready flag + 0x408 + read-only + 0x00000001 + + + READYNEXT + NVMC can accept a new write operation + 0 + 0 + + + Busy + NVMC cannot accept any write operation + 0 + + + Ready + NVMC is ready + 1 + + + + + + + CONFIG + Configuration register + 0x504 + read-write + + + + WEN + Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. + 0 + 2 + + + Ren + Read only access + 0 + + + Wen + Write enabled + 1 + + + Een + Erase enabled + 2 + + + PEen + Partial erase enabled + 4 + + + + + + + ERASEALL + Register for erasing all non-volatile user memory + 0x50C + write-only + + + + ERASEALL + Erase all non-volatile memory including UICR registers. Before the non-volatile memory can be erased, erasing must be enabled by setting CONFIG.WEN=Een. + 0 + 0 + + + NoOperation + No operation + 0 + + + Erase + Start chip erase + 1 + + + + + + + ERASEPAGEPARTIALCFG + Register for partial erase configuration + 0x51C + read-write + 0x0000000A + + + + DURATION + Duration of the partial erase in milliseconds + 0 + 6 + + + + + CONFIGNS + Non-secure configuration register + 0x584 + read-write + + + WEN + Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. + 0 + 1 + + + Ren + Read only access + 0 + + + Wen + Write enabled + 1 + + + Een + Erase enabled + 2 + + + + + + + WRITEUICRNS + Non-secure APPROTECT enable register + 0x588 + write-only + + + SET + Allow non-secure code to set APPROTECT + 0 + 0 + + + Set + Set value + 1 + + + + + KEY + Key to write in order to validate the write operation + 4 + 31 + + + Keyvalid + Key value + 0xAFBE5A7 + + + + + + + + + KMU_S + Key management unit 1 + 0x50039000 + + + + KMU + 57 + + + + NVMC_S + Non-volatile memory controller 1 + 0x50039000 + KMU_S + + + + + P0_NS + GPIO Port 0 + 0x40842500 + GPIO + + + + 0 + 0x300 + registers + + GPIO + 0x20 + + + OUT + Write GPIO port + 0x004 + read-write + + + PIN0 + Pin 0 + 0 + 0 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + + + OUTSET + Set individual bits in GPIO port + 0x008 + read-write + oneToSet + + + PIN0 + Pin 0 + 0 + 0 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + + + OUTCLR + Clear individual bits in GPIO port + 0x00C + read-write + oneToClear + + + PIN0 + Pin 0 + 0 + 0 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + + + IN + Read GPIO port + 0x010 + read-only + + + PIN0 + Pin 0 + 0 + 0 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + + + DIR + Direction of GPIO pins + 0x014 + read-write + + + PIN0 + Pin 0 + 0 + 0 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + + + DIRSET + DIR set register + 0x018 + read-write + oneToSet + + + PIN0 + Set as output pin 0 + 0 + 0 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN1 + Set as output pin 1 + 1 + 1 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN2 + Set as output pin 2 + 2 + 2 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN3 + Set as output pin 3 + 3 + 3 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN4 + Set as output pin 4 + 4 + 4 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN5 + Set as output pin 5 + 5 + 5 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN6 + Set as output pin 6 + 6 + 6 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN7 + Set as output pin 7 + 7 + 7 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN8 + Set as output pin 8 + 8 + 8 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN9 + Set as output pin 9 + 9 + 9 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN10 + Set as output pin 10 + 10 + 10 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN11 + Set as output pin 11 + 11 + 11 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN12 + Set as output pin 12 + 12 + 12 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN13 + Set as output pin 13 + 13 + 13 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN14 + Set as output pin 14 + 14 + 14 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN15 + Set as output pin 15 + 15 + 15 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN16 + Set as output pin 16 + 16 + 16 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN17 + Set as output pin 17 + 17 + 17 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN18 + Set as output pin 18 + 18 + 18 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN19 + Set as output pin 19 + 19 + 19 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN20 + Set as output pin 20 + 20 + 20 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN21 + Set as output pin 21 + 21 + 21 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN22 + Set as output pin 22 + 22 + 22 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN23 + Set as output pin 23 + 23 + 23 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN24 + Set as output pin 24 + 24 + 24 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN25 + Set as output pin 25 + 25 + 25 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN26 + Set as output pin 26 + 26 + 26 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN27 + Set as output pin 27 + 27 + 27 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN28 + Set as output pin 28 + 28 + 28 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN29 + Set as output pin 29 + 29 + 29 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN30 + Set as output pin 30 + 30 + 30 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN31 + Set as output pin 31 + 31 + 31 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + + + DIRCLR + DIR clear register + 0x01C + read-write + oneToClear + + + PIN0 + Set as input pin 0 + 0 + 0 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN1 + Set as input pin 1 + 1 + 1 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN2 + Set as input pin 2 + 2 + 2 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN3 + Set as input pin 3 + 3 + 3 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN4 + Set as input pin 4 + 4 + 4 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN5 + Set as input pin 5 + 5 + 5 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN6 + Set as input pin 6 + 6 + 6 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN7 + Set as input pin 7 + 7 + 7 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN8 + Set as input pin 8 + 8 + 8 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN9 + Set as input pin 9 + 9 + 9 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN10 + Set as input pin 10 + 10 + 10 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN11 + Set as input pin 11 + 11 + 11 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN12 + Set as input pin 12 + 12 + 12 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN13 + Set as input pin 13 + 13 + 13 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN14 + Set as input pin 14 + 14 + 14 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN15 + Set as input pin 15 + 15 + 15 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN16 + Set as input pin 16 + 16 + 16 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN17 + Set as input pin 17 + 17 + 17 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN18 + Set as input pin 18 + 18 + 18 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN19 + Set as input pin 19 + 19 + 19 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN20 + Set as input pin 20 + 20 + 20 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN21 + Set as input pin 21 + 21 + 21 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN22 + Set as input pin 22 + 22 + 22 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN23 + Set as input pin 23 + 23 + 23 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN24 + Set as input pin 24 + 24 + 24 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN25 + Set as input pin 25 + 25 + 25 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN26 + Set as input pin 26 + 26 + 26 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN27 + Set as input pin 27 + 27 + 27 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN28 + Set as input pin 28 + 28 + 28 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN29 + Set as input pin 29 + 29 + 29 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN30 + Set as input pin 30 + 30 + 30 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN31 + Set as input pin 31 + 31 + 31 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + + + LATCH + Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers + 0x020 + read-write + + + PIN0 + Status on whether PIN[0] has met criteria set in PIN_CNF[0].SENSE register. Write '1' to clear. + 0 + 0 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN1 + Status on whether PIN[1] has met criteria set in PIN_CNF[1].SENSE register. Write '1' to clear. + 1 + 1 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN2 + Status on whether PIN[2] has met criteria set in PIN_CNF[2].SENSE register. Write '1' to clear. + 2 + 2 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN3 + Status on whether PIN[3] has met criteria set in PIN_CNF[3].SENSE register. Write '1' to clear. + 3 + 3 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN4 + Status on whether PIN[4] has met criteria set in PIN_CNF[4].SENSE register. Write '1' to clear. + 4 + 4 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN5 + Status on whether PIN[5] has met criteria set in PIN_CNF[5].SENSE register. Write '1' to clear. + 5 + 5 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN6 + Status on whether PIN[6] has met criteria set in PIN_CNF[6].SENSE register. Write '1' to clear. + 6 + 6 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN7 + Status on whether PIN[7] has met criteria set in PIN_CNF[7].SENSE register. Write '1' to clear. + 7 + 7 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN8 + Status on whether PIN[8] has met criteria set in PIN_CNF[8].SENSE register. Write '1' to clear. + 8 + 8 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN9 + Status on whether PIN[9] has met criteria set in PIN_CNF[9].SENSE register. Write '1' to clear. + 9 + 9 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN10 + Status on whether PIN[10] has met criteria set in PIN_CNF[10].SENSE register. Write '1' to clear. + 10 + 10 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN11 + Status on whether PIN[11] has met criteria set in PIN_CNF[11].SENSE register. Write '1' to clear. + 11 + 11 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN12 + Status on whether PIN[12] has met criteria set in PIN_CNF[12].SENSE register. Write '1' to clear. + 12 + 12 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN13 + Status on whether PIN[13] has met criteria set in PIN_CNF[13].SENSE register. Write '1' to clear. + 13 + 13 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN14 + Status on whether PIN[14] has met criteria set in PIN_CNF[14].SENSE register. Write '1' to clear. + 14 + 14 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN15 + Status on whether PIN[15] has met criteria set in PIN_CNF[15].SENSE register. Write '1' to clear. + 15 + 15 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN16 + Status on whether PIN[16] has met criteria set in PIN_CNF[16].SENSE register. Write '1' to clear. + 16 + 16 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN17 + Status on whether PIN[17] has met criteria set in PIN_CNF[17].SENSE register. Write '1' to clear. + 17 + 17 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN18 + Status on whether PIN[18] has met criteria set in PIN_CNF[18].SENSE register. Write '1' to clear. + 18 + 18 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN19 + Status on whether PIN[19] has met criteria set in PIN_CNF[19].SENSE register. Write '1' to clear. + 19 + 19 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN20 + Status on whether PIN[20] has met criteria set in PIN_CNF[20].SENSE register. Write '1' to clear. + 20 + 20 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN21 + Status on whether PIN[21] has met criteria set in PIN_CNF[21].SENSE register. Write '1' to clear. + 21 + 21 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN22 + Status on whether PIN[22] has met criteria set in PIN_CNF[22].SENSE register. Write '1' to clear. + 22 + 22 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN23 + Status on whether PIN[23] has met criteria set in PIN_CNF[23].SENSE register. Write '1' to clear. + 23 + 23 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN24 + Status on whether PIN[24] has met criteria set in PIN_CNF[24].SENSE register. Write '1' to clear. + 24 + 24 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN25 + Status on whether PIN[25] has met criteria set in PIN_CNF[25].SENSE register. Write '1' to clear. + 25 + 25 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN26 + Status on whether PIN[26] has met criteria set in PIN_CNF[26].SENSE register. Write '1' to clear. + 26 + 26 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN27 + Status on whether PIN[27] has met criteria set in PIN_CNF[27].SENSE register. Write '1' to clear. + 27 + 27 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN28 + Status on whether PIN[28] has met criteria set in PIN_CNF[28].SENSE register. Write '1' to clear. + 28 + 28 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN29 + Status on whether PIN[29] has met criteria set in PIN_CNF[29].SENSE register. Write '1' to clear. + 29 + 29 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN30 + Status on whether PIN[30] has met criteria set in PIN_CNF[30].SENSE register. Write '1' to clear. + 30 + 30 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN31 + Status on whether PIN[31] has met criteria set in PIN_CNF[31].SENSE register. Write '1' to clear. + 31 + 31 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + + + DETECTMODE + Select between default DETECT signal behavior and LDETECT mode (For non-secure pin only) + 0x024 + read-write + + + DETECTMODE + Select between default DETECT signal behavior and LDETECT mode + 0 + 0 + + + Default + DETECT directly connected to PIN DETECT signals + 0 + + + LDETECT + Use the latched LDETECT behavior + 1 + + + + + + + DETECTMODE_SEC + Select between default DETECT signal behavior and LDETECT mode (For secure pin only) + 0x028 + read-write + + + DETECTMODE + Select between default DETECT signal behavior and LDETECT mode + 0 + 0 + + + Default + DETECT directly connected to PIN DETECT signals + 0 + + + LDETECT + Use the latched LDETECT behavior + 1 + + + + + + + 0x20 + 0x4 + PIN_CNF[%s] + Description collection: Configuration of GPIO pins + 0x200 + read-write + 0x00000002 + + + DIR + Pin direction. Same physical register as DIR register + 0 + 0 + + + Input + Configure pin as an input pin + 0 + + + Output + Configure pin as an output pin + 1 + + + + + INPUT + Connect or disconnect input buffer + 1 + 1 + + + Connect + Connect input buffer + 0 + + + Disconnect + Disconnect input buffer + 1 + + + + + PULL + Pull configuration + 2 + 3 + + + Disabled + No pull + 0 + + + Pulldown + Pull down on pin + 1 + + + Pullup + Pull up on pin + 3 + + + + + DRIVE + Drive configuration + 8 + 11 + + + S0S1 + Standard '0', standard '1' + 0 + + + H0S1 + High drive '0', standard '1' + 1 + + + S0H1 + Standard '0', high drive '1' + 2 + + + H0H1 + High drive '0', high 'drive '1'' + 3 + + + D0S1 + Disconnect '0', standard '1' (normally used for wired-or connections) + 4 + + + D0H1 + Disconnect '0', high drive '1' (normally used for wired-or connections) + 5 + + + S0D1 + Standard '0', disconnect '1' (normally used for wired-and connections) + 6 + + + H0D1 + High drive '0', disconnect '1' (normally used for wired-and connections) + 7 + + + E0E1 + Extra high drive '0', extra high drive '1' + 11 + + + + + SENSE + Pin sensing mechanism + 16 + 17 + + + Disabled + Disabled + 0 + + + High + Sense for high level + 2 + + + Low + Sense for low level + 3 + + + + + MCUSEL + Select which MCU/Subsystem controls this pin Note: this field is only accessible from secure code. + 28 + 30 + + + AppMCU + Application MCU + 0x0 + + + NetworkMCU + Network MCU + 0x1 + + + Peripheral + Peripheral with dedicated pins + 0x3 + + + TND + Trace and Debug Subsystem + 0x7 + + + + + + + + + P1_NS + GPIO Port 1 + 0x40842800 + + + + + P0_S + GPIO Port 2 + 0x50842500 + + + + + P1_S + GPIO Port 3 + 0x50842800 + + + + + CRYPTOCELL_S + ARM TrustZone CryptoCell register interface + 0x50844000 + CRYPTOCELL + + + + 0 + 0x1000 + registers + + + CRYPTOCELL + 68 + + CRYPTOCELL + 0x20 + + + ENABLE + Enable CRYPTOCELL subsystem. + 0x500 + read-write + 0x00000000 + + + ENABLE + Enable or disable the CRYPTOCELL subsystem. + 0 + 0 + + + Disabled + CRYPTOCELL subsystem disabled. + 0 + + + Enabled + CRYPTOCELL subsystem enabled. + 1 + + + + + + + + + VMC_NS + Volatile Memory controller 0 + 0x40081000 + VMC + + + + 0 + 0x1000 + registers + + VMC + 0x20 + + + 8 + 0x010 + RAM[%s] + Unspecified + VMC_RAM + read-write + 0x600 + + POWER + Description cluster: RAM[n] power control register + 0x000 + read-write + 0x0000FFFF + + + S0POWER + Keep RAM section S0 of RAM[n] on or off in System ON mode + 0 + 0 + + + Off + Off + 0 + + + On + On + 1 + + + + + S1POWER + Keep RAM section S1 of RAM[n] on or off in System ON mode + 1 + 1 + + + Off + Off + 0 + + + On + On + 1 + + + + + S2POWER + Keep RAM section S2 of RAM[n] on or off in System ON mode + 2 + 2 + + + Off + Off + 0 + + + On + On + 1 + + + + + S3POWER + Keep RAM section S3 of RAM[n] on or off in System ON mode + 3 + 3 + + + Off + Off + 0 + + + On + On + 1 + + + + + S4POWER + Keep RAM section S4 of RAM[n] on or off in System ON mode + 4 + 4 + + + Off + Off + 0 + + + On + On + 1 + + + + + S5POWER + Keep RAM section S5 of RAM[n] on or off in System ON mode + 5 + 5 + + + Off + Off + 0 + + + On + On + 1 + + + + + S6POWER + Keep RAM section S6 of RAM[n] on or off in System ON mode + 6 + 6 + + + Off + Off + 0 + + + On + On + 1 + + + + + S7POWER + Keep RAM section S7 of RAM[n] on or off in System ON mode + 7 + 7 + + + Off + Off + 0 + + + On + On + 1 + + + + + S8POWER + Keep RAM section S8 of RAM[n] on or off in System ON mode + 8 + 8 + + + Off + Off + 0 + + + On + On + 1 + + + + + S9POWER + Keep RAM section S9 of RAM[n] on or off in System ON mode + 9 + 9 + + + Off + Off + 0 + + + On + On + 1 + + + + + S10POWER + Keep RAM section S10 of RAM[n] on or off in System ON mode + 10 + 10 + + + Off + Off + 0 + + + On + On + 1 + + + + + S11POWER + Keep RAM section S11 of RAM[n] on or off in System ON mode + 11 + 11 + + + Off + Off + 0 + + + On + On + 1 + + + + + S12POWER + Keep RAM section S12 of RAM[n] on or off in System ON mode + 12 + 12 + + + Off + Off + 0 + + + On + On + 1 + + + + + S13POWER + Keep RAM section S13 of RAM[n] on or off in System ON mode + 13 + 13 + + + Off + Off + 0 + + + On + On + 1 + + + + + S14POWER + Keep RAM section S14 of RAM[n] on or off in System ON mode + 14 + 14 + + + Off + Off + 0 + + + On + On + 1 + + + + + S15POWER + Keep RAM section S15 of RAM[n] on or off in System ON mode + 15 + 15 + + + Off + Off + 0 + + + On + On + 1 + + + + + S0RETENTION + Keep retention on RAM section S0 of RAM[n] when RAM section is switched off + 16 + 16 + + + Off + Off + 0 + + + On + On + 1 + + + + + S1RETENTION + Keep retention on RAM section S1 of RAM[n] when RAM section is switched off + 17 + 17 + + + Off + Off + 0 + + + On + On + 1 + + + + + S2RETENTION + Keep retention on RAM section S2 of RAM[n] when RAM section is switched off + 18 + 18 + + + Off + Off + 0 + + + On + On + 1 + + + + + S3RETENTION + Keep retention on RAM section S3 of RAM[n] when RAM section is switched off + 19 + 19 + + + Off + Off + 0 + + + On + On + 1 + + + + + S4RETENTION + Keep retention on RAM section S4 of RAM[n] when RAM section is switched off + 20 + 20 + + + Off + Off + 0 + + + On + On + 1 + + + + + S5RETENTION + Keep retention on RAM section S5 of RAM[n] when RAM section is switched off + 21 + 21 + + + Off + Off + 0 + + + On + On + 1 + + + + + S6RETENTION + Keep retention on RAM section S6 of RAM[n] when RAM section is switched off + 22 + 22 + + + Off + Off + 0 + + + On + On + 1 + + + + + S7RETENTION + Keep retention on RAM section S7 of RAM[n] when RAM section is switched off + 23 + 23 + + + Off + Off + 0 + + + On + On + 1 + + + + + S8RETENTION + Keep retention on RAM section S8 of RAM[n] when RAM section is switched off + 24 + 24 + + + Off + Off + 0 + + + On + On + 1 + + + + + S9RETENTION + Keep retention on RAM section S9 of RAM[n] when RAM section is switched off + 25 + 25 + + + Off + Off + 0 + + + On + On + 1 + + + + + S10RETENTION + Keep retention on RAM section S10 of RAM[n] when RAM section is switched off + 26 + 26 + + + Off + Off + 0 + + + On + On + 1 + + + + + S11RETENTION + Keep retention on RAM section S11 of RAM[n] when RAM section is switched off + 27 + 27 + + + Off + Off + 0 + + + On + On + 1 + + + + + S12RETENTION + Keep retention on RAM section S12 of RAM[n] when RAM section is switched off + 28 + 28 + + + Off + Off + 0 + + + On + On + 1 + + + + + S13RETENTION + Keep retention on RAM section S13 of RAM[n] when RAM section is switched off + 29 + 29 + + + Off + Off + 0 + + + On + On + 1 + + + + + S14RETENTION + Keep retention on RAM section S14 of RAM[n] when RAM section is switched off + 30 + 30 + + + Off + Off + 0 + + + On + On + 1 + + + + + S15RETENTION + Keep retention on RAM section S15 of RAM[n] when RAM section is switched off + 31 + 31 + + + Off + Off + 0 + + + On + On + 1 + + + + + + + POWERSET + Description cluster: RAM[n] power control set register + 0x004 + read-write + 0x0000FFFF + + + S0POWER + Keep RAM section S0 of RAM[n] on or off in System ON mode + 0 + 0 + + + On + On + 1 + + + + + S1POWER + Keep RAM section S1 of RAM[n] on or off in System ON mode + 1 + 1 + + + On + On + 1 + + + + + S2POWER + Keep RAM section S2 of RAM[n] on or off in System ON mode + 2 + 2 + + + On + On + 1 + + + + + S3POWER + Keep RAM section S3 of RAM[n] on or off in System ON mode + 3 + 3 + + + On + On + 1 + + + + + S4POWER + Keep RAM section S4 of RAM[n] on or off in System ON mode + 4 + 4 + + + On + On + 1 + + + + + S5POWER + Keep RAM section S5 of RAM[n] on or off in System ON mode + 5 + 5 + + + On + On + 1 + + + + + S6POWER + Keep RAM section S6 of RAM[n] on or off in System ON mode + 6 + 6 + + + On + On + 1 + + + + + S7POWER + Keep RAM section S7 of RAM[n] on or off in System ON mode + 7 + 7 + + + On + On + 1 + + + + + S8POWER + Keep RAM section S8 of RAM[n] on or off in System ON mode + 8 + 8 + + + On + On + 1 + + + + + S9POWER + Keep RAM section S9 of RAM[n] on or off in System ON mode + 9 + 9 + + + On + On + 1 + + + + + S10POWER + Keep RAM section S10 of RAM[n] on or off in System ON mode + 10 + 10 + + + On + On + 1 + + + + + S11POWER + Keep RAM section S11 of RAM[n] on or off in System ON mode + 11 + 11 + + + On + On + 1 + + + + + S12POWER + Keep RAM section S12 of RAM[n] on or off in System ON mode + 12 + 12 + + + On + On + 1 + + + + + S13POWER + Keep RAM section S13 of RAM[n] on or off in System ON mode + 13 + 13 + + + On + On + 1 + + + + + S14POWER + Keep RAM section S14 of RAM[n] on or off in System ON mode + 14 + 14 + + + On + On + 1 + + + + + S15POWER + Keep RAM section S15 of RAM[n] on or off in System ON mode + 15 + 15 + + + On + On + 1 + + + + + S0RETENTION + Keep retention on RAM section S0 of RAM[n] when RAM section is switched off + 16 + 16 + + + On + On + 1 + + + + + S1RETENTION + Keep retention on RAM section S1 of RAM[n] when RAM section is switched off + 17 + 17 + + + On + On + 1 + + + + + S2RETENTION + Keep retention on RAM section S2 of RAM[n] when RAM section is switched off + 18 + 18 + + + On + On + 1 + + + + + S3RETENTION + Keep retention on RAM section S3 of RAM[n] when RAM section is switched off + 19 + 19 + + + On + On + 1 + + + + + S4RETENTION + Keep retention on RAM section S4 of RAM[n] when RAM section is switched off + 20 + 20 + + + On + On + 1 + + + + + S5RETENTION + Keep retention on RAM section S5 of RAM[n] when RAM section is switched off + 21 + 21 + + + On + On + 1 + + + + + S6RETENTION + Keep retention on RAM section S6 of RAM[n] when RAM section is switched off + 22 + 22 + + + On + On + 1 + + + + + S7RETENTION + Keep retention on RAM section S7 of RAM[n] when RAM section is switched off + 23 + 23 + + + On + On + 1 + + + + + S8RETENTION + Keep retention on RAM section S8 of RAM[n] when RAM section is switched off + 24 + 24 + + + On + On + 1 + + + + + S9RETENTION + Keep retention on RAM section S9 of RAM[n] when RAM section is switched off + 25 + 25 + + + On + On + 1 + + + + + S10RETENTION + Keep retention on RAM section S10 of RAM[n] when RAM section is switched off + 26 + 26 + + + On + On + 1 + + + + + S11RETENTION + Keep retention on RAM section S11 of RAM[n] when RAM section is switched off + 27 + 27 + + + On + On + 1 + + + + + S12RETENTION + Keep retention on RAM section S12 of RAM[n] when RAM section is switched off + 28 + 28 + + + On + On + 1 + + + + + S13RETENTION + Keep retention on RAM section S13 of RAM[n] when RAM section is switched off + 29 + 29 + + + On + On + 1 + + + + + S14RETENTION + Keep retention on RAM section S14 of RAM[n] when RAM section is switched off + 30 + 30 + + + On + On + 1 + + + + + S15RETENTION + Keep retention on RAM section S15 of RAM[n] when RAM section is switched off + 31 + 31 + + + On + On + 1 + + + + + + + POWERCLR + Description cluster: RAM[n] power control clear register + 0x008 + read-write + 0x0000FFFF + + + S0POWER + Keep RAM section S0 of RAM[n] on or off in System ON mode + 0 + 0 + + + Off + Off + 1 + + + + + S1POWER + Keep RAM section S1 of RAM[n] on or off in System ON mode + 1 + 1 + + + Off + Off + 1 + + + + + S2POWER + Keep RAM section S2 of RAM[n] on or off in System ON mode + 2 + 2 + + + Off + Off + 1 + + + + + S3POWER + Keep RAM section S3 of RAM[n] on or off in System ON mode + 3 + 3 + + + Off + Off + 1 + + + + + S4POWER + Keep RAM section S4 of RAM[n] on or off in System ON mode + 4 + 4 + + + Off + Off + 1 + + + + + S5POWER + Keep RAM section S5 of RAM[n] on or off in System ON mode + 5 + 5 + + + Off + Off + 1 + + + + + S6POWER + Keep RAM section S6 of RAM[n] on or off in System ON mode + 6 + 6 + + + Off + Off + 1 + + + + + S7POWER + Keep RAM section S7 of RAM[n] on or off in System ON mode + 7 + 7 + + + Off + Off + 1 + + + + + S8POWER + Keep RAM section S8 of RAM[n] on or off in System ON mode + 8 + 8 + + + Off + Off + 1 + + + + + S9POWER + Keep RAM section S9 of RAM[n] on or off in System ON mode + 9 + 9 + + + Off + Off + 1 + + + + + S10POWER + Keep RAM section S10 of RAM[n] on or off in System ON mode + 10 + 10 + + + Off + Off + 1 + + + + + S11POWER + Keep RAM section S11 of RAM[n] on or off in System ON mode + 11 + 11 + + + Off + Off + 1 + + + + + S12POWER + Keep RAM section S12 of RAM[n] on or off in System ON mode + 12 + 12 + + + Off + Off + 1 + + + + + S13POWER + Keep RAM section S13 of RAM[n] on or off in System ON mode + 13 + 13 + + + Off + Off + 1 + + + + + S14POWER + Keep RAM section S14 of RAM[n] on or off in System ON mode + 14 + 14 + + + Off + Off + 1 + + + + + S15POWER + Keep RAM section S15 of RAM[n] on or off in System ON mode + 15 + 15 + + + Off + Off + 1 + + + + + S0RETENTION + Keep retention on RAM section S0 of RAM[n] when RAM section is switched off + 16 + 16 + + + Off + Off + 1 + + + + + S1RETENTION + Keep retention on RAM section S1 of RAM[n] when RAM section is switched off + 17 + 17 + + + Off + Off + 1 + + + + + S2RETENTION + Keep retention on RAM section S2 of RAM[n] when RAM section is switched off + 18 + 18 + + + Off + Off + 1 + + + + + S3RETENTION + Keep retention on RAM section S3 of RAM[n] when RAM section is switched off + 19 + 19 + + + Off + Off + 1 + + + + + S4RETENTION + Keep retention on RAM section S4 of RAM[n] when RAM section is switched off + 20 + 20 + + + Off + Off + 1 + + + + + S5RETENTION + Keep retention on RAM section S5 of RAM[n] when RAM section is switched off + 21 + 21 + + + Off + Off + 1 + + + + + S6RETENTION + Keep retention on RAM section S6 of RAM[n] when RAM section is switched off + 22 + 22 + + + Off + Off + 1 + + + + + S7RETENTION + Keep retention on RAM section S7 of RAM[n] when RAM section is switched off + 23 + 23 + + + Off + Off + 1 + + + + + S8RETENTION + Keep retention on RAM section S8 of RAM[n] when RAM section is switched off + 24 + 24 + + + Off + Off + 1 + + + + + S9RETENTION + Keep retention on RAM section S9 of RAM[n] when RAM section is switched off + 25 + 25 + + + Off + Off + 1 + + + + + S10RETENTION + Keep retention on RAM section S10 of RAM[n] when RAM section is switched off + 26 + 26 + + + Off + Off + 1 + + + + + S11RETENTION + Keep retention on RAM section S11 of RAM[n] when RAM section is switched off + 27 + 27 + + + Off + Off + 1 + + + + + S12RETENTION + Keep retention on RAM section S12 of RAM[n] when RAM section is switched off + 28 + 28 + + + Off + Off + 1 + + + + + S13RETENTION + Keep retention on RAM section S13 of RAM[n] when RAM section is switched off + 29 + 29 + + + Off + Off + 1 + + + + + S14RETENTION + Keep retention on RAM section S14 of RAM[n] when RAM section is switched off + 30 + 30 + + + Off + Off + 1 + + + + + S15RETENTION + Keep retention on RAM section S15 of RAM[n] when RAM section is switched off + 31 + 31 + + + Off + Off + 1 + + + + + + + + + + VMC_S + Volatile Memory controller 1 + 0x50081000 + + + + + diff --git a/svd/nrf5340-net.svd b/svd/nrf5340-net.svd index 70d1333..74badb2 100644 --- a/svd/nrf5340-net.svd +++ b/svd/nrf5340-net.svd @@ -1,37535 +1,38987 @@ - - - - Nordic Semiconductor - Nordic - nrf5340_network - nrf53 - 1 - nRF53 reference description for system-on-chip with dual ARM 32-bit Cortex-M33 microcontrollers - -Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - -3. Neither the name of Nordic Semiconductor ASA nor the names of its - contributors may be used to endorse or promote products derived from this - software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE -ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE -LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -POSSIBILITY OF SUCH DAMAGE. - - 8 - 32 - 32 - 0x00000000 - 0xFFFFFFFF - - CM33 - r0p4 - little - 1 - 0 - 3 - 0 - 30 - 0 - - system_nrf5340_network - NRF_ - - 129 - - - - FICR_NS - Factory Information Configuration Registers - 0x01FF0000 - FICR - - - - 0 - 0x1000 - registers - - FICR - 0x20 - - - INFO - Device info - FICR_INFO - read-write - 0x200 - - CONFIGID - Configuration identifier - 0x000 - read-only - 0xFFFFFFFF - - - HWID - Identification number for the HW - 0 - 15 - - - - - 0x2 - 0x4 - DEVICEID[%s] - Description collection: Device identifier - 0x004 - read-only - 0xFFFFFFFF - - - DEVICEID - 64 bit unique device identifier - 0 - 31 - - - - - PART - Part code - 0x00C - read-only - 0x00005340 - - - PART - Part code - 0 - 31 - - - N5340 - nRF5340 - 0x5340 - - - Unspecified - Unspecified - 0xFFFFFFFF - - - - - - - VARIANT - Part Variant, Hardware version and Production configuration - 0x010 - read-only - 0xFFFFFFFF - - - VARIANT - Part Variant, Hardware version and Production configuration, encoded as ASCII - 0 - 31 - - - QKAA - QKAA - 0x514B4141 - - - Unspecified - Unspecified - 0xFFFFFFFF - - - - - - - PACKAGE - Package option - 0x014 - read-only - 0xFFFFFFFF - - - PACKAGE - Package option - 0 - 31 - - - QK - QKxx - 94-pin aQFN - 0x2000 - - - Unspecified - Unspecified - 0xFFFFFFFF - - - - - - - RAM - RAM variant - 0x018 - read-only - 0xFFFFFFFF - - - RAM - RAM variant - 0 - 31 - - - K16 - 16 kByte RAM - 0x10 - - - K32 - 32 kByte RAM - 0x20 - - - K64 - 64 kByte RAM - 0x40 - - - K128 - 128 kByte RAM - 0x80 - - - K256 - 256 kByte RAM - 0x100 - - - K512 - 512 kByte RAM - 0x200 - - - Unspecified - Unspecified - 0xFFFFFFFF - - - - - - - FLASH - Flash variant - 0x01C - read-only - 0xFFFFFFFF - - - FLASH - Flash variant - 0 - 31 - - - K128 - 128 kByte FLASH - 0x80 - - - K256 - 256 kByte FLASH - 0x100 - - - K512 - 512 kByte FLASH - 0x200 - - - K1024 - 1 MByte FLASH - 0x400 - - - K2048 - 2 MByte FLASH - 0x800 - - - Unspecified - Unspecified - 0xFFFFFFFF - - - - - - - CODEPAGESIZE - Code memory page size in bytes - 0x020 - read-only - 0x00000800 - - - CODEPAGESIZE - Code memory page size in bytes - 0 - 31 - - - K2048 - 2 kByte - 0x800 - - - - - - - CODESIZE - Code memory size - 0x024 - read-only - 0x00000080 - - - CODESIZE - Code memory size in number of pages - 0 - 31 - - - P128 - 128 pages - 128 - - - - - - - DEVICETYPE - Device type - 0x028 - read-only - 0x00000000 - - - DEVICETYPE - Device type - 0 - 31 - - - Die - Device is an physical DIE - 0x0000000 - - - FPGA - Device is an FPGA - 0xFFFFFFFF - - - - - - - - 0x4 - 0x4 - ER[%s] - Description collection: Encryption Root, word n - 0x280 - read-only - 0xFFFFFFFF - - - ER - Encryption Root, word n - 0 - 31 - - - - - 0x4 - 0x4 - IR[%s] - Description collection: Identity Root, word n - 0x290 - read-only - 0xFFFFFFFF - - - IR - Identity Root, word n - 0 - 31 - - - - - DEVICEADDRTYPE - Device address type - 0x2A0 - read-only - 0xFFFFFFFF - - - DEVICEADDRTYPE - Device address type - 0 - 0 - - - Public - Public address - 0 - - - Random - Random address - 1 - - - - - - - 0x2 - 0x4 - DEVICEADDR[%s] - Description collection: Device address n - 0x2A4 - read-only - 0xFFFFFFFF - - - DEVICEADDR - 48 bit device address - 0 - 31 - - - - - 32 - 0x008 - TRIMCNF[%s] - Unspecified - FICR_TRIMCNF - read-write - 0x300 - - ADDR - Description cluster: Address - 0x000 - read-write - 0xFFFFFFFF - uint32_t * - - - Address - Address - 0 - 31 - - - - - DATA - Description cluster: Data - 0x004 - read-only - 0xFFFFFFFF - - - Data - Data - 0 - 31 - - - - - - - - UICR_NS - User Information Configuration Registers - 0x01FF8000 - UICR - - - - 0 - 0x1000 - registers - - UICR - 0x20 - - - APPROTECT - Access port protection - 0x000 - read-write - 0x00000000 - - - PALL - Blocks debugger read/write access to all CPU registers and memory mapped - addresses. - 0 - 31 - - - Unprotected - Unprotected - 0x50FA50FA - - - Protected - Protected - 0x00000000 - - - - - - - ERASEPROTECT - Erase protection - 0x004 - read-write - 0x00000000 - - - PALL - Blocks NVMC ERASEALL and CTRLAP ERASEALL functionality. Using any value except Unprotected will lead to the protection being enabled. - 0 - 31 - - - Unprotected - Unprotected - 0xFFFFFFFF - - - Protected - Protected - 0x00000000 - - - - - - - 0x20 - 0x4 - NRFFW[%s] - Description collection: Reserved for Nordic firmware design - 0x200 - read-write - 0xFFFFFFFF - - - NRFFW - Reserved for Nordic firmware design - 0 - 31 - - - - - 0x20 - 0x4 - CUSTOMER[%s] - Description collection: Reserved for customer - 0x300 - read-write - 0xFFFFFFFF - - - CUSTOMER - Reserved for customer - 0 - 31 - - - - - - - CTI_NS - Cross-Trigger Interface control. NOTE: this is not a separate peripheral, but describes CM33 functionality. - 0xE0042000 - CTI - - - - 0 - 0x1000 - registers - - CTI - 0x20 - - - CTICONTROL - CTI Control register - 0x000 - read-write - 0x00000000 - - - GLBEN - Enables or disables the CTI. - 0 - 0 - - - Disabled - All cross-triggering mapping logic functionality is disabled. - 0 - - - Enabled - Cross-triggering mapping logic functionality is enabled. - 1 - - - - - - - CTIINTACK - CTI Interrupt Acknowledge register - 0x010 - write-only - 0x00000000 - - - DEBUGREQ - Processor debug request - 0 - 0 - - write - - Acknowledge - Clears the ctitrigout. - 1 - - - - - CPURESTART - Processor Restart - 1 - 1 - - write - - Acknowledge - Clears the ctitrigout. - 1 - - - - - UNUSED0 - N/A - 2 - 2 - - write - - Acknowledge - Clears the ctitrigout. - 1 - - - - - UNUSED1 - N/A - 3 - 3 - - write - - Acknowledge - Clears the ctitrigout. - 1 - - - - - UNUSED2 - N/A - 4 - 4 - - write - - Acknowledge - Clears the ctitrigout. - 1 - - - - - UNUSED3 - N/A - 5 - 5 - - write - - Acknowledge - Clears the ctitrigout. - 1 - - - - - UNUSED4 - N/A - 6 - 6 - - write - - Acknowledge - Clears the ctitrigout. - 1 - - - - - UNUSED5 - N/A - 7 - 7 - - write - - Acknowledge - Clears the ctitrigout. - 1 - - - - - - - CTIAPPSET - CTI Application Trigger Set register - 0x014 - read-write - 0x00000000 - - - APPSET_0 - Application trigger event for channel 0. - 0 - 0 - - read - - Inactive - Application trigger 0 is inactive. - 0 - - - Active - Application trigger 0 is active. - 1 - - - - write - - Activate - Generate channel event for channel 0. - 1 - - - - - APPSET_1 - Application trigger event for channel 1. - 1 - 1 - - read - - Inactive - Application trigger 1 is inactive. - 0 - - - Active - Application trigger 1 is active. - 1 - - - - write - - Activate - Generate channel event for channel 1. - 1 - - - - - APPSET_2 - Application trigger event for channel 2. - 2 - 2 - - read - - Inactive - Application trigger 2 is inactive. - 0 - - - Active - Application trigger 2 is active. - 1 - - - - write - - Activate - Generate channel event for channel 2. - 1 - - - - - APPSET_3 - Application trigger event for channel 3. - 3 - 3 - - read - - Inactive - Application trigger 3 is inactive. - 0 - - - Active - Application trigger 3 is active. - 1 - - - - write - - Activate - Generate channel event for channel 3. - 1 - - - - - - - CTIAPPCLEAR - CTI Application Trigger Clear register - 0x018 - write-only - 0x00000000 - - - APPCLEAR_0 - Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. - 0 - 0 - - write - - Clear - Clears the event for channel 0. - 1 - - - - - APPCLEAR_1 - Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. - 1 - 1 - - write - - Clear - Clears the event for channel 1. - 1 - - - - - APPCLEAR_2 - Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. - 2 - 2 - - write - - Clear - Clears the event for channel 2. - 1 - - - - - APPCLEAR_3 - Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. - 3 - 3 - - write - - Clear - Clears the event for channel 3. - 1 - - - - - - - CTIAPPPULSE - CTI Application Pulse register - 0x01C - write-only - 0x00000000 - - - APPULSE_0 - Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. - 0 - 0 - - write - - Generate - Generates an event pulse on channel 0. - 1 - - - - - APPULSE_1 - Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. - 1 - 1 - - write - - Generate - Generates an event pulse on channel 1. - 1 - - - - - APPULSE_2 - Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. - 2 - 2 - - write - - Generate - Generates an event pulse on channel 2. - 1 - - - - - APPULSE_3 - Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. - 3 - 3 - - write - - Generate - Generates an event pulse on channel 3. - 1 - - - - - - - 0x8 - 0x4 - CTIINEN[%s] - Description collection: CTI Trigger input - 0x020 - read-write - 0x00000000 - - - TRIGINEN_0 - Enables a cross trigger event to channel 0 when a ctitrigin input is activated. - 0 - 0 - - - Disabled - Input trigger n events are ignored by channel 0. - 0 - - - Enabled - When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 0. - 1 - - - - - TRIGINEN_1 - Enables a cross trigger event to channel 1 when a ctitrigin input is activated. - 1 - 1 - - - Disabled - Input trigger n events are ignored by channel 1. - 0 - - - Enabled - When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 1. - 1 - - - - - TRIGINEN_2 - Enables a cross trigger event to channel 2 when a ctitrigin input is activated. - 2 - 2 - - - Disabled - Input trigger n events are ignored by channel 2. - 0 - - - Enabled - When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 2. - 1 - - - - - TRIGINEN_3 - Enables a cross trigger event to channel 3 when a ctitrigin input is activated. - 3 - 3 - - - Disabled - Input trigger n events are ignored by channel 3. - 0 - - - Enabled - When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 3. - 1 - - - - - - - 0x8 - 0x4 - CTIOUTEN[%s] - Description collection: CTI Trigger output - 0x0A0 - read-write - 0x00000000 - - - TRIGOUTEN_0 - Enables a cross trigger event to ctitrigout when channel 0 is activated. - 0 - 0 - - - Disabled - Channel 0 is ignored by output trigger n. - 0 - - - Enabled - When an event occurs on channel 0, generate an event on output event n (ctitrigout[n]). - 1 - - - - - TRIGOUTEN_1 - Enables a cross trigger event to ctitrigout when channel 1 is activated. - 1 - 1 - - - Disabled - Channel 1 is ignored by output trigger n. - 0 - - - Enabled - When an event occurs on channel 1, generate an event on output event n (ctitrigout[n]). - 1 - - - - - TRIGOUTEN_2 - Enables a cross trigger event to ctitrigout when channel 2 is activated. - 2 - 2 - - - Disabled - Channel 2 is ignored by output trigger n. - 0 - - - Enabled - When an event occurs on channel 2, generate an event on output event n (ctitrigout[n]). - 1 - - - - - TRIGOUTEN_3 - Enables a cross trigger event to ctitrigout when channel 3 is activated. - 3 - 3 - - - Disabled - Channel 3 is ignored by output trigger n. - 0 - - - Enabled - When an event occurs on channel 3, generate an event on output event n (ctitrigout[n]). - 1 - - - - - - - CTITRIGINSTATUS - CTI Trigger In Status register - 0x130 - read-only - 0x00000000 - - - CPUHALTED - Processor Halted - 0 - 0 - - - Active - Ctitrigin 0 is active. - 1 - - - Inactive - Ctitrigin 0 is inactive. - 0 - - - - - DWTCOMPOUT0 - DWT Comparator Output 0 - 1 - 1 - - - Active - Ctitrigin 1 is active. - 1 - - - Inactive - Ctitrigin 1 is inactive. - 0 - - - - - DWTCOMPOUT1 - DWT Comparator Output 1 - 2 - 2 - - - Active - Ctitrigin 2 is active. - 1 - - - Inactive - Ctitrigin 2 is inactive. - 0 - - - - - DWTCOMPOUT2 - DWT Comparator Output 2 - 3 - 3 - - - Active - Ctitrigin 3 is active. - 1 - - - Inactive - Ctitrigin 3 is inactive. - 0 - - - - - UNUSED0 - N/A - 4 - 4 - - - Active - Ctitrigin 4 is active. - 1 - - - Inactive - Ctitrigin 4 is inactive. - 0 - - - - - UNUSED1 - N/A - 5 - 5 - - - Active - Ctitrigin 5 is active. - 1 - - - Inactive - Ctitrigin 5 is inactive. - 0 - - - - - UNUSED2 - N/A - 6 - 6 - - - Active - Ctitrigin 6 is active. - 1 - - - Inactive - Ctitrigin 6 is inactive. - 0 - - - - - UNUSED3 - N/A - 7 - 7 - - - Active - Ctitrigin 7 is active. - 1 - - - Inactive - Ctitrigin 7 is inactive. - 0 - - - - - - - CTITRIGOUTSTATUS - CTI Trigger Out Status register - 0x134 - read-only - 0x00000000 - - - DEBUGREQ - Processor debug request - 0 - 0 - - - Active - Ctitrigout 0 is active. - 1 - - - Inactive - Ctitrigout 0 is inactive. - 0 - - - - - CPURESTART - Processor Restart - 1 - 1 - - - Active - Ctitrigout 1 is active. - 1 - - - Inactive - Ctitrigout 1 is inactive. - 0 - - - - - UNUSED0 - N/A - 2 - 2 - - - Active - Ctitrigout 2 is active. - 1 - - - Inactive - Ctitrigout 2 is inactive. - 0 - - - - - UNUSED1 - N/A - 3 - 3 - - - Active - Ctitrigout 3 is active. - 1 - - - Inactive - Ctitrigout 3 is inactive. - 0 - - - - - UNUSED2 - N/A - 4 - 4 - - - Active - Ctitrigout 4 is active. - 1 - - - Inactive - Ctitrigout 4 is inactive. - 0 - - - - - UNUSED3 - N/A - 5 - 5 - - - Active - Ctitrigout 5 is active. - 1 - - - Inactive - Ctitrigout 5 is inactive. - 0 - - - - - UNUSED4 - N/A - 6 - 6 - - - Active - Ctitrigout 6 is active. - 1 - - - Inactive - Ctitrigout 6 is inactive. - 0 - - - - - UNUSED5 - N/A - 7 - 7 - - - Active - Ctitrigout 7 is active. - 1 - - - Inactive - Ctitrigout 7 is inactive. - 0 - - - - - - - CTICHINSTATUS - CTI Channel In Status register - 0x138 - read-only - 0x00000000 - - - CTICHINSTATUS_0 - Shows the status of the ctitrigin 0 input. - 0 - 0 - - - Active - Ctichin 0 is active. - 1 - - - Inactive - Ctichin 0 is inactive. - 0 - - - - - CTICHINSTATUS_1 - Shows the status of the ctitrigin 1 input. - 1 - 1 - - - Active - Ctichin 1 is active. - 1 - - - Inactive - Ctichin 1 is inactive. - 0 - - - - - CTICHINSTATUS_2 - Shows the status of the ctitrigin 2 input. - 2 - 2 - - - Active - Ctichin 2 is active. - 1 - - - Inactive - Ctichin 2 is inactive. - 0 - - - - - CTICHINSTATUS_3 - Shows the status of the ctitrigin 3 input. - 3 - 3 - - - Active - Ctichin 3 is active. - 1 - - - Inactive - Ctichin 3 is inactive. - 0 - - - - - - - CTIGATE - Enable CTI Channel Gate register - 0x140 - read-write - 0x0000000F - - - CTIGATEEN_0 - Enable ctichout0. - 0 - 0 - - - Enabled - Enable ctichout channel 0 propagation. - 1 - - - Disabled - Disable ctichout channel 0 propagation. - 0 - - - - - CTIGATEEN_1 - Enable ctichout1. - 1 - 1 - - - Enabled - Enable ctichout channel 1 propagation. - 1 - - - Disabled - Disable ctichout channel 1 propagation. - 0 - - - - - CTIGATEEN_2 - Enable ctichout2. - 2 - 2 - - - Enabled - Enable ctichout channel 2 propagation. - 1 - - - Disabled - Disable ctichout channel 2 propagation. - 0 - - - - - CTIGATEEN_3 - Enable ctichout3. - 3 - 3 - - - Enabled - Enable ctichout channel 3 propagation. - 1 - - - Disabled - Disable ctichout channel 3 propagation. - 0 - - - - - - - DEVARCH - Device Architecture register - 0xFBC - read-only - 0x47701A14 - - - Architecture - Contains the CTI device architecture. - 0 - 0 - - - - - DEVID - Device Configuration register - 0xFC8 - read-only - 0x00040800 - - - EXTMUXNUM - Indicates the number of multiplexers available on Trigger Inputs and Trigger Outputs that are using asicctl. - The default value of 0b00000 indicates that no multiplexing is present. - 0 - 4 - - - NUMTRIG - Number of ECT triggers available. - 8 - 15 - - - NUMCH - Number of ECT channels available. - 16 - 19 - - - - - DEVTYPE - Device Type Identifier register - 0xFCC - read-only - 0x00000014 - - - MAJOR - Major classification of the type of the debug component as specified in the Arm Architecture Specification for this - debug and trace component. - 0 - 3 - - - Controller - Indicates that this component allows a debugger to control other components in an Arm CoreSight SoC-400 system. - 4 - - - - - SUB - Sub-classification of the type of the debug component as specified in the Arm Architecture Specification within - the major classification as specified in the MAJOR field. - 4 - 7 - - - Crosstrigger - Indicates that this component is a sub-triggering component. - 1 - - - - - - - PIDR4 - Peripheral ID4 Register - 0xFD0 - read-only - 0x00000004 - - - DES_2 - Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. - 0 - 3 - - - Code - JEDEC continuation code. - 4 - - - - - SIZE - Always 0b0000. Indicates that the device only occupies 4KB of memory. - 4 - 7 - - - - - PIDR5 - Peripheral ID5 register - 0xFD4 - read-only - - - PIDR6 - Peripheral ID6 register - 0xFD8 - read-only - - - PIDR7 - Peripheral ID7 register - 0xFDC - read-only - - - PIDR0 - Peripheral ID0 Register - 0xFE0 - read-only - 0x00000021 - - - PART_0 - Bits[7:0] of the 12-bit part number of the component. The designer of the component assigns this part number. - 0 - 7 - - - PartnumberL - Indicates bits[7:0] of the part number of the component. - 0x21 - - - - - - - PIDR1 - Peripheral ID1 Register - 0xFE4 - read-only - 0x000000BD - - - PART_1 - Bits[11:8] of the 12-bit part number of the component. The designer of the component assigns this part number. - 0 - 3 - - - PartnumberH - Indicates bits[11:8] of the part number of the component. - 13 - - - - - DES_0 - Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. - 4 - 7 - - - Arm - Arm. Bits[3:0] of the JEDEC JEP106 Identity Code - 11 - - - - - - - PIDR2 - Peripheral ID2 Register - 0xFE8 - read-only - 0x0000000B - - - DES_1 - Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. - 0 - 2 - - - Arm - Arm. Bits[6:4] of the JEDEC JEP106 Identity Code - 3 - - - - - JEDEC - Always 1. Indicates that the JEDEC-assigned designer ID is used. - 3 - 3 - - - REVISION - Peripheral revision - 4 - 7 - - - Rev0p0 - This device is at r0p0 - 0 - - - - - - - PIDR3 - Peripheral ID3 Register - 0xFEC - read-only - 0x00000000 - - - CMOD - Customer Modified. Indicates whether the customer has modified the behavior of the component. In most cases, - this field is 0b0000. Customers change this value when they make authorized modifications to this component. - 0 - 3 - - - Unmodified - Indicates that the customer has not modified this component. - 0 - - - - - REVAND - Indicates minor errata fixes specific to the revision of the component being used, for example metal fixes after - implementation. In most cases, this field is 0b0000. Arm recommends that the component designers ensure that a - metal fix can change this field if required, for example, by driving it from registers that reset to 0b0000. - 4 - 7 - - - NoErrata - Indicates that there are no errata fixes to this component. - 0 - - - - - - - CIDR0 - Component ID0 Register - 0xFF0 - read-only - 0x0000000D - - - PRMBL_0 - Preamble[0]. Contains bits[7:0] of the component identification code. - 0 - 7 - - - Value - Bits[7:0] of the identification code. - 0x0D - - - - - - - CIDR1 - Component ID1 Register - 0xFF4 - read-only - 0x00000090 - - - PRMBL_1 - Preamble[1]. Contains bits[11:8] of the component identification code. - 0 - 3 - - - Value - Bits[11:8] of the identification code. - 0 - - - - - CLASS - Class of the component, for example, whether the component is a ROM table or a generic CoreSight component. - Contains bits[15:12] of the component identification code - 4 - 7 - - - Coresight - Indicates that the component is a CoreSight component. - 9 - - - - - - - CIDR2 - Component ID2 Register - 0xFF8 - read-only - 0x00000005 - - - PRMBL_2 - Preamble[2]. Contains bits[23:16] of the component identification code. - 0 - 7 - - - Value - Bits[23:16] of the identification code. - 0x05 - - - - - - - CIDR3 - Component ID3 Register - 0xFFC - read-only - 0x000000B1 - - - PRMBL_3 - Preamble[3]. Contains bits[31:24] of the component identification code. - 0 - 7 - - - Value - Bits[31:24] of the identification code. - 0xB1 - - - - - - - - - DCNF_NS - Domain configuration management - 0x41000000 - DCNF - - - - 0 - 0x1000 - registers - - DCNF - 0x20 - - - CPUID - CPU ID of this subsystem - 0x420 - read-only - 0x00000001 - - - CPUID - CPU ID - 0 - 7 - - - - - - - VREQCTRL_NS - Voltage request control - 0x41004000 - VREQCTRL - - - - 0 - 0x1000 - registers - - VREQCTRL - 0x20 - - - VREGRADIO - Unspecified - VREQCTRL_VREGRADIO - read-write - 0x500 - - VREQH - Request high voltage on RADIO After requesting high voltage, the user must wait until VREQHREADY is set to Ready - 0x000 - read-write - - - VREQH - Request high voltage - 0 - 0 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - VREQHREADY - High voltage on RADIO is ready - 0x008 - read-only - - - READY - RADIO is ready to operate on high voltage - 0 - 0 - - - NotReady - Not ready - 0 - - - Ready - Ready - 1 - - - - - - - - - - CLOCK_NS - Clock management - 0x41005000 - CLOCK - - - - 0 - 0x1000 - registers - - - CLOCK_POWER - 5 - - CLOCK - 0x20 - - - TASKS_HFCLKSTART - Start HFCLK128M/HFCLK64M source as selected in HFCLKSRC - 0x000 - write-only - - - TASKS_HFCLKSTART - Start HFCLK128M/HFCLK64M source as selected in HFCLKSRC - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_HFCLKSTOP - Stop HFCLK128M/HFCLK64M source - 0x004 - write-only - - - TASKS_HFCLKSTOP - Stop HFCLK128M/HFCLK64M source - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_LFCLKSTART - Start LFCLK source as selected in LFCLKSRC - 0x008 - write-only - - - TASKS_LFCLKSTART - Start LFCLK source as selected in LFCLKSRC - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_LFCLKSTOP - Stop LFCLK source - 0x00C - write-only - - - TASKS_LFCLKSTOP - Stop LFCLK source - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_CAL - Start calibration of LFRC oscillator - 0x010 - write-only - - - TASKS_CAL - Start calibration of LFRC oscillator - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - SUBSCRIBE_HFCLKSTART - Subscribe configuration for task HFCLKSTART - 0x080 - read-write - - - CHIDX - DPPI channel that task HFCLKSTART will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_HFCLKSTOP - Subscribe configuration for task HFCLKSTOP - 0x084 - read-write - - - CHIDX - DPPI channel that task HFCLKSTOP will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_LFCLKSTART - Subscribe configuration for task LFCLKSTART - 0x088 - read-write - - - CHIDX - DPPI channel that task LFCLKSTART will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_LFCLKSTOP - Subscribe configuration for task LFCLKSTOP - 0x08C - read-write - - - CHIDX - DPPI channel that task LFCLKSTOP will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_CAL - Subscribe configuration for task CAL - 0x090 - read-write - - - CHIDX - DPPI channel that task CAL will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - EVENTS_HFCLKSTARTED - HFCLK128M/HFCLK64M source started - 0x100 - read-write - - - EVENTS_HFCLKSTARTED - HFCLK128M/HFCLK64M source started - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_LFCLKSTARTED - LFCLK source started - 0x104 - read-write - - - EVENTS_LFCLKSTARTED - LFCLK source started - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_DONE - Calibration of LFRC oscillator complete event - 0x11C - read-write - - - EVENTS_DONE - Calibration of LFRC oscillator complete event - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - PUBLISH_HFCLKSTARTED - Publish configuration for event HFCLKSTARTED - 0x180 - read-write - - - CHIDX - DPPI channel that event HFCLKSTARTED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_LFCLKSTARTED - Publish configuration for event LFCLKSTARTED - 0x184 - read-write - - - CHIDX - DPPI channel that event LFCLKSTARTED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_DONE - Publish configuration for event DONE - 0x19C - read-write - - - CHIDX - DPPI channel that event DONE will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - - HFCLKSTARTED - Enable or disable interrupt for event HFCLKSTARTED - 0 - 0 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - LFCLKSTARTED - Enable or disable interrupt for event LFCLKSTARTED - 1 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - DONE - Enable or disable interrupt for event DONE - 7 - 7 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - HFCLKSTARTED - Write '1' to enable interrupt for event HFCLKSTARTED - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - LFCLKSTARTED - Write '1' to enable interrupt for event LFCLKSTARTED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - DONE - Write '1' to enable interrupt for event DONE - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - HFCLKSTARTED - Write '1' to disable interrupt for event HFCLKSTARTED - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - LFCLKSTARTED - Write '1' to disable interrupt for event LFCLKSTARTED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - DONE - Write '1' to disable interrupt for event DONE - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - INTPEND - Pending interrupts - 0x30C - read-only - - - HFCLKSTARTED - Read pending status of interrupt for event HFCLKSTARTED - 0 - 0 - - read - - NotPending - Read: Not pending - 0 - - - Pending - Read: Pending - 1 - - - - - LFCLKSTARTED - Read pending status of interrupt for event LFCLKSTARTED - 1 - 1 - - read - - NotPending - Read: Not pending - 0 - - - Pending - Read: Pending - 1 - - - - - DONE - Read pending status of interrupt for event DONE - 7 - 7 - - read - - NotPending - Read: Not pending - 0 - - - Pending - Read: Pending - 1 - - - - - - - HFCLKRUN - Status indicating that HFCLKSTART task has been triggered - 0x408 - read-only - - - STATUS - HFCLKSTART task triggered or not - 0 - 0 - - - NotTriggered - Task not triggered - 0 - - - Triggered - Task triggered - 1 - - - - - - - HFCLKSTAT - Status indicating which HFCLK128M/HFCLK64M source is running This register value in any CLOCK instance reflects status only due to configurations/actions in that CLOCK instance. - 0x40C - read-only - - - SRC - Active clock source - 0 - 0 - - - HFINT - Clock source: HFINT - 128 MHz on-chip oscillator - 0 - - - HFXO - Clock source: HFXO - 128 MHz clock derived from external 32 MHz crystal oscillator - 1 - - - - - ALWAYSRUNNING - ALWAYSRUN activated - 4 - 4 - - - NotRunning - Automatic clock control enabled - 0 - - - Running - Oscillator is always running - 1 - - - - - STATE - HFCLK state - 16 - 16 - - - NotRunning - HFCLK not running - 0 - - - Running - HFCLK running - 1 - - - - - - - LFCLKRUN - Status indicating that LFCLKSTART task has been triggered - 0x414 - read-only - - - STATUS - LFCLKSTART task triggered or not - 0 - 0 - - - NotTriggered - Task not triggered - 0 - - - Triggered - Task triggered - 1 - - - - - - - LFCLKSTAT - Status indicating which LFCLK source is running This register value in any CLOCK instance reflects status only due to configurations/actions in that CLOCK instance. - 0x418 - read-only - - - SRC - Active clock source - 0 - 1 - - - LFRC - 32.768 kHz RC oscillator - 1 - - - LFXO - 32.768 kHz crystal oscillator - 2 - - - LFSYNT - 32.768 kHz synthesized from HFCLK - 3 - - - - - ALWAYSRUNNING - ALWAYSRUN activated - 4 - 4 - - - NotRunning - Automatic clock control enabled - 0 - - - Running - Oscillator is always running - 1 - - - - - STATE - LFCLK state - 16 - 16 - - - NotRunning - LFCLK not running - 0 - - - Running - LFCLK running - 1 - - - - - - - LFCLKSRCCOPY - Copy of LFCLKSRC register, set when LFCLKSTART task was triggered - 0x41C - read-only - 0x00000001 - - - SRC - Clock source - 0 - 1 - - - LFRC - 32.768 kHz RC oscillator - 1 - - - LFXO - 32.768 kHz crystal oscillator - 2 - - - LFSYNT - 32.768 kHz synthesized from HFCLK - 3 - - - - - - - HFCLKSRC - Clock source for HFCLK128M/HFCLK64M - 0x514 - read-write - 0x00000001 - - - SRC - Select which HFCLK source is started by the HFCLKSTART task - 0 - 0 - - - HFINT - HFCLKSTART task starts HFINT oscillator - 0 - - - HFXO - HFCLKSTART task starts HFXO oscillator - 1 - - - - - - - LFCLKSRC - Clock source for LFCLK - 0x518 - read-write - 0x00000001 - - - SRC - Select which LFCLK source is started by the LFCLKSTART task - 0 - 1 - - - LFRC - 32.768 kHz RC oscillator - 1 - - - LFXO - 32.768 kHz crystal oscillator - 2 - - - LFSYNT - 32.768 kHz synthesized from HFCLK - 3 - - - - - - - HFCLKCTRL - HFCLK128M frequency configuration - 0x558 - read-write - 0x00000000 - - - HCLK - High frequency clock HCLK - 0 - 1 - - - Div1 - Divide HFCLK by 1 - 0 - - - Div2 - Divide HFCLK by 2 - 1 - - - - - - - HFCLKALWAYSRUN - Automatic or manual control of HFCLK128M/HFCLK64M - 0x570 - read-write - - - ALWAYSRUN - Ensure clock is always running - 0 - 0 - - - Automatic - Use automatic clock control - 0 - - - AlwaysRun - Ensure clock is always running - 1 - - - - - - - LFCLKALWAYSRUN - Automatic or manual control of LFCLK - 0x574 - read-write - - - ALWAYSRUN - Ensure clock is always running - 0 - 0 - - - Automatic - Use automatic clock control - 0 - - - AlwaysRun - Ensure clock is always running - 1 - - - - - - - - - POWER_NS - Power control - 0x41005000 - CLOCK_NS - POWER - - - - 0 - 0x1000 - registers - - - CLOCK_POWER - 5 - - POWER - 0x20 - - - TASKS_CONSTLAT - Enable Constant Latency mode - 0x78 - write-only - - - TASKS_CONSTLAT - Enable Constant Latency mode - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_LOWPWR - Enable Low-Power mode (variable latency) - 0x7C - write-only - - - TASKS_LOWPWR - Enable Low-Power mode (variable latency) - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - SUBSCRIBE_CONSTLAT - Subscribe configuration for task CONSTLAT - 0xF8 - read-write - - - CHIDX - DPPI channel that task CONSTLAT will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_LOWPWR - Subscribe configuration for task LOWPWR - 0xFC - read-write - - - CHIDX - DPPI channel that task LOWPWR will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - EVENTS_POFWARN - Power failure warning - 0x108 - read-write - - - EVENTS_POFWARN - Power failure warning - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_SLEEPENTER - CPU entered WFI/WFE sleep - 0x114 - read-write - - - EVENTS_SLEEPENTER - CPU entered WFI/WFE sleep - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_SLEEPEXIT - CPU exited WFI/WFE sleep - 0x118 - read-write - - - EVENTS_SLEEPEXIT - CPU exited WFI/WFE sleep - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - PUBLISH_POFWARN - Publish configuration for event POFWARN - 0x188 - read-write - - - CHIDX - DPPI channel that event POFWARN will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_SLEEPENTER - Publish configuration for event SLEEPENTER - 0x194 - read-write - - - CHIDX - DPPI channel that event SLEEPENTER will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_SLEEPEXIT - Publish configuration for event SLEEPEXIT - 0x198 - read-write - - - CHIDX - DPPI channel that event SLEEPEXIT will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - - POFWARN - Enable or disable interrupt for event POFWARN - 2 - 2 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - SLEEPENTER - Enable or disable interrupt for event SLEEPENTER - 5 - 5 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - SLEEPEXIT - Enable or disable interrupt for event SLEEPEXIT - 6 - 6 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - POFWARN - Write '1' to enable interrupt for event POFWARN - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - SLEEPENTER - Write '1' to enable interrupt for event SLEEPENTER - 5 - 5 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - SLEEPEXIT - Write '1' to enable interrupt for event SLEEPEXIT - 6 - 6 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - POFWARN - Write '1' to disable interrupt for event POFWARN - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - SLEEPENTER - Write '1' to disable interrupt for event SLEEPENTER - 5 - 5 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - SLEEPEXIT - Write '1' to disable interrupt for event SLEEPEXIT - 6 - 6 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - 0x2 - 0x4 - GPREGRET[%s] - Description collection: General purpose retention register - 0x51C - read-write - - - GPREGRET - General purpose retention register - 0 - 7 - - - - - - - RESET_NS - Reset control - 0x41005000 - CLOCK_NS - RESET - - - - 0 - 0x1000 - registers - - RESET - 0x20 - - - RESETREAS - Reset reason - 0x400 - read-write - - - RESETPIN - Reset from pin reset detected - 0 - 0 - - - NotDetected - Not detected - 0 - - - Detected - Detected - 1 - - - - - DOG0 - Reset from application watchdog timer 0 detected - 1 - 1 - - - NotDetected - Not detected - 0 - - - Detected - Detected - 1 - - - - - CTRLAP - Reset from application CTRL-AP detected - 2 - 2 - - - NotDetected - Not detected - 0 - - - Detected - Detected - 1 - - - - - SREQ - Reset from application soft reset detected - 3 - 3 - - - NotDetected - Not detected - 0 - - - Detected - Detected - 1 - - - - - LOCKUP - Reset from application CPU lockup detected - 4 - 4 - - - NotDetected - Not detected - 0 - - - Detected - Detected - 1 - - - - - OFF - Reset due to wakeup from System OFF mode when wakeup is triggered by DETECT signal from GPIO - 5 - 5 - - - NotDetected - Not detected - 0 - - - Detected - Detected - 1 - - - - - LPCOMP - Reset due to wakeup from System OFF mode when wakeup is triggered by ANADETECT signal from LPCOMP - 6 - 6 - - - NotDetected - Not detected - 0 - - - Detected - Detected - 1 - - - - - DIF - Reset due to wakeup from System OFF mode when wakeup is triggered by entering the Debug Interface mode - 7 - 7 - - - NotDetected - Not detected - 0 - - - Detected - Detected - 1 - - - - - LSREQ - Reset from network soft reset detected - 16 - 16 - - - NotDetected - Not detected - 0 - - - Detected - Detected - 1 - - - - - LLOCKUP - Reset from network CPU lockup detected - 17 - 17 - - - NotDetected - Not detected - 0 - - - Detected - Detected - 1 - - - - - LDOG - Reset from network watchdog timer detected - 18 - 18 - - - NotDetected - Not detected - 0 - - - Detected - Detected - 1 - - - - - MFORCEOFF - Force-OFF reset from application core detected - 23 - 23 - - - NotDetected - Not detected - 0 - - - Detected - Detected - 1 - - - - - NFC - Reset after wakeup from System OFF mode due to NFC field being detected - 24 - 24 - - - NotDetected - Not detected - 0 - - - Detected - Detected - 1 - - - - - DOG1 - Reset from application watchdog timer 1 detected - 25 - 25 - - - NotDetected - Not detected - 0 - - - Detected - Detected - 1 - - - - - VBUS - Reset after wakeup from System OFF mode due to VBUS rising into valid range - 26 - 26 - - - NotDetected - Not detected - 0 - - - Detected - Detected - 1 - - - - - LCTRLAP - Reset from network CTRL-AP detected - 27 - 27 - - - NotDetected - Not detected - 0 - - - Detected - Detected - 1 - - - - - - - - - CTRLAP_NS - Control access port - 0x41006000 - CTRLAPPERI - - - - 0 - 0x1000 - registers - - CTRLAPPERI - 0x20 - - - MAILBOX - Unspecified - CTRLAPPERI_MAILBOX - read-write - 0x400 - - RXDATA - Data sent from the debugger to the CPU. - 0x000 - read-only - 0x00000000 - - - RXDATA - Data received from debugger - 0 - 31 - - - - - RXSTATUS - This register shows a status that indicates if data sent from the debugger to the CPU has been read. - 0x004 - read-only - 0x00000000 - - - RXSTATUS - Status of data in register RXDATA - 0 - 0 - - - NoDataPending - No data pending in register RXDATA - 0 - - - DataPending - Data pending in register RXDATA - 1 - - - - - - - TXDATA - Data sent from the CPU to the debugger. - 0x80 - read-write - 0x00000000 - - - TXDATA - Data sent to debugger - 0 - 31 - - - - - TXSTATUS - This register shows a status that indicates if the data sent from the CPU to the debugger has been read. - 0x84 - read-only - 0x00000000 - - - TXSTATUS - Status of data in register TXDATA - 0 - 0 - - - NoDataPending - No data pending in register TXDATA - 0 - - - DataPending - Data pending in register TXDATA - 1 - - - - - - - - ERASEPROTECT - Unspecified - CTRLAPPERI_ERASEPROTECT - read-write - 0x500 - - LOCK - This register locks the ERASEPROTECT.DISABLE register from being written until next reset. - 0x000 - read-writeOnce - 0x00000000 - - - LOCK - Lock ERASEPROTECT.DISABLE register from being written until next reset - 0 - 0 - - - Unlocked - Register ERASEPROTECT.DISABLE is writeable - 0 - - - Locked - Register ERASEPROTECT.DISABLE is read-only - 1 - - - - - - - DISABLE - This register disables the ERASEPROTECT register and performs an ERASEALL operation. - 0x004 - read-writeOnce - 0x00000000 - - - KEY - The ERASEALL sequence is initiated if the value of the KEY fields are non-zero and the KEY fields match on both the CPU and debugger sides. - 0 - 31 - - - - - - APPROTECT - Unspecified - CTRLAPPERI_APPROTECT - read-write - 0x540 - - LOCK - This register locks the APPROTECT.DISABLE register from being written to until next reset. - 0x000 - read-writeOnce - 0x00000000 - - - LOCK - Lock the APPROTECT.DISABLE register from being written to until next reset - 0 - 0 - - - Unlocked - Register APPROTECT.DISABLE is writeable - 0 - - - Locked - Register APPROTECT.DISABLE is read-only - 1 - - - - - - - DISABLE - This register disables the APPROTECT register and enables debug access to non-secure mode. - 0x004 - read-write - 0x00000000 - - - KEY - If the value of the KEY field is non-zero, and the KEY fields match on both the - CPU and debugger sides, disable APPROTECT and enable debug access to non-secure mode until - the next pin reset, brown-out reset, power-on reset, or watchog timer reset. After reset the debugger side register has a fixed KEY value. To enable debug access, both CTRL-AP and UICR.APPROTECT protection needs to be disabled. - 0 - 31 - - - - - - STATUS - Status bits for CTRL-AP peripheral. - 0x600 - read-only - 0x00000000 - - - UICRAPPROTECT - Status bit for UICR part of access port protection at last reset. - 0 - 0 - - - Enabled - APPROTECT was enabled in UICR - 0 - - - Disabled - APPROTECT wasdisabled in UICR - 1 - - - - - DBGIFACEMODE - Status bit for device debug interface mode - 2 - 2 - - - Disabled - No debugger attached - 0 - - - Enabled - Debugger is attached and device is in debug interface mode - 1 - - - - - - - - - RADIO_NS - 2.4 GHz radio - 0x41008000 - RADIO - - - - 0 - 0x1000 - registers - - - RADIO - 8 - - RADIO - 0x20 - - - TASKS_TXEN - Enable RADIO in TX mode - 0x000 - write-only - - - TASKS_TXEN - Enable RADIO in TX mode - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_RXEN - Enable RADIO in RX mode - 0x004 - write-only - - - TASKS_RXEN - Enable RADIO in RX mode - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_START - Start RADIO - 0x008 - write-only - - - TASKS_START - Start RADIO - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STOP - Stop RADIO - 0x00C - write-only - - - TASKS_STOP - Stop RADIO - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_DISABLE - Disable RADIO - 0x010 - write-only - - - TASKS_DISABLE - Disable RADIO - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_RSSISTART - Start the RSSI and take one single sample of the receive signal strength - 0x014 - write-only - - - TASKS_RSSISTART - Start the RSSI and take one single sample of the receive signal strength - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_RSSISTOP - Stop the RSSI measurement - 0x018 - write-only - - - TASKS_RSSISTOP - Stop the RSSI measurement - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_BCSTART - Start the bit counter - 0x01C - write-only - - - TASKS_BCSTART - Start the bit counter - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_BCSTOP - Stop the bit counter - 0x020 - write-only - - - TASKS_BCSTOP - Stop the bit counter - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_EDSTART - Start the energy detect measurement used in IEEE 802.15.4 mode - 0x024 - write-only - - - TASKS_EDSTART - Start the energy detect measurement used in IEEE 802.15.4 mode - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_EDSTOP - Stop the energy detect measurement - 0x028 - write-only - - - TASKS_EDSTOP - Stop the energy detect measurement - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_CCASTART - Start the clear channel assessment used in IEEE 802.15.4 mode - 0x02C - write-only - - - TASKS_CCASTART - Start the clear channel assessment used in IEEE 802.15.4 mode - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_CCASTOP - Stop the clear channel assessment - 0x030 - write-only - - - TASKS_CCASTOP - Stop the clear channel assessment - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - SUBSCRIBE_TXEN - Subscribe configuration for task TXEN - 0x080 - read-write - - - CHIDX - DPPI channel that task TXEN will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_RXEN - Subscribe configuration for task RXEN - 0x084 - read-write - - - CHIDX - DPPI channel that task RXEN will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_START - Subscribe configuration for task START - 0x088 - read-write - - - CHIDX - DPPI channel that task START will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_STOP - Subscribe configuration for task STOP - 0x08C - read-write - - - CHIDX - DPPI channel that task STOP will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_DISABLE - Subscribe configuration for task DISABLE - 0x090 - read-write - - - CHIDX - DPPI channel that task DISABLE will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_RSSISTART - Subscribe configuration for task RSSISTART - 0x094 - read-write - - - CHIDX - DPPI channel that task RSSISTART will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_RSSISTOP - Subscribe configuration for task RSSISTOP - 0x098 - read-write - - - CHIDX - DPPI channel that task RSSISTOP will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_BCSTART - Subscribe configuration for task BCSTART - 0x09C - read-write - - - CHIDX - DPPI channel that task BCSTART will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_BCSTOP - Subscribe configuration for task BCSTOP - 0x0A0 - read-write - - - CHIDX - DPPI channel that task BCSTOP will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_EDSTART - Subscribe configuration for task EDSTART - 0x0A4 - read-write - - - CHIDX - DPPI channel that task EDSTART will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_EDSTOP - Subscribe configuration for task EDSTOP - 0x0A8 - read-write - - - CHIDX - DPPI channel that task EDSTOP will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_CCASTART - Subscribe configuration for task CCASTART - 0x0AC - read-write - - - CHIDX - DPPI channel that task CCASTART will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_CCASTOP - Subscribe configuration for task CCASTOP - 0x0B0 - read-write - - - CHIDX - DPPI channel that task CCASTOP will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - EVENTS_READY - RADIO has ramped up and is ready to be started - 0x100 - read-write - - - EVENTS_READY - RADIO has ramped up and is ready to be started - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_ADDRESS - Address sent or received - 0x104 - read-write - - - EVENTS_ADDRESS - Address sent or received - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_PAYLOAD - Packet payload sent or received - 0x108 - read-write - - - EVENTS_PAYLOAD - Packet payload sent or received - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_END - Packet sent or received - 0x10C - read-write - - - EVENTS_END - Packet sent or received - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_DISABLED - RADIO has been disabled - 0x110 - read-write - - - EVENTS_DISABLED - RADIO has been disabled - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_DEVMATCH - A device address match occurred on the last received packet - 0x114 - read-write - - - EVENTS_DEVMATCH - A device address match occurred on the last received packet - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_DEVMISS - No device address match occurred on the last received packet - 0x118 - read-write - - - EVENTS_DEVMISS - No device address match occurred on the last received packet - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_RSSIEND - Sampling of receive signal strength complete - 0x11C - read-write - - - EVENTS_RSSIEND - Sampling of receive signal strength complete - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_BCMATCH - Bit counter reached bit count value - 0x128 - read-write - - - EVENTS_BCMATCH - Bit counter reached bit count value - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_CRCOK - Packet received with CRC ok - 0x130 - read-write - - - EVENTS_CRCOK - Packet received with CRC ok - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_CRCERROR - Packet received with CRC error - 0x134 - read-write - - - EVENTS_CRCERROR - Packet received with CRC error - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_FRAMESTART - IEEE 802.15.4 length field received - 0x138 - read-write - - - EVENTS_FRAMESTART - IEEE 802.15.4 length field received - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_EDEND - Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. - 0x13C - read-write - - - EVENTS_EDEND - Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_EDSTOPPED - The sampling of energy detection has stopped - 0x140 - read-write - - - EVENTS_EDSTOPPED - The sampling of energy detection has stopped - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_CCAIDLE - Wireless medium in idle - clear to send - 0x144 - read-write - - - EVENTS_CCAIDLE - Wireless medium in idle - clear to send - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_CCABUSY - Wireless medium busy - do not send - 0x148 - read-write - - - EVENTS_CCABUSY - Wireless medium busy - do not send - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_CCASTOPPED - The CCA has stopped - 0x14C - read-write - - - EVENTS_CCASTOPPED - The CCA has stopped - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_RATEBOOST - Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. - 0x150 - read-write - - - EVENTS_RATEBOOST - Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_TXREADY - RADIO has ramped up and is ready to be started TX path - 0x154 - read-write - - - EVENTS_TXREADY - RADIO has ramped up and is ready to be started TX path - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_RXREADY - RADIO has ramped up and is ready to be started RX path - 0x158 - read-write - - - EVENTS_RXREADY - RADIO has ramped up and is ready to be started RX path - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_MHRMATCH - MAC header match found - 0x15C - read-write - - - EVENTS_MHRMATCH - MAC header match found - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_SYNC - Preamble indicator - 0x168 - read-write - - - EVENTS_SYNC - Preamble indicator - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_PHYEND - Generated when last bit is sent on air, or received from air - 0x16C - read-write - - - EVENTS_PHYEND - Generated when last bit is sent on air, or received from air - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_CTEPRESENT - CTE is present (early warning right after receiving CTEInfo byte) - 0x170 - read-write - - - EVENTS_CTEPRESENT - CTE is present (early warning right after receiving CTEInfo byte) - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - PUBLISH_READY - Publish configuration for event READY - 0x180 - read-write - - - CHIDX - DPPI channel that event READY will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_ADDRESS - Publish configuration for event ADDRESS - 0x184 - read-write - - - CHIDX - DPPI channel that event ADDRESS will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_PAYLOAD - Publish configuration for event PAYLOAD - 0x188 - read-write - - - CHIDX - DPPI channel that event PAYLOAD will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_END - Publish configuration for event END - 0x18C - read-write - - - CHIDX - DPPI channel that event END will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_DISABLED - Publish configuration for event DISABLED - 0x190 - read-write - - - CHIDX - DPPI channel that event DISABLED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_DEVMATCH - Publish configuration for event DEVMATCH - 0x194 - read-write - - - CHIDX - DPPI channel that event DEVMATCH will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_DEVMISS - Publish configuration for event DEVMISS - 0x198 - read-write - - - CHIDX - DPPI channel that event DEVMISS will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_RSSIEND - Publish configuration for event RSSIEND - 0x19C - read-write - - - CHIDX - DPPI channel that event RSSIEND will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_BCMATCH - Publish configuration for event BCMATCH - 0x1A8 - read-write - - - CHIDX - DPPI channel that event BCMATCH will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_CRCOK - Publish configuration for event CRCOK - 0x1B0 - read-write - - - CHIDX - DPPI channel that event CRCOK will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_CRCERROR - Publish configuration for event CRCERROR - 0x1B4 - read-write - - - CHIDX - DPPI channel that event CRCERROR will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_FRAMESTART - Publish configuration for event FRAMESTART - 0x1B8 - read-write - - - CHIDX - DPPI channel that event FRAMESTART will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_EDEND - Publish configuration for event EDEND - 0x1BC - read-write - - - CHIDX - DPPI channel that event EDEND will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_EDSTOPPED - Publish configuration for event EDSTOPPED - 0x1C0 - read-write - - - CHIDX - DPPI channel that event EDSTOPPED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_CCAIDLE - Publish configuration for event CCAIDLE - 0x1C4 - read-write - - - CHIDX - DPPI channel that event CCAIDLE will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_CCABUSY - Publish configuration for event CCABUSY - 0x1C8 - read-write - - - CHIDX - DPPI channel that event CCABUSY will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_CCASTOPPED - Publish configuration for event CCASTOPPED - 0x1CC - read-write - - - CHIDX - DPPI channel that event CCASTOPPED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_RATEBOOST - Publish configuration for event RATEBOOST - 0x1D0 - read-write - - - CHIDX - DPPI channel that event RATEBOOST will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_TXREADY - Publish configuration for event TXREADY - 0x1D4 - read-write - - - CHIDX - DPPI channel that event TXREADY will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_RXREADY - Publish configuration for event RXREADY - 0x1D8 - read-write - - - CHIDX - DPPI channel that event RXREADY will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_MHRMATCH - Publish configuration for event MHRMATCH - 0x1DC - read-write - - - CHIDX - DPPI channel that event MHRMATCH will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_SYNC - Publish configuration for event SYNC - 0x1E8 - read-write - - - CHIDX - DPPI channel that event SYNC will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_PHYEND - Publish configuration for event PHYEND - 0x1EC - read-write - - - CHIDX - DPPI channel that event PHYEND will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_CTEPRESENT - Publish configuration for event CTEPRESENT - 0x1F0 - read-write - - - CHIDX - DPPI channel that event CTEPRESENT will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - SHORTS - Shortcuts between local events and tasks - 0x200 - read-write - - - READY_START - Shortcut between event READY and task START - 0 - 0 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - END_DISABLE - Shortcut between event END and task DISABLE - 1 - 1 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - DISABLED_TXEN - Shortcut between event DISABLED and task TXEN - 2 - 2 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - DISABLED_RXEN - Shortcut between event DISABLED and task RXEN - 3 - 3 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - ADDRESS_RSSISTART - Shortcut between event ADDRESS and task RSSISTART - 4 - 4 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - END_START - Shortcut between event END and task START - 5 - 5 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - ADDRESS_BCSTART - Shortcut between event ADDRESS and task BCSTART - 6 - 6 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - DISABLED_RSSISTOP - Shortcut between event DISABLED and task RSSISTOP - 8 - 8 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - RXREADY_CCASTART - Shortcut between event RXREADY and task CCASTART - 11 - 11 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - CCAIDLE_TXEN - Shortcut between event CCAIDLE and task TXEN - 12 - 12 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - CCABUSY_DISABLE - Shortcut between event CCABUSY and task DISABLE - 13 - 13 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - FRAMESTART_BCSTART - Shortcut between event FRAMESTART and task BCSTART - 14 - 14 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - READY_EDSTART - Shortcut between event READY and task EDSTART - 15 - 15 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - EDEND_DISABLE - Shortcut between event EDEND and task DISABLE - 16 - 16 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - CCAIDLE_STOP - Shortcut between event CCAIDLE and task STOP - 17 - 17 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - TXREADY_START - Shortcut between event TXREADY and task START - 18 - 18 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - RXREADY_START - Shortcut between event RXREADY and task START - 19 - 19 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - PHYEND_DISABLE - Shortcut between event PHYEND and task DISABLE - 20 - 20 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - PHYEND_START - Shortcut between event PHYEND and task START - 21 - 21 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - READY - Write '1' to enable interrupt for event READY - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ADDRESS - Write '1' to enable interrupt for event ADDRESS - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - PAYLOAD - Write '1' to enable interrupt for event PAYLOAD - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - END - Write '1' to enable interrupt for event END - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - DISABLED - Write '1' to enable interrupt for event DISABLED - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - DEVMATCH - Write '1' to enable interrupt for event DEVMATCH - 5 - 5 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - DEVMISS - Write '1' to enable interrupt for event DEVMISS - 6 - 6 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RSSIEND - Write '1' to enable interrupt for event RSSIEND - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - BCMATCH - Write '1' to enable interrupt for event BCMATCH - 10 - 10 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CRCOK - Write '1' to enable interrupt for event CRCOK - 12 - 12 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CRCERROR - Write '1' to enable interrupt for event CRCERROR - 13 - 13 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - FRAMESTART - Write '1' to enable interrupt for event FRAMESTART - 14 - 14 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - EDEND - Write '1' to enable interrupt for event EDEND - 15 - 15 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - EDSTOPPED - Write '1' to enable interrupt for event EDSTOPPED - 16 - 16 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CCAIDLE - Write '1' to enable interrupt for event CCAIDLE - 17 - 17 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CCABUSY - Write '1' to enable interrupt for event CCABUSY - 18 - 18 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CCASTOPPED - Write '1' to enable interrupt for event CCASTOPPED - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RATEBOOST - Write '1' to enable interrupt for event RATEBOOST - 20 - 20 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TXREADY - Write '1' to enable interrupt for event TXREADY - 21 - 21 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RXREADY - Write '1' to enable interrupt for event RXREADY - 22 - 22 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - MHRMATCH - Write '1' to enable interrupt for event MHRMATCH - 23 - 23 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - SYNC - Write '1' to enable interrupt for event SYNC - 26 - 26 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - PHYEND - Write '1' to enable interrupt for event PHYEND - 27 - 27 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CTEPRESENT - Write '1' to enable interrupt for event CTEPRESENT - 28 - 28 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - READY - Write '1' to disable interrupt for event READY - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ADDRESS - Write '1' to disable interrupt for event ADDRESS - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - PAYLOAD - Write '1' to disable interrupt for event PAYLOAD - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - END - Write '1' to disable interrupt for event END - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - DISABLED - Write '1' to disable interrupt for event DISABLED - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - DEVMATCH - Write '1' to disable interrupt for event DEVMATCH - 5 - 5 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - DEVMISS - Write '1' to disable interrupt for event DEVMISS - 6 - 6 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RSSIEND - Write '1' to disable interrupt for event RSSIEND - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - BCMATCH - Write '1' to disable interrupt for event BCMATCH - 10 - 10 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CRCOK - Write '1' to disable interrupt for event CRCOK - 12 - 12 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CRCERROR - Write '1' to disable interrupt for event CRCERROR - 13 - 13 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - FRAMESTART - Write '1' to disable interrupt for event FRAMESTART - 14 - 14 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - EDEND - Write '1' to disable interrupt for event EDEND - 15 - 15 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - EDSTOPPED - Write '1' to disable interrupt for event EDSTOPPED - 16 - 16 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CCAIDLE - Write '1' to disable interrupt for event CCAIDLE - 17 - 17 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CCABUSY - Write '1' to disable interrupt for event CCABUSY - 18 - 18 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CCASTOPPED - Write '1' to disable interrupt for event CCASTOPPED - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RATEBOOST - Write '1' to disable interrupt for event RATEBOOST - 20 - 20 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TXREADY - Write '1' to disable interrupt for event TXREADY - 21 - 21 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RXREADY - Write '1' to disable interrupt for event RXREADY - 22 - 22 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - MHRMATCH - Write '1' to disable interrupt for event MHRMATCH - 23 - 23 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - SYNC - Write '1' to disable interrupt for event SYNC - 26 - 26 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - PHYEND - Write '1' to disable interrupt for event PHYEND - 27 - 27 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CTEPRESENT - Write '1' to disable interrupt for event CTEPRESENT - 28 - 28 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - CRCSTATUS - CRC status - 0x400 - read-only - - - CRCSTATUS - CRC status of packet received - 0 - 0 - - - CRCError - Packet received with CRC error - 0 - - - CRCOk - Packet received with CRC ok - 1 - - - - - - - RXMATCH - Received address - 0x408 - read-only - - - RXMATCH - Received address - 0 - 2 - - - - - RXCRC - CRC field of previously received packet - 0x40C - read-only - - - RXCRC - CRC field of previously received packet - 0 - 23 - - - - - DAI - Device address match index - 0x410 - read-only - - - DAI - Device address match index - 0 - 2 - - - - - PDUSTAT - Payload status - 0x414 - read-only - - - PDUSTAT - Status on payload length vs. PCNF1.MAXLEN - 0 - 0 - - - LessThan - Payload less than PCNF1.MAXLEN - 0 - - - GreaterThan - Payload greater than PCNF1.MAXLEN - 1 - - - - - CISTAT - Status on what rate packet is received with in Long Range - 1 - 2 - - - LR125kbit - Frame is received at 125 kbps - 0 - - - LR500kbit - Frame is received at 500 kbps - 1 - - - - - - - CTESTATUS - CTEInfo parsed from received packet - 0x44C - read-only - - - CTETIME - CTETime parsed from packet - 0 - 4 - - - RFU - RFU parsed from packet - 5 - 5 - - - CTETYPE - CTEType parsed from packet - 6 - 7 - - - - - DFESTATUS - DFE status information - 0x458 - read-only - - - SWITCHINGSTATE - Internal state of switching state machine - 0 - 2 - - - Idle - Switching state Idle - 0 - - - Offset - Switching state Offset - 1 - - - Guard - Switching state Guard - 2 - - - Ref - Switching state Ref - 3 - - - Switching - Switching state Switching - 4 - - - Ending - Switching state Ending - 5 - - - - - SAMPLINGSTATE - Internal state of sampling state machine - 4 - 4 - - - Idle - Sampling state Idle - 0 - - - Sampling - Sampling state Sampling - 1 - - - - - - - PACKETPTR - Packet pointer - 0x504 - read-write - 0x01000000 - - - PACKETPTR - Packet pointer - 0 - 31 - - - - - FREQUENCY - Frequency - 0x508 - read-write - 0x00000002 - - - FREQUENCY - Radio channel frequency - 0 - 6 - - - MAP - Channel map selection - 8 - 8 - - - Default - Channel map between 2400 MHz and 2500 MHz - 0 - - - Low - Channel map between 2360 MHz and 2460 MHz - 1 - - - - - - - TXPOWER - Output power - 0x50C - read-write - - - TXPOWER - RADIO output power - 0 - 7 - - - 0dBm - 0 dBm - 0x0 - - - Neg1dBm - -1 dBm - 0xFF - - - Neg2dBm - -2 dBm - 0xFE - - - Neg3dBm - -3 dBm - 0xFD - - - Neg4dBm - -4 dBm - 0xFC - - - Neg5dBm - -5 dBm - 0xFB - - - Neg6dBm - -6 dBm - 0xFA - - - Neg7dBm - -7 dBm - 0xF9 - - - Neg8dBm - -8 dBm - 0xF8 - - - Neg12dBm - -12 dBm - 0xF4 - - - Neg16dBm - -16 dBm - 0xF0 - - - Neg20dBm - -20 dBm - 0xEC - - - Neg30dBm - Deprecated enumerator - -40 dBm - 0xE2 - - - Neg40dBm - -40 dBm - 0xD8 - - - - - - - MODE - Data rate and modulation - 0x510 - read-write - - - MODE - Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation. - 0 - 3 - - - Nrf_1Mbit - 1 Mbps Nordic proprietary radio mode - 0 - - - Nrf_2Mbit - 2 Mbps Nordic proprietary radio mode - 1 - - - Ble_1Mbit - 1 Mbps BLE - 3 - - - Ble_2Mbit - 2 Mbps BLE - 4 - - - Ble_LR125Kbit - Long Range 125 kbps TX, 125 kbps and 500 kbps RX - 5 - - - Ble_LR500Kbit - Long Range 500 kbps TX, 125 kbps and 500 kbps RX - 6 - - - Ieee802154_250Kbit - IEEE 802.15.4-2006 250 kbps - 15 - - - - - - - PCNF0 - Packet configuration register 0 - 0x514 - read-write - - - LFLEN - Length on air of LENGTH field in number of bits - 0 - 3 - - - S0LEN - Length on air of S0 field in number of bytes - 8 - 8 - - - S1LEN - Length on air of S1 field in number of bits - 16 - 19 - - - S1INCL - Include or exclude S1 field in RAM - 20 - 20 - - - Automatic - Include S1 field in RAM only if S1LEN &gt; 0 - 0 - - - Include - Always include S1 field in RAM independent of S1LEN - 1 - - - - - CILEN - Length of code indicator - Long Range - 22 - 23 - - - PLEN - Length of preamble on air. Decision point: TASKS_START task - 24 - 25 - - - 8bit - 8-bit preamble - 0 - - - 16bit - 16-bit preamble - 1 - - - 32bitZero - 32-bit zero preamble - used for IEEE 802.15.4 - 2 - - - LongRange - Preamble - used for Bluetooth LE Long Range - 3 - - - - - CRCINC - Indicates if LENGTH field contains CRC or not - 26 - 26 - - - Exclude - LENGTH does not contain CRC - 0 - - - Include - LENGTH includes CRC - 1 - - - - - TERMLEN - Length of TERM field in Long Range operation - 29 - 30 - - - - - PCNF1 - Packet configuration register 1 - 0x518 - read-write - - - MAXLEN - Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. - 0 - 7 - - - STATLEN - Static length in number of bytes - 8 - 15 - - - BALEN - Base address length in number of bytes - 16 - 18 - - - ENDIAN - On-air endianness of packet, this applies to the S0, LENGTH, S1, and the PAYLOAD fields. - 24 - 24 - - - Little - Least significant bit on air first - 0 - - - Big - Most significant bit on air first - 1 - - - - - WHITEEN - Enable or disable packet whitening - 25 - 25 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - BASE0 - Base address 0 - 0x51C - read-write - - - BASE0 - Base address 0 - 0 - 31 - - - - - BASE1 - Base address 1 - 0x520 - read-write - - - BASE1 - Base address 1 - 0 - 31 - - - - - PREFIX0 - Prefixes bytes for logical addresses 0-3 - 0x524 - read-write - - - AP0 - Address prefix 0. - 0 - 7 - - - AP1 - Address prefix 1. - 8 - 15 - - - AP2 - Address prefix 2. - 16 - 23 - - - AP3 - Address prefix 3. - 24 - 31 - - - - - PREFIX1 - Prefixes bytes for logical addresses 4-7 - 0x528 - read-write - - - AP4 - Address prefix 4. - 0 - 7 - - - AP5 - Address prefix 5. - 8 - 15 - - - AP6 - Address prefix 6. - 16 - 23 - - - AP7 - Address prefix 7. - 24 - 31 - - - - - TXADDRESS - Transmit address select - 0x52C - read-write - - - TXADDRESS - Transmit address select - 0 - 2 - - - - - RXADDRESSES - Receive address select - 0x530 - read-write - - - ADDR0 - Enable or disable reception on logical address 0. - 0 - 0 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ADDR1 - Enable or disable reception on logical address 1. - 1 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ADDR2 - Enable or disable reception on logical address 2. - 2 - 2 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ADDR3 - Enable or disable reception on logical address 3. - 3 - 3 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ADDR4 - Enable or disable reception on logical address 4. - 4 - 4 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ADDR5 - Enable or disable reception on logical address 5. - 5 - 5 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ADDR6 - Enable or disable reception on logical address 6. - 6 - 6 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ADDR7 - Enable or disable reception on logical address 7. - 7 - 7 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - CRCCNF - CRC configuration - 0x534 - read-write - - - LEN - CRC length in number of bytes For MODE Ble_LR125Kbit and Ble_LR500Kbit, only LEN set to 3 is supported - 0 - 1 - - - Disabled - CRC length is zero and CRC calculation is disabled - 0 - - - One - CRC length is one byte and CRC calculation is enabled - 1 - - - Two - CRC length is two bytes and CRC calculation is enabled - 2 - - - Three - CRC length is three bytes and CRC calculation is enabled - 3 - - - - - SKIPADDR - Include or exclude packet address field out of CRC calculation. - 8 - 9 - - - Include - CRC calculation includes address field - 0 - - - Skip - CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. - 1 - - - Ieee802154 - CRC calculation as per 802.15.4 standard. Starting at first byte after length field. - 2 - - - - - - - CRCPOLY - CRC polynomial - 0x538 - read-write - 0x00000000 - - - CRCPOLY - CRC polynomial - 0 - 23 - - - - - CRCINIT - CRC initial value - 0x53C - read-write - - - CRCINIT - CRC initial value - 0 - 23 - - - - - TIFS - Interframe spacing in us - 0x544 - read-write - - - TIFS - Interframe spacing in us. - 0 - 9 - - - - - RSSISAMPLE - RSSI sample - 0x548 - read-only - - - RSSISAMPLE - RSSI sample. - 0 - 6 - - - - - STATE - Current radio state - 0x550 - read-only - - - STATE - Current radio state - 0 - 3 - - - Disabled - RADIO is in the Disabled state - 0 - - - RxRu - RADIO is in the RXRU state - 1 - - - RxIdle - RADIO is in the RXIDLE state - 2 - - - Rx - RADIO is in the RX state - 3 - - - RxDisable - RADIO is in the RXDISABLED state - 4 - - - TxRu - RADIO is in the TXRU state - 9 - - - TxIdle - RADIO is in the TXIDLE state - 10 - - - Tx - RADIO is in the TX state - 11 - - - TxDisable - RADIO is in the TXDISABLED state - 12 - - - - - - - DATAWHITEIV - Data whitening initial value - 0x554 - read-write - 0x00000040 - - - DATAWHITEIV - Data whitening initial value. Bit 6 is hardwired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. - 0 - 6 - - - - - BCC - Bit counter compare - 0x560 - read-write - - - BCC - Bit counter compare - 0 - 31 - - - - - 0x8 - 0x4 - DAB[%s] - Description collection: Device address base segment n - 0x600 - read-write - - - DAB - Device address base segment n - 0 - 31 - - - - - 0x8 - 0x4 - DAP[%s] - Description collection: Device address prefix n - 0x620 - read-write - - - DAP - Device address prefix n - 0 - 15 - - - - - DACNF - Device address match configuration - 0x640 - read-write - - - ENA0 - Enable or disable device address matching using device address 0 - 0 - 0 - - - Disabled - Disabled - 0 - - - Enabled - Enabled - 1 - - - - - ENA1 - Enable or disable device address matching using device address 1 - 1 - 1 - - - Disabled - Disabled - 0 - - - Enabled - Enabled - 1 - - - - - ENA2 - Enable or disable device address matching using device address 2 - 2 - 2 - - - Disabled - Disabled - 0 - - - Enabled - Enabled - 1 - - - - - ENA3 - Enable or disable device address matching using device address 3 - 3 - 3 - - - Disabled - Disabled - 0 - - - Enabled - Enabled - 1 - - - - - ENA4 - Enable or disable device address matching using device address 4 - 4 - 4 - - - Disabled - Disabled - 0 - - - Enabled - Enabled - 1 - - - - - ENA5 - Enable or disable device address matching using device address 5 - 5 - 5 - - - Disabled - Disabled - 0 - - - Enabled - Enabled - 1 - - - - - ENA6 - Enable or disable device address matching using device address 6 - 6 - 6 - - - Disabled - Disabled - 0 - - - Enabled - Enabled - 1 - - - - - ENA7 - Enable or disable device address matching using device address 7 - 7 - 7 - - - Disabled - Disabled - 0 - - - Enabled - Enabled - 1 - - - - - TXADD0 - TxAdd for device address 0 - 8 - 8 - - - TXADD1 - TxAdd for device address 1 - 9 - 9 - - - TXADD2 - TxAdd for device address 2 - 10 - 10 - - - TXADD3 - TxAdd for device address 3 - 11 - 11 - - - TXADD4 - TxAdd for device address 4 - 12 - 12 - - - TXADD5 - TxAdd for device address 5 - 13 - 13 - - - TXADD6 - TxAdd for device address 6 - 14 - 14 - - - TXADD7 - TxAdd for device address 7 - 15 - 15 - - - - - MHRMATCHCONF - Search pattern configuration - 0x644 - read-write - - - MHRMATCHCONF - Search pattern configuration - 0 - 31 - - - - - MHRMATCHMAS - Pattern mask - 0x648 - read-write - - - MHRMATCHMAS - Pattern mask - 0 - 31 - - - - - MODECNF0 - Radio mode configuration register 0 - 0x650 - read-write - 0x00000200 - - - RU - Radio ramp-up time - 0 - 0 - - - Default - Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51 - 0 - - - Fast - Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specifications for more information - 1 - - - - - DTX - Default TX value - 8 - 9 - - - B1 - Transmit '1' - 0 - - - B0 - Transmit '0' - 1 - - - Center - Transmit center frequency - 2 - - - - - - - SFD - IEEE 802.15.4 start of frame delimiter - 0x660 - read-write - 0x000000A7 - - - SFD - IEEE 802.15.4 start of frame delimiter - 0 - 7 - - - - - EDCNT - IEEE 802.15.4 energy detect loop count - 0x664 - read-write - 0x00000000 - - - EDCNT - IEEE 802.15.4 energy detect loop count - 0 - 20 - - - - - EDSAMPLE - IEEE 802.15.4 energy detect level - 0x668 - read-only - 0x00000000 - - - EDLVL - IEEE 802.15.4 energy detect level - 0 - 7 - - - - - CCACTRL - IEEE 802.15.4 clear channel assessment control - 0x66C - read-write - 0x052D0000 - - - CCAMODE - CCA mode of operation - 0 - 2 - - - EdMode - Energy above threshold - 0 - - - CarrierMode - Carrier seen - 1 - - - CarrierAndEdMode - Energy above threshold AND carrier seen - 2 - - - CarrierOrEdMode - Energy above threshold OR carrier seen - 3 - - - EdModeTest1 - Energy above threshold test mode that will abort when first ED measurement over threshold is seen. No averaging. - 4 - - - - - CCAEDTHRES - CCA energy busy threshold. Used in all the CCA modes except CarrierMode. - 8 - 15 - - - CCACORRTHRES - CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode, and CarrierOrEdMode. - 16 - 23 - - - CCACORRCNT - Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect is enabled. - 24 - 31 - - - - - DFEMODE - Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure (AOD) - 0x900 - read-write - 0x00000000 - - - DFEOPMODE - Direction finding operation mode - 0 - 1 - - - Disabled - Direction finding mode disabled - 0 - - - AoD - Direction finding mode set to AoD - 2 - - - AoA - Direction finding mode set to AoA - 3 - - - - - - - CTEINLINECONF - Configuration for CTE inline mode - 0x904 - read-write - 0x00002800 - - - CTEINLINECTRLEN - Enable parsing of CTEInfo from received packet in BLE modes - 0 - 0 - - - Enabled - Parsing of CTEInfo is enabled - 1 - - - Disabled - Parsing of CTEInfo is disabled - 0 - - - - - CTEINFOINS1 - CTEInfo is S1 byte or not - 3 - 3 - - - InS1 - CTEInfo is in S1 byte (data PDU) - 1 - - - NotInS1 - CTEInfo is NOT in S1 byte (advertising PDU) - 0 - - - - - CTEERRORHANDLING - Sampling/switching if CRC is not OK - 4 - 4 - - - Yes - Sampling and antenna switching also when CRC is not OK - 1 - - - No - No sampling and antenna switching when CRC is not OK - 0 - - - - - CTETIMEVALIDRANGE - Max range of CTETime - 6 - 7 - - - 20 - 20 in 8 us unit (default) Set to 20 if parsed CTETime is larger than 20 - 0 - - - 31 - 31 in 8 us unit - 1 - - - 63 - 63 in 8 us unit - 2 - - - - - CTEINLINERXMODE1US - Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set. - 10 - 12 - - - 4us - 4 us - 1 - - - 2us - 2 us - 2 - - - 1us - 1 us - 3 - - - 500ns - 0.5 us - 4 - - - 250ns - 0.25 us - 5 - - - 125ns - 0.125 us - 6 - - - - - CTEINLINERXMODE2US - Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set. - 13 - 15 - - - 4us - 4 us - 1 - - - 2us - 2 us - 2 - - - 1us - 1 us - 3 - - - 500ns - 0.5 us - 4 - - - 250ns - 0.25 us - 5 - - - 125ns - 0.125 us - 6 - - - - - S0CONF - S0 bit pattern to match - 16 - 23 - - - S0MASK - S0 bit mask to set which bit to match - 24 - 31 - - - - - DFECTRL1 - Various configuration for Direction finding - 0x910 - read-write - 0x00023282 - - - NUMBEROF8US - Length of the AoA/AoD procedure in number of 8 us units - 0 - 5 - - - DFEINEXTENSION - Add CTE extension and do antenna switching/sampling in this extension - 7 - 7 - - - CRC - AoA/AoD procedure triggered at end of CRC - 1 - - - Payload - Antenna switching/sampling is done in the packet payload - 0 - - - - - TSWITCHSPACING - Interval between every time the antenna is changed in the SWITCHING state - 8 - 10 - - - 4us - 4 us - 1 - - - 2us - 2 us - 2 - - - 1us - 1 us - 3 - - - - - TSAMPLESPACINGREF - Interval between samples in the REFERENCE period - 12 - 14 - - - 4us - 4 us - 1 - - - 2us - 2 us - 2 - - - 1us - 1 us - 3 - - - 500ns - 0.5 us - 4 - - - 250ns - 0.25 us - 5 - - - 125ns - 0.125 us - 6 - - - - - SAMPLETYPE - Whether to sample I/Q or magnitude/phase - 15 - 15 - - - IQ - Complex samples in I and Q - 0 - - - MagPhase - Complex samples as magnitude and phase - 1 - - - - - TSAMPLESPACING - Interval between samples in the SWITCHING period when CTEINLINECTRLEN is 0 - 16 - 18 - - - 4us - 4 us - 1 - - - 2us - 2 us - 2 - - - 1us - 1 us - 3 - - - 500ns - 0.5 us - 4 - - - 250ns - 0.25 us - 5 - - - 125ns - 0.125 us - 6 - - - - - REPEATPATTERN - Repeat each individual antenna pattern N times sequentially, i.e. P0, P0, P1, P1, P2, P2, P3, P3, etc. - 20 - 23 - - - NoRepeat - Do not repeat (1 time in total) - 0 - - - - - AGCBACKOFFGAIN - Gain will be lowered by the specified number of gain steps at the start of CTE - 24 - 27 - - - - - DFECTRL2 - Start offset for Direction finding - 0x914 - read-write - 0x00000000 - - - TSWITCHOFFSET - Signed value offset after the end of the CRC before starting switching in number of 16 MHz clock cycles - 0 - 12 - - - TSAMPLEOFFSET - Signed value offset in number of 16 MHz clock cycles for fine tuning of the sampling instant for all IQ samples. With TSAMPLEOFFSET=0 the first sample is taken immediately at the start of the reference period - 16 - 27 - - - - - SWITCHPATTERN - GPIO patterns to be used for each antenna - 0x928 - read-write - 0x00000000 - - - SWITCHPATTERN - Fill array of GPIO patterns for antenna control. - 0 - 7 - - - - - CLEARPATTERN - Clear the GPIO pattern array for antenna control - 0x92C - read-write - - - CLEARPATTERN - Clears GPIO pattern array for antenna control - 0 - 0 - oneToClear - - - Clear - Clear the GPIO pattern - 1 - - - - - - - PSEL - Unspecified - RADIO_PSEL - read-write - 0x930 - - 0x8 - 0x4 - DFEGPIO[%s] - Description collection: Pin select for DFE pin n - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - DFEPACKET - DFE packet EasyDMA channel - RADIO_DFEPACKET - read-write - 0x950 - - PTR - Data pointer - 0x000 - read-write - 0x01000000 - - - PTR - Data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of buffer words to transfer - 0x004 - read-write - 0x00001000 - - - MAXCNT - Maximum number of buffer words to transfer - 0 - 13 - - - - - AMOUNT - Number of samples transferred in the last transaction - 0x008 - read-only - - - AMOUNT - Number of samples transferred in the last transaction - 0 - 15 - - - - - - POWER - Peripheral power control - 0xFFC - read-write - 0x00000001 - - - POWER - Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. - 0 - 0 - - - Disabled - Peripheral is powered off - 0 - - - Enabled - Peripheral is powered on - 1 - - - - - - - - - RNG_NS - Random Number Generator - 0x41009000 - RNG - - - - 0 - 0x1000 - registers - - - RNG - 9 - - RNG - 0x20 - - - TASKS_START - Task starting the random number generator - 0x000 - write-only - - - TASKS_START - Task starting the random number generator - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STOP - Task stopping the random number generator - 0x004 - write-only - - - TASKS_STOP - Task stopping the random number generator - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - SUBSCRIBE_START - Subscribe configuration for task START - 0x080 - read-write - - - CHIDX - DPPI channel that task START will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_STOP - Subscribe configuration for task STOP - 0x084 - read-write - - - CHIDX - DPPI channel that task STOP will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - EVENTS_VALRDY - Event being generated for every new random number written to the VALUE register - 0x100 - read-write - - - EVENTS_VALRDY - Event being generated for every new random number written to the VALUE register - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - PUBLISH_VALRDY - Publish configuration for event VALRDY - 0x180 - read-write - - - CHIDX - DPPI channel that event VALRDY will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - SHORTS - Shortcuts between local events and tasks - 0x200 - read-write - - - VALRDY_STOP - Shortcut between event VALRDY and task STOP - 0 - 0 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - VALRDY - Write '1' to enable interrupt for event VALRDY - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - VALRDY - Write '1' to disable interrupt for event VALRDY - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - CONFIG - Configuration register - 0x504 - read-write - - - DERCEN - Bias correction - 0 - 0 - - - Disabled - Disabled - 0 - - - Enabled - Enabled - 1 - - - - - - - VALUE - Output random number - 0x508 - read-only - - - VALUE - Generated random number - 0 - 7 - - - - - - - GPIOTE_NS - GPIO Tasks and Events - 0x4100A000 - GPIOTE - - - - 0 - 0x1000 - registers - - - GPIOTE - 10 - - GPIOTE - 0x20 - - - 0x8 - 0x4 - TASKS_OUT[%s] - Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. - 0x000 - write-only - - - TASKS_OUT - Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - 0x8 - 0x4 - TASKS_SET[%s] - Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. - 0x030 - write-only - - - TASKS_SET - Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - 0x8 - 0x4 - TASKS_CLR[%s] - Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. - 0x060 - write-only - - - TASKS_CLR - Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - 0x8 - 0x4 - SUBSCRIBE_OUT[%s] - Description collection: Subscribe configuration for task OUT[n] - 0x080 - read-write - - - CHIDX - DPPI channel that task OUT[n] will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - 0x8 - 0x4 - SUBSCRIBE_SET[%s] - Description collection: Subscribe configuration for task SET[n] - 0x0B0 - read-write - - - CHIDX - DPPI channel that task SET[n] will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - 0x8 - 0x4 - SUBSCRIBE_CLR[%s] - Description collection: Subscribe configuration for task CLR[n] - 0x0E0 - read-write - - - CHIDX - DPPI channel that task CLR[n] will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - 0x8 - 0x4 - EVENTS_IN[%s] - Description collection: Event generated from pin specified in CONFIG[n].PSEL - 0x100 - read-write - - - EVENTS_IN - Event generated from pin specified in CONFIG[n].PSEL - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_PORT - Event generated from multiple input GPIO pins with SENSE mechanism enabled - 0x17C - read-write - - - EVENTS_PORT - Event generated from multiple input GPIO pins with SENSE mechanism enabled - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - 0x8 - 0x4 - PUBLISH_IN[%s] - Description collection: Publish configuration for event IN[n] - 0x180 - read-write - - - CHIDX - DPPI channel that event IN[n] will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_PORT - Publish configuration for event PORT - 0x1FC - read-write - - - CHIDX - DPPI channel that event PORT will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - IN0 - Write '1' to enable interrupt for event IN[0] - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - IN1 - Write '1' to enable interrupt for event IN[1] - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - IN2 - Write '1' to enable interrupt for event IN[2] - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - IN3 - Write '1' to enable interrupt for event IN[3] - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - IN4 - Write '1' to enable interrupt for event IN[4] - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - IN5 - Write '1' to enable interrupt for event IN[5] - 5 - 5 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - IN6 - Write '1' to enable interrupt for event IN[6] - 6 - 6 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - IN7 - Write '1' to enable interrupt for event IN[7] - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - PORT - Write '1' to enable interrupt for event PORT - 31 - 31 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - IN0 - Write '1' to disable interrupt for event IN[0] - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - IN1 - Write '1' to disable interrupt for event IN[1] - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - IN2 - Write '1' to disable interrupt for event IN[2] - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - IN3 - Write '1' to disable interrupt for event IN[3] - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - IN4 - Write '1' to disable interrupt for event IN[4] - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - IN5 - Write '1' to disable interrupt for event IN[5] - 5 - 5 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - IN6 - Write '1' to disable interrupt for event IN[6] - 6 - 6 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - IN7 - Write '1' to disable interrupt for event IN[7] - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - PORT - Write '1' to disable interrupt for event PORT - 31 - 31 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - LATENCY - Latency selection for Event mode (MODE=Event) with rising or falling edge detection on the pin. - 0x504 - read-write - 0x00000001 - - - LATENCY - Latency setting - 0 - 0 - - - LowPower - Low power setting, for signals with minimum hold time tGPIOTE,HOLD,LP; refer to Electrical specification section - 0 - - - LowLatency - Low latency setting, for signals with minimum hold time tGPIOTE,HOLD,LL; refer to Electrical specification section - 1 - - - - - - - 0x8 - 0x4 - CONFIG[%s] - Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event - 0x510 - read-write - - - MODE - Mode - 0 - 1 - - - Disabled - Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. - 0 - - - Event - Event mode - 1 - - - Task - Task mode - 3 - - - - - PSEL - GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event - 8 - 12 - - - PORT - Port number - 13 - 13 - - - POLARITY - When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. - 16 - 17 - - - None - Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. - 0 - - - LoToHi - Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. - 1 - - - HiToLo - Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. - 2 - - - Toggle - Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. - 3 - - - - - OUTINIT - When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. - 20 - 20 - - - Low - Task mode: Initial value of pin before task triggering is low - 0 - - - High - Task mode: Initial value of pin before task triggering is high - 1 - - - - - - - - - WDT_NS - Watchdog Timer - 0x4100B000 - WDT - - - - 0 - 0x1000 - registers - - - WDT - 11 - - WDT - 0x20 - - - TASKS_START - Start WDT - 0x000 - write-only - - - TASKS_START - Start WDT - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STOP - Stop WDT - 0x004 - write-only - - - TASKS_STOP - Stop WDT - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - SUBSCRIBE_START - Subscribe configuration for task START - 0x080 - read-write - - - CHIDX - DPPI channel that task START will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_STOP - Subscribe configuration for task STOP - 0x084 - read-write - - - CHIDX - DPPI channel that task STOP will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - EVENTS_TIMEOUT - Watchdog timeout - 0x100 - read-write - - - EVENTS_TIMEOUT - Watchdog timeout - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_STOPPED - Watchdog stopped - 0x104 - read-write - - - EVENTS_STOPPED - Watchdog stopped - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - PUBLISH_TIMEOUT - Publish configuration for event TIMEOUT - 0x180 - read-write - - - CHIDX - DPPI channel that event TIMEOUT will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_STOPPED - Publish configuration for event STOPPED - 0x184 - read-write - - - CHIDX - DPPI channel that event STOPPED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - TIMEOUT - Write '1' to enable interrupt for event TIMEOUT - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - STOPPED - Write '1' to enable interrupt for event STOPPED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - TIMEOUT - Write '1' to disable interrupt for event TIMEOUT - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - STOPPED - Write '1' to disable interrupt for event STOPPED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - NMIENSET - Enable interrupt - 0x324 - read-write - - - TIMEOUT - Write '1' to enable interrupt for event TIMEOUT - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - STOPPED - Write '1' to enable interrupt for event STOPPED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - NMIENCLR - Disable interrupt - 0x328 - read-write - - - TIMEOUT - Write '1' to disable interrupt for event TIMEOUT - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - STOPPED - Write '1' to disable interrupt for event STOPPED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - RUNSTATUS - Run status - 0x400 - read-only - - - RUNSTATUSWDT - Indicates whether or not WDT is running - 0 - 0 - - - NotRunning - Watchdog is not running - 0 - - - Running - Watchdog is running - 1 - - - - - - - REQSTATUS - Request status - 0x404 - read-only - 0x00000001 - - - RR0 - Request status for RR[0] register - 0 - 0 - - - DisabledOrRequested - RR[0] register is not enabled, or are already requesting reload - 0 - - - EnabledAndUnrequested - RR[0] register is enabled, and are not yet requesting reload - 1 - - - - - RR1 - Request status for RR[1] register - 1 - 1 - - - DisabledOrRequested - RR[1] register is not enabled, or are already requesting reload - 0 - - - EnabledAndUnrequested - RR[1] register is enabled, and are not yet requesting reload - 1 - - - - - RR2 - Request status for RR[2] register - 2 - 2 - - - DisabledOrRequested - RR[2] register is not enabled, or are already requesting reload - 0 - - - EnabledAndUnrequested - RR[2] register is enabled, and are not yet requesting reload - 1 - - - - - RR3 - Request status for RR[3] register - 3 - 3 - - - DisabledOrRequested - RR[3] register is not enabled, or are already requesting reload - 0 - - - EnabledAndUnrequested - RR[3] register is enabled, and are not yet requesting reload - 1 - - - - - RR4 - Request status for RR[4] register - 4 - 4 - - - DisabledOrRequested - RR[4] register is not enabled, or are already requesting reload - 0 - - - EnabledAndUnrequested - RR[4] register is enabled, and are not yet requesting reload - 1 - - - - - RR5 - Request status for RR[5] register - 5 - 5 - - - DisabledOrRequested - RR[5] register is not enabled, or are already requesting reload - 0 - - - EnabledAndUnrequested - RR[5] register is enabled, and are not yet requesting reload - 1 - - - - - RR6 - Request status for RR[6] register - 6 - 6 - - - DisabledOrRequested - RR[6] register is not enabled, or are already requesting reload - 0 - - - EnabledAndUnrequested - RR[6] register is enabled, and are not yet requesting reload - 1 - - - - - RR7 - Request status for RR[7] register - 7 - 7 - - - DisabledOrRequested - RR[7] register is not enabled, or are already requesting reload - 0 - - - EnabledAndUnrequested - RR[7] register is enabled, and are not yet requesting reload - 1 - - - - - - - CRV - Counter reload value - 0x504 - read-write - 0xFFFFFFFF - - - CRV - Counter reload value in number of cycles of the 32.768 kHz clock - 0 - 31 - - - - - RREN - Enable register for reload request registers - 0x508 - read-write - 0x00000001 - - - RR0 - Enable or disable RR[0] register - 0 - 0 - - - Disabled - Disable RR[0] register - 0 - - - Enabled - Enable RR[0] register - 1 - - - - - RR1 - Enable or disable RR[1] register - 1 - 1 - - - Disabled - Disable RR[1] register - 0 - - - Enabled - Enable RR[1] register - 1 - - - - - RR2 - Enable or disable RR[2] register - 2 - 2 - - - Disabled - Disable RR[2] register - 0 - - - Enabled - Enable RR[2] register - 1 - - - - - RR3 - Enable or disable RR[3] register - 3 - 3 - - - Disabled - Disable RR[3] register - 0 - - - Enabled - Enable RR[3] register - 1 - - - - - RR4 - Enable or disable RR[4] register - 4 - 4 - - - Disabled - Disable RR[4] register - 0 - - - Enabled - Enable RR[4] register - 1 - - - - - RR5 - Enable or disable RR[5] register - 5 - 5 - - - Disabled - Disable RR[5] register - 0 - - - Enabled - Enable RR[5] register - 1 - - - - - RR6 - Enable or disable RR[6] register - 6 - 6 - - - Disabled - Disable RR[6] register - 0 - - - Enabled - Enable RR[6] register - 1 - - - - - RR7 - Enable or disable RR[7] register - 7 - 7 - - - Disabled - Disable RR[7] register - 0 - - - Enabled - Enable RR[7] register - 1 - - - - - - - CONFIG - Configuration register - 0x50C - read-write - 0x00000001 - - - SLEEP - Configure WDT to either be paused, or kept running, while the CPU is sleeping - 0 - 0 - - - Pause - Pause WDT while the CPU is sleeping - 0 - - - Run - Keep WDT running while the CPU is sleeping - 1 - - - - - HALT - Configure WDT to either be paused, or kept running, while the CPU is halted by the debugger - 3 - 3 - - - Pause - Pause WDT while the CPU is halted by the debugger - 0 - - - Run - Keep WDT running while the CPU is halted by the debugger - 1 - - - - - STOPEN - Allow stopping WDT - 6 - 6 - - - Disable - Do not allow stopping WDT - 0 - - - Enable - Allow stopping WDT - 1 - - - - - - - TSEN - Task stop enable - 0x520 - write-only - 0x00000000 - - - TSEN - Allow stopping WDT - 0 - 31 - - - Enable - Value to allow stopping WDT - 0x6E524635 - - - - - - - 0x8 - 0x4 - RR[%s] - Description collection: Reload request n - 0x600 - write-only - - - RR - Reload request register - 0 - 31 - - - Reload - Value to request a reload of the watchdog timer - 0x6E524635 - - - - - - - - - TIMER0_NS - Timer/Counter 0 - 0x4100C000 - TIMER - - - - 0 - 0x1000 - registers - - - TIMER0 - 12 - - TIMER - 0x20 - - - TASKS_START - Start Timer - 0x000 - write-only - - - TASKS_START - Start Timer - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STOP - Stop Timer - 0x004 - write-only - - - TASKS_STOP - Stop Timer - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_COUNT - Increment Timer (Counter mode only) - 0x008 - write-only - - - TASKS_COUNT - Increment Timer (Counter mode only) - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_CLEAR - Clear time - 0x00C - write-only - - - TASKS_CLEAR - Clear time - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_SHUTDOWN - Deprecated register - Shut down timer - 0x010 - write-only - - - TASKS_SHUTDOWN - Deprecated field - Shut down timer - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - 0x8 - 0x4 - TASKS_CAPTURE[%s] - Description collection: Capture Timer value to CC[n] register - 0x040 - write-only - - - TASKS_CAPTURE - Capture Timer value to CC[n] register - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - SUBSCRIBE_START - Subscribe configuration for task START - 0x080 - read-write - - - CHIDX - DPPI channel that task START will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_STOP - Subscribe configuration for task STOP - 0x084 - read-write - - - CHIDX - DPPI channel that task STOP will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_COUNT - Subscribe configuration for task COUNT - 0x088 - read-write - - - CHIDX - DPPI channel that task COUNT will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_CLEAR - Subscribe configuration for task CLEAR - 0x08C - read-write - - - CHIDX - DPPI channel that task CLEAR will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_SHUTDOWN - Deprecated register - Subscribe configuration for task SHUTDOWN - 0x090 - read-write - - - CHIDX - DPPI channel that task SHUTDOWN will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - 0x8 - 0x4 - SUBSCRIBE_CAPTURE[%s] - Description collection: Subscribe configuration for task CAPTURE[n] - 0x0C0 - read-write - - - CHIDX - DPPI channel that task CAPTURE[n] will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - 0x8 - 0x4 - EVENTS_COMPARE[%s] - Description collection: Compare event on CC[n] match - 0x140 - read-write - - - EVENTS_COMPARE - Compare event on CC[n] match - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - 0x8 - 0x4 - PUBLISH_COMPARE[%s] - Description collection: Publish configuration for event COMPARE[n] - 0x1C0 - read-write - - - CHIDX - DPPI channel that event COMPARE[n] will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - SHORTS - Shortcuts between local events and tasks - 0x200 - read-write - - - COMPARE0_CLEAR - Shortcut between event COMPARE[0] and task CLEAR - 0 - 0 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - COMPARE1_CLEAR - Shortcut between event COMPARE[1] and task CLEAR - 1 - 1 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - COMPARE2_CLEAR - Shortcut between event COMPARE[2] and task CLEAR - 2 - 2 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - COMPARE3_CLEAR - Shortcut between event COMPARE[3] and task CLEAR - 3 - 3 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - COMPARE4_CLEAR - Shortcut between event COMPARE[4] and task CLEAR - 4 - 4 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - COMPARE5_CLEAR - Shortcut between event COMPARE[5] and task CLEAR - 5 - 5 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - COMPARE6_CLEAR - Shortcut between event COMPARE[6] and task CLEAR - 6 - 6 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - COMPARE7_CLEAR - Shortcut between event COMPARE[7] and task CLEAR - 7 - 7 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - COMPARE0_STOP - Shortcut between event COMPARE[0] and task STOP - 16 - 16 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - COMPARE1_STOP - Shortcut between event COMPARE[1] and task STOP - 17 - 17 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - COMPARE2_STOP - Shortcut between event COMPARE[2] and task STOP - 18 - 18 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - COMPARE3_STOP - Shortcut between event COMPARE[3] and task STOP - 19 - 19 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - COMPARE4_STOP - Shortcut between event COMPARE[4] and task STOP - 20 - 20 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - COMPARE5_STOP - Shortcut between event COMPARE[5] and task STOP - 21 - 21 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - COMPARE6_STOP - Shortcut between event COMPARE[6] and task STOP - 22 - 22 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - COMPARE7_STOP - Shortcut between event COMPARE[7] and task STOP - 23 - 23 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - - COMPARE0 - Enable or disable interrupt for event COMPARE[0] - 16 - 16 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - COMPARE1 - Enable or disable interrupt for event COMPARE[1] - 17 - 17 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - COMPARE2 - Enable or disable interrupt for event COMPARE[2] - 18 - 18 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - COMPARE3 - Enable or disable interrupt for event COMPARE[3] - 19 - 19 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - COMPARE4 - Enable or disable interrupt for event COMPARE[4] - 20 - 20 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - COMPARE5 - Enable or disable interrupt for event COMPARE[5] - 21 - 21 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - COMPARE6 - Enable or disable interrupt for event COMPARE[6] - 22 - 22 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - COMPARE7 - Enable or disable interrupt for event COMPARE[7] - 23 - 23 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - COMPARE0 - Write '1' to enable interrupt for event COMPARE[0] - 16 - 16 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - COMPARE1 - Write '1' to enable interrupt for event COMPARE[1] - 17 - 17 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - COMPARE2 - Write '1' to enable interrupt for event COMPARE[2] - 18 - 18 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - COMPARE3 - Write '1' to enable interrupt for event COMPARE[3] - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - COMPARE4 - Write '1' to enable interrupt for event COMPARE[4] - 20 - 20 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - COMPARE5 - Write '1' to enable interrupt for event COMPARE[5] - 21 - 21 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - COMPARE6 - Write '1' to enable interrupt for event COMPARE[6] - 22 - 22 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - COMPARE7 - Write '1' to enable interrupt for event COMPARE[7] - 23 - 23 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - COMPARE0 - Write '1' to disable interrupt for event COMPARE[0] - 16 - 16 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - COMPARE1 - Write '1' to disable interrupt for event COMPARE[1] - 17 - 17 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - COMPARE2 - Write '1' to disable interrupt for event COMPARE[2] - 18 - 18 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - COMPARE3 - Write '1' to disable interrupt for event COMPARE[3] - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - COMPARE4 - Write '1' to disable interrupt for event COMPARE[4] - 20 - 20 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - COMPARE5 - Write '1' to disable interrupt for event COMPARE[5] - 21 - 21 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - COMPARE6 - Write '1' to disable interrupt for event COMPARE[6] - 22 - 22 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - COMPARE7 - Write '1' to disable interrupt for event COMPARE[7] - 23 - 23 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - MODE - Timer mode selection - 0x504 - read-write - - - MODE - Timer mode - 0 - 1 - - - Timer - Select Timer mode - 0 - - - Counter - Deprecated enumerator - Select Counter mode - 1 - - - LowPowerCounter - Select Low Power Counter mode - 2 - - - - - - - BITMODE - Configure the number of bits used by the TIMER - 0x508 - read-write - - - BITMODE - Timer bit width - 0 - 1 - - - 16Bit - 16 bit timer bit width - 0 - - - 08Bit - 8 bit timer bit width - 1 - - - 24Bit - 24 bit timer bit width - 2 - - - 32Bit - 32 bit timer bit width - 3 - - - - - - - PRESCALER - Timer prescaler register - 0x510 - read-write - 0x00000004 - - - PRESCALER - Prescaler value - 0 - 3 - - - - - 0x8 - 0x4 - CC[%s] - Description collection: Capture/Compare register n - 0x540 - read-write - - - CC - Capture/Compare value - 0 - 31 - - - - - 0x8 - 0x4 - ONESHOTEN[%s] - Description collection: Enable one-shot operation for Capture/Compare channel n - 0x580 - read-write - - - ONESHOTEN - Enable one-shot operation - 0 - 0 - - - Disable - Disable one-shot operation - 0 - - - Enable - Enable one-shot operation - 1 - - - - - - - - - ECB_NS - AES ECB Mode Encryption - 0x4100D000 - ECB - - - - 0 - 0x1000 - registers - - - ECB - 13 - - ECB - 0x20 - - - TASKS_STARTECB - Start ECB block encrypt - 0x000 - write-only - - - TASKS_STARTECB - Start ECB block encrypt - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STOPECB - Abort a possible executing ECB operation - 0x004 - write-only - - - TASKS_STOPECB - Abort a possible executing ECB operation - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - SUBSCRIBE_STARTECB - Subscribe configuration for task STARTECB - 0x080 - read-write - - - CHIDX - DPPI channel that task STARTECB will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_STOPECB - Subscribe configuration for task STOPECB - 0x084 - read-write - - - CHIDX - DPPI channel that task STOPECB will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - EVENTS_ENDECB - ECB block encrypt complete - 0x100 - read-write - - - EVENTS_ENDECB - ECB block encrypt complete - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_ERRORECB - ECB block encrypt aborted because of a STOPECB task or due to an error - 0x104 - read-write - - - EVENTS_ERRORECB - ECB block encrypt aborted because of a STOPECB task or due to an error - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - PUBLISH_ENDECB - Publish configuration for event ENDECB - 0x180 - read-write - - - CHIDX - DPPI channel that event ENDECB will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_ERRORECB - Publish configuration for event ERRORECB - 0x184 - read-write - - - CHIDX - DPPI channel that event ERRORECB will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - ENDECB - Write '1' to enable interrupt for event ENDECB - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ERRORECB - Write '1' to enable interrupt for event ERRORECB - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - ENDECB - Write '1' to disable interrupt for event ENDECB - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ERRORECB - Write '1' to disable interrupt for event ERRORECB - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - ECBDATAPTR - ECB block encrypt memory pointers - 0x504 - read-write - - - ECBDATAPTR - Pointer to the ECB data structure (see Table 1 ECB data structure overview) - 0 - 31 - - - - - - - AAR_NS - Accelerated Address Resolver - 0x4100E000 - AAR - - - - 0 - 0x1000 - registers - - - AAR_CCM - 14 - - AAR - 0x20 - - - TASKS_START - Start resolving addresses based on IRKs specified in the IRK data structure - 0x000 - write-only - - - TASKS_START - Start resolving addresses based on IRKs specified in the IRK data structure - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STOP - Stop resolving addresses - 0x008 - write-only - - - TASKS_STOP - Stop resolving addresses - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - SUBSCRIBE_START - Subscribe configuration for task START - 0x080 - read-write - - - CHIDX - DPPI channel that task START will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_STOP - Subscribe configuration for task STOP - 0x088 - read-write - - - CHIDX - DPPI channel that task STOP will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - EVENTS_END - Address resolution procedure complete - 0x100 - read-write - - - EVENTS_END - Address resolution procedure complete - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_RESOLVED - Address resolved - 0x104 - read-write - - - EVENTS_RESOLVED - Address resolved - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_NOTRESOLVED - Address not resolved - 0x108 - read-write - - - EVENTS_NOTRESOLVED - Address not resolved - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - PUBLISH_END - Publish configuration for event END - 0x180 - read-write - - - CHIDX - DPPI channel that event END will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_RESOLVED - Publish configuration for event RESOLVED - 0x184 - read-write - - - CHIDX - DPPI channel that event RESOLVED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_NOTRESOLVED - Publish configuration for event NOTRESOLVED - 0x188 - read-write - - - CHIDX - DPPI channel that event NOTRESOLVED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - END - Write '1' to enable interrupt for event END - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RESOLVED - Write '1' to enable interrupt for event RESOLVED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - NOTRESOLVED - Write '1' to enable interrupt for event NOTRESOLVED - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - END - Write '1' to disable interrupt for event END - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RESOLVED - Write '1' to disable interrupt for event RESOLVED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - NOTRESOLVED - Write '1' to disable interrupt for event NOTRESOLVED - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - STATUS - Resolution status - 0x400 - read-only - - - STATUS - The IRK that was used last time an address was resolved - 0 - 3 - - - - - ENABLE - Enable AAR - 0x500 - read-write - - - ENABLE - Enable or disable AAR - 0 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 3 - - - - - - - NIRK - Number of IRKs - 0x504 - read-write - 0x00000001 - - - NIRK - Number of Identity Root Keys available in the IRK data structure - 0 - 4 - - - - - IRKPTR - Pointer to IRK data structure - 0x508 - read-write - - - IRKPTR - Pointer to the IRK data structure - 0 - 31 - - - - - ADDRPTR - Pointer to the resolvable address - 0x510 - read-write - - - ADDRPTR - Pointer to the resolvable address (6-bytes) - 0 - 31 - - - - - SCRATCHPTR - Pointer to data area used for temporary storage - 0x514 - read-write - - - SCRATCHPTR - Pointer to a scratch data area used for temporary storage during resolution. A space of minimum 3 bytes must be reserved. - 0 - 31 - - - - - - - CCM_NS - AES CCM mode encryption - 0x4100E000 - AAR_NS - CCM - - - - 0 - 0x1000 - registers - - - AAR_CCM - 14 - - CCM - 0x20 - - - TASKS_KSGEN - Start generation of keystream. This operation will stop by itself when completed. - 0x000 - write-only - - - TASKS_KSGEN - Start generation of keystream. This operation will stop by itself when completed. - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_CRYPT - Start encryption/decryption. This operation will stop by itself when completed. - 0x004 - write-only - - - TASKS_CRYPT - Start encryption/decryption. This operation will stop by itself when completed. - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STOP - Stop encryption/decryption - 0x008 - write-only - - - TASKS_STOP - Stop encryption/decryption - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_RATEOVERRIDE - Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption - 0x00C - write-only - - - TASKS_RATEOVERRIDE - Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - SUBSCRIBE_KSGEN - Subscribe configuration for task KSGEN - 0x080 - read-write - - - CHIDX - DPPI channel that task KSGEN will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_CRYPT - Subscribe configuration for task CRYPT - 0x084 - read-write - - - CHIDX - DPPI channel that task CRYPT will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_STOP - Subscribe configuration for task STOP - 0x088 - read-write - - - CHIDX - DPPI channel that task STOP will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_RATEOVERRIDE - Subscribe configuration for task RATEOVERRIDE - 0x08C - read-write - - - CHIDX - DPPI channel that task RATEOVERRIDE will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - EVENTS_ENDKSGEN - Keystream generation complete - 0x100 - read-write - - - EVENTS_ENDKSGEN - Keystream generation complete - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_ENDCRYPT - Encrypt/decrypt complete - 0x104 - read-write - - - EVENTS_ENDCRYPT - Encrypt/decrypt complete - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_ERROR - Deprecated register - CCM error event - 0x108 - read-write - - - EVENTS_ERROR - Deprecated field - CCM error event - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - PUBLISH_ENDKSGEN - Publish configuration for event ENDKSGEN - 0x180 - read-write - - - CHIDX - DPPI channel that event ENDKSGEN will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_ENDCRYPT - Publish configuration for event ENDCRYPT - 0x184 - read-write - - - CHIDX - DPPI channel that event ENDCRYPT will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_ERROR - Deprecated register - Publish configuration for event ERROR - 0x188 - read-write - - - CHIDX - DPPI channel that event ERROR will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - SHORTS - Shortcuts between local events and tasks - 0x200 - read-write - - - ENDKSGEN_CRYPT - Shortcut between event ENDKSGEN and task CRYPT - 0 - 0 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - ENDKSGEN - Write '1' to enable interrupt for event ENDKSGEN - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ENDCRYPT - Write '1' to enable interrupt for event ENDCRYPT - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ERROR - Deprecated intsetfield - Write '1' to enable interrupt for event ERROR - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - ENDKSGEN - Write '1' to disable interrupt for event ENDKSGEN - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ENDCRYPT - Write '1' to disable interrupt for event ENDCRYPT - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ERROR - Deprecated intclrfield - Write '1' to disable interrupt for event ERROR - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - MICSTATUS - MIC check result - 0x400 - read-only - - - MICSTATUS - The result of the MIC check performed during the previous decryption operation - 0 - 0 - - - CheckFailed - MIC check failed - 0 - - - CheckPassed - MIC check passed - 1 - - - - - - - ENABLE - Enable - 0x500 - read-write - - - ENABLE - Enable or disable CCM - 0 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 2 - - - - - - - MODE - Operation mode - 0x504 - read-write - 0x00000001 - - - MODE - The mode of operation to be used. Settings in this register apply whenever either the KSGEN task or the CRYPT task is triggered. - 0 - 0 - - - Encryption - AES CCM packet encryption mode - 0 - - - Decryption - AES CCM packet decryption mode - 1 - - - - - DATARATE - Radio data rate that the CCM shall run synchronous with - 16 - 17 - - - 1Mbit - 1 Mbps - 0 - - - 2Mbit - 2 Mbps - 1 - - - 125Kbps - 125 kbps - 2 - - - 500Kbps - 500 kbps - 3 - - - - - LENGTH - Packet length configuration - 24 - 24 - - - Default - Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A keystream for packet payloads up to 27 bytes will be generated. - 0 - - - Extended - Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A keystream for packet payloads up to MAXPACKETSIZE bytes will be generated. - 1 - - - - - - - CNFPTR - Pointer to data structure holding the AES key and the NONCE vector - 0x508 - read-write - - - CNFPTR - Pointer to the data structure holding the AES key and the CCM NONCE vector (see table CCM data structure overview) - 0 - 31 - - - - - INPTR - Input pointer - 0x50C - read-write - - - INPTR - Input pointer - 0 - 31 - - - - - OUTPTR - Output pointer - 0x510 - read-write - - - OUTPTR - Output pointer - 0 - 31 - - - - - SCRATCHPTR - Pointer to data area used for temporary storage - 0x514 - read-write - - - SCRATCHPTR - Pointer to a scratch data area used for temporary storage during keystream generation, - MIC generation and encryption/decryption. - 0 - 31 - - - - - MAXPACKETSIZE - Length of keystream generated when MODE.LENGTH = Extended - 0x518 - read-write - 0x000000FB - - - MAXPACKETSIZE - Length of keystream generated when MODE.LENGTH = Extended. This value must be greater than or equal to the subsequent packet payload to be encrypted/decrypted. - 0 - 7 - - - - - RATEOVERRIDE - Data rate override setting. - 0x51C - read-write - 0x00000000 - - - RATEOVERRIDE - Data rate override setting - 0 - 1 - - - 1Mbit - 1 Mbps - 0 - - - 2Mbit - 2 Mbps - 1 - - - 125Kbps - 125 kbps - 2 - - - 500Kbps - 500 kbps - 3 - - - - - - - HEADERMASK - Header (S0) mask. - 0x520 - read-write - 0x000000E3 - - - HEADERMASK - Header (S0) mask - 0 - 7 - - - - - - - DPPIC_NS - Distributed programmable peripheral interconnect controller - 0x4100F000 - DPPIC - - - - 0 - 0x1000 - registers - - DPPIC - 0x20 - - - 6 - 0x008 - TASKS_CHG[%s] - Channel group tasks - DPPIC_TASKS_CHG - write-only - 0x000 - - EN - Description cluster: Enable channel group n - 0x000 - write-only - - - EN - Enable channel group n - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - DIS - Description cluster: Disable channel group n - 0x004 - write-only - - - DIS - Disable channel group n - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - - 6 - 0x008 - SUBSCRIBE_CHG[%s] - Subscribe configuration for tasks - DPPIC_SUBSCRIBE_CHG - read-write - 0x080 - - EN - Description cluster: Subscribe configuration for task CHG[n].EN - 0x000 - read-write - - - CHIDX - DPPI channel that task CHG[n].EN will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - DIS - Description cluster: Subscribe configuration for task CHG[n].DIS - 0x004 - read-write - - - CHIDX - DPPI channel that task CHG[n].DIS will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - - CHEN - Channel enable register - 0x500 - read-write - - - CH0 - Enable or disable channel 0 - 0 - 0 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH1 - Enable or disable channel 1 - 1 - 1 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH2 - Enable or disable channel 2 - 2 - 2 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH3 - Enable or disable channel 3 - 3 - 3 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH4 - Enable or disable channel 4 - 4 - 4 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH5 - Enable or disable channel 5 - 5 - 5 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH6 - Enable or disable channel 6 - 6 - 6 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH7 - Enable or disable channel 7 - 7 - 7 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH8 - Enable or disable channel 8 - 8 - 8 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH9 - Enable or disable channel 9 - 9 - 9 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH10 - Enable or disable channel 10 - 10 - 10 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH11 - Enable or disable channel 11 - 11 - 11 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH12 - Enable or disable channel 12 - 12 - 12 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH13 - Enable or disable channel 13 - 13 - 13 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH14 - Enable or disable channel 14 - 14 - 14 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH15 - Enable or disable channel 15 - 15 - 15 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - - - CHENSET - Channel enable set register - 0x504 - read-write - oneToSet - - - CH0 - Channel 0 enable set register. Writing 0 has no effect. - 0 - 0 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH1 - Channel 1 enable set register. Writing 0 has no effect. - 1 - 1 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH2 - Channel 2 enable set register. Writing 0 has no effect. - 2 - 2 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH3 - Channel 3 enable set register. Writing 0 has no effect. - 3 - 3 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH4 - Channel 4 enable set register. Writing 0 has no effect. - 4 - 4 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH5 - Channel 5 enable set register. Writing 0 has no effect. - 5 - 5 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH6 - Channel 6 enable set register. Writing 0 has no effect. - 6 - 6 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH7 - Channel 7 enable set register. Writing 0 has no effect. - 7 - 7 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH8 - Channel 8 enable set register. Writing 0 has no effect. - 8 - 8 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH9 - Channel 9 enable set register. Writing 0 has no effect. - 9 - 9 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH10 - Channel 10 enable set register. Writing 0 has no effect. - 10 - 10 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH11 - Channel 11 enable set register. Writing 0 has no effect. - 11 - 11 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH12 - Channel 12 enable set register. Writing 0 has no effect. - 12 - 12 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH13 - Channel 13 enable set register. Writing 0 has no effect. - 13 - 13 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH14 - Channel 14 enable set register. Writing 0 has no effect. - 14 - 14 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - CH15 - Channel 15 enable set register. Writing 0 has no effect. - 15 - 15 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - - - - - - CHENCLR - Channel enable clear register - 0x508 - read-write - oneToClear - - - CH0 - Channel 0 enable clear register. Writing 0 has no effect. - 0 - 0 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Clear - Write: Disable channel - 1 - - - - - CH1 - Channel 1 enable clear register. Writing 0 has no effect. - 1 - 1 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Clear - Write: Disable channel - 1 - - - - - CH2 - Channel 2 enable clear register. Writing 0 has no effect. - 2 - 2 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Clear - Write: Disable channel - 1 - - - - - CH3 - Channel 3 enable clear register. Writing 0 has no effect. - 3 - 3 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Clear - Write: Disable channel - 1 - - - - - CH4 - Channel 4 enable clear register. Writing 0 has no effect. - 4 - 4 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Clear - Write: Disable channel - 1 - - - - - CH5 - Channel 5 enable clear register. Writing 0 has no effect. - 5 - 5 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Clear - Write: Disable channel - 1 - - - - - CH6 - Channel 6 enable clear register. Writing 0 has no effect. - 6 - 6 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Clear - Write: Disable channel - 1 - - - - - CH7 - Channel 7 enable clear register. Writing 0 has no effect. - 7 - 7 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Clear - Write: Disable channel - 1 - - - - - CH8 - Channel 8 enable clear register. Writing 0 has no effect. - 8 - 8 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Clear - Write: Disable channel - 1 - - - - - CH9 - Channel 9 enable clear register. Writing 0 has no effect. - 9 - 9 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Clear - Write: Disable channel - 1 - - - - - CH10 - Channel 10 enable clear register. Writing 0 has no effect. - 10 - 10 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Clear - Write: Disable channel - 1 - - - - - CH11 - Channel 11 enable clear register. Writing 0 has no effect. - 11 - 11 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Clear - Write: Disable channel - 1 - - - - - CH12 - Channel 12 enable clear register. Writing 0 has no effect. - 12 - 12 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Clear - Write: Disable channel - 1 - - - - - CH13 - Channel 13 enable clear register. Writing 0 has no effect. - 13 - 13 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Clear - Write: Disable channel - 1 - - - - - CH14 - Channel 14 enable clear register. Writing 0 has no effect. - 14 - 14 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Clear - Write: Disable channel - 1 - - - - - CH15 - Channel 15 enable clear register. Writing 0 has no effect. - 15 - 15 - - read - - Disabled - Read: Channel disabled - 0 - - - Enabled - Read: Channel enabled - 1 - - - - write - - Clear - Write: Disable channel - 1 - - - - - - - 0x6 - 0x4 - CHG[%s] - Description collection: Channel group n Note: Writes to this register are ignored if either SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS is enabled - 0x800 - read-write - - - CH0 - Include or exclude channel 0 - 0 - 0 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH1 - Include or exclude channel 1 - 1 - 1 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH2 - Include or exclude channel 2 - 2 - 2 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH3 - Include or exclude channel 3 - 3 - 3 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH4 - Include or exclude channel 4 - 4 - 4 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH5 - Include or exclude channel 5 - 5 - 5 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH6 - Include or exclude channel 6 - 6 - 6 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH7 - Include or exclude channel 7 - 7 - 7 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH8 - Include or exclude channel 8 - 8 - 8 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH9 - Include or exclude channel 9 - 9 - 9 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH10 - Include or exclude channel 10 - 10 - 10 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH11 - Include or exclude channel 11 - 11 - 11 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH12 - Include or exclude channel 12 - 12 - 12 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH13 - Include or exclude channel 13 - 13 - 13 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH14 - Include or exclude channel 14 - 14 - 14 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH15 - Include or exclude channel 15 - 15 - 15 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - - - - - TEMP_NS - Temperature Sensor - 0x41010000 - TEMP - - - - 0 - 0x1000 - registers - - - TEMP - 16 - - TEMP - 0x20 - - - TASKS_START - Start temperature measurement - 0x000 - write-only - - - TASKS_START - Start temperature measurement - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STOP - Stop temperature measurement - 0x004 - write-only - - - TASKS_STOP - Stop temperature measurement - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - SUBSCRIBE_START - Subscribe configuration for task START - 0x080 - read-write - - - CHIDX - DPPI channel that task START will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_STOP - Subscribe configuration for task STOP - 0x084 - read-write - - - CHIDX - DPPI channel that task STOP will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - EVENTS_DATARDY - Temperature measurement complete, data ready - 0x100 - read-write - - - EVENTS_DATARDY - Temperature measurement complete, data ready - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - PUBLISH_DATARDY - Publish configuration for event DATARDY - 0x180 - read-write - - - CHIDX - DPPI channel that event DATARDY will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - DATARDY - Write '1' to enable interrupt for event DATARDY - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - DATARDY - Write '1' to disable interrupt for event DATARDY - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - TEMP - Temperature in degC (0.25deg steps) - 0x508 - read-only - int32_t - - - TEMP - Temperature in degC (0.25deg steps) - 0 - 31 - - - - - A0 - Slope of first piecewise linear function - 0x520 - read-write - 0x000002D9 - - - A0 - Slope of first piecewise linear function - 0 - 11 - - - - - A1 - Slope of second piecewise linear function - 0x524 - read-write - 0x00000322 - - - A1 - Slope of second piecewise linear function - 0 - 11 - - - - - A2 - Slope of third piecewise linear function - 0x528 - read-write - 0x00000355 - - - A2 - Slope of third piecewise linear function - 0 - 11 - - - - - A3 - Slope of fourth piecewise linear function - 0x52C - read-write - 0x000003DF - - - A3 - Slope of fourth piecewise linear function - 0 - 11 - - - - - A4 - Slope of fifth piecewise linear function - 0x530 - read-write - 0x0000044E - - - A4 - Slope of fifth piecewise linear function - 0 - 11 - - - - - A5 - Slope of sixth piecewise linear function - 0x534 - read-write - 0x000004B7 - - - A5 - Slope of sixth piecewise linear function - 0 - 11 - - - - - B0 - y-intercept of first piecewise linear function - 0x540 - read-write - 0x00000FC7 - - - B0 - y-intercept of first piecewise linear function - 0 - 11 - - - - - B1 - y-intercept of second piecewise linear function - 0x544 - read-write - 0x00000F71 - - - B1 - y-intercept of second piecewise linear function - 0 - 11 - - - - - B2 - y-intercept of third piecewise linear function - 0x548 - read-write - 0x00000F6C - - - B2 - y-intercept of third piecewise linear function - 0 - 11 - - - - - B3 - y-intercept of fourth piecewise linear function - 0x54C - read-write - 0x00000FCB - - - B3 - y-intercept of fourth piecewise linear function - 0 - 11 - - - - - B4 - y-intercept of fifth piecewise linear function - 0x550 - read-write - 0x0000004B - - - B4 - y-intercept of fifth piecewise linear function - 0 - 11 - - - - - B5 - y-intercept of sixth piecewise linear function - 0x554 - read-write - 0x000000F6 - - - B5 - y-intercept of sixth piecewise linear function - 0 - 11 - - - - - T0 - Endpoint of first piecewise linear function - 0x560 - read-write - 0x000000E1 - - - T0 - Endpoint of first piecewise linear function - 0 - 7 - - - - - T1 - Endpoint of second piecewise linear function - 0x564 - read-write - 0x000000F9 - - - T1 - Endpoint of second piecewise linear function - 0 - 7 - - - - - T2 - Endpoint of third piecewise linear function - 0x568 - read-write - 0x00000010 - - - T2 - Endpoint of third piecewise linear function - 0 - 7 - - - - - T3 - Endpoint of fourth piecewise linear function - 0x56C - read-write - 0x00000026 - - - T3 - Endpoint of fourth piecewise linear function - 0 - 7 - - - - - T4 - Endpoint of fifth piecewise linear function - 0x570 - read-write - 0x0000003F - - - T4 - Endpoint of fifth piecewise linear function - 0 - 7 - - - - - - - RTC0_NS - Real-time counter 0 - 0x41011000 - RTC - - - - 0 - 0x1000 - registers - - - RTC0 - 17 - - RTC - 0x20 - - - TASKS_START - Start RTC counter - 0x000 - write-only - - - TASKS_START - Start RTC counter - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STOP - Stop RTC counter - 0x004 - write-only - - - TASKS_STOP - Stop RTC counter - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_CLEAR - Clear RTC counter - 0x008 - write-only - - - TASKS_CLEAR - Clear RTC counter - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_TRIGOVRFLW - Set counter to 0xFFFFF0 - 0x00C - write-only - - - TASKS_TRIGOVRFLW - Set counter to 0xFFFFF0 - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - 0x4 - 0x4 - TASKS_CAPTURE[%s] - Description collection: Capture RTC counter to CC[n] register - 0x040 - write-only - - - TASKS_CAPTURE - Capture RTC counter to CC[n] register - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - SUBSCRIBE_START - Subscribe configuration for task START - 0x080 - read-write - - - CHIDX - DPPI channel that task START will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_STOP - Subscribe configuration for task STOP - 0x084 - read-write - - - CHIDX - DPPI channel that task STOP will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_CLEAR - Subscribe configuration for task CLEAR - 0x088 - read-write - - - CHIDX - DPPI channel that task CLEAR will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_TRIGOVRFLW - Subscribe configuration for task TRIGOVRFLW - 0x08C - read-write - - - CHIDX - DPPI channel that task TRIGOVRFLW will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - 0x4 - 0x4 - SUBSCRIBE_CAPTURE[%s] - Description collection: Subscribe configuration for task CAPTURE[n] - 0x0C0 - read-write - - - CHIDX - DPPI channel that task CAPTURE[n] will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - EVENTS_TICK - Event on counter increment - 0x100 - read-write - - - EVENTS_TICK - Event on counter increment - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_OVRFLW - Event on counter overflow - 0x104 - read-write - - - EVENTS_OVRFLW - Event on counter overflow - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - 0x4 - 0x4 - EVENTS_COMPARE[%s] - Description collection: Compare event on CC[n] match - 0x140 - read-write - - - EVENTS_COMPARE - Compare event on CC[n] match - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - PUBLISH_TICK - Publish configuration for event TICK - 0x180 - read-write - - - CHIDX - DPPI channel that event TICK will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_OVRFLW - Publish configuration for event OVRFLW - 0x184 - read-write - - - CHIDX - DPPI channel that event OVRFLW will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - 0x4 - 0x4 - PUBLISH_COMPARE[%s] - Description collection: Publish configuration for event COMPARE[n] - 0x1C0 - read-write - - - CHIDX - DPPI channel that event COMPARE[n] will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - SHORTS - Shortcuts between local events and tasks - 0x200 - read-write - - - COMPARE0_CLEAR - Shortcut between event COMPARE[0] and task CLEAR - 0 - 0 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - COMPARE1_CLEAR - Shortcut between event COMPARE[1] and task CLEAR - 1 - 1 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - COMPARE2_CLEAR - Shortcut between event COMPARE[2] and task CLEAR - 2 - 2 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - COMPARE3_CLEAR - Shortcut between event COMPARE[3] and task CLEAR - 3 - 3 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - TICK - Write '1' to enable interrupt for event TICK - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - OVRFLW - Write '1' to enable interrupt for event OVRFLW - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - COMPARE0 - Write '1' to enable interrupt for event COMPARE[0] - 16 - 16 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - COMPARE1 - Write '1' to enable interrupt for event COMPARE[1] - 17 - 17 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - COMPARE2 - Write '1' to enable interrupt for event COMPARE[2] - 18 - 18 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - COMPARE3 - Write '1' to enable interrupt for event COMPARE[3] - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - TICK - Write '1' to disable interrupt for event TICK - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - OVRFLW - Write '1' to disable interrupt for event OVRFLW - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - COMPARE0 - Write '1' to disable interrupt for event COMPARE[0] - 16 - 16 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - COMPARE1 - Write '1' to disable interrupt for event COMPARE[1] - 17 - 17 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - COMPARE2 - Write '1' to disable interrupt for event COMPARE[2] - 18 - 18 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - COMPARE3 - Write '1' to disable interrupt for event COMPARE[3] - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - EVTEN - Enable or disable event routing - 0x340 - read-write - - - TICK - Enable or disable event routing for event TICK - 0 - 0 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - OVRFLW - Enable or disable event routing for event OVRFLW - 1 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - COMPARE0 - Enable or disable event routing for event COMPARE[0] - 16 - 16 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - COMPARE1 - Enable or disable event routing for event COMPARE[1] - 17 - 17 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - COMPARE2 - Enable or disable event routing for event COMPARE[2] - 18 - 18 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - COMPARE3 - Enable or disable event routing for event COMPARE[3] - 19 - 19 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - EVTENSET - Enable event routing - 0x344 - read-write - - - TICK - Write '1' to enable event routing for event TICK - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - OVRFLW - Write '1' to enable event routing for event OVRFLW - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - COMPARE0 - Write '1' to enable event routing for event COMPARE[0] - 16 - 16 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - COMPARE1 - Write '1' to enable event routing for event COMPARE[1] - 17 - 17 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - COMPARE2 - Write '1' to enable event routing for event COMPARE[2] - 18 - 18 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - COMPARE3 - Write '1' to enable event routing for event COMPARE[3] - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - EVTENCLR - Disable event routing - 0x348 - read-write - - - TICK - Write '1' to disable event routing for event TICK - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - OVRFLW - Write '1' to disable event routing for event OVRFLW - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - COMPARE0 - Write '1' to disable event routing for event COMPARE[0] - 16 - 16 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - COMPARE1 - Write '1' to disable event routing for event COMPARE[1] - 17 - 17 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - COMPARE2 - Write '1' to disable event routing for event COMPARE[2] - 18 - 18 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - COMPARE3 - Write '1' to disable event routing for event COMPARE[3] - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - COUNTER - Current counter value - 0x504 - read-only - - - COUNTER - Counter value - 0 - 23 - - - - - PRESCALER - 12-bit prescaler for counter frequency (32768 / (PRESCALER + 1)). Must be written when RTC is stopped. - 0x508 - read-write - - - PRESCALER - Prescaler value - 0 - 11 - - - - - 0x4 - 0x4 - CC[%s] - Description collection: Compare register n - 0x540 - read-write - - - COMPARE - Compare value - 0 - 23 - - - - - - - IPC_NS - Interprocessor communication - 0x41012000 - IPC - - - - 0 - 0x1000 - registers - - - IPC - 18 - - IPC - 0x20 - - - 0x10 - 0x4 - TASKS_SEND[%s] - Description collection: Trigger events on IPC channel enabled in SEND_CNF[n] - 0x000 - write-only - - - TASKS_SEND - Trigger events on IPC channel enabled in SEND_CNF[n] - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - 0x10 - 0x4 - SUBSCRIBE_SEND[%s] - Description collection: Subscribe configuration for task SEND[n] - 0x080 - read-write - - - CHIDX - DPPI channel that task SEND[n] will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - 0x10 - 0x4 - EVENTS_RECEIVE[%s] - Description collection: Event received on one or more of the enabled IPC channels in RECEIVE_CNF[n] - 0x100 - read-write - - - EVENTS_RECEIVE - Event received on one or more of the enabled IPC channels in RECEIVE_CNF[n] - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - 0x10 - 0x4 - PUBLISH_RECEIVE[%s] - Description collection: Publish configuration for event RECEIVE[n] - 0x180 - read-write - - - CHIDX - DPPI channel that event RECEIVE[n] will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - - RECEIVE0 - Enable or disable interrupt for event RECEIVE[0] - 0 - 0 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RECEIVE1 - Enable or disable interrupt for event RECEIVE[1] - 1 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RECEIVE2 - Enable or disable interrupt for event RECEIVE[2] - 2 - 2 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RECEIVE3 - Enable or disable interrupt for event RECEIVE[3] - 3 - 3 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RECEIVE4 - Enable or disable interrupt for event RECEIVE[4] - 4 - 4 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RECEIVE5 - Enable or disable interrupt for event RECEIVE[5] - 5 - 5 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RECEIVE6 - Enable or disable interrupt for event RECEIVE[6] - 6 - 6 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RECEIVE7 - Enable or disable interrupt for event RECEIVE[7] - 7 - 7 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RECEIVE8 - Enable or disable interrupt for event RECEIVE[8] - 8 - 8 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RECEIVE9 - Enable or disable interrupt for event RECEIVE[9] - 9 - 9 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RECEIVE10 - Enable or disable interrupt for event RECEIVE[10] - 10 - 10 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RECEIVE11 - Enable or disable interrupt for event RECEIVE[11] - 11 - 11 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RECEIVE12 - Enable or disable interrupt for event RECEIVE[12] - 12 - 12 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RECEIVE13 - Enable or disable interrupt for event RECEIVE[13] - 13 - 13 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RECEIVE14 - Enable or disable interrupt for event RECEIVE[14] - 14 - 14 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RECEIVE15 - Enable or disable interrupt for event RECEIVE[15] - 15 - 15 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - RECEIVE0 - Write '1' to enable interrupt for event RECEIVE[0] - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RECEIVE1 - Write '1' to enable interrupt for event RECEIVE[1] - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RECEIVE2 - Write '1' to enable interrupt for event RECEIVE[2] - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RECEIVE3 - Write '1' to enable interrupt for event RECEIVE[3] - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RECEIVE4 - Write '1' to enable interrupt for event RECEIVE[4] - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RECEIVE5 - Write '1' to enable interrupt for event RECEIVE[5] - 5 - 5 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RECEIVE6 - Write '1' to enable interrupt for event RECEIVE[6] - 6 - 6 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RECEIVE7 - Write '1' to enable interrupt for event RECEIVE[7] - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RECEIVE8 - Write '1' to enable interrupt for event RECEIVE[8] - 8 - 8 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RECEIVE9 - Write '1' to enable interrupt for event RECEIVE[9] - 9 - 9 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RECEIVE10 - Write '1' to enable interrupt for event RECEIVE[10] - 10 - 10 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RECEIVE11 - Write '1' to enable interrupt for event RECEIVE[11] - 11 - 11 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RECEIVE12 - Write '1' to enable interrupt for event RECEIVE[12] - 12 - 12 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RECEIVE13 - Write '1' to enable interrupt for event RECEIVE[13] - 13 - 13 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RECEIVE14 - Write '1' to enable interrupt for event RECEIVE[14] - 14 - 14 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RECEIVE15 - Write '1' to enable interrupt for event RECEIVE[15] - 15 - 15 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - RECEIVE0 - Write '1' to disable interrupt for event RECEIVE[0] - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RECEIVE1 - Write '1' to disable interrupt for event RECEIVE[1] - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RECEIVE2 - Write '1' to disable interrupt for event RECEIVE[2] - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RECEIVE3 - Write '1' to disable interrupt for event RECEIVE[3] - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RECEIVE4 - Write '1' to disable interrupt for event RECEIVE[4] - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RECEIVE5 - Write '1' to disable interrupt for event RECEIVE[5] - 5 - 5 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RECEIVE6 - Write '1' to disable interrupt for event RECEIVE[6] - 6 - 6 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RECEIVE7 - Write '1' to disable interrupt for event RECEIVE[7] - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RECEIVE8 - Write '1' to disable interrupt for event RECEIVE[8] - 8 - 8 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RECEIVE9 - Write '1' to disable interrupt for event RECEIVE[9] - 9 - 9 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RECEIVE10 - Write '1' to disable interrupt for event RECEIVE[10] - 10 - 10 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RECEIVE11 - Write '1' to disable interrupt for event RECEIVE[11] - 11 - 11 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RECEIVE12 - Write '1' to disable interrupt for event RECEIVE[12] - 12 - 12 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RECEIVE13 - Write '1' to disable interrupt for event RECEIVE[13] - 13 - 13 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RECEIVE14 - Write '1' to disable interrupt for event RECEIVE[14] - 14 - 14 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RECEIVE15 - Write '1' to disable interrupt for event RECEIVE[15] - 15 - 15 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - INTPEND - Pending interrupts - 0x30C - read-only - - - RECEIVE0 - Read pending status of interrupt for event RECEIVE[0] - 0 - 0 - - read - - NotPending - Read: Not pending - 0 - - - Pending - Read: Pending - 1 - - - - - RECEIVE1 - Read pending status of interrupt for event RECEIVE[1] - 1 - 1 - - read - - NotPending - Read: Not pending - 0 - - - Pending - Read: Pending - 1 - - - - - RECEIVE2 - Read pending status of interrupt for event RECEIVE[2] - 2 - 2 - - read - - NotPending - Read: Not pending - 0 - - - Pending - Read: Pending - 1 - - - - - RECEIVE3 - Read pending status of interrupt for event RECEIVE[3] - 3 - 3 - - read - - NotPending - Read: Not pending - 0 - - - Pending - Read: Pending - 1 - - - - - RECEIVE4 - Read pending status of interrupt for event RECEIVE[4] - 4 - 4 - - read - - NotPending - Read: Not pending - 0 - - - Pending - Read: Pending - 1 - - - - - RECEIVE5 - Read pending status of interrupt for event RECEIVE[5] - 5 - 5 - - read - - NotPending - Read: Not pending - 0 - - - Pending - Read: Pending - 1 - - - - - RECEIVE6 - Read pending status of interrupt for event RECEIVE[6] - 6 - 6 - - read - - NotPending - Read: Not pending - 0 - - - Pending - Read: Pending - 1 - - - - - RECEIVE7 - Read pending status of interrupt for event RECEIVE[7] - 7 - 7 - - read - - NotPending - Read: Not pending - 0 - - - Pending - Read: Pending - 1 - - - - - RECEIVE8 - Read pending status of interrupt for event RECEIVE[8] - 8 - 8 - - read - - NotPending - Read: Not pending - 0 - - - Pending - Read: Pending - 1 - - - - - RECEIVE9 - Read pending status of interrupt for event RECEIVE[9] - 9 - 9 - - read - - NotPending - Read: Not pending - 0 - - - Pending - Read: Pending - 1 - - - - - RECEIVE10 - Read pending status of interrupt for event RECEIVE[10] - 10 - 10 - - read - - NotPending - Read: Not pending - 0 - - - Pending - Read: Pending - 1 - - - - - RECEIVE11 - Read pending status of interrupt for event RECEIVE[11] - 11 - 11 - - read - - NotPending - Read: Not pending - 0 - - - Pending - Read: Pending - 1 - - - - - RECEIVE12 - Read pending status of interrupt for event RECEIVE[12] - 12 - 12 - - read - - NotPending - Read: Not pending - 0 - - - Pending - Read: Pending - 1 - - - - - RECEIVE13 - Read pending status of interrupt for event RECEIVE[13] - 13 - 13 - - read - - NotPending - Read: Not pending - 0 - - - Pending - Read: Pending - 1 - - - - - RECEIVE14 - Read pending status of interrupt for event RECEIVE[14] - 14 - 14 - - read - - NotPending - Read: Not pending - 0 - - - Pending - Read: Pending - 1 - - - - - RECEIVE15 - Read pending status of interrupt for event RECEIVE[15] - 15 - 15 - - read - - NotPending - Read: Not pending - 0 - - - Pending - Read: Pending - 1 - - - - - - - 0x10 - 0x4 - SEND_CNF[%s] - Description collection: Send event configuration for TASKS_SEND[n] - 0x510 - read-write - 0x00000000 - - - CHEN0 - Enable broadcasting on IPC channel 0 - 0 - 0 - - - Disable - Disable broadcast - 0 - - - Enable - Enable broadcast - 1 - - - - - CHEN1 - Enable broadcasting on IPC channel 1 - 1 - 1 - - - Disable - Disable broadcast - 0 - - - Enable - Enable broadcast - 1 - - - - - CHEN2 - Enable broadcasting on IPC channel 2 - 2 - 2 - - - Disable - Disable broadcast - 0 - - - Enable - Enable broadcast - 1 - - - - - CHEN3 - Enable broadcasting on IPC channel 3 - 3 - 3 - - - Disable - Disable broadcast - 0 - - - Enable - Enable broadcast - 1 - - - - - CHEN4 - Enable broadcasting on IPC channel 4 - 4 - 4 - - - Disable - Disable broadcast - 0 - - - Enable - Enable broadcast - 1 - - - - - CHEN5 - Enable broadcasting on IPC channel 5 - 5 - 5 - - - Disable - Disable broadcast - 0 - - - Enable - Enable broadcast - 1 - - - - - CHEN6 - Enable broadcasting on IPC channel 6 - 6 - 6 - - - Disable - Disable broadcast - 0 - - - Enable - Enable broadcast - 1 - - - - - CHEN7 - Enable broadcasting on IPC channel 7 - 7 - 7 - - - Disable - Disable broadcast - 0 - - - Enable - Enable broadcast - 1 - - - - - CHEN8 - Enable broadcasting on IPC channel 8 - 8 - 8 - - - Disable - Disable broadcast - 0 - - - Enable - Enable broadcast - 1 - - - - - CHEN9 - Enable broadcasting on IPC channel 9 - 9 - 9 - - - Disable - Disable broadcast - 0 - - - Enable - Enable broadcast - 1 - - - - - CHEN10 - Enable broadcasting on IPC channel 10 - 10 - 10 - - - Disable - Disable broadcast - 0 - - - Enable - Enable broadcast - 1 - - - - - CHEN11 - Enable broadcasting on IPC channel 11 - 11 - 11 - - - Disable - Disable broadcast - 0 - - - Enable - Enable broadcast - 1 - - - - - CHEN12 - Enable broadcasting on IPC channel 12 - 12 - 12 - - - Disable - Disable broadcast - 0 - - - Enable - Enable broadcast - 1 - - - - - CHEN13 - Enable broadcasting on IPC channel 13 - 13 - 13 - - - Disable - Disable broadcast - 0 - - - Enable - Enable broadcast - 1 - - - - - CHEN14 - Enable broadcasting on IPC channel 14 - 14 - 14 - - - Disable - Disable broadcast - 0 - - - Enable - Enable broadcast - 1 - - - - - CHEN15 - Enable broadcasting on IPC channel 15 - 15 - 15 - - - Disable - Disable broadcast - 0 - - - Enable - Enable broadcast - 1 - - - - - - - 0x10 - 0x4 - RECEIVE_CNF[%s] - Description collection: Receive event configuration for EVENTS_RECEIVE[n] - 0x590 - read-write - 0x00000000 - - - CHEN0 - Enable subscription to IPC channel 0 - 0 - 0 - - - Disable - Disable events - 0 - - - Enable - Enable events - 1 - - - - - CHEN1 - Enable subscription to IPC channel 1 - 1 - 1 - - - Disable - Disable events - 0 - - - Enable - Enable events - 1 - - - - - CHEN2 - Enable subscription to IPC channel 2 - 2 - 2 - - - Disable - Disable events - 0 - - - Enable - Enable events - 1 - - - - - CHEN3 - Enable subscription to IPC channel 3 - 3 - 3 - - - Disable - Disable events - 0 - - - Enable - Enable events - 1 - - - - - CHEN4 - Enable subscription to IPC channel 4 - 4 - 4 - - - Disable - Disable events - 0 - - - Enable - Enable events - 1 - - - - - CHEN5 - Enable subscription to IPC channel 5 - 5 - 5 - - - Disable - Disable events - 0 - - - Enable - Enable events - 1 - - - - - CHEN6 - Enable subscription to IPC channel 6 - 6 - 6 - - - Disable - Disable events - 0 - - - Enable - Enable events - 1 - - - - - CHEN7 - Enable subscription to IPC channel 7 - 7 - 7 - - - Disable - Disable events - 0 - - - Enable - Enable events - 1 - - - - - CHEN8 - Enable subscription to IPC channel 8 - 8 - 8 - - - Disable - Disable events - 0 - - - Enable - Enable events - 1 - - - - - CHEN9 - Enable subscription to IPC channel 9 - 9 - 9 - - - Disable - Disable events - 0 - - - Enable - Enable events - 1 - - - - - CHEN10 - Enable subscription to IPC channel 10 - 10 - 10 - - - Disable - Disable events - 0 - - - Enable - Enable events - 1 - - - - - CHEN11 - Enable subscription to IPC channel 11 - 11 - 11 - - - Disable - Disable events - 0 - - - Enable - Enable events - 1 - - - - - CHEN12 - Enable subscription to IPC channel 12 - 12 - 12 - - - Disable - Disable events - 0 - - - Enable - Enable events - 1 - - - - - CHEN13 - Enable subscription to IPC channel 13 - 13 - 13 - - - Disable - Disable events - 0 - - - Enable - Enable events - 1 - - - - - CHEN14 - Enable subscription to IPC channel 14 - 14 - 14 - - - Disable - Disable events - 0 - - - Enable - Enable events - 1 - - - - - CHEN15 - Enable subscription to IPC channel 15 - 15 - 15 - - - Disable - Disable events - 0 - - - Enable - Enable events - 1 - - - - - - - 0x2 - 0x4 - GPMEM[%s] - Description collection: General purpose memory - 0x610 - read-write - 0x00000000 - - - GPMEM - General purpose memory - 0 - 31 - - - - - - - SPIM0_NS - Serial Peripheral Interface Master with EasyDMA - 0x41013000 - SPIM - - - - 0 - 0x1000 - registers - - - SERIAL0 - 19 - - SPIM - 0x20 - - - TASKS_START - Start SPI transaction - 0x010 - write-only - - - TASKS_START - Start SPI transaction - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STOP - Stop SPI transaction - 0x014 - write-only - - - TASKS_STOP - Stop SPI transaction - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_SUSPEND - Suspend SPI transaction - 0x01C - write-only - - - TASKS_SUSPEND - Suspend SPI transaction - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_RESUME - Resume SPI transaction - 0x020 - write-only - - - TASKS_RESUME - Resume SPI transaction - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - SUBSCRIBE_START - Subscribe configuration for task START - 0x090 - read-write - - - CHIDX - DPPI channel that task START will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_STOP - Subscribe configuration for task STOP - 0x094 - read-write - - - CHIDX - DPPI channel that task STOP will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_SUSPEND - Subscribe configuration for task SUSPEND - 0x09C - read-write - - - CHIDX - DPPI channel that task SUSPEND will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_RESUME - Subscribe configuration for task RESUME - 0x0A0 - read-write - - - CHIDX - DPPI channel that task RESUME will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - EVENTS_STOPPED - SPI transaction has stopped - 0x104 - read-write - - - EVENTS_STOPPED - SPI transaction has stopped - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_ENDRX - End of RXD buffer reached - 0x110 - read-write - - - EVENTS_ENDRX - End of RXD buffer reached - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_END - End of RXD buffer and TXD buffer reached - 0x118 - read-write - - - EVENTS_END - End of RXD buffer and TXD buffer reached - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_ENDTX - End of TXD buffer reached - 0x120 - read-write - - - EVENTS_ENDTX - End of TXD buffer reached - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_STARTED - Transaction started - 0x14C - read-write - - - EVENTS_STARTED - Transaction started - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - PUBLISH_STOPPED - Publish configuration for event STOPPED - 0x184 - read-write - - - CHIDX - DPPI channel that event STOPPED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_ENDRX - Publish configuration for event ENDRX - 0x190 - read-write - - - CHIDX - DPPI channel that event ENDRX will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_END - Publish configuration for event END - 0x198 - read-write - - - CHIDX - DPPI channel that event END will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_ENDTX - Publish configuration for event ENDTX - 0x1A0 - read-write - - - CHIDX - DPPI channel that event ENDTX will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_STARTED - Publish configuration for event STARTED - 0x1CC - read-write - - - CHIDX - DPPI channel that event STARTED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - SHORTS - Shortcuts between local events and tasks - 0x200 - read-write - - - END_START - Shortcut between event END and task START - 17 - 17 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - STOPPED - Write '1' to enable interrupt for event STOPPED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ENDRX - Write '1' to enable interrupt for event ENDRX - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - END - Write '1' to enable interrupt for event END - 6 - 6 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ENDTX - Write '1' to enable interrupt for event ENDTX - 8 - 8 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - STARTED - Write '1' to enable interrupt for event STARTED - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - STOPPED - Write '1' to disable interrupt for event STOPPED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ENDRX - Write '1' to disable interrupt for event ENDRX - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - END - Write '1' to disable interrupt for event END - 6 - 6 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ENDTX - Write '1' to disable interrupt for event ENDTX - 8 - 8 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - STARTED - Write '1' to disable interrupt for event STARTED - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - STALLSTAT - Stall status for EasyDMA RAM accesses. The fields in this register are set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU. - 0x400 - read-write - 0x00000000 - - - TX - Stall status for EasyDMA RAM reads - 0 - 0 - - - NOSTALL - No stall - 0 - - - STALL - A stall has occurred - 1 - - - - - RX - Stall status for EasyDMA RAM writes - 1 - 1 - - - NOSTALL - No stall - 0 - - - STALL - A stall has occurred - 1 - - - - - - - ENABLE - Enable SPIM - 0x500 - read-write - - - ENABLE - Enable or disable SPIM - 0 - 3 - - - Disabled - Disable SPIM - 0 - - - Enabled - Enable SPIM - 7 - - - - - - - PSEL - Unspecified - SPIM_PSEL - read-write - 0x508 - - SCK - Pin select for SCK - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - MOSI - Pin select for MOSI signal - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - MISO - Pin select for MISO signal - 0x008 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - CSN - Pin select for CSN - 0x00C - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - FREQUENCY - SPI frequency. Accuracy depends on the HFCLK source selected. - 0x524 - read-write - 0x04000000 - - - FREQUENCY - SPI master data rate - 0 - 31 - - - K125 - 125 kbps - 0x02000000 - - - K250 - 250 kbps - 0x04000000 - - - K500 - 500 kbps - 0x08000000 - - - M1 - 1 Mbps - 0x10000000 - - - M2 - 2 Mbps - 0x20000000 - - - M4 - 4 Mbps - 0x40000000 - - - M8 - 8 Mbps - 0x80000000 - - - M16 - 16 Mbps - 0x0A000000 - - - M32 - 32 Mbps - 0x14000000 - - - - - - - RXD - RXD EasyDMA channel - SPIM_RXD - read-write - 0x534 - - PTR - Data pointer - 0x000 - read-write - - - PTR - Data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in receive buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in receive buffer - 0 - 15 - - - - - AMOUNT - Number of bytes transferred in the last transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last transaction - 0 - 15 - - - - - LIST - EasyDMA list type - 0x00C - read-write - - - LIST - List type - 0 - 1 - - - Disabled - Disable EasyDMA list - 0 - - - ArrayList - Use array list - 1 - - - - - - - - TXD - TXD EasyDMA channel - SPIM_TXD - read-write - 0x544 - - PTR - Data pointer - 0x000 - read-write - - - PTR - Data pointer - 0 - 31 - - - - - MAXCNT - Number of bytes in transmit buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in transmit buffer - 0 - 15 - - - - - AMOUNT - Number of bytes transferred in the last transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last transaction - 0 - 15 - - - - - LIST - EasyDMA list type - 0x00C - read-write - - - LIST - List type - 0 - 1 - - - Disabled - Disable EasyDMA list - 0 - - - ArrayList - Use array list - 1 - - - - - - - - CONFIG - Configuration register - 0x554 - read-write - - - ORDER - Bit order - 0 - 0 - - - MsbFirst - Most significant bit shifted out first - 0 - - - LsbFirst - Least significant bit shifted out first - 1 - - - - - CPHA - Serial clock (SCK) phase - 1 - 1 - - - Leading - Sample on leading edge of clock, shift serial data on trailing edge - 0 - - - Trailing - Sample on trailing edge of clock, shift serial data on leading edge - 1 - - - - - CPOL - Serial clock (SCK) polarity - 2 - 2 - - - ActiveHigh - Active high - 0 - - - ActiveLow - Active low - 1 - - - - - - - IFTIMING - Unspecified - SPIM_IFTIMING - read-write - 0x560 - - RXDELAY - Sample delay for input serial data on MISO - 0x000 - read-write - 0x00000002 - - - RXDELAY - Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK. - 0 - 2 - - - - - CSNDUR - Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions - 0x004 - read-write - 0x00000002 - - - CSNDUR - Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns). - 0 - 7 - - - - - - CSNPOL - Polarity of CSN output - 0x568 - read-write - 0x00000000 - - - CSNPOL - Polarity of CSN output - 0 - 0 - - - LOW - Active low (idle state high) - 0 - - - HIGH - Active high (idle state low) - 1 - - - - - - - PSELDCX - Pin select for DCX signal - 0x56C - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - DCXCNT - DCX configuration - 0x570 - read-write - - - DCXCNT - This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates that all bytes are command bytes. - 0 - 3 - - - - - ORC - Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT - 0x5C0 - read-write - - - ORC - Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT. - 0 - 7 - - - - - - - SPIS0_NS - SPI Slave - 0x41013000 - SPIM0_NS - SPIS - - - - 0 - 0x1000 - registers - - - SERIAL0 - 19 - - SPIS - 0x20 - - - TASKS_ACQUIRE - Acquire SPI semaphore - 0x024 - write-only - - - TASKS_ACQUIRE - Acquire SPI semaphore - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_RELEASE - Release SPI semaphore, enabling the SPI slave to acquire it - 0x028 - write-only - - - TASKS_RELEASE - Release SPI semaphore, enabling the SPI slave to acquire it - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - SUBSCRIBE_ACQUIRE - Subscribe configuration for task ACQUIRE - 0x0A4 - read-write - - - CHIDX - DPPI channel that task ACQUIRE will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_RELEASE - Subscribe configuration for task RELEASE - 0x0A8 - read-write - - - CHIDX - DPPI channel that task RELEASE will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - EVENTS_END - Granted transaction completed - 0x104 - read-write - - - EVENTS_END - Granted transaction completed - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_ENDRX - End of RXD buffer reached - 0x110 - read-write - - - EVENTS_ENDRX - End of RXD buffer reached - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_ACQUIRED - Semaphore acquired - 0x128 - read-write - - - EVENTS_ACQUIRED - Semaphore acquired - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - PUBLISH_END - Publish configuration for event END - 0x184 - read-write - - - CHIDX - DPPI channel that event END will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_ENDRX - Publish configuration for event ENDRX - 0x190 - read-write - - - CHIDX - DPPI channel that event ENDRX will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_ACQUIRED - Publish configuration for event ACQUIRED - 0x1A8 - read-write - - - CHIDX - DPPI channel that event ACQUIRED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - SHORTS - Shortcuts between local events and tasks - 0x200 - read-write - - - END_ACQUIRE - Shortcut between event END and task ACQUIRE - 2 - 2 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - END - Write '1' to enable interrupt for event END - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ENDRX - Write '1' to enable interrupt for event ENDRX - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ACQUIRED - Write '1' to enable interrupt for event ACQUIRED - 10 - 10 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - END - Write '1' to disable interrupt for event END - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ENDRX - Write '1' to disable interrupt for event ENDRX - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ACQUIRED - Write '1' to disable interrupt for event ACQUIRED - 10 - 10 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - SEMSTAT - Semaphore status register - 0x400 - read-only - 0x00000001 - - - SEMSTAT - Semaphore status - 0 - 1 - - - Free - Semaphore is free - 0 - - - CPU - Semaphore is assigned to CPU - 1 - - - SPIS - Semaphore is assigned to SPI slave - 2 - - - CPUPending - Semaphore is assigned to SPI but a handover to the CPU is pending - 3 - - - - - - - STATUS - Status from last transaction - 0x440 - read-write - - - OVERREAD - TX buffer over-read detected, and prevented - 0 - 0 - - read - - NotPresent - Read: error not present - 0 - - - Present - Read: error present - 1 - - - - write - - Clear - Write: clear error on writing '1' - 1 - - - - - OVERFLOW - RX buffer overflow detected, and prevented - 1 - 1 - - read - - NotPresent - Read: error not present - 0 - - - Present - Read: error present - 1 - - - - write - - Clear - Write: clear error on writing '1' - 1 - - - - - - - ENABLE - Enable SPI slave - 0x500 - read-write - - - ENABLE - Enable or disable SPI slave - 0 - 3 - - - Disabled - Disable SPI slave - 0 - - - Enabled - Enable SPI slave - 2 - - - - - - - PSEL - Unspecified - SPIS_PSEL - read-write - 0x508 - - SCK - Pin select for SCK - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - MISO - Pin select for MISO signal - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - MOSI - Pin select for MOSI signal - 0x008 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - CSN - Pin select for CSN signal - 0x00C - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - RXD - Unspecified - SPIS_RXD - read-write - 0x534 - - PTR - RXD data pointer - 0x000 - read-write - - - PTR - RXD data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in receive buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in receive buffer - 0 - 15 - - - - - AMOUNT - Number of bytes received in last granted transaction - 0x008 - read-only - - - AMOUNT - Number of bytes received in the last granted transaction - 0 - 15 - - - - - LIST - EasyDMA list type - 0x00C - read-write - - - LIST - List type - 0 - 1 - - - Disabled - Disable EasyDMA list - 0 - - - ArrayList - Use array list - 1 - - - - - - - - TXD - Unspecified - SPIS_TXD - read-write - 0x544 - - PTR - TXD data pointer - 0x000 - read-write - - - PTR - TXD data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in transmit buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in transmit buffer - 0 - 15 - - - - - AMOUNT - Number of bytes transmitted in last granted transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transmitted in last granted transaction - 0 - 15 - - - - - LIST - EasyDMA list type - 0x00C - read-write - - - LIST - List type - 0 - 1 - - - Disabled - Disable EasyDMA list - 0 - - - ArrayList - Use array list - 1 - - - - - - - - CONFIG - Configuration register - 0x554 - read-write - - - ORDER - Bit order - 0 - 0 - - - MsbFirst - Most significant bit shifted out first - 0 - - - LsbFirst - Least significant bit shifted out first - 1 - - - - - CPHA - Serial clock (SCK) phase - 1 - 1 - - - Leading - Sample on leading edge of clock, shift serial data on trailing edge - 0 - - - Trailing - Sample on trailing edge of clock, shift serial data on leading edge - 1 - - - - - CPOL - Serial clock (SCK) polarity - 2 - 2 - - - ActiveHigh - Active high - 0 - - - ActiveLow - Active low - 1 - - - - - - - DEF - Default character. Character clocked out in case of an ignored transaction. - 0x55C - read-write - - - DEF - Default character. Character clocked out in case of an ignored transaction. - 0 - 7 - - - - - ORC - Over-read character - 0x5C0 - read-write - - - ORC - Over-read character. Character clocked out after an over-read of the transmit buffer. - 0 - 7 - - - - - - - TWIM0_NS - I2C compatible Two-Wire Master Interface with EasyDMA - 0x41013000 - SPIM0_NS - TWIM - - - - 0 - 0x1000 - registers - - - SERIAL0 - 19 - - TWIM - 0x20 - - - TASKS_STARTRX - Start TWI receive sequence - 0x000 - write-only - - - TASKS_STARTRX - Start TWI receive sequence - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STARTTX - Start TWI transmit sequence - 0x008 - write-only - - - TASKS_STARTTX - Start TWI transmit sequence - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STOP - Stop TWI transaction. Must be issued while the TWI master is not suspended. - 0x014 - write-only - - - TASKS_STOP - Stop TWI transaction. Must be issued while the TWI master is not suspended. - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_SUSPEND - Suspend TWI transaction - 0x01C - write-only - - - TASKS_SUSPEND - Suspend TWI transaction - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_RESUME - Resume TWI transaction - 0x020 - write-only - - - TASKS_RESUME - Resume TWI transaction - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - SUBSCRIBE_STARTRX - Subscribe configuration for task STARTRX - 0x080 - read-write - - - CHIDX - DPPI channel that task STARTRX will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_STARTTX - Subscribe configuration for task STARTTX - 0x088 - read-write - - - CHIDX - DPPI channel that task STARTTX will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_STOP - Subscribe configuration for task STOP - 0x094 - read-write - - - CHIDX - DPPI channel that task STOP will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_SUSPEND - Subscribe configuration for task SUSPEND - 0x09C - read-write - - - CHIDX - DPPI channel that task SUSPEND will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_RESUME - Subscribe configuration for task RESUME - 0x0A0 - read-write - - - CHIDX - DPPI channel that task RESUME will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - EVENTS_STOPPED - TWI stopped - 0x104 - read-write - - - EVENTS_STOPPED - TWI stopped - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_ERROR - TWI error - 0x124 - read-write - - - EVENTS_ERROR - TWI error - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_SUSPENDED - SUSPEND task has been issued, TWI traffic is now suspended. - 0x148 - read-write - - - EVENTS_SUSPENDED - SUSPEND task has been issued, TWI traffic is now suspended. - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_RXSTARTED - Receive sequence started - 0x14C - read-write - - - EVENTS_RXSTARTED - Receive sequence started - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_TXSTARTED - Transmit sequence started - 0x150 - read-write - - - EVENTS_TXSTARTED - Transmit sequence started - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_LASTRX - Byte boundary, starting to receive the last byte - 0x15C - read-write - - - EVENTS_LASTRX - Byte boundary, starting to receive the last byte - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_LASTTX - Byte boundary, starting to transmit the last byte - 0x160 - read-write - - - EVENTS_LASTTX - Byte boundary, starting to transmit the last byte - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - PUBLISH_STOPPED - Publish configuration for event STOPPED - 0x184 - read-write - - - CHIDX - DPPI channel that event STOPPED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_ERROR - Publish configuration for event ERROR - 0x1A4 - read-write - - - CHIDX - DPPI channel that event ERROR will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_SUSPENDED - Publish configuration for event SUSPENDED - 0x1C8 - read-write - - - CHIDX - DPPI channel that event SUSPENDED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_RXSTARTED - Publish configuration for event RXSTARTED - 0x1CC - read-write - - - CHIDX - DPPI channel that event RXSTARTED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_TXSTARTED - Publish configuration for event TXSTARTED - 0x1D0 - read-write - - - CHIDX - DPPI channel that event TXSTARTED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_LASTRX - Publish configuration for event LASTRX - 0x1DC - read-write - - - CHIDX - DPPI channel that event LASTRX will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_LASTTX - Publish configuration for event LASTTX - 0x1E0 - read-write - - - CHIDX - DPPI channel that event LASTTX will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - SHORTS - Shortcuts between local events and tasks - 0x200 - read-write - - - LASTTX_STARTRX - Shortcut between event LASTTX and task STARTRX - 7 - 7 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - LASTTX_SUSPEND - Shortcut between event LASTTX and task SUSPEND - 8 - 8 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - LASTTX_STOP - Shortcut between event LASTTX and task STOP - 9 - 9 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - LASTRX_STARTTX - Shortcut between event LASTRX and task STARTTX - 10 - 10 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - LASTRX_STOP - Shortcut between event LASTRX and task STOP - 12 - 12 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - - STOPPED - Enable or disable interrupt for event STOPPED - 1 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ERROR - Enable or disable interrupt for event ERROR - 9 - 9 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - SUSPENDED - Enable or disable interrupt for event SUSPENDED - 18 - 18 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RXSTARTED - Enable or disable interrupt for event RXSTARTED - 19 - 19 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TXSTARTED - Enable or disable interrupt for event TXSTARTED - 20 - 20 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - LASTRX - Enable or disable interrupt for event LASTRX - 23 - 23 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - LASTTX - Enable or disable interrupt for event LASTTX - 24 - 24 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - STOPPED - Write '1' to enable interrupt for event STOPPED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ERROR - Write '1' to enable interrupt for event ERROR - 9 - 9 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - SUSPENDED - Write '1' to enable interrupt for event SUSPENDED - 18 - 18 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RXSTARTED - Write '1' to enable interrupt for event RXSTARTED - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TXSTARTED - Write '1' to enable interrupt for event TXSTARTED - 20 - 20 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - LASTRX - Write '1' to enable interrupt for event LASTRX - 23 - 23 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - LASTTX - Write '1' to enable interrupt for event LASTTX - 24 - 24 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - STOPPED - Write '1' to disable interrupt for event STOPPED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ERROR - Write '1' to disable interrupt for event ERROR - 9 - 9 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - SUSPENDED - Write '1' to disable interrupt for event SUSPENDED - 18 - 18 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RXSTARTED - Write '1' to disable interrupt for event RXSTARTED - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TXSTARTED - Write '1' to disable interrupt for event TXSTARTED - 20 - 20 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - LASTRX - Write '1' to disable interrupt for event LASTRX - 23 - 23 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - LASTTX - Write '1' to disable interrupt for event LASTTX - 24 - 24 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - ERRORSRC - Error source - 0x4C4 - read-write - oneToClear - - - OVERRUN - Overrun error - 0 - 0 - - - NotReceived - Error did not occur - 0 - - - Received - Error occurred - 1 - - - - - ANACK - NACK received after sending the address (write '1' to clear) - 1 - 1 - - - NotReceived - Error did not occur - 0 - - - Received - Error occurred - 1 - - - - - DNACK - NACK received after sending a data byte (write '1' to clear) - 2 - 2 - - - NotReceived - Error did not occur - 0 - - - Received - Error occurred - 1 - - - - - - - ENABLE - Enable TWIM - 0x500 - read-write - - - ENABLE - Enable or disable TWIM - 0 - 3 - - - Disabled - Disable TWIM - 0 - - - Enabled - Enable TWIM - 6 - - - - - - - PSEL - Unspecified - TWIM_PSEL - read-write - 0x508 - - SCL - Pin select for SCL signal - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - SDA - Pin select for SDA signal - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - FREQUENCY - TWI frequency. Accuracy depends on the HFCLK source selected. - 0x524 - read-write - 0x04000000 - - - FREQUENCY - TWI master clock frequency - 0 - 31 - - - K100 - 100 kbps - 0x01980000 - - - K250 - 250 kbps - 0x04000000 - - - K400 - 400 kbps - 0x06400000 - - - K1000 - 1000 kbps - 0x0FF00000 - - - - - - - RXD - RXD EasyDMA channel - TWIM_RXD - read-write - 0x534 - - PTR - Data pointer - 0x000 - read-write - - - PTR - Data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in receive buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in receive buffer - 0 - 15 - - - - - AMOUNT - Number of bytes transferred in the last transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. - 0 - 15 - - - - - LIST - EasyDMA list type - 0x00C - read-write - - - LIST - List type - 0 - 2 - - - Disabled - Disable EasyDMA list - 0 - - - ArrayList - Use array list - 1 - - - - - - - - TXD - TXD EasyDMA channel - TWIM_TXD - read-write - 0x544 - - PTR - Data pointer - 0x000 - read-write - - - PTR - Data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in transmit buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in transmit buffer - 0 - 15 - - - - - AMOUNT - Number of bytes transferred in the last transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. - 0 - 15 - - - - - LIST - EasyDMA list type - 0x00C - read-write - - - LIST - List type - 0 - 2 - - - Disabled - Disable EasyDMA list - 0 - - - ArrayList - Use array list - 1 - - - - - - - - ADDRESS - Address used in the TWI transfer - 0x588 - read-write - - - ADDRESS - Address used in the TWI transfer - 0 - 6 - - - - - - - TWIS0_NS - I2C compatible Two-Wire Slave Interface with EasyDMA - 0x41013000 - SPIM0_NS - TWIS - - - - 0 - 0x1000 - registers - - - SERIAL0 - 19 - - TWIS - 0x20 - - - TASKS_STOP - Stop TWI transaction - 0x014 - write-only - - - TASKS_STOP - Stop TWI transaction - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_SUSPEND - Suspend TWI transaction - 0x01C - write-only - - - TASKS_SUSPEND - Suspend TWI transaction - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_RESUME - Resume TWI transaction - 0x020 - write-only - - - TASKS_RESUME - Resume TWI transaction - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_PREPARERX - Prepare the TWI slave to respond to a write command - 0x030 - write-only - - - TASKS_PREPARERX - Prepare the TWI slave to respond to a write command - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_PREPARETX - Prepare the TWI slave to respond to a read command - 0x034 - write-only - - - TASKS_PREPARETX - Prepare the TWI slave to respond to a read command - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - SUBSCRIBE_STOP - Subscribe configuration for task STOP - 0x094 - read-write - - - CHIDX - DPPI channel that task STOP will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_SUSPEND - Subscribe configuration for task SUSPEND - 0x09C - read-write - - - CHIDX - DPPI channel that task SUSPEND will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_RESUME - Subscribe configuration for task RESUME - 0x0A0 - read-write - - - CHIDX - DPPI channel that task RESUME will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_PREPARERX - Subscribe configuration for task PREPARERX - 0x0B0 - read-write - - - CHIDX - DPPI channel that task PREPARERX will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_PREPARETX - Subscribe configuration for task PREPARETX - 0x0B4 - read-write - - - CHIDX - DPPI channel that task PREPARETX will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - EVENTS_STOPPED - TWI stopped - 0x104 - read-write - - - EVENTS_STOPPED - TWI stopped - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_ERROR - TWI error - 0x124 - read-write - - - EVENTS_ERROR - TWI error - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_RXSTARTED - Receive sequence started - 0x14C - read-write - - - EVENTS_RXSTARTED - Receive sequence started - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_TXSTARTED - Transmit sequence started - 0x150 - read-write - - - EVENTS_TXSTARTED - Transmit sequence started - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_WRITE - Write command received - 0x164 - read-write - - - EVENTS_WRITE - Write command received - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_READ - Read command received - 0x168 - read-write - - - EVENTS_READ - Read command received - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - PUBLISH_STOPPED - Publish configuration for event STOPPED - 0x184 - read-write - - - CHIDX - DPPI channel that event STOPPED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_ERROR - Publish configuration for event ERROR - 0x1A4 - read-write - - - CHIDX - DPPI channel that event ERROR will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_RXSTARTED - Publish configuration for event RXSTARTED - 0x1CC - read-write - - - CHIDX - DPPI channel that event RXSTARTED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_TXSTARTED - Publish configuration for event TXSTARTED - 0x1D0 - read-write - - - CHIDX - DPPI channel that event TXSTARTED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_WRITE - Publish configuration for event WRITE - 0x1E4 - read-write - - - CHIDX - DPPI channel that event WRITE will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_READ - Publish configuration for event READ - 0x1E8 - read-write - - - CHIDX - DPPI channel that event READ will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - SHORTS - Shortcuts between local events and tasks - 0x200 - read-write - - - WRITE_SUSPEND - Shortcut between event WRITE and task SUSPEND - 13 - 13 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - READ_SUSPEND - Shortcut between event READ and task SUSPEND - 14 - 14 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - - STOPPED - Enable or disable interrupt for event STOPPED - 1 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ERROR - Enable or disable interrupt for event ERROR - 9 - 9 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RXSTARTED - Enable or disable interrupt for event RXSTARTED - 19 - 19 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TXSTARTED - Enable or disable interrupt for event TXSTARTED - 20 - 20 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - WRITE - Enable or disable interrupt for event WRITE - 25 - 25 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - READ - Enable or disable interrupt for event READ - 26 - 26 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - STOPPED - Write '1' to enable interrupt for event STOPPED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ERROR - Write '1' to enable interrupt for event ERROR - 9 - 9 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RXSTARTED - Write '1' to enable interrupt for event RXSTARTED - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TXSTARTED - Write '1' to enable interrupt for event TXSTARTED - 20 - 20 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - WRITE - Write '1' to enable interrupt for event WRITE - 25 - 25 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - READ - Write '1' to enable interrupt for event READ - 26 - 26 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - STOPPED - Write '1' to disable interrupt for event STOPPED - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ERROR - Write '1' to disable interrupt for event ERROR - 9 - 9 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RXSTARTED - Write '1' to disable interrupt for event RXSTARTED - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TXSTARTED - Write '1' to disable interrupt for event TXSTARTED - 20 - 20 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - WRITE - Write '1' to disable interrupt for event WRITE - 25 - 25 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - READ - Write '1' to disable interrupt for event READ - 26 - 26 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - ERRORSRC - Error source - 0x4D0 - read-write - oneToClear - - - OVERFLOW - RX buffer overflow detected, and prevented - 0 - 0 - - - NotDetected - Error did not occur - 0 - - - Detected - Error occurred - 1 - - - - - DNACK - NACK sent after receiving a data byte - 2 - 2 - - - NotReceived - Error did not occur - 0 - - - Received - Error occurred - 1 - - - - - OVERREAD - TX buffer over-read detected, and prevented - 3 - 3 - - - NotDetected - Error did not occur - 0 - - - Detected - Error occurred - 1 - - - - - - - MATCH - Status register indicating which address had a match - 0x4D4 - read-only - - - MATCH - Indication of which address in {ADDRESS} that matched the incoming address - 0 - 0 - - - - - ENABLE - Enable TWIS - 0x500 - read-write - - - ENABLE - Enable or disable TWIS - 0 - 3 - - - Disabled - Disable TWIS - 0 - - - Enabled - Enable TWIS - 9 - - - - - - - PSEL - Unspecified - TWIS_PSEL - read-write - 0x508 - - SCL - Pin select for SCL signal - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - SDA - Pin select for SDA signal - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - RXD - RXD EasyDMA channel - TWIS_RXD - read-write - 0x534 - - PTR - RXD Data pointer - 0x000 - read-write - - - PTR - RXD Data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in RXD buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in RXD buffer - 0 - 15 - - - - - AMOUNT - Number of bytes transferred in the last RXD transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last RXD transaction - 0 - 15 - - - - - LIST - EasyDMA list type - 0x00C - read-write - - - LIST - List type - 0 - 1 - - - Disabled - Disable EasyDMA list - 0 - - - ArrayList - Use array list - 1 - - - - - - - - TXD - TXD EasyDMA channel - TWIS_TXD - read-write - 0x544 - - PTR - TXD Data pointer - 0x000 - read-write - - - PTR - TXD Data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in TXD buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in TXD buffer - 0 - 15 - - - - - AMOUNT - Number of bytes transferred in the last TXD transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last TXD transaction - 0 - 15 - - - - - LIST - EasyDMA list type - 0x00C - read-write - - - LIST - List type - 0 - 1 - - - Disabled - Disable EasyDMA list - 0 - - - ArrayList - Use array list - 1 - - - - - - - - 0x2 - 0x4 - ADDRESS[%s] - Description collection: TWI slave address n - 0x588 - read-write - - - ADDRESS - TWI slave address - 0 - 6 - - - - - CONFIG - Configuration register for the address match mechanism - 0x594 - read-write - 0x00000001 - - - ADDRESS0 - Enable or disable address matching on ADDRESS[0] - 0 - 0 - - - Disabled - Disabled - 0 - - - Enabled - Enabled - 1 - - - - - ADDRESS1 - Enable or disable address matching on ADDRESS[1] - 1 - 1 - - - Disabled - Disabled - 0 - - - Enabled - Enabled - 1 - - - - - - - ORC - Over-read character. Character sent out in case of an over-read of the transmit buffer. - 0x5C0 - read-write - - - ORC - Over-read character. Character sent out in case of an over-read of the transmit buffer. - 0 - 7 - - - - - - - UARTE0_NS - UART with EasyDMA - 0x41013000 - SPIM0_NS - UARTE - - - - 0 - 0x1000 - registers - - - SERIAL0 - 19 - - UARTE - 0x20 - - - TASKS_STARTRX - Start UART receiver - 0x000 - write-only - - - TASKS_STARTRX - Start UART receiver - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STOPRX - Stop UART receiver - 0x004 - write-only - - - TASKS_STOPRX - Stop UART receiver - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STARTTX - Start UART transmitter - 0x008 - write-only - - - TASKS_STARTTX - Start UART transmitter - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_STOPTX - Stop UART transmitter - 0x00C - write-only - - - TASKS_STOPTX - Stop UART transmitter - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_FLUSHRX - Flush RX FIFO into RX buffer - 0x02C - write-only - - - TASKS_FLUSHRX - Flush RX FIFO into RX buffer - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - SUBSCRIBE_STARTRX - Subscribe configuration for task STARTRX - 0x080 - read-write - - - CHIDX - DPPI channel that task STARTRX will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_STOPRX - Subscribe configuration for task STOPRX - 0x084 - read-write - - - CHIDX - DPPI channel that task STOPRX will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_STARTTX - Subscribe configuration for task STARTTX - 0x088 - read-write - - - CHIDX - DPPI channel that task STARTTX will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_STOPTX - Subscribe configuration for task STOPTX - 0x08C - read-write - - - CHIDX - DPPI channel that task STOPTX will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_FLUSHRX - Subscribe configuration for task FLUSHRX - 0x0AC - read-write - - - CHIDX - DPPI channel that task FLUSHRX will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - EVENTS_CTS - CTS is activated (set low). Clear To Send. - 0x100 - read-write - - - EVENTS_CTS - CTS is activated (set low). Clear To Send. - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_NCTS - CTS is deactivated (set high). Not Clear To Send. - 0x104 - read-write - - - EVENTS_NCTS - CTS is deactivated (set high). Not Clear To Send. - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_RXDRDY - Data received in RXD (but potentially not yet transferred to Data RAM) - 0x108 - read-write - - - EVENTS_RXDRDY - Data received in RXD (but potentially not yet transferred to Data RAM) - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_ENDRX - Receive buffer is filled up - 0x110 - read-write - - - EVENTS_ENDRX - Receive buffer is filled up - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_TXDRDY - Data sent from TXD - 0x11C - read-write - - - EVENTS_TXDRDY - Data sent from TXD - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_ENDTX - Last TX byte transmitted - 0x120 - read-write - - - EVENTS_ENDTX - Last TX byte transmitted - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_ERROR - Error detected - 0x124 - read-write - - - EVENTS_ERROR - Error detected - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_RXTO - Receiver timeout - 0x144 - read-write - - - EVENTS_RXTO - Receiver timeout - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_RXSTARTED - UART receiver has started - 0x14C - read-write - - - EVENTS_RXSTARTED - UART receiver has started - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_TXSTARTED - UART transmitter has started - 0x150 - read-write - - - EVENTS_TXSTARTED - UART transmitter has started - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_TXSTOPPED - Transmitter stopped - 0x158 - read-write - - - EVENTS_TXSTOPPED - Transmitter stopped - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - PUBLISH_CTS - Publish configuration for event CTS - 0x180 - read-write - - - CHIDX - DPPI channel that event CTS will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_NCTS - Publish configuration for event NCTS - 0x184 - read-write - - - CHIDX - DPPI channel that event NCTS will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_RXDRDY - Publish configuration for event RXDRDY - 0x188 - read-write - - - CHIDX - DPPI channel that event RXDRDY will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_ENDRX - Publish configuration for event ENDRX - 0x190 - read-write - - - CHIDX - DPPI channel that event ENDRX will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_TXDRDY - Publish configuration for event TXDRDY - 0x19C - read-write - - - CHIDX - DPPI channel that event TXDRDY will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_ENDTX - Publish configuration for event ENDTX - 0x1A0 - read-write - - - CHIDX - DPPI channel that event ENDTX will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_ERROR - Publish configuration for event ERROR - 0x1A4 - read-write - - - CHIDX - DPPI channel that event ERROR will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_RXTO - Publish configuration for event RXTO - 0x1C4 - read-write - - - CHIDX - DPPI channel that event RXTO will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_RXSTARTED - Publish configuration for event RXSTARTED - 0x1CC - read-write - - - CHIDX - DPPI channel that event RXSTARTED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_TXSTARTED - Publish configuration for event TXSTARTED - 0x1D0 - read-write - - - CHIDX - DPPI channel that event TXSTARTED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_TXSTOPPED - Publish configuration for event TXSTOPPED - 0x1D8 - read-write - - - CHIDX - DPPI channel that event TXSTOPPED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - SHORTS - Shortcuts between local events and tasks - 0x200 - read-write - - - ENDRX_STARTRX - Shortcut between event ENDRX and task STARTRX - 5 - 5 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - ENDRX_STOPRX - Shortcut between event ENDRX and task STOPRX - 6 - 6 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - - CTS - Enable or disable interrupt for event CTS - 0 - 0 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - NCTS - Enable or disable interrupt for event NCTS - 1 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RXDRDY - Enable or disable interrupt for event RXDRDY - 2 - 2 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ENDRX - Enable or disable interrupt for event ENDRX - 4 - 4 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TXDRDY - Enable or disable interrupt for event TXDRDY - 7 - 7 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ENDTX - Enable or disable interrupt for event ENDTX - 8 - 8 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - ERROR - Enable or disable interrupt for event ERROR - 9 - 9 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RXTO - Enable or disable interrupt for event RXTO - 17 - 17 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RXSTARTED - Enable or disable interrupt for event RXSTARTED - 19 - 19 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TXSTARTED - Enable or disable interrupt for event TXSTARTED - 20 - 20 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TXSTOPPED - Enable or disable interrupt for event TXSTOPPED - 22 - 22 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - CTS - Write '1' to enable interrupt for event CTS - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - NCTS - Write '1' to enable interrupt for event NCTS - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RXDRDY - Write '1' to enable interrupt for event RXDRDY - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ENDRX - Write '1' to enable interrupt for event ENDRX - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TXDRDY - Write '1' to enable interrupt for event TXDRDY - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ENDTX - Write '1' to enable interrupt for event ENDTX - 8 - 8 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ERROR - Write '1' to enable interrupt for event ERROR - 9 - 9 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RXTO - Write '1' to enable interrupt for event RXTO - 17 - 17 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RXSTARTED - Write '1' to enable interrupt for event RXSTARTED - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TXSTARTED - Write '1' to enable interrupt for event TXSTARTED - 20 - 20 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TXSTOPPED - Write '1' to enable interrupt for event TXSTOPPED - 22 - 22 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - CTS - Write '1' to disable interrupt for event CTS - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - NCTS - Write '1' to disable interrupt for event NCTS - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RXDRDY - Write '1' to disable interrupt for event RXDRDY - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ENDRX - Write '1' to disable interrupt for event ENDRX - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TXDRDY - Write '1' to disable interrupt for event TXDRDY - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ENDTX - Write '1' to disable interrupt for event ENDTX - 8 - 8 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ERROR - Write '1' to disable interrupt for event ERROR - 9 - 9 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RXTO - Write '1' to disable interrupt for event RXTO - 17 - 17 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RXSTARTED - Write '1' to disable interrupt for event RXSTARTED - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TXSTARTED - Write '1' to disable interrupt for event TXSTARTED - 20 - 20 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TXSTOPPED - Write '1' to disable interrupt for event TXSTOPPED - 22 - 22 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - ERRORSRC - Error source - 0x480 - read-write - oneToClear - - - OVERRUN - Overrun error - 0 - 0 - - read - - NotPresent - Read: error not present - 0 - - - Present - Read: error present - 1 - - - - - PARITY - Parity error - 1 - 1 - - read - - NotPresent - Read: error not present - 0 - - - Present - Read: error present - 1 - - - - - FRAMING - Framing error occurred - 2 - 2 - - read - - NotPresent - Read: error not present - 0 - - - Present - Read: error present - 1 - - - - - BREAK - Break condition - 3 - 3 - - read - - NotPresent - Read: error not present - 0 - - - Present - Read: error present - 1 - - - - - - - ENABLE - Enable UART - 0x500 - read-write - - - ENABLE - Enable or disable UARTE - 0 - 3 - - - Disabled - Disable UARTE - 0 - - - Enabled - Enable UARTE - 8 - - - - - - - PSEL - Unspecified - UARTE_PSEL - read-write - 0x508 - - RTS - Pin select for RTS signal - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - TXD - Pin select for TXD signal - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - CTS - Pin select for CTS signal - 0x008 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - RXD - Pin select for RXD signal - 0x00C - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - BAUDRATE - Baud rate. Accuracy depends on the HFCLK source selected. - 0x524 - read-write - 0x04000000 - - - BAUDRATE - Baud rate - 0 - 31 - - - Baud1200 - 1200 baud (actual rate: 1205) - 0x0004F000 - - - Baud2400 - 2400 baud (actual rate: 2396) - 0x0009D000 - - - Baud4800 - 4800 baud (actual rate: 4808) - 0x0013B000 - - - Baud9600 - 9600 baud (actual rate: 9598) - 0x00275000 - - - Baud14400 - 14400 baud (actual rate: 14401) - 0x003AF000 - - - Baud19200 - 19200 baud (actual rate: 19208) - 0x004EA000 - - - Baud28800 - 28800 baud (actual rate: 28777) - 0x0075C000 - - - Baud31250 - 31250 baud - 0x00800000 - - - Baud38400 - 38400 baud (actual rate: 38369) - 0x009D0000 - - - Baud56000 - 56000 baud (actual rate: 55944) - 0x00E50000 - - - Baud57600 - 57600 baud (actual rate: 57554) - 0x00EB0000 - - - Baud76800 - 76800 baud (actual rate: 76923) - 0x013A9000 - - - Baud115200 - 115200 baud (actual rate: 115108) - 0x01D60000 - - - Baud230400 - 230400 baud (actual rate: 231884) - 0x03B00000 - - - Baud250000 - 250000 baud - 0x04000000 - - - Baud460800 - 460800 baud (actual rate: 457143) - 0x07400000 - - - Baud921600 - 921600 baud (actual rate: 941176) - 0x0F000000 - - - Baud1M - 1 megabaud - 0x10000000 - - - - - - - RXD - RXD EasyDMA channel - UARTE_RXD - read-write - 0x534 - - PTR - Data pointer - 0x000 - read-write - - - PTR - Data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in receive buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in receive buffer - 0 - 15 - - - - - AMOUNT - Number of bytes transferred in the last transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last transaction - 0 - 15 - - - - - - TXD - TXD EasyDMA channel - UARTE_TXD - read-write - 0x544 - - PTR - Data pointer - 0x000 - read-write - - - PTR - Data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in transmit buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in transmit buffer - 0 - 15 - - - - - AMOUNT - Number of bytes transferred in the last transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last transaction - 0 - 15 - - - - - - CONFIG - Configuration of parity and hardware flow control - 0x56C - read-write - - - HWFC - Hardware flow control - 0 - 0 - - - Disabled - Disabled - 0 - - - Enabled - Enabled - 1 - - - - - PARITY - Parity - 1 - 3 - - - Excluded - Exclude parity bit - 0x0 - - - Included - Include even parity bit - 0x7 - - - - - STOP - Stop bits - 4 - 4 - - - One - One stop bit - 0 - - - Two - Two stop bits - 1 - - - - - PARITYTYPE - Even or odd parity type - 8 - 8 - - - Even - Even parity - 0 - - - Odd - Odd parity - 1 - - - - - - - - - EGU0_NS - Event generator unit - 0x41014000 - EGU - - - - 0 - 0x1000 - registers - - - EGU0 - 20 - - EGU - 0x20 - - - 0x10 - 0x4 - TASKS_TRIGGER[%s] - Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event - 0x000 - write-only - - - TASKS_TRIGGER - Trigger n for triggering the corresponding TRIGGERED[n] event - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - 0x10 - 0x4 - SUBSCRIBE_TRIGGER[%s] - Description collection: Subscribe configuration for task TRIGGER[n] - 0x080 - read-write - - - CHIDX - DPPI channel that task TRIGGER[n] will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - 0x10 - 0x4 - EVENTS_TRIGGERED[%s] - Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task - 0x100 - read-write - - - EVENTS_TRIGGERED - Event number n generated by triggering the corresponding TRIGGER[n] task - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - 0x10 - 0x4 - PUBLISH_TRIGGERED[%s] - Description collection: Publish configuration for event TRIGGERED[n] - 0x180 - read-write - - - CHIDX - DPPI channel that event TRIGGERED[n] will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - - TRIGGERED0 - Enable or disable interrupt for event TRIGGERED[0] - 0 - 0 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED1 - Enable or disable interrupt for event TRIGGERED[1] - 1 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED2 - Enable or disable interrupt for event TRIGGERED[2] - 2 - 2 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED3 - Enable or disable interrupt for event TRIGGERED[3] - 3 - 3 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED4 - Enable or disable interrupt for event TRIGGERED[4] - 4 - 4 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED5 - Enable or disable interrupt for event TRIGGERED[5] - 5 - 5 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED6 - Enable or disable interrupt for event TRIGGERED[6] - 6 - 6 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED7 - Enable or disable interrupt for event TRIGGERED[7] - 7 - 7 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED8 - Enable or disable interrupt for event TRIGGERED[8] - 8 - 8 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED9 - Enable or disable interrupt for event TRIGGERED[9] - 9 - 9 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED10 - Enable or disable interrupt for event TRIGGERED[10] - 10 - 10 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED11 - Enable or disable interrupt for event TRIGGERED[11] - 11 - 11 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED12 - Enable or disable interrupt for event TRIGGERED[12] - 12 - 12 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED13 - Enable or disable interrupt for event TRIGGERED[13] - 13 - 13 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED14 - Enable or disable interrupt for event TRIGGERED[14] - 14 - 14 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED15 - Enable or disable interrupt for event TRIGGERED[15] - 15 - 15 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - TRIGGERED0 - Write '1' to enable interrupt for event TRIGGERED[0] - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TRIGGERED1 - Write '1' to enable interrupt for event TRIGGERED[1] - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TRIGGERED2 - Write '1' to enable interrupt for event TRIGGERED[2] - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TRIGGERED3 - Write '1' to enable interrupt for event TRIGGERED[3] - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TRIGGERED4 - Write '1' to enable interrupt for event TRIGGERED[4] - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TRIGGERED5 - Write '1' to enable interrupt for event TRIGGERED[5] - 5 - 5 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TRIGGERED6 - Write '1' to enable interrupt for event TRIGGERED[6] - 6 - 6 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TRIGGERED7 - Write '1' to enable interrupt for event TRIGGERED[7] - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TRIGGERED8 - Write '1' to enable interrupt for event TRIGGERED[8] - 8 - 8 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TRIGGERED9 - Write '1' to enable interrupt for event TRIGGERED[9] - 9 - 9 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TRIGGERED10 - Write '1' to enable interrupt for event TRIGGERED[10] - 10 - 10 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TRIGGERED11 - Write '1' to enable interrupt for event TRIGGERED[11] - 11 - 11 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TRIGGERED12 - Write '1' to enable interrupt for event TRIGGERED[12] - 12 - 12 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TRIGGERED13 - Write '1' to enable interrupt for event TRIGGERED[13] - 13 - 13 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TRIGGERED14 - Write '1' to enable interrupt for event TRIGGERED[14] - 14 - 14 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TRIGGERED15 - Write '1' to enable interrupt for event TRIGGERED[15] - 15 - 15 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - TRIGGERED0 - Write '1' to disable interrupt for event TRIGGERED[0] - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TRIGGERED1 - Write '1' to disable interrupt for event TRIGGERED[1] - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TRIGGERED2 - Write '1' to disable interrupt for event TRIGGERED[2] - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TRIGGERED3 - Write '1' to disable interrupt for event TRIGGERED[3] - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TRIGGERED4 - Write '1' to disable interrupt for event TRIGGERED[4] - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TRIGGERED5 - Write '1' to disable interrupt for event TRIGGERED[5] - 5 - 5 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TRIGGERED6 - Write '1' to disable interrupt for event TRIGGERED[6] - 6 - 6 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TRIGGERED7 - Write '1' to disable interrupt for event TRIGGERED[7] - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TRIGGERED8 - Write '1' to disable interrupt for event TRIGGERED[8] - 8 - 8 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TRIGGERED9 - Write '1' to disable interrupt for event TRIGGERED[9] - 9 - 9 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TRIGGERED10 - Write '1' to disable interrupt for event TRIGGERED[10] - 10 - 10 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TRIGGERED11 - Write '1' to disable interrupt for event TRIGGERED[11] - 11 - 11 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TRIGGERED12 - Write '1' to disable interrupt for event TRIGGERED[12] - 12 - 12 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TRIGGERED13 - Write '1' to disable interrupt for event TRIGGERED[13] - 13 - 13 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TRIGGERED14 - Write '1' to disable interrupt for event TRIGGERED[14] - 14 - 14 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TRIGGERED15 - Write '1' to disable interrupt for event TRIGGERED[15] - 15 - 15 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - - - RTC1_NS - Real-time counter 1 - 0x41016000 - - - - RTC1 - 22 - - - - TIMER1_NS - Timer/Counter 1 - 0x41018000 - - - - TIMER1 - 24 - - - - TIMER2_NS - Timer/Counter 2 - 0x41019000 - - - - TIMER2 - 25 - - - - SWI0_NS - Software interrupt 0 - 0x4101A000 - SWI - - - - 0 - 0x1000 - registers - - - SWI0 - 26 - - SWI - 0x20 - - - UNUSED - Unused. - 0x000 - 0x00000000 - read-only - - - - - SWI1_NS - Software interrupt 1 - 0x4101B000 - - - - SWI1 - 27 - - - - SWI2_NS - Software interrupt 2 - 0x4101C000 - - - - SWI2 - 28 - - - - SWI3_NS - Software interrupt 3 - 0x4101D000 - - - - SWI3 - 29 - - - - APPMUTEX_NS - MUTEX 0 - 0x40030000 - MUTEX - - - - 0 - 0x1000 - registers - - MUTEX - 0x20 - - - 0x10 - 0x4 - MUTEX[%s] - Description collection: Mutex register - 0x400 - read-write - - - MUTEX - Mutex register n - 0 - 0 - - - Unlocked - Mutex n is in unlocked state - 0 - - - Locked - Mutex n is in locked state - 1 - - - - - - - - - APPMUTEX_S - MUTEX 1 - 0x50030000 - - - - - ACL_NS - Access control lists - 0x41080000 - ACL - - - - 0 - 0x1000 - registers - - ACL - 0x20 - - - 8 - 0x010 - ACL[%s] - Unspecified - ACL_ACL - read-write - 0x800 - - ADDR - Description cluster: Start address of region to protect. The start address must be word-aligned. - 0x000 - read-writeOnce - 0x00000000 - - - ADDR - Start address of flash region n. The start address must point to a flash page boundary. - 0 - 31 - - - - - SIZE - Description cluster: Size of region to protect counting from address ACL[n].ADDR. Writing a '0' has no effect. - 0x004 - read-writeOnce - 0x00000000 - - - SIZE - Size of flash region n in bytes. Must be a multiple of the flash page size. - 0 - 31 - - - - - PERM - Description cluster: Access permissions for region n as defined by start address ACL[n].ADDR and size ACL[n].SIZE - 0x008 - read-writeOnce - 0x00000000 - - - WRITE - Configure write and erase permissions for region n. Writing a '0' has no effect. - 1 - 1 - - - Enable - Allow write and erase instructions to region n. - 0 - - - Disable - Block write and erase instructions to region n. - 1 - - - - - READ - Configure read permissions for region n. Writing a '0' has no effect. - 2 - 2 - - - Enable - Allow read instructions to region n. - 0 - - - Disable - Block read instructions to region n. - 1 - - - - - - - - - - NVMC_NS - Non-volatile memory controller - 0x41080000 - ACL_NS - NVMC - - - - 0 - 0x1000 - registers - - NVMC - 0x20 - - - READY - Ready flag - 0x400 - read-only - 0x00000001 - - - READY - NVMC is ready or busy - 0 - 0 - - - Busy - NVMC is busy (ongoing write or erase operation) - 0 - - - Ready - NVMC is ready - 1 - - - - - - - READYNEXT - Ready flag - 0x408 - read-only - 0x00000001 - - - READYNEXT - NVMC can accept a new write operation - 0 - 0 - - - Busy - NVMC cannot accept any write operation - 0 - - - Ready - NVMC is ready - 1 - - - - - - - CONFIG - Configuration register - 0x504 - read-write - - - - WEN - Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. - 0 - 2 - - - Ren - Read only access - 0 - - - Wen - Write enabled - 1 - - - Een - Erase enabled - 2 - - - PEen - Partial erase enabled - 4 - - - - - - - ERASEALL - Register for erasing all non-volatile user memory - 0x50C - write-only - - - - ERASEALL - Erase all non-volatile memory including UICR registers. Before the non-volatile memory can be erased, erasing must be enabled by setting CONFIG.WEN=Een. - 0 - 0 - - - NoOperation - No operation - 0 - - - Erase - Start chip erase - 1 - - - - - - - ERASEPAGEPARTIALCFG - Register for partial erase configuration - 0x51C - read-write - 0x0000000A - - - - DURATION - Duration of the partial erase in milliseconds - 0 - 6 - - - - - ICACHECNF - I-code cache configuration register - 0x540 - read-write - 0x00000000 - - - - CACHEEN - Cache enable - 0 - 0 - - - Disabled - Disable cache. Invalidates all cache entries. - 0 - - - Enabled - Enable cache - 1 - - - - - CACHEPROFEN - Cache profiling enable - 8 - 8 - - - Disabled - Disable cache profiling - 0 - - - Enabled - Enable cache profiling - 1 - - - - - - - IHIT - I-code cache hit counter - 0x548 - read-write - - - - HITS - Number of cache hits Write zero to clear - 0 - 31 - - - - - IMISS - I-code cache miss counter - 0x54C - read-write - - - - MISSES - Number of cache misses Write zero to clear - 0 - 31 - - - - - - - VMC_NS - Volatile Memory controller - 0x41081000 - VMC - - - - 0 - 0x1000 - registers - - VMC - 0x20 - - - 4 - 0x010 - RAM[%s] - Unspecified - VMC_RAM - read-write - 0x600 - - POWER - Description cluster: RAM[n] power control register - 0x000 - read-write - 0x0000FFFF - - - S0POWER - Keep RAM section S0 of RAM[n] on or off in System ON mode - 0 - 0 - - - Off - Off - 0 - - - On - On - 1 - - - - - S1POWER - Keep RAM section S1 of RAM[n] on or off in System ON mode - 1 - 1 - - - Off - Off - 0 - - - On - On - 1 - - - - - S2POWER - Keep RAM section S2 of RAM[n] on or off in System ON mode - 2 - 2 - - - Off - Off - 0 - - - On - On - 1 - - - - - S3POWER - Keep RAM section S3 of RAM[n] on or off in System ON mode - 3 - 3 - - - Off - Off - 0 - - - On - On - 1 - - - - - S0RETENTION - Keep retention on RAM section S0 of RAM[n] when RAM section is switched off - 16 - 16 - - - Off - Off - 0 - - - On - On - 1 - - - - - S1RETENTION - Keep retention on RAM section S1 of RAM[n] when RAM section is switched off - 17 - 17 - - - Off - Off - 0 - - - On - On - 1 - - - - - S2RETENTION - Keep retention on RAM section S2 of RAM[n] when RAM section is switched off - 18 - 18 - - - Off - Off - 0 - - - On - On - 1 - - - - - S3RETENTION - Keep retention on RAM section S3 of RAM[n] when RAM section is switched off - 19 - 19 - - - Off - Off - 0 - - - On - On - 1 - - - - - - - POWERSET - Description cluster: RAM[n] power control set register - 0x004 - read-write - 0x0000FFFF - - - S0POWER - Keep RAM section S0 of RAM[n] on or off in System ON mode - 0 - 0 - - - On - On - 1 - - - - - S1POWER - Keep RAM section S1 of RAM[n] on or off in System ON mode - 1 - 1 - - - On - On - 1 - - - - - S2POWER - Keep RAM section S2 of RAM[n] on or off in System ON mode - 2 - 2 - - - On - On - 1 - - - - - S3POWER - Keep RAM section S3 of RAM[n] on or off in System ON mode - 3 - 3 - - - On - On - 1 - - - - - S0RETENTION - Keep retention on RAM section S0 of RAM[n] when RAM section is switched off - 16 - 16 - - - On - On - 1 - - - - - S1RETENTION - Keep retention on RAM section S1 of RAM[n] when RAM section is switched off - 17 - 17 - - - On - On - 1 - - - - - S2RETENTION - Keep retention on RAM section S2 of RAM[n] when RAM section is switched off - 18 - 18 - - - On - On - 1 - - - - - S3RETENTION - Keep retention on RAM section S3 of RAM[n] when RAM section is switched off - 19 - 19 - - - On - On - 1 - - - - - - - POWERCLR - Description cluster: RAM[n] power control clear register - 0x008 - read-write - 0x0000FFFF - - - S0POWER - Keep RAM section S0 of RAM[n] on or off in System ON mode - 0 - 0 - - - Off - Off - 1 - - - - - S1POWER - Keep RAM section S1 of RAM[n] on or off in System ON mode - 1 - 1 - - - Off - Off - 1 - - - - - S2POWER - Keep RAM section S2 of RAM[n] on or off in System ON mode - 2 - 2 - - - Off - Off - 1 - - - - - S3POWER - Keep RAM section S3 of RAM[n] on or off in System ON mode - 3 - 3 - - - Off - Off - 1 - - - - - S0RETENTION - Keep retention on RAM section S0 of RAM[n] when RAM section is switched off - 16 - 16 - - - Off - Off - 1 - - - - - S1RETENTION - Keep retention on RAM section S1 of RAM[n] when RAM section is switched off - 17 - 17 - - - Off - Off - 1 - - - - - S2RETENTION - Keep retention on RAM section S2 of RAM[n] when RAM section is switched off - 18 - 18 - - - Off - Off - 1 - - - - - S3RETENTION - Keep retention on RAM section S3 of RAM[n] when RAM section is switched off - 19 - 19 - - - Off - Off - 1 - - - - - - - - - - P0_NS - GPIO Port 0 - 0x418C0500 - GPIO - - - - 0 - 0x300 - registers - - GPIO - 0x20 - - - OUT - Write GPIO port - 0x004 - read-write - - - PIN0 - Pin 0 - 0 - 0 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN1 - Pin 1 - 1 - 1 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN2 - Pin 2 - 2 - 2 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN3 - Pin 3 - 3 - 3 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN4 - Pin 4 - 4 - 4 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN5 - Pin 5 - 5 - 5 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN6 - Pin 6 - 6 - 6 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN7 - Pin 7 - 7 - 7 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN8 - Pin 8 - 8 - 8 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN9 - Pin 9 - 9 - 9 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN10 - Pin 10 - 10 - 10 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN11 - Pin 11 - 11 - 11 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN12 - Pin 12 - 12 - 12 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN13 - Pin 13 - 13 - 13 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN14 - Pin 14 - 14 - 14 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN15 - Pin 15 - 15 - 15 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN16 - Pin 16 - 16 - 16 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN17 - Pin 17 - 17 - 17 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN18 - Pin 18 - 18 - 18 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN19 - Pin 19 - 19 - 19 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN20 - Pin 20 - 20 - 20 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN21 - Pin 21 - 21 - 21 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN22 - Pin 22 - 22 - 22 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN23 - Pin 23 - 23 - 23 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN24 - Pin 24 - 24 - 24 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN25 - Pin 25 - 25 - 25 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN26 - Pin 26 - 26 - 26 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN27 - Pin 27 - 27 - 27 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN28 - Pin 28 - 28 - 28 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN29 - Pin 29 - 29 - 29 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN30 - Pin 30 - 30 - 30 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - PIN31 - Pin 31 - 31 - 31 - - - Low - Pin driver is low - 0 - - - High - Pin driver is high - 1 - - - - - - - OUTSET - Set individual bits in GPIO port - 0x008 - read-write - oneToSet - - - PIN0 - Pin 0 - 0 - 0 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN1 - Pin 1 - 1 - 1 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN2 - Pin 2 - 2 - 2 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN3 - Pin 3 - 3 - 3 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN4 - Pin 4 - 4 - 4 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN5 - Pin 5 - 5 - 5 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN6 - Pin 6 - 6 - 6 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN7 - Pin 7 - 7 - 7 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN8 - Pin 8 - 8 - 8 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN9 - Pin 9 - 9 - 9 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN10 - Pin 10 - 10 - 10 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN11 - Pin 11 - 11 - 11 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN12 - Pin 12 - 12 - 12 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN13 - Pin 13 - 13 - 13 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN14 - Pin 14 - 14 - 14 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN15 - Pin 15 - 15 - 15 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN16 - Pin 16 - 16 - 16 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN17 - Pin 17 - 17 - 17 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN18 - Pin 18 - 18 - 18 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN19 - Pin 19 - 19 - 19 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN20 - Pin 20 - 20 - 20 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN21 - Pin 21 - 21 - 21 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN22 - Pin 22 - 22 - 22 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN23 - Pin 23 - 23 - 23 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN24 - Pin 24 - 24 - 24 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN25 - Pin 25 - 25 - 25 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN26 - Pin 26 - 26 - 26 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN27 - Pin 27 - 27 - 27 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN28 - Pin 28 - 28 - 28 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN29 - Pin 29 - 29 - 29 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN30 - Pin 30 - 30 - 30 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN31 - Pin 31 - 31 - 31 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - - - OUTCLR - Clear individual bits in GPIO port - 0x00C - read-write - oneToClear - - - PIN0 - Pin 0 - 0 - 0 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN1 - Pin 1 - 1 - 1 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN2 - Pin 2 - 2 - 2 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN3 - Pin 3 - 3 - 3 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN4 - Pin 4 - 4 - 4 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN5 - Pin 5 - 5 - 5 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN6 - Pin 6 - 6 - 6 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN7 - Pin 7 - 7 - 7 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN8 - Pin 8 - 8 - 8 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN9 - Pin 9 - 9 - 9 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN10 - Pin 10 - 10 - 10 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN11 - Pin 11 - 11 - 11 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN12 - Pin 12 - 12 - 12 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN13 - Pin 13 - 13 - 13 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN14 - Pin 14 - 14 - 14 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN15 - Pin 15 - 15 - 15 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN16 - Pin 16 - 16 - 16 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN17 - Pin 17 - 17 - 17 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN18 - Pin 18 - 18 - 18 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN19 - Pin 19 - 19 - 19 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN20 - Pin 20 - 20 - 20 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN21 - Pin 21 - 21 - 21 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN22 - Pin 22 - 22 - 22 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN23 - Pin 23 - 23 - 23 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN24 - Pin 24 - 24 - 24 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN25 - Pin 25 - 25 - 25 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN26 - Pin 26 - 26 - 26 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN27 - Pin 27 - 27 - 27 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN28 - Pin 28 - 28 - 28 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN29 - Pin 29 - 29 - 29 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN30 - Pin 30 - 30 - 30 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - PIN31 - Pin 31 - 31 - 31 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 - - - - - - - IN - Read GPIO port - 0x010 - read-only - - - PIN0 - Pin 0 - 0 - 0 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN1 - Pin 1 - 1 - 1 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN2 - Pin 2 - 2 - 2 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN3 - Pin 3 - 3 - 3 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN4 - Pin 4 - 4 - 4 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN5 - Pin 5 - 5 - 5 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN6 - Pin 6 - 6 - 6 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN7 - Pin 7 - 7 - 7 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN8 - Pin 8 - 8 - 8 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN9 - Pin 9 - 9 - 9 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN10 - Pin 10 - 10 - 10 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN11 - Pin 11 - 11 - 11 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN12 - Pin 12 - 12 - 12 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN13 - Pin 13 - 13 - 13 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN14 - Pin 14 - 14 - 14 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN15 - Pin 15 - 15 - 15 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN16 - Pin 16 - 16 - 16 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN17 - Pin 17 - 17 - 17 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN18 - Pin 18 - 18 - 18 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN19 - Pin 19 - 19 - 19 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN20 - Pin 20 - 20 - 20 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN21 - Pin 21 - 21 - 21 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN22 - Pin 22 - 22 - 22 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN23 - Pin 23 - 23 - 23 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN24 - Pin 24 - 24 - 24 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN25 - Pin 25 - 25 - 25 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN26 - Pin 26 - 26 - 26 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN27 - Pin 27 - 27 - 27 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN28 - Pin 28 - 28 - 28 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN29 - Pin 29 - 29 - 29 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN30 - Pin 30 - 30 - 30 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - PIN31 - Pin 31 - 31 - 31 - - - Low - Pin input is low - 0 - - - High - Pin input is high - 1 - - - - - - - DIR - Direction of GPIO pins - 0x014 - read-write - - - PIN0 - Pin 0 - 0 - 0 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN1 - Pin 1 - 1 - 1 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN2 - Pin 2 - 2 - 2 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN3 - Pin 3 - 3 - 3 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN4 - Pin 4 - 4 - 4 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN5 - Pin 5 - 5 - 5 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN6 - Pin 6 - 6 - 6 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN7 - Pin 7 - 7 - 7 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN8 - Pin 8 - 8 - 8 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN9 - Pin 9 - 9 - 9 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN10 - Pin 10 - 10 - 10 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN11 - Pin 11 - 11 - 11 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN12 - Pin 12 - 12 - 12 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN13 - Pin 13 - 13 - 13 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN14 - Pin 14 - 14 - 14 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN15 - Pin 15 - 15 - 15 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN16 - Pin 16 - 16 - 16 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN17 - Pin 17 - 17 - 17 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN18 - Pin 18 - 18 - 18 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN19 - Pin 19 - 19 - 19 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN20 - Pin 20 - 20 - 20 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN21 - Pin 21 - 21 - 21 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN22 - Pin 22 - 22 - 22 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN23 - Pin 23 - 23 - 23 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN24 - Pin 24 - 24 - 24 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN25 - Pin 25 - 25 - 25 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN26 - Pin 26 - 26 - 26 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN27 - Pin 27 - 27 - 27 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN28 - Pin 28 - 28 - 28 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN29 - Pin 29 - 29 - 29 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN30 - Pin 30 - 30 - 30 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - PIN31 - Pin 31 - 31 - 31 - - - Input - Pin set as input - 0 - - - Output - Pin set as output - 1 - - - - - - - DIRSET - DIR set register - 0x018 - read-write - oneToSet - - - PIN0 - Set as output pin 0 - 0 - 0 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN1 - Set as output pin 1 - 1 - 1 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN2 - Set as output pin 2 - 2 - 2 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN3 - Set as output pin 3 - 3 - 3 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN4 - Set as output pin 4 - 4 - 4 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN5 - Set as output pin 5 - 5 - 5 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN6 - Set as output pin 6 - 6 - 6 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN7 - Set as output pin 7 - 7 - 7 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN8 - Set as output pin 8 - 8 - 8 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN9 - Set as output pin 9 - 9 - 9 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN10 - Set as output pin 10 - 10 - 10 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN11 - Set as output pin 11 - 11 - 11 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN12 - Set as output pin 12 - 12 - 12 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN13 - Set as output pin 13 - 13 - 13 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN14 - Set as output pin 14 - 14 - 14 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN15 - Set as output pin 15 - 15 - 15 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN16 - Set as output pin 16 - 16 - 16 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN17 - Set as output pin 17 - 17 - 17 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN18 - Set as output pin 18 - 18 - 18 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN19 - Set as output pin 19 - 19 - 19 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN20 - Set as output pin 20 - 20 - 20 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN21 - Set as output pin 21 - 21 - 21 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN22 - Set as output pin 22 - 22 - 22 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN23 - Set as output pin 23 - 23 - 23 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN24 - Set as output pin 24 - 24 - 24 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN25 - Set as output pin 25 - 25 - 25 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN26 - Set as output pin 26 - 26 - 26 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN27 - Set as output pin 27 - 27 - 27 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN28 - Set as output pin 28 - 28 - 28 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN29 - Set as output pin 29 - 29 - 29 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN30 - Set as output pin 30 - 30 - 30 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - PIN31 - Set as output pin 31 - 31 - 31 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 - - - - - - - DIRCLR - DIR clear register - 0x01C - read-write - oneToClear - - - PIN0 - Set as input pin 0 - 0 - 0 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN1 - Set as input pin 1 - 1 - 1 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN2 - Set as input pin 2 - 2 - 2 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN3 - Set as input pin 3 - 3 - 3 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN4 - Set as input pin 4 - 4 - 4 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN5 - Set as input pin 5 - 5 - 5 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN6 - Set as input pin 6 - 6 - 6 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN7 - Set as input pin 7 - 7 - 7 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN8 - Set as input pin 8 - 8 - 8 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN9 - Set as input pin 9 - 9 - 9 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN10 - Set as input pin 10 - 10 - 10 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN11 - Set as input pin 11 - 11 - 11 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN12 - Set as input pin 12 - 12 - 12 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN13 - Set as input pin 13 - 13 - 13 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN14 - Set as input pin 14 - 14 - 14 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN15 - Set as input pin 15 - 15 - 15 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN16 - Set as input pin 16 - 16 - 16 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN17 - Set as input pin 17 - 17 - 17 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN18 - Set as input pin 18 - 18 - 18 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN19 - Set as input pin 19 - 19 - 19 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN20 - Set as input pin 20 - 20 - 20 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN21 - Set as input pin 21 - 21 - 21 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN22 - Set as input pin 22 - 22 - 22 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN23 - Set as input pin 23 - 23 - 23 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN24 - Set as input pin 24 - 24 - 24 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN25 - Set as input pin 25 - 25 - 25 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN26 - Set as input pin 26 - 26 - 26 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN27 - Set as input pin 27 - 27 - 27 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN28 - Set as input pin 28 - 28 - 28 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN29 - Set as input pin 29 - 29 - 29 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN30 - Set as input pin 30 - 30 - 30 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - PIN31 - Set as input pin 31 - 31 - 31 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - - - - - LATCH - Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers - 0x020 - read-write - - - PIN0 - Status on whether PIN[0] has met criteria set in PIN_CNF[0].SENSE register. Write '1' to clear. - 0 - 0 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN1 - Status on whether PIN[1] has met criteria set in PIN_CNF[1].SENSE register. Write '1' to clear. - 1 - 1 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN2 - Status on whether PIN[2] has met criteria set in PIN_CNF[2].SENSE register. Write '1' to clear. - 2 - 2 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN3 - Status on whether PIN[3] has met criteria set in PIN_CNF[3].SENSE register. Write '1' to clear. - 3 - 3 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN4 - Status on whether PIN[4] has met criteria set in PIN_CNF[4].SENSE register. Write '1' to clear. - 4 - 4 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN5 - Status on whether PIN[5] has met criteria set in PIN_CNF[5].SENSE register. Write '1' to clear. - 5 - 5 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN6 - Status on whether PIN[6] has met criteria set in PIN_CNF[6].SENSE register. Write '1' to clear. - 6 - 6 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN7 - Status on whether PIN[7] has met criteria set in PIN_CNF[7].SENSE register. Write '1' to clear. - 7 - 7 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN8 - Status on whether PIN[8] has met criteria set in PIN_CNF[8].SENSE register. Write '1' to clear. - 8 - 8 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN9 - Status on whether PIN[9] has met criteria set in PIN_CNF[9].SENSE register. Write '1' to clear. - 9 - 9 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN10 - Status on whether PIN[10] has met criteria set in PIN_CNF[10].SENSE register. Write '1' to clear. - 10 - 10 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN11 - Status on whether PIN[11] has met criteria set in PIN_CNF[11].SENSE register. Write '1' to clear. - 11 - 11 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN12 - Status on whether PIN[12] has met criteria set in PIN_CNF[12].SENSE register. Write '1' to clear. - 12 - 12 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN13 - Status on whether PIN[13] has met criteria set in PIN_CNF[13].SENSE register. Write '1' to clear. - 13 - 13 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN14 - Status on whether PIN[14] has met criteria set in PIN_CNF[14].SENSE register. Write '1' to clear. - 14 - 14 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN15 - Status on whether PIN[15] has met criteria set in PIN_CNF[15].SENSE register. Write '1' to clear. - 15 - 15 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN16 - Status on whether PIN[16] has met criteria set in PIN_CNF[16].SENSE register. Write '1' to clear. - 16 - 16 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN17 - Status on whether PIN[17] has met criteria set in PIN_CNF[17].SENSE register. Write '1' to clear. - 17 - 17 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN18 - Status on whether PIN[18] has met criteria set in PIN_CNF[18].SENSE register. Write '1' to clear. - 18 - 18 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN19 - Status on whether PIN[19] has met criteria set in PIN_CNF[19].SENSE register. Write '1' to clear. - 19 - 19 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN20 - Status on whether PIN[20] has met criteria set in PIN_CNF[20].SENSE register. Write '1' to clear. - 20 - 20 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN21 - Status on whether PIN[21] has met criteria set in PIN_CNF[21].SENSE register. Write '1' to clear. - 21 - 21 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN22 - Status on whether PIN[22] has met criteria set in PIN_CNF[22].SENSE register. Write '1' to clear. - 22 - 22 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN23 - Status on whether PIN[23] has met criteria set in PIN_CNF[23].SENSE register. Write '1' to clear. - 23 - 23 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN24 - Status on whether PIN[24] has met criteria set in PIN_CNF[24].SENSE register. Write '1' to clear. - 24 - 24 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN25 - Status on whether PIN[25] has met criteria set in PIN_CNF[25].SENSE register. Write '1' to clear. - 25 - 25 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN26 - Status on whether PIN[26] has met criteria set in PIN_CNF[26].SENSE register. Write '1' to clear. - 26 - 26 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN27 - Status on whether PIN[27] has met criteria set in PIN_CNF[27].SENSE register. Write '1' to clear. - 27 - 27 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN28 - Status on whether PIN[28] has met criteria set in PIN_CNF[28].SENSE register. Write '1' to clear. - 28 - 28 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN29 - Status on whether PIN[29] has met criteria set in PIN_CNF[29].SENSE register. Write '1' to clear. - 29 - 29 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN30 - Status on whether PIN[30] has met criteria set in PIN_CNF[30].SENSE register. Write '1' to clear. - 30 - 30 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN31 - Status on whether PIN[31] has met criteria set in PIN_CNF[31].SENSE register. Write '1' to clear. - 31 - 31 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - - - DETECTMODE - Select between default DETECT signal behavior and LDETECT mode (For non-secure pin only) - 0x024 - read-write - - - DETECTMODE - Select between default DETECT signal behavior and LDETECT mode - 0 - 0 - - - Default - DETECT directly connected to PIN DETECT signals - 0 - - - LDETECT - Use the latched LDETECT behavior - 1 - - - - - - - DETECTMODE_SEC - Select between default DETECT signal behavior and LDETECT mode (For secure pin only) - 0x028 - read-write - - - DETECTMODE - Select between default DETECT signal behavior and LDETECT mode - 0 - 0 - - - Default - DETECT directly connected to PIN DETECT signals - 0 - - - LDETECT - Use the latched LDETECT behavior - 1 - - - - - - - 0x20 - 0x4 - PIN_CNF[%s] - Description collection: Configuration of GPIO pins - 0x200 - read-write - 0x00000002 - - - DIR - Pin direction. Same physical register as DIR register - 0 - 0 - - - Input - Configure pin as an input pin - 0 - - - Output - Configure pin as an output pin - 1 - - - - - INPUT - Connect or disconnect input buffer - 1 - 1 - - - Connect - Connect input buffer - 0 - - - Disconnect - Disconnect input buffer - 1 - - - - - PULL - Pull configuration - 2 - 3 - - - Disabled - No pull - 0 - - - Pulldown - Pull down on pin - 1 - - - Pullup - Pull up on pin - 3 - - - - - DRIVE - Drive configuration - 8 - 11 - - - S0S1 - Standard '0', standard '1' - 0 - - - H0S1 - High drive '0', standard '1' - 1 - - - S0H1 - Standard '0', high drive '1' - 2 - - - H0H1 - High drive '0', high 'drive '1'' - 3 - - - D0S1 - Disconnect '0', standard '1' (normally used for wired-or connections) - 4 - - - D0H1 - Disconnect '0', high drive '1' (normally used for wired-or connections) - 5 - - - S0D1 - Standard '0', disconnect '1' (normally used for wired-and connections) - 6 - - - H0D1 - High drive '0', disconnect '1' (normally used for wired-and connections) - 7 - - - E0E1 - Extra high drive '0', extra high drive '1' - 11 - - - - - SENSE - Pin sensing mechanism - 16 - 17 - - - Disabled - Disabled - 0 - - - High - Sense for high level - 2 - - - Low - Sense for low level - 3 - - - - - MCUSEL - Select which MCU/Subsystem controls this pin Note: this field is only accessible from secure code. - 28 - 30 - - - AppMCU - Application MCU - 0x0 - - - NetworkMCU - Network MCU - 0x1 - - - Peripheral - Peripheral with dedicated pins - 0x3 - - - TND - Trace and Debug Subsystem - 0x7 - - - - - - - - - P1_NS - GPIO Port 1 - 0x418C0800 - - - - - \ No newline at end of file + + + + Nordic Semiconductor + Nordic + nrf5340_network + nrf53 + 1 + nRF53 reference description for system-on-chip with dual ARM 32-bit Cortex-M33 microcontrollers + +Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + + 8 + 32 + 32 + 0x00000000 + 0xFFFFFFFF + + CM33 + r0p4 + little + 1 + 0 + 3 + 0 + 30 + 0 + + system_nrf53 + NRF_ + + 129 + + + + FICR_NS + Factory Information Configuration Registers + 0x01FF0000 + FICR + + + + 0 + 0x1000 + registers + + FICR + 0x20 + + + INFO + Device info + FICR_INFO + read-write + 0x200 + + CONFIGID + Configuration identifier + 0x000 + read-only + 0xFFFFFFFF + + + HWID + Identification number for the HW + 0 + 15 + + + + + 0x2 + 0x4 + DEVICEID[%s] + Description collection: Device identifier + 0x004 + read-only + 0xFFFFFFFF + + + DEVICEID + 64 bit unique device identifier + 0 + 31 + + + + + PART + Part code + 0x00C + read-only + 0x00005340 + + + PART + Part code + 0 + 31 + + + N5340 + nRF5340 + 0x5340 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + VARIANT + Part Variant, Hardware version and Production configuration + 0x010 + read-only + 0xFFFFFFFF + + + VARIANT + Part Variant, Hardware version and Production configuration, encoded as ASCII + 0 + 31 + + + QKAA + QKAA + 0x514B4141 + + + CLAA + CLAA + 0x434C4141 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + PACKAGE + Package option + 0x014 + read-only + 0xFFFFFFFF + + + PACKAGE + Package option + 0 + 31 + + + QK + QKxx - 94-pin aQFN + 0x2000 + + + CL + CLxx - WLCSP + 0x2005 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + RAM + RAM variant + 0x018 + read-only + 0xFFFFFFFF + + + RAM + RAM variant + 0 + 31 + + + K16 + 16 kByte RAM + 0x10 + + + K32 + 32 kByte RAM + 0x20 + + + K64 + 64 kByte RAM + 0x40 + + + K128 + 128 kByte RAM + 0x80 + + + K256 + 256 kByte RAM + 0x100 + + + K512 + 512 kByte RAM + 0x200 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + FLASH + Flash variant + 0x01C + read-only + 0xFFFFFFFF + + + FLASH + Flash variant + 0 + 31 + + + K128 + 128 kByte FLASH + 0x80 + + + K256 + 256 kByte FLASH + 0x100 + + + K512 + 512 kByte FLASH + 0x200 + + + K1024 + 1 MByte FLASH + 0x400 + + + K2048 + 2 MByte FLASH + 0x800 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + CODEPAGESIZE + Code memory page size in bytes + 0x020 + read-only + 0x00000800 + + + CODEPAGESIZE + Code memory page size in bytes + 0 + 31 + + + K2048 + 2 kByte + 0x800 + + + + + + + CODESIZE + Code memory size + 0x024 + read-only + 0x00000080 + + + CODESIZE + Code memory size in number of pages + 0 + 31 + + + P128 + 128 pages + 128 + + + + + + + DEVICETYPE + Device type + 0x028 + read-only + 0x00000000 + + + DEVICETYPE + Device type + 0 + 31 + + + Die + Device is an physical DIE + 0x0000000 + + + FPGA + Device is an FPGA + 0xFFFFFFFF + + + + + + + + 0x4 + 0x4 + ER[%s] + Description collection: Encryption Root, word n + 0x280 + read-only + 0xFFFFFFFF + + + ER + Encryption Root, word n + 0 + 31 + + + + + 0x4 + 0x4 + IR[%s] + Description collection: Identity Root, word n + 0x290 + read-only + 0xFFFFFFFF + + + IR + Identity Root, word n + 0 + 31 + + + + + DEVICEADDRTYPE + Device address type + 0x2A0 + read-only + 0xFFFFFFFF + + + DEVICEADDRTYPE + Device address type + 0 + 0 + + + Public + Public address + 0 + + + Random + Random address + 1 + + + + + + + 0x2 + 0x4 + DEVICEADDR[%s] + Description collection: Device address n + 0x2A4 + read-only + 0xFFFFFFFF + + + DEVICEADDR + 48 bit device address + 0 + 31 + + + + + 32 + 0x008 + TRIMCNF[%s] + Unspecified + FICR_TRIMCNF + read-write + 0x300 + + ADDR + Description cluster: Address + 0x000 + read-only + 0xFFFFFFFF + uint32_t + + + Address + Address + 0 + 31 + + + + + DATA + Description cluster: Data + 0x004 + read-only + 0xFFFFFFFF + + + Data + Data + 0 + 31 + + + + + + + + UICR_NS + User Information Configuration Registers + 0x01FF8000 + UICR + + + + 0 + 0x1000 + registers + + UICR + 0x20 + + + APPROTECT + Access port protection + 0x000 + read-write + 0x00000000 + + + PALL + Blocks debugger read/write access to all CPU registers and memory mapped + addresses. + 0 + 31 + + + Unprotected + Unprotected + 0x50FA50FA + + + Protected + Protected + 0x00000000 + + + + + + + ERASEPROTECT + Erase protection + 0x004 + read-write + 0x00000000 + + + PALL + Blocks NVMC ERASEALL and CTRLAP ERASEALL functionality. Using any value except Unprotected will lead to the protection being enabled. + 0 + 31 + + + Unprotected + Unprotected + 0xFFFFFFFF + + + Protected + Protected + 0x00000000 + + + + + + + 0x20 + 0x4 + NRFFW[%s] + Description collection: Reserved for Nordic firmware design + 0x200 + read-write + 0xFFFFFFFF + + + NRFFW + Reserved for Nordic firmware design + 0 + 31 + + + + + 0x20 + 0x4 + CUSTOMER[%s] + Description collection: Reserved for customer + 0x300 + read-write + 0xFFFFFFFF + + + CUSTOMER + Reserved for customer + 0 + 31 + + + + + + + CTI_NS + Cross-Trigger Interface control. NOTE: this is not a separate peripheral, but describes CM33 functionality. + 0xE0042000 + CTI + + + + 0 + 0x1000 + registers + + CTI + 0x20 + + + CTICONTROL + CTI Control register + 0x000 + read-write + 0x00000000 + + + GLBEN + Enables or disables the CTI. + 0 + 0 + + + Disabled + All cross-triggering mapping logic functionality is disabled. + 0 + + + Enabled + Cross-triggering mapping logic functionality is enabled. + 1 + + + + + + + CTIINTACK + CTI Interrupt Acknowledge register + 0x010 + write-only + 0x00000000 + + + DEBUGREQ + Processor debug request + 0 + 0 + + write + + Acknowledge + Clears the ctitrigout. + 1 + + + + + CPURESTART + Processor Restart + 1 + 1 + + write + + Acknowledge + Clears the ctitrigout. + 1 + + + + + UNUSED0 + N/A + 2 + 2 + + write + + Acknowledge + Clears the ctitrigout. + 1 + + + + + UNUSED1 + N/A + 3 + 3 + + write + + Acknowledge + Clears the ctitrigout. + 1 + + + + + UNUSED2 + N/A + 4 + 4 + + write + + Acknowledge + Clears the ctitrigout. + 1 + + + + + UNUSED3 + N/A + 5 + 5 + + write + + Acknowledge + Clears the ctitrigout. + 1 + + + + + UNUSED4 + N/A + 6 + 6 + + write + + Acknowledge + Clears the ctitrigout. + 1 + + + + + UNUSED5 + N/A + 7 + 7 + + write + + Acknowledge + Clears the ctitrigout. + 1 + + + + + + + CTIAPPSET + CTI Application Trigger Set register + 0x014 + read-write + 0x00000000 + + + APPSET_0 + Application trigger event for channel 0. + 0 + 0 + + read + + Inactive + Application trigger 0 is inactive. + 0 + + + Active + Application trigger 0 is active. + 1 + + + + write + + Activate + Generate channel event for channel 0. + 1 + + + + + APPSET_1 + Application trigger event for channel 1. + 1 + 1 + + read + + Inactive + Application trigger 1 is inactive. + 0 + + + Active + Application trigger 1 is active. + 1 + + + + write + + Activate + Generate channel event for channel 1. + 1 + + + + + APPSET_2 + Application trigger event for channel 2. + 2 + 2 + + read + + Inactive + Application trigger 2 is inactive. + 0 + + + Active + Application trigger 2 is active. + 1 + + + + write + + Activate + Generate channel event for channel 2. + 1 + + + + + APPSET_3 + Application trigger event for channel 3. + 3 + 3 + + read + + Inactive + Application trigger 3 is inactive. + 0 + + + Active + Application trigger 3 is active. + 1 + + + + write + + Activate + Generate channel event for channel 3. + 1 + + + + + + + CTIAPPCLEAR + CTI Application Trigger Clear register + 0x018 + write-only + 0x00000000 + + + APPCLEAR_0 + Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. + 0 + 0 + + write + + Clear + Clears the event for channel 0. + 1 + + + + + APPCLEAR_1 + Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. + 1 + 1 + + write + + Clear + Clears the event for channel 1. + 1 + + + + + APPCLEAR_2 + Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. + 2 + 2 + + write + + Clear + Clears the event for channel 2. + 1 + + + + + APPCLEAR_3 + Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. + 3 + 3 + + write + + Clear + Clears the event for channel 3. + 1 + + + + + + + CTIAPPPULSE + CTI Application Pulse register + 0x01C + write-only + 0x00000000 + + + APPULSE_0 + Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. + 0 + 0 + + write + + Generate + Generates an event pulse on channel 0. + 1 + + + + + APPULSE_1 + Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. + 1 + 1 + + write + + Generate + Generates an event pulse on channel 1. + 1 + + + + + APPULSE_2 + Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. + 2 + 2 + + write + + Generate + Generates an event pulse on channel 2. + 1 + + + + + APPULSE_3 + Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. + 3 + 3 + + write + + Generate + Generates an event pulse on channel 3. + 1 + + + + + + + 0x8 + 0x4 + CTIINEN[%s] + Description collection: CTI Trigger input + 0x020 + read-write + 0x00000000 + + + TRIGINEN_0 + Enables a cross trigger event to channel 0 when a ctitrigin input is activated. + 0 + 0 + + + Disabled + Input trigger n events are ignored by channel 0. + 0 + + + Enabled + When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 0. + 1 + + + + + TRIGINEN_1 + Enables a cross trigger event to channel 1 when a ctitrigin input is activated. + 1 + 1 + + + Disabled + Input trigger n events are ignored by channel 1. + 0 + + + Enabled + When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 1. + 1 + + + + + TRIGINEN_2 + Enables a cross trigger event to channel 2 when a ctitrigin input is activated. + 2 + 2 + + + Disabled + Input trigger n events are ignored by channel 2. + 0 + + + Enabled + When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 2. + 1 + + + + + TRIGINEN_3 + Enables a cross trigger event to channel 3 when a ctitrigin input is activated. + 3 + 3 + + + Disabled + Input trigger n events are ignored by channel 3. + 0 + + + Enabled + When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 3. + 1 + + + + + + + 0x8 + 0x4 + CTIOUTEN[%s] + Description collection: CTI Trigger output + 0x0A0 + read-write + 0x00000000 + + + TRIGOUTEN_0 + Enables a cross trigger event to ctitrigout when channel 0 is activated. + 0 + 0 + + + Disabled + Channel 0 is ignored by output trigger n. + 0 + + + Enabled + When an event occurs on channel 0, generate an event on output event n (ctitrigout[n]). + 1 + + + + + TRIGOUTEN_1 + Enables a cross trigger event to ctitrigout when channel 1 is activated. + 1 + 1 + + + Disabled + Channel 1 is ignored by output trigger n. + 0 + + + Enabled + When an event occurs on channel 1, generate an event on output event n (ctitrigout[n]). + 1 + + + + + TRIGOUTEN_2 + Enables a cross trigger event to ctitrigout when channel 2 is activated. + 2 + 2 + + + Disabled + Channel 2 is ignored by output trigger n. + 0 + + + Enabled + When an event occurs on channel 2, generate an event on output event n (ctitrigout[n]). + 1 + + + + + TRIGOUTEN_3 + Enables a cross trigger event to ctitrigout when channel 3 is activated. + 3 + 3 + + + Disabled + Channel 3 is ignored by output trigger n. + 0 + + + Enabled + When an event occurs on channel 3, generate an event on output event n (ctitrigout[n]). + 1 + + + + + + + CTITRIGINSTATUS + CTI Trigger In Status register + 0x130 + read-only + 0x00000000 + + + CPUHALTED + Processor Halted + 0 + 0 + + + Active + Ctitrigin 0 is active. + 1 + + + Inactive + Ctitrigin 0 is inactive. + 0 + + + + + DWTCOMPOUT0 + DWT Comparator Output 0 + 1 + 1 + + + Active + Ctitrigin 1 is active. + 1 + + + Inactive + Ctitrigin 1 is inactive. + 0 + + + + + DWTCOMPOUT1 + DWT Comparator Output 1 + 2 + 2 + + + Active + Ctitrigin 2 is active. + 1 + + + Inactive + Ctitrigin 2 is inactive. + 0 + + + + + DWTCOMPOUT2 + DWT Comparator Output 2 + 3 + 3 + + + Active + Ctitrigin 3 is active. + 1 + + + Inactive + Ctitrigin 3 is inactive. + 0 + + + + + UNUSED0 + N/A + 4 + 4 + + + Active + Ctitrigin 4 is active. + 1 + + + Inactive + Ctitrigin 4 is inactive. + 0 + + + + + UNUSED1 + N/A + 5 + 5 + + + Active + Ctitrigin 5 is active. + 1 + + + Inactive + Ctitrigin 5 is inactive. + 0 + + + + + UNUSED2 + N/A + 6 + 6 + + + Active + Ctitrigin 6 is active. + 1 + + + Inactive + Ctitrigin 6 is inactive. + 0 + + + + + UNUSED3 + N/A + 7 + 7 + + + Active + Ctitrigin 7 is active. + 1 + + + Inactive + Ctitrigin 7 is inactive. + 0 + + + + + + + CTITRIGOUTSTATUS + CTI Trigger Out Status register + 0x134 + read-only + 0x00000000 + + + DEBUGREQ + Processor debug request + 0 + 0 + + + Active + Ctitrigout 0 is active. + 1 + + + Inactive + Ctitrigout 0 is inactive. + 0 + + + + + CPURESTART + Processor Restart + 1 + 1 + + + Active + Ctitrigout 1 is active. + 1 + + + Inactive + Ctitrigout 1 is inactive. + 0 + + + + + UNUSED0 + N/A + 2 + 2 + + + Active + Ctitrigout 2 is active. + 1 + + + Inactive + Ctitrigout 2 is inactive. + 0 + + + + + UNUSED1 + N/A + 3 + 3 + + + Active + Ctitrigout 3 is active. + 1 + + + Inactive + Ctitrigout 3 is inactive. + 0 + + + + + UNUSED2 + N/A + 4 + 4 + + + Active + Ctitrigout 4 is active. + 1 + + + Inactive + Ctitrigout 4 is inactive. + 0 + + + + + UNUSED3 + N/A + 5 + 5 + + + Active + Ctitrigout 5 is active. + 1 + + + Inactive + Ctitrigout 5 is inactive. + 0 + + + + + UNUSED4 + N/A + 6 + 6 + + + Active + Ctitrigout 6 is active. + 1 + + + Inactive + Ctitrigout 6 is inactive. + 0 + + + + + UNUSED5 + N/A + 7 + 7 + + + Active + Ctitrigout 7 is active. + 1 + + + Inactive + Ctitrigout 7 is inactive. + 0 + + + + + + + CTICHINSTATUS + CTI Channel In Status register + 0x138 + read-only + 0x00000000 + + + CTICHINSTATUS_0 + Shows the status of the ctitrigin 0 input. + 0 + 0 + + + Active + Ctichin 0 is active. + 1 + + + Inactive + Ctichin 0 is inactive. + 0 + + + + + CTICHINSTATUS_1 + Shows the status of the ctitrigin 1 input. + 1 + 1 + + + Active + Ctichin 1 is active. + 1 + + + Inactive + Ctichin 1 is inactive. + 0 + + + + + CTICHINSTATUS_2 + Shows the status of the ctitrigin 2 input. + 2 + 2 + + + Active + Ctichin 2 is active. + 1 + + + Inactive + Ctichin 2 is inactive. + 0 + + + + + CTICHINSTATUS_3 + Shows the status of the ctitrigin 3 input. + 3 + 3 + + + Active + Ctichin 3 is active. + 1 + + + Inactive + Ctichin 3 is inactive. + 0 + + + + + + + CTIGATE + Enable CTI Channel Gate register + 0x140 + read-write + 0x0000000F + + + CTIGATEEN_0 + Enable ctichout0. + 0 + 0 + + + Enabled + Enable ctichout channel 0 propagation. + 1 + + + Disabled + Disable ctichout channel 0 propagation. + 0 + + + + + CTIGATEEN_1 + Enable ctichout1. + 1 + 1 + + + Enabled + Enable ctichout channel 1 propagation. + 1 + + + Disabled + Disable ctichout channel 1 propagation. + 0 + + + + + CTIGATEEN_2 + Enable ctichout2. + 2 + 2 + + + Enabled + Enable ctichout channel 2 propagation. + 1 + + + Disabled + Disable ctichout channel 2 propagation. + 0 + + + + + CTIGATEEN_3 + Enable ctichout3. + 3 + 3 + + + Enabled + Enable ctichout channel 3 propagation. + 1 + + + Disabled + Disable ctichout channel 3 propagation. + 0 + + + + + + + DEVARCH + Device Architecture register + 0xFBC + read-only + 0x47701A14 + + + Architecture + Contains the CTI device architecture. + 0 + 0 + + + + + DEVID + Device Configuration register + 0xFC8 + read-only + 0x00040800 + + + EXTMUXNUM + Indicates the number of multiplexers available on Trigger Inputs and Trigger Outputs that are using asicctl. + The default value of 0b00000 indicates that no multiplexing is present. + 0 + 4 + + + NUMTRIG + Number of ECT triggers available. + 8 + 15 + + + NUMCH + Number of ECT channels available. + 16 + 19 + + + + + DEVTYPE + Device Type Identifier register + 0xFCC + read-only + 0x00000014 + + + MAJOR + Major classification of the type of the debug component as specified in the Arm Architecture Specification for this + debug and trace component. + 0 + 3 + + + Controller + Indicates that this component allows a debugger to control other components in an Arm CoreSight SoC-400 system. + 4 + + + + + SUB + Sub-classification of the type of the debug component as specified in the Arm Architecture Specification within + the major classification as specified in the MAJOR field. + 4 + 7 + + + Crosstrigger + Indicates that this component is a sub-triggering component. + 1 + + + + + + + PIDR4 + Peripheral ID4 Register + 0xFD0 + read-only + 0x00000004 + + + DES_2 + Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. + 0 + 3 + + + Code + JEDEC continuation code. + 4 + + + + + SIZE + Always 0b0000. Indicates that the device only occupies 4KB of memory. + 4 + 7 + + + + + PIDR5 + Peripheral ID5 register + 0xFD4 + read-only + + + PIDR6 + Peripheral ID6 register + 0xFD8 + read-only + + + PIDR7 + Peripheral ID7 register + 0xFDC + read-only + + + PIDR0 + Peripheral ID0 Register + 0xFE0 + read-only + 0x00000021 + + + PART_0 + Bits[7:0] of the 12-bit part number of the component. The designer of the component assigns this part number. + 0 + 7 + + + PartnumberL + Indicates bits[7:0] of the part number of the component. + 0x21 + + + + + + + PIDR1 + Peripheral ID1 Register + 0xFE4 + read-only + 0x000000BD + + + PART_1 + Bits[11:8] of the 12-bit part number of the component. The designer of the component assigns this part number. + 0 + 3 + + + PartnumberH + Indicates bits[11:8] of the part number of the component. + 13 + + + + + DES_0 + Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. + 4 + 7 + + + Arm + Arm. Bits[3:0] of the JEDEC JEP106 Identity Code + 11 + + + + + + + PIDR2 + Peripheral ID2 Register + 0xFE8 + read-only + 0x0000000B + + + DES_1 + Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. + 0 + 2 + + + Arm + Arm. Bits[6:4] of the JEDEC JEP106 Identity Code + 3 + + + + + JEDEC + Always 1. Indicates that the JEDEC-assigned designer ID is used. + 3 + 3 + + + REVISION + Peripheral revision + 4 + 7 + + + Rev0p0 + This device is at r0p0 + 0 + + + + + + + PIDR3 + Peripheral ID3 Register + 0xFEC + read-only + 0x00000000 + + + CMOD + Customer Modified. Indicates whether the customer has modified the behavior of the component. In most cases, + this field is 0b0000. Customers change this value when they make authorized modifications to this component. + 0 + 3 + + + Unmodified + Indicates that the customer has not modified this component. + 0 + + + + + REVAND + Indicates minor errata fixes specific to the revision of the component being used, for example metal fixes after + implementation. In most cases, this field is 0b0000. Arm recommends that the component designers ensure that a + metal fix can change this field if required, for example, by driving it from registers that reset to 0b0000. + 4 + 7 + + + NoErrata + Indicates that there are no errata fixes to this component. + 0 + + + + + + + CIDR0 + Component ID0 Register + 0xFF0 + read-only + 0x0000000D + + + PRMBL_0 + Preamble[0]. Contains bits[7:0] of the component identification code. + 0 + 7 + + + Value + Bits[7:0] of the identification code. + 0x0D + + + + + + + CIDR1 + Component ID1 Register + 0xFF4 + read-only + 0x00000090 + + + PRMBL_1 + Preamble[1]. Contains bits[11:8] of the component identification code. + 0 + 3 + + + Value + Bits[11:8] of the identification code. + 0 + + + + + CLASS + Class of the component, for example, whether the component is a ROM table or a generic CoreSight component. + Contains bits[15:12] of the component identification code + 4 + 7 + + + Coresight + Indicates that the component is a CoreSight component. + 9 + + + + + + + CIDR2 + Component ID2 Register + 0xFF8 + read-only + 0x00000005 + + + PRMBL_2 + Preamble[2]. Contains bits[23:16] of the component identification code. + 0 + 7 + + + Value + Bits[23:16] of the identification code. + 0x05 + + + + + + + CIDR3 + Component ID3 Register + 0xFFC + read-only + 0x000000B1 + + + PRMBL_3 + Preamble[3]. Contains bits[31:24] of the component identification code. + 0 + 7 + + + Value + Bits[31:24] of the identification code. + 0xB1 + + + + + + + + + DCNF_NS + Domain configuration management + 0x41000000 + DCNF + + + + 0 + 0x1000 + registers + + DCNF + 0x20 + + + CPUID + CPU ID of this subsystem + 0x420 + read-only + 0x00000001 + + + CPUID + CPU ID + 0 + 7 + + + + + + + VREQCTRL_NS + Voltage request control + 0x41004000 + VREQCTRL + + + + 0 + 0x1000 + registers + + VREQCTRL + 0x20 + + + VREGRADIO + Unspecified + VREQCTRL_VREGRADIO + read-write + 0x500 + + VREQH + Request high voltage on RADIO After requesting high voltage, the user must wait until VREQHREADY is set to Ready + 0x000 + read-write + + + VREQH + Request high voltage + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + VREQHREADY + High voltage on RADIO is ready + 0x008 + read-only + + + READY + RADIO is ready to operate on high voltage + 0 + 0 + + + NotReady + Not ready + 0 + + + Ready + Ready + 1 + + + + + + + + + + CLOCK_NS + Clock management + 0x41005000 + CLOCK + + + + 0 + 0x1000 + registers + + + CLOCK_POWER + 5 + + CLOCK + 0x20 + + + TASKS_HFCLKSTART + Start HFCLK128M/HFCLK64M source as selected in HFCLKSRC + 0x000 + write-only + + + TASKS_HFCLKSTART + Start HFCLK128M/HFCLK64M source as selected in HFCLKSRC + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_HFCLKSTOP + Stop HFCLK128M/HFCLK64M source + 0x004 + write-only + + + TASKS_HFCLKSTOP + Stop HFCLK128M/HFCLK64M source + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_LFCLKSTART + Start LFCLK source as selected in LFCLKSRC + 0x008 + write-only + + + TASKS_LFCLKSTART + Start LFCLK source as selected in LFCLKSRC + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_LFCLKSTOP + Stop LFCLK source + 0x00C + write-only + + + TASKS_LFCLKSTOP + Stop LFCLK source + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CAL + Start calibration of LFRC oscillator + 0x010 + write-only + + + TASKS_CAL + Start calibration of LFRC oscillator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_HFCLKSTART + Subscribe configuration for task HFCLKSTART + 0x080 + read-write + + + CHIDX + DPPI channel that task HFCLKSTART will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_HFCLKSTOP + Subscribe configuration for task HFCLKSTOP + 0x084 + read-write + + + CHIDX + DPPI channel that task HFCLKSTOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_LFCLKSTART + Subscribe configuration for task LFCLKSTART + 0x088 + read-write + + + CHIDX + DPPI channel that task LFCLKSTART will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_LFCLKSTOP + Subscribe configuration for task LFCLKSTOP + 0x08C + read-write + + + CHIDX + DPPI channel that task LFCLKSTOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_CAL + Subscribe configuration for task CAL + 0x090 + read-write + + + CHIDX + DPPI channel that task CAL will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_HFCLKSTARTED + HFCLK128M/HFCLK64M source started + 0x100 + read-write + + + EVENTS_HFCLKSTARTED + HFCLK128M/HFCLK64M source started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_LFCLKSTARTED + LFCLK source started + 0x104 + read-write + + + EVENTS_LFCLKSTARTED + LFCLK source started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DONE + Calibration of LFRC oscillator complete event + 0x11C + read-write + + + EVENTS_DONE + Calibration of LFRC oscillator complete event + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_HFCLKSTARTED + Publish configuration for event HFCLKSTARTED + 0x180 + read-write + + + CHIDX + DPPI channel that event HFCLKSTARTED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_LFCLKSTARTED + Publish configuration for event LFCLKSTARTED + 0x184 + read-write + + + CHIDX + DPPI channel that event LFCLKSTARTED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_DONE + Publish configuration for event DONE + 0x19C + read-write + + + CHIDX + DPPI channel that event DONE will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + HFCLKSTARTED + Enable or disable interrupt for event HFCLKSTARTED + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + LFCLKSTARTED + Enable or disable interrupt for event LFCLKSTARTED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + DONE + Enable or disable interrupt for event DONE + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + HFCLKSTARTED + Write '1' to enable interrupt for event HFCLKSTARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + LFCLKSTARTED + Write '1' to enable interrupt for event LFCLKSTARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DONE + Write '1' to enable interrupt for event DONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + HFCLKSTARTED + Write '1' to disable interrupt for event HFCLKSTARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + LFCLKSTARTED + Write '1' to disable interrupt for event LFCLKSTARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DONE + Write '1' to disable interrupt for event DONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + + + HFCLKSTARTED + Read pending status of interrupt for event HFCLKSTARTED + 0 + 0 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + LFCLKSTARTED + Read pending status of interrupt for event LFCLKSTARTED + 1 + 1 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + DONE + Read pending status of interrupt for event DONE + 7 + 7 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + + + HFCLKRUN + Status indicating that HFCLKSTART task has been triggered + 0x408 + read-only + + + STATUS + HFCLKSTART task triggered or not + 0 + 0 + + + NotTriggered + Task not triggered + 0 + + + Triggered + Task triggered + 1 + + + + + + + HFCLKSTAT + Status indicating which HFCLK128M/HFCLK64M source is running This register value in any CLOCK instance reflects status only due to configurations/actions in that CLOCK instance. + 0x40C + read-only + + + SRC + Active clock source + 0 + 0 + + + HFINT + Clock source: HFINT - 128 MHz on-chip oscillator + 0 + + + HFXO + Clock source: HFXO - 128 MHz clock derived from external 32 MHz crystal oscillator + 1 + + + + + ALWAYSRUNNING + ALWAYSRUN activated + 4 + 4 + + + NotRunning + Automatic clock control enabled + 0 + + + Running + Oscillator is always running + 1 + + + + + STATE + HFCLK state + 16 + 16 + + + NotRunning + HFCLK not running + 0 + + + Running + HFCLK running + 1 + + + + + + + LFCLKRUN + Status indicating that LFCLKSTART task has been triggered + 0x414 + read-only + + + STATUS + LFCLKSTART task triggered or not + 0 + 0 + + + NotTriggered + Task not triggered + 0 + + + Triggered + Task triggered + 1 + + + + + + + LFCLKSTAT + Status indicating which LFCLK source is running This register value in any CLOCK instance reflects status only due to configurations/actions in that CLOCK instance. + 0x418 + read-only + + + SRC + Active clock source + 0 + 1 + + + LFRC + 32.768 kHz RC oscillator + 1 + + + LFXO + 32.768 kHz crystal oscillator + 2 + + + LFSYNT + 32.768 kHz synthesized from HFCLK + 3 + + + + + ALWAYSRUNNING + ALWAYSRUN activated + 4 + 4 + + + NotRunning + Automatic clock control enabled + 0 + + + Running + Oscillator is always running + 1 + + + + + STATE + LFCLK state + 16 + 16 + + + NotRunning + LFCLK not running + 0 + + + Running + LFCLK running + 1 + + + + + + + LFCLKSRCCOPY + Copy of LFCLKSRC register, set when LFCLKSTART task was triggered + 0x41C + read-only + 0x00000001 + + + SRC + Clock source + 0 + 1 + + + LFRC + 32.768 kHz RC oscillator + 1 + + + LFXO + 32.768 kHz crystal oscillator + 2 + + + LFSYNT + 32.768 kHz synthesized from HFCLK + 3 + + + + + + + HFCLKSRC + Clock source for HFCLK128M/HFCLK64M + 0x514 + read-write + 0x00000001 + + + SRC + Select which HFCLK source is started by the HFCLKSTART task + 0 + 0 + + + HFINT + HFCLKSTART task starts HFINT oscillator + 0 + + + HFXO + HFCLKSTART task starts HFXO oscillator + 1 + + + + + + + LFCLKSRC + Clock source for LFCLK + 0x518 + read-write + 0x00000001 + + + SRC + Select which LFCLK source is started by the LFCLKSTART task + 0 + 1 + + + LFRC + 32.768 kHz RC oscillator + 1 + + + LFXO + 32.768 kHz crystal oscillator + 2 + + + LFSYNT + 32.768 kHz synthesized from HFCLK + 3 + + + + + + + HFCLKCTRL + HFCLK128M frequency configuration + 0x558 + read-write + 0x00000000 + + + HCLK + High frequency clock HCLK + 0 + 1 + + + Div1 + Divide HFCLK by 1 + 0 + + + Div2 + Divide HFCLK by 2 + 1 + + + + + + + HFCLKALWAYSRUN + Automatic or manual control of HFCLK128M/HFCLK64M + 0x570 + read-write + + + ALWAYSRUN + Ensure clock is always running + 0 + 0 + + + Automatic + Use automatic clock control + 0 + + + AlwaysRun + Ensure clock is always running + 1 + + + + + + + LFCLKALWAYSRUN + Automatic or manual control of LFCLK + 0x574 + read-write + + + ALWAYSRUN + Ensure clock is always running + 0 + 0 + + + Automatic + Use automatic clock control + 0 + + + AlwaysRun + Ensure clock is always running + 1 + + + + + + + + + POWER_NS + Power control + 0x41005000 + CLOCK_NS + POWER + + + + 0 + 0x1000 + registers + + + CLOCK_POWER + 5 + + POWER + 0x20 + + + TASKS_CONSTLAT + Enable Constant Latency mode + 0x78 + write-only + + + TASKS_CONSTLAT + Enable Constant Latency mode + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_LOWPWR + Enable Low-Power mode (variable latency) + 0x7C + write-only + + + TASKS_LOWPWR + Enable Low-Power mode (variable latency) + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_CONSTLAT + Subscribe configuration for task CONSTLAT + 0xF8 + read-write + + + CHIDX + DPPI channel that task CONSTLAT will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_LOWPWR + Subscribe configuration for task LOWPWR + 0xFC + read-write + + + CHIDX + DPPI channel that task LOWPWR will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_POFWARN + Power failure warning + 0x108 + read-write + + + EVENTS_POFWARN + Power failure warning + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SLEEPENTER + CPU entered WFI/WFE sleep + 0x114 + read-write + + + EVENTS_SLEEPENTER + CPU entered WFI/WFE sleep + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SLEEPEXIT + CPU exited WFI/WFE sleep + 0x118 + read-write + + + EVENTS_SLEEPEXIT + CPU exited WFI/WFE sleep + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_POFWARN + Publish configuration for event POFWARN + 0x188 + read-write + + + CHIDX + DPPI channel that event POFWARN will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_SLEEPENTER + Publish configuration for event SLEEPENTER + 0x194 + read-write + + + CHIDX + DPPI channel that event SLEEPENTER will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_SLEEPEXIT + Publish configuration for event SLEEPEXIT + 0x198 + read-write + + + CHIDX + DPPI channel that event SLEEPEXIT will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + POFWARN + Enable or disable interrupt for event POFWARN + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SLEEPENTER + Enable or disable interrupt for event SLEEPENTER + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SLEEPEXIT + Enable or disable interrupt for event SLEEPEXIT + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + POFWARN + Write '1' to enable interrupt for event POFWARN + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SLEEPENTER + Write '1' to enable interrupt for event SLEEPENTER + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SLEEPEXIT + Write '1' to enable interrupt for event SLEEPEXIT + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + POFWARN + Write '1' to disable interrupt for event POFWARN + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SLEEPENTER + Write '1' to disable interrupt for event SLEEPENTER + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SLEEPEXIT + Write '1' to disable interrupt for event SLEEPEXIT + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + 0x2 + 0x4 + GPREGRET[%s] + Description collection: General purpose retention register + 0x51C + read-write + + + GPREGRET + General purpose retention register + 0 + 7 + + + + + + + RESET_NS + Reset control + 0x41005000 + CLOCK_NS + RESET + + + + 0 + 0x1000 + registers + + RESET + 0x20 + + + RESETREAS + Reset reason + 0x400 + read-write + + + RESETPIN + Reset from pin reset detected + 0 + 0 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + DOG0 + Reset from application watchdog timer 0 detected + 1 + 1 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + CTRLAP + Reset from application CTRL-AP detected + 2 + 2 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + SREQ + Reset from application soft reset detected + 3 + 3 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + LOCKUP + Reset from application CPU lockup detected + 4 + 4 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + OFF + Reset due to wakeup from System OFF mode when wakeup is triggered by DETECT signal from GPIO + 5 + 5 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + LPCOMP + Reset due to wakeup from System OFF mode when wakeup is triggered by ANADETECT signal from LPCOMP + 6 + 6 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + DIF + Reset due to wakeup from System OFF mode when wakeup is triggered by entering the Debug Interface mode + 7 + 7 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + LSREQ + Reset from network soft reset detected + 16 + 16 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + LLOCKUP + Reset from network CPU lockup detected + 17 + 17 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + LDOG + Reset from network watchdog timer detected + 18 + 18 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + MFORCEOFF + Force-OFF reset from application core detected + 23 + 23 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + NFC + Reset after wakeup from System OFF mode due to NFC field being detected + 24 + 24 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + DOG1 + Reset from application watchdog timer 1 detected + 25 + 25 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + VBUS + Reset after wakeup from System OFF mode due to VBUS rising into valid range + 26 + 26 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + LCTRLAP + Reset from network CTRL-AP detected + 27 + 27 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + + + + + CTRLAP_NS + Control access port + 0x41006000 + CTRLAPPERI + + + + 0 + 0x1000 + registers + + CTRLAPPERI + 0x20 + + + MAILBOX + Unspecified + CTRLAPPERI_MAILBOX + read-write + 0x400 + + RXDATA + Data sent from the debugger to the CPU. + 0x000 + read-only + 0x00000000 + + + RXDATA + Data received from debugger + 0 + 31 + + + + + RXSTATUS + This register shows a status that indicates if data sent from the debugger to the CPU has been read. + 0x004 + read-only + 0x00000000 + + + RXSTATUS + Status of data in register RXDATA + 0 + 0 + + + NoDataPending + No data pending in register RXDATA + 0 + + + DataPending + Data pending in register RXDATA + 1 + + + + + + + TXDATA + Data sent from the CPU to the debugger. + 0x80 + read-write + 0x00000000 + + + TXDATA + Data sent to debugger + 0 + 31 + + + + + TXSTATUS + This register shows a status that indicates if the data sent from the CPU to the debugger has been read. + 0x84 + read-only + 0x00000000 + + + TXSTATUS + Status of data in register TXDATA + 0 + 0 + + + NoDataPending + No data pending in register TXDATA + 0 + + + DataPending + Data pending in register TXDATA + 1 + + + + + + + + ERASEPROTECT + Unspecified + CTRLAPPERI_ERASEPROTECT + read-write + 0x500 + + LOCK + This register locks the ERASEPROTECT.DISABLE register from being written until next reset. + 0x000 + read-writeOnce + 0x00000000 + + + LOCK + Lock ERASEPROTECT.DISABLE register from being written until next reset + 0 + 0 + + + Unlocked + Register ERASEPROTECT.DISABLE is writeable + 0 + + + Locked + Register ERASEPROTECT.DISABLE is read-only + 1 + + + + + + + DISABLE + This register disables the ERASEPROTECT register and performs an ERASEALL operation. + 0x004 + read-writeOnce + 0x00000000 + + + KEY + The ERASEALL sequence is initiated if the value of the KEY fields are non-zero and the KEY fields match on both the CPU and debugger sides. + 0 + 31 + + + + + + APPROTECT + Unspecified + CTRLAPPERI_APPROTECT + read-write + 0x540 + + LOCK + This register locks the APPROTECT.DISABLE register from being written to until next reset. + 0x000 + read-writeOnce + 0x00000000 + + + LOCK + Lock the APPROTECT.DISABLE register from being written to until next reset + 0 + 0 + + + Unlocked + Register APPROTECT.DISABLE is writeable + 0 + + + Locked + Register APPROTECT.DISABLE is read-only + 1 + + + + + + + DISABLE + This register disables the APPROTECT register and enables debug access to non-secure mode. + 0x004 + read-write + 0x00000000 + + + KEY + If the value of the KEY field is non-zero, and the KEY fields match on both the + CPU and debugger sides, disable APPROTECT and enable debug access to non-secure mode until + the next pin reset, brown-out reset, power-on reset, or watchog timer reset. After reset the debugger side register has a fixed KEY value. To enable debug access, both CTRL-AP and UICR.APPROTECT protection needs to be disabled. + 0 + 31 + + + + + + STATUS + Status bits for CTRL-AP peripheral. + 0x600 + read-only + 0x00000000 + + + UICRAPPROTECT + Status bit for UICR part of access port protection at last reset. + 0 + 0 + + + Enabled + APPROTECT was enabled in UICR + 0 + + + Disabled + APPROTECT wasdisabled in UICR + 1 + + + + + DBGIFACEMODE + Status bit for device debug interface mode + 2 + 2 + + + Disabled + No debugger attached + 0 + + + Enabled + Debugger is attached and device is in debug interface mode + 1 + + + + + + + + + RADIO_NS + 2.4 GHz radio + 0x41008000 + RADIO + + + + 0 + 0x1000 + registers + + + RADIO + 8 + + RADIO + 0x20 + + + TASKS_TXEN + Enable RADIO in TX mode + 0x000 + write-only + + + TASKS_TXEN + Enable RADIO in TX mode + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RXEN + Enable RADIO in RX mode + 0x004 + write-only + + + TASKS_RXEN + Enable RADIO in RX mode + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_START + Start RADIO + 0x008 + write-only + + + TASKS_START + Start RADIO + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop RADIO + 0x00C + write-only + + + TASKS_STOP + Stop RADIO + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_DISABLE + Disable RADIO + 0x010 + write-only + + + TASKS_DISABLE + Disable RADIO + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RSSISTART + Start the RSSI and take one single sample of the receive signal strength + 0x014 + write-only + + + TASKS_RSSISTART + Start the RSSI and take one single sample of the receive signal strength + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RSSISTOP + Stop the RSSI measurement + 0x018 + write-only + + + TASKS_RSSISTOP + Stop the RSSI measurement + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_BCSTART + Start the bit counter + 0x01C + write-only + + + TASKS_BCSTART + Start the bit counter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_BCSTOP + Stop the bit counter + 0x020 + write-only + + + TASKS_BCSTOP + Stop the bit counter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_EDSTART + Start the energy detect measurement used in IEEE 802.15.4 mode + 0x024 + write-only + + + TASKS_EDSTART + Start the energy detect measurement used in IEEE 802.15.4 mode + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_EDSTOP + Stop the energy detect measurement + 0x028 + write-only + + + TASKS_EDSTOP + Stop the energy detect measurement + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CCASTART + Start the clear channel assessment used in IEEE 802.15.4 mode + 0x02C + write-only + + + TASKS_CCASTART + Start the clear channel assessment used in IEEE 802.15.4 mode + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CCASTOP + Stop the clear channel assessment + 0x030 + write-only + + + TASKS_CCASTOP + Stop the clear channel assessment + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_TXEN + Subscribe configuration for task TXEN + 0x080 + read-write + + + CHIDX + DPPI channel that task TXEN will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_RXEN + Subscribe configuration for task RXEN + 0x084 + read-write + + + CHIDX + DPPI channel that task RXEN will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x088 + read-write + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x08C + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_DISABLE + Subscribe configuration for task DISABLE + 0x090 + read-write + + + CHIDX + DPPI channel that task DISABLE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_RSSISTART + Subscribe configuration for task RSSISTART + 0x094 + read-write + + + CHIDX + DPPI channel that task RSSISTART will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_RSSISTOP + Subscribe configuration for task RSSISTOP + 0x098 + read-write + + + CHIDX + DPPI channel that task RSSISTOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_BCSTART + Subscribe configuration for task BCSTART + 0x09C + read-write + + + CHIDX + DPPI channel that task BCSTART will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_BCSTOP + Subscribe configuration for task BCSTOP + 0x0A0 + read-write + + + CHIDX + DPPI channel that task BCSTOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_EDSTART + Subscribe configuration for task EDSTART + 0x0A4 + read-write + + + CHIDX + DPPI channel that task EDSTART will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_EDSTOP + Subscribe configuration for task EDSTOP + 0x0A8 + read-write + + + CHIDX + DPPI channel that task EDSTOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_CCASTART + Subscribe configuration for task CCASTART + 0x0AC + read-write + + + CHIDX + DPPI channel that task CCASTART will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_CCASTOP + Subscribe configuration for task CCASTOP + 0x0B0 + read-write + + + CHIDX + DPPI channel that task CCASTOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_READY + RADIO has ramped up and is ready to be started + 0x100 + read-write + + + EVENTS_READY + RADIO has ramped up and is ready to be started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ADDRESS + Address sent or received + 0x104 + read-write + + + EVENTS_ADDRESS + Address sent or received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_PAYLOAD + Packet payload sent or received + 0x108 + read-write + + + EVENTS_PAYLOAD + Packet payload sent or received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_END + Packet sent or received + 0x10C + read-write + + + EVENTS_END + Packet sent or received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DISABLED + RADIO has been disabled + 0x110 + read-write + + + EVENTS_DISABLED + RADIO has been disabled + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DEVMATCH + A device address match occurred on the last received packet + 0x114 + read-write + + + EVENTS_DEVMATCH + A device address match occurred on the last received packet + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DEVMISS + No device address match occurred on the last received packet + 0x118 + read-write + + + EVENTS_DEVMISS + No device address match occurred on the last received packet + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RSSIEND + Sampling of receive signal strength complete + 0x11C + read-write + + + EVENTS_RSSIEND + Sampling of receive signal strength complete + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_BCMATCH + Bit counter reached bit count value + 0x128 + read-write + + + EVENTS_BCMATCH + Bit counter reached bit count value + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CRCOK + Packet received with CRC ok + 0x130 + read-write + + + EVENTS_CRCOK + Packet received with CRC ok + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CRCERROR + Packet received with CRC error + 0x134 + read-write + + + EVENTS_CRCERROR + Packet received with CRC error + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_FRAMESTART + IEEE 802.15.4 length field received + 0x138 + read-write + + + EVENTS_FRAMESTART + IEEE 802.15.4 length field received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_EDEND + Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. + 0x13C + read-write + + + EVENTS_EDEND + Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_EDSTOPPED + The sampling of energy detection has stopped + 0x140 + read-write + + + EVENTS_EDSTOPPED + The sampling of energy detection has stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CCAIDLE + Wireless medium in idle - clear to send + 0x144 + read-write + + + EVENTS_CCAIDLE + Wireless medium in idle - clear to send + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CCABUSY + Wireless medium busy - do not send + 0x148 + read-write + + + EVENTS_CCABUSY + Wireless medium busy - do not send + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CCASTOPPED + The CCA has stopped + 0x14C + read-write + + + EVENTS_CCASTOPPED + The CCA has stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RATEBOOST + Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. + 0x150 + read-write + + + EVENTS_RATEBOOST + Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXREADY + RADIO has ramped up and is ready to be started TX path + 0x154 + read-write + + + EVENTS_TXREADY + RADIO has ramped up and is ready to be started TX path + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXREADY + RADIO has ramped up and is ready to be started RX path + 0x158 + read-write + + + EVENTS_RXREADY + RADIO has ramped up and is ready to be started RX path + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_MHRMATCH + MAC header match found + 0x15C + read-write + + + EVENTS_MHRMATCH + MAC header match found + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SYNC + Preamble indicator + 0x168 + read-write + + + EVENTS_SYNC + Preamble indicator + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_PHYEND + Generated when last bit is sent on air, or received from air + 0x16C + read-write + + + EVENTS_PHYEND + Generated when last bit is sent on air, or received from air + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CTEPRESENT + CTE is present (early warning right after receiving CTEInfo byte) + 0x170 + read-write + + + EVENTS_CTEPRESENT + CTE is present (early warning right after receiving CTEInfo byte) + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_READY + Publish configuration for event READY + 0x180 + read-write + + + CHIDX + DPPI channel that event READY will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ADDRESS + Publish configuration for event ADDRESS + 0x184 + read-write + + + CHIDX + DPPI channel that event ADDRESS will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_PAYLOAD + Publish configuration for event PAYLOAD + 0x188 + read-write + + + CHIDX + DPPI channel that event PAYLOAD will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x18C + read-write + + + CHIDX + DPPI channel that event END will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_DISABLED + Publish configuration for event DISABLED + 0x190 + read-write + + + CHIDX + DPPI channel that event DISABLED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_DEVMATCH + Publish configuration for event DEVMATCH + 0x194 + read-write + + + CHIDX + DPPI channel that event DEVMATCH will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_DEVMISS + Publish configuration for event DEVMISS + 0x198 + read-write + + + CHIDX + DPPI channel that event DEVMISS will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_RSSIEND + Publish configuration for event RSSIEND + 0x19C + read-write + + + CHIDX + DPPI channel that event RSSIEND will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_BCMATCH + Publish configuration for event BCMATCH + 0x1A8 + read-write + + + CHIDX + DPPI channel that event BCMATCH will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_CRCOK + Publish configuration for event CRCOK + 0x1B0 + read-write + + + CHIDX + DPPI channel that event CRCOK will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_CRCERROR + Publish configuration for event CRCERROR + 0x1B4 + read-write + + + CHIDX + DPPI channel that event CRCERROR will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_FRAMESTART + Publish configuration for event FRAMESTART + 0x1B8 + read-write + + + CHIDX + DPPI channel that event FRAMESTART will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_EDEND + Publish configuration for event EDEND + 0x1BC + read-write + + + CHIDX + DPPI channel that event EDEND will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_EDSTOPPED + Publish configuration for event EDSTOPPED + 0x1C0 + read-write + + + CHIDX + DPPI channel that event EDSTOPPED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_CCAIDLE + Publish configuration for event CCAIDLE + 0x1C4 + read-write + + + CHIDX + DPPI channel that event CCAIDLE will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_CCABUSY + Publish configuration for event CCABUSY + 0x1C8 + read-write + + + CHIDX + DPPI channel that event CCABUSY will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_CCASTOPPED + Publish configuration for event CCASTOPPED + 0x1CC + read-write + + + CHIDX + DPPI channel that event CCASTOPPED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_RATEBOOST + Publish configuration for event RATEBOOST + 0x1D0 + read-write + + + CHIDX + DPPI channel that event RATEBOOST will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_TXREADY + Publish configuration for event TXREADY + 0x1D4 + read-write + + + CHIDX + DPPI channel that event TXREADY will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_RXREADY + Publish configuration for event RXREADY + 0x1D8 + read-write + + + CHIDX + DPPI channel that event RXREADY will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_MHRMATCH + Publish configuration for event MHRMATCH + 0x1DC + read-write + + + CHIDX + DPPI channel that event MHRMATCH will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_SYNC + Publish configuration for event SYNC + 0x1E8 + read-write + + + CHIDX + DPPI channel that event SYNC will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_PHYEND + Publish configuration for event PHYEND + 0x1EC + read-write + + + CHIDX + DPPI channel that event PHYEND will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_CTEPRESENT + Publish configuration for event CTEPRESENT + 0x1F0 + read-write + + + CHIDX + DPPI channel that event CTEPRESENT will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + READY_START + Shortcut between event READY and task START + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + END_DISABLE + Shortcut between event END and task DISABLE + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DISABLED_TXEN + Shortcut between event DISABLED and task TXEN + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DISABLED_RXEN + Shortcut between event DISABLED and task RXEN + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + ADDRESS_RSSISTART + Shortcut between event ADDRESS and task RSSISTART + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + END_START + Shortcut between event END and task START + 5 + 5 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + ADDRESS_BCSTART + Shortcut between event ADDRESS and task BCSTART + 6 + 6 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DISABLED_RSSISTOP + Shortcut between event DISABLED and task RSSISTOP + 8 + 8 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + RXREADY_CCASTART + Shortcut between event RXREADY and task CCASTART + 11 + 11 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + CCAIDLE_TXEN + Shortcut between event CCAIDLE and task TXEN + 12 + 12 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + CCABUSY_DISABLE + Shortcut between event CCABUSY and task DISABLE + 13 + 13 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + FRAMESTART_BCSTART + Shortcut between event FRAMESTART and task BCSTART + 14 + 14 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + READY_EDSTART + Shortcut between event READY and task EDSTART + 15 + 15 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + EDEND_DISABLE + Shortcut between event EDEND and task DISABLE + 16 + 16 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + CCAIDLE_STOP + Shortcut between event CCAIDLE and task STOP + 17 + 17 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + TXREADY_START + Shortcut between event TXREADY and task START + 18 + 18 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + RXREADY_START + Shortcut between event RXREADY and task START + 19 + 19 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + PHYEND_DISABLE + Shortcut between event PHYEND and task DISABLE + 20 + 20 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + PHYEND_START + Shortcut between event PHYEND and task START + 21 + 21 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + READY + Write '1' to enable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ADDRESS + Write '1' to enable interrupt for event ADDRESS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PAYLOAD + Write '1' to enable interrupt for event PAYLOAD + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + END + Write '1' to enable interrupt for event END + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DISABLED + Write '1' to enable interrupt for event DISABLED + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DEVMATCH + Write '1' to enable interrupt for event DEVMATCH + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DEVMISS + Write '1' to enable interrupt for event DEVMISS + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RSSIEND + Write '1' to enable interrupt for event RSSIEND + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + BCMATCH + Write '1' to enable interrupt for event BCMATCH + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CRCOK + Write '1' to enable interrupt for event CRCOK + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CRCERROR + Write '1' to enable interrupt for event CRCERROR + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + FRAMESTART + Write '1' to enable interrupt for event FRAMESTART + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + EDEND + Write '1' to enable interrupt for event EDEND + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + EDSTOPPED + Write '1' to enable interrupt for event EDSTOPPED + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CCAIDLE + Write '1' to enable interrupt for event CCAIDLE + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CCABUSY + Write '1' to enable interrupt for event CCABUSY + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CCASTOPPED + Write '1' to enable interrupt for event CCASTOPPED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RATEBOOST + Write '1' to enable interrupt for event RATEBOOST + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXREADY + Write '1' to enable interrupt for event TXREADY + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXREADY + Write '1' to enable interrupt for event RXREADY + 22 + 22 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + MHRMATCH + Write '1' to enable interrupt for event MHRMATCH + 23 + 23 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SYNC + Write '1' to enable interrupt for event SYNC + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PHYEND + Write '1' to enable interrupt for event PHYEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CTEPRESENT + Write '1' to enable interrupt for event CTEPRESENT + 28 + 28 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + READY + Write '1' to disable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ADDRESS + Write '1' to disable interrupt for event ADDRESS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PAYLOAD + Write '1' to disable interrupt for event PAYLOAD + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + END + Write '1' to disable interrupt for event END + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DISABLED + Write '1' to disable interrupt for event DISABLED + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DEVMATCH + Write '1' to disable interrupt for event DEVMATCH + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DEVMISS + Write '1' to disable interrupt for event DEVMISS + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RSSIEND + Write '1' to disable interrupt for event RSSIEND + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + BCMATCH + Write '1' to disable interrupt for event BCMATCH + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CRCOK + Write '1' to disable interrupt for event CRCOK + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CRCERROR + Write '1' to disable interrupt for event CRCERROR + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + FRAMESTART + Write '1' to disable interrupt for event FRAMESTART + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + EDEND + Write '1' to disable interrupt for event EDEND + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + EDSTOPPED + Write '1' to disable interrupt for event EDSTOPPED + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CCAIDLE + Write '1' to disable interrupt for event CCAIDLE + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CCABUSY + Write '1' to disable interrupt for event CCABUSY + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CCASTOPPED + Write '1' to disable interrupt for event CCASTOPPED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RATEBOOST + Write '1' to disable interrupt for event RATEBOOST + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXREADY + Write '1' to disable interrupt for event TXREADY + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXREADY + Write '1' to disable interrupt for event RXREADY + 22 + 22 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + MHRMATCH + Write '1' to disable interrupt for event MHRMATCH + 23 + 23 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SYNC + Write '1' to disable interrupt for event SYNC + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PHYEND + Write '1' to disable interrupt for event PHYEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CTEPRESENT + Write '1' to disable interrupt for event CTEPRESENT + 28 + 28 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + CRCSTATUS + CRC status + 0x400 + read-only + + + CRCSTATUS + CRC status of packet received + 0 + 0 + + + CRCError + Packet received with CRC error + 0 + + + CRCOk + Packet received with CRC ok + 1 + + + + + + + RXMATCH + Received address + 0x408 + read-only + + + RXMATCH + Received address + 0 + 2 + + + + + RXCRC + CRC field of previously received packet + 0x40C + read-only + + + RXCRC + CRC field of previously received packet + 0 + 23 + + + + + DAI + Device address match index + 0x410 + read-only + + + DAI + Device address match index + 0 + 2 + + + + + PDUSTAT + Payload status + 0x414 + read-only + + + PDUSTAT + Status on payload length vs. PCNF1.MAXLEN + 0 + 0 + + + LessThan + Payload less than PCNF1.MAXLEN + 0 + + + GreaterThan + Payload greater than PCNF1.MAXLEN + 1 + + + + + CISTAT + Status on what rate packet is received with in Long Range + 1 + 2 + + + LR125kbit + Frame is received at 125 kbps + 0 + + + LR500kbit + Frame is received at 500 kbps + 1 + + + + + + + CTESTATUS + CTEInfo parsed from received packet + 0x44C + read-only + + + CTETIME + CTETime parsed from packet + 0 + 4 + + + RFU + RFU parsed from packet + 5 + 5 + + + CTETYPE + CTEType parsed from packet + 6 + 7 + + + + + DFESTATUS + DFE status information + 0x458 + read-only + + + SWITCHINGSTATE + Internal state of switching state machine + 0 + 2 + + + Idle + Switching state Idle + 0 + + + Offset + Switching state Offset + 1 + + + Guard + Switching state Guard + 2 + + + Ref + Switching state Ref + 3 + + + Switching + Switching state Switching + 4 + + + Ending + Switching state Ending + 5 + + + + + SAMPLINGSTATE + Internal state of sampling state machine + 4 + 4 + + + Idle + Sampling state Idle + 0 + + + Sampling + Sampling state Sampling + 1 + + + + + + + PACKETPTR + Packet pointer + 0x504 + read-write + 0x01000000 + + + PACKETPTR + Packet pointer + 0 + 31 + + + + + FREQUENCY + Frequency + 0x508 + read-write + 0x00000002 + + + FREQUENCY + Radio channel frequency + 0 + 6 + + + MAP + Channel map selection + 8 + 8 + + + Default + Channel map between 2400 MHz and 2500 MHz + 0 + + + Low + Channel map between 2360 MHz and 2460 MHz + 1 + + + + + + + TXPOWER + Output power + 0x50C + read-write + + + TXPOWER + RADIO output power + 0 + 7 + + + 0dBm + 0 dBm + 0x0 + + + Neg1dBm + -1 dBm + 0xFF + + + Neg2dBm + -2 dBm + 0xFE + + + Neg3dBm + -3 dBm + 0xFD + + + Neg4dBm + -4 dBm + 0xFC + + + Neg5dBm + -5 dBm + 0xFB + + + Neg6dBm + -6 dBm + 0xFA + + + Neg7dBm + -7 dBm + 0xF9 + + + Neg8dBm + -8 dBm + 0xF8 + + + Neg12dBm + -12 dBm + 0xF4 + + + Neg16dBm + -16 dBm + 0xF0 + + + Neg20dBm + -20 dBm + 0xEC + + + Neg30dBm + Deprecated enumerator - -40 dBm + 0xE2 + + + Neg40dBm + -40 dBm + 0xD8 + + + + + + + MODE + Data rate and modulation + 0x510 + read-write + + + MODE + Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation. + 0 + 3 + + + Nrf_1Mbit + 1 Mbps Nordic proprietary radio mode + 0 + + + Nrf_2Mbit + 2 Mbps Nordic proprietary radio mode + 1 + + + Ble_1Mbit + 1 Mbps BLE + 3 + + + Ble_2Mbit + 2 Mbps BLE + 4 + + + Ble_LR125Kbit + Long Range 125 kbps TX, 125 kbps and 500 kbps RX + 5 + + + Ble_LR500Kbit + Long Range 500 kbps TX, 125 kbps and 500 kbps RX + 6 + + + Ieee802154_250Kbit + IEEE 802.15.4-2006 250 kbps + 15 + + + + + + + PCNF0 + Packet configuration register 0 + 0x514 + read-write + + + LFLEN + Length on air of LENGTH field in number of bits + 0 + 3 + + + S0LEN + Length on air of S0 field in number of bytes + 8 + 8 + + + S1LEN + Length on air of S1 field in number of bits + 16 + 19 + + + S1INCL + Include or exclude S1 field in RAM + 20 + 20 + + + Automatic + Include S1 field in RAM only if S1LEN &gt; 0 + 0 + + + Include + Always include S1 field in RAM independent of S1LEN + 1 + + + + + CILEN + Length of code indicator - Long Range + 22 + 23 + + + PLEN + Length of preamble on air. Decision point: TASKS_START task + 24 + 25 + + + 8bit + 8-bit preamble + 0 + + + 16bit + 16-bit preamble + 1 + + + 32bitZero + 32-bit zero preamble - used for IEEE 802.15.4 + 2 + + + LongRange + Preamble - used for Bluetooth LE Long Range + 3 + + + + + CRCINC + Indicates if LENGTH field contains CRC or not + 26 + 26 + + + Exclude + LENGTH does not contain CRC + 0 + + + Include + LENGTH includes CRC + 1 + + + + + TERMLEN + Length of TERM field in Long Range operation + 29 + 30 + + + + + PCNF1 + Packet configuration register 1 + 0x518 + read-write + + + MAXLEN + Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. + 0 + 7 + + + STATLEN + Static length in number of bytes + 8 + 15 + + + BALEN + Base address length in number of bytes + 16 + 18 + + + ENDIAN + On-air endianness of packet, this applies to the S0, LENGTH, S1, and the PAYLOAD fields. + 24 + 24 + + + Little + Least significant bit on air first + 0 + + + Big + Most significant bit on air first + 1 + + + + + WHITEEN + Enable or disable packet whitening + 25 + 25 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + BASE0 + Base address 0 + 0x51C + read-write + + + BASE0 + Base address 0 + 0 + 31 + + + + + BASE1 + Base address 1 + 0x520 + read-write + + + BASE1 + Base address 1 + 0 + 31 + + + + + PREFIX0 + Prefixes bytes for logical addresses 0-3 + 0x524 + read-write + + + AP0 + Address prefix 0. + 0 + 7 + + + AP1 + Address prefix 1. + 8 + 15 + + + AP2 + Address prefix 2. + 16 + 23 + + + AP3 + Address prefix 3. + 24 + 31 + + + + + PREFIX1 + Prefixes bytes for logical addresses 4-7 + 0x528 + read-write + + + AP4 + Address prefix 4. + 0 + 7 + + + AP5 + Address prefix 5. + 8 + 15 + + + AP6 + Address prefix 6. + 16 + 23 + + + AP7 + Address prefix 7. + 24 + 31 + + + + + TXADDRESS + Transmit address select + 0x52C + read-write + + + TXADDRESS + Transmit address select + 0 + 2 + + + + + RXADDRESSES + Receive address select + 0x530 + read-write + + + ADDR0 + Enable or disable reception on logical address 0. + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR1 + Enable or disable reception on logical address 1. + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR2 + Enable or disable reception on logical address 2. + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR3 + Enable or disable reception on logical address 3. + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR4 + Enable or disable reception on logical address 4. + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR5 + Enable or disable reception on logical address 5. + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR6 + Enable or disable reception on logical address 6. + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR7 + Enable or disable reception on logical address 7. + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + CRCCNF + CRC configuration + 0x534 + read-write + + + LEN + CRC length in number of bytes For MODE Ble_LR125Kbit and Ble_LR500Kbit, only LEN set to 3 is supported + 0 + 1 + + + Disabled + CRC length is zero and CRC calculation is disabled + 0 + + + One + CRC length is one byte and CRC calculation is enabled + 1 + + + Two + CRC length is two bytes and CRC calculation is enabled + 2 + + + Three + CRC length is three bytes and CRC calculation is enabled + 3 + + + + + SKIPADDR + Include or exclude packet address field out of CRC calculation. + 8 + 9 + + + Include + CRC calculation includes address field + 0 + + + Skip + CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. + 1 + + + Ieee802154 + CRC calculation as per 802.15.4 standard. Starting at first byte after length field. + 2 + + + + + + + CRCPOLY + CRC polynomial + 0x538 + read-write + 0x00000000 + + + CRCPOLY + CRC polynomial + 0 + 23 + + + + + CRCINIT + CRC initial value + 0x53C + read-write + + + CRCINIT + CRC initial value + 0 + 23 + + + + + TIFS + Interframe spacing in us + 0x544 + read-write + + + TIFS + Interframe spacing in us. + 0 + 9 + + + + + RSSISAMPLE + RSSI sample + 0x548 + read-only + + + RSSISAMPLE + RSSI sample. + 0 + 6 + + + + + STATE + Current radio state + 0x550 + read-only + + + STATE + Current radio state + 0 + 3 + + + Disabled + RADIO is in the Disabled state + 0 + + + RxRu + RADIO is in the RXRU state + 1 + + + RxIdle + RADIO is in the RXIDLE state + 2 + + + Rx + RADIO is in the RX state + 3 + + + RxDisable + RADIO is in the RXDISABLED state + 4 + + + TxRu + RADIO is in the TXRU state + 9 + + + TxIdle + RADIO is in the TXIDLE state + 10 + + + Tx + RADIO is in the TX state + 11 + + + TxDisable + RADIO is in the TXDISABLED state + 12 + + + + + + + DATAWHITEIV + Data whitening initial value + 0x554 + read-write + 0x00000040 + + + DATAWHITEIV + Data whitening initial value. Bit 6 is hardwired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. + 0 + 6 + + + + + BCC + Bit counter compare + 0x560 + read-write + + + BCC + Bit counter compare + 0 + 31 + + + + + 0x8 + 0x4 + DAB[%s] + Description collection: Device address base segment n + 0x600 + read-write + + + DAB + Device address base segment n + 0 + 31 + + + + + 0x8 + 0x4 + DAP[%s] + Description collection: Device address prefix n + 0x620 + read-write + + + DAP + Device address prefix n + 0 + 15 + + + + + DACNF + Device address match configuration + 0x640 + read-write + + + ENA0 + Enable or disable device address matching using device address 0 + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA1 + Enable or disable device address matching using device address 1 + 1 + 1 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA2 + Enable or disable device address matching using device address 2 + 2 + 2 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA3 + Enable or disable device address matching using device address 3 + 3 + 3 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA4 + Enable or disable device address matching using device address 4 + 4 + 4 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA5 + Enable or disable device address matching using device address 5 + 5 + 5 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA6 + Enable or disable device address matching using device address 6 + 6 + 6 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA7 + Enable or disable device address matching using device address 7 + 7 + 7 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + TXADD0 + TxAdd for device address 0 + 8 + 8 + + + TXADD1 + TxAdd for device address 1 + 9 + 9 + + + TXADD2 + TxAdd for device address 2 + 10 + 10 + + + TXADD3 + TxAdd for device address 3 + 11 + 11 + + + TXADD4 + TxAdd for device address 4 + 12 + 12 + + + TXADD5 + TxAdd for device address 5 + 13 + 13 + + + TXADD6 + TxAdd for device address 6 + 14 + 14 + + + TXADD7 + TxAdd for device address 7 + 15 + 15 + + + + + MHRMATCHCONF + Search pattern configuration + 0x644 + read-write + + + MHRMATCHCONF + Search pattern configuration + 0 + 31 + + + + + MHRMATCHMAS + Pattern mask + 0x648 + read-write + + + MHRMATCHMAS + Pattern mask + 0 + 31 + + + + + MODECNF0 + Radio mode configuration register 0 + 0x650 + read-write + 0x00000200 + + + RU + Radio ramp-up time + 0 + 0 + + + Default + Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51 + 0 + + + Fast + Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specifications for more information + 1 + + + + + DTX + Default TX value + 8 + 9 + + + B1 + Transmit '1' + 0 + + + B0 + Transmit '0' + 1 + + + Center + Transmit center frequency + 2 + + + + + + + SFD + IEEE 802.15.4 start of frame delimiter + 0x660 + read-write + 0x000000A7 + + + SFD + IEEE 802.15.4 start of frame delimiter + 0 + 7 + + + + + EDCNT + IEEE 802.15.4 energy detect loop count + 0x664 + read-write + 0x00000000 + + + EDCNT + IEEE 802.15.4 energy detect loop count + 0 + 20 + + + + + EDSAMPLE + IEEE 802.15.4 energy detect level + 0x668 + read-only + 0x00000000 + + + EDLVL + IEEE 802.15.4 energy detect level + 0 + 7 + + + + + CCACTRL + IEEE 802.15.4 clear channel assessment control + 0x66C + read-write + 0x052D0000 + + + CCAMODE + CCA mode of operation + 0 + 2 + + + EdMode + Energy above threshold + 0 + + + CarrierMode + Carrier seen + 1 + + + CarrierAndEdMode + Energy above threshold AND carrier seen + 2 + + + CarrierOrEdMode + Energy above threshold OR carrier seen + 3 + + + EdModeTest1 + Energy above threshold test mode that will abort when first ED measurement over threshold is seen. No averaging. + 4 + + + + + CCAEDTHRES + CCA energy busy threshold. Used in all the CCA modes except CarrierMode. + 8 + 15 + + + CCACORRTHRES + CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode, and CarrierOrEdMode. + 16 + 23 + + + CCACORRCNT + Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect is enabled. + 24 + 31 + + + + + DFEMODE + Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure (AOD) + 0x900 + read-write + 0x00000000 + + + DFEOPMODE + Direction finding operation mode + 0 + 1 + + + Disabled + Direction finding mode disabled + 0 + + + AoD + Direction finding mode set to AoD + 2 + + + AoA + Direction finding mode set to AoA + 3 + + + + + + + CTEINLINECONF + Configuration for CTE inline mode + 0x904 + read-write + 0x00002800 + + + CTEINLINECTRLEN + Enable parsing of CTEInfo from received packet in BLE modes + 0 + 0 + + + Enabled + Parsing of CTEInfo is enabled + 1 + + + Disabled + Parsing of CTEInfo is disabled + 0 + + + + + CTEINFOINS1 + CTEInfo is S1 byte or not + 3 + 3 + + + InS1 + CTEInfo is in S1 byte (data PDU) + 1 + + + NotInS1 + CTEInfo is NOT in S1 byte (advertising PDU) + 0 + + + + + CTEERRORHANDLING + Sampling/switching if CRC is not OK + 4 + 4 + + + Yes + Sampling and antenna switching also when CRC is not OK + 1 + + + No + No sampling and antenna switching when CRC is not OK + 0 + + + + + CTETIMEVALIDRANGE + Max range of CTETime + 6 + 7 + + + 20 + 20 in 8 us unit (default) Set to 20 if parsed CTETime is larger than 20 + 0 + + + 31 + 31 in 8 us unit + 1 + + + 63 + 63 in 8 us unit + 2 + + + + + CTEINLINERXMODE1US + Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set. + 10 + 12 + + + 4us + 4 us + 1 + + + 2us + 2 us + 2 + + + 1us + 1 us + 3 + + + 500ns + 0.5 us + 4 + + + 250ns + 0.25 us + 5 + + + 125ns + 0.125 us + 6 + + + + + CTEINLINERXMODE2US + Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set. + 13 + 15 + + + 4us + 4 us + 1 + + + 2us + 2 us + 2 + + + 1us + 1 us + 3 + + + 500ns + 0.5 us + 4 + + + 250ns + 0.25 us + 5 + + + 125ns + 0.125 us + 6 + + + + + S0CONF + S0 bit pattern to match + 16 + 23 + + + S0MASK + S0 bit mask to set which bit to match + 24 + 31 + + + + + DFECTRL1 + Various configuration for Direction finding + 0x910 + read-write + 0x00023282 + + + NUMBEROF8US + Length of the AoA/AoD procedure in number of 8 us units + 0 + 5 + + + DFEINEXTENSION + Add CTE extension and do antenna switching/sampling in this extension + 7 + 7 + + + CRC + AoA/AoD procedure triggered at end of CRC + 1 + + + Payload + Antenna switching/sampling is done in the packet payload + 0 + + + + + TSWITCHSPACING + Interval between every time the antenna is changed in the SWITCHING state + 8 + 10 + + + 4us + 4 us + 1 + + + 2us + 2 us + 2 + + + 1us + 1 us + 3 + + + + + TSAMPLESPACINGREF + Interval between samples in the REFERENCE period + 12 + 14 + + + 4us + 4 us + 1 + + + 2us + 2 us + 2 + + + 1us + 1 us + 3 + + + 500ns + 0.5 us + 4 + + + 250ns + 0.25 us + 5 + + + 125ns + 0.125 us + 6 + + + + + SAMPLETYPE + Whether to sample I/Q or magnitude/phase + 15 + 15 + + + IQ + Complex samples in I and Q + 0 + + + MagPhase + Complex samples as magnitude and phase + 1 + + + + + TSAMPLESPACING + Interval between samples in the SWITCHING period when CTEINLINECTRLEN is 0 + 16 + 18 + + + 4us + 4 us + 1 + + + 2us + 2 us + 2 + + + 1us + 1 us + 3 + + + 500ns + 0.5 us + 4 + + + 250ns + 0.25 us + 5 + + + 125ns + 0.125 us + 6 + + + + + REPEATPATTERN + Repeat each individual antenna pattern N times sequentially, i.e. P0, P0, P1, P1, P2, P2, P3, P3, etc. + 20 + 23 + + + NoRepeat + Do not repeat (1 time in total) + 0 + + + + + AGCBACKOFFGAIN + Gain will be lowered by the specified number of gain steps at the start of CTE + 24 + 27 + + + + + DFECTRL2 + Start offset for Direction finding + 0x914 + read-write + 0x00000000 + + + TSWITCHOFFSET + Signed value offset after the end of the CRC before starting switching in number of 16 MHz clock cycles + 0 + 12 + + + TSAMPLEOFFSET + Signed value offset in number of 16 MHz clock cycles for fine tuning of the sampling instant for all IQ samples. With TSAMPLEOFFSET=0 the first sample is taken immediately at the start of the reference period + 16 + 27 + + + + + SWITCHPATTERN + GPIO patterns to be used for each antenna + 0x928 + read-write + 0x00000000 + + + SWITCHPATTERN + Fill array of GPIO patterns for antenna control. + 0 + 7 + + + + + CLEARPATTERN + Clear the GPIO pattern array for antenna control + 0x92C + read-write + + + CLEARPATTERN + Clears GPIO pattern array for antenna control + 0 + 0 + oneToClear + + + Clear + Clear the GPIO pattern + 1 + + + + + + + PSEL + Unspecified + RADIO_PSEL + read-write + 0x930 + + 0x8 + 0x4 + DFEGPIO[%s] + Description collection: Pin select for DFE pin n + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + DFEPACKET + DFE packet EasyDMA channel + RADIO_DFEPACKET + read-write + 0x950 + + PTR + Data pointer + 0x000 + read-write + 0x01000000 + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of buffer words to transfer + 0x004 + read-write + 0x00001000 + + + MAXCNT + Maximum number of buffer words to transfer + 0 + 13 + + + + + AMOUNT + Number of samples transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of samples transferred in the last transaction + 0 + 15 + + + + + + POWER + Peripheral power control + 0xFFC + read-write + 0x00000001 + + + POWER + Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. + 0 + 0 + + + Disabled + Peripheral is powered off + 0 + + + Enabled + Peripheral is powered on + 1 + + + + + + + + + RNG_NS + Random Number Generator + 0x41009000 + RNG + + + + 0 + 0x1000 + registers + + + RNG + 9 + + RNG + 0x20 + + + TASKS_START + Task starting the random number generator + 0x000 + write-only + + + TASKS_START + Task starting the random number generator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Task stopping the random number generator + 0x004 + write-only + + + TASKS_STOP + Task stopping the random number generator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_VALRDY + Event being generated for every new random number written to the VALUE register + 0x100 + read-write + + + EVENTS_VALRDY + Event being generated for every new random number written to the VALUE register + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_VALRDY + Publish configuration for event VALRDY + 0x180 + read-write + + + CHIDX + DPPI channel that event VALRDY will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + VALRDY_STOP + Shortcut between event VALRDY and task STOP + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + VALRDY + Write '1' to enable interrupt for event VALRDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + VALRDY + Write '1' to disable interrupt for event VALRDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + CONFIG + Configuration register + 0x504 + read-write + + + DERCEN + Bias correction + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + + + VALUE + Output random number + 0x508 + read-only + + + VALUE + Generated random number + 0 + 7 + + + + + + + GPIOTE_NS + GPIO Tasks and Events + 0x4100A000 + GPIOTE + + + + 0 + 0x1000 + registers + + + GPIOTE + 10 + + GPIOTE + 0x20 + + + 0x8 + 0x4 + TASKS_OUT[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. + 0x000 + write-only + + + TASKS_OUT + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x8 + 0x4 + TASKS_SET[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. + 0x030 + write-only + + + TASKS_SET + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x8 + 0x4 + TASKS_CLR[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. + 0x060 + write-only + + + TASKS_CLR + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_OUT[%s] + Description collection: Subscribe configuration for task OUT[n] + 0x080 + read-write + + + CHIDX + DPPI channel that task OUT[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_SET[%s] + Description collection: Subscribe configuration for task SET[n] + 0x0B0 + read-write + + + CHIDX + DPPI channel that task SET[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_CLR[%s] + Description collection: Subscribe configuration for task CLR[n] + 0x0E0 + read-write + + + CHIDX + DPPI channel that task CLR[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + 0x8 + 0x4 + EVENTS_IN[%s] + Description collection: Event generated from pin specified in CONFIG[n].PSEL + 0x100 + read-write + + + EVENTS_IN + Event generated from pin specified in CONFIG[n].PSEL + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_PORT + Event generated from multiple input GPIO pins with SENSE mechanism enabled + 0x17C + read-write + + + EVENTS_PORT + Event generated from multiple input GPIO pins with SENSE mechanism enabled + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x8 + 0x4 + PUBLISH_IN[%s] + Description collection: Publish configuration for event IN[n] + 0x180 + read-write + + + CHIDX + DPPI channel that event IN[n] will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_PORT + Publish configuration for event PORT + 0x1FC + read-write + + + CHIDX + DPPI channel that event PORT will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + IN0 + Write '1' to enable interrupt for event IN[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN1 + Write '1' to enable interrupt for event IN[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN2 + Write '1' to enable interrupt for event IN[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN3 + Write '1' to enable interrupt for event IN[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN4 + Write '1' to enable interrupt for event IN[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN5 + Write '1' to enable interrupt for event IN[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN6 + Write '1' to enable interrupt for event IN[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN7 + Write '1' to enable interrupt for event IN[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PORT + Write '1' to enable interrupt for event PORT + 31 + 31 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + IN0 + Write '1' to disable interrupt for event IN[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN1 + Write '1' to disable interrupt for event IN[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN2 + Write '1' to disable interrupt for event IN[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN3 + Write '1' to disable interrupt for event IN[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN4 + Write '1' to disable interrupt for event IN[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN5 + Write '1' to disable interrupt for event IN[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN6 + Write '1' to disable interrupt for event IN[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN7 + Write '1' to disable interrupt for event IN[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PORT + Write '1' to disable interrupt for event PORT + 31 + 31 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + LATENCY + Latency selection for Event mode (MODE=Event) with rising or falling edge detection on the pin. + 0x504 + read-write + 0x00000001 + + + LATENCY + Latency setting + 0 + 0 + + + LowPower + Low power setting, for signals with minimum hold time tGPIOTE,HOLD,LP; refer to Electrical specification section + 0 + + + LowLatency + Low latency setting, for signals with minimum hold time tGPIOTE,HOLD,LL; refer to Electrical specification section + 1 + + + + + + + 0x8 + 0x4 + CONFIG[%s] + Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event + 0x510 + read-write + + + MODE + Mode + 0 + 1 + + + Disabled + Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. + 0 + + + Event + Event mode + 1 + + + Task + Task mode + 3 + + + + + PSEL + GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event + 8 + 12 + + + PORT + Port number + 13 + 13 + + + POLARITY + When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. + 16 + 17 + + + None + Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. + 0 + + + LoToHi + Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. + 1 + + + HiToLo + Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. + 2 + + + Toggle + Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. + 3 + + + + + OUTINIT + When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. + 20 + 20 + + + Low + Task mode: Initial value of pin before task triggering is low + 0 + + + High + Task mode: Initial value of pin before task triggering is high + 1 + + + + + + + + + WDT_NS + Watchdog Timer + 0x4100B000 + WDT + + + + 0 + 0x1000 + registers + + + WDT + 11 + + WDT + 0x20 + + + TASKS_START + Start WDT + 0x000 + write-only + + + TASKS_START + Start WDT + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop WDT + 0x004 + write-only + + + TASKS_STOP + Stop WDT + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_TIMEOUT + Watchdog timeout + 0x100 + read-write + + + EVENTS_TIMEOUT + Watchdog timeout + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STOPPED + Watchdog stopped + 0x104 + read-write + + + EVENTS_STOPPED + Watchdog stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_TIMEOUT + Publish configuration for event TIMEOUT + 0x180 + read-write + + + CHIDX + DPPI channel that event TIMEOUT will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + + + CHIDX + DPPI channel that event STOPPED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + TIMEOUT + Write '1' to enable interrupt for event TIMEOUT + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + TIMEOUT + Write '1' to disable interrupt for event TIMEOUT + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + NMIENSET + Enable interrupt + 0x324 + read-write + + + TIMEOUT + Write '1' to enable interrupt for event TIMEOUT + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + NMIENCLR + Disable interrupt + 0x328 + read-write + + + TIMEOUT + Write '1' to disable interrupt for event TIMEOUT + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + RUNSTATUS + Run status + 0x400 + read-only + + + RUNSTATUSWDT + Indicates whether or not WDT is running + 0 + 0 + + + NotRunning + Watchdog is not running + 0 + + + Running + Watchdog is running + 1 + + + + + + + REQSTATUS + Request status + 0x404 + read-only + 0x00000001 + + + RR0 + Request status for RR[0] register + 0 + 0 + + + DisabledOrRequested + RR[0] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[0] register is enabled, and are not yet requesting reload + 1 + + + + + RR1 + Request status for RR[1] register + 1 + 1 + + + DisabledOrRequested + RR[1] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[1] register is enabled, and are not yet requesting reload + 1 + + + + + RR2 + Request status for RR[2] register + 2 + 2 + + + DisabledOrRequested + RR[2] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[2] register is enabled, and are not yet requesting reload + 1 + + + + + RR3 + Request status for RR[3] register + 3 + 3 + + + DisabledOrRequested + RR[3] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[3] register is enabled, and are not yet requesting reload + 1 + + + + + RR4 + Request status for RR[4] register + 4 + 4 + + + DisabledOrRequested + RR[4] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[4] register is enabled, and are not yet requesting reload + 1 + + + + + RR5 + Request status for RR[5] register + 5 + 5 + + + DisabledOrRequested + RR[5] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[5] register is enabled, and are not yet requesting reload + 1 + + + + + RR6 + Request status for RR[6] register + 6 + 6 + + + DisabledOrRequested + RR[6] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[6] register is enabled, and are not yet requesting reload + 1 + + + + + RR7 + Request status for RR[7] register + 7 + 7 + + + DisabledOrRequested + RR[7] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[7] register is enabled, and are not yet requesting reload + 1 + + + + + + + CRV + Counter reload value + 0x504 + read-write + 0xFFFFFFFF + + + CRV + Counter reload value in number of cycles of the 32.768 kHz clock + 0 + 31 + + + + + RREN + Enable register for reload request registers + 0x508 + read-write + 0x00000001 + + + RR0 + Enable or disable RR[0] register + 0 + 0 + + + Disabled + Disable RR[0] register + 0 + + + Enabled + Enable RR[0] register + 1 + + + + + RR1 + Enable or disable RR[1] register + 1 + 1 + + + Disabled + Disable RR[1] register + 0 + + + Enabled + Enable RR[1] register + 1 + + + + + RR2 + Enable or disable RR[2] register + 2 + 2 + + + Disabled + Disable RR[2] register + 0 + + + Enabled + Enable RR[2] register + 1 + + + + + RR3 + Enable or disable RR[3] register + 3 + 3 + + + Disabled + Disable RR[3] register + 0 + + + Enabled + Enable RR[3] register + 1 + + + + + RR4 + Enable or disable RR[4] register + 4 + 4 + + + Disabled + Disable RR[4] register + 0 + + + Enabled + Enable RR[4] register + 1 + + + + + RR5 + Enable or disable RR[5] register + 5 + 5 + + + Disabled + Disable RR[5] register + 0 + + + Enabled + Enable RR[5] register + 1 + + + + + RR6 + Enable or disable RR[6] register + 6 + 6 + + + Disabled + Disable RR[6] register + 0 + + + Enabled + Enable RR[6] register + 1 + + + + + RR7 + Enable or disable RR[7] register + 7 + 7 + + + Disabled + Disable RR[7] register + 0 + + + Enabled + Enable RR[7] register + 1 + + + + + + + CONFIG + Configuration register + 0x50C + read-write + 0x00000001 + + + SLEEP + Configure WDT to either be paused, or kept running, while the CPU is sleeping + 0 + 0 + + + Pause + Pause WDT while the CPU is sleeping + 0 + + + Run + Keep WDT running while the CPU is sleeping + 1 + + + + + HALT + Configure WDT to either be paused, or kept running, while the CPU is halted by the debugger + 3 + 3 + + + Pause + Pause WDT while the CPU is halted by the debugger + 0 + + + Run + Keep WDT running while the CPU is halted by the debugger + 1 + + + + + STOPEN + Allow stopping WDT + 6 + 6 + + + Disable + Do not allow stopping WDT + 0 + + + Enable + Allow stopping WDT + 1 + + + + + + + TSEN + Task stop enable + 0x520 + write-only + 0x00000000 + + + TSEN + Allow stopping WDT + 0 + 31 + + + Enable + Value to allow stopping WDT + 0x6E524635 + + + + + + + 0x8 + 0x4 + RR[%s] + Description collection: Reload request n + 0x600 + write-only + + + RR + Reload request register + 0 + 31 + + + Reload + Value to request a reload of the watchdog timer + 0x6E524635 + + + + + + + + + TIMER0_NS + Timer/Counter 0 + 0x4100C000 + TIMER + + + + 0 + 0x1000 + registers + + + TIMER0 + 12 + + TIMER + 0x20 + + + TASKS_START + Start Timer + 0x000 + write-only + + + TASKS_START + Start Timer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop Timer + 0x004 + write-only + + + TASKS_STOP + Stop Timer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_COUNT + Increment Timer (Counter mode only) + 0x008 + write-only + + + TASKS_COUNT + Increment Timer (Counter mode only) + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CLEAR + Clear time + 0x00C + write-only + + + TASKS_CLEAR + Clear time + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SHUTDOWN + Deprecated register - Shut down timer + 0x010 + write-only + + + TASKS_SHUTDOWN + Deprecated field - Shut down timer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x8 + 0x4 + TASKS_CAPTURE[%s] + Description collection: Capture Timer value to CC[n] register + 0x040 + write-only + + + TASKS_CAPTURE + Capture Timer value to CC[n] register + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_COUNT + Subscribe configuration for task COUNT + 0x088 + read-write + + + CHIDX + DPPI channel that task COUNT will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_CLEAR + Subscribe configuration for task CLEAR + 0x08C + read-write + + + CHIDX + DPPI channel that task CLEAR will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_SHUTDOWN + Deprecated register - Subscribe configuration for task SHUTDOWN + 0x090 + read-write + + + CHIDX + DPPI channel that task SHUTDOWN will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_CAPTURE[%s] + Description collection: Subscribe configuration for task CAPTURE[n] + 0x0C0 + read-write + + + CHIDX + DPPI channel that task CAPTURE[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + 0x8 + 0x4 + EVENTS_COMPARE[%s] + Description collection: Compare event on CC[n] match + 0x140 + read-write + + + EVENTS_COMPARE + Compare event on CC[n] match + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x8 + 0x4 + PUBLISH_COMPARE[%s] + Description collection: Publish configuration for event COMPARE[n] + 0x1C0 + read-write + + + CHIDX + DPPI channel that event COMPARE[n] will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + COMPARE0_CLEAR + Shortcut between event COMPARE[0] and task CLEAR + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE1_CLEAR + Shortcut between event COMPARE[1] and task CLEAR + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE2_CLEAR + Shortcut between event COMPARE[2] and task CLEAR + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE3_CLEAR + Shortcut between event COMPARE[3] and task CLEAR + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE4_CLEAR + Shortcut between event COMPARE[4] and task CLEAR + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE5_CLEAR + Shortcut between event COMPARE[5] and task CLEAR + 5 + 5 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE6_CLEAR + Shortcut between event COMPARE[6] and task CLEAR + 6 + 6 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE7_CLEAR + Shortcut between event COMPARE[7] and task CLEAR + 7 + 7 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE0_STOP + Shortcut between event COMPARE[0] and task STOP + 16 + 16 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE1_STOP + Shortcut between event COMPARE[1] and task STOP + 17 + 17 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE2_STOP + Shortcut between event COMPARE[2] and task STOP + 18 + 18 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE3_STOP + Shortcut between event COMPARE[3] and task STOP + 19 + 19 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE4_STOP + Shortcut between event COMPARE[4] and task STOP + 20 + 20 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE5_STOP + Shortcut between event COMPARE[5] and task STOP + 21 + 21 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE6_STOP + Shortcut between event COMPARE[6] and task STOP + 22 + 22 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE7_STOP + Shortcut between event COMPARE[7] and task STOP + 23 + 23 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 16 + 16 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 17 + 17 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 21 + 21 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 22 + 22 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 23 + 23 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 22 + 22 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 23 + 23 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 22 + 22 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 23 + 23 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + MODE + Timer mode selection + 0x504 + read-write + + + MODE + Timer mode + 0 + 1 + + + Timer + Select Timer mode + 0 + + + Counter + Deprecated enumerator - Select Counter mode + 1 + + + LowPowerCounter + Select Low Power Counter mode + 2 + + + + + + + BITMODE + Configure the number of bits used by the TIMER + 0x508 + read-write + + + BITMODE + Timer bit width + 0 + 1 + + + 16Bit + 16 bit timer bit width + 0 + + + 08Bit + 8 bit timer bit width + 1 + + + 24Bit + 24 bit timer bit width + 2 + + + 32Bit + 32 bit timer bit width + 3 + + + + + + + PRESCALER + Timer prescaler register + 0x510 + read-write + 0x00000004 + + + PRESCALER + Prescaler value + 0 + 3 + + + + + 0x8 + 0x4 + CC[%s] + Description collection: Capture/Compare register n + 0x540 + read-write + + + CC + Capture/Compare value + 0 + 31 + + + + + 0x8 + 0x4 + ONESHOTEN[%s] + Description collection: Enable one-shot operation for Capture/Compare channel n + 0x580 + read-write + + + ONESHOTEN + Enable one-shot operation + 0 + 0 + + + Disable + Disable one-shot operation + 0 + + + Enable + Enable one-shot operation + 1 + + + + + + + + + ECB_NS + AES ECB Mode Encryption + 0x4100D000 + ECB + + + + 0 + 0x1000 + registers + + + ECB + 13 + + ECB + 0x20 + + + TASKS_STARTECB + Start ECB block encrypt + 0x000 + write-only + + + TASKS_STARTECB + Start ECB block encrypt + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOPECB + Abort a possible executing ECB operation + 0x004 + write-only + + + TASKS_STOPECB + Abort a possible executing ECB operation + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_STARTECB + Subscribe configuration for task STARTECB + 0x080 + read-write + + + CHIDX + DPPI channel that task STARTECB will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOPECB + Subscribe configuration for task STOPECB + 0x084 + read-write + + + CHIDX + DPPI channel that task STOPECB will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_ENDECB + ECB block encrypt complete + 0x100 + read-write + + + EVENTS_ENDECB + ECB block encrypt complete + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERRORECB + ECB block encrypt aborted because of a STOPECB task or due to an error + 0x104 + read-write + + + EVENTS_ERRORECB + ECB block encrypt aborted because of a STOPECB task or due to an error + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_ENDECB + Publish configuration for event ENDECB + 0x180 + read-write + + + CHIDX + DPPI channel that event ENDECB will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ERRORECB + Publish configuration for event ERRORECB + 0x184 + read-write + + + CHIDX + DPPI channel that event ERRORECB will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + ENDECB + Write '1' to enable interrupt for event ENDECB + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERRORECB + Write '1' to enable interrupt for event ERRORECB + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + ENDECB + Write '1' to disable interrupt for event ENDECB + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERRORECB + Write '1' to disable interrupt for event ERRORECB + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ECBDATAPTR + ECB block encrypt memory pointers + 0x504 + read-write + + + ECBDATAPTR + Pointer to the ECB data structure (see Table 1 ECB data structure overview) + 0 + 31 + + + + + + + AAR_NS + Accelerated Address Resolver + 0x4100E000 + AAR + + + + 0 + 0x1000 + registers + + + AAR_CCM + 14 + + AAR + 0x20 + + + TASKS_START + Start resolving addresses based on IRKs specified in the IRK data structure + 0x000 + write-only + + + TASKS_START + Start resolving addresses based on IRKs specified in the IRK data structure + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop resolving addresses + 0x008 + write-only + + + TASKS_STOP + Stop resolving addresses + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x088 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_END + Address resolution procedure complete + 0x100 + read-write + + + EVENTS_END + Address resolution procedure complete + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RESOLVED + Address resolved + 0x104 + read-write + + + EVENTS_RESOLVED + Address resolved + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_NOTRESOLVED + Address not resolved + 0x108 + read-write + + + EVENTS_NOTRESOLVED + Address not resolved + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x180 + read-write + + + CHIDX + DPPI channel that event END will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_RESOLVED + Publish configuration for event RESOLVED + 0x184 + read-write + + + CHIDX + DPPI channel that event RESOLVED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_NOTRESOLVED + Publish configuration for event NOTRESOLVED + 0x188 + read-write + + + CHIDX + DPPI channel that event NOTRESOLVED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + END + Write '1' to enable interrupt for event END + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RESOLVED + Write '1' to enable interrupt for event RESOLVED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + NOTRESOLVED + Write '1' to enable interrupt for event NOTRESOLVED + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + END + Write '1' to disable interrupt for event END + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RESOLVED + Write '1' to disable interrupt for event RESOLVED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + NOTRESOLVED + Write '1' to disable interrupt for event NOTRESOLVED + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + STATUS + Resolution status + 0x400 + read-only + + + STATUS + The IRK that was used last time an address was resolved + 0 + 3 + + + + + ENABLE + Enable AAR + 0x500 + read-write + + + ENABLE + Enable or disable AAR + 0 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 3 + + + + + + + NIRK + Number of IRKs + 0x504 + read-write + 0x00000001 + + + NIRK + Number of Identity Root Keys available in the IRK data structure + 0 + 4 + + + + + IRKPTR + Pointer to IRK data structure + 0x508 + read-write + + + IRKPTR + Pointer to the IRK data structure + 0 + 31 + + + + + ADDRPTR + Pointer to the resolvable address + 0x510 + read-write + + + ADDRPTR + Pointer to the resolvable address (6-bytes) + 0 + 31 + + + + + SCRATCHPTR + Pointer to data area used for temporary storage + 0x514 + read-write + + + SCRATCHPTR + Pointer to a scratch data area used for temporary storage during resolution. A space of minimum 3 bytes must be reserved. + 0 + 31 + + + + + + + CCM_NS + AES CCM mode encryption + 0x4100E000 + AAR_NS + CCM + + + + 0 + 0x1000 + registers + + + AAR_CCM + 14 + + CCM + 0x20 + + + TASKS_KSGEN + Start generation of keystream. This operation will stop by itself when completed. + 0x000 + write-only + + + TASKS_KSGEN + Start generation of keystream. This operation will stop by itself when completed. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CRYPT + Start encryption/decryption. This operation will stop by itself when completed. + 0x004 + write-only + + + TASKS_CRYPT + Start encryption/decryption. This operation will stop by itself when completed. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop encryption/decryption + 0x008 + write-only + + + TASKS_STOP + Stop encryption/decryption + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RATEOVERRIDE + Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption + 0x00C + write-only + + + TASKS_RATEOVERRIDE + Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_KSGEN + Subscribe configuration for task KSGEN + 0x080 + read-write + + + CHIDX + DPPI channel that task KSGEN will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_CRYPT + Subscribe configuration for task CRYPT + 0x084 + read-write + + + CHIDX + DPPI channel that task CRYPT will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x088 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_RATEOVERRIDE + Subscribe configuration for task RATEOVERRIDE + 0x08C + read-write + + + CHIDX + DPPI channel that task RATEOVERRIDE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_ENDKSGEN + Keystream generation complete + 0x100 + read-write + + + EVENTS_ENDKSGEN + Keystream generation complete + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDCRYPT + Encrypt/decrypt complete + 0x104 + read-write + + + EVENTS_ENDCRYPT + Encrypt/decrypt complete + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + Deprecated register - CCM error event + 0x108 + read-write + + + EVENTS_ERROR + Deprecated field - CCM error event + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_ENDKSGEN + Publish configuration for event ENDKSGEN + 0x180 + read-write + + + CHIDX + DPPI channel that event ENDKSGEN will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ENDCRYPT + Publish configuration for event ENDCRYPT + 0x184 + read-write + + + CHIDX + DPPI channel that event ENDCRYPT will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ERROR + Deprecated register - Publish configuration for event ERROR + 0x188 + read-write + + + CHIDX + DPPI channel that event ERROR will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + ENDKSGEN_CRYPT + Shortcut between event ENDKSGEN and task CRYPT + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + ENDKSGEN + Write '1' to enable interrupt for event ENDKSGEN + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDCRYPT + Write '1' to enable interrupt for event ENDCRYPT + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Deprecated intsetfield - Write '1' to enable interrupt for event ERROR + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + ENDKSGEN + Write '1' to disable interrupt for event ENDKSGEN + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDCRYPT + Write '1' to disable interrupt for event ENDCRYPT + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Deprecated intclrfield - Write '1' to disable interrupt for event ERROR + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + MICSTATUS + MIC check result + 0x400 + read-only + + + MICSTATUS + The result of the MIC check performed during the previous decryption operation + 0 + 0 + + + CheckFailed + MIC check failed + 0 + + + CheckPassed + MIC check passed + 1 + + + + + + + ENABLE + Enable + 0x500 + read-write + + + ENABLE + Enable or disable CCM + 0 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 2 + + + + + + + MODE + Operation mode + 0x504 + read-write + 0x00000001 + + + MODE + The mode of operation to be used. Settings in this register apply whenever either the KSGEN task or the CRYPT task is triggered. + 0 + 0 + + + Encryption + AES CCM packet encryption mode + 0 + + + Decryption + AES CCM packet decryption mode + 1 + + + + + DATARATE + Radio data rate that the CCM shall run synchronous with + 16 + 17 + + + 1Mbit + 1 Mbps + 0 + + + 2Mbit + 2 Mbps + 1 + + + 125Kbps + 125 kbps + 2 + + + 500Kbps + 500 kbps + 3 + + + + + LENGTH + Packet length configuration + 24 + 24 + + + Default + Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A keystream for packet payloads up to 27 bytes will be generated. + 0 + + + Extended + Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A keystream for packet payloads up to MAXPACKETSIZE bytes will be generated. + 1 + + + + + + + CNFPTR + Pointer to data structure holding the AES key and the NONCE vector + 0x508 + read-write + + + CNFPTR + Pointer to the data structure holding the AES key and the CCM NONCE vector (see table CCM data structure overview) + 0 + 31 + + + + + INPTR + Input pointer + 0x50C + read-write + + + INPTR + Input pointer + 0 + 31 + + + + + OUTPTR + Output pointer + 0x510 + read-write + + + OUTPTR + Output pointer + 0 + 31 + + + + + SCRATCHPTR + Pointer to data area used for temporary storage + 0x514 + read-write + + + SCRATCHPTR + Pointer to a scratch data area used for temporary storage during keystream generation, + MIC generation and encryption/decryption. + 0 + 31 + + + + + MAXPACKETSIZE + Length of keystream generated when MODE.LENGTH = Extended + 0x518 + read-write + 0x000000FB + + + MAXPACKETSIZE + Length of keystream generated when MODE.LENGTH = Extended. This value must be greater than or equal to the subsequent packet payload to be encrypted/decrypted. + 0 + 7 + + + + + RATEOVERRIDE + Data rate override setting. + 0x51C + read-write + 0x00000000 + + + RATEOVERRIDE + Data rate override setting + 0 + 1 + + + 1Mbit + 1 Mbps + 0 + + + 2Mbit + 2 Mbps + 1 + + + 125Kbps + 125 kbps + 2 + + + 500Kbps + 500 kbps + 3 + + + + + + + HEADERMASK + Header (S0) mask. + 0x520 + read-write + 0x000000E3 + + + HEADERMASK + Header (S0) mask + 0 + 7 + + + + + + + DPPIC_NS + Distributed programmable peripheral interconnect controller + 0x4100F000 + DPPIC + + + + 0 + 0x1000 + registers + + DPPIC + 0x20 + + + 6 + 0x008 + TASKS_CHG[%s] + Channel group tasks + DPPIC_TASKS_CHG + write-only + 0x000 + + EN + Description cluster: Enable channel group n + 0x000 + write-only + + + EN + Enable channel group n + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + DIS + Description cluster: Disable channel group n + 0x004 + write-only + + + DIS + Disable channel group n + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + + 6 + 0x008 + SUBSCRIBE_CHG[%s] + Subscribe configuration for tasks + DPPIC_SUBSCRIBE_CHG + read-write + 0x080 + + EN + Description cluster: Subscribe configuration for task CHG[n].EN + 0x000 + read-write + + + CHIDX + DPPI channel that task CHG[n].EN will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + DIS + Description cluster: Subscribe configuration for task CHG[n].DIS + 0x004 + read-write + + + CHIDX + DPPI channel that task CHG[n].DIS will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + + CHEN + Channel enable register + 0x500 + read-write + + + CH0 + Enable or disable channel 0 + 0 + 0 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH1 + Enable or disable channel 1 + 1 + 1 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH2 + Enable or disable channel 2 + 2 + 2 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH3 + Enable or disable channel 3 + 3 + 3 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH4 + Enable or disable channel 4 + 4 + 4 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH5 + Enable or disable channel 5 + 5 + 5 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH6 + Enable or disable channel 6 + 6 + 6 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH7 + Enable or disable channel 7 + 7 + 7 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH8 + Enable or disable channel 8 + 8 + 8 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH9 + Enable or disable channel 9 + 9 + 9 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH10 + Enable or disable channel 10 + 10 + 10 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH11 + Enable or disable channel 11 + 11 + 11 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH12 + Enable or disable channel 12 + 12 + 12 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH13 + Enable or disable channel 13 + 13 + 13 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH14 + Enable or disable channel 14 + 14 + 14 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH15 + Enable or disable channel 15 + 15 + 15 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH16 + Enable or disable channel 16 + 16 + 16 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH17 + Enable or disable channel 17 + 17 + 17 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH18 + Enable or disable channel 18 + 18 + 18 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH19 + Enable or disable channel 19 + 19 + 19 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH20 + Enable or disable channel 20 + 20 + 20 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH21 + Enable or disable channel 21 + 21 + 21 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH22 + Enable or disable channel 22 + 22 + 22 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH23 + Enable or disable channel 23 + 23 + 23 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH24 + Enable or disable channel 24 + 24 + 24 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH25 + Enable or disable channel 25 + 25 + 25 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH26 + Enable or disable channel 26 + 26 + 26 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH27 + Enable or disable channel 27 + 27 + 27 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH28 + Enable or disable channel 28 + 28 + 28 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH29 + Enable or disable channel 29 + 29 + 29 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH30 + Enable or disable channel 30 + 30 + 30 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH31 + Enable or disable channel 31 + 31 + 31 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + + + CHENSET + Channel enable set register + 0x504 + read-write + oneToSet + + + CH0 + Channel 0 enable set register. Writing 0 has no effect. + 0 + 0 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH1 + Channel 1 enable set register. Writing 0 has no effect. + 1 + 1 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH2 + Channel 2 enable set register. Writing 0 has no effect. + 2 + 2 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH3 + Channel 3 enable set register. Writing 0 has no effect. + 3 + 3 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH4 + Channel 4 enable set register. Writing 0 has no effect. + 4 + 4 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH5 + Channel 5 enable set register. Writing 0 has no effect. + 5 + 5 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH6 + Channel 6 enable set register. Writing 0 has no effect. + 6 + 6 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH7 + Channel 7 enable set register. Writing 0 has no effect. + 7 + 7 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH8 + Channel 8 enable set register. Writing 0 has no effect. + 8 + 8 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH9 + Channel 9 enable set register. Writing 0 has no effect. + 9 + 9 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH10 + Channel 10 enable set register. Writing 0 has no effect. + 10 + 10 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH11 + Channel 11 enable set register. Writing 0 has no effect. + 11 + 11 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH12 + Channel 12 enable set register. Writing 0 has no effect. + 12 + 12 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH13 + Channel 13 enable set register. Writing 0 has no effect. + 13 + 13 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH14 + Channel 14 enable set register. Writing 0 has no effect. + 14 + 14 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH15 + Channel 15 enable set register. Writing 0 has no effect. + 15 + 15 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH16 + Channel 16 enable set register. Writing 0 has no effect. + 16 + 16 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH17 + Channel 17 enable set register. Writing 0 has no effect. + 17 + 17 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH18 + Channel 18 enable set register. Writing 0 has no effect. + 18 + 18 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH19 + Channel 19 enable set register. Writing 0 has no effect. + 19 + 19 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH20 + Channel 20 enable set register. Writing 0 has no effect. + 20 + 20 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH21 + Channel 21 enable set register. Writing 0 has no effect. + 21 + 21 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH22 + Channel 22 enable set register. Writing 0 has no effect. + 22 + 22 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH23 + Channel 23 enable set register. Writing 0 has no effect. + 23 + 23 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH24 + Channel 24 enable set register. Writing 0 has no effect. + 24 + 24 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH25 + Channel 25 enable set register. Writing 0 has no effect. + 25 + 25 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH26 + Channel 26 enable set register. Writing 0 has no effect. + 26 + 26 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH27 + Channel 27 enable set register. Writing 0 has no effect. + 27 + 27 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH28 + Channel 28 enable set register. Writing 0 has no effect. + 28 + 28 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH29 + Channel 29 enable set register. Writing 0 has no effect. + 29 + 29 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH30 + Channel 30 enable set register. Writing 0 has no effect. + 30 + 30 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH31 + Channel 31 enable set register. Writing 0 has no effect. + 31 + 31 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + + + CHENCLR + Channel enable clear register + 0x508 + read-write + oneToClear + + + CH0 + Channel 0 enable clear register. Writing 0 has no effect. + 0 + 0 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH1 + Channel 1 enable clear register. Writing 0 has no effect. + 1 + 1 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH2 + Channel 2 enable clear register. Writing 0 has no effect. + 2 + 2 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH3 + Channel 3 enable clear register. Writing 0 has no effect. + 3 + 3 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH4 + Channel 4 enable clear register. Writing 0 has no effect. + 4 + 4 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH5 + Channel 5 enable clear register. Writing 0 has no effect. + 5 + 5 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH6 + Channel 6 enable clear register. Writing 0 has no effect. + 6 + 6 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH7 + Channel 7 enable clear register. Writing 0 has no effect. + 7 + 7 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH8 + Channel 8 enable clear register. Writing 0 has no effect. + 8 + 8 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH9 + Channel 9 enable clear register. Writing 0 has no effect. + 9 + 9 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH10 + Channel 10 enable clear register. Writing 0 has no effect. + 10 + 10 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH11 + Channel 11 enable clear register. Writing 0 has no effect. + 11 + 11 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH12 + Channel 12 enable clear register. Writing 0 has no effect. + 12 + 12 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH13 + Channel 13 enable clear register. Writing 0 has no effect. + 13 + 13 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH14 + Channel 14 enable clear register. Writing 0 has no effect. + 14 + 14 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH15 + Channel 15 enable clear register. Writing 0 has no effect. + 15 + 15 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH16 + Channel 16 enable clear register. Writing 0 has no effect. + 16 + 16 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH17 + Channel 17 enable clear register. Writing 0 has no effect. + 17 + 17 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH18 + Channel 18 enable clear register. Writing 0 has no effect. + 18 + 18 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH19 + Channel 19 enable clear register. Writing 0 has no effect. + 19 + 19 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH20 + Channel 20 enable clear register. Writing 0 has no effect. + 20 + 20 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH21 + Channel 21 enable clear register. Writing 0 has no effect. + 21 + 21 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH22 + Channel 22 enable clear register. Writing 0 has no effect. + 22 + 22 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH23 + Channel 23 enable clear register. Writing 0 has no effect. + 23 + 23 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH24 + Channel 24 enable clear register. Writing 0 has no effect. + 24 + 24 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH25 + Channel 25 enable clear register. Writing 0 has no effect. + 25 + 25 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH26 + Channel 26 enable clear register. Writing 0 has no effect. + 26 + 26 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH27 + Channel 27 enable clear register. Writing 0 has no effect. + 27 + 27 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH28 + Channel 28 enable clear register. Writing 0 has no effect. + 28 + 28 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH29 + Channel 29 enable clear register. Writing 0 has no effect. + 29 + 29 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH30 + Channel 30 enable clear register. Writing 0 has no effect. + 30 + 30 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH31 + Channel 31 enable clear register. Writing 0 has no effect. + 31 + 31 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + + + 0x6 + 0x4 + CHG[%s] + Description collection: Channel group n Note: Writes to this register are ignored if either SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS is enabled + 0x800 + read-write + + + CH0 + Include or exclude channel 0 + 0 + 0 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH1 + Include or exclude channel 1 + 1 + 1 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH2 + Include or exclude channel 2 + 2 + 2 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH3 + Include or exclude channel 3 + 3 + 3 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH4 + Include or exclude channel 4 + 4 + 4 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH5 + Include or exclude channel 5 + 5 + 5 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH6 + Include or exclude channel 6 + 6 + 6 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH7 + Include or exclude channel 7 + 7 + 7 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH8 + Include or exclude channel 8 + 8 + 8 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH9 + Include or exclude channel 9 + 9 + 9 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH10 + Include or exclude channel 10 + 10 + 10 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH11 + Include or exclude channel 11 + 11 + 11 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH12 + Include or exclude channel 12 + 12 + 12 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH13 + Include or exclude channel 13 + 13 + 13 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH14 + Include or exclude channel 14 + 14 + 14 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH15 + Include or exclude channel 15 + 15 + 15 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH16 + Include or exclude channel 16 + 16 + 16 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH17 + Include or exclude channel 17 + 17 + 17 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH18 + Include or exclude channel 18 + 18 + 18 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH19 + Include or exclude channel 19 + 19 + 19 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH20 + Include or exclude channel 20 + 20 + 20 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH21 + Include or exclude channel 21 + 21 + 21 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH22 + Include or exclude channel 22 + 22 + 22 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH23 + Include or exclude channel 23 + 23 + 23 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH24 + Include or exclude channel 24 + 24 + 24 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH25 + Include or exclude channel 25 + 25 + 25 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH26 + Include or exclude channel 26 + 26 + 26 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH27 + Include or exclude channel 27 + 27 + 27 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH28 + Include or exclude channel 28 + 28 + 28 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH29 + Include or exclude channel 29 + 29 + 29 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH30 + Include or exclude channel 30 + 30 + 30 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH31 + Include or exclude channel 31 + 31 + 31 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + + + + + TEMP_NS + Temperature Sensor + 0x41010000 + TEMP + + + + 0 + 0x1000 + registers + + + TEMP + 16 + + TEMP + 0x20 + + + TASKS_START + Start temperature measurement + 0x000 + write-only + + + TASKS_START + Start temperature measurement + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop temperature measurement + 0x004 + write-only + + + TASKS_STOP + Stop temperature measurement + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_DATARDY + Temperature measurement complete, data ready + 0x100 + read-write + + + EVENTS_DATARDY + Temperature measurement complete, data ready + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_DATARDY + Publish configuration for event DATARDY + 0x180 + read-write + + + CHIDX + DPPI channel that event DATARDY will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + DATARDY + Write '1' to enable interrupt for event DATARDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + DATARDY + Write '1' to disable interrupt for event DATARDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + TEMP + Temperature in degC (0.25deg steps) + 0x508 + read-only + int32_t + + + TEMP + Temperature in degC (0.25deg steps) + 0 + 31 + + + + + A0 + Slope of first piecewise linear function + 0x520 + read-write + 0x000002D9 + + + A0 + Slope of first piecewise linear function + 0 + 11 + + + + + A1 + Slope of second piecewise linear function + 0x524 + read-write + 0x00000322 + + + A1 + Slope of second piecewise linear function + 0 + 11 + + + + + A2 + Slope of third piecewise linear function + 0x528 + read-write + 0x00000355 + + + A2 + Slope of third piecewise linear function + 0 + 11 + + + + + A3 + Slope of fourth piecewise linear function + 0x52C + read-write + 0x000003DF + + + A3 + Slope of fourth piecewise linear function + 0 + 11 + + + + + A4 + Slope of fifth piecewise linear function + 0x530 + read-write + 0x0000044E + + + A4 + Slope of fifth piecewise linear function + 0 + 11 + + + + + A5 + Slope of sixth piecewise linear function + 0x534 + read-write + 0x000004B7 + + + A5 + Slope of sixth piecewise linear function + 0 + 11 + + + + + B0 + y-intercept of first piecewise linear function + 0x540 + read-write + 0x00000FC7 + + + B0 + y-intercept of first piecewise linear function + 0 + 11 + + + + + B1 + y-intercept of second piecewise linear function + 0x544 + read-write + 0x00000F71 + + + B1 + y-intercept of second piecewise linear function + 0 + 11 + + + + + B2 + y-intercept of third piecewise linear function + 0x548 + read-write + 0x00000F6C + + + B2 + y-intercept of third piecewise linear function + 0 + 11 + + + + + B3 + y-intercept of fourth piecewise linear function + 0x54C + read-write + 0x00000FCB + + + B3 + y-intercept of fourth piecewise linear function + 0 + 11 + + + + + B4 + y-intercept of fifth piecewise linear function + 0x550 + read-write + 0x0000004B + + + B4 + y-intercept of fifth piecewise linear function + 0 + 11 + + + + + B5 + y-intercept of sixth piecewise linear function + 0x554 + read-write + 0x000000F6 + + + B5 + y-intercept of sixth piecewise linear function + 0 + 11 + + + + + T0 + Endpoint of first piecewise linear function + 0x560 + read-write + 0x000000E1 + + + T0 + Endpoint of first piecewise linear function + 0 + 7 + + + + + T1 + Endpoint of second piecewise linear function + 0x564 + read-write + 0x000000F9 + + + T1 + Endpoint of second piecewise linear function + 0 + 7 + + + + + T2 + Endpoint of third piecewise linear function + 0x568 + read-write + 0x00000010 + + + T2 + Endpoint of third piecewise linear function + 0 + 7 + + + + + T3 + Endpoint of fourth piecewise linear function + 0x56C + read-write + 0x00000026 + + + T3 + Endpoint of fourth piecewise linear function + 0 + 7 + + + + + T4 + Endpoint of fifth piecewise linear function + 0x570 + read-write + 0x0000003F + + + T4 + Endpoint of fifth piecewise linear function + 0 + 7 + + + + + + + RTC0_NS + Real-time counter 0 + 0x41011000 + RTC + + + + 0 + 0x1000 + registers + + + RTC0 + 17 + + RTC + 0x20 + + + TASKS_START + Start RTC counter + 0x000 + write-only + + + TASKS_START + Start RTC counter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop RTC counter + 0x004 + write-only + + + TASKS_STOP + Stop RTC counter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CLEAR + Clear RTC counter + 0x008 + write-only + + + TASKS_CLEAR + Clear RTC counter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_TRIGOVRFLW + Set counter to 0xFFFFF0 + 0x00C + write-only + + + TASKS_TRIGOVRFLW + Set counter to 0xFFFFF0 + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x4 + 0x4 + TASKS_CAPTURE[%s] + Description collection: Capture RTC counter to CC[n] register + 0x040 + write-only + + + TASKS_CAPTURE + Capture RTC counter to CC[n] register + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_CLEAR + Subscribe configuration for task CLEAR + 0x088 + read-write + + + CHIDX + DPPI channel that task CLEAR will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_TRIGOVRFLW + Subscribe configuration for task TRIGOVRFLW + 0x08C + read-write + + + CHIDX + DPPI channel that task TRIGOVRFLW will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + 0x4 + 0x4 + SUBSCRIBE_CAPTURE[%s] + Description collection: Subscribe configuration for task CAPTURE[n] + 0x0C0 + read-write + + + CHIDX + DPPI channel that task CAPTURE[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_TICK + Event on counter increment + 0x100 + read-write + + + EVENTS_TICK + Event on counter increment + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_OVRFLW + Event on counter overflow + 0x104 + read-write + + + EVENTS_OVRFLW + Event on counter overflow + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x4 + 0x4 + EVENTS_COMPARE[%s] + Description collection: Compare event on CC[n] match + 0x140 + read-write + + + EVENTS_COMPARE + Compare event on CC[n] match + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_TICK + Publish configuration for event TICK + 0x180 + read-write + + + CHIDX + DPPI channel that event TICK will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_OVRFLW + Publish configuration for event OVRFLW + 0x184 + read-write + + + CHIDX + DPPI channel that event OVRFLW will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + 0x4 + 0x4 + PUBLISH_COMPARE[%s] + Description collection: Publish configuration for event COMPARE[n] + 0x1C0 + read-write + + + CHIDX + DPPI channel that event COMPARE[n] will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + COMPARE0_CLEAR + Shortcut between event COMPARE[0] and task CLEAR + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE1_CLEAR + Shortcut between event COMPARE[1] and task CLEAR + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE2_CLEAR + Shortcut between event COMPARE[2] and task CLEAR + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE3_CLEAR + Shortcut between event COMPARE[3] and task CLEAR + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + TICK + Write '1' to enable interrupt for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + OVRFLW + Write '1' to enable interrupt for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + TICK + Write '1' to disable interrupt for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + OVRFLW + Write '1' to disable interrupt for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + EVTEN + Enable or disable event routing + 0x340 + read-write + + + TICK + Enable or disable event routing for event TICK + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + OVRFLW + Enable or disable event routing for event OVRFLW + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COMPARE0 + Enable or disable event routing for event COMPARE[0] + 16 + 16 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COMPARE1 + Enable or disable event routing for event COMPARE[1] + 17 + 17 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COMPARE2 + Enable or disable event routing for event COMPARE[2] + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COMPARE3 + Enable or disable event routing for event COMPARE[3] + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + EVTENSET + Enable event routing + 0x344 + read-write + + + TICK + Write '1' to enable event routing for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + OVRFLW + Write '1' to enable event routing for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE0 + Write '1' to enable event routing for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE1 + Write '1' to enable event routing for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE2 + Write '1' to enable event routing for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE3 + Write '1' to enable event routing for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + EVTENCLR + Disable event routing + 0x348 + read-write + + + TICK + Write '1' to disable event routing for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + OVRFLW + Write '1' to disable event routing for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE0 + Write '1' to disable event routing for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE1 + Write '1' to disable event routing for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE2 + Write '1' to disable event routing for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE3 + Write '1' to disable event routing for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + COUNTER + Current counter value + 0x504 + read-only + + + COUNTER + Counter value + 0 + 23 + + + + + PRESCALER + 12-bit prescaler for counter frequency (32768 / (PRESCALER + 1)). Must be written when RTC is stopped. + 0x508 + read-write + + + PRESCALER + Prescaler value + 0 + 11 + + + + + 0x4 + 0x4 + CC[%s] + Description collection: Compare register n + 0x540 + read-write + + + COMPARE + Compare value + 0 + 23 + + + + + + + IPC_NS + Interprocessor communication + 0x41012000 + IPC + + + + 0 + 0x1000 + registers + + + IPC + 18 + + IPC + 0x20 + + + 0x10 + 0x4 + TASKS_SEND[%s] + Description collection: Trigger events on IPC channel enabled in SEND_CNF[n] + 0x000 + write-only + + + TASKS_SEND + Trigger events on IPC channel enabled in SEND_CNF[n] + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x10 + 0x4 + SUBSCRIBE_SEND[%s] + Description collection: Subscribe configuration for task SEND[n] + 0x080 + read-write + + + CHIDX + DPPI channel that task SEND[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + 0x10 + 0x4 + EVENTS_RECEIVE[%s] + Description collection: Event received on one or more of the enabled IPC channels in RECEIVE_CNF[n] + 0x100 + read-write + + + EVENTS_RECEIVE + Event received on one or more of the enabled IPC channels in RECEIVE_CNF[n] + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x10 + 0x4 + PUBLISH_RECEIVE[%s] + Description collection: Publish configuration for event RECEIVE[n] + 0x180 + read-write + + + CHIDX + DPPI channel that event RECEIVE[n] will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + RECEIVE0 + Enable or disable interrupt for event RECEIVE[0] + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE1 + Enable or disable interrupt for event RECEIVE[1] + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE2 + Enable or disable interrupt for event RECEIVE[2] + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE3 + Enable or disable interrupt for event RECEIVE[3] + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE4 + Enable or disable interrupt for event RECEIVE[4] + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE5 + Enable or disable interrupt for event RECEIVE[5] + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE6 + Enable or disable interrupt for event RECEIVE[6] + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE7 + Enable or disable interrupt for event RECEIVE[7] + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE8 + Enable or disable interrupt for event RECEIVE[8] + 8 + 8 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE9 + Enable or disable interrupt for event RECEIVE[9] + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE10 + Enable or disable interrupt for event RECEIVE[10] + 10 + 10 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE11 + Enable or disable interrupt for event RECEIVE[11] + 11 + 11 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE12 + Enable or disable interrupt for event RECEIVE[12] + 12 + 12 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE13 + Enable or disable interrupt for event RECEIVE[13] + 13 + 13 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE14 + Enable or disable interrupt for event RECEIVE[14] + 14 + 14 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE15 + Enable or disable interrupt for event RECEIVE[15] + 15 + 15 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + RECEIVE0 + Write '1' to enable interrupt for event RECEIVE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE1 + Write '1' to enable interrupt for event RECEIVE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE2 + Write '1' to enable interrupt for event RECEIVE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE3 + Write '1' to enable interrupt for event RECEIVE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE4 + Write '1' to enable interrupt for event RECEIVE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE5 + Write '1' to enable interrupt for event RECEIVE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE6 + Write '1' to enable interrupt for event RECEIVE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE7 + Write '1' to enable interrupt for event RECEIVE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE8 + Write '1' to enable interrupt for event RECEIVE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE9 + Write '1' to enable interrupt for event RECEIVE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE10 + Write '1' to enable interrupt for event RECEIVE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE11 + Write '1' to enable interrupt for event RECEIVE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE12 + Write '1' to enable interrupt for event RECEIVE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE13 + Write '1' to enable interrupt for event RECEIVE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE14 + Write '1' to enable interrupt for event RECEIVE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE15 + Write '1' to enable interrupt for event RECEIVE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + RECEIVE0 + Write '1' to disable interrupt for event RECEIVE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE1 + Write '1' to disable interrupt for event RECEIVE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE2 + Write '1' to disable interrupt for event RECEIVE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE3 + Write '1' to disable interrupt for event RECEIVE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE4 + Write '1' to disable interrupt for event RECEIVE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE5 + Write '1' to disable interrupt for event RECEIVE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE6 + Write '1' to disable interrupt for event RECEIVE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE7 + Write '1' to disable interrupt for event RECEIVE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE8 + Write '1' to disable interrupt for event RECEIVE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE9 + Write '1' to disable interrupt for event RECEIVE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE10 + Write '1' to disable interrupt for event RECEIVE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE11 + Write '1' to disable interrupt for event RECEIVE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE12 + Write '1' to disable interrupt for event RECEIVE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE13 + Write '1' to disable interrupt for event RECEIVE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE14 + Write '1' to disable interrupt for event RECEIVE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE15 + Write '1' to disable interrupt for event RECEIVE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + + + RECEIVE0 + Read pending status of interrupt for event RECEIVE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE1 + Read pending status of interrupt for event RECEIVE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE2 + Read pending status of interrupt for event RECEIVE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE3 + Read pending status of interrupt for event RECEIVE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE4 + Read pending status of interrupt for event RECEIVE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE5 + Read pending status of interrupt for event RECEIVE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE6 + Read pending status of interrupt for event RECEIVE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE7 + Read pending status of interrupt for event RECEIVE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE8 + Read pending status of interrupt for event RECEIVE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE9 + Read pending status of interrupt for event RECEIVE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE10 + Read pending status of interrupt for event RECEIVE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE11 + Read pending status of interrupt for event RECEIVE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE12 + Read pending status of interrupt for event RECEIVE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE13 + Read pending status of interrupt for event RECEIVE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE14 + Read pending status of interrupt for event RECEIVE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE15 + Read pending status of interrupt for event RECEIVE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + + + 0x10 + 0x4 + SEND_CNF[%s] + Description collection: Send event configuration for TASKS_SEND[n] + 0x510 + read-write + 0x00000000 + + + CHEN0 + Enable broadcasting on IPC channel 0 + 0 + 0 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN1 + Enable broadcasting on IPC channel 1 + 1 + 1 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN2 + Enable broadcasting on IPC channel 2 + 2 + 2 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN3 + Enable broadcasting on IPC channel 3 + 3 + 3 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN4 + Enable broadcasting on IPC channel 4 + 4 + 4 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN5 + Enable broadcasting on IPC channel 5 + 5 + 5 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN6 + Enable broadcasting on IPC channel 6 + 6 + 6 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN7 + Enable broadcasting on IPC channel 7 + 7 + 7 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN8 + Enable broadcasting on IPC channel 8 + 8 + 8 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN9 + Enable broadcasting on IPC channel 9 + 9 + 9 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN10 + Enable broadcasting on IPC channel 10 + 10 + 10 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN11 + Enable broadcasting on IPC channel 11 + 11 + 11 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN12 + Enable broadcasting on IPC channel 12 + 12 + 12 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN13 + Enable broadcasting on IPC channel 13 + 13 + 13 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN14 + Enable broadcasting on IPC channel 14 + 14 + 14 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN15 + Enable broadcasting on IPC channel 15 + 15 + 15 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + + + 0x10 + 0x4 + RECEIVE_CNF[%s] + Description collection: Receive event configuration for EVENTS_RECEIVE[n] + 0x590 + read-write + 0x00000000 + + + CHEN0 + Enable subscription to IPC channel 0 + 0 + 0 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN1 + Enable subscription to IPC channel 1 + 1 + 1 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN2 + Enable subscription to IPC channel 2 + 2 + 2 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN3 + Enable subscription to IPC channel 3 + 3 + 3 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN4 + Enable subscription to IPC channel 4 + 4 + 4 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN5 + Enable subscription to IPC channel 5 + 5 + 5 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN6 + Enable subscription to IPC channel 6 + 6 + 6 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN7 + Enable subscription to IPC channel 7 + 7 + 7 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN8 + Enable subscription to IPC channel 8 + 8 + 8 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN9 + Enable subscription to IPC channel 9 + 9 + 9 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN10 + Enable subscription to IPC channel 10 + 10 + 10 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN11 + Enable subscription to IPC channel 11 + 11 + 11 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN12 + Enable subscription to IPC channel 12 + 12 + 12 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN13 + Enable subscription to IPC channel 13 + 13 + 13 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN14 + Enable subscription to IPC channel 14 + 14 + 14 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN15 + Enable subscription to IPC channel 15 + 15 + 15 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + + + 0x2 + 0x4 + GPMEM[%s] + Description collection: General purpose memory + 0x610 + read-write + 0x00000000 + + + GPMEM + General purpose memory + 0 + 31 + + + + + + + SPIM0_NS + Serial Peripheral Interface Master with EasyDMA + 0x41013000 + SPIM + + + + 0 + 0x1000 + registers + + + SERIAL0 + 19 + + SPIM + 0x20 + + + TASKS_START + Start SPI transaction + 0x010 + write-only + + + TASKS_START + Start SPI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop SPI transaction + 0x014 + write-only + + + TASKS_STOP + Stop SPI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SUSPEND + Suspend SPI transaction + 0x01C + write-only + + + TASKS_SUSPEND + Suspend SPI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RESUME + Resume SPI transaction + 0x020 + write-only + + + TASKS_RESUME + Resume SPI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x090 + read-write + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x094 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_SUSPEND + Subscribe configuration for task SUSPEND + 0x09C + read-write + + + CHIDX + DPPI channel that task SUSPEND will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_RESUME + Subscribe configuration for task RESUME + 0x0A0 + read-write + + + CHIDX + DPPI channel that task RESUME will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_STOPPED + SPI transaction has stopped + 0x104 + read-write + + + EVENTS_STOPPED + SPI transaction has stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDRX + End of RXD buffer reached + 0x110 + read-write + + + EVENTS_ENDRX + End of RXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_END + End of RXD buffer and TXD buffer reached + 0x118 + read-write + + + EVENTS_END + End of RXD buffer and TXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDTX + End of TXD buffer reached + 0x120 + read-write + + + EVENTS_ENDTX + End of TXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STARTED + Transaction started + 0x14C + read-write + + + EVENTS_STARTED + Transaction started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + + + CHIDX + DPPI channel that event STOPPED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ENDRX + Publish configuration for event ENDRX + 0x190 + read-write + + + CHIDX + DPPI channel that event ENDRX will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x198 + read-write + + + CHIDX + DPPI channel that event END will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ENDTX + Publish configuration for event ENDTX + 0x1A0 + read-write + + + CHIDX + DPPI channel that event ENDTX will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_STARTED + Publish configuration for event STARTED + 0x1CC + read-write + + + CHIDX + DPPI channel that event STARTED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + END_START + Shortcut between event END and task START + 17 + 17 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDRX + Write '1' to enable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + END + Write '1' to enable interrupt for event END + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDTX + Write '1' to enable interrupt for event ENDTX + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STARTED + Write '1' to enable interrupt for event STARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDRX + Write '1' to disable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + END + Write '1' to disable interrupt for event END + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDTX + Write '1' to disable interrupt for event ENDTX + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STARTED + Write '1' to disable interrupt for event STARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + STALLSTAT + Stall status for EasyDMA RAM accesses. The fields in this register are set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU. + 0x400 + read-write + 0x00000000 + + + TX + Stall status for EasyDMA RAM reads + 0 + 0 + + + NOSTALL + No stall + 0 + + + STALL + A stall has occurred + 1 + + + + + RX + Stall status for EasyDMA RAM writes + 1 + 1 + + + NOSTALL + No stall + 0 + + + STALL + A stall has occurred + 1 + + + + + + + ENABLE + Enable SPIM + 0x500 + read-write + + + ENABLE + Enable or disable SPIM + 0 + 3 + + + Disabled + Disable SPIM + 0 + + + Enabled + Enable SPIM + 7 + + + + + + + PSEL + Unspecified + SPIM_PSEL + read-write + 0x508 + + SCK + Pin select for SCK + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MOSI + Pin select for MOSI signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MISO + Pin select for MISO signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + CSN + Pin select for CSN + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + FREQUENCY + SPI frequency. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + FREQUENCY + SPI master data rate + 0 + 31 + + + K125 + 125 kbps + 0x02000000 + + + K250 + 250 kbps + 0x04000000 + + + K500 + 500 kbps + 0x08000000 + + + M1 + 1 Mbps + 0x10000000 + + + M2 + 2 Mbps + 0x20000000 + + + M4 + 4 Mbps + 0x40000000 + + + M8 + 8 Mbps + 0x80000000 + + + M16 + 16 Mbps + 0x0A000000 + + + M32 + 32 Mbps + 0x14000000 + + + + + + + RXD + RXD EasyDMA channel + SPIM_RXD + read-write + 0x534 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + TXD + TXD EasyDMA channel + SPIM_TXD + read-write + 0x544 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + CONFIG + Configuration register + 0x554 + read-write + + + ORDER + Bit order + 0 + 0 + + + MsbFirst + Most significant bit shifted out first + 0 + + + LsbFirst + Least significant bit shifted out first + 1 + + + + + CPHA + Serial clock (SCK) phase + 1 + 1 + + + Leading + Sample on leading edge of clock, shift serial data on trailing edge + 0 + + + Trailing + Sample on trailing edge of clock, shift serial data on leading edge + 1 + + + + + CPOL + Serial clock (SCK) polarity + 2 + 2 + + + ActiveHigh + Active high + 0 + + + ActiveLow + Active low + 1 + + + + + + + IFTIMING + Unspecified + SPIM_IFTIMING + read-write + 0x560 + + RXDELAY + Sample delay for input serial data on MISO + 0x000 + read-write + 0x00000002 + + + RXDELAY + Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK. + 0 + 2 + + + + + CSNDUR + Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, this is also the minimum duration CSN must stay high between transactions. + 0x004 + read-write + 0x00000002 + + + CSNDUR + Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, this is the minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns). + 0 + 7 + + + + + + CSNPOL + Polarity of CSN output + 0x568 + read-write + 0x00000000 + + + CSNPOL + Polarity of CSN output + 0 + 0 + + + LOW + Active low (idle state high) + 0 + + + HIGH + Active high (idle state low) + 1 + + + + + + + PSELDCX + Pin select for DCX signal + 0x56C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + DCXCNT + DCX configuration + 0x570 + read-write + + + DCXCNT + This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates that all bytes are command bytes. + 0 + 3 + + + + + ORC + Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT + 0x5C0 + read-write + + + ORC + Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT. + 0 + 7 + + + + + + + SPIS0_NS + SPI Slave + 0x41013000 + SPIM0_NS + SPIS + + + + 0 + 0x1000 + registers + + + SERIAL0 + 19 + + SPIS + 0x20 + + + TASKS_ACQUIRE + Acquire SPI semaphore + 0x024 + write-only + + + TASKS_ACQUIRE + Acquire SPI semaphore + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RELEASE + Release SPI semaphore, enabling the SPI slave to acquire it + 0x028 + write-only + + + TASKS_RELEASE + Release SPI semaphore, enabling the SPI slave to acquire it + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_ACQUIRE + Subscribe configuration for task ACQUIRE + 0x0A4 + read-write + + + CHIDX + DPPI channel that task ACQUIRE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_RELEASE + Subscribe configuration for task RELEASE + 0x0A8 + read-write + + + CHIDX + DPPI channel that task RELEASE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_END + Granted transaction completed + 0x104 + read-write + + + EVENTS_END + Granted transaction completed + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDRX + End of RXD buffer reached + 0x110 + read-write + + + EVENTS_ENDRX + End of RXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ACQUIRED + Semaphore acquired + 0x128 + read-write + + + EVENTS_ACQUIRED + Semaphore acquired + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x184 + read-write + + + CHIDX + DPPI channel that event END will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ENDRX + Publish configuration for event ENDRX + 0x190 + read-write + + + CHIDX + DPPI channel that event ENDRX will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ACQUIRED + Publish configuration for event ACQUIRED + 0x1A8 + read-write + + + CHIDX + DPPI channel that event ACQUIRED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + END_ACQUIRE + Shortcut between event END and task ACQUIRE + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + END + Write '1' to enable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDRX + Write '1' to enable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ACQUIRED + Write '1' to enable interrupt for event ACQUIRED + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + END + Write '1' to disable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDRX + Write '1' to disable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ACQUIRED + Write '1' to disable interrupt for event ACQUIRED + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + SEMSTAT + Semaphore status register + 0x400 + read-only + 0x00000001 + + + SEMSTAT + Semaphore status + 0 + 1 + + + Free + Semaphore is free + 0 + + + CPU + Semaphore is assigned to CPU + 1 + + + SPIS + Semaphore is assigned to SPI slave + 2 + + + CPUPending + Semaphore is assigned to SPI but a handover to the CPU is pending + 3 + + + + + + + STATUS + Status from last transaction + 0x440 + read-write + + + OVERREAD + TX buffer over-read detected, and prevented + 0 + 0 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + write + + Clear + Write: clear error on writing '1' + 1 + + + + + OVERFLOW + RX buffer overflow detected, and prevented + 1 + 1 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + write + + Clear + Write: clear error on writing '1' + 1 + + + + + + + ENABLE + Enable SPI slave + 0x500 + read-write + + + ENABLE + Enable or disable SPI slave + 0 + 3 + + + Disabled + Disable SPI slave + 0 + + + Enabled + Enable SPI slave + 2 + + + + + + + PSEL + Unspecified + SPIS_PSEL + read-write + 0x508 + + SCK + Pin select for SCK + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MISO + Pin select for MISO signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MOSI + Pin select for MOSI signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + CSN + Pin select for CSN signal + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + RXD + Unspecified + SPIS_RXD + read-write + 0x534 + + PTR + RXD data pointer + 0x000 + read-write + + + PTR + RXD data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 15 + + + + + AMOUNT + Number of bytes received in last granted transaction + 0x008 + read-only + + + AMOUNT + Number of bytes received in the last granted transaction + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + TXD + Unspecified + SPIS_TXD + read-write + 0x544 + + PTR + TXD data pointer + 0x000 + read-write + + + PTR + TXD data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transmitted in last granted transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transmitted in last granted transaction + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + CONFIG + Configuration register + 0x554 + read-write + + + ORDER + Bit order + 0 + 0 + + + MsbFirst + Most significant bit shifted out first + 0 + + + LsbFirst + Least significant bit shifted out first + 1 + + + + + CPHA + Serial clock (SCK) phase + 1 + 1 + + + Leading + Sample on leading edge of clock, shift serial data on trailing edge + 0 + + + Trailing + Sample on trailing edge of clock, shift serial data on leading edge + 1 + + + + + CPOL + Serial clock (SCK) polarity + 2 + 2 + + + ActiveHigh + Active high + 0 + + + ActiveLow + Active low + 1 + + + + + + + DEF + Default character. Character clocked out in case of an ignored transaction. + 0x55C + read-write + + + DEF + Default character. Character clocked out in case of an ignored transaction. + 0 + 7 + + + + + ORC + Over-read character + 0x5C0 + read-write + + + ORC + Over-read character. Character clocked out after an over-read of the transmit buffer. + 0 + 7 + + + + + + + TWIM0_NS + I2C compatible Two-Wire Master Interface with EasyDMA + 0x41013000 + SPIM0_NS + TWIM + + + + 0 + 0x1000 + registers + + + SERIAL0 + 19 + + TWIM + 0x20 + + + TASKS_STARTRX + Start TWI receive sequence + 0x000 + write-only + + + TASKS_STARTRX + Start TWI receive sequence + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTTX + Start TWI transmit sequence + 0x008 + write-only + + + TASKS_STARTTX + Start TWI transmit sequence + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop TWI transaction. Must be issued while the TWI master is not suspended. + 0x014 + write-only + + + TASKS_STOP + Stop TWI transaction. Must be issued while the TWI master is not suspended. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SUSPEND + Suspend TWI transaction + 0x01C + write-only + + + TASKS_SUSPEND + Suspend TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RESUME + Resume TWI transaction + 0x020 + write-only + + + TASKS_RESUME + Resume TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_STARTRX + Subscribe configuration for task STARTRX + 0x080 + read-write + + + CHIDX + DPPI channel that task STARTRX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STARTTX + Subscribe configuration for task STARTTX + 0x088 + read-write + + + CHIDX + DPPI channel that task STARTTX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x094 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_SUSPEND + Subscribe configuration for task SUSPEND + 0x09C + read-write + + + CHIDX + DPPI channel that task SUSPEND will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_RESUME + Subscribe configuration for task RESUME + 0x0A0 + read-write + + + CHIDX + DPPI channel that task RESUME will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_STOPPED + TWI stopped + 0x104 + read-write + + + EVENTS_STOPPED + TWI stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + TWI error + 0x124 + read-write + + + EVENTS_ERROR + TWI error + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SUSPENDED + SUSPEND task has been issued, TWI traffic is now suspended. + 0x148 + read-write + + + EVENTS_SUSPENDED + SUSPEND task has been issued, TWI traffic is now suspended. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXSTARTED + Receive sequence started + 0x14C + read-write + + + EVENTS_RXSTARTED + Receive sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXSTARTED + Transmit sequence started + 0x150 + read-write + + + EVENTS_TXSTARTED + Transmit sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_LASTRX + Byte boundary, starting to receive the last byte + 0x15C + read-write + + + EVENTS_LASTRX + Byte boundary, starting to receive the last byte + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_LASTTX + Byte boundary, starting to transmit the last byte + 0x160 + read-write + + + EVENTS_LASTTX + Byte boundary, starting to transmit the last byte + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + + + CHIDX + DPPI channel that event STOPPED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ERROR + Publish configuration for event ERROR + 0x1A4 + read-write + + + CHIDX + DPPI channel that event ERROR will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_SUSPENDED + Publish configuration for event SUSPENDED + 0x1C8 + read-write + + + CHIDX + DPPI channel that event SUSPENDED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_RXSTARTED + Publish configuration for event RXSTARTED + 0x1CC + read-write + + + CHIDX + DPPI channel that event RXSTARTED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_TXSTARTED + Publish configuration for event TXSTARTED + 0x1D0 + read-write + + + CHIDX + DPPI channel that event TXSTARTED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_LASTRX + Publish configuration for event LASTRX + 0x1DC + read-write + + + CHIDX + DPPI channel that event LASTRX will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_LASTTX + Publish configuration for event LASTTX + 0x1E0 + read-write + + + CHIDX + DPPI channel that event LASTTX will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + LASTTX_STARTRX + Shortcut between event LASTTX and task STARTRX + 7 + 7 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTTX_SUSPEND + Shortcut between event LASTTX and task SUSPEND + 8 + 8 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTTX_STOP + Shortcut between event LASTTX and task STOP + 9 + 9 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTRX_STARTTX + Shortcut between event LASTRX and task STARTTX + 10 + 10 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTRX_STOP + Shortcut between event LASTRX and task STOP + 12 + 12 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SUSPENDED + Enable or disable interrupt for event SUSPENDED + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXSTARTED + Enable or disable interrupt for event RXSTARTED + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTARTED + Enable or disable interrupt for event TXSTARTED + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + LASTRX + Enable or disable interrupt for event LASTRX + 23 + 23 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + LASTTX + Enable or disable interrupt for event LASTTX + 24 + 24 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SUSPENDED + Write '1' to enable interrupt for event SUSPENDED + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXSTARTED + Write '1' to enable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTARTED + Write '1' to enable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + LASTRX + Write '1' to enable interrupt for event LASTRX + 23 + 23 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + LASTTX + Write '1' to enable interrupt for event LASTTX + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SUSPENDED + Write '1' to disable interrupt for event SUSPENDED + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXSTARTED + Write '1' to disable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXSTARTED + Write '1' to disable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + LASTRX + Write '1' to disable interrupt for event LASTRX + 23 + 23 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + LASTTX + Write '1' to disable interrupt for event LASTTX + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source + 0x4C4 + read-write + oneToClear + + + OVERRUN + Overrun error + 0 + 0 + + + NotReceived + Error did not occur + 0 + + + Received + Error occurred + 1 + + + + + ANACK + NACK received after sending the address (write '1' to clear) + 1 + 1 + + + NotReceived + Error did not occur + 0 + + + Received + Error occurred + 1 + + + + + DNACK + NACK received after sending a data byte (write '1' to clear) + 2 + 2 + + + NotReceived + Error did not occur + 0 + + + Received + Error occurred + 1 + + + + + + + ENABLE + Enable TWIM + 0x500 + read-write + + + ENABLE + Enable or disable TWIM + 0 + 3 + + + Disabled + Disable TWIM + 0 + + + Enabled + Enable TWIM + 6 + + + + + + + PSEL + Unspecified + TWIM_PSEL + read-write + 0x508 + + SCL + Pin select for SCL signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDA + Pin select for SDA signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + FREQUENCY + TWI frequency. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + FREQUENCY + TWI master clock frequency + 0 + 31 + + + K100 + 100 kbps + 0x01980000 + + + K250 + 250 kbps + 0x04000000 + + + K400 + 400 kbps + 0x06400000 + + + K1000 + 1000 kbps + 0x0FF00000 + + + + + + + RXD + RXD EasyDMA channel + TWIM_RXD + read-write + 0x534 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + TXD + TXD EasyDMA channel + TWIM_TXD + read-write + 0x544 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + ADDRESS + Address used in the TWI transfer + 0x588 + read-write + + + ADDRESS + Address used in the TWI transfer + 0 + 6 + + + + + + + TWIS0_NS + I2C compatible Two-Wire Slave Interface with EasyDMA + 0x41013000 + SPIM0_NS + TWIS + + + + 0 + 0x1000 + registers + + + SERIAL0 + 19 + + TWIS + 0x20 + + + TASKS_STOP + Stop TWI transaction + 0x014 + write-only + + + TASKS_STOP + Stop TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SUSPEND + Suspend TWI transaction + 0x01C + write-only + + + TASKS_SUSPEND + Suspend TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RESUME + Resume TWI transaction + 0x020 + write-only + + + TASKS_RESUME + Resume TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_PREPARERX + Prepare the TWI slave to respond to a write command + 0x030 + write-only + + + TASKS_PREPARERX + Prepare the TWI slave to respond to a write command + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_PREPARETX + Prepare the TWI slave to respond to a read command + 0x034 + write-only + + + TASKS_PREPARETX + Prepare the TWI slave to respond to a read command + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x094 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_SUSPEND + Subscribe configuration for task SUSPEND + 0x09C + read-write + + + CHIDX + DPPI channel that task SUSPEND will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_RESUME + Subscribe configuration for task RESUME + 0x0A0 + read-write + + + CHIDX + DPPI channel that task RESUME will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_PREPARERX + Subscribe configuration for task PREPARERX + 0x0B0 + read-write + + + CHIDX + DPPI channel that task PREPARERX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_PREPARETX + Subscribe configuration for task PREPARETX + 0x0B4 + read-write + + + CHIDX + DPPI channel that task PREPARETX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_STOPPED + TWI stopped + 0x104 + read-write + + + EVENTS_STOPPED + TWI stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + TWI error + 0x124 + read-write + + + EVENTS_ERROR + TWI error + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXSTARTED + Receive sequence started + 0x14C + read-write + + + EVENTS_RXSTARTED + Receive sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXSTARTED + Transmit sequence started + 0x150 + read-write + + + EVENTS_TXSTARTED + Transmit sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_WRITE + Write command received + 0x164 + read-write + + + EVENTS_WRITE + Write command received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_READ + Read command received + 0x168 + read-write + + + EVENTS_READ + Read command received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + + + CHIDX + DPPI channel that event STOPPED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ERROR + Publish configuration for event ERROR + 0x1A4 + read-write + + + CHIDX + DPPI channel that event ERROR will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_RXSTARTED + Publish configuration for event RXSTARTED + 0x1CC + read-write + + + CHIDX + DPPI channel that event RXSTARTED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_TXSTARTED + Publish configuration for event TXSTARTED + 0x1D0 + read-write + + + CHIDX + DPPI channel that event TXSTARTED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_WRITE + Publish configuration for event WRITE + 0x1E4 + read-write + + + CHIDX + DPPI channel that event WRITE will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_READ + Publish configuration for event READ + 0x1E8 + read-write + + + CHIDX + DPPI channel that event READ will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + WRITE_SUSPEND + Shortcut between event WRITE and task SUSPEND + 13 + 13 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + READ_SUSPEND + Shortcut between event READ and task SUSPEND + 14 + 14 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXSTARTED + Enable or disable interrupt for event RXSTARTED + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTARTED + Enable or disable interrupt for event TXSTARTED + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + WRITE + Enable or disable interrupt for event WRITE + 25 + 25 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + READ + Enable or disable interrupt for event READ + 26 + 26 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXSTARTED + Write '1' to enable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTARTED + Write '1' to enable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + WRITE + Write '1' to enable interrupt for event WRITE + 25 + 25 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + READ + Write '1' to enable interrupt for event READ + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXSTARTED + Write '1' to disable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXSTARTED + Write '1' to disable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + WRITE + Write '1' to disable interrupt for event WRITE + 25 + 25 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + READ + Write '1' to disable interrupt for event READ + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source + 0x4D0 + read-write + oneToClear + + + OVERFLOW + RX buffer overflow detected, and prevented + 0 + 0 + + + NotDetected + Error did not occur + 0 + + + Detected + Error occurred + 1 + + + + + DNACK + NACK sent after receiving a data byte + 2 + 2 + + + NotReceived + Error did not occur + 0 + + + Received + Error occurred + 1 + + + + + OVERREAD + TX buffer over-read detected, and prevented + 3 + 3 + + + NotDetected + Error did not occur + 0 + + + Detected + Error occurred + 1 + + + + + + + MATCH + Status register indicating which address had a match + 0x4D4 + read-only + + + MATCH + Indication of which address in {ADDRESS} that matched the incoming address + 0 + 0 + + + + + ENABLE + Enable TWIS + 0x500 + read-write + + + ENABLE + Enable or disable TWIS + 0 + 3 + + + Disabled + Disable TWIS + 0 + + + Enabled + Enable TWIS + 9 + + + + + + + PSEL + Unspecified + TWIS_PSEL + read-write + 0x508 + + SCL + Pin select for SCL signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDA + Pin select for SDA signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + RXD + RXD EasyDMA channel + TWIS_RXD + read-write + 0x534 + + PTR + RXD Data pointer + 0x000 + read-write + + + PTR + RXD Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in RXD buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in RXD buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last RXD transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last RXD transaction + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + TXD + TXD EasyDMA channel + TWIS_TXD + read-write + 0x544 + + PTR + TXD Data pointer + 0x000 + read-write + + + PTR + TXD Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in TXD buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in TXD buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last TXD transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last TXD transaction + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + 0x2 + 0x4 + ADDRESS[%s] + Description collection: TWI slave address n + 0x588 + read-write + + + ADDRESS + TWI slave address + 0 + 6 + + + + + CONFIG + Configuration register for the address match mechanism + 0x594 + read-write + 0x00000001 + + + ADDRESS0 + Enable or disable address matching on ADDRESS[0] + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ADDRESS1 + Enable or disable address matching on ADDRESS[1] + 1 + 1 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + + + ORC + Over-read character. Character sent out in case of an over-read of the transmit buffer. + 0x5C0 + read-write + + + ORC + Over-read character. Character sent out in case of an over-read of the transmit buffer. + 0 + 7 + + + + + + + UARTE0_NS + UART with EasyDMA + 0x41013000 + SPIM0_NS + UARTE + + + + 0 + 0x1000 + registers + + + SERIAL0 + 19 + + UARTE + 0x20 + + + TASKS_STARTRX + Start UART receiver + 0x000 + write-only + + + TASKS_STARTRX + Start UART receiver + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOPRX + Stop UART receiver + 0x004 + write-only + + + TASKS_STOPRX + Stop UART receiver + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTTX + Start UART transmitter + 0x008 + write-only + + + TASKS_STARTTX + Start UART transmitter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOPTX + Stop UART transmitter + 0x00C + write-only + + + TASKS_STOPTX + Stop UART transmitter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_FLUSHRX + Flush RX FIFO into RX buffer + 0x02C + write-only + + + TASKS_FLUSHRX + Flush RX FIFO into RX buffer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_STARTRX + Subscribe configuration for task STARTRX + 0x080 + read-write + + + CHIDX + DPPI channel that task STARTRX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOPRX + Subscribe configuration for task STOPRX + 0x084 + read-write + + + CHIDX + DPPI channel that task STOPRX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STARTTX + Subscribe configuration for task STARTTX + 0x088 + read-write + + + CHIDX + DPPI channel that task STARTTX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOPTX + Subscribe configuration for task STOPTX + 0x08C + read-write + + + CHIDX + DPPI channel that task STOPTX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_FLUSHRX + Subscribe configuration for task FLUSHRX + 0x0AC + read-write + + + CHIDX + DPPI channel that task FLUSHRX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0x100 + read-write + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0x104 + read-write + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXDRDY + Data received in RXD (but potentially not yet transferred to Data RAM) + 0x108 + read-write + + + EVENTS_RXDRDY + Data received in RXD (but potentially not yet transferred to Data RAM) + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDRX + Receive buffer is filled up + 0x110 + read-write + + + EVENTS_ENDRX + Receive buffer is filled up + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXDRDY + Data sent from TXD + 0x11C + read-write + + + EVENTS_TXDRDY + Data sent from TXD + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDTX + Last TX byte transmitted + 0x120 + read-write + + + EVENTS_ENDTX + Last TX byte transmitted + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + Error detected + 0x124 + read-write + + + EVENTS_ERROR + Error detected + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXTO + Receiver timeout + 0x144 + read-write + + + EVENTS_RXTO + Receiver timeout + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXSTARTED + UART receiver has started + 0x14C + read-write + + + EVENTS_RXSTARTED + UART receiver has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXSTARTED + UART transmitter has started + 0x150 + read-write + + + EVENTS_TXSTARTED + UART transmitter has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXSTOPPED + Transmitter stopped + 0x158 + read-write + + + EVENTS_TXSTOPPED + Transmitter stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_CTS + Publish configuration for event CTS + 0x180 + read-write + + + CHIDX + DPPI channel that event CTS will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_NCTS + Publish configuration for event NCTS + 0x184 + read-write + + + CHIDX + DPPI channel that event NCTS will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_RXDRDY + Publish configuration for event RXDRDY + 0x188 + read-write + + + CHIDX + DPPI channel that event RXDRDY will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ENDRX + Publish configuration for event ENDRX + 0x190 + read-write + + + CHIDX + DPPI channel that event ENDRX will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_TXDRDY + Publish configuration for event TXDRDY + 0x19C + read-write + + + CHIDX + DPPI channel that event TXDRDY will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ENDTX + Publish configuration for event ENDTX + 0x1A0 + read-write + + + CHIDX + DPPI channel that event ENDTX will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ERROR + Publish configuration for event ERROR + 0x1A4 + read-write + + + CHIDX + DPPI channel that event ERROR will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_RXTO + Publish configuration for event RXTO + 0x1C4 + read-write + + + CHIDX + DPPI channel that event RXTO will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_RXSTARTED + Publish configuration for event RXSTARTED + 0x1CC + read-write + + + CHIDX + DPPI channel that event RXSTARTED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_TXSTARTED + Publish configuration for event TXSTARTED + 0x1D0 + read-write + + + CHIDX + DPPI channel that event TXSTARTED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_TXSTOPPED + Publish configuration for event TXSTOPPED + 0x1D8 + read-write + + + CHIDX + DPPI channel that event TXSTOPPED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + ENDRX_STARTRX + Shortcut between event ENDRX and task STARTRX + 5 + 5 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + ENDRX_STOPRX + Shortcut between event ENDRX and task STOPRX + 6 + 6 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + CTS + Enable or disable interrupt for event CTS + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + NCTS + Enable or disable interrupt for event NCTS + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXDRDY + Enable or disable interrupt for event RXDRDY + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDRX + Enable or disable interrupt for event ENDRX + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXDRDY + Enable or disable interrupt for event TXDRDY + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDTX + Enable or disable interrupt for event ENDTX + 8 + 8 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXTO + Enable or disable interrupt for event RXTO + 17 + 17 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXSTARTED + Enable or disable interrupt for event RXSTARTED + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTARTED + Enable or disable interrupt for event TXSTARTED + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTOPPED + Enable or disable interrupt for event TXSTOPPED + 22 + 22 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + CTS + Write '1' to enable interrupt for event CTS + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + NCTS + Write '1' to enable interrupt for event NCTS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXDRDY + Write '1' to enable interrupt for event RXDRDY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDRX + Write '1' to enable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXDRDY + Write '1' to enable interrupt for event TXDRDY + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDTX + Write '1' to enable interrupt for event ENDTX + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXTO + Write '1' to enable interrupt for event RXTO + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXSTARTED + Write '1' to enable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTARTED + Write '1' to enable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTOPPED + Write '1' to enable interrupt for event TXSTOPPED + 22 + 22 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + CTS + Write '1' to disable interrupt for event CTS + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + NCTS + Write '1' to disable interrupt for event NCTS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXDRDY + Write '1' to disable interrupt for event RXDRDY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDRX + Write '1' to disable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXDRDY + Write '1' to disable interrupt for event TXDRDY + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDTX + Write '1' to disable interrupt for event ENDTX + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXTO + Write '1' to disable interrupt for event RXTO + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXSTARTED + Write '1' to disable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXSTARTED + Write '1' to disable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXSTOPPED + Write '1' to disable interrupt for event TXSTOPPED + 22 + 22 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source + 0x480 + read-write + oneToClear + + + OVERRUN + Overrun error + 0 + 0 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + PARITY + Parity error + 1 + 1 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + FRAMING + Framing error occurred + 2 + 2 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + BREAK + Break condition + 3 + 3 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + + + ENABLE + Enable UART + 0x500 + read-write + + + ENABLE + Enable or disable UARTE + 0 + 3 + + + Disabled + Disable UARTE + 0 + + + Enabled + Enable UARTE + 8 + + + + + + + PSEL + Unspecified + UARTE_PSEL + read-write + 0x508 + + RTS + Pin select for RTS signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + TXD + Pin select for TXD signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + CTS + Pin select for CTS signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + RXD + Pin select for RXD signal + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + BAUDRATE + Baud rate. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + BAUDRATE + Baud rate + 0 + 31 + + + Baud1200 + 1200 baud (actual rate: 1205) + 0x0004F000 + + + Baud2400 + 2400 baud (actual rate: 2396) + 0x0009D000 + + + Baud4800 + 4800 baud (actual rate: 4808) + 0x0013B000 + + + Baud9600 + 9600 baud (actual rate: 9598) + 0x00275000 + + + Baud14400 + 14400 baud (actual rate: 14401) + 0x003AF000 + + + Baud19200 + 19200 baud (actual rate: 19208) + 0x004EA000 + + + Baud28800 + 28800 baud (actual rate: 28777) + 0x0075C000 + + + Baud31250 + 31250 baud + 0x00800000 + + + Baud38400 + 38400 baud (actual rate: 38369) + 0x009D0000 + + + Baud56000 + 56000 baud (actual rate: 55944) + 0x00E50000 + + + Baud57600 + 57600 baud (actual rate: 57554) + 0x00EB0000 + + + Baud76800 + 76800 baud (actual rate: 76923) + 0x013A9000 + + + Baud115200 + 115200 baud (actual rate: 115108) + 0x01D60000 + + + Baud230400 + 230400 baud (actual rate: 231884) + 0x03B00000 + + + Baud250000 + 250000 baud + 0x04000000 + + + Baud460800 + 460800 baud (actual rate: 457143) + 0x07400000 + + + Baud921600 + 921600 baud (actual rate: 941176) + 0x0F000000 + + + Baud1M + 1 megabaud + 0x10000000 + + + + + + + RXD + RXD EasyDMA channel + UARTE_RXD + read-write + 0x534 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 15 + + + + + + TXD + TXD EasyDMA channel + UARTE_TXD + read-write + 0x544 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 15 + + + + + + CONFIG + Configuration of parity and hardware flow control + 0x56C + read-write + + + HWFC + Hardware flow control + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + PARITY + Parity + 1 + 3 + + + Excluded + Exclude parity bit + 0x0 + + + Included + Include even parity bit + 0x7 + + + + + STOP + Stop bits + 4 + 4 + + + One + One stop bit + 0 + + + Two + Two stop bits + 1 + + + + + PARITYTYPE + Even or odd parity type + 8 + 8 + + + Even + Even parity + 0 + + + Odd + Odd parity + 1 + + + + + + + + + EGU0_NS + Event generator unit + 0x41014000 + EGU + + + + 0 + 0x1000 + registers + + + EGU0 + 20 + + EGU + 0x20 + + + 0x10 + 0x4 + TASKS_TRIGGER[%s] + Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event + 0x000 + write-only + + + TASKS_TRIGGER + Trigger n for triggering the corresponding TRIGGERED[n] event + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x10 + 0x4 + SUBSCRIBE_TRIGGER[%s] + Description collection: Subscribe configuration for task TRIGGER[n] + 0x080 + read-write + + + CHIDX + DPPI channel that task TRIGGER[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + 0x10 + 0x4 + EVENTS_TRIGGERED[%s] + Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task + 0x100 + read-write + + + EVENTS_TRIGGERED + Event number n generated by triggering the corresponding TRIGGER[n] task + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x10 + 0x4 + PUBLISH_TRIGGERED[%s] + Description collection: Publish configuration for event TRIGGERED[n] + 0x180 + read-write + + + CHIDX + DPPI channel that event TRIGGERED[n] will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + TRIGGERED0 + Enable or disable interrupt for event TRIGGERED[0] + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED1 + Enable or disable interrupt for event TRIGGERED[1] + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED2 + Enable or disable interrupt for event TRIGGERED[2] + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED3 + Enable or disable interrupt for event TRIGGERED[3] + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED4 + Enable or disable interrupt for event TRIGGERED[4] + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED5 + Enable or disable interrupt for event TRIGGERED[5] + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED6 + Enable or disable interrupt for event TRIGGERED[6] + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED7 + Enable or disable interrupt for event TRIGGERED[7] + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED8 + Enable or disable interrupt for event TRIGGERED[8] + 8 + 8 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED9 + Enable or disable interrupt for event TRIGGERED[9] + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED10 + Enable or disable interrupt for event TRIGGERED[10] + 10 + 10 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED11 + Enable or disable interrupt for event TRIGGERED[11] + 11 + 11 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED12 + Enable or disable interrupt for event TRIGGERED[12] + 12 + 12 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED13 + Enable or disable interrupt for event TRIGGERED[13] + 13 + 13 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED14 + Enable or disable interrupt for event TRIGGERED[14] + 14 + 14 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED15 + Enable or disable interrupt for event TRIGGERED[15] + 15 + 15 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + TRIGGERED0 + Write '1' to enable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED1 + Write '1' to enable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED2 + Write '1' to enable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED3 + Write '1' to enable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED4 + Write '1' to enable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED5 + Write '1' to enable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED6 + Write '1' to enable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED7 + Write '1' to enable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED8 + Write '1' to enable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED9 + Write '1' to enable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED10 + Write '1' to enable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED11 + Write '1' to enable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED12 + Write '1' to enable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED13 + Write '1' to enable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED14 + Write '1' to enable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED15 + Write '1' to enable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + TRIGGERED0 + Write '1' to disable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED1 + Write '1' to disable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED2 + Write '1' to disable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED3 + Write '1' to disable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED4 + Write '1' to disable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED5 + Write '1' to disable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED6 + Write '1' to disable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED7 + Write '1' to disable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED8 + Write '1' to disable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED9 + Write '1' to disable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED10 + Write '1' to disable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED11 + Write '1' to disable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED12 + Write '1' to disable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED13 + Write '1' to disable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED14 + Write '1' to disable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED15 + Write '1' to disable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + + + RTC1_NS + Real-time counter 1 + 0x41016000 + + + + RTC1 + 22 + + + + TIMER1_NS + Timer/Counter 1 + 0x41018000 + + + + TIMER1 + 24 + + + + TIMER2_NS + Timer/Counter 2 + 0x41019000 + + + + TIMER2 + 25 + + + + SWI0_NS + Software interrupt 0 + 0x4101A000 + SWI + + + + 0 + 0x1000 + registers + + + SWI0 + 26 + + SWI + 0x20 + + + UNUSED + Unused. + 0x000 + 0x00000000 + read-only + + + + + SWI1_NS + Software interrupt 1 + 0x4101B000 + + + + SWI1 + 27 + + + + SWI2_NS + Software interrupt 2 + 0x4101C000 + + + + SWI2 + 28 + + + + SWI3_NS + Software interrupt 3 + 0x4101D000 + + + + SWI3 + 29 + + + + APPMUTEX_NS + MUTEX 0 + 0x40030000 + MUTEX + + + + 0 + 0x1000 + registers + + MUTEX + 0x20 + + + 0x10 + 0x4 + MUTEX[%s] + Description collection: Mutex register + 0x400 + read-write + + + MUTEX + Mutex register n + 0 + 0 + + + Unlocked + Mutex n is in unlocked state + 0 + + + Locked + Mutex n is in locked state + 1 + + + + + + + + + APPMUTEX_S + MUTEX 1 + 0x50030000 + + + + + ACL_NS + Access control lists + 0x41080000 + ACL + + + + 0 + 0x1000 + registers + + ACL + 0x20 + + + 8 + 0x010 + ACL[%s] + Unspecified + ACL_ACL + read-write + 0x800 + + ADDR + Description cluster: Start address of region to protect. The start address must be word-aligned. + 0x000 + read-writeOnce + 0x00000000 + + + ADDR + Start address of flash region n. The start address must point to a flash page boundary. + 0 + 31 + + + + + SIZE + Description cluster: Size of region to protect counting from address ACL[n].ADDR. Writing a '0' has no effect. + 0x004 + read-writeOnce + 0x00000000 + + + SIZE + Size of flash region n in bytes. Must be a multiple of the flash page size. + 0 + 31 + + + + + PERM + Description cluster: Access permissions for region n as defined by start address ACL[n].ADDR and size ACL[n].SIZE + 0x008 + read-writeOnce + 0x00000000 + + + WRITE + Configure write and erase permissions for region n. Writing a '0' has no effect. + 1 + 1 + + + Enable + Allow write and erase instructions to region n. + 0 + + + Disable + Block write and erase instructions to region n. + 1 + + + + + READ + Configure read permissions for region n. Writing a '0' has no effect. + 2 + 2 + + + Enable + Allow read instructions to region n. + 0 + + + Disable + Block read instructions to region n. + 1 + + + + + + + + + + NVMC_NS + Non-volatile memory controller + 0x41080000 + ACL_NS + NVMC + + + + 0 + 0x1000 + registers + + NVMC + 0x20 + + + READY + Ready flag + 0x400 + read-only + 0x00000001 + + + READY + NVMC is ready or busy + 0 + 0 + + + Busy + NVMC is busy (ongoing write or erase operation) + 0 + + + Ready + NVMC is ready + 1 + + + + + + + READYNEXT + Ready flag + 0x408 + read-only + 0x00000001 + + + READYNEXT + NVMC can accept a new write operation + 0 + 0 + + + Busy + NVMC cannot accept any write operation + 0 + + + Ready + NVMC is ready + 1 + + + + + + + CONFIG + Configuration register + 0x504 + read-write + + + + WEN + Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. + 0 + 2 + + + Ren + Read only access + 0 + + + Wen + Write enabled + 1 + + + Een + Erase enabled + 2 + + + PEen + Partial erase enabled + 4 + + + + + + + ERASEALL + Register for erasing all non-volatile user memory + 0x50C + write-only + + + + ERASEALL + Erase all non-volatile memory including UICR registers. Before the non-volatile memory can be erased, erasing must be enabled by setting CONFIG.WEN=Een. + 0 + 0 + + + NoOperation + No operation + 0 + + + Erase + Start chip erase + 1 + + + + + + + ERASEPAGEPARTIALCFG + Register for partial erase configuration + 0x51C + read-write + 0x0000000A + + + + DURATION + Duration of the partial erase in milliseconds + 0 + 6 + + + + + ICACHECNF + I-code cache configuration register + 0x540 + read-write + 0x00000000 + + + + CACHEEN + Cache enable + 0 + 0 + + + Disabled + Disable cache. Invalidates all cache entries. + 0 + + + Enabled + Enable cache + 1 + + + + + CACHEPROFEN + Cache profiling enable + 8 + 8 + + + Disabled + Disable cache profiling + 0 + + + Enabled + Enable cache profiling + 1 + + + + + + + IHIT + I-code cache hit counter + 0x548 + read-write + + + + HITS + Number of cache hits Write zero to clear + 0 + 31 + + + + + IMISS + I-code cache miss counter + 0x54C + read-write + + + + MISSES + Number of cache misses Write zero to clear + 0 + 31 + + + + + + + VMC_NS + Volatile Memory controller + 0x41081000 + VMC + + + + 0 + 0x1000 + registers + + VMC + 0x20 + + + 4 + 0x010 + RAM[%s] + Unspecified + VMC_RAM + read-write + 0x600 + + POWER + Description cluster: RAM[n] power control register + 0x000 + read-write + 0x0000FFFF + + + S0POWER + Keep RAM section S0 of RAM[n] on or off in System ON mode + 0 + 0 + + + Off + Off + 0 + + + On + On + 1 + + + + + S1POWER + Keep RAM section S1 of RAM[n] on or off in System ON mode + 1 + 1 + + + Off + Off + 0 + + + On + On + 1 + + + + + S2POWER + Keep RAM section S2 of RAM[n] on or off in System ON mode + 2 + 2 + + + Off + Off + 0 + + + On + On + 1 + + + + + S3POWER + Keep RAM section S3 of RAM[n] on or off in System ON mode + 3 + 3 + + + Off + Off + 0 + + + On + On + 1 + + + + + S0RETENTION + Keep retention on RAM section S0 of RAM[n] when RAM section is switched off + 16 + 16 + + + Off + Off + 0 + + + On + On + 1 + + + + + S1RETENTION + Keep retention on RAM section S1 of RAM[n] when RAM section is switched off + 17 + 17 + + + Off + Off + 0 + + + On + On + 1 + + + + + S2RETENTION + Keep retention on RAM section S2 of RAM[n] when RAM section is switched off + 18 + 18 + + + Off + Off + 0 + + + On + On + 1 + + + + + S3RETENTION + Keep retention on RAM section S3 of RAM[n] when RAM section is switched off + 19 + 19 + + + Off + Off + 0 + + + On + On + 1 + + + + + + + POWERSET + Description cluster: RAM[n] power control set register + 0x004 + read-write + 0x0000FFFF + + + S0POWER + Keep RAM section S0 of RAM[n] on or off in System ON mode + 0 + 0 + + + On + On + 1 + + + + + S1POWER + Keep RAM section S1 of RAM[n] on or off in System ON mode + 1 + 1 + + + On + On + 1 + + + + + S2POWER + Keep RAM section S2 of RAM[n] on or off in System ON mode + 2 + 2 + + + On + On + 1 + + + + + S3POWER + Keep RAM section S3 of RAM[n] on or off in System ON mode + 3 + 3 + + + On + On + 1 + + + + + S0RETENTION + Keep retention on RAM section S0 of RAM[n] when RAM section is switched off + 16 + 16 + + + On + On + 1 + + + + + S1RETENTION + Keep retention on RAM section S1 of RAM[n] when RAM section is switched off + 17 + 17 + + + On + On + 1 + + + + + S2RETENTION + Keep retention on RAM section S2 of RAM[n] when RAM section is switched off + 18 + 18 + + + On + On + 1 + + + + + S3RETENTION + Keep retention on RAM section S3 of RAM[n] when RAM section is switched off + 19 + 19 + + + On + On + 1 + + + + + + + POWERCLR + Description cluster: RAM[n] power control clear register + 0x008 + read-write + 0x0000FFFF + + + S0POWER + Keep RAM section S0 of RAM[n] on or off in System ON mode + 0 + 0 + + + Off + Off + 1 + + + + + S1POWER + Keep RAM section S1 of RAM[n] on or off in System ON mode + 1 + 1 + + + Off + Off + 1 + + + + + S2POWER + Keep RAM section S2 of RAM[n] on or off in System ON mode + 2 + 2 + + + Off + Off + 1 + + + + + S3POWER + Keep RAM section S3 of RAM[n] on or off in System ON mode + 3 + 3 + + + Off + Off + 1 + + + + + S0RETENTION + Keep retention on RAM section S0 of RAM[n] when RAM section is switched off + 16 + 16 + + + Off + Off + 1 + + + + + S1RETENTION + Keep retention on RAM section S1 of RAM[n] when RAM section is switched off + 17 + 17 + + + Off + Off + 1 + + + + + S2RETENTION + Keep retention on RAM section S2 of RAM[n] when RAM section is switched off + 18 + 18 + + + Off + Off + 1 + + + + + S3RETENTION + Keep retention on RAM section S3 of RAM[n] when RAM section is switched off + 19 + 19 + + + Off + Off + 1 + + + + + + + + + + P0_NS + GPIO Port 0 + 0x418C0500 + GPIO + + + + 0 + 0x300 + registers + + GPIO + 0x20 + + + OUT + Write GPIO port + 0x004 + read-write + + + PIN0 + Pin 0 + 0 + 0 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + + + OUTSET + Set individual bits in GPIO port + 0x008 + read-write + oneToSet + + + PIN0 + Pin 0 + 0 + 0 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + + + OUTCLR + Clear individual bits in GPIO port + 0x00C + read-write + oneToClear + + + PIN0 + Pin 0 + 0 + 0 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + + + IN + Read GPIO port + 0x010 + read-only + + + PIN0 + Pin 0 + 0 + 0 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + + + DIR + Direction of GPIO pins + 0x014 + read-write + + + PIN0 + Pin 0 + 0 + 0 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + + + DIRSET + DIR set register + 0x018 + read-write + oneToSet + + + PIN0 + Set as output pin 0 + 0 + 0 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN1 + Set as output pin 1 + 1 + 1 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN2 + Set as output pin 2 + 2 + 2 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN3 + Set as output pin 3 + 3 + 3 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN4 + Set as output pin 4 + 4 + 4 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN5 + Set as output pin 5 + 5 + 5 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN6 + Set as output pin 6 + 6 + 6 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN7 + Set as output pin 7 + 7 + 7 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN8 + Set as output pin 8 + 8 + 8 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN9 + Set as output pin 9 + 9 + 9 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN10 + Set as output pin 10 + 10 + 10 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN11 + Set as output pin 11 + 11 + 11 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN12 + Set as output pin 12 + 12 + 12 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN13 + Set as output pin 13 + 13 + 13 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN14 + Set as output pin 14 + 14 + 14 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN15 + Set as output pin 15 + 15 + 15 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN16 + Set as output pin 16 + 16 + 16 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN17 + Set as output pin 17 + 17 + 17 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN18 + Set as output pin 18 + 18 + 18 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN19 + Set as output pin 19 + 19 + 19 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN20 + Set as output pin 20 + 20 + 20 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN21 + Set as output pin 21 + 21 + 21 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN22 + Set as output pin 22 + 22 + 22 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN23 + Set as output pin 23 + 23 + 23 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN24 + Set as output pin 24 + 24 + 24 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN25 + Set as output pin 25 + 25 + 25 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN26 + Set as output pin 26 + 26 + 26 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN27 + Set as output pin 27 + 27 + 27 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN28 + Set as output pin 28 + 28 + 28 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN29 + Set as output pin 29 + 29 + 29 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN30 + Set as output pin 30 + 30 + 30 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN31 + Set as output pin 31 + 31 + 31 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + + + DIRCLR + DIR clear register + 0x01C + read-write + oneToClear + + + PIN0 + Set as input pin 0 + 0 + 0 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN1 + Set as input pin 1 + 1 + 1 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN2 + Set as input pin 2 + 2 + 2 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN3 + Set as input pin 3 + 3 + 3 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN4 + Set as input pin 4 + 4 + 4 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN5 + Set as input pin 5 + 5 + 5 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN6 + Set as input pin 6 + 6 + 6 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN7 + Set as input pin 7 + 7 + 7 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN8 + Set as input pin 8 + 8 + 8 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN9 + Set as input pin 9 + 9 + 9 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN10 + Set as input pin 10 + 10 + 10 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN11 + Set as input pin 11 + 11 + 11 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN12 + Set as input pin 12 + 12 + 12 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN13 + Set as input pin 13 + 13 + 13 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN14 + Set as input pin 14 + 14 + 14 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN15 + Set as input pin 15 + 15 + 15 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN16 + Set as input pin 16 + 16 + 16 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN17 + Set as input pin 17 + 17 + 17 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN18 + Set as input pin 18 + 18 + 18 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN19 + Set as input pin 19 + 19 + 19 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN20 + Set as input pin 20 + 20 + 20 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN21 + Set as input pin 21 + 21 + 21 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN22 + Set as input pin 22 + 22 + 22 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN23 + Set as input pin 23 + 23 + 23 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN24 + Set as input pin 24 + 24 + 24 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN25 + Set as input pin 25 + 25 + 25 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN26 + Set as input pin 26 + 26 + 26 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN27 + Set as input pin 27 + 27 + 27 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN28 + Set as input pin 28 + 28 + 28 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN29 + Set as input pin 29 + 29 + 29 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN30 + Set as input pin 30 + 30 + 30 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN31 + Set as input pin 31 + 31 + 31 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + + + LATCH + Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers + 0x020 + read-write + + + PIN0 + Status on whether PIN[0] has met criteria set in PIN_CNF[0].SENSE register. Write '1' to clear. + 0 + 0 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN1 + Status on whether PIN[1] has met criteria set in PIN_CNF[1].SENSE register. Write '1' to clear. + 1 + 1 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN2 + Status on whether PIN[2] has met criteria set in PIN_CNF[2].SENSE register. Write '1' to clear. + 2 + 2 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN3 + Status on whether PIN[3] has met criteria set in PIN_CNF[3].SENSE register. Write '1' to clear. + 3 + 3 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN4 + Status on whether PIN[4] has met criteria set in PIN_CNF[4].SENSE register. Write '1' to clear. + 4 + 4 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN5 + Status on whether PIN[5] has met criteria set in PIN_CNF[5].SENSE register. Write '1' to clear. + 5 + 5 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN6 + Status on whether PIN[6] has met criteria set in PIN_CNF[6].SENSE register. Write '1' to clear. + 6 + 6 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN7 + Status on whether PIN[7] has met criteria set in PIN_CNF[7].SENSE register. Write '1' to clear. + 7 + 7 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN8 + Status on whether PIN[8] has met criteria set in PIN_CNF[8].SENSE register. Write '1' to clear. + 8 + 8 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN9 + Status on whether PIN[9] has met criteria set in PIN_CNF[9].SENSE register. Write '1' to clear. + 9 + 9 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN10 + Status on whether PIN[10] has met criteria set in PIN_CNF[10].SENSE register. Write '1' to clear. + 10 + 10 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN11 + Status on whether PIN[11] has met criteria set in PIN_CNF[11].SENSE register. Write '1' to clear. + 11 + 11 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN12 + Status on whether PIN[12] has met criteria set in PIN_CNF[12].SENSE register. Write '1' to clear. + 12 + 12 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN13 + Status on whether PIN[13] has met criteria set in PIN_CNF[13].SENSE register. Write '1' to clear. + 13 + 13 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN14 + Status on whether PIN[14] has met criteria set in PIN_CNF[14].SENSE register. Write '1' to clear. + 14 + 14 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN15 + Status on whether PIN[15] has met criteria set in PIN_CNF[15].SENSE register. Write '1' to clear. + 15 + 15 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN16 + Status on whether PIN[16] has met criteria set in PIN_CNF[16].SENSE register. Write '1' to clear. + 16 + 16 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN17 + Status on whether PIN[17] has met criteria set in PIN_CNF[17].SENSE register. Write '1' to clear. + 17 + 17 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN18 + Status on whether PIN[18] has met criteria set in PIN_CNF[18].SENSE register. Write '1' to clear. + 18 + 18 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN19 + Status on whether PIN[19] has met criteria set in PIN_CNF[19].SENSE register. Write '1' to clear. + 19 + 19 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN20 + Status on whether PIN[20] has met criteria set in PIN_CNF[20].SENSE register. Write '1' to clear. + 20 + 20 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN21 + Status on whether PIN[21] has met criteria set in PIN_CNF[21].SENSE register. Write '1' to clear. + 21 + 21 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN22 + Status on whether PIN[22] has met criteria set in PIN_CNF[22].SENSE register. Write '1' to clear. + 22 + 22 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN23 + Status on whether PIN[23] has met criteria set in PIN_CNF[23].SENSE register. Write '1' to clear. + 23 + 23 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN24 + Status on whether PIN[24] has met criteria set in PIN_CNF[24].SENSE register. Write '1' to clear. + 24 + 24 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN25 + Status on whether PIN[25] has met criteria set in PIN_CNF[25].SENSE register. Write '1' to clear. + 25 + 25 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN26 + Status on whether PIN[26] has met criteria set in PIN_CNF[26].SENSE register. Write '1' to clear. + 26 + 26 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN27 + Status on whether PIN[27] has met criteria set in PIN_CNF[27].SENSE register. Write '1' to clear. + 27 + 27 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN28 + Status on whether PIN[28] has met criteria set in PIN_CNF[28].SENSE register. Write '1' to clear. + 28 + 28 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN29 + Status on whether PIN[29] has met criteria set in PIN_CNF[29].SENSE register. Write '1' to clear. + 29 + 29 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN30 + Status on whether PIN[30] has met criteria set in PIN_CNF[30].SENSE register. Write '1' to clear. + 30 + 30 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN31 + Status on whether PIN[31] has met criteria set in PIN_CNF[31].SENSE register. Write '1' to clear. + 31 + 31 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + + + DETECTMODE + Select between default DETECT signal behavior and LDETECT mode (For non-secure pin only) + 0x024 + read-write + + + DETECTMODE + Select between default DETECT signal behavior and LDETECT mode + 0 + 0 + + + Default + DETECT directly connected to PIN DETECT signals + 0 + + + LDETECT + Use the latched LDETECT behavior + 1 + + + + + + + DETECTMODE_SEC + Select between default DETECT signal behavior and LDETECT mode (For secure pin only) + 0x028 + read-write + + + DETECTMODE + Select between default DETECT signal behavior and LDETECT mode + 0 + 0 + + + Default + DETECT directly connected to PIN DETECT signals + 0 + + + LDETECT + Use the latched LDETECT behavior + 1 + + + + + + + 0x20 + 0x4 + PIN_CNF[%s] + Description collection: Configuration of GPIO pins + 0x200 + read-write + 0x00000002 + + + DIR + Pin direction. Same physical register as DIR register + 0 + 0 + + + Input + Configure pin as an input pin + 0 + + + Output + Configure pin as an output pin + 1 + + + + + INPUT + Connect or disconnect input buffer + 1 + 1 + + + Connect + Connect input buffer + 0 + + + Disconnect + Disconnect input buffer + 1 + + + + + PULL + Pull configuration + 2 + 3 + + + Disabled + No pull + 0 + + + Pulldown + Pull down on pin + 1 + + + Pullup + Pull up on pin + 3 + + + + + DRIVE + Drive configuration + 8 + 11 + + + S0S1 + Standard '0', standard '1' + 0 + + + H0S1 + High drive '0', standard '1' + 1 + + + S0H1 + Standard '0', high drive '1' + 2 + + + H0H1 + High drive '0', high 'drive '1'' + 3 + + + D0S1 + Disconnect '0', standard '1' (normally used for wired-or connections) + 4 + + + D0H1 + Disconnect '0', high drive '1' (normally used for wired-or connections) + 5 + + + S0D1 + Standard '0', disconnect '1' (normally used for wired-and connections) + 6 + + + H0D1 + High drive '0', disconnect '1' (normally used for wired-and connections) + 7 + + + E0E1 + Extra high drive '0', extra high drive '1' + 11 + + + + + SENSE + Pin sensing mechanism + 16 + 17 + + + Disabled + Disabled + 0 + + + High + Sense for high level + 2 + + + Low + Sense for low level + 3 + + + + + MCUSEL + Select which MCU/Subsystem controls this pin Note: this field is only accessible from secure code. + 28 + 30 + + + AppMCU + Application MCU + 0x0 + + + NetworkMCU + Network MCU + 0x1 + + + Peripheral + Peripheral with dedicated pins + 0x3 + + + TND + Trace and Debug Subsystem + 0x7 + + + + + + + + + P1_NS + GPIO Port 1 + 0x418C0800 + + + + + diff --git a/svd/nrf9160.svd b/svd/nrf9160.svd index d834f9c..a0fd98a 100644 --- a/svd/nrf9160.svd +++ b/svd/nrf9160.svd @@ -6,43 +6,44 @@ nrf9160 nrf91 1 - nrf9160 reference description for radio MCU with ARM 32-bit Cortex-M33 Microcontroller + nrf9160 reference description for radio MCU with ARM 32-bit Cortex-M33 Microcontroller -Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.\n -\n -SPDX-License-Identifier: BSD-3-Clause\n -\n -Redistribution and use in source and binary forms, with or without\n -modification, are permitted provided that the following conditions are met:\n -\n -1. Redistributions of source code must retain the above copyright notice, this\n - list of conditions and the following disclaimer.\n -\n -2. Redistributions in binary form must reproduce the above copyright\n - notice, this list of conditions and the following disclaimer in the\n - documentation and/or other materials provided with the distribution.\n -\n -3. Neither the name of Nordic Semiconductor ASA nor the names of its\n - contributors may be used to endorse or promote products derived from this\n - software without specific prior written permission.\n -\n -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\n -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n -IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE\n -ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\n -LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n -SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n -INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n -CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n -POSSIBILITY OF SUCH DAMAGE.\n - +Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + 8 32 32 0x00000000 0xFFFFFFFF + NRF_ CM33 r0p4 @@ -54,8 +55,7 @@ POSSIBILITY OF SUCH DAMAGE.\n 69 0 - system_nrf9160 - NRF_ + system_nrf91 240 @@ -75,6 +75,70 @@ POSSIBILITY OF SUCH DAMAGE.\n FICR 0x20 + + SIPINFO + SIP-specific device info + FICR_SIPINFO + read-write + 0x140 + + PARTNO + SIP part number + 0x000 + read-only + 0xFFFFFFFF + + + PARTNO + 0 + 31 + + + 9160 + Device is an nRF9160 sip + 0x00009160 + + + + + + + 0x4 + 0x1 + HWREVISION[%s] + Description collection: SIP hardware revision, encoded in ASCII, ex B0A or B1A + 0x004 + read-only + 0x000000FF + uint8_t + 0x8 + + + HWREVISION + 0 + 7 + + + + + 0x4 + 0x1 + VARIANT[%s] + Description collection: SIP VARIANT, encoded in ASCII, ex SIAA, SIBA or SICA + 0x008 + read-only + 0x000000FF + uint8_t + 0x8 + + + VARIANT + 0 + 7 + + + + INFO Device info @@ -103,7 +167,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Part code 0x00C read-only - 0x00009160 + 0xFFFFFFFF PART @@ -116,6 +180,11 @@ POSSIBILITY OF SUCH DAMAGE.\n nRF9160 0x9160 + + N9120 + nRF9120 + 0x9120 + @@ -143,6 +212,16 @@ POSSIBILITY OF SUCH DAMAGE.\n AAA0 0x41414130 + + AAB0 + AAB0 + 0x41414230 + + + AAC0 + AAC0 + 0x41414330 + @@ -161,9 +240,9 @@ POSSIBILITY OF SUCH DAMAGE.\n 31 - CC - CCxx - 236 ball wlCSP - 0x2000 + CF + CFxx - 236 ball wlCSP + 0x2002 @@ -230,6 +309,13 @@ POSSIBILITY OF SUCH DAMAGE.\n Code memory page size 0 31 + + + K4096 + 4 kByte + 0x1000 + + @@ -242,9 +328,16 @@ POSSIBILITY OF SUCH DAMAGE.\n CODESIZE - Code memory size in number of pages + Code memory size in number of pages Total code space is: CODEPAGESIZE * CODESIZE 0 31 + + + P256 + 256 pages + 256 + + @@ -371,7 +464,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Amount of bytes for the startup tests 0x00C read-only - 0x00000210 + 0xFFFFFFFF STARTUP @@ -556,6 +649,33 @@ POSSIBILITY OF SUCH DAMAGE.\n + + APPNVMCPOFGUARD + Enable blocking NVM WRITE and aborting NVM ERASE for Application NVM in POFWARN condition . + 0x024 + read-write + 0xFFFFFFFF + + + NVMCPOFGUARDEN + Enable blocking NVM WRITE and aborting NVM ERASE in POFWARN condition + 0 + 0 + + + Disabled + NVM WRITE and NVM ERASE are not blocked in POFWARN condition + 0 + + + Enabled + NVM WRITE and NVM ERASE are blocked in POFWARN condition + 1 + + + + + SECUREAPPROTECT Secure access port protection @@ -653,9 +773,9 @@ POSSIBILITY OF SUCH DAMAGE.\n DEST Description cluster: Destination address where content of the key value registers (KEYSLOT.KEYn.VALUE[0-3]) - will be pushed by KMU. Note that this address MUST match that of a peripherals + will be pushed by KMU. Note that this address must match that of a peripherals APB mapped write-only key registers, else the KMU can push this key value into - an address range which the CPU can potentially read! + an address range which the CPU can potentially read. 0x000 read-write 0xFFFFFFFF @@ -795,19 +915,20 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x20 - CLOCKSTART + TASKS_CLOCKSTART Start all trace and debug clocks. 0x000 write-only - START + TASKS_CLOCKSTART + Start all trace and debug clocks. 0 0 - Start - Start all trace and debug clocks. + Trigger + Trigger task 1 @@ -815,19 +936,20 @@ POSSIBILITY OF SUCH DAMAGE.\n - CLOCKSTOP + TASKS_CLOCKSTOP Stop all trace and debug clocks. 0x004 write-only - STOP + TASKS_CLOCKSTOP + Stop all trace and debug clocks. 0 0 - Stop - Stop all trace and debug clocks. + Trigger + Trigger task 1 @@ -867,7 +989,7 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x504 TRACECLK - Pin number configuration for TRACECLK + Pin configuration for TRACECLK 0x000 read-write 0xFFFFFFFF @@ -877,6 +999,13 @@ POSSIBILITY OF SUCH DAMAGE.\n Pin number 0 4 + + + Traceclk + TRACECLK pin + 21 + + CONNECT @@ -900,7 +1029,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TRACEDATA0 - Pin number configuration for TRACEDATA[0] + Pin configuration for TRACEDATA[0] 0x004 read-write 0xFFFFFFFF @@ -910,6 +1039,13 @@ POSSIBILITY OF SUCH DAMAGE.\n Pin number 0 4 + + + Tracedata0 + TRACEDATA0 pin + 22 + + CONNECT @@ -933,7 +1069,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TRACEDATA1 - Pin number configuration for TRACEDATA[1] + Pin configuration for TRACEDATA[1] 0x008 read-write 0xFFFFFFFF @@ -943,6 +1079,13 @@ POSSIBILITY OF SUCH DAMAGE.\n Pin number 0 4 + + + Tracedata1 + TRACEDATA1 pin + 23 + + CONNECT @@ -966,7 +1109,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TRACEDATA2 - Pin number configuration for TRACEDATA[2] + Pin configuration for TRACEDATA[2] 0x00C read-write 0xFFFFFFFF @@ -976,6 +1119,13 @@ POSSIBILITY OF SUCH DAMAGE.\n Pin number 0 4 + + + Tracedata2 + TRACEDATA2 pin + 24 + + CONNECT @@ -999,7 +1149,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TRACEDATA3 - Pin number configuration for TRACEDATA[3] + Pin configuration for TRACEDATA[3] 0x010 read-write 0xFFFFFFFF @@ -1009,6 +1159,13 @@ POSSIBILITY OF SUCH DAMAGE.\n Pin number 0 4 + + + Tracedata3 + TRACEDATA3 pin + 25 + + CONNECT @@ -1033,35 +1190,35 @@ POSSIBILITY OF SUCH DAMAGE.\n TRACEPORTSPEED - Clocking options for the Trace Port debug interface + Clocking options for the Trace Port debug interface Reset behavior is the same as debug components 0x518 read-write 0x00000000 TRACEPORTSPEED - Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two. + Speed of Trace Port clock. Note that the TRACECLK pin output will be divided again by two from the Trace Port clock. 0 1 32MHz - 32 MHz Trace Port clock (TRACECLK = 16 MHz) + Trace Port clock is: 32MHz 0 16MHz - 16 MHz Trace Port clock (TRACECLK = 8 MHz) + Trace Port clock is: 16MHz 1 8MHz - 8 MHz Trace Port clock (TRACECLK = 4 MHz) + Trace Port clock is: 8MHz 2 4MHz - 4 MHz Trace Port clock (TRACECLK = 2 MHz) + Trace Port clock is: 4MHz 3 @@ -1175,9 +1332,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event RAMACCERR will publish to. + DPPI channel that event RAMACCERR will publish to 0 - 3 + 7 EN @@ -1206,9 +1363,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event FLASHACCERR will publish to. + DPPI channel that event FLASHACCERR will publish to 0 - 3 + 7 EN @@ -1237,9 +1394,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event PERIPHACCERR will publish to. + DPPI channel that event PERIPHACCERR will publish to 0 - 3 + 7 EN @@ -1544,9 +1701,10 @@ POSSIBILITY OF SUCH DAMAGE.\n SECUREMAPPING - Define configuration capabilities for TrustZone Cortex-M secure attribute + Define configuration capabilities for TrustZone Cortex-M secure attribute 0 1 + read-only NonSecure @@ -2694,7 +2852,7 @@ POSSIBILITY OF SUCH DAMAGE.\n REGION Region number 0 - 3 + 4 LOCK @@ -3190,6 +3348,32 @@ POSSIBILITY OF SUCH DAMAGE.\n + + EXTPOFCON + External power failure warning configuration + 0x514 + read-write + + + POF + Enable or disable external power failure warning + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + DCDCEN Enable DC/DC mode of the main voltage regulator. @@ -3336,9 +3520,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task HFCLKSTART will subscribe to + DPPI channel that task HFCLKSTART will subscribe to 0 - 3 + 7 EN @@ -3367,9 +3551,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task HFCLKSTOP will subscribe to + DPPI channel that task HFCLKSTOP will subscribe to 0 - 3 + 7 EN @@ -3398,9 +3582,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task LFCLKSTART will subscribe to + DPPI channel that task LFCLKSTART will subscribe to 0 - 3 + 7 EN @@ -3429,9 +3613,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task LFCLKSTOP will subscribe to + DPPI channel that task LFCLKSTOP will subscribe to 0 - 3 + 7 EN @@ -3512,9 +3696,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event HFCLKSTARTED will publish to. + DPPI channel that event HFCLKSTARTED will publish to 0 - 3 + 7 EN @@ -3543,9 +3727,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event LFCLKSTARTED will publish to. + DPPI channel that event LFCLKSTARTED will publish to 0 - 3 + 7 EN @@ -3818,6 +4002,11 @@ POSSIBILITY OF SUCH DAMAGE.\n 0 0 + + HFINT + HFINT - 64 MHz on-chip oscillator + 0 + HFXO HFXO - 64 MHz clock derived from external 32 MHz crystal oscillator @@ -4056,9 +4245,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task CONSTLAT will subscribe to + DPPI channel that task CONSTLAT will subscribe to 0 - 3 + 7 EN @@ -4087,9 +4276,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task LOWPWR will subscribe to + DPPI channel that task LOWPWR will subscribe to 0 - 3 + 7 EN @@ -4196,9 +4385,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event POFWARN will publish to. + DPPI channel that event POFWARN will publish to 0 - 3 + 7 EN @@ -4227,9 +4416,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event SLEEPENTER will publish to. + DPPI channel that event SLEEPENTER will publish to 0 - 3 + 7 EN @@ -4258,9 +4447,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event SLEEPEXIT will publish to. + DPPI channel that event SLEEPEXIT will publish to 0 - 3 + 7 EN @@ -4697,6 +4886,67 @@ POSSIBILITY OF SUCH DAMAGE.\n + + LTEMODEM + LTE Modem + POWER_LTEMODEM + read-write + 0x610 + + STARTN + Start LTE modem + 0x000 + read-write + 0x00000001 + + + STARTN + Start LTE modem + 0 + 0 + + + Start + Start LTE modem + 0 + + + Hold + Hold LTE modem disabled + 1 + + + + + + + FORCEOFF + Force off LTE modem + 0x004 + read-write + 0x00000000 + + + FORCEOFF + Force off LTE modem + 0 + 0 + + + Release + Release force off + 0 + + + Hold + Hold force off active + 1 + + + + + + @@ -4745,7 +4995,7 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x400 RXDATA - Data sent from the debugger to the CPU + Data sent from the debugger to the CPU. 0x000 read-only 0x00000000 @@ -4760,7 +5010,7 @@ POSSIBILITY OF SUCH DAMAGE.\n RXSTATUS - Status to indicate if data sent from the debugger to the CPU has been read + This register shows a status that indicates if data sent from the debugger to the CPU has been read. 0x004 read-only 0x00000000 @@ -4787,7 +5037,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TXDATA - Data sent from the CPU to the debugger + Data sent from the CPU to the debugger. 0x80 read-write 0x00000000 @@ -4802,7 +5052,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TXSTATUS - Status to indicate if data sent from the CPU to the debugger has been read + This register shows a status that indicates if the data sent from the CPU to the debugger has been read. 0x84 read-only 0x00000000 @@ -4836,14 +5086,14 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x500 LOCK - Lock register ERASEPROTECT.DISABLE from being written until next reset + This register locks the ERASEPROTECT.DISABLE register from being written until next reset. 0x000 read-writeOnce 0x00000000 LOCK - Lock register ERASEPROTECT.DISABLE from being written until next reset + Lock ERASEPROTECT.DISABLE register from being written until next reset 0 0 @@ -4863,14 +5113,14 @@ POSSIBILITY OF SUCH DAMAGE.\n DISABLE - Disable ERASEPROTECT and perform ERASEALL + This register disables the ERASEPROTECT register and performs an ERASEALL operation. 0x004 read-write 0x00000000 KEY - The ERASEALL sequence will be initiated if value of KEY fields are non-zero and KEY fields match on both CPU and debugger side + The ERASEALL sequence is initiated if the value of the KEY fields are non-zero and the KEY fields match on both the CPU and debugger sides. 0 31 @@ -4892,7 +5142,7 @@ POSSIBILITY OF SUCH DAMAGE.\n registers - UARTE0_SPIM0_SPIS0_TWIM0_TWIS0 + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 8 SPIM @@ -4990,9 +5240,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task START will subscribe to + DPPI channel that task START will subscribe to 0 - 3 + 7 EN @@ -5021,9 +5271,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task STOP will subscribe to + DPPI channel that task STOP will subscribe to 0 - 3 + 7 EN @@ -5052,9 +5302,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task SUSPEND will subscribe to + DPPI channel that task SUSPEND will subscribe to 0 - 3 + 7 EN @@ -5083,9 +5333,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task RESUME will subscribe to + DPPI channel that task RESUME will subscribe to 0 - 3 + 7 EN @@ -5244,9 +5494,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event STOPPED will publish to. + DPPI channel that event STOPPED will publish to 0 - 3 + 7 EN @@ -5275,9 +5525,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event ENDRX will publish to. + DPPI channel that event ENDRX will publish to 0 - 3 + 7 EN @@ -5306,9 +5556,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event END will publish to. + DPPI channel that event END will publish to 0 - 3 + 7 EN @@ -5337,9 +5587,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event ENDTX will publish to. + DPPI channel that event ENDTX will publish to 0 - 3 + 7 EN @@ -5368,9 +5618,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event STARTED will publish to. + DPPI channel that event STARTED will publish to 0 - 3 + 7 EN @@ -6129,7 +6379,7 @@ POSSIBILITY OF SUCH DAMAGE.\n registers - UARTE0_SPIM0_SPIS0_TWIM0_TWIS0 + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 8 SPIS @@ -6185,9 +6435,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task ACQUIRE will subscribe to + DPPI channel that task ACQUIRE will subscribe to 0 - 3 + 7 EN @@ -6216,9 +6466,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task RELEASE will subscribe to + DPPI channel that task RELEASE will subscribe to 0 - 3 + 7 EN @@ -6325,9 +6575,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event END will publish to. + DPPI channel that event END will publish to 0 - 3 + 7 EN @@ -6356,9 +6606,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event ENDRX will publish to. + DPPI channel that event ENDRX will publish to 0 - 3 + 7 EN @@ -6387,9 +6637,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event ACQUIRED will publish to. + DPPI channel that event ACQUIRED will publish to 0 - 3 + 7 EN @@ -7134,7 +7384,7 @@ POSSIBILITY OF SUCH DAMAGE.\n registers - UARTE0_SPIM0_SPIS0_TWIM0_TWIS0 + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 8 TWIM @@ -7253,9 +7503,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task STARTRX will subscribe to + DPPI channel that task STARTRX will subscribe to 0 - 3 + 7 EN @@ -7284,9 +7534,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task STARTTX will subscribe to + DPPI channel that task STARTTX will subscribe to 0 - 3 + 7 EN @@ -7315,9 +7565,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task STOP will subscribe to + DPPI channel that task STOP will subscribe to 0 - 3 + 7 EN @@ -7346,9 +7596,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task SUSPEND will subscribe to + DPPI channel that task SUSPEND will subscribe to 0 - 3 + 7 EN @@ -7377,9 +7627,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task RESUME will subscribe to + DPPI channel that task RESUME will subscribe to 0 - 3 + 7 EN @@ -7590,9 +7840,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event STOPPED will publish to. + DPPI channel that event STOPPED will publish to 0 - 3 + 7 EN @@ -7621,9 +7871,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event ERROR will publish to. + DPPI channel that event ERROR will publish to 0 - 3 + 7 EN @@ -7652,9 +7902,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event SUSPENDED will publish to. + DPPI channel that event SUSPENDED will publish to 0 - 3 + 7 EN @@ -7683,9 +7933,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event RXSTARTED will publish to. + DPPI channel that event RXSTARTED will publish to 0 - 3 + 7 EN @@ -7714,9 +7964,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event TXSTARTED will publish to. + DPPI channel that event TXSTARTED will publish to 0 - 3 + 7 EN @@ -7745,9 +7995,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event LASTRX will publish to. + DPPI channel that event LASTRX will publish to 0 - 3 + 7 EN @@ -7776,9 +8026,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event LASTTX will publish to. + DPPI channel that event LASTTX will publish to 0 - 3 + 7 EN @@ -8817,7 +9067,7 @@ POSSIBILITY OF SUCH DAMAGE.\n registers - UARTE0_SPIM0_SPIS0_TWIM0_TWIS0 + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 8 TWIS @@ -8936,9 +9186,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task STOP will subscribe to + DPPI channel that task STOP will subscribe to 0 - 3 + 7 EN @@ -8967,9 +9217,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task SUSPEND will subscribe to + DPPI channel that task SUSPEND will subscribe to 0 - 3 + 7 EN @@ -8998,9 +9248,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task RESUME will subscribe to + DPPI channel that task RESUME will subscribe to 0 - 3 + 7 EN @@ -9029,9 +9279,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task PREPARERX will subscribe to + DPPI channel that task PREPARERX will subscribe to 0 - 3 + 7 EN @@ -9060,9 +9310,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task PREPARETX will subscribe to + DPPI channel that task PREPARETX will subscribe to 0 - 3 + 7 EN @@ -9247,9 +9497,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event STOPPED will publish to. + DPPI channel that event STOPPED will publish to 0 - 3 + 7 EN @@ -9278,9 +9528,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event ERROR will publish to. + DPPI channel that event ERROR will publish to 0 - 3 + 7 EN @@ -9309,9 +9559,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event RXSTARTED will publish to. + DPPI channel that event RXSTARTED will publish to 0 - 3 + 7 EN @@ -9340,9 +9590,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event TXSTARTED will publish to. + DPPI channel that event TXSTARTED will publish to 0 - 3 + 7 EN @@ -9371,9 +9621,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event WRITE will publish to. + DPPI channel that event WRITE will publish to 0 - 3 + 7 EN @@ -9402,9 +9652,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event READ will publish to. + DPPI channel that event READ will publish to 0 - 3 + 7 EN @@ -9996,7 +10246,7 @@ POSSIBILITY OF SUCH DAMAGE.\n MATCH - Which of the addresses in {ADDRESS} matched the incoming address + Indication of which address in {ADDRESS} that matched the incoming address 0 0 @@ -10342,7 +10592,7 @@ POSSIBILITY OF SUCH DAMAGE.\n registers - UARTE0_SPIM0_SPIS0_TWIM0_TWIS0 + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 8 UARTE @@ -10461,9 +10711,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task STARTRX will subscribe to + DPPI channel that task STARTRX will subscribe to 0 - 3 + 7 EN @@ -10492,9 +10742,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task STOPRX will subscribe to + DPPI channel that task STOPRX will subscribe to 0 - 3 + 7 EN @@ -10523,9 +10773,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task STARTTX will subscribe to + DPPI channel that task STARTTX will subscribe to 0 - 3 + 7 EN @@ -10554,9 +10804,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task STOPTX will subscribe to + DPPI channel that task STOPTX will subscribe to 0 - 3 + 7 EN @@ -10585,9 +10835,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task FLUSHRX will subscribe to + DPPI channel that task FLUSHRX will subscribe to 0 - 3 + 7 EN @@ -10902,9 +11152,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event CTS will publish to. + DPPI channel that event CTS will publish to 0 - 3 + 7 EN @@ -10933,9 +11183,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event NCTS will publish to. + DPPI channel that event NCTS will publish to 0 - 3 + 7 EN @@ -10964,9 +11214,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event RXDRDY will publish to. + DPPI channel that event RXDRDY will publish to 0 - 3 + 7 EN @@ -10995,9 +11245,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event ENDRX will publish to. + DPPI channel that event ENDRX will publish to 0 - 3 + 7 EN @@ -11026,9 +11276,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event TXDRDY will publish to. + DPPI channel that event TXDRDY will publish to 0 - 3 + 7 EN @@ -11057,9 +11307,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event ENDTX will publish to. + DPPI channel that event ENDTX will publish to 0 - 3 + 7 EN @@ -11088,9 +11338,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event ERROR will publish to. + DPPI channel that event ERROR will publish to 0 - 3 + 7 EN @@ -11119,9 +11369,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event RXTO will publish to. + DPPI channel that event RXTO will publish to 0 - 3 + 7 EN @@ -11150,9 +11400,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event RXSTARTED will publish to. + DPPI channel that event RXSTARTED will publish to 0 - 3 + 7 EN @@ -11181,9 +11431,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event TXSTARTED will publish to. + DPPI channel that event TXSTARTED will publish to 0 - 3 + 7 EN @@ -11212,9 +11462,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event TXSTOPPED will publish to. + DPPI channel that event TXSTOPPED will publish to 0 - 3 + 7 EN @@ -12097,7 +12347,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ERRORSRC - Error source Note : this register is read / write one to clear. + Error source This register is read/write one to clear. 0x480 read-write oneToClear @@ -12445,7 +12695,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Baud1M - 1Mega baud + 1 megabaud 0x10000000 @@ -12621,7 +12871,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE0_SPIM0_SPIS0_TWIM0_TWIS0 + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 8 @@ -12633,7 +12883,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE0_SPIM0_SPIS0_TWIM0_TWIS0 + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 8 @@ -12645,7 +12895,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE0_SPIM0_SPIS0_TWIM0_TWIS0 + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 8 @@ -12657,7 +12907,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE0_SPIM0_SPIS0_TWIM0_TWIS0 + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 8 @@ -12669,7 +12919,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE0_SPIM0_SPIS0_TWIM0_TWIS0 + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 8 @@ -12680,7 +12930,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE1_SPIM1_SPIS1_TWIM1_TWIS1 + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 9 @@ -12692,7 +12942,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE1_SPIM1_SPIS1_TWIM1_TWIS1 + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 9 @@ -12704,7 +12954,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE1_SPIM1_SPIS1_TWIM1_TWIS1 + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 9 @@ -12716,7 +12966,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE1_SPIM1_SPIS1_TWIM1_TWIS1 + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 9 @@ -12728,7 +12978,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE1_SPIM1_SPIS1_TWIM1_TWIS1 + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 9 @@ -12739,7 +12989,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE1_SPIM1_SPIS1_TWIM1_TWIS1 + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 9 @@ -12751,7 +13001,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE1_SPIM1_SPIS1_TWIM1_TWIS1 + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 9 @@ -12763,7 +13013,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE1_SPIM1_SPIS1_TWIM1_TWIS1 + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 9 @@ -12775,7 +13025,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE1_SPIM1_SPIS1_TWIM1_TWIS1 + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 9 @@ -12787,7 +13037,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE1_SPIM1_SPIS1_TWIM1_TWIS1 + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 9 @@ -12798,7 +13048,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE2_SPIM2_SPIS2_TWIM2_TWIS2 + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 10 @@ -12810,7 +13060,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE2_SPIM2_SPIS2_TWIM2_TWIS2 + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 10 @@ -12822,7 +13072,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE2_SPIM2_SPIS2_TWIM2_TWIS2 + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 10 @@ -12834,7 +13084,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE2_SPIM2_SPIS2_TWIM2_TWIS2 + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 10 @@ -12846,7 +13096,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE2_SPIM2_SPIS2_TWIM2_TWIS2 + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 10 @@ -12857,7 +13107,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE2_SPIM2_SPIS2_TWIM2_TWIS2 + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 10 @@ -12869,7 +13119,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE2_SPIM2_SPIS2_TWIM2_TWIS2 + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 10 @@ -12881,7 +13131,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE2_SPIM2_SPIS2_TWIM2_TWIS2 + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 10 @@ -12893,7 +13143,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE2_SPIM2_SPIS2_TWIM2_TWIS2 + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 10 @@ -12905,7 +13155,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE2_SPIM2_SPIS2_TWIM2_TWIS2 + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 10 @@ -12916,7 +13166,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE3_SPIM3_SPIS3_TWIM3_TWIS3 + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 11 @@ -12928,7 +13178,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE3_SPIM3_SPIS3_TWIM3_TWIS3 + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 11 @@ -12940,7 +13190,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE3_SPIM3_SPIS3_TWIM3_TWIS3 + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 11 @@ -12952,7 +13202,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE3_SPIM3_SPIS3_TWIM3_TWIS3 + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 11 @@ -12964,7 +13214,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE3_SPIM3_SPIS3_TWIM3_TWIS3 + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 11 @@ -12975,7 +13225,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE3_SPIM3_SPIS3_TWIM3_TWIS3 + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 11 @@ -12987,7 +13237,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE3_SPIM3_SPIS3_TWIM3_TWIS3 + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 11 @@ -12999,7 +13249,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE3_SPIM3_SPIS3_TWIM3_TWIS3 + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 11 @@ -13011,7 +13261,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE3_SPIM3_SPIS3_TWIM3_TWIS3 + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 11 @@ -13023,7 +13273,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - UARTE3_SPIM3_SPIS3_TWIM3_TWIS3 + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 11 @@ -13125,9 +13375,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task OUT[n] will subscribe to + DPPI channel that task OUT[n] will subscribe to 0 - 3 + 7 EN @@ -13158,9 +13408,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task SET[n] will subscribe to + DPPI channel that task SET[n] will subscribe to 0 - 3 + 7 EN @@ -13191,9 +13441,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task CLR[n] will subscribe to + DPPI channel that task CLR[n] will subscribe to 0 - 3 + 7 EN @@ -13278,9 +13528,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event IN[n] will publish to. + DPPI channel that event IN[n] will publish to 0 - 3 + 7 EN @@ -13309,9 +13559,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event PORT will publish to. + DPPI channel that event PORT will publish to 0 - 3 + 7 EN @@ -13838,7 +14088,7 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x8 0x4 CONFIG[%s] - Description collection: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event + Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event 0x510 read-write @@ -13867,7 +14117,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PSEL - GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event + GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event 8 12 @@ -14032,9 +14282,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task START will subscribe to + DPPI channel that task START will subscribe to 0 - 3 + 7 EN @@ -14063,9 +14313,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task SAMPLE will subscribe to + DPPI channel that task SAMPLE will subscribe to 0 - 3 + 7 EN @@ -14094,9 +14344,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task STOP will subscribe to + DPPI channel that task STOP will subscribe to 0 - 3 + 7 EN @@ -14125,9 +14375,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task CALIBRATEOFFSET will subscribe to + DPPI channel that task CALIBRATEOFFSET will subscribe to 0 - 3 + 7 EN @@ -14373,9 +14623,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event STARTED will publish to. + DPPI channel that event STARTED will publish to 0 - 3 + 7 EN @@ -14404,9 +14654,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event END will publish to. + DPPI channel that event END will publish to 0 - 3 + 7 EN @@ -14435,9 +14685,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event DONE will publish to. + DPPI channel that event DONE will publish to 0 - 3 + 7 EN @@ -14466,9 +14716,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event RESULTDONE will publish to. + DPPI channel that event RESULTDONE will publish to 0 - 3 + 7 EN @@ -14497,9 +14747,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event CALIBRATEDONE will publish to. + DPPI channel that event CALIBRATEDONE will publish to 0 - 3 + 7 EN @@ -14528,9 +14778,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event STOPPED will publish to. + DPPI channel that event STOPPED will publish to 0 - 3 + 7 EN @@ -14567,9 +14817,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event CH[n].LIMITH will publish to. + DPPI channel that event CH[n].LIMITH will publish to 0 - 3 + 7 EN @@ -14598,9 +14848,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event CH[n].LIMITL will publish to. + DPPI channel that event CH[n].LIMITL will publish to 0 - 3 + 7 EN @@ -16998,9 +17248,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task START will subscribe to + DPPI channel that task START will subscribe to 0 - 3 + 7 EN @@ -17029,9 +17279,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task STOP will subscribe to + DPPI channel that task STOP will subscribe to 0 - 3 + 7 EN @@ -17060,9 +17310,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task COUNT will subscribe to + DPPI channel that task COUNT will subscribe to 0 - 3 + 7 EN @@ -17091,9 +17341,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task CLEAR will subscribe to + DPPI channel that task CLEAR will subscribe to 0 - 3 + 7 EN @@ -17122,9 +17372,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task SHUTDOWN will subscribe to + DPPI channel that task SHUTDOWN will subscribe to 0 - 3 + 7 EN @@ -17155,9 +17405,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task CAPTURE[n] will subscribe to + DPPI channel that task CAPTURE[n] will subscribe to 0 - 3 + 7 EN @@ -17216,9 +17466,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event COMPARE[n] will publish to. + DPPI channel that event COMPARE[n] will publish to 0 - 3 + 7 EN @@ -18097,9 +18347,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task START will subscribe to + DPPI channel that task START will subscribe to 0 - 3 + 7 EN @@ -18128,9 +18378,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task STOP will subscribe to + DPPI channel that task STOP will subscribe to 0 - 3 + 7 EN @@ -18159,9 +18409,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task CLEAR will subscribe to + DPPI channel that task CLEAR will subscribe to 0 - 3 + 7 EN @@ -18190,9 +18440,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task TRIGOVRFLW will subscribe to + DPPI channel that task TRIGOVRFLW will subscribe to 0 - 3 + 7 EN @@ -18301,9 +18551,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event TICK will publish to. + DPPI channel that event TICK will publish to 0 - 3 + 7 EN @@ -18332,9 +18582,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event OVRFLW will publish to. + DPPI channel that event OVRFLW will publish to 0 - 3 + 7 EN @@ -18365,9 +18615,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event COMPARE[n] will publish to. + DPPI channel that event COMPARE[n] will publish to 0 - 3 + 7 EN @@ -18747,7 +18997,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Enabled - Disable + Enable 1 @@ -18765,7 +19015,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Enabled - Disable + Enable 1 @@ -18783,7 +19033,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Enabled - Disable + Enable 1 @@ -18801,7 +19051,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Enabled - Disable + Enable 1 @@ -18819,7 +19069,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Enabled - Disable + Enable 1 @@ -18837,7 +19087,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Enabled - Disable + Enable 1 @@ -19265,7 +19515,7 @@ POSSIBILITY OF SUCH DAMAGE.\n DPPIC_NS - Distributed Programmable Peripheral Interconnect Controller 0 + Distributed programmable peripheral interconnect controller 0 0x40017000 DPPIC @@ -19345,9 +19595,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task CHG[n].EN will subscribe to + DPPI channel that task CHG[n].EN will subscribe to 0 - 3 + 7 EN @@ -19376,9 +19626,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task CHG[n].DIS will subscribe to + DPPI channel that task CHG[n].DIS will subscribe to 0 - 3 + 7 EN @@ -19705,19 +19955,19 @@ POSSIBILITY OF SUCH DAMAGE.\n CH0 - Channel 0 enable set register. Writing '0' has no effect + Channel 0 enable set register. Writing 0 has no effect. 0 0 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -19732,19 +19982,19 @@ POSSIBILITY OF SUCH DAMAGE.\n CH1 - Channel 1 enable set register. Writing '0' has no effect + Channel 1 enable set register. Writing 0 has no effect. 1 1 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -19759,19 +20009,19 @@ POSSIBILITY OF SUCH DAMAGE.\n CH2 - Channel 2 enable set register. Writing '0' has no effect + Channel 2 enable set register. Writing 0 has no effect. 2 2 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -19786,19 +20036,19 @@ POSSIBILITY OF SUCH DAMAGE.\n CH3 - Channel 3 enable set register. Writing '0' has no effect + Channel 3 enable set register. Writing 0 has no effect. 3 3 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -19813,19 +20063,19 @@ POSSIBILITY OF SUCH DAMAGE.\n CH4 - Channel 4 enable set register. Writing '0' has no effect + Channel 4 enable set register. Writing 0 has no effect. 4 4 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -19840,19 +20090,19 @@ POSSIBILITY OF SUCH DAMAGE.\n CH5 - Channel 5 enable set register. Writing '0' has no effect + Channel 5 enable set register. Writing 0 has no effect. 5 5 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -19867,19 +20117,19 @@ POSSIBILITY OF SUCH DAMAGE.\n CH6 - Channel 6 enable set register. Writing '0' has no effect + Channel 6 enable set register. Writing 0 has no effect. 6 6 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -19894,19 +20144,19 @@ POSSIBILITY OF SUCH DAMAGE.\n CH7 - Channel 7 enable set register. Writing '0' has no effect + Channel 7 enable set register. Writing 0 has no effect. 7 7 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -19921,19 +20171,19 @@ POSSIBILITY OF SUCH DAMAGE.\n CH8 - Channel 8 enable set register. Writing '0' has no effect + Channel 8 enable set register. Writing 0 has no effect. 8 8 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -19948,19 +20198,19 @@ POSSIBILITY OF SUCH DAMAGE.\n CH9 - Channel 9 enable set register. Writing '0' has no effect + Channel 9 enable set register. Writing 0 has no effect. 9 9 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -19975,19 +20225,19 @@ POSSIBILITY OF SUCH DAMAGE.\n CH10 - Channel 10 enable set register. Writing '0' has no effect + Channel 10 enable set register. Writing 0 has no effect. 10 10 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -20002,19 +20252,19 @@ POSSIBILITY OF SUCH DAMAGE.\n CH11 - Channel 11 enable set register. Writing '0' has no effect + Channel 11 enable set register. Writing 0 has no effect. 11 11 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -20029,19 +20279,19 @@ POSSIBILITY OF SUCH DAMAGE.\n CH12 - Channel 12 enable set register. Writing '0' has no effect + Channel 12 enable set register. Writing 0 has no effect. 12 12 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -20056,19 +20306,19 @@ POSSIBILITY OF SUCH DAMAGE.\n CH13 - Channel 13 enable set register. Writing '0' has no effect + Channel 13 enable set register. Writing 0 has no effect. 13 13 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -20083,19 +20333,19 @@ POSSIBILITY OF SUCH DAMAGE.\n CH14 - Channel 14 enable set register. Writing '0' has no effect + Channel 14 enable set register. Writing 0 has no effect. 14 14 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -20110,19 +20360,19 @@ POSSIBILITY OF SUCH DAMAGE.\n CH15 - Channel 15 enable set register. Writing '0' has no effect + Channel 15 enable set register. Writing 0 has no effect. 15 15 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -20146,19 +20396,19 @@ POSSIBILITY OF SUCH DAMAGE.\n CH0 - Channel 0 enable clear register. Writing '0' has no effect + Channel 0 enable clear register. Writing 0 has no effect. 0 0 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -20166,26 +20416,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: disable channel + Write: Disable channel 1 CH1 - Channel 1 enable clear register. Writing '0' has no effect + Channel 1 enable clear register. Writing 0 has no effect. 1 1 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -20193,26 +20443,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: disable channel + Write: Disable channel 1 CH2 - Channel 2 enable clear register. Writing '0' has no effect + Channel 2 enable clear register. Writing 0 has no effect. 2 2 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -20220,26 +20470,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: disable channel + Write: Disable channel 1 CH3 - Channel 3 enable clear register. Writing '0' has no effect + Channel 3 enable clear register. Writing 0 has no effect. 3 3 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -20247,26 +20497,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: disable channel + Write: Disable channel 1 CH4 - Channel 4 enable clear register. Writing '0' has no effect + Channel 4 enable clear register. Writing 0 has no effect. 4 4 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -20274,26 +20524,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: disable channel + Write: Disable channel 1 CH5 - Channel 5 enable clear register. Writing '0' has no effect + Channel 5 enable clear register. Writing 0 has no effect. 5 5 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -20301,26 +20551,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: disable channel + Write: Disable channel 1 CH6 - Channel 6 enable clear register. Writing '0' has no effect + Channel 6 enable clear register. Writing 0 has no effect. 6 6 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -20328,26 +20578,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: disable channel + Write: Disable channel 1 CH7 - Channel 7 enable clear register. Writing '0' has no effect + Channel 7 enable clear register. Writing 0 has no effect. 7 7 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -20355,26 +20605,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: disable channel + Write: Disable channel 1 CH8 - Channel 8 enable clear register. Writing '0' has no effect + Channel 8 enable clear register. Writing 0 has no effect. 8 8 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -20382,26 +20632,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: disable channel + Write: Disable channel 1 CH9 - Channel 9 enable clear register. Writing '0' has no effect + Channel 9 enable clear register. Writing 0 has no effect. 9 9 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -20409,26 +20659,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: disable channel + Write: Disable channel 1 CH10 - Channel 10 enable clear register. Writing '0' has no effect + Channel 10 enable clear register. Writing 0 has no effect. 10 10 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -20436,26 +20686,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: disable channel + Write: Disable channel 1 CH11 - Channel 11 enable clear register. Writing '0' has no effect + Channel 11 enable clear register. Writing 0 has no effect. 11 11 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -20463,26 +20713,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: disable channel + Write: Disable channel 1 CH12 - Channel 12 enable clear register. Writing '0' has no effect + Channel 12 enable clear register. Writing 0 has no effect. 12 12 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -20490,26 +20740,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: disable channel + Write: Disable channel 1 CH13 - Channel 13 enable clear register. Writing '0' has no effect + Channel 13 enable clear register. Writing 0 has no effect. 13 13 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -20517,26 +20767,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: disable channel + Write: Disable channel 1 CH14 - Channel 14 enable clear register. Writing '0' has no effect + Channel 14 enable clear register. Writing 0 has no effect. 14 14 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -20544,26 +20794,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: disable channel + Write: Disable channel 1 CH15 - Channel 15 enable clear register. Writing '0' has no effect + Channel 15 enable clear register. Writing 0 has no effect. 15 15 read Disabled - Read: channel disabled + Read: Channel disabled 0 Enabled - Read: channel enabled + Read: Channel enabled 1 @@ -20571,7 +20821,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: disable channel + Write: Disable channel 1 @@ -20582,7 +20832,7 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x6 0x4 CHG[%s] - Description collection: Channel group n Note: Writes to this register is ignored if either SUBSCRIBE_CHG[n].EN/DIS are enabled. + Description collection: Channel group n Note: Writes to this register are ignored if either SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS is enabled 0x800 read-write @@ -20880,7 +21130,7 @@ POSSIBILITY OF SUCH DAMAGE.\n DPPIC_S - Distributed Programmable Peripheral Interconnect Controller 1 + Distributed programmable peripheral interconnect controller 1 0x50017000 @@ -20933,9 +21183,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task START will subscribe to + DPPI channel that task START will subscribe to 0 - 3 + 7 EN @@ -20990,9 +21240,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event TIMEOUT will publish to. + DPPI channel that event TIMEOUT will publish to 0 - 3 + 7 EN @@ -21563,9 +21813,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task TRIGGER[n] will subscribe to + DPPI channel that task TRIGGER[n] will subscribe to 0 - 3 + 7 EN @@ -21624,9 +21874,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event TRIGGERED[n] will publish to. + DPPI channel that event TRIGGERED[n] will publish to 0 - 3 + 7 EN @@ -23038,9 +23288,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task STOP will subscribe to + DPPI channel that task STOP will subscribe to 0 - 3 + 7 EN @@ -23071,9 +23321,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task SEQSTART[n] will subscribe to + DPPI channel that task SEQSTART[n] will subscribe to 0 - 3 + 7 EN @@ -23102,9 +23352,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task NEXTSTEP will subscribe to + DPPI channel that task NEXTSTEP will subscribe to 0 - 3 + 7 EN @@ -23267,9 +23517,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event STOPPED will publish to. + DPPI channel that event STOPPED will publish to 0 - 3 + 7 EN @@ -23300,9 +23550,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event SEQSTARTED[n] will publish to. + DPPI channel that event SEQSTARTED[n] will publish to 0 - 3 + 7 EN @@ -23333,9 +23583,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event SEQEND[n] will publish to. + DPPI channel that event SEQEND[n] will publish to 0 - 3 + 7 EN @@ -23364,9 +23614,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event PWMPERIODEND will publish to. + DPPI channel that event PWMPERIODEND will publish to 0 - 3 + 7 EN @@ -23395,9 +23645,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event LOOPSDONE will publish to. + DPPI channel that event LOOPSDONE will publish to 0 - 3 + 7 EN @@ -24520,9 +24770,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task START will subscribe to + DPPI channel that task START will subscribe to 0 - 3 + 7 EN @@ -24551,9 +24801,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task STOP will subscribe to + DPPI channel that task STOP will subscribe to 0 - 3 + 7 EN @@ -24660,9 +24910,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event STARTED will publish to. + DPPI channel that event STARTED will publish to 0 - 3 + 7 EN @@ -24691,9 +24941,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event STOPPED will publish to. + DPPI channel that event STOPPED will publish to 0 - 3 + 7 EN @@ -24722,9 +24972,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event END will publish to. + DPPI channel that event END will publish to 0 - 3 + 7 EN @@ -25021,7 +25271,7 @@ POSSIBILITY OF SUCH DAMAGE.\n FREQ - PDM_CLK frequency + PDM_CLK frequency configuration. 0 31 @@ -25074,19 +25324,19 @@ POSSIBILITY OF SUCH DAMAGE.\n Stereo - Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] + Sample and store one pair (left + right) of 16-bit samples per RAM word R=[31:16]; L=[15:0] 0 Mono - Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] + Sample and store two successive left samples (16 bits each) per RAM word L1=[31:16]; L0=[15:0] 1 EDGE - Defines on which PDM_CLK edge Left (or mono) is sampled + Defines on which PDM_CLK edge left (or mono) is sampled 1 1 @@ -25119,17 +25369,17 @@ POSSIBILITY OF SUCH DAMAGE.\n MinGain - -20dB gain adjustment (minimum) + -20 dB gain adjustment (minimum) 0x00 DefaultGain - 0dB gain adjustment + 0 dB gain adjustment 0x28 MaxGain - +20dB gain adjustment (maximum) + +20 dB gain adjustment (maximum) 0x50 @@ -25151,17 +25401,17 @@ POSSIBILITY OF SUCH DAMAGE.\n MinGain - -20dB gain adjustment (minimum) + -20 dB gain adjustment (minimum) 0x00 DefaultGain - 0dB gain adjustment + 0 dB gain adjustment 0x28 MaxGain - +20dB gain adjustment (maximum) + +20 dB gain adjustment (maximum) 0x50 @@ -25385,9 +25635,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task START will subscribe to + DPPI channel that task START will subscribe to 0 - 3 + 7 EN @@ -25416,9 +25666,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task STOP will subscribe to + DPPI channel that task STOP will subscribe to 0 - 3 + 7 EN @@ -25529,9 +25779,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event RXPTRUPD will publish to. + DPPI channel that event RXPTRUPD will publish to 0 - 3 + 7 EN @@ -25560,9 +25810,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event STOPPED will publish to. + DPPI channel that event STOPPED will publish to 0 - 3 + 7 EN @@ -25591,9 +25841,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event TXPTRUPD will publish to. + DPPI channel that event TXPTRUPD will publish to 0 - 3 + 7 EN @@ -26511,7 +26761,7 @@ POSSIBILITY OF SUCH DAMAGE.\n IPC_NS - Inter Processor Communication 0 + Interprocessor communication 0 0x4002A000 IPC @@ -26532,13 +26782,13 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x8 0x4 TASKS_SEND[%s] - Description collection: Trigger events on channel enabled in SEND_CNF[n]. + Description collection: Trigger events on IPC channel enabled in SEND_CNF[n] 0x000 write-only TASKS_SEND - Trigger events on channel enabled in SEND_CNF[n]. + Trigger events on IPC channel enabled in SEND_CNF[n] 0 0 @@ -26561,9 +26811,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that task SEND[n] will subscribe to + DPPI channel that task SEND[n] will subscribe to 0 - 3 + 7 EN @@ -26588,13 +26838,13 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x8 0x4 EVENTS_RECEIVE[%s] - Description collection: Event received on one or more of the enabled channels in RECEIVE_CNF[n]. + Description collection: Event received on one or more of the enabled IPC channels in RECEIVE_CNF[n] 0x100 read-write EVENTS_RECEIVE - Event received on one or more of the enabled channels in RECEIVE_CNF[n]. + Event received on one or more of the enabled IPC channels in RECEIVE_CNF[n] 0 0 @@ -26622,9 +26872,9 @@ POSSIBILITY OF SUCH DAMAGE.\n CHIDX - Channel that event RECEIVE[n] will publish to. + DPPI channel that event RECEIVE[n] will publish to 0 - 3 + 7 EN @@ -27409,151 +27659,151 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x8 0x4 SEND_CNF[%s] - Description collection: Send event configuration for TASKS_SEND[n]. + Description collection: Send event configuration for TASKS_SEND[n] 0x510 read-write 0x00000000 CHEN0 - Enable broadcasting on channel 0. + Enable broadcasting on IPC channel 0 0 0 Disable - Disable broadcast. + Disable broadcast 0 Enable - Enable broadcast. + Enable broadcast 1 CHEN1 - Enable broadcasting on channel 1. + Enable broadcasting on IPC channel 1 1 1 Disable - Disable broadcast. + Disable broadcast 0 Enable - Enable broadcast. + Enable broadcast 1 CHEN2 - Enable broadcasting on channel 2. + Enable broadcasting on IPC channel 2 2 2 Disable - Disable broadcast. + Disable broadcast 0 Enable - Enable broadcast. + Enable broadcast 1 CHEN3 - Enable broadcasting on channel 3. + Enable broadcasting on IPC channel 3 3 3 Disable - Disable broadcast. + Disable broadcast 0 Enable - Enable broadcast. + Enable broadcast 1 CHEN4 - Enable broadcasting on channel 4. + Enable broadcasting on IPC channel 4 4 4 Disable - Disable broadcast. + Disable broadcast 0 Enable - Enable broadcast. + Enable broadcast 1 CHEN5 - Enable broadcasting on channel 5. + Enable broadcasting on IPC channel 5 5 5 Disable - Disable broadcast. + Disable broadcast 0 Enable - Enable broadcast. + Enable broadcast 1 CHEN6 - Enable broadcasting on channel 6. + Enable broadcasting on IPC channel 6 6 6 Disable - Disable broadcast. + Disable broadcast 0 Enable - Enable broadcast. + Enable broadcast 1 CHEN7 - Enable broadcasting on channel 7. + Enable broadcasting on IPC channel 7 7 7 Disable - Disable broadcast. + Disable broadcast 0 Enable - Enable broadcast. + Enable broadcast 1 @@ -27564,151 +27814,151 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x8 0x4 RECEIVE_CNF[%s] - Description collection: Receive event configuration for EVENTS_RECEIVE[n]. + Description collection: Receive event configuration for EVENTS_RECEIVE[n] 0x590 read-write 0x00000000 CHEN0 - Enable subscription to channel 0. + Enable subscription to IPC channel 0 0 0 Disable - Disable events. + Disable events 0 Enable - Enable events. + Enable events 1 CHEN1 - Enable subscription to channel 1. + Enable subscription to IPC channel 1 1 1 Disable - Disable events. + Disable events 0 Enable - Enable events. + Enable events 1 CHEN2 - Enable subscription to channel 2. + Enable subscription to IPC channel 2 2 2 Disable - Disable events. + Disable events 0 Enable - Enable events. + Enable events 1 CHEN3 - Enable subscription to channel 3. + Enable subscription to IPC channel 3 3 3 Disable - Disable events. + Disable events 0 Enable - Enable events. + Enable events 1 CHEN4 - Enable subscription to channel 4. + Enable subscription to IPC channel 4 4 4 Disable - Disable events. + Disable events 0 Enable - Enable events. + Enable events 1 CHEN5 - Enable subscription to channel 5. + Enable subscription to IPC channel 5 5 5 Disable - Disable events. + Disable events 0 Enable - Enable events. + Enable events 1 CHEN6 - Enable subscription to channel 6. + Enable subscription to IPC channel 6 6 6 Disable - Disable events. + Disable events 0 Enable - Enable events. + Enable events 1 CHEN7 - Enable subscription to channel 7. + Enable subscription to IPC channel 7 7 7 Disable - Disable events. + Disable events 0 Enable - Enable events. + Enable events 1 @@ -27719,7 +27969,7 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x4 0x4 GPMEM[%s] - Description collection: General purpose memory. + Description collection: General purpose memory 0x610 read-write 0x00000000 @@ -27736,7 +27986,7 @@ POSSIBILITY OF SUCH DAMAGE.\n IPC_S - Inter Processor Communication 1 + Interprocessor communication 1 0x5002A000 @@ -28272,7 +28522,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ID - Select key slot ID to be read over AHB, or pushed over secure APB, when TASKS_PUSH_KEYSLOT is started NOTE: ID=0 is not a valid key slot ID. The 0 ID should be used when the KMU is idle or not in use NOTE: Index N in UICR-&gt;KEYSLOT.KEY[N] and UICR-&gt;KEYSLOT.CONFIG[N] corresponds to KMU key slot ID=N+1 + Select key slot ID to be read over AHB, or pushed over secure APB, when TASKS_PUSH_KEYSLOT is started. NOTE: ID=0 is not a valid key slot ID. The 0 ID should be used when the KMU is idle or not in use. NOTE: Index N in UICR-&gt;KEYSLOT.KEY[N] and UICR-&gt;KEYSLOT.CONFIG[N] corresponds to KMU key slot ID=N+1. 0 7 @@ -28302,7 +28552,6 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x400 read-only 0x00000001 - READY @@ -28330,7 +28579,6 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x408 read-only 0x00000001 - READYNEXT @@ -28513,7 +28761,6 @@ POSSIBILITY OF SUCH DAMAGE.\n Unspecified 0x584 read-write - WEN @@ -28545,7 +28792,6 @@ POSSIBILITY OF SUCH DAMAGE.\n Non-secure APPROTECT enable register 0x588 write-only - SET @@ -34505,7 +34751,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN0 - Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. + Status on whether PIN[0] has met criteria set in PIN_CNF[0].SENSE register. Write '1' to clear. 0 0 @@ -34523,7 +34769,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN1 - Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. + Status on whether PIN[1] has met criteria set in PIN_CNF[1].SENSE register. Write '1' to clear. 1 1 @@ -34541,7 +34787,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN2 - Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. + Status on whether PIN[2] has met criteria set in PIN_CNF[2].SENSE register. Write '1' to clear. 2 2 @@ -34559,7 +34805,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN3 - Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. + Status on whether PIN[3] has met criteria set in PIN_CNF[3].SENSE register. Write '1' to clear. 3 3 @@ -34577,7 +34823,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN4 - Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. + Status on whether PIN[4] has met criteria set in PIN_CNF[4].SENSE register. Write '1' to clear. 4 4 @@ -34595,7 +34841,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN5 - Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. + Status on whether PIN[5] has met criteria set in PIN_CNF[5].SENSE register. Write '1' to clear. 5 5 @@ -34613,7 +34859,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN6 - Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. + Status on whether PIN[6] has met criteria set in PIN_CNF[6].SENSE register. Write '1' to clear. 6 6 @@ -34631,7 +34877,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN7 - Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. + Status on whether PIN[7] has met criteria set in PIN_CNF[7].SENSE register. Write '1' to clear. 7 7 @@ -34649,7 +34895,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN8 - Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. + Status on whether PIN[8] has met criteria set in PIN_CNF[8].SENSE register. Write '1' to clear. 8 8 @@ -34667,7 +34913,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN9 - Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. + Status on whether PIN[9] has met criteria set in PIN_CNF[9].SENSE register. Write '1' to clear. 9 9 @@ -34685,7 +34931,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN10 - Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. + Status on whether PIN[10] has met criteria set in PIN_CNF[10].SENSE register. Write '1' to clear. 10 10 @@ -34703,7 +34949,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN11 - Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. + Status on whether PIN[11] has met criteria set in PIN_CNF[11].SENSE register. Write '1' to clear. 11 11 @@ -34721,7 +34967,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN12 - Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. + Status on whether PIN[12] has met criteria set in PIN_CNF[12].SENSE register. Write '1' to clear. 12 12 @@ -34739,7 +34985,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN13 - Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. + Status on whether PIN[13] has met criteria set in PIN_CNF[13].SENSE register. Write '1' to clear. 13 13 @@ -34757,7 +35003,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN14 - Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. + Status on whether PIN[14] has met criteria set in PIN_CNF[14].SENSE register. Write '1' to clear. 14 14 @@ -34775,7 +35021,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN15 - Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. + Status on whether PIN[15] has met criteria set in PIN_CNF[15].SENSE register. Write '1' to clear. 15 15 @@ -34793,7 +35039,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN16 - Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. + Status on whether PIN[16] has met criteria set in PIN_CNF[16].SENSE register. Write '1' to clear. 16 16 @@ -34811,7 +35057,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN17 - Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. + Status on whether PIN[17] has met criteria set in PIN_CNF[17].SENSE register. Write '1' to clear. 17 17 @@ -34829,7 +35075,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN18 - Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. + Status on whether PIN[18] has met criteria set in PIN_CNF[18].SENSE register. Write '1' to clear. 18 18 @@ -34847,7 +35093,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN19 - Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. + Status on whether PIN[19] has met criteria set in PIN_CNF[19].SENSE register. Write '1' to clear. 19 19 @@ -34865,7 +35111,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN20 - Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. + Status on whether PIN[20] has met criteria set in PIN_CNF[20].SENSE register. Write '1' to clear. 20 20 @@ -34883,7 +35129,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN21 - Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. + Status on whether PIN[21] has met criteria set in PIN_CNF[21].SENSE register. Write '1' to clear. 21 21 @@ -34901,7 +35147,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN22 - Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. + Status on whether PIN[22] has met criteria set in PIN_CNF[22].SENSE register. Write '1' to clear. 22 22 @@ -34919,7 +35165,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN23 - Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. + Status on whether PIN[23] has met criteria set in PIN_CNF[23].SENSE register. Write '1' to clear. 23 23 @@ -34937,7 +35183,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN24 - Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. + Status on whether PIN[24] has met criteria set in PIN_CNF[24].SENSE register. Write '1' to clear. 24 24 @@ -34955,7 +35201,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN25 - Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. + Status on whether PIN[25] has met criteria set in PIN_CNF[25].SENSE register. Write '1' to clear. 25 25 @@ -34973,7 +35219,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN26 - Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. + Status on whether PIN[26] has met criteria set in PIN_CNF[26].SENSE register. Write '1' to clear. 26 26 @@ -34991,7 +35237,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN27 - Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. + Status on whether PIN[27] has met criteria set in PIN_CNF[27].SENSE register. Write '1' to clear. 27 27 @@ -35009,7 +35255,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN28 - Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. + Status on whether PIN[28] has met criteria set in PIN_CNF[28].SENSE register. Write '1' to clear. 28 28 @@ -35027,7 +35273,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN29 - Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. + Status on whether PIN[29] has met criteria set in PIN_CNF[29].SENSE register. Write '1' to clear. 29 29 @@ -35045,7 +35291,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN30 - Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. + Status on whether PIN[30] has met criteria set in PIN_CNF[30].SENSE register. Write '1' to clear. 30 30 @@ -35063,7 +35309,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PIN31 - Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. + Status on whether PIN[31] has met criteria set in PIN_CNF[31].SENSE register. Write '1' to clear. 31 31