chiptool fmt on changed yamls

Author: Gerzain Mata

data/registers/flash_wba.yaml

@@ -533,6 +533,28 @@ fieldset/SECSR:
     description: "Secure wait data to write\r This bit indicates that the memory write buffer has been written by a secure or non-secure operation. It is set when the first data is stored in the buffer and cleared when the write is performed in the memory."
     bit_offset: 17
     bit_size: 1
+fieldset/SECWM2R1:
+  description: Flash bank 2 secure watermark register 1
+  fields:
+  - name: SECWM2_PSTRT
+    description: "WRP area B start page\r This field contains the first page of the secure area in bank 2."
+    bit_offset: 0
+    bit_size: 7
+  - name: SECWM2_PEND
+    description: "End page of secure area\r This field contains the last page of the secure area in bank 2."
+    bit_offset: 16
+    bit_size: 7
+fieldset/SECWM2R2:
+  description: Flash bank 2 secure watermark register 2
+  fields:
+  - name: HDP2_PEND
+    description: "Bank 2 end page of secure hide protection area\r This field contains the last page of the secure HDP area in bank 2."
+    bit_offset: 16
+    bit_size: 7
+  - name: HDP2EN
+    description: Bank 2 secure Hide protection area enable
+    bit_offset: 31
+    bit_size: 1
 fieldset/SECWMR1:
   description: secure watermark register 1
   fields:
@@ -585,28 +607,6 @@ fieldset/WRP1BR:
     description: WPR area B unlock
     bit_offset: 31
     bit_size: 1
-fieldset/SECWM2R1:
-  description: Flash bank 2 secure watermark register 1
-  fields:
-  - name: SECWM2_PSTRT
-    description: "WRP area B start page\r This field contains the first page of the secure area in bank 2."
-    bit_offset: 0
-    bit_size: 7
-  - name: SECWM2_PEND
-    description: "End page of secure area\r This field contains the last page of the secure area in bank 2."
-    bit_offset: 16
-    bit_size: 7
-fieldset/SECWM2R2:
-  description: Flash bank 2 secure watermark register 2
-  fields:
-  - name: HDP2_PEND
-    description: "Bank 2 end page of secure hide protection area\r This field contains the last page of the secure HDP area in bank 2."
-    bit_offset: 16
-    bit_size: 7
-  - name: HDP2EN
-    description: "Bank 2 secure Hide protection area enable"
-    bit_offset: 31
-    bit_size: 1
 fieldset/WRP2AR:
   description: WRP bank 2 area A address register
   fields:

data/registers/pwr_wba.yaml

@@ -79,6 +79,10 @@ block/PWR:
     description: 2.4 GHz RADIO status and control register
     byte_offset: 256
     fieldset: RADIOSCR
+  - name: S2RETR
+    description: Stop 2 peripheral IOs retention register
+    byte_offset: 260
+    fieldset: S2RETR
 fieldset/CR1:
   description: control register 1
   fields:
@@ -357,6 +361,17 @@ fieldset/WUSR:
     array:
       len: 8
       stride: 1
+fieldset/S2RETR:
+  description: Stop 2 peripheral IOs retention register
+  fields:
+  - name: PTASREN
+    description: "PTA output signals Stop 2 mode retention enable\r Access can be secured by GTZC_TZSC PTACONVSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV."
+    bit_offset: 0
+    bit_size: 1
+  - name: PTASR
+    description: "PTA interface output signals state retnetion in Stop 2 mode active\r Access can be secured by GTZC_TZSC PTACONVSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV."
+    bit_offset: 16
+    bit_size: 1
 enum/ACTVOS:
   bit_size: 1
   variants:

data/registers/rcc_wba.yaml

@@ -184,17 +184,17 @@ block/RCC:
   - name: ASCNTR
     description: RCC audio synchronization counter register
     byte_offset: 460
-    fieldset: ASCNTR
     access: Read
+    fieldset: ASCNTR
   - name: ASARR
     description: RCC audio synchronization auto-reload register
     byte_offset: 464
     fieldset: ASARR
   - name: ASCAR
     description: RCC audio synchronization capture register
     byte_offset: 468
-    fieldset: ASCAR
     access: Read
+    fieldset: ASCAR
   - name: ASCOR
     description: RCC audio synchronization compare register
     byte_offset: 472
@@ -835,6 +835,79 @@ fieldset/APB7SMENR:
     description: "RTC and TAMP APB clock enable during Sleep and Stop modes\r Set and cleared by software.\r Can only be accessed secure when one or more features in the RTC or TAMP is/are secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
     bit_offset: 21
     bit_size: 1
+fieldset/ASARR:
+  description: RCC audio synchronization auto-reload register
+  fields:
+  - name: AR
+    description: "Auto-reload value\r This field is set by software.\r CA[19:0] is the counter auto-reload value at which to restart the audio synchronization counter from value 0. It defines the counter period."
+    bit_offset: 0
+    bit_size: 20
+fieldset/ASCAR:
+  description: RCC audio synchronization capture register
+  fields:
+  - name: CA
+    description: "Capture value\r This field is set by hardware.\r CA[26:20] is the capture period counter value loaded on the trigger event. CA[19:0] is the audio synchronization counter value loaded on the trigger event."
+    bit_offset: 0
+    bit_size: 27
+fieldset/ASCNTR:
+  description: RCC audio synchronization counter register
+  fields:
+  - name: CNT
+    description: "Counter value\r This field is set by hardware.\r CNT[19:0] is the counter value at the time this register is read."
+    bit_offset: 0
+    bit_size: 20
+fieldset/ASCOR:
+  description: RCC audio synchronization compare register
+  fields:
+  - name: CO
+    description: "Compare value\r This field is set by software.\r CO[19:0] is the value to be compared to the audio synchronization counter to generate an compare interrupt event."
+    bit_offset: 0
+    bit_size: 20
+fieldset/ASCR:
+  description: RCC audio synchronization control register
+  fields:
+  - name: CEN
+    description: "Counter enable\r This bit is set and cleared by software.\r Clearing this bit will reset the audio synchronization counter and capture prescaler and all associated registers ASCR, ASIER, ASSR, ASCNTR, ASARR, ASCAR, and ASCOR."
+    bit_offset: 0
+    bit_size: 1
+  - name: PSC
+    description: "Clock prescaler\r This field is set and cleared by software.\r Counter clock frequency = f_audiosync_ker_ck / (PSC + 1)"
+    bit_offset: 8
+    bit_size: 7
+  - name: CPS
+    description: "Capture prescaler\r This field is set and cleared by software.\r Capture period in number of counter periods. Capture period = counter period * (TPS + 1)"
+    bit_offset: 16
+    bit_size: 7
+fieldset/ASIER:
+  description: RCC audio synchronization interrupt enable register
+  fields:
+  - name: CAIE
+    description: "Capture trigger interrupt enable\r This bit is set and cleared by software."
+    bit_offset: 0
+    bit_size: 1
+  - name: COIE
+    description: "Comparer interrupt enable\r This field is set and cleared by software."
+    bit_offset: 1
+    bit_size: 1
+  - name: CAEIE
+    description: "Capture error interrupt enable\r This field is set and cleared by software."
+    bit_offset: 2
+    bit_size: 1
+fieldset/ASSR:
+  description: RCC audio synchronization status register
+  fields:
+  - name: CAF
+    description: "Capture trigger interrupt flag\r This field is set by hardware, only when CAIE is enabled. This bit is cleared by software by writing it to 0 or masked when CAIE is 0."
+    bit_offset: 0
+    bit_size: 1
+  - name: COF
+    description: "Comparer interrupt flag\r This field is set by hardware, only when COIE is enabled. This bit is cleared by software by writing it to 0 or masked when COIE is 0."
+    bit_offset: 1
+    bit_size: 1
+  - name: CAEF
+    description: "Capture error interrupt flag\r This field is set by hardware, only when CAEIE is enabled. This bit is cleared by software by writing it to 0 or masked when CAEIE is 0."
+    bit_offset: 2
+    bit_size: 1
 fieldset/BDCR:
   description: RCC backup domain control register
   fields:
@@ -1391,79 +1464,6 @@ fieldset/SECCFGR:
     description: "Remove reset flag security\r Set and reset by software."
     bit_offset: 12
     bit_size: 1
-fieldset/ASCR:
-  description: RCC audio synchronization control register
-  fields:
-  - name: CEN
-    description: "Counter enable\r This bit is set and cleared by software.\r Clearing this bit will reset the audio synchronization counter and capture prescaler and all associated registers ASCR, ASIER, ASSR, ASCNTR, ASARR, ASCAR, and ASCOR."
-    bit_offset: 0
-    bit_size: 1
-  - name: PSC
-    description: "Clock prescaler\r This field is set and cleared by software.\r Counter clock frequency = f_audiosync_ker_ck / (PSC + 1)"
-    bit_offset: 8
-    bit_size: 7
-  - name: CPS
-    description: "Capture prescaler\r This field is set and cleared by software.\r Capture period in number of counter periods. Capture period = counter period * (TPS + 1)"
-    bit_offset: 16
-    bit_size: 7
-fieldset/ASIER:
-  description: RCC audio synchronization interrupt enable register
-  fields:
-  - name: CAIE
-    description: "Capture trigger interrupt enable\r This bit is set and cleared by software."
-    bit_offset: 0
-    bit_size: 1
-  - name: COIE
-    description: "Comparer interrupt enable\r This field is set and cleared by software."
-    bit_offset: 1
-    bit_size: 1
-  - name: CAEIE
-    description: "Capture error interrupt enable\r This field is set and cleared by software."
-    bit_offset: 2
-    bit_size: 1
-fieldset/ASSR:
-  description: RCC audio synchronization status register
-  fields:
-  - name: CAF
-    description: "Capture trigger interrupt flag\r This field is set by hardware, only when CAIE is enabled. This bit is cleared by software by writing it to 0 or masked when CAIE is 0."
-    bit_offset: 0
-    bit_size: 1
-  - name: COF
-    description: "Comparer interrupt flag\r This field is set by hardware, only when COIE is enabled. This bit is cleared by software by writing it to 0 or masked when COIE is 0."
-    bit_offset: 1
-    bit_size: 1
-  - name: CAEF
-    description: "Capture error interrupt flag\r This field is set by hardware, only when CAEIE is enabled. This bit is cleared by software by writing it to 0 or masked when CAEIE is 0."
-    bit_offset: 2
-    bit_size: 1
-fieldset/ASCNTR:
-  description: RCC audio synchronization counter register
-  fields:
-  - name: CNT
-    description: "Counter value\r This field is set by hardware.\r CNT[19:0] is the counter value at the time this register is read."
-    bit_offset: 0
-    bit_size: 20
-fieldset/ASARR:
-  description: RCC audio synchronization auto-reload register
-  fields:
-  - name: AR
-    description: "Auto-reload value\r This field is set by software.\r CA[19:0] is the counter auto-reload value at which to restart the audio synchronization counter from value 0. It defines the counter period."
-    bit_offset: 0
-    bit_size: 20
-fieldset/ASCAR:
-  description: RCC audio synchronization capture register
-  fields:
-  - name: CA
-    description: "Capture value\r This field is set by hardware.\r CA[26:20] is the capture period counter value loaded on the trigger event. CA[19:0] is the audio synchronization counter value loaded on the trigger event."
-    bit_offset: 0
-    bit_size: 27
-fieldset/ASCOR:
-  description: RCC audio synchronization compare register
-  fields:
-  - name: CO
-    description: "Compare value\r This field is set by software.\r CO[19:0] is the value to be compared to the audio synchronization counter to generate an compare interrupt event."
-    bit_offset: 0
-    bit_size: 20
 enum/ADCSEL:
   bit_size: 3
   variants:
@@ -1482,6 +1482,15 @@ enum/ADCSEL:
   - name: HSI
     description: HSI clock selected
     value: 4
+enum/ASSEL:
+  bit_size: 1
+  variants:
+  - name: PLL1_P
+    description: pll1pclk selected.
+    value: 0
+  - name: PLL1_Q
+    description: pll1qclk selected.
+    value: 1
 enum/HDIV5:
   bit_size: 1
   variants:
@@ -1704,6 +1713,21 @@ enum/MCOSEL:
   - name: HCLK5
     description: hclk5 clock selected
     value: 10
+enum/OTGHSSEL:
+  bit_size: 2
+  variants:
+  - name: HSE
+    description: HSE32 selected.
+    value: 0
+  - name: PLL1_P
+    description: pll1pclk selected,.
+    value: 1
+  - name: HSE_DIV_2
+    description: HSE32 divided by 2 selected.
+    value: 2
+  - name: PLL1_P_DIV_2
+    description: pll1pclk divided by 2 selected.
+    value: 3
 enum/PLLRCLKPRE:
   bit_size: 1
   variants:
@@ -1806,20 +1830,20 @@ enum/RTCSEL:
 enum/SAI1SEL:
   bit_size: 3
   variants:
-  - description: pll1pclk selected.
-    name: PLL1_P
+  - name: PLL1_P
+    description: pll1pclk selected.
     value: 0
-  - description: pll1qclk selected.
-    name: PLL1_Q
+  - name: PLL1_Q
+    description: pll1qclk selected.
     value: 1
-  - description: SYSCLK selected.
-    name: SYS
+  - name: SYS
+    description: SYSCLK selected.
     value: 2
-  - description: input pin AUDIOCLK selected.
-    name: AUDIOCLK
+  - name: AUDIOCLK
+    description: input pin AUDIOCLK selected.
     value: 3
-  - description: HSI16 clock selected.
-    name: HSI
+  - name: HSI
+    description: HSI16 clock selected.
     value: 4
 enum/SPI1SEL:
   bit_size: 2
@@ -1920,27 +1944,3 @@ enum/USARTSEL:
   - name: LSE
     description: LSE selected
     value: 3
-enum/ASSEL:
-  bit_size: 1
-  variants:
-  - description: pll1pclk selected.
-    name: PLL1_P
-    value: 0
-  - description: pll1qclk selected.
-    name: PLL1_Q
-    value: 1
-enum/OTGHSSEL:
-  bit_size: 2
-  variants:
-  - description: HSE32 selected.
-    name: HSE
-    value: 0
-  - description: pll1pclk selected,.
-    name: PLL1_P
-    value: 1
-  - description: HSE32 divided by 2 selected.
-    name: HSE_DIV_2
-    value: 2
-  - description: pll1pclk divided by 2 selected.
-    name: PLL1_P_DIV_2
-    value: 3