Merge pull request #601 from embassy-rs/updat-esources

Update stm32-data-sources.

Author: Dirbaio

d

@@ -4,7 +4,7 @@ set -e
 cd $(dirname $0)
 
 CMD=$1
-REV=709c1060ac2ec57f6042f2b4eb9cf8c1821a6c57
+REV=1659e761beb29d3949bd1ec72039c3ce5f6bdf6c
 shift
 
 case "$CMD" in

stm32-data-gen/src/chips.rs

@@ -210,19 +210,29 @@ pub fn parse_groups() -> Result<(HashMap<String, Chip>, Vec<ChipGroup>), anyhow:
     Ok((chips, chip_groups))
 }
 
-static NOPELIST: &[&str] = &[
+static NOPELIST: RegexMap<()> = RegexMap::new(&[
     // Not supported, not planned unless someone wants to do it.
-    "STM32MP",
+    ("STM32MP.*", ()),
+    // TODO, PRs welcome :)
+    ("STM32C0[579].*", ()),
+    ("STM32U3.*", ()),
+    ("STM32N6.*", ()),
+    ("STM32G41[14].*", ()),
+    ("STM32G4.*xZ", ()),
+    ("STM32WBA6.*", ()),
+    ("STM32WB0.*", ()),
+    ("STM32WL3.*", ()),
     // Does not exist in ST website. No datasheet, no RM.
-    "STM32GBK",
-    "STM32L485",
+    ("STM32GBK.*", ()),
+    ("STM32L485.*", ()),
     // STM32WxM modules. These are based on a chip that's supported on its own,
     // not sure why we want a separate target for it.
-    "STM32WL5M",
-    "STM32WB1M",
-    "STM32WB3M",
-    "STM32WB5M",
-];
+    ("STM32WL5M.*", ()),
+    ("STM32WB1M.*", ()),
+    ("STM32WB3M.*", ()),
+    ("STM32WB5M.*", ()),
+    ("STM32WBA5M.*", ()),
+]);
 
 fn parse_group(
     f: std::path::PathBuf,
@@ -231,10 +241,8 @@ fn parse_group(
 ) -> anyhow::Result<()> {
     let ff = f.file_name().unwrap().to_string_lossy();
 
-    for nope in NOPELIST {
-        if ff.contains(nope) {
-            return Ok(());
-        }
+    if NOPELIST.get(ff.split('.').next().unwrap()).is_some() {
+        return Ok(());
     }
 
     let parsed: xml::Mcu = quick_xml::de::from_str(&std::fs::read_to_string(f)?)?;
@@ -294,6 +302,7 @@ fn parse_group(
     let mut package_pins: Vec<stm32_data_serde::chip::PackagePin> = package_pins
         .into_iter()
         .map(|(position, mut signals)| {
+            signals.retain(|s| s != "NC");
             signals.sort();
             stm32_data_serde::chip::PackagePin { position, signals }
         })

stm32-data-gen/src/interrupts.rs

@@ -343,7 +343,9 @@ impl ChipInterrupts {
 
                     for s in ss {
                         if !known.contains(&s.clone()) {
-                            panic!("Unknown signal {s} for peri {p}, known={known:?}, parts={parts:?}");
+                            panic!(
+                                "Unknown signal {s} for peri {p} chip {chip_name}, known={known:?}, parts={parts:?}"
+                            );
                         }
                         trace!("    signal: {} {}", p, s);
                         interrupt_signals.insert((p.clone(), s));
@@ -496,7 +498,7 @@ fn valid_signals(peri: &str) -> Vec<String> {
             &["FLT0", "FLT1", "FLT2", "FLT3", "FLT4", "FLT5", "FLT6", "FLT7"],
         ),
         ("MDF", &["FLT0", "FLT1", "FLT2", "FLT3", "FLT4", "FLT5", "FLT6", "FLT7"]),
-        ("PWR", &["S3WU", "WKUP"]),
+        ("PWR", &["S3WU", "WKUP", "PVD"]),
         ("GTZC", &["GLOBAL", "ILA"]),
         ("WWDG", &["GLOBAL", "RST"]),
         ("USB_OTG_FS", &["GLOBAL", "EP1_OUT", "EP1_IN", "WKUP"]),
@@ -505,6 +507,7 @@ fn valid_signals(peri: &str) -> Vec<String> {
         ("GPU2D", &["ER"]),
         ("SAI", &["A", "B"]),
         ("ADF", &["FLT0"]),
+        ("RAMECC", &["ECC"]),
     ];
 
     for (prefix, signals) in IRQ_SIGNALS_MAP {

stm32-data-gen/src/perimap.rs

@@ -88,7 +88,7 @@ pub static PERIMAP: RegexMap<(&str, &str, &str)> = RegexMap::new(&[
     (".*:DAC:dacif_v3_0", ("dac", "v4", "DAC")),
     (".*:DAC:WL_dacif_v3_0", ("dac", "v4", "DAC")),
     (".*:DAC:G4_dacif_v4_0", ("dac", "v7", "DAC")),
-    (".*:DAC:dacif_v5_0", ("dac", "v6", "DAC")),
+    (".*:DAC:dacif_v5_0.*", ("dac", "v6", "DAC")),
     (".*:ADC:aditf_v2_5F1", ("adc", "f1", "ADC")),
     (".*:ADC:aditf5_v1_1", ("adc", "f3", "ADC")),
     (".*:ADC:aditf_v2_5", ("adc", "f3_v2", "ADC")),
@@ -294,8 +294,8 @@ pub static PERIMAP: RegexMap<(&str, &str, &str)> = RegexMap::new(&[
     ("STM32H5.*:CRS:.*", ("crs", "v1", "CRS")),
     ("STM32H7.*:CRS:.*", ("crs", "v1", "CRS")),
     ("STM32WB.*:CRS:.*", ("crs", "v1", "CRS")),
-    (".*SDMMC:sdmmc2_v1_0", ("sdmmc", "v2", "SDMMC")),
-    (".*SDMMC:sdmmc2_v2_1", ("sdmmc", "v2", "SDMMC")),
+    (".*SDMMC:sdmmc2_v1_0.*", ("sdmmc", "v2", "SDMMC")),
+    (".*SDMMC:sdmmc2_v2_1.*", ("sdmmc", "v2", "SDMMC")),
     ("STM32C0.*:PWR:.*", ("pwr", "c0", "PWR")),
     ("STM32G0.*:PWR:.*", ("pwr", "g0", "PWR")),
     ("STM32G4.*:PWR:.*", ("pwr", "g4", "PWR")),