Merge pull request #610 from diorcety/stm32wle_mux

Add RCC_CCIPR enums for STM32WLE chips

Author: Dirbaio

data/registers/rcc_wle.yaml

@@ -650,42 +650,52 @@ fieldset/CCIPR:
     description: USART1 clock source selection
     bit_offset: 0
     bit_size: 2
+    enum: USART1SEL
   - name: USART2SEL
     description: USART2 clock source selection
     bit_offset: 2
     bit_size: 2
-  - name: SPI2SEL
+    enum: USART2SEL
+  - name: SPI2S2SEL
     description: SPI2 I2S clock source selection
     bit_offset: 8
     bit_size: 2
+    enum: SPI2S2SEL
   - name: LPUART1SEL
     description: LPUART1 clock source selection
     bit_offset: 10
     bit_size: 2
+    enum: LPUART1SEL
   - name: I2C1SEL
     description: I2C1 clock source selection
     bit_offset: 12
     bit_size: 2
+    enum: I2C1SEL
   - name: I2C2SEL
     description: I2C2 clock source selection
     bit_offset: 14
     bit_size: 2
+    enum: I2C2SEL
   - name: I2C3SEL
     description: I2C3 clock source selection
     bit_offset: 16
     bit_size: 2
+    enum: I2C3SEL
   - name: LPTIM1SEL
     description: Low power timer 1 clock source selection
     bit_offset: 18
     bit_size: 2
+    enum: LPTIM1SEL
   - name: LPTIM2SEL
     description: Low power timer 2 clock source selection
     bit_offset: 20
     bit_size: 2
+    enum: LPTIM2SEL
   - name: LPTIM3SEL
     description: Low power timer 3 clock source selection
     bit_offset: 22
     bit_size: 2
+    enum: LPTIM3SEL
   - name: ADCSEL
     description: ADC clock source selection
     bit_offset: 28
@@ -1067,6 +1077,9 @@ fieldset/PLLCFGR:
 enum/ADCSEL:
   bit_size: 2
   variants:
+  - name: DISABLE
+    description: No clock selected
+    value: 0
   - name: HSI
     description: HSI used as ADC clock source
     value: 1
@@ -1638,12 +1651,124 @@ enum/RNGSEL:
   bit_size: 2
   variants:
   - name: PLL1_Q
+    description: PLL "Q" clock selected
     value: 0
   - name: LSI
+    description: LSI clock selected
     value: 1
   - name: LSE
+    description: LSE clock selected
     value: 2
   - name: MSI
+    description: MSI clock selected
+    value: 3
+enum/LPTIM3SEL:
+  bit_size: 2
+  variants:
+  - name: PCLK1
+    description: APB clock selected
+    value: 0
+  - name: LSI
+    description: LSI clock selected
+    value: 1
+  - name: HSI
+    description: HSI16 clock selected
+    value: 2
+  - name: LSE
+    description: LSE clock selected
+    value: 3
+enum/LPTIM2SEL:
+  bit_size: 2
+  variants:
+  - name: PCLK1
+    description: APB clock selected
+    value: 0
+  - name: LSI
+    description: LSI clock selected
+    value: 1
+  - name: HSI
+    description: HSI16 clock selected
+    value: 2
+  - name: LSE
+    description: LSE clock selected
+    value: 3
+enum/LPTIM1SEL:
+  bit_size: 2
+  variants:
+  - name: PCLK1
+    description: APB clock selected
+    value: 0
+  - name: LSI
+    description: LSI clock selected
+    value: 1
+  - name: HSI
+    description: HSI16 clock selected
+    value: 2
+  - name: LSE
+    description: LSE clock selected
+    value: 3
+enum/I2C3SEL:
+  bit_size: 2
+  variants:
+  - name: PCLK1
+    description: APB clock selected
+    value: 0
+  - name: SYS
+    description: System clock selected
+    value: 1
+  - name: HSI
+    description: HSI16 clock selected
+    value: 2
+enum/I2C2SEL:
+  bit_size: 2
+  variants:
+  - name: PCLK1
+    description: APB clock selected
+    value: 0
+  - name: SYS
+    description: System clock selected
+    value: 1
+  - name: HSI
+    description: HSI16 clock selected
+    value: 2
+enum/I2C1SEL:
+  bit_size: 2
+  variants:
+  - name: PCLK1
+    description: APB clock selected
+    value: 0
+  - name: SYS
+    description: System clock selected
+    value: 1
+  - name: HSI
+    description: HSI16 clock selected
+    value: 2
+enum/LPUART1SEL:
+  bit_size: 2
+  variants:
+  - name: PCLK1
+    description: APB clock selected
+    value: 0
+  - name: SYS
+    description: System clock selected
+    value: 1
+  - name: HSI
+    description: HSI16 clock selected
+    value: 2
+  - name: LSE
+    description: LSE clock selected
+    value: 3
+enum/SPI2S2SEL:
+  bit_size: 2
+  variants:
+  - name: PLL1_Q
+    description: PLL "Q" clock selected
+    value: 1
+  - name: HSI
+    description: HSI16 clock selected
+    value: 2
+  - name: I2S_CKIN
+    description: External input I2S_CKIN selected
     value: 3
 enum/RTCSEL:
   bit_size: 2
@@ -1660,6 +1785,36 @@ enum/RTCSEL:
   - name: HSE
     description: HSE oscillator clock divided by 32 selected
     value: 3
+enum/USART2SEL:
+  bit_size: 2
+  variants:
+  - name: PCLK1
+    description: APB clock selected
+    value: 0
+  - name: SYS
+    description: System clock selected
+    value: 1
+  - name: HSI
+    description: HSI16 clock selected
+    value: 2
+  - name: LSE
+    description: LSE clock selected
+    value: 3
+enum/USART1SEL:
+  bit_size: 2
+  variants:
+  - name: PCLK2
+    description: APB clock selected
+    value: 0
+  - name: SYS
+    description: System clock selected
+    value: 1
+  - name: HSI
+    description: HSI16 clock selected
+    value: 2
+  - name: LSE
+    description: LSE clock selected
+    value: 3
 enum/SW:
   bit_size: 2
   variants: