fix: STM32F4 RCC naming for SPDIFRX enable/reset

Author: elagil

data/registers/rcc_f4.yaml

@@ -567,8 +567,8 @@ fieldset/APB1ENR:
     description: SPI3 clock enable
     bit_offset: 15
     bit_size: 1
-  - name: SPDIFEN
-    description: SPDIF-IN clock enable
+  - name: SPDIFRXEN
+    description: SPDIF-Rx clock enable
     bit_offset: 16
     bit_size: 1
   - name: USART2EN
@@ -817,8 +817,8 @@ fieldset/APB1RSTR:
     description: SPI 3 reset
     bit_offset: 15
     bit_size: 1
-  - name: SPDIFRST
-    description: SPDIF-IN reset
+  - name: SPDIFRXRST
+    description: SPDIF-Rx reset
     bit_offset: 16
     bit_size: 1
   - name: USART2RST