Merge pull request #604 from skoe/split_chips_to_chips_and_generator

Split chips to chips and generator, refactoring

Author: Dirbaio

.vscode/settings.json

@@ -12,4 +12,7 @@
   "[cpp]": {
     "editor.formatOnSave": false
   },
+  "editor.rulers": [
+    120
+  ],
 }

README.md

@@ -117,7 +117,7 @@ This project is built in three stages:
      6. Parse RCC registers for clock/reset settings (`src/rcc.rs`).
      7. Parse interrupts to map NVIC lines (`src/interrupts.rs`).
      8. Group all packages of a chip into `ChipGroup` structures (`src/chips.rs`).
-     9. Use the parsed data to dump one JSON per MCU into `build/data/chips/*.json` (in `process_chip` of `src/chips.rs`).
+     9. Use the parsed data to dump one JSON per MCU into `build/data/chips/*.json` (in `process_chip` of `src/generator.rs`).
 
 3. **PAC Generation**
    - `stm32-metapac-gen` consumes the JSON files and generates the PAC crate:

stm32-data-gen/src/check.rs

@@ -9,7 +9,7 @@ pub fn check(chip: &Chip) {
         for ch in &core.dma_channels {
             let dma = peris.get(&ch.dma).unwrap();
             let signal = ch.name.strip_prefix(&format!("{}_", dma.name)).unwrap();
-            if dma.interrupts.iter().find(|i| i.signal == signal).is_none() {
+            if !dma.interrupts.iter().any(|i| i.signal == signal) {
                 panic!("{}: missing irq for ch {}", chip.name, ch.name);
             }
         }