|
34 | 34 | #endif |
35 | 35 |
|
36 | 36 | #ifndef EMSESP_STANDALONE |
37 | | -#ifdef ESP_IDF_VERSION_MAJOR // IDF 4+ |
38 | | -#if CONFIG_IDF_TARGET_ESP32 // ESP32/PICO-D4 |
39 | | -#include "../esp32/rom/rtc.h" |
40 | | -#elif CONFIG_IDF_TARGET_ESP32S2 |
41 | | -#include "../esp32s2/rom/rtc.h" |
42 | | -#elif CONFIG_IDF_TARGET_ESP32C3 |
43 | | -#include "../esp32c3/rom/rtc.h" |
44 | | -#elif CONFIG_IDF_TARGET_ESP32S3 |
45 | | -#include "../esp32s3/rom/rtc.h" |
46 | | -#else |
47 | | -#error Target CONFIG_IDF_TARGET is not supported |
48 | | -#endif |
49 | | -#else // ESP32 Before IDF 4.0 |
50 | | -#include "../rom/rtc.h" |
51 | | -#endif |
52 | 37 | #include <esp_mac.h> |
53 | | -#endif |
54 | | - |
55 | | -#ifndef EMSESP_STANDALONE |
56 | 38 | #include "esp_efuse.h" |
57 | 39 | #endif |
58 | 40 |
|
@@ -2534,37 +2516,38 @@ bool System::command_restart(const char * value, const int8_t id) { |
2534 | 2516 |
|
2535 | 2517 | std::string System::reset_reason(uint8_t cpu) const { |
2536 | 2518 | #ifndef EMSESP_STANDALONE |
2537 | | - switch (rtc_get_reset_reason(cpu)) { |
2538 | | - case 1: |
| 2519 | + switch (esp_rom_get_reset_reason(cpu)) { |
| 2520 | + case RESET_REASON_CHIP_POWER_ON: |
2539 | 2521 | return ("Power on reset"); |
2540 | | - // case 2 :reset pin not on esp32 |
2541 | | - case 3: |
| 2522 | + case 2: // not on esp32 |
| 2523 | + return ("reset pin"); |
| 2524 | + case RESET_REASON_CORE_SW: |
2542 | 2525 | return ("Software reset"); |
2543 | 2526 | case 4: // not on S2, C3 |
2544 | 2527 | return ("Legacy watch dog reset"); |
2545 | | - case 5: |
| 2528 | + case RESET_REASON_CORE_DEEP_SLEEP: |
2546 | 2529 | return ("Deep sleep reset"); |
2547 | | - case 6: // not on S2, C3 |
2548 | | - return ("Reset by SDIO"); |
2549 | | - case 7: |
| 2530 | + case 6: // RESET_REASON_CORE_SDIO: // not on S2, S3, C3 |
| 2531 | + return ("Reset by SDIO"); |
| 2532 | + case RESET_REASON_CORE_MWDT0: |
2550 | 2533 | return ("Timer group0 watch dog reset"); |
2551 | | - case 8: |
| 2534 | + case RESET_REASON_CORE_MWDT1: |
2552 | 2535 | return ("Timer group1 watch dog reset"); |
2553 | | - case 9: |
| 2536 | + case RESET_REASON_CORE_RTC_WDT: |
2554 | 2537 | return ("RTC watch dog reset"); |
2555 | 2538 | case 10: |
2556 | 2539 | return ("Intrusion reset CPU"); |
2557 | | - case 11: |
| 2540 | + case RESET_REASON_CPU0_MWDT0: |
2558 | 2541 | return ("Timer group reset CPU"); |
2559 | | - case 12: |
| 2542 | + case RESET_REASON_CPU0_SW: |
2560 | 2543 | return ("Software reset CPU"); |
2561 | | - case 13: |
| 2544 | + case RESET_REASON_CPU0_RTC_WDT: |
2562 | 2545 | return ("RTC watch dog reset: CPU"); |
2563 | | - case 14: // not on S2, C3 |
| 2546 | + case 14: // RESET_REASON_CPU1_CPU0: // not on S2, S3, C3 |
2564 | 2547 | return ("APP CPU reset by PRO CPU"); |
2565 | | - case 15: |
| 2548 | + case RESET_REASON_SYS_BROWN_OUT: |
2566 | 2549 | return ("Brownout reset"); |
2567 | | - case 16: |
| 2550 | + case RESET_REASON_SYS_RTC_WDT: |
2568 | 2551 | return ("RTC watch dog reset: CPU+RTC"); |
2569 | 2552 | default: |
2570 | 2553 | break; |
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