OPCODE_DATA too

Author: ethteck

objdiff-core/src/arch/arm.rs

@@ -11,7 +11,7 @@ use object::{Endian as _, Object as _, ObjectSection as _, ObjectSymbol as _, el
 use unarm::{args, arm, thumb};
 
 use crate::{
-    arch::{Arch, OPCODE_INVALID, RelocationOverride, RelocationOverrideTarget},
+    arch::{Arch, OPCODE_DATA, OPCODE_INVALID, RelocationOverride, RelocationOverrideTarget},
     diff::{ArmArchVersion, ArmR9Usage, DiffObjConfig, display::InstructionPart},
     obj::{
         InstructionRef, Relocation, RelocationFlags, ResolvedInstructionRef, ResolvedRelocation,
@@ -164,7 +164,7 @@ impl ArchArm {
             }
             _ => bail!("Invalid instruction size {}", ins_ref.size),
         };
-        let (ins, parsed_ins) = if ins_ref.opcode == OPCODE_INVALID {
+        let (ins, parsed_ins) = if ins_ref.opcode == OPCODE_DATA {
             let mut args = args::Arguments::default();
             args[0] = args::Argument::UImm(code);
             let mnemonic = if ins_ref.size == 4 { ".word" } else { ".hword" };
@@ -238,7 +238,7 @@ impl Arch for ArchArm {
                 ops.push(InstructionRef {
                     address: address as u64,
                     size: data.len() as u8,
-                    opcode: OPCODE_INVALID,
+                    opcode: OPCODE_DATA,
                     branch_dest: None,
                 });
                 break;
@@ -318,7 +318,7 @@ impl Arch for ArchArm {
                     };
                     (opcode, branch_dest)
                 }
-                unarm::ParseMode::Data => (OPCODE_INVALID, None),
+                unarm::ParseMode::Data => (OPCODE_DATA, None),
             };
 
             ops.push(InstructionRef {

objdiff-core/src/arch/mod.rs

@@ -41,7 +41,8 @@ pub mod superh;
 #[cfg(feature = "x86")]
 pub mod x86;
 
-pub const OPCODE_INVALID: u16 = u16::MAX - 1;
+pub const OPCODE_INVALID: u16 = u16::MAX;
+pub const OPCODE_DATA: u16 = u16::MAX - 1;
 
 /// Represents the type of data associated with an instruction
 #[derive(PartialEq)]

objdiff-core/src/arch/x86.rs

@@ -9,7 +9,7 @@ use iced_x86::{
 use object::{Endian as _, Object as _, ObjectSection as _, elf, pe};
 
 use crate::{
-    arch::{Arch, OPCODE_INVALID, RelocationOverride, RelocationOverrideTarget},
+    arch::{Arch, OPCODE_DATA, RelocationOverride, RelocationOverrideTarget},
     diff::{DiffObjConfig, X86Formatter, display::InstructionPart},
     obj::{InstructionRef, Relocation, RelocationFlags, ResolvedInstructionRef, Section, Symbol},
 };
@@ -119,7 +119,7 @@ impl Arch for ArchX86 {
                             out.push(InstructionRef {
                                 address,
                                 size: size as u8,
-                                opcode: OPCODE_INVALID,
+                                opcode: OPCODE_DATA,
                                 branch_dest: None,
                             });
 
@@ -146,7 +146,7 @@ impl Arch for ArchX86 {
                                     out.push(InstructionRef {
                                         address: indirect_array_address + i as u64,
                                         size: 1,
-                                        opcode: OPCODE_INVALID,
+                                        opcode: OPCODE_DATA,
                                         branch_dest: None,
                                     });
                                 }
@@ -185,14 +185,14 @@ impl Arch for ArchX86 {
         diff_config: &DiffObjConfig,
         cb: &mut dyn FnMut(InstructionPart) -> Result<()>,
     ) -> Result<()> {
-        if resolved.ins_ref.opcode == OPCODE_INVALID {
+        if resolved.ins_ref.opcode == OPCODE_DATA {
             let (mnemonic, imm) = match resolved.ins_ref.size {
                 1 => (".byte", resolved.code[0] as u64),
                 2 => (".word", self.endianness.read_u16_bytes(resolved.code.try_into()?) as u64),
                 4 => (".dword", self.endianness.read_u32_bytes(resolved.code.try_into()?) as u64),
                 _ => bail!("Unsupported x86 inline data size {}", resolved.ins_ref.size),
             };
-            cb(InstructionPart::opcode(mnemonic, OPCODE_INVALID))?;
+            cb(InstructionPart::opcode(mnemonic, OPCODE_DATA))?;
             if resolved.relocation.is_some() {
                 cb(InstructionPart::reloc())?;
             } else {
@@ -834,7 +834,7 @@ mod test {
                 ins_ref: InstructionRef {
                     address: 0x1234,
                     size: 1,
-                    opcode: OPCODE_INVALID,
+                    opcode: OPCODE_DATA,
                     branch_dest: None,
                 },
                 code: &code,
@@ -848,7 +848,7 @@ mod test {
         )
         .unwrap();
         assert_eq!(parts, &[
-            InstructionPart::opcode(".byte", OPCODE_INVALID),
+            InstructionPart::opcode(".byte", OPCODE_DATA),
             InstructionPart::unsigned(0xABu64),
         ]);
     }