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Remove std use from ppc flow analysis
1 parent fcbe72b commit f37fab5

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4 files changed

+28
-22
lines changed

4 files changed

+28
-22
lines changed

objdiff-core/src/arch/ppc/flow_analysis.rs

Lines changed: 9 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -5,9 +5,9 @@ use crate::{
55
};
66
use itertools::Itertools;
77
use ppc750cl::Simm;
8-
use std::collections::BTreeMap;
9-
use std::ffi::CStr;
10-
use std::ops::{Index, IndexMut};
8+
use alloc::collections::{BTreeMap, BTreeSet};
9+
use core::ffi::CStr;
10+
use core::ops::{Index, IndexMut};
1111

1212
fn is_store_instruction(op: ppc750cl::Opcode) -> bool {
1313
use ppc750cl::Opcode;
@@ -59,7 +59,7 @@ pub fn guess_data_type_from_load_store_inst_op(inst_op: ppc750cl::Opcode) -> Opt
5959
}
6060
}
6161

62-
#[derive(Default, PartialEq, Eq, Copy, Hash, Clone, Debug)]
62+
#[derive(Default, PartialEq, Eq, Copy, Clone, Debug, PartialOrd, Ord)]
6363
enum RegisterContent {
6464
#[default]
6565
Unknown,
@@ -71,8 +71,8 @@ enum RegisterContent {
7171
Symbol(usize),
7272
}
7373

74-
impl std::fmt::Display for RegisterContent {
75-
fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
74+
impl core::fmt::Display for RegisterContent {
75+
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
7676
match self {
7777
RegisterContent::Unknown => write!(f, "unknown"),
7878
RegisterContent::Variable => write!(f, "variable"),
@@ -93,7 +93,7 @@ impl std::fmt::Display for RegisterContent {
9393
}
9494
}
9595

96-
#[derive(Clone, PartialEq, Eq, Hash)]
96+
#[derive(Clone, PartialEq, Eq, Ord, PartialOrd)]
9797
struct RegisterState {
9898
gpr: [RegisterContent; 32],
9999
fpr: [RegisterContent; 32],
@@ -380,8 +380,7 @@ pub fn ppc_data_flow_analysis(
380380
relocations: &[Relocation],
381381
) -> Box<dyn FlowAnalysisResult> {
382382
use ppc750cl::InsIter;
383-
use std::collections::HashSet;
384-
use std::collections::VecDeque;
383+
use alloc::collections::VecDeque;
385384
let instructions = InsIter::new(code, func_symbol.address as u32)
386385
.map(|(_addr, ins)| (ins.op, ins.basic().args))
387386
.collect_vec();
@@ -397,7 +396,7 @@ pub fn ppc_data_flow_analysis(
397396

398397
// Execute the instructions against abstract data
399398
let mut failsafe_counter = 0;
400-
let mut taken_branches = HashSet::<(usize, RegisterState)>::new();
399+
let mut taken_branches = BTreeSet::<(usize, RegisterState)>::new();
401400
let mut register_state_at = Vec::<RegisterState>::new();
402401
let mut completed_first_pass = false;
403402
register_state_at.resize_with(instructions.len(), RegisterState::new);

objdiff-core/src/arch/ppc/mod.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -662,7 +662,7 @@ fn make_fake_pool_reloc(
662662
// and returns a Vec of "fake pool relocations" that simulate what a relocation for that instruction
663663
// would look like if data hadn't been pooled.
664664
// This method tries to follow the function's proper control flow. It keeps track of a queue of
665-
// states it hasn't traversed yet, where each state holds an instruction address and a HashMap of
665+
// states it hasn't traversed yet, where each state holds an instruction address and a map of
666666
// which registers hold which pool relocations at that point.
667667
// When a conditional or unconditional branch is encountered, the destination of the branch is added
668668
// to the queue. Conditional branches will traverse both the path where the branch is taken and the

objdiff-core/src/obj/mod.rs

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,6 @@ use core::{
1313
fmt,
1414
num::{NonZeroU32, NonZeroU64},
1515
};
16-
use std::collections::HashMap;
1716

1817
use flagset::{FlagSet, flags};
1918

@@ -270,7 +269,7 @@ pub struct Object {
270269
pub path: Option<std::path::PathBuf>,
271270
#[cfg(feature = "std")]
272271
pub timestamp: Option<filetime::FileTime>,
273-
pub flow_analysis_results: HashMap<u64, Box<dyn FlowAnalysisResult>>,
272+
pub flow_analysis_results: BTreeMap<u64, Box<dyn FlowAnalysisResult>>,
274273
}
275274

276275
impl Default for Object {
@@ -285,7 +284,7 @@ impl Default for Object {
285284
path: None,
286285
#[cfg(feature = "std")]
287286
timestamp: None,
288-
flow_analysis_results: HashMap::<u64, Box<dyn FlowAnalysisResult>>::new(),
287+
flow_analysis_results: BTreeMap::<u64, Box<dyn FlowAnalysisResult>>::new(),
289288
}
290289
}
291290
}

objdiff-core/src/util.rs

Lines changed: 16 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -5,8 +5,6 @@ use anyhow::{Result, ensure};
55
use num_traits::PrimInt;
66
use object::{Endian, Object};
77

8-
use std::hash::{Hash, Hasher};
9-
108
// https://stackoverflow.com/questions/44711012/how-do-i-format-a-signed-integer-to-a-sign-aware-hexadecimal-representation
119
pub struct ReallySigned<N: PrimInt>(pub N);
1210

@@ -72,9 +70,14 @@ impl PartialEq for RawFloat {
7270
}
7371
}
7472
impl Eq for RawFloat {}
75-
impl Hash for RawFloat {
76-
fn hash<H: Hasher>(&self, state: &mut H) {
77-
self.0.to_bits().hash(state)
73+
impl Ord for RawFloat {
74+
fn cmp(&self, other: &Self) -> core::cmp::Ordering {
75+
self.0.to_bits().cmp(&other.0.to_bits())
76+
}
77+
}
78+
impl PartialOrd for RawFloat {
79+
fn partial_cmp(&self, other: &Self) -> Option<core::cmp::Ordering> {
80+
Some(self.cmp(other))
7881
}
7982
}
8083

@@ -88,8 +91,13 @@ impl PartialEq for RawDouble {
8891
}
8992
}
9093
impl Eq for RawDouble {}
91-
impl Hash for RawDouble {
92-
fn hash<H: Hasher>(&self, state: &mut H) {
93-
self.0.to_bits().hash(state)
94+
impl Ord for RawDouble {
95+
fn cmp(&self, other: &Self) -> core::cmp::Ordering {
96+
self.0.to_bits().cmp(&other.0.to_bits())
97+
}
98+
}
99+
impl PartialOrd for RawDouble {
100+
fn partial_cmp(&self, other: &Self) -> Option<core::cmp::Ordering> {
101+
Some(self.cmp(other))
94102
}
95103
}

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