|
19 | 19 |
|
20 | 20 | from litex.gen.sim import * |
21 | 21 |
|
22 | | -ip_address = 0x12345678 |
| 22 | +# Constants ---------------------------------------------------------------------------------------- |
| 23 | + |
| 24 | +ip_address = 0x12345678 |
23 | 25 | mac_address = 0x12345678abcd |
24 | 26 |
|
| 27 | +# DUT ---------------------------------------------------------------------------------------------- |
25 | 28 |
|
26 | | -class DUT(Module): |
| 29 | +class DUT(LiteXModule): |
27 | 30 | def __init__(self): |
28 | | - self.submodules.phy_model = phy.PHY(8, debug=False) |
29 | | - self.submodules.mac_model = mac.MAC(self.phy_model, debug=False, loopback=False) |
30 | | - self.submodules.arp_model = arp.ARP(self.mac_model, mac_address, ip_address, debug=False) |
31 | | - self.submodules.ip_model = ip.IP(self.mac_model, mac_address, ip_address, debug=False, loopback=False) |
32 | | - self.submodules.udp_model = udp.UDP(self.ip_model, ip_address, debug=False, loopback=False) |
33 | | - self.submodules.etherbone_model = etherbone.Etherbone(self.udp_model, debug=False) |
| 31 | + self.phy_model = phy.PHY(8, debug=False) |
| 32 | + self.mac_model = mac.MAC(self.phy_model, debug=False, loopback=False) |
| 33 | + self.arp_model = arp.ARP(self.mac_model, mac_address, ip_address, debug=False) |
| 34 | + self.ip_model = ip.IP(self.mac_model, mac_address, ip_address, debug=False, loopback=False) |
| 35 | + self.udp_model = udp.UDP(self.ip_model, ip_address, debug=False, loopback=False) |
| 36 | + self.etherbone_model = etherbone.Etherbone(self.udp_model, debug=False) |
34 | 37 |
|
35 | | - self.submodules.core = LiteEthUDPIPCore(self.phy_model, mac_address, ip_address, 100000) |
36 | | - self.submodules.etherbone = LiteEthEtherbone(self.core.udp, 0x1234) |
| 38 | + self.core = LiteEthUDPIPCore(self.phy_model, mac_address, ip_address, 100000) |
| 39 | + self.etherbone = LiteEthEtherbone(self.core.udp, 0x1234) |
37 | 40 |
|
38 | | - self.submodules.sram = wishbone.SRAM(1024) |
39 | | - self.submodules.interconnect = wishbone.InterconnectPointToPoint(self.etherbone.wishbone.bus, self.sram.bus) |
| 41 | + self.sram = wishbone.SRAM(1024) |
| 42 | + self.interconnect = wishbone.InterconnectPointToPoint(self.etherbone.wishbone.bus, self.sram.bus) |
40 | 43 |
|
| 44 | +# Genrator ----------------------------------------------------------------------------------------- |
41 | 45 |
|
42 | 46 | def main_generator(dut): |
43 | 47 | test_probe = True |
@@ -104,17 +108,19 @@ def main_generator(dut): |
104 | 108 | s, l, e = check(writes_datas, loopback_writes_datas) |
105 | 109 | print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e)) |
106 | 110 |
|
| 111 | +# Test Etherbone ----------------------------------------------------------------------------------- |
107 | 112 |
|
108 | 113 | class TestEtherbone(unittest.TestCase): |
109 | 114 | def test_etherbone(self): |
110 | 115 | dut = DUT() |
111 | 116 | generators = { |
112 | | - "sys" : [main_generator(dut)], |
113 | | - "eth_tx": [dut.phy_model.phy_sink.generator(), |
114 | | - dut.phy_model.generator()], |
115 | | - "eth_rx": dut.phy_model.phy_source.generator() |
| 117 | + "sys" : [main_generator(dut)], |
| 118 | + "eth_tx" : [dut.phy_model.phy_sink.generator(), dut.phy_model.generator()], |
| 119 | + "eth_rx" : [dut.phy_model.phy_source.generator()] |
| 120 | + } |
| 121 | + clocks = { |
| 122 | + "sys": 10, |
| 123 | + "eth_rx": 10, |
| 124 | + "eth_tx": 10, |
116 | 125 | } |
117 | | - clocks = {"sys": 10, |
118 | | - "eth_rx": 10, |
119 | | - "eth_tx": 10} |
120 | 126 | #run_simulation(dut, generators, clocks, vcd_name="sim.vcd") # FIXME: hanging |
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