Skip to content

Commit 9b5edb6

Browse files
enjoy-digitalenjoy-digital
committed
phy/pcs_1000basex: Remove valid/input_valid support since not used and always valid.
1 parent e468ccc commit 9b5edb6

File tree

1 file changed

+52
-62
lines changed

1 file changed

+52
-62
lines changed

‎liteeth/phy/pcs_1000basex.py‎

Lines changed: 52 additions & 62 deletions
Original file line numberDiff line numberDiff line change
@@ -55,7 +55,7 @@ def __init__(self):
5555
SGMII_10MBPS_SPEED = 0b00
5656

5757
class PCSSGMIITimer(LiteXModule):
58-
def __init__(self, speed, valid=True):
58+
def __init__(self, speed):
5959
self.enable = Signal()
6060
self.done = Signal()
6161

@@ -64,16 +64,13 @@ def __init__(self, speed, valid=True):
6464
count = Signal(max=100)
6565
self.comb += self.done.eq(count == 0)
6666
self.sync += [
67-
If(valid,
68-
If(~self.enable | self.done,
69-
Case(speed, {
70-
SGMII_10MBPS_SPEED : count.eq(99),
71-
SGMII_100MBPS_SPEED : count.eq(9),
72-
SGMII_1000MBPS_SPEED : count.eq(0),
73-
})
74-
).Else(
75-
count.eq(count - 1),
76-
)
67+
count.eq(count - 1),
68+
If(~self.enable | self.done,
69+
Case(speed, {
70+
SGMII_10MBPS_SPEED : count.eq(99),
71+
SGMII_100MBPS_SPEED : count.eq(9),
72+
SGMII_1000MBPS_SPEED : count.eq(0),
73+
})
7774
)
7875
]
7976

@@ -176,7 +173,6 @@ def __init__(self, lsb_first=False):
176173
self.config_reg = Signal(16) # Config register (16-bit).
177174
self.sgmii_speed = Signal(2) # SGMII speed.
178175
self.source = source = stream.Endpoint([("data", 8), ("error", 1)]) # Data output.
179-
self.input_valid = Signal(reset=1) # Data input valid.
180176

181177
self.decoder = Decoder(lsb_first=lsb_first) # 8b/10b Decoder.
182178

@@ -188,12 +184,12 @@ def __init__(self, lsb_first=False):
188184

189185
# SGMII Timer.
190186
# ------------
191-
self.timer = timer = PCSSGMIITimer(speed=self.sgmii_speed, valid=self.input_valid)
187+
self.timer = timer = PCSSGMIITimer(speed=self.sgmii_speed)
192188

193189
# Buffer.
194190
# -------
195191
self.buffer = buffer = stream.Buffer([("data", 8)], pipe_valid=True, pipe_ready=False)
196-
self.comb += If(timer.done & self.input_valid,
192+
self.comb += If(timer.done,
197193
buffer.source.connect(source, omit={"last", "error"}),
198194
source.last.eq(buffer.source.valid & ~buffer.sink.valid), # Last when next is not valid.
199195
)
@@ -203,7 +199,7 @@ def __init__(self, lsb_first=False):
203199
self.fsm = fsm = FSM()
204200
fsm.act("START",
205201
# Wait for a K-character.
206-
If(self.input_valid & self.decoder.k,
202+
If(self.decoder.k,
207203
# K-character is Config or Idle K28.5.
208204
If(self.decoder.d == K(28, 5),
209205
NextValue(count, 0),
@@ -219,60 +215,54 @@ def __init__(self, lsb_first=False):
219215
)
220216
)
221217
fsm.act("CONFIG-D-OR-IDLE",
222-
If(self.input_valid,
223-
If(~self.decoder.k & ~self.decoder.invalid,
224-
# Check for Configuration Word.
225-
If((self.decoder.d == D(21, 5)) | # /C1/.
226-
(self.decoder.d == D( 2, 2)), # /C2/.
227-
self.seen_valid_ci.eq(1),
228-
NextState("CONFIG-REG")
229-
),
230-
# Check for Idle Word.
231-
If((self.decoder.d == D( 5, 6)) | # /I1/.
232-
(self.decoder.d == D(16, 2)), # /I2/.
233-
self.seen_valid_ci.eq(1),
234-
NextState("START")
235-
)
236-
).Else(
237-
NextState("ERROR"),
218+
If(~self.decoder.k & ~self.decoder.invalid,
219+
# Check for Configuration Word.
220+
If((self.decoder.d == D(21, 5)) | # /C1/.
221+
(self.decoder.d == D( 2, 2)), # /C2/.
222+
self.seen_valid_ci.eq(1),
223+
NextState("CONFIG-REG")
224+
),
225+
# Check for Idle Word.
226+
If((self.decoder.d == D( 5, 6)) | # /I1/.
227+
(self.decoder.d == D(16, 2)), # /I2/.
228+
self.seen_valid_ci.eq(1),
229+
NextState("START")
238230
)
231+
).Else(
232+
NextState("ERROR"),
239233
)
240234
)
241235
fsm.act("CONFIG-REG",
242-
If(self.input_valid,
243-
If(~self.decoder.k & ~self.decoder.invalid,
244-
# Receive for Configuration Register.
245-
NextValue(count, count + 1),
246-
Case(count, {
247-
0b0 : NextValue(self.config_reg[:8], self.decoder.d), # LSB.
248-
0b1 : NextValue(self.config_reg[8:], self.decoder.d), # MSB.
249-
}),
250-
If(count == (2 - 1),
251-
self.seen_config_reg.eq(1),
252-
NextState("START")
253-
)
254-
).Else(
255-
NextState("ERROR"),
236+
If(~self.decoder.k & ~self.decoder.invalid,
237+
# Receive for Configuration Register.
238+
NextValue(count, count + 1),
239+
Case(count, {
240+
0b0 : NextValue(self.config_reg[:8], self.decoder.d), # LSB.
241+
0b1 : NextValue(self.config_reg[8:], self.decoder.d), # MSB.
242+
}),
243+
If(count == (2 - 1),
244+
self.seen_config_reg.eq(1),
245+
NextState("START")
256246
)
247+
).Else(
248+
NextState("ERROR"),
257249
)
258250
)
259251
fsm.act("DATA",
260-
If(self.input_valid,
261-
If(~self.decoder.k & ~self.decoder.invalid,
262-
# Receive Data.
263-
timer.enable.eq(1),
264-
buffer.sink.valid.eq(timer.done),
265-
buffer.sink.data.eq(self.decoder.d),
266-
).Elif(self.decoder.k & (self.decoder.d == K(29, 7)) & ~self.decoder.invalid,
267-
# K-character is End-of-packet /S/.
268-
NextState("START"),
269-
).Else(
270-
source.error.eq(1),
271-
source.last.eq(1),
272-
source.valid.eq(1),
273-
If(source.ready,
274-
NextState("ERROR"),
275-
)
252+
If(~self.decoder.k & ~self.decoder.invalid,
253+
# Receive Data.
254+
timer.enable.eq(1),
255+
buffer.sink.valid.eq(timer.done),
256+
buffer.sink.data.eq(self.decoder.d),
257+
).Elif(self.decoder.k & (self.decoder.d == K(29, 7)) & ~self.decoder.invalid,
258+
# K-character is End-of-packet /S/.
259+
NextState("START"),
260+
).Else(
261+
source.error.eq(1),
262+
source.last.eq(1),
263+
source.valid.eq(1),
264+
If(source.ready,
265+
NextState("ERROR"),
276266
)
277267
)
278268
)
@@ -290,7 +280,7 @@ def __init__(self, lsb_first=False, check_period=6e-3, breaklink_time=10e-3, mor
290280

291281
self.tbi_tx = self.tx.encoder.output[0]
292282
self.tbi_rx = self.rx.decoder.input
293-
self.tbi_rx_valid = self.rx.input_valid
283+
self.tbi_rx_valid = Signal(reset=1)
294284
self.sink = stream.Endpoint(eth_phy_description(8))
295285
self.source = stream.Endpoint(eth_phy_description(8))
296286

0 commit comments

Comments
 (0)