liteeth from PyPI: liteeth_gen raises `ValueError` when generating example core.

[Sazzach]

With liteeth installed from PyPI via pip in a fresh virtual environment, running liteeth_gen wishbone_mii.yml produces the following output:

(.venv) samuelz@sz-t14 ~/F/liteeth_pip> liteeth_gen wishbone_mii.yml
INFO:SoC:        __   _ __      _  __  
INFO:SoC:       / /  (_) /____ | |/_/  
INFO:SoC:      / /__/ / __/ -_)>  <    
INFO:SoC:     /____/_/\__/\__/_/|_|  
INFO:SoC:  Build your hardware, easily!
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Creating SoC... (2025-04-30 17:14:33)
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:FPGA device : .
INFO:SoC:System clock: 100.000MHz.
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoCBusHandler:Adding reserved Bus Regions...
INFO:SoCBusHandler:Bus Handler created.
INFO:SoCCSRHandler:Creating CSR Handler...
INFO:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoCCSRHandler:Adding reserved CSRs...
INFO:SoCCSRHandler:ctrl CSR added at Location 0.
INFO:SoCCSRHandler:ethphy CSR added at Location 1.
INFO:SoCCSRHandler:ethmac CSR added at Location 2.
INFO:SoCCSRHandler:CSR Handler created.
INFO:SoCIRQHandler:Creating IRQ Handler...
INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
INFO:SoCIRQHandler:Adding reserved IRQs...
INFO:SoCIRQHandler:IRQ Handler created.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Initial SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
CSR Locations: (3)
- ctrl   : 0
- ethphy : 1
- ethmac : 2
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Controller ctrl added.
Traceback (most recent call last):
  File "/home/samuelz/Flux/liteeth_pip/.venv/bin/liteeth_gen", line 8, in <module>
    sys.exit(main())
             ^^^^^^
  File "/home/samuelz/Flux/liteeth_pip/.venv/lib/python3.12/site-packages/liteeth/gen.py", line 698, in main
    soc = MACCore(platform, core_config)
          ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/home/samuelz/Flux/liteeth_pip/.venv/lib/python3.12/site-packages/liteeth/gen.py", line 413, in __init__
    PHYCore.__init__(self, platform, core_config)
  File "/home/samuelz/Flux/liteeth_pip/.venv/lib/python3.12/site-packages/liteeth/gen.py", line 254, in __init__
    SoCMini.__init__(self, platform, clk_freq=core_config["clk_freq"], **soc_args)
  File "/home/samuelz/Flux/liteeth_pip/.venv/lib/python3.12/site-packages/litex/soc/integration/soc_core.py", line 395, in __init__
    SoCCore.__init__(self, *args, **kwargs)
  File "/home/samuelz/Flux/liteeth_pip/.venv/lib/python3.12/site-packages/litex/soc/integration/soc_core.py", line 215, in __init__
    self.add_controller("ctrl")
  File "/home/samuelz/Flux/liteeth_pip/.venv/lib/python3.12/site-packages/litex/soc/integration/soc.py", line 1054, in add_controller
    self.add_module(name=name, module=SoCController(**kwargs))
                                      ^^^^^^^^^^^^^^^^^^^^^^^
  File "/home/samuelz/Flux/liteeth_pip/.venv/lib/python3.12/site-packages/litex/soc/integration/soc.py", line 889, in __init__
    self._reset = CSRStorage(fields=[
                  ^^^^^^^^^^^^^^^^^^^
  File "/home/samuelz/Flux/liteeth_pip/.venv/lib/python3.12/site-packages/litex/soc/interconnect/csr.py", line 388, in __init__
    _CompoundCSR.__init__(self, size, name, n)
  File "/home/samuelz/Flux/liteeth_pip/.venv/lib/python3.12/site-packages/litex/soc/interconnect/csr.py", line 136, in __init__
    _CSRBase.__init__(self, size, name, n)
  File "/home/samuelz/Flux/liteeth_pip/.venv/lib/python3.12/site-packages/litex/soc/interconnect/csr.py", line 53, in __init__
    raise ValueError("Cannot extract CSR name from code, need to specify.")
ValueError: Cannot extract CSR name from code, need to specify.

wishbone_mii.yml is from liteeth/examples
It works fine with liteeth installed the recommended way.