Merge pull request #2314 from VOGL-electronic/litespi_ddr_clk_divider

litespi: use new clk divisor

Author: enjoy-digital

litex/soc/integration/soc.py

@@ -2181,8 +2181,10 @@ def add_spi_flash(self, name="spiflash", mode="4x", clk_freq=20e6, module=None,
 
         # Checks/Parameters.
         assert mode in ["1x", "4x"]
-        default_divisor = math.ceil(self.sys_clk_freq/(2*clk_freq)) - 1
-        clk_freq        = int(self.sys_clk_freq/(2*(default_divisor + 1)))
+        default_divisor = math.ceil(self.sys_clk_freq/clk_freq)
+        if rate == "1:1":
+            default_divisor += default_divisor % 2 # Round up to nearest even number.
+        clk_freq        = int(self.sys_clk_freq/default_divisor)
 
         if "master_with_irq" not in kwargs and self.irq.enabled and name in self.irq.locs.keys():
             # If IRQ is enabled, use master_with_irq.
@@ -2210,6 +2212,7 @@ def add_spi_flash(self, name="spiflash", mode="4x", clk_freq=20e6, module=None,
         # Constants.
         self.add_constant(f"{name}_PHY_FREQUENCY",     clk_freq)
         if module is not None:
+            self.add_constant(f"{name}_PHY_MIN_DIVISOR",   2 if rate == "1:1" else 1)
             self.add_constant(f"{name}_MODULE_NAME",       module.name)
             self.add_constant(f"{name}_MODULE_TOTAL_SIZE", module.total_size)
             self.add_constant(f"{name}_MODULE_PAGE_SIZE",  module.page_size)
@@ -2235,8 +2238,10 @@ def add_spi_ram(self, name="spiram", mode="4x", clk_freq=20e6, module=None, phy=
 
         # Checks/Parameters.
         assert mode in ["1x", "4x"]
-        default_divisor = math.ceil(self.sys_clk_freq/(2*clk_freq)) - 1
-        clk_freq        = int(self.sys_clk_freq/(2*(default_divisor + 1)))
+        default_divisor = math.ceil(self.sys_clk_freq/clk_freq)
+        if rate == "1:1":
+            default_divisor += default_divisor % 2 # Round up to nearest even number.
+        clk_freq        = int(self.sys_clk_freq/default_divisor)
 
         if "master_with_irq" not in kwargs and self.irq.enabled and name in self.irq.locs.keys():
             # If IRQ is enabled, use master_with_irq.
@@ -2282,6 +2287,7 @@ def add_spi_ram(self, name="spiram", mode="4x", clk_freq=20e6, module=None, phy=
 
         # Constants.
         self.add_constant(f"{name}_PHY_FREQUENCY",     clk_freq)
+        self.add_constant(f"{name}_PHY_MIN_DIVISOR",   2 if rate == "1:1" else 1)
         self.add_constant(f"{name}_MODULE_NAME",       module.name)
         self.add_constant(f"{name}_MODULE_TOTAL_SIZE", module.total_size)
         self.add_constant(f"{name}_MODULE_PAGE_SIZE",  module.page_size)

litex/soc/software/liblitespi/spiflash.c

@@ -40,8 +40,11 @@ int spiflash_freq_init(void)
 		printf("First SPI Flash block erased, unable to perform freq test.\n\r");
 		return -1;
 	}
-
-	while((crc == crc_test) && (lowest_div-- > 0)) {
+#if defined(SPIFLASH_PHY_MIN_DIVISOR) && SPIFLASH_PHY_MIN_DIVISOR == 1
+	while((crc == crc_test) && (lowest_div-- > 1)) {
+#else
+	while((crc == crc_test) && ((lowest_div -= 2) >= 2)) {
+#endif
 		spiflash_phy_clk_divisor_write((uint32_t)lowest_div);
 		invd_cpu_dcache_range((void *)SPIFLASH_BASE, SPI_FLASH_BLOCK_SIZE);
 		flush_l2_cache();
@@ -50,10 +53,15 @@ int spiflash_freq_init(void)
 		printf("[DIV: %d] %08x\n\r", lowest_div, crc_test);
 #endif
 	}
+#if defined(SPIFLASH_PHY_MIN_DIVISOR) && SPIFLASH_PHY_MIN_DIVISOR == 1
 	lowest_div++;
-	printf("SPI Flash clk configured to %d MHz\n", CONFIG_CLOCK_FREQUENCY/(2*(1+lowest_div)*1000000));
+#else
+	lowest_div += 2;
+#endif
+	printf("SPI Flash clk configured to %d MHz (div: %d)\n", CONFIG_CLOCK_FREQUENCY/(lowest_div*1000000), lowest_div);
 
 	spiflash_phy_clk_divisor_write(lowest_div);
+	spiflash_mmap_clk_divisor_write(lowest_div);
 
 #else