build/efinix: use default library for Verilog sources

Author: enjoy-digital

litex/build/efinix/efinity.py

@@ -70,8 +70,10 @@ def _default_efx_pgm_params(generate_bitbin=False, generate_hexbin=False):
         "enable_crc_check"         : True,
     }
 
-def _get_design_file_library(filename, library):
-    return "default" if filename.endswith((".vh", ".svh")) else library
+def _get_design_file_library(filename, language, library):
+    if language in ("verilog", "systemverilog"):
+        return "default"
+    return library
 
 def _add_custom_params(parent, params):
     for key, value in params.items():
@@ -365,7 +367,7 @@ def build_project(self):
             et.SubElement(design_info, "efx:design_file", {
                 "name"    : filename,
                 "version" : "default",
-                "library" : _get_design_file_library(filename, library),
+                "library" : _get_design_file_library(filename, language, library),
             })
 
         # Add Timing Constraints.