Add screen zoom feature for accessibility

Implements a screen zoom setting accessible from the Analogue Pocket
interact menu, addressing the request for larger display output to
improve readability. The zoom works by remapping framebuffer read
addresses to display a cropped/enlarged portion of the 512x512
framebuffer:

- Off: Normal 1:1 display (default)
- Small: ~1.14x zoom (reads 448px from center, offset 32)
- Large: ~1.33x zoom (reads 384px from center, offset 64)

The setting persists across sessions via the APF interact system.

Closes #1

https://claude.ai/code/session_01NYKHEx1oSSxcWrEi23wb4L

Author: claude

dist/Cores/ericlewis.LunarLander/interact.json

@@ -1,7 +1,23 @@
 {
     "interact": {
         "magic": "APF_VER_1",
-        "variables": [],
+        "variables": [
+            {
+                "id": 0,
+                "name": "Screen Zoom",
+                "type": "list",
+                "enabled": true,
+                "persist": true,
+                "address": "0x50000000",
+                "defaultval": "0x00",
+                "mask": "0x03",
+                "options": [
+                    {"value": "0x00", "name": "Off"},
+                    {"value": "0x01", "name": "Small"},
+                    {"value": "0x02", "name": "Large"}
+                ]
+            }
+        ],
         "messages": []
     }
-}
+}

src/fpga/core/core_top.sv

@@ -309,6 +309,18 @@ assign vpll_feed = 1'bZ;
 // for bridge write data, we just broadcast it to all bus devices
 // for bridge read data, we have to mux it
 // add your own devices here
+
+// Interact variables
+reg [31:0] interact_zoom = 32'h0;
+
+always @(posedge clk_74a) begin
+    if (bridge_wr) begin
+        casex (bridge_addr)
+            32'h50000000: interact_zoom <= bridge_wr_data;
+        endcase
+    end
+end
+
 always @(*) begin
     casex(bridge_addr)
     default: begin
@@ -319,6 +331,9 @@ always @(*) begin
         // bridge_rd_data <= example_device_data;
         bridge_rd_data <= 0;
     end
+    32'h50000000: begin
+        bridge_rd_data <= interact_zoom;
+    end
     32'hF8xxxxxx: begin
         bridge_rd_data <= cmd_bridge_rd_data;
     end
@@ -766,7 +781,8 @@ LLANDER_TOP LLANDER_TOP
 	.VID_HBLANK(hblank),
 	.VID_VBLANK(vblank_lunarlander),
 	.DIP(m_dip),
-	.RESET_L (reset_n),	
+	.ZOOM(interact_zoom[1:0]),
+	.RESET_L (reset_n),
 	.clk_6(clk_6),
 	.clk_25(clk_25)
 );

src/fpga/core/rtl/asteroids_dw.vhd

@@ -67,6 +67,8 @@ entity ASTEROIDS_DW is
     BEAM_ON          : in    std_logic;
     BEAM_ENA         : in    std_logic;
 
+    ZOOM             : in    std_logic_vector(1 downto 0);
+
     VIDEO_R_OUT      : out   std_logic_vector(3 downto 0);
     VIDEO_G_OUT      : out   std_logic_vector(3 downto 0);
     VIDEO_B_OUT      : out   std_logic_vector(3 downto 0);
@@ -125,9 +127,8 @@ architecture RTL of ASTEROIDS_DW is
   signal pxcount					: std_logic_vector(8 downto 0);
   signal vram_wren				: std_logic;
 
-
-
-  
+  signal X_Read					: std_logic_vector(8 downto 0);
+  signal Y_Read					: std_logic_vector(8 downto 0);
 
 begin
 
@@ -317,7 +318,31 @@ begin
 
   end process;
 
-  up_addr <= (Y_Vid(8 downto 0) & X_Vid(8 downto 0));
+  -- Zoom: remap read addresses to display a cropped/enlarged portion of the framebuffer.
+  -- Small zoom (~1.14x): pixel * 7/8 + 32 => reads 448 pixels from 32..480
+  -- Large zoom (~1.33x): pixel * 3/4 + 64 => reads 384 pixels from 64..448
+  zoom_addr : process(X_Vid, Y_Vid, ZOOM)
+    variable x_shift : std_logic_vector(8 downto 0);
+    variable y_shift : std_logic_vector(8 downto 0);
+  begin
+    case ZOOM is
+      when "01" =>
+        x_shift := "000" & X_Vid(8 downto 3);
+        y_shift := "000" & Y_Vid(8 downto 3);
+        X_Read <= (X_Vid - x_shift) + 32;
+        Y_Read <= (Y_Vid - y_shift) + 32;
+      when "10" | "11" =>
+        x_shift := "00" & X_Vid(8 downto 2);
+        y_shift := "00" & Y_Vid(8 downto 2);
+        X_Read <= (X_Vid - x_shift) + 64;
+        Y_Read <= (Y_Vid - y_shift) + 64;
+      when others =>
+        X_Read <= X_Vid;
+        Y_Read <= Y_Vid;
+    end case;
+  end process;
+
+  up_addr <= (Y_Read & X_Read);
 
   clear_ram : process(clk_25, RESET)
 	variable state 				: integer range 0 to 4;

src/fpga/core/rtl/llander_top.vhd

@@ -99,6 +99,8 @@ entity LLANDER_TOP is
 
     DIP               : in    std_logic_vector(7 downto 0);
 
+    ZOOM              : in    std_logic_vector(1 downto 0);
+
     RESET_L           : in    std_logic;
 
     -- ref clock in
@@ -198,6 +200,8 @@ begin
       BEAM_ON     => beam_on,
       BEAM_ENA    => beam_ena,
 
+      ZOOM        => ZOOM,
+
       VIDEO_R_OUT => VIDEO_R_OUT,
       VIDEO_G_OUT => VIDEO_G_OUT,
       VIDEO_B_OUT => VIDEO_B_OUT,