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Lines changed: 80 additions & 74 deletions

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lib/Conversion/CoreDSLToPy/CoreDSLToPy.cpp

Lines changed: 80 additions & 74 deletions
Original file line numberDiff line numberDiff line change
@@ -153,7 +153,8 @@ handleWordWiseAccess(Op op,
153153
}
154154
}
155155

156-
// Handles both scf::YieldOp and coredsl::YieldOp, as their handling is identical
156+
// Handles both scf::YieldOp and coredsl::YieldOp, as their handling is
157+
// identical
157158
template <typename YieldOp>
158159
static WalkResult emitYieldOp(mlir::raw_indented_ostream &os, YieldOp yieldOp) {
159160
os << "return ";
@@ -485,80 +486,86 @@ static WalkResult emitCoreDSLOp(mlir::raw_indented_ostream &os, Operation *op) {
485486
<< (targetType.isSigned() ? "True" : "False") << ")\n";
486487
return WalkResult::advance();
487488
})
488-
.Case<coredsl::SwitchOp>([&](coredsl::SwitchOp switchOp){
489-
const unsigned switchId = uniqueSwitchNumber++;
490-
for (unsigned i = 0, end = switchOp.getNumCases(); i < end; ++i) {
491-
Block &caseBlock = switchOp.getCaseBlock(i);
492-
// Emit each case as a helper function. This way each
493-
// switch has the form
494-
// 'ret1, ret2, ..., retn = helper_function', thereby
495-
// making handling of the results easier and allowing
496-
// us to just emit a return for every yield op
497-
os << "def helper_function_coredsl_switch_" << switchId << "_case_" << i << "():\n";
498-
os.indent();
499-
auto res = caseBlock.template walk<WalkOrder::PreOrder>([&os](Operation *op){return emitOp(os, op);});
500-
if (res.wasInterrupted())
501-
return res;
502-
os.unindent();
503-
}
504-
os << "def helper_function_coresl_switch_" << switchId << "_default_case():\n";
505-
os.indent();
506-
auto res = switchOp.getDefaultBlock().walk<WalkOrder::PreOrder>([&os](Operation *op){return emitOp(os, op);});
507-
if (res.wasInterrupted())
508-
return res;
509-
os.unindent();
489+
.Case<coredsl::SwitchOp>([&](coredsl::SwitchOp switchOp) {
490+
const unsigned switchId = uniqueSwitchNumber++;
491+
for (unsigned i = 0, end = switchOp.getNumCases(); i < end; ++i) {
492+
Block &caseBlock = switchOp.getCaseBlock(i);
493+
// Emit each case as a helper function. This way each
494+
// switch has the form
495+
// 'ret1, ret2, ..., retn = helper_function', thereby
496+
// making handling of the results easier and allowing
497+
// us to just emit a return for every yield op
498+
os << "def helper_function_coredsl_switch_" << switchId << "_case_"
499+
<< i << "():\n";
500+
os.indent();
501+
auto res = caseBlock.template walk<WalkOrder::PreOrder>(
502+
[&os](Operation *op) { return emitOp(os, op); });
503+
if (res.wasInterrupted())
504+
return res;
505+
os.unindent();
506+
}
507+
os << "def helper_function_coresl_switch_" << switchId
508+
<< "_default_case():\n";
509+
os.indent();
510+
auto res = switchOp.getDefaultBlock().walk<WalkOrder::PreOrder>(
511+
[&os](Operation *op) { return emitOp(os, op); });
512+
if (res.wasInterrupted())
513+
return res;
514+
os.unindent();
515+
bool first = true;
516+
for (const auto &[idx, attr] : llvm::enumerate(switchOp.getCases())) {
517+
const IntegerAttr &intAttr = cast<IntegerAttr>(attr);
518+
const APInt &caseValAPInt = intAttr.getValue();
519+
const unsigned bitWidth = switchOp.getArg().getType().getWidth();
520+
const auto signedness = switchOp.getArg().getType().getSignedness();
521+
assert(signedness != IntegerType::Signless);
522+
const APSInt caseVal = APSInt(caseValAPInt.sextOrTrunc(bitWidth),
523+
signedness == IntegerType::Signed);
524+
if (first)
525+
os << "if ";
526+
else
527+
os << "elif ";
528+
first = false;
529+
valToPy(os, switchOp.getArg());
530+
os << "." << hwarith::ICmpPredicate::eq << "(";
531+
os << intToPy(caseVal) << "):\n";
532+
os.indent();
533+
if (switchOp.getNumResults() > 0) {
510534
bool first = true;
511-
for (const auto &[idx, attr] : llvm::enumerate(switchOp.getCases())) {
512-
const IntegerAttr &intAttr = cast<IntegerAttr>(attr);
513-
const APInt &caseValAPInt = intAttr.getValue();
514-
const unsigned bitWidth = switchOp.getArg().getType().getWidth();
515-
const auto signedness = switchOp.getArg().getType().getSignedness();
516-
assert(signedness != IntegerType::Signless);
517-
const APSInt caseVal = APSInt(caseValAPInt.sextOrTrunc(bitWidth), signedness == IntegerType::Signed);
518-
if (first)
519-
os << "if ";
520-
else
521-
os << "elif ";
522-
first = false;
523-
valToPy(os, switchOp.getArg());
524-
os << "." << hwarith::ICmpPredicate::eq << "(";
525-
os << intToPy(caseVal) << "):\n";
526-
os.indent();
527-
if (switchOp.getNumResults() > 0) {
528-
bool first = true;
529-
for (auto res : switchOp.getResults()) {
530-
if (!first) {
531-
os << ", ";
532-
}
533-
first = false;
534-
valToPy(os, res);
535-
}
536-
os << " = ";
535+
for (auto res : switchOp.getResults()) {
536+
if (!first) {
537+
os << ", ";
537538
}
538-
os << "helper_function_coredsl_switch_" << switchId << "_case_" << idx << "()\n";
539-
os.unindent();
539+
first = false;
540+
valToPy(os, res);
540541
}
541-
os << "else:\n";
542-
os.indent();
543-
if (switchOp.getNumResults() > 0) {
544-
bool first = true;
545-
for (auto res : switchOp.getResults()) {
546-
if (!first) {
547-
os << ", ";
548-
}
549-
first = false;
550-
valToPy(os, res);
551-
}
552-
os << " = ";
542+
os << " = ";
543+
}
544+
os << "helper_function_coredsl_switch_" << switchId << "_case_" << idx
545+
<< "()\n";
546+
os.unindent();
547+
}
548+
os << "else:\n";
549+
os.indent();
550+
if (switchOp.getNumResults() > 0) {
551+
bool first = true;
552+
for (auto res : switchOp.getResults()) {
553+
if (!first) {
554+
os << ", ";
553555
}
554-
os << "helper_function_coredsl_switch_" << switchId << "_default_case()\n";
555-
os.unindent();
556-
// Skip the child scopes, as we already visited them
557-
return WalkResult::skip();
558-
})
559-
.Case<coredsl::YieldOp>([&](coredsl::YieldOp yieldOp) {
560-
return emitYieldOp(os, yieldOp);
561-
})
556+
first = false;
557+
valToPy(os, res);
558+
}
559+
os << " = ";
560+
}
561+
os << "helper_function_coredsl_switch_" << switchId
562+
<< "_default_case()\n";
563+
os.unindent();
564+
// Skip the child scopes, as we already visited them
565+
return WalkResult::skip();
566+
})
567+
.Case<coredsl::YieldOp>(
568+
[&](coredsl::YieldOp yieldOp) { return emitYieldOp(os, yieldOp); })
562569
.Default([&](auto _) {
563570
op->emitError() << "CoreDSLToPy::emitCoreDSLOp lacks emission code for "
564571
"this operation!";
@@ -737,9 +744,8 @@ static WalkResult emitSCFOp(mlir::raw_indented_ostream &os, Operation *op) {
737744

738745
return WalkResult::skip();
739746
})
740-
.Case<scf::YieldOp>([&](auto yieldOp) {
741-
return emitYieldOp(os, yieldOp);
742-
})
747+
.Case<scf::YieldOp>(
748+
[&](auto yieldOp) { return emitYieldOp(os, yieldOp); })
743749
// .Case<scf::WhileOp>([&](auto whileOp) {
744750
// // TODO PITA
745751
// return WalkResult::interrupt();

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