RMT: move more things to esp-metadata, improve HIL test robustness (#4138)

* RMT: use hil_test::assert{,eq}, clarify potential timing issues

* RMT: prevent flaky HIL tests by matching pulse codes fuzzily

* RMT: add rmt_clock_rate HIL test

* RMT: add esp-metadata flags for most hardware features

* RMT: move supported clock sources to esp-metadata

* RMT: move max_idle_threshold to esp-metadata

from a quick glance at the TRMs, it seems that these values are also
wrong! e.g. c3 & c6 appear to support up to 0x7FFF -> this should be verified
and fixed if correct

Author: wisp3rwind

esp-hal/src/rmt.rs

@@ -213,6 +213,7 @@ use crate::{
     Async,
     Blocking,
     asynch::AtomicWaker,
+    clock::Clocks,
     gpio::{
         self,
         InputConfig,
@@ -788,7 +789,7 @@ impl<'d> Rmt<'d, Blocking> {
     /// Create a new RMT instance
     pub fn new(peripheral: RMT<'d>, frequency: Rate) -> Result<Self, Error> {
         let this = Rmt::create(peripheral);
-        self::chip_specific::configure_clock(frequency)?;
+        self::chip_specific::configure_clock(ClockSource::default(), frequency)?;
         Ok(this)
     }
 
@@ -1032,13 +1033,7 @@ where
 
         let _guard = GenericPeripheralGuard::new();
 
-        let threshold = if cfg!(any(esp32, esp32s2)) {
-            0b111_1111_1111_1111
-        } else {
-            0b11_1111_1111_1111
-        };
-
-        if config.idle_threshold > threshold {
+        if config.idle_threshold > property!("rmt.max_idle_threshold") {
             return Err(Error::InvalidArgument);
         }
 
@@ -1661,13 +1656,70 @@ impl DynChannelAccess<Rx> {
     }
 }
 
+for_each_rmt_clock_source!(
+    (all $(($name:ident, $bits:literal)),+) => {
+        #[derive(Clone, Copy, Debug)]
+        #[repr(u8)]
+        enum ClockSource {
+            $(
+                #[allow(unused)]
+                $name = $bits,
+            )+
+        }
+    };
+
+    (is_boolean) => {
+        impl ClockSource {
+            fn bit(self) -> bool {
+                match (self as u8) {
+                    0 => false,
+                    1 => true,
+                    _ => unreachable!("should be removed by the compiler!"),
+                }
+            }
+        }
+    };
+
+    (default ($name:ident)) => {
+        impl ClockSource {
+            fn default() -> Self {
+                Self::$name
+            }
+
+            fn bits(self) -> u8 {
+                self as u8
+            }
+
+            fn freq(self) -> crate::time::Rate {
+                match self {
+                    #[cfg(rmt_supports_apb_clock)]
+                    ClockSource::Apb => Clocks::get().apb_clock,
+
+                    #[cfg(rmt_supports_rcfast_clock)]
+                    ClockSource::RcFast => todo!(),
+
+                    #[cfg(rmt_supports_xtal_clock)]
+                    ClockSource::Xtal => Clocks::get().xtal_clock,
+
+                    #[cfg(rmt_supports_pll80mhz_clock)]
+                    ClockSource::Pll80MHz => Rate::from_mhz(80),
+
+                    #[cfg(rmt_supports_reftick_clock)]
+                    ClockSource::RefTick => todo!(),
+                }
+            }
+        }
+    };
+);
+
 #[cfg(not(any(esp32, esp32s2)))]
 mod chip_specific {
     use enumset::EnumSet;
 
     use super::{
         CHANNEL_INDEX_COUNT,
         ChannelIndex,
+        ClockSource,
         Direction,
         DynChannelAccess,
         Error,
@@ -1680,8 +1732,8 @@ mod chip_specific {
     };
     use crate::{peripherals::RMT, time::Rate};
 
-    pub(super) fn configure_clock(frequency: Rate) -> Result<(), Error> {
-        let src_clock = crate::soc::constants::RMT_CLOCK_SRC_FREQ;
+    pub(super) fn configure_clock(source: ClockSource, frequency: Rate) -> Result<(), Error> {
+        let src_clock = source.freq();
 
         if frequency > src_clock {
             return Err(Error::UnreachableTargetFrequency);
@@ -1695,7 +1747,7 @@ mod chip_specific {
         {
             RMT::regs().sys_conf().modify(|_, w| unsafe {
                 w.clk_en().clear_bit();
-                w.sclk_sel().bits(crate::soc::constants::RMT_CLOCK_SRC);
+                w.sclk_sel().bits(source.bits());
                 w.sclk_div_num().bits(div);
                 w.sclk_div_a().bits(0);
                 w.sclk_div_b().bits(0);
@@ -1715,11 +1767,11 @@ mod chip_specific {
             #[cfg(esp32c6)]
             PCR::regs()
                 .rmt_sclk_conf()
-                .modify(|_, w| unsafe { w.sclk_sel().bits(crate::soc::constants::RMT_CLOCK_SRC) });
+                .modify(|_, w| unsafe { w.sclk_sel().bits(source.bits()) });
             #[cfg(not(esp32c6))]
             PCR::regs()
                 .rmt_sclk_conf()
-                .modify(|_, w| w.sclk_sel().bit(crate::soc::constants::RMT_CLOCK_SRC));
+                .modify(|_, w| w.sclk_sel().bit(source.bit()));
 
             RMT::regs()
                 .sys_conf()
@@ -2097,6 +2149,7 @@ mod chip_specific {
 
     use super::{
         ChannelIndex,
+        ClockSource,
         Direction,
         DynChannelAccess,
         Error,
@@ -2111,16 +2164,16 @@ mod chip_specific {
     };
     use crate::{peripherals::RMT, time::Rate};
 
-    pub(super) fn configure_clock(frequency: Rate) -> Result<(), Error> {
-        if frequency != Rate::from_mhz(80) {
+    pub(super) fn configure_clock(source: ClockSource, frequency: Rate) -> Result<(), Error> {
+        if frequency != source.freq() {
             return Err(Error::UnreachableTargetFrequency);
         }
 
         let rmt = RMT::regs();
 
         for ch_num in 0..NUM_CHANNELS {
             rmt.chconf1(ch_num)
-                .modify(|_, w| w.ref_always_on().set_bit());
+                .modify(|_, w| w.ref_always_on().bit(source.bit()));
         }
 
         rmt.apb_conf().modify(|_, w| w.apb_fifo_mask().set_bit());
@@ -2201,7 +2254,7 @@ mod chip_specific {
     }
 
     impl DynChannelAccess<Tx> {
-        #[cfg(not(esp32))]
+        #[cfg(rmt_has_tx_loop_count)]
         #[inline]
         pub fn set_generate_repeat_interrupt(&self, loopcount: Option<LoopCount>) {
             let rmt = crate::peripherals::RMT::regs();
@@ -2215,7 +2268,7 @@ mod chip_specific {
                 .modify(|_, w| unsafe { w.tx_loop_num().bits(repeats) });
         }
 
-        #[cfg(esp32)]
+        #[cfg(not(rmt_has_tx_loop_count))]
         #[inline]
         pub fn set_generate_repeat_interrupt(&self, _loopcount: Option<LoopCount>) {
             // unsupported
@@ -2329,7 +2382,7 @@ mod chip_specific {
         // Returns whether stopping was immediate, or needs to wait for tx end
         // Due to inlining, the compiler should be able to eliminate code in the caller that
         // depends on this.
-        #[cfg(esp32s2)]
+        #[cfg(rmt_has_tx_immediate_stop)]
         #[inline]
         pub fn stop_tx(&self) -> bool {
             let rmt = crate::peripherals::RMT::regs();
@@ -2338,7 +2391,7 @@ mod chip_specific {
             true
         }
 
-        #[cfg(esp32)]
+        #[cfg(not(rmt_has_tx_immediate_stop))]
         #[inline]
         pub fn stop_tx(&self) -> bool {
             let ptr = self.channel_ram_start();

esp-hal/src/soc/esp32c3/mod.rs

@@ -19,17 +19,10 @@ pub(crate) use esp32c3 as pac;
 
 #[cfg_attr(not(feature = "unstable"), allow(unused))]
 pub(crate) mod constants {
-    use crate::time::Rate;
-
     /// The base clock frequency for the I2S peripheral (Hertz).
     pub const I2S_SCLK: u32 = 160_000_000;
     /// The default clock source for I2S operations.
     pub const I2S_DEFAULT_CLK_SRC: u8 = 2;
-
-    /// RMT Clock source value.
-    pub const RMT_CLOCK_SRC: u8 = 1;
-    /// RMT Clock source frequency.
-    pub const RMT_CLOCK_SRC_FREQ: Rate = Rate::from_mhz(80);
 }
 
 pub(crate) fn pre_init() {}

esp-hal/src/soc/esp32c6/mod.rs

@@ -21,18 +21,11 @@ pub(crate) use esp32c6 as pac;
 
 #[cfg_attr(not(feature = "unstable"), allow(unused))]
 pub(crate) mod constants {
-    use crate::time::Rate;
-
     /// The clock frequency for the I2S peripheral in Hertz.
     pub const I2S_SCLK: u32 = 160_000_000;
     /// The default clock source for the I2S peripheral.
     pub const I2S_DEFAULT_CLK_SRC: u8 = 2;
 
-    /// The default clock source for the RMT peripheral.
-    pub const RMT_CLOCK_SRC: u8 = 1;
-    /// The frequency of the RMT clock source in Hertz.
-    pub const RMT_CLOCK_SRC_FREQ: Rate = Rate::from_mhz(80);
-
     /// The clock frequency for the Parallel IO peripheral in Hertz.
     pub const PARL_IO_SCLK: u32 = 240_000_000;
 }

esp-hal/src/soc/esp32h2/mod.rs

@@ -20,18 +20,11 @@ pub(crate) use esp32h2 as pac;
 
 #[cfg_attr(not(feature = "unstable"), allow(unused))]
 pub(crate) mod constants {
-    use crate::time::Rate;
-
     /// Default clock source for the I2S peripheral.
     pub const I2S_DEFAULT_CLK_SRC: u8 = 1;
     /// Clock frequency for the I2S peripheral, in Hertz.
     pub const I2S_SCLK: u32 = 96_000_000;
 
-    /// Clock source for the RMT peripheral (false = default source).
-    pub const RMT_CLOCK_SRC: bool = false;
-    /// Frequency of the RMT clock source, in Hertz.
-    pub const RMT_CLOCK_SRC_FREQ: Rate = Rate::from_mhz(32);
-
     /// System clock frequency for the parallel I/O (PARL IO) peripheral, in
     /// Hertz.
     pub const PARL_IO_SCLK: u32 = 96_000_000;

esp-hal/src/soc/esp32s3/mod.rs

@@ -21,17 +21,10 @@ pub use esp32s3 as pac;
 
 #[cfg_attr(not(feature = "unstable"), allow(unused))]
 pub(crate) mod constants {
-    use crate::time::Rate;
-
     /// The base clock frequency for the I2S peripheral (Hertz).
     pub const I2S_SCLK: u32 = 160_000_000;
     /// The default clock source for I2S operations.
     pub const I2S_DEFAULT_CLK_SRC: u8 = 2;
-
-    /// RMT Clock source value.
-    pub const RMT_CLOCK_SRC: u8 = 1;
-    /// RMT Clock source frequency.
-    pub const RMT_CLOCK_SRC_FREQ: Rate = Rate::from_mhz(80);
 }
 
 #[unsafe(link_section = ".rwtext")]