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41 | 41 | //! ```rust, no_run |
42 | 42 | //! # {before_snippet} |
43 | 43 | //! # use esp_hal::i2s::master::{I2s, Standard, DataFormat}; |
44 | | -//! # use esp_hal::dma_buffers; |
| 44 | +//! # use esp_hal::dma_buffers_chunk_size; |
45 | 45 | //! # {dma_channel} |
46 | | -//! let (mut rx_buffer, rx_descriptors, _, _) = dma_buffers!(4 * 4092, 0); |
| 46 | +//! let (mut rx_buffer, rx_descriptors, _, _) = dma_buffers_chunk_sizse!(4 * 4092, 0, 4092); |
47 | 47 | //! |
48 | 48 | //! let i2s = I2s::new( |
49 | 49 | //! peripherals.I2S0, |
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58 | 58 | //! .with_bclk(peripherals.GPIO1) |
59 | 59 | //! .with_ws(peripherals.GPIO2) |
60 | 60 | //! .with_din(peripherals.GPIO5) |
61 | | -//! .build(rx_descriptors); |
| 61 | +//! .build(); |
62 | 62 | //! |
63 | | -//! let mut transfer = i2s_rx.read_dma_circular(&mut rx_buffer)?; |
| 63 | +//! let mut transfer = i2s_rx.read( |
| 64 | +//! DmaRxStreamBuf::new(rx_descriptors, rx_buffer).unwrap(), |
| 65 | +//! 4092, |
| 66 | +//! )?; |
64 | 67 | //! |
65 | 68 | //! loop { |
66 | | -//! let avail = transfer.available()?; |
| 69 | +//! let avail = transfer.available_bytes(); |
67 | 70 | //! |
68 | 71 | //! if avail > 0 { |
69 | 72 | //! let mut rcv = [0u8; 5000]; |
70 | | -//! transfer.pop(&mut rcv[..avail])?; |
| 73 | +//! transfer.pop(&mut rcv[..avail]); |
71 | 74 | //! } |
72 | 75 | //! } |
73 | 76 | //! # } |
@@ -1004,6 +1007,12 @@ mod private { |
1004 | 1007 | self.regs().conf().modify(|_, w| w.tx_start().clear_bit()); |
1005 | 1008 | } |
1006 | 1009 |
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| 1010 | + fn rx_stop(&self) { |
| 1011 | + self.regs() |
| 1012 | + .rx_conf() |
| 1013 | + .modify(|_, w| w.rx_start().clear_bit()); |
| 1014 | + } |
| 1015 | + |
1007 | 1016 | fn wait_for_tx_done(&self) { |
1008 | 1017 | while self.regs().state().read().tx_idle().bit_is_clear() { |
1009 | 1018 | // wait |
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