Add light/deep sleep support for H2 (#4587)

* MVP for light/deep sleep with timer wakeup

The design is based on C6 implementation of esp-hal,
and the logic is based on H2 implementation of esp-idf.
It is worth noting that esp-idf implementation writes
to a lot of registers which are not documented in
H2 Technical Reference Manual -- these writes are not
added here, which does not break functionality.

Both light sleep and deep sleep seem to work in an
example app with BT connection, with wakeup on timer.
No other wakeup source is currently supported.

Some other limitations:
  * clock settings are not preserved through light sleep
  * peripheral clocks are not disabled in light sleep

* Add changelog entry

* Address lint issues

* Update esp-hal/CHANGELOG.md

Co-authored-by: Juraj Sadel <[email protected]>

* Enable the sleep_timer QA test

---------

Co-authored-by: Dániel Buga <[email protected]>
Co-authored-by: Juraj Sadel <[email protected]>

Author: 3 people

esp-hal/CHANGELOG.md

@@ -14,6 +14,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - Added blocking `send_break`, `wait_for_break` and `wait_for_break_with_timeout` for sending and detecting software breaks with the UART driver (#4284)
 - Added support for `RxBreakDetected` interrupt and `wait_for_break_async` for detecting software breaks asynchronously to the UART driver (#4284)
 - Unsafely expose GPIO pins that are only available on certain chip/module variants (#4520)
+- ESP32-H2: light sleep and deep sleep support with timer wakeup source (#4587)
 
 ### Changed
 - RMT: `SingleShotTxTransaction` has been renamed to `TxTransaction`. (#4302)

esp-hal/src/clock/clocks_ll/esp32h2.rs

@@ -124,11 +124,9 @@ pub(crate) fn esp32h2_rtc_update_to_xtal(freq: XtalClock, div: u8) {
     crate::rom::ets_update_cpu_frequency_rom(freq.mhz());
     // Set divider from XTAL to APB clock. Need to set divider to 1 (reg. value 0)
     // first.
+    clk_ll_cpu_set_divider(div as u32);
     clk_ll_ahb_set_divider(div as u32);
 
-    PCR::regs()
-        .cpu_freq_conf()
-        .modify(|_, w| unsafe { w.cpu_div_num().bits(div - 1) });
     // Switch clock source
     PCR::regs()
         .sysclk_conf()

esp-hal/src/rtc_cntl/mod.rs

@@ -113,7 +113,7 @@
 pub use self::rtc::SocResetReason;
 #[cfg(not(esp32))]
 use crate::efuse::Efuse;
-#[cfg(any(esp32, esp32s2, esp32s3, esp32c3, esp32c6, esp32c2))]
+#[cfg(any(esp32, esp32s2, esp32s3, esp32c3, esp32c6, esp32c2, esp32h2))]
 use crate::rtc_cntl::sleep::{RtcSleepConfig, WakeSource, WakeTriggers};
 use crate::{
     clock::{Clock, RtcClock},
@@ -123,7 +123,7 @@ use crate::{
     time::Duration,
 };
 // only include sleep where it's been implemented
-#[cfg(any(esp32, esp32s2, esp32s3, esp32c3, esp32c6, esp32c2))]
+#[cfg(any(esp32, esp32s2, esp32s3, esp32c3, esp32c6, esp32c2, esp32h2))]
 pub mod sleep;
 
 #[cfg_attr(esp32, path = "rtc/esp32.rs")]
@@ -403,23 +403,23 @@ impl<'d> Rtc<'d> {
     ///
     /// You can use the [`#[esp_hal::ram(persistent)]`][procmacros::ram]
     /// attribute to persist a variable though deep sleep.
-    #[cfg(any(esp32, esp32s2, esp32s3, esp32c3, esp32c6, esp32c2))]
+    #[cfg(any(esp32, esp32s2, esp32s3, esp32c3, esp32c6, esp32c2, esp32h2))]
     pub fn sleep_deep(&mut self, wake_sources: &[&dyn WakeSource]) -> ! {
         let config = RtcSleepConfig::deep();
         self.sleep(&config, wake_sources);
         unreachable!();
     }
 
     /// Enter light sleep and wake with the provided `wake_sources`.
-    #[cfg(any(esp32, esp32s2, esp32s3, esp32c3, esp32c6, esp32c2))]
+    #[cfg(any(esp32, esp32s2, esp32s3, esp32c3, esp32c6, esp32c2, esp32h2))]
     pub fn sleep_light(&mut self, wake_sources: &[&dyn WakeSource]) {
         let config = RtcSleepConfig::default();
         self.sleep(&config, wake_sources);
     }
 
     /// Enter sleep with the provided `config` and wake with the provided
     /// `wake_sources`.
-    #[cfg(any(esp32, esp32s2, esp32s3, esp32c3, esp32c6, esp32c2))]
+    #[cfg(any(esp32, esp32s2, esp32s3, esp32c3, esp32c6, esp32c2, esp32h2))]
     pub fn sleep(&mut self, config: &RtcSleepConfig, wake_sources: &[&dyn WakeSource]) {
         let mut config = *config;
         let mut wakeup_triggers = WakeTriggers::default();

esp-hal/src/rtc_cntl/rtc/esp32h2.rs

@@ -1,7 +1,13 @@
 use strum::FromRepr;
 
 use crate::{
-    clock::{RtcClock, RtcFastClock, RtcSlowClock, clocks_ll::regi2c_write_mask},
+    clock::{
+        RtcClock,
+        RtcFastClock,
+        RtcSlowClock,
+        XtalClock,
+        clocks_ll::{esp32h2_rtc_update_to_xtal, regi2c_write_mask},
+    },
     peripherals::{LP_AON, PMU},
     rtc_cntl::RtcCalSel,
 };
@@ -37,6 +43,13 @@ const I2C_PMU_OR_XPD_TRX: u8 = 15;
 const I2C_PMU_OR_XPD_TRX_MSB: u8 = 2;
 const I2C_PMU_OR_XPD_TRX_LSB: u8 = 2;
 
+const I2C_BIAS: u8 = 0x6a;
+const I2C_BIAS_HOSTID: u8 = 0;
+
+const I2C_BIAS_DREG_0P8: u8 = 0;
+const I2C_BIAS_DREG_0P8_MSB: u8 = 7;
+const I2C_BIAS_DREG_0P8_LSB: u8 = 4;
+
 pub(crate) fn init() {
     // * No peripheral reg i2c power up required on the target */
     regi2c_write_mask(
@@ -95,6 +108,14 @@ pub(crate) fn init() {
         I2C_PMU_OR_XPD_TRX_LSB,
         0,
     );
+    regi2c_write_mask(
+        I2C_BIAS,
+        I2C_BIAS_HOSTID,
+        I2C_BIAS_DREG_0P8,
+        I2C_BIAS_DREG_0P8_MSB,
+        I2C_BIAS_DREG_0P8_LSB,
+        8,
+    );
 
     let pmu = PMU::regs();
     unsafe {
@@ -110,6 +131,43 @@ pub(crate) fn init() {
         pmu.hp_sleep_lp_regulator0()
             .modify(|_, w| w.hp_sleep_lp_regulator_dbias().bits(26));
 
+        pmu.hp_sleep_dig_power().modify(|_, w| {
+            w.hp_sleep_vdd_spi_pd_en()
+                .set_bit()
+                .hp_sleep_pd_hp_wifi_pd_en()
+                .set_bit()
+                .hp_sleep_pd_hp_cpu_pd_en()
+                .set_bit()
+                .hp_sleep_pd_top_pd_en()
+                .set_bit()
+        });
+
+        pmu.hp_active_hp_ck_power().modify(|_, w| {
+            w.hp_active_xpd_bbpll()
+                .set_bit()
+                .hp_active_xpd_bb_i2c()
+                .set_bit()
+                .hp_active_xpd_bbpll_i2c()
+                .set_bit()
+        });
+
+        pmu.hp_active_sysclk().modify(|_, w| {
+            w.hp_active_icg_sys_clock_en()
+                .set_bit()
+                .hp_active_sys_clk_slp_sel()
+                .clear_bit()
+                .hp_active_icg_slp_sel()
+                .clear_bit()
+        });
+        pmu.hp_sleep_sysclk().modify(|_, w| {
+            w.hp_sleep_icg_sys_clock_en()
+                .clear_bit()
+                .hp_sleep_sys_clk_slp_sel()
+                .set_bit()
+                .hp_sleep_icg_slp_sel()
+                .set_bit()
+        });
+
         pmu.slp_wakeup_cntl5()
             .modify(|_, w| w.lp_ana_wait_target().bits(15));
         pmu.slp_wakeup_cntl7()
@@ -185,3 +243,85 @@ pub enum SocResetReason {
     /// Glitch on power resets the digital core
     CorePwrGlitch = 0x17,
 }
+
+bitfield::bitfield! {
+    /// Representation of `PMU_HP_{ACTIVE,SLEEP}_DIG_POWER_REG` registers.
+    #[derive(Clone, Copy, Default)]
+    pub struct HpDigPower(u32);
+
+    pub bool, vdd_spi_pd_en, set_vdd_spi_pd_en: 21;
+    pub bool, mem_dslp     , set_mem_dslp     : 22;
+    pub bool, modem_pd_en  , set_modem_pd_en  : 27;
+    pub bool, cpu_pd_en    , set_cpu_pd_en    : 29;
+    pub bool, top_pd_en    , set_top_pd_en    : 31;
+}
+
+bitfield::bitfield! {
+    /// Representation of `PMU_HP_{ACTIVE,SLEEP}_HP_CK_POWER_REG` registers.
+    #[derive(Clone, Copy, Default)]
+    pub struct HpClkPower(u32);
+
+    pub bool, xpd_bbpll    , set_xpd_bbpll    : 30;
+}
+
+bitfield::bitfield! {
+    /// Representation of `PMU_{HP_ACTIVE,HP_SLEEP,LP_SLEEP}_XTAL_REG` register.
+    #[derive(Clone, Copy, Default)]
+    pub struct XtalPower(u32);
+
+    pub bool, xpd_xtal     , set_xpd_xtal     : 31;
+}
+
+/// Combined HP system power settings.
+#[derive(Clone, Copy, Default)]
+pub struct HpSysPower {
+    pub dig_power: HpDigPower,
+    pub clk: HpClkPower,
+    pub xtal: XtalPower,
+}
+
+bitfield::bitfield! {
+    /// Representation of `PMU_{HP,LP}_SLEEP_LP_DIG_POWER_REG`.
+    #[derive(Clone, Copy, Default)]
+    pub struct LpDigPower(u32);
+
+    pub bool, bod_source_sel, set_bod_source_sel : 27;
+    pub u32, vddbat_mode, set_vddbat_mode : 29, 28;
+    pub u32, mem_dslp  , set_mem_dslp  : 30;
+
+}
+
+bitfield::bitfield! {
+    /// Representation of `PMU_{HP,LP}_SLEEP_LP_CK_POWER_REG`.
+    #[derive(Clone, Copy, Default)]
+    pub struct LpClkPower(u32);
+
+    pub u32, xpd_xtal32k, set_xpd_xtal32k: 28;
+    pub u32, xpd_fosc   , set_xpd_fosc   : 30;
+}
+
+/// Combined LP system power settings.
+#[derive(Clone, Copy, Default)]
+pub struct LpSysPower {
+    pub dig_power: LpDigPower,
+    pub clk_power: LpClkPower,
+    pub xtal: XtalPower,
+}
+
+bitfield::bitfield! {
+    /// Representation of `PMU_HP_{ACTIVE,SLEEP}_HP_SYS_CNTL_REG` register.
+    #[derive(Clone, Copy, Default)]
+    pub struct HpSysCntlReg(u32);
+
+    pub bool, uart_wakeup_en , set_uart_wakeup_en : 24;
+    pub bool, lp_pad_hold_all, set_lp_pad_hold_all: 25;
+    pub bool, hp_pad_hold_all, set_hp_pad_hold_all: 26;
+    pub bool, dig_pad_slp_sel, set_dig_pad_slp_sel: 27;
+    pub bool, dig_pause_wdt  , set_dig_pause_wdt  : 28;
+    pub bool, dig_cpu_stall  , set_dig_cpu_stall  : 29;
+}
+
+pub(crate) fn rtc_clk_cpu_freq_set_xtal() {
+    // rtc_clk_cpu_set_to_default_config
+    esp32h2_rtc_update_to_xtal(XtalClock::_32M, 1);
+}