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bjoernQbjoernQ
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QSPI tests (#2015)
* Add QSPI tests * Simplify * Add qspi_write_read test
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‎hil-test/Cargo.toml‎

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@@ -67,6 +67,18 @@ harness = false
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name = "lcd_cam_i8080_async"
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harness = false
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[[test]]
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name = "qspi_read"
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harness = false
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[[test]]
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name = "qspi_write"
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harness = false
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[[test]]
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name = "qspi_write_read"
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harness = false
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[[test]]
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name = "spi_full_duplex"
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harness = false

‎hil-test/tests/qspi_read.rs‎

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//! QSPI Read Test
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//!
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//! Following pins are used:
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//! MISO GPIO2
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//!
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//! GPIO GPIO3
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//!
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//! Connect MISO (GPIO2) and GPIO (GPIO3) pins.
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//% CHIPS: esp32 esp32c2 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3
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#![no_std]
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#![no_main]
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use esp_hal::{
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clock::{ClockControl, Clocks},
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dma::{Channel, Dma, DmaPriority, DmaRxBuf},
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dma_buffers,
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gpio::{GpioPin, Io, Level, Output},
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peripherals::Peripherals,
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prelude::*,
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spi::{
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master::{Address, Command, Spi, SpiDma},
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HalfDuplexMode,
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SpiDataMode,
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SpiMode,
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},
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system::SystemControl,
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Blocking,
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};
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use hil_test as _;
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cfg_if::cfg_if! {
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if #[cfg(any(
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feature = "esp32",
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feature = "esp32s2",
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))] {
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use esp_hal::dma::Spi2DmaChannel as DmaChannel0;
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} else {
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use esp_hal::dma::DmaChannel0;
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}
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}
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struct Context {
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spi: esp_hal::peripherals::SPI2,
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dma_channel: Channel<'static, DmaChannel0, Blocking>,
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miso: esp_hal::gpio::GpioPin<2>,
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miso_mirror: Output<'static, GpioPin<3>>,
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clocks: Clocks<'static>,
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}
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fn execute(
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mut spi: SpiDma<'static, esp_hal::peripherals::SPI2, DmaChannel0, HalfDuplexMode, Blocking>,
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mut miso_mirror: Output<'static, GpioPin<3>>,
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wanted: u8,
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) {
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const DMA_BUFFER_SIZE: usize = 4;
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let (buffer, descriptors, _, _) = dma_buffers!(DMA_BUFFER_SIZE, 0);
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let mut dma_rx_buf = DmaRxBuf::new(descriptors, buffer).unwrap();
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miso_mirror.set_low();
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let transfer = spi
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.read(
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SpiDataMode::Quad,
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Command::None,
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Address::None,
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0,
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dma_rx_buf,
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)
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.map_err(|e| e.0)
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.unwrap();
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(spi, dma_rx_buf) = transfer.wait();
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assert_eq!(dma_rx_buf.as_slice(), &[wanted; DMA_BUFFER_SIZE]);
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// SPI should read all '1's
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miso_mirror.set_high();
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let transfer = spi
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.read(
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SpiDataMode::Quad,
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Command::None,
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Address::None,
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0,
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dma_rx_buf,
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)
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.map_err(|e| e.0)
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.unwrap();
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(_, dma_rx_buf) = transfer.wait();
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assert_eq!(dma_rx_buf.as_slice(), &[0xFF; DMA_BUFFER_SIZE]);
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}
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#[cfg(test)]
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#[embedded_test::tests]
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mod tests {
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use super::*;
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#[init]
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fn init() -> Context {
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let peripherals = Peripherals::take();
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let system = SystemControl::new(peripherals.SYSTEM);
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let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
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let io = Io::new(peripherals.GPIO, peripherals.IO_MUX);
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let miso = io.pins.gpio2;
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let miso_mirror = Output::new(io.pins.gpio3, Level::High);
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let dma = Dma::new(peripherals.DMA);
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cfg_if::cfg_if! {
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if #[cfg(any(feature = "esp32", feature = "esp32s2"))] {
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let dma_channel = dma.spi2channel;
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} else {
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let dma_channel = dma.channel0;
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}
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}
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let dma_channel = dma_channel.configure(false, DmaPriority::Priority0);
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Context {
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spi: peripherals.SPI2,
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dma_channel,
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miso,
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miso_mirror,
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clocks,
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}
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}
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#[test]
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#[timeout(3)]
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fn test_spi_reads_correctly_from_gpio_pin_0(ctx: Context) {
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let spi = Spi::new_half_duplex(ctx.spi, 100.kHz(), SpiMode::Mode0, &ctx.clocks)
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.with_pins(
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esp_hal::gpio::NO_PIN,
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Some(ctx.miso),
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esp_hal::gpio::NO_PIN,
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esp_hal::gpio::NO_PIN,
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esp_hal::gpio::NO_PIN,
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esp_hal::gpio::NO_PIN,
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)
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.with_dma(ctx.dma_channel);
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// SPI should read '0b11101110'
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super::execute(spi, ctx.miso_mirror, 238);
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}
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#[test]
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#[timeout(3)]
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fn test_spi_reads_correctly_from_gpio_pin_1(ctx: Context) {
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let spi = Spi::new_half_duplex(ctx.spi, 100.kHz(), SpiMode::Mode0, &ctx.clocks)
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.with_pins(
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esp_hal::gpio::NO_PIN,
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esp_hal::gpio::NO_PIN,
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Some(ctx.miso),
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esp_hal::gpio::NO_PIN,
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esp_hal::gpio::NO_PIN,
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esp_hal::gpio::NO_PIN,
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)
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.with_dma(ctx.dma_channel);
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// SPI should read '0b11011101'
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super::execute(spi, ctx.miso_mirror, 221);
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}
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#[test]
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#[timeout(3)]
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fn test_spi_reads_correctly_from_gpio_pin_2(ctx: Context) {
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let spi = Spi::new_half_duplex(ctx.spi, 100.kHz(), SpiMode::Mode0, &ctx.clocks)
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.with_pins(
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esp_hal::gpio::NO_PIN,
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esp_hal::gpio::NO_PIN,
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esp_hal::gpio::NO_PIN,
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Some(ctx.miso),
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esp_hal::gpio::NO_PIN,
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esp_hal::gpio::NO_PIN,
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)
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.with_dma(ctx.dma_channel);
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// SPI should read '0b10111011'
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super::execute(spi, ctx.miso_mirror, 187);
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}
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#[test]
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#[timeout(3)]
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fn test_spi_reads_correctly_from_gpio_pin_3(ctx: Context) {
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let spi = Spi::new_half_duplex(ctx.spi, 100.kHz(), SpiMode::Mode0, &ctx.clocks)
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.with_pins(
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esp_hal::gpio::NO_PIN,
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esp_hal::gpio::NO_PIN,
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esp_hal::gpio::NO_PIN,
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esp_hal::gpio::NO_PIN,
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Some(ctx.miso),
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esp_hal::gpio::NO_PIN,
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)
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.with_dma(ctx.dma_channel);
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// SPI should read '0b01110111'
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super::execute(spi, ctx.miso_mirror, 119);
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}
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}

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