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C61: Add GPIO support, enable HIL test (#5248)
* C61: Add GPIO support, enable HIL test * rebase * changelog entries * Tweak documentation * format gpio metadata, add ZCD analog functions * rebase
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‎esp-hal/CHANGELOG.md‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -51,6 +51,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
5151
- Initial ESP32-C61 support (#5187, #5237)
5252
- Add support for ADC1 on ESP32C5. (#5215)
5353
- ESP32-C61: RNG (#5244)
54+
- C61: Add GPIO support (#5248)
5455

5556
### Changed
5657

‎esp-hal/Cargo.toml‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -104,15 +104,15 @@ ufmt-write = { version = "0.1", optional = true }
104104
# IMPORTANT:
105105
# Each supported device MUST have its PAC included below along with a
106106
# corresponding feature.
107-
esp32 = { version = "0.39", features = ["critical-section", "rt"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "405f40e" }
108-
esp32c2 = { version = "0.28", features = ["critical-section", "rt"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "405f40e" }
109-
esp32c3 = { version = "0.31", features = ["critical-section", "rt"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "405f40e" }
110-
esp32c5 = { version = "0.1", features = ["critical-section", "rt"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "405f40e" }
111-
esp32c6 = { version = "0.22", features = ["critical-section", "rt"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "405f40e" }
112-
esp32c61 = { version = "0.1", features = ["critical-section", "rt"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "405f40e" }
113-
esp32h2 = { version = "0.18", features = ["critical-section", "rt"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "405f40e" }
114-
esp32s2 = { version = "0.30", features = ["critical-section", "rt"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "405f40e" }
115-
esp32s3 = { version = "0.34", features = ["critical-section", "rt"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "405f40e" }
107+
esp32 = { version = "0.39", features = ["critical-section", "rt"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "663c742" }
108+
esp32c2 = { version = "0.28", features = ["critical-section", "rt"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "663c742" }
109+
esp32c3 = { version = "0.31", features = ["critical-section", "rt"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "663c742" }
110+
esp32c5 = { version = "0.1", features = ["critical-section", "rt"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "663c742" }
111+
esp32c6 = { version = "0.22", features = ["critical-section", "rt"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "663c742" }
112+
esp32c61 = { version = "0.1", features = ["critical-section", "rt"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "663c742" }
113+
esp32h2 = { version = "0.18", features = ["critical-section", "rt"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "663c742" }
114+
esp32s2 = { version = "0.30", features = ["critical-section", "rt"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "663c742" }
115+
esp32s3 = { version = "0.34", features = ["critical-section", "rt"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "663c742" }
116116

117117
[target.'cfg(target_arch = "riscv32")'.dependencies]
118118
riscv = { version = "0.15.0" }

‎esp-hal/README.md‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -72,7 +72,7 @@ For help getting started with this HAL, please refer to [The Rust on ESP Book] a
7272
| ECC | | ⚒️ | | ⚒️ | ⚒️ | | ⚒️ | | |
7373
| Ethernet | ❌ | | | | | | | | |
7474
| ETM | | | | [❌][5167] [^1] | ⚒️ | | ⚒️ | | |
75-
| GPIO | ✔️ | ✔️ | ✔️ | ⚒️ | ✔️ | | ✔️ | ✔️ | ✔️ |
75+
| GPIO | ✔️ | ✔️ | ✔️ | ⚒️ | ✔️ | ⚒️ | ✔️ | ✔️ | ✔️ |
7676
| HMAC | | | ⚒️ | [❌][5166] [^1] | ⚒️ | | ⚒️ | ⚒️ | ⚒️ |
7777
| I2C master | ✔️ | ✔️ | ✔️ | ✔️ | ✔️ | | ✔️ | ✔️ | ✔️ |
7878
| I2C slave | ❌ | | ❌ | [❌][5156] [^1] | ❌ | | ❌ | ❌ | ❌ |

‎esp-hal/src/gpio/interconnect.rs‎

Lines changed: 24 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -53,19 +53,22 @@
5353
//! [split](AnyPin::split) into signals. In this case you need to carefully
5454
//! ensure that only a single driver configures the split pin, by selectively
5555
//! [freezing](`InputSignal::freeze`) the signals.
56-
//!
57-
//! For example, if you want to route GPIO3 to both a Pulse Counter
58-
//! input and a [UART](crate::uart::Uart) RX line, you will need to make sure
59-
//! one of the signals is frozen, otherwise the driver that is configured later
60-
//! will overwrite the other driver's configuration. Configuring the signals on
61-
//! multiple cores is undefined behaviour unless you ensure the configuration
62-
//! does not happen at the same time.
63-
//!
56+
#![cfg_attr(
57+
uart_driver_supported,
58+
doc = "\n\nFor example, if you want to route GPIO3 to both a Pulse Counter
59+
input and a [UART](crate::uart::Uart) RX line, you will need to make sure
60+
one of the signals is frozen, otherwise the driver that is configured later
61+
will overwrite the other driver's configuration. Configuring the signals on
62+
multiple cores is undefined behaviour unless you ensure the configuration
63+
does not happen at the same time."
64+
)]
6465
//! ### Using pins and signals
6566
//!
6667
//! A GPIO pin can be configured either with a GPIO driver such as [`Input`], or
6768
//! by a peripheral driver using a pin assignment method such as
68-
//! [`Spi::with_mosi`]. The peripheral drivers' preferences can be overridden by
69+
#![cfg_attr(spi_master_driver_supported, doc = "[`Spi::with_mosi`].")]
70+
#![cfg_attr(not(spi_master_driver_supported), doc = "`Spi::with_mosi`.")]
71+
//! The peripheral drivers' preferences can be overridden by
6972
//! passing a pin driver to the peripheral driver. When converting a driver to
7073
//! signals, the underlying signals will be initially
7174
//! [frozen](InputSignal::freeze) to support this use case.
@@ -93,7 +96,10 @@
9396
//! - A GPIO output can be driven by only one peripheral output.
9497
//!
9598
//! [`GPIO0`]: crate::peripherals::GPIO0
96-
//! [`Spi::with_mosi`]: crate::spi::master::Spi::with_mosi
99+
#![cfg_attr(
100+
spi_master_driver_supported,
101+
doc = "[`Spi::with_mosi`]: crate::spi::master::Spi::with_mosi"
102+
)]
97103

98104
#[cfg(feature = "unstable")]
99105
use crate::gpio::{Input, Output};
@@ -855,6 +861,14 @@ impl<'d> OutputSignal<'d> {
855861

856862
#[doc(hidden)]
857863
#[instability::unstable]
864+
#[cfg_attr(
865+
not(any(
866+
i2c_master_driver_supported,
867+
spi_master_driver_supported,
868+
uart_driver_supported
869+
)),
870+
expect(unused)
871+
)]
858872
pub(crate) fn connect_with_guard(self, signal: crate::gpio::OutputSignal) -> PinGuard {
859873
signal.connect_to(&self);
860874
match self.pin {

‎esp-hal/src/gpio/mod.rs‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -351,7 +351,7 @@ impl TryFrom<usize> for AlternateFunction {
351351
#[instability::unstable]
352352
#[derive(Debug, Eq, PartialEq, Copy, Clone, Hash)]
353353
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
354-
#[cfg(not(any(esp32h2, esp32c5)))]
354+
#[cfg(not(any(esp32h2, esp32c5, esp32c61)))]
355355
pub enum RtcFunction {
356356
/// RTC mode.
357357
Rtc = 0,
@@ -364,7 +364,7 @@ pub enum RtcFunction {
364364

365365
/// Trait implemented by RTC pins
366366
#[instability::unstable]
367-
#[cfg(not(esp32c5))]
367+
#[cfg(not(any(esp32c5, esp32c61)))]
368368
pub trait RtcPin: Pin {
369369
/// RTC number of the pin
370370
#[cfg(any(xtensa, esp32h2))]
@@ -391,7 +391,7 @@ pub trait RtcPin: Pin {
391391
/// Trait implemented by RTC pins which support internal pull-up / pull-down
392392
/// resistors.
393393
#[instability::unstable]
394-
#[cfg(not(esp32c5))]
394+
#[cfg(not(any(esp32c5, esp32c61)))]
395395
pub trait RtcPinWithResistors: RtcPin {
396396
/// Enable/disable the internal pull-up resistor
397397
#[cfg(not(esp32h2))]
@@ -2202,7 +2202,7 @@ fn pin_does_not_support_function(pin: u8, function: &str) {
22022202
panic!("Pin {} is not an {}", pin, function)
22032203
}
22042204

2205-
#[cfg(not(esp32c5))]
2205+
#[cfg(not(any(esp32c5, esp32c61)))]
22062206
macro_rules! for_each_rtcio_pin {
22072207
(@impl $ident:ident, $target:ident, $gpio:ident, $code:tt) => {
22082208
if $ident.number() == $crate::peripherals::$gpio::NUMBER {
@@ -2225,7 +2225,7 @@ macro_rules! for_each_rtcio_pin {
22252225
};
22262226
}
22272227

2228-
#[cfg(not(any(esp32h2, esp32c5)))]
2228+
#[cfg(not(any(esp32h2, esp32c5, esp32c61)))]
22292229
macro_rules! for_each_rtcio_output_pin {
22302230
(@impl $ident:ident, $target:ident, $gpio:ident, $code:tt, $kind:literal) => {
22312231
if $ident.number() == $crate::peripherals::$gpio::NUMBER {
@@ -2257,7 +2257,7 @@ macro_rules! for_each_rtcio_output_pin {
22572257
};
22582258
}
22592259

2260-
#[cfg(not(esp32c5))]
2260+
#[cfg(not(any(esp32c5, esp32c61)))]
22612261
impl RtcPin for AnyPin<'_> {
22622262
#[cfg(any(xtensa, esp32h2))]
22632263
fn rtc_number(&self) -> u8 {
@@ -2287,7 +2287,7 @@ impl RtcPin for AnyPin<'_> {
22872287
}
22882288
}
22892289

2290-
#[cfg(not(esp32c5))]
2290+
#[cfg(not(any(esp32c5, esp32c61)))]
22912291
impl RtcPinWithResistors for AnyPin<'_> {
22922292
#[cfg(not(esp32h2))]
22932293
fn rtcio_pullup(&self, enable: bool) {

‎esp-hal/src/interrupt/mod.rs‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -368,7 +368,6 @@ pub(super) fn map_raw(core: Cpu, interrupt: Interrupt, cpu_interrupt: u32) {
368368
}
369369

370370
/// Get cpu interrupt assigned to peripheral interrupt
371-
#[cfg_attr(esp32c61, expect(unused))] // TODO: remove when more peripherals are supported
372371
pub(crate) fn mapped_to(cpu: Cpu, interrupt: Interrupt) -> Option<CpuInterrupt> {
373372
mapped_to_raw(cpu, interrupt as u32)
374373
}

‎esp-hal/src/soc/esp32c61/mod.rs‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,4 +15,7 @@ pub(crate) mod regi2c;
1515

1616
pub(crate) use esp32c61 as pac;
1717

18-
pub(crate) fn pre_init() {}
18+
pub(crate) fn pre_init() {
19+
// this is hacky, but for some reason we must reset the output enable register manually
20+
crate::peripherals::GPIO::regs().enable().reset();
21+
}

‎esp-lp-hal/Cargo.toml‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -45,9 +45,9 @@ nb = { version = "1.1.0", optional = true }
4545
procmacros = { version = "0.21.0", package = "esp-hal-procmacros", path = "../esp-hal-procmacros" }
4646
riscv = { version = "0.15", features = ["critical-section-single-hart"] }
4747
esp-metadata-generated = { version = "0.3.0", path = "../esp-metadata-generated" }
48-
esp32c6-lp = { version = "0.3.0", features = ["critical-section"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "405f40e" }
49-
esp32s2-ulp = { version = "0.3.0", features = ["critical-section"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "405f40e" }
50-
esp32s3-ulp = { version = "0.3.0", features = ["critical-section"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "405f40e" }
48+
esp32c6-lp = { version = "0.3.0", features = ["critical-section"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "663c742" }
49+
esp32s2-ulp = { version = "0.3.0", features = ["critical-section"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "663c742" }
50+
esp32s3-ulp = { version = "0.3.0", features = ["critical-section"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "663c742" }
5151

5252
[dev-dependencies]
5353
panic-halt = "0.2.0"

‎esp-metadata-generated/src/_build_script_utils.rs‎

Lines changed: 138 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2977,6 +2977,7 @@ impl Chip {
29772977
"soc_has_ecdsa",
29782978
"soc_has_efuse",
29792979
"soc_has_etm",
2980+
"soc_has_gpio",
29802981
"soc_has_hp_apm",
29812982
"soc_has_hp_sys",
29822983
"soc_has_i2c_ana_mst",
@@ -3021,13 +3022,20 @@ impl Chip {
30213022
"rom_crc_le",
30223023
"rom_crc_be",
30233024
"rom_md5_bsd",
3025+
"gpio_driver_supported",
30243026
"interrupts_driver_supported",
30253027
"rng_driver_supported",
30263028
"soc_driver_supported",
30273029
"systimer_driver_supported",
30283030
"timergroup_driver_supported",
30293031
"timergroup_timg0",
30303032
"timergroup_timg1",
3033+
"gpio_gpio_function=\"1\"",
3034+
"gpio_constant_0_input=\"96\"",
3035+
"gpio_constant_1_input=\"64\"",
3036+
"gpio_func_in_sel_offset=\"0\"",
3037+
"gpio_input_signal_max=\"100\"",
3038+
"gpio_output_signal_max=\"256\"",
30313039
"interrupts_status_registers=\"3\"",
30323040
"interrupt_controller=\"clic\"",
30333041
"rng_apb_cycle_wait_num=\"16\"",
@@ -3074,6 +3082,7 @@ impl Chip {
30743082
"cargo:rustc-cfg=soc_has_ecdsa",
30753083
"cargo:rustc-cfg=soc_has_efuse",
30763084
"cargo:rustc-cfg=soc_has_etm",
3085+
"cargo:rustc-cfg=soc_has_gpio",
30773086
"cargo:rustc-cfg=soc_has_hp_apm",
30783087
"cargo:rustc-cfg=soc_has_hp_sys",
30793088
"cargo:rustc-cfg=soc_has_i2c_ana_mst",
@@ -3118,13 +3127,20 @@ impl Chip {
31183127
"cargo:rustc-cfg=rom_crc_le",
31193128
"cargo:rustc-cfg=rom_crc_be",
31203129
"cargo:rustc-cfg=rom_md5_bsd",
3130+
"cargo:rustc-cfg=gpio_driver_supported",
31213131
"cargo:rustc-cfg=interrupts_driver_supported",
31223132
"cargo:rustc-cfg=rng_driver_supported",
31233133
"cargo:rustc-cfg=soc_driver_supported",
31243134
"cargo:rustc-cfg=systimer_driver_supported",
31253135
"cargo:rustc-cfg=timergroup_driver_supported",
31263136
"cargo:rustc-cfg=timergroup_timg0",
31273137
"cargo:rustc-cfg=timergroup_timg1",
3138+
"cargo:rustc-cfg=gpio_gpio_function=\"1\"",
3139+
"cargo:rustc-cfg=gpio_constant_0_input=\"96\"",
3140+
"cargo:rustc-cfg=gpio_constant_1_input=\"64\"",
3141+
"cargo:rustc-cfg=gpio_func_in_sel_offset=\"0\"",
3142+
"cargo:rustc-cfg=gpio_input_signal_max=\"100\"",
3143+
"cargo:rustc-cfg=gpio_output_signal_max=\"256\"",
31283144
"cargo:rustc-cfg=interrupts_status_registers=\"3\"",
31293145
"cargo:rustc-cfg=interrupt_controller=\"clic\"",
31303146
"cargo:rustc-cfg=rng_apb_cycle_wait_num=\"16\"",
@@ -3176,7 +3192,128 @@ impl Chip {
31763192
),
31773193
],
31783194
},
3179-
pins: &[],
3195+
pins: &[
3196+
PinInfo {
3197+
pin: 0,
3198+
limitations: &[],
3199+
},
3200+
PinInfo {
3201+
pin: 1,
3202+
limitations: &[],
3203+
},
3204+
PinInfo {
3205+
pin: 2,
3206+
limitations: &[],
3207+
},
3208+
PinInfo {
3209+
pin: 3,
3210+
limitations: &["strapping", "jtag"],
3211+
},
3212+
PinInfo {
3213+
pin: 4,
3214+
limitations: &["strapping", "jtag"],
3215+
},
3216+
PinInfo {
3217+
pin: 5,
3218+
limitations: &["jtag"],
3219+
},
3220+
PinInfo {
3221+
pin: 6,
3222+
limitations: &["jtag"],
3223+
},
3224+
PinInfo {
3225+
pin: 7,
3226+
limitations: &["strapping"],
3227+
},
3228+
PinInfo {
3229+
pin: 8,
3230+
limitations: &["strapping"],
3231+
},
3232+
PinInfo {
3233+
pin: 9,
3234+
limitations: &["strapping"],
3235+
},
3236+
PinInfo {
3237+
pin: 10,
3238+
limitations: &["bootloader_uart"],
3239+
},
3240+
PinInfo {
3241+
pin: 11,
3242+
limitations: &["bootloader_uart"],
3243+
},
3244+
PinInfo {
3245+
pin: 12,
3246+
limitations: &["usb_jtag"],
3247+
},
3248+
PinInfo {
3249+
pin: 13,
3250+
limitations: &["usb_jtag"],
3251+
},
3252+
PinInfo {
3253+
pin: 14,
3254+
limitations: &["spi_flash"],
3255+
},
3256+
PinInfo {
3257+
pin: 15,
3258+
limitations: &["spi_flash"],
3259+
},
3260+
PinInfo {
3261+
pin: 16,
3262+
limitations: &["spi_flash"],
3263+
},
3264+
PinInfo {
3265+
pin: 17,
3266+
limitations: &["spi_flash"],
3267+
},
3268+
PinInfo {
3269+
pin: 18,
3270+
limitations: &["spi_flash"],
3271+
},
3272+
PinInfo {
3273+
pin: 19,
3274+
limitations: &["spi_flash"],
3275+
},
3276+
PinInfo {
3277+
pin: 20,
3278+
limitations: &["spi_flash"],
3279+
},
3280+
PinInfo {
3281+
pin: 21,
3282+
limitations: &["spi_flash"],
3283+
},
3284+
PinInfo {
3285+
pin: 22,
3286+
limitations: &[],
3287+
},
3288+
PinInfo {
3289+
pin: 23,
3290+
limitations: &[],
3291+
},
3292+
PinInfo {
3293+
pin: 24,
3294+
limitations: &[],
3295+
},
3296+
PinInfo {
3297+
pin: 25,
3298+
limitations: &[],
3299+
},
3300+
PinInfo {
3301+
pin: 26,
3302+
limitations: &[],
3303+
},
3304+
PinInfo {
3305+
pin: 27,
3306+
limitations: &[],
3307+
},
3308+
PinInfo {
3309+
pin: 28,
3310+
limitations: &[],
3311+
},
3312+
PinInfo {
3313+
pin: 29,
3314+
limitations: &[],
3315+
},
3316+
],
31803317
},
31813318
Self::Esp32h2 => Config {
31823319
architecture: "riscv",

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