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feat: restart tx
1 parent 1dbe551 commit 51bc882

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3 files changed

+25
-12
lines changed

3 files changed

+25
-12
lines changed

esp-hal/src/dma/buffers.rs

Lines changed: 1 addition & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1540,7 +1540,7 @@ impl DmaTxStreamBufView {
15401540
let dma_start = self.descriptor_idx * chunk_size + self.descriptor_offset;
15411541
let dma_end = truncate_by(dma_start + buf.len(), dma_size);
15421542

1543-
if dma_start < dma_end {
1543+
if dma_start <= dma_end {
15441544
self.buf.buffer[dma_start..dma_end].copy_from_slice(buf);
15451545
} else {
15461546
self.buf.buffer[dma_start..].copy_from_slice(&buf[..dma_size - dma_start]);
@@ -1576,11 +1576,6 @@ impl DmaTxStreamBufView {
15761576
}
15771577
}
15781578

1579-
info!(
1580-
"self.descriptor_idx: {}, self.descriptor_offset: {}, dma_start: {}, dma_end: {}",
1581-
self.descriptor_idx, self.descriptor_offset, dma_start, dma_end
1582-
);
1583-
15841579
bytes_to_fill
15851580
}
15861581
}

esp-hal/src/dma/mod.rs

Lines changed: 12 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2989,6 +2989,13 @@ pub(crate) mod asynch {
29892989
{
29902990
self.tx.clear_out(DmaTxInterrupt::Done);
29912991
Poll::Ready(Ok(()))
2992+
} else if self
2993+
.tx
2994+
.pending_out_interrupts()
2995+
.contains(DmaTxInterrupt::TotalEof)
2996+
{
2997+
self.tx.clear_interrupts();
2998+
return Poll::Ready(Err(DmaError::Late));
29922999
} else if self
29933000
.tx
29943001
.pending_out_interrupts()
@@ -2998,8 +3005,11 @@ pub(crate) mod asynch {
29983005
Poll::Ready(Err(DmaError::DescriptorError))
29993006
} else {
30003007
self.tx.waker().register(cx.waker());
3001-
self.tx
3002-
.listen_out(DmaTxInterrupt::Done | DmaTxInterrupt::DescriptorError);
3008+
self.tx.listen_out(
3009+
DmaTxInterrupt::Done
3010+
| DmaTxInterrupt::DescriptorError
3011+
| DmaTxInterrupt::TotalEof,
3012+
);
30033013
Poll::Pending
30043014
}
30053015
}

esp-hal/src/i2s/master.rs

Lines changed: 12 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1704,13 +1704,10 @@ pub mod asynch {
17041704
dma::{
17051705
DmaEligible,
17061706
DmaTxBuffer,
1707-
ReadBuffer,
17081707
RxCircularState,
1709-
TxCircularState,
17101708
WriteBuffer,
1711-
asynch::{DmaRxDoneChFuture, DmaRxFuture, DmaTxDoneChFuture, DmaTxFuture},
1709+
asynch::{DmaRxDoneChFuture, DmaRxFuture, DmaTxDoneChFuture},
17121710
},
1713-
i2s::master::private::RegBlock,
17141711
};
17151712

17161713
impl<'d> I2sTx<'d, Async> {
@@ -1788,6 +1785,17 @@ pub mod asynch {
17881785
self.i2s_tx.tx_channel.is_done()
17891786
}
17901787

1788+
/// Stops and restarts the DMA transfer.
1789+
pub fn restart(self) -> Result<Self, Error> {
1790+
let (i2s, buf) = self.stop();
1791+
i2s.write(buf)
1792+
}
1793+
1794+
/// Checks if the DMA transfer has an error.
1795+
pub fn has_error(&self) -> bool {
1796+
self.i2s_tx.tx_channel.has_error()
1797+
}
1798+
17911799
/// Waits for any DMA process to be made.
17921800
pub async fn process(&mut self) -> Result<(), Error> {
17931801
DmaTxDoneChFuture::new(&mut self.i2s_tx.tx_channel).await?;

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