Refactor MMU related code into its own module

Author: EliteTK

esp-hal/src/soc/esp32s3/mmu.rs

@@ -0,0 +1,45 @@
+//! Thin MMU bindings
+//!
+//! More general information about the MMU can be found here:
+//! https://docs.espressif.com/projects/esp-idf/en/stable/esp32s3/api-reference/system/mm.html#introduction
+
+const DBUS_VADDR_BASE: u32 = 0x3C000000;
+const DR_REG_MMU_TABLE: u32 = 0x600C5000;
+const ENTRY_INVALID: u32 = 1 << 14;
+const ICACHE_MMU_SIZE: usize = 0x800;
+const TABLE_SIZE: usize = ICACHE_MMU_SIZE / core::mem::size_of::<u32>();
+
+pub(super) const ENTRY_ACCESS_SPIRAM: u32 = 1 << 15;
+pub(super) const PAGE_SIZE: usize = 0x10000;
+
+extern "C" {
+    /// Set DCache mmu mapping.
+    ///
+    /// [`ext_ram`]: u32 ENTRY_ACCESS_FLASH for flash, ENTRY_ACCESS_SPIRAM for spiram, ENTRY_INVALID for invalid.
+    /// [`vaddr`]: u32 Virtual address in CPU address space.
+    /// [`paddr`]: u32 Physical address in external memory. Should be aligned by psize.
+    /// [`psize`]: u32 Page size of DCache, in kilobytes. Should be 64 here.
+    /// [`num`]: u32 Pages to be set.
+    /// [`fixes`]: u32 0 for physical pages grow with virtual pages, other for virtual pages map to same physical page.
+    pub(super) fn cache_dbus_mmu_set(
+        ext_ram: u32,
+        vaddr: u32,
+        paddr: u32,
+        psize: u32,
+        num: u32,
+        fixed: u32,
+    ) -> i32;
+}
+
+#[procmacros::ram]
+pub(super) fn last_mapped_index() -> Option<usize> {
+    let mmu_table_ptr = DR_REG_MMU_TABLE as *const u32;
+    (0..TABLE_SIZE)
+        .rev()
+        .find(|&i| unsafe { mmu_table_ptr.add(i).read_volatile() } != ENTRY_INVALID)
+}
+
+#[procmacros::ram]
+pub(super) fn index_to_data_address(index: usize) -> u32 {
+    DBUS_VADDR_BASE + (PAGE_SIZE * index) as u32
+}

esp-hal/src/soc/esp32s3/mod.rs

@@ -23,6 +23,7 @@ crate::unstable_module! {
 }
 pub mod cpu_control;
 pub mod gpio;
+mod mmu;
 pub mod peripherals;
 
 /// The name of the chip ("esp32s3") as `&str`

esp-hal/src/soc/esp32s3/psram.rs

@@ -57,11 +57,10 @@
 //! # }
 //! ```
 
+use super::mmu;
 use crate::peripherals::{EXTMEM, IO_MUX, SPI0, SPI1};
 pub use crate::soc::psram_common::*;
 
-const EXTMEM_ORIGIN: u32 = 0x3C000000;
-
 /// Frequency of flash memory
 #[derive(Copy, Clone, Debug, Default)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
@@ -125,7 +124,6 @@ pub(crate) fn init_psram(config: PsramConfig) {
     const CONFIG_ESP32S3_DATA_CACHE_SIZE: u32 = 0x8000;
     const CONFIG_ESP32S3_DCACHE_ASSOCIATED_WAYS: u8 = 8;
     const CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE: u8 = 32;
-    const MMU_ACCESS_SPIRAM: u32 = 1 << 15;
     const START_PAGE: u32 = 0;
 
     extern "C" {
@@ -144,48 +142,16 @@ pub(crate) fn init_psram(config: PsramConfig) {
         );
 
         fn Cache_Resume_DCache(param: u32);
-
-        /// Set DCache mmu mapping.
-        ///
-        /// [`ext_ram`]: u32 DPORT_MMU_ACCESS_FLASH for flash, DPORT_MMU_ACCESS_SPIRAM for spiram, DPORT_MMU_INVALID for invalid.
-        /// [`vaddr`]: u32 Virtual address in CPU address space.
-        /// [`paddr`]: u32 Physical address in external memory. Should be aligned by psize.
-        /// [`psize`]: u32 Page size of DCache, in kilobytes. Should be 64 here.
-        /// [`num`]: u32 Pages to be set.
-        /// [`fixes`]: u32 0 for physical pages grow with virtual pages, other for virtual pages map to same physical page.
-        fn cache_dbus_mmu_set(
-            ext_ram: u32,
-            vaddr: u32,
-            paddr: u32,
-            psize: u32,
-            num: u32,
-            fixed: u32,
-        ) -> i32;
     }
 
     let start = unsafe {
-        const MMU_PAGE_SIZE: u32 = 0x10000;
-        const ICACHE_MMU_SIZE: usize = 0x800;
-        const FLASH_MMU_TABLE_SIZE: usize = ICACHE_MMU_SIZE / core::mem::size_of::<u32>();
-        const MMU_INVALID: u32 = 1 << 14;
-        const DR_REG_MMU_TABLE: u32 = 0x600C5000;
 
         // calculate the PSRAM start address to map
         // the linker scripts can produce a gap between mapped IROM and DROM segments
         // bigger than a flash page - i.e. we will see an unmapped memory slot
         // start from the end and find the last mapped flash page
-        //
-        // More general information about the MMU can be found here:
-        // https://docs.espressif.com/projects/esp-idf/en/stable/esp32s3/api-reference/system/mm.html#introduction
-        let mmu_table_ptr = DR_REG_MMU_TABLE as *const u32;
-        let mut mapped_pages = 0;
-        for i in (0..FLASH_MMU_TABLE_SIZE).rev() {
-            if mmu_table_ptr.add(i).read_volatile() != MMU_INVALID {
-                mapped_pages = (i + 1) as u32;
-                break;
-            }
-        }
-        let start = EXTMEM_ORIGIN + (MMU_PAGE_SIZE * mapped_pages);
+        let psram_start_index = mmu::last_mapped_index().map(|e| e + 1).unwrap_or(0);
+        let start = mmu::index_to_data_address(psram_start_index);
         debug!("PSRAM start address = {:x}", start);
 
         // Configure the mode of instruction cache : cache size, cache line size.
@@ -205,8 +171,8 @@ pub(crate) fn init_psram(config: PsramConfig) {
             CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE,
         );
 
-        if cache_dbus_mmu_set(
-            MMU_ACCESS_SPIRAM,
+        if mmu::cache_dbus_mmu_set(
+            mmu::ENTRY_ACCESS_SPIRAM,
             start,
             START_PAGE << 16,
             64,