Suggestions for improving initial draft for LP core interrupts on the esp32c6 #3724
aarch64angel
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Thanks for looking into this! Very cool that you have this working already! As you suggested, I would ditch the unstable |
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Hello!
I've put together a small proof of concept implementation of LP core interrupt handling on the esp32c6.
fork
It's not very sophisticated or well tested yet, I'm mainly just looking for architectural suggestions and or issues. It currently relies on the unstable 'riscv-interrupt-m' feature, that will probably have to be replaced by an intermediate naked asm function.
I tried to include references for every assumption that I made.
Again, any suggestion is welcome.
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