From 3c94d767981c0fb41b6136ce52f8d3edaa36fcb3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?D=C3=A1niel=20Buga?= Date: Wed, 15 Oct 2025 16:54:03 +0200 Subject: [PATCH 1/3] Make the memory map less special --- .../src/_build_script_utils.rs | 29 +++---- .../src/_generated_esp32.rs | 16 ++-- .../src/_generated_esp32c2.rs | 16 ++-- .../src/_generated_esp32c3.rs | 16 ++-- .../src/_generated_esp32c6.rs | 16 ++-- .../src/_generated_esp32h2.rs | 16 ++-- .../src/_generated_esp32s2.rs | 16 ++-- .../src/_generated_esp32s3.rs | 16 ++-- esp-metadata/devices/esp32.toml | 6 +- esp-metadata/devices/esp32c2.toml | 7 +- esp-metadata/devices/esp32c3.toml | 7 +- esp-metadata/devices/esp32c6.toml | 7 +- esp-metadata/devices/esp32h2.toml | 7 +- esp-metadata/devices/esp32s2.toml | 7 +- esp-metadata/devices/esp32s3.toml | 7 +- esp-metadata/src/cfg.rs | 1 + esp-metadata/src/cfg/soc.rs | 55 ++++++++++++- esp-metadata/src/lib.rs | 77 ++++--------------- 18 files changed, 175 insertions(+), 147 deletions(-) diff --git a/esp-metadata-generated/src/_build_script_utils.rs b/esp-metadata-generated/src/_build_script_utils.rs index cb8570e95c..013a832659 100644 --- a/esp-metadata-generated/src/_build_script_utils.rs +++ b/esp-metadata-generated/src/_build_script_utils.rs @@ -270,6 +270,7 @@ impl Chip { "soc_rc_fast_clk_default_is_set", "soc_rc_slow_clock=\"150000\"", "soc_rc_slow_clock_is_set", + "has_dram_region", "soc_has_multiple_xtal_options", "aes_endianness_configurable", "gpio_has_bank_1", @@ -299,7 +300,6 @@ impl Chip { "uart_ram_size=\"128\"", "bt_controller=\"btdm\"", "phy_combo_module", - "has_dram_region", ], cfgs: &[ "cargo:rustc-cfg=esp32", @@ -432,6 +432,7 @@ impl Chip { "cargo:rustc-cfg=soc_rc_fast_clk_default_is_set", "cargo:rustc-cfg=soc_rc_slow_clock=\"150000\"", "cargo:rustc-cfg=soc_rc_slow_clock_is_set", + "cargo:rustc-cfg=has_dram_region", "cargo:rustc-cfg=soc_has_multiple_xtal_options", "cargo:rustc-cfg=aes_endianness_configurable", "cargo:rustc-cfg=gpio_has_bank_1", @@ -461,7 +462,6 @@ impl Chip { "cargo:rustc-cfg=uart_ram_size=\"128\"", "cargo:rustc-cfg=bt_controller=\"btdm\"", "cargo:rustc-cfg=phy_combo_module", - "cargo:rustc-cfg=has_dram_region", ], }, Self::Esp32c2 => Config { @@ -557,6 +557,7 @@ impl Chip { "soc_rc_fast_clk_default_is_set", "soc_rc_slow_clock=\"136000\"", "soc_rc_slow_clock_is_set", + "has_dram_region", "soc_has_multiple_xtal_options", "assist_debug_has_sp_monitor", "gpio_gpio_function=\"1\"", @@ -586,7 +587,6 @@ impl Chip { "uart_ram_size=\"128\"", "bt_controller=\"npl\"", "phy_combo_module", - "has_dram_region", ], cfgs: &[ "cargo:rustc-cfg=esp32c2", @@ -678,6 +678,7 @@ impl Chip { "cargo:rustc-cfg=soc_rc_fast_clk_default_is_set", "cargo:rustc-cfg=soc_rc_slow_clock=\"136000\"", "cargo:rustc-cfg=soc_rc_slow_clock_is_set", + "cargo:rustc-cfg=has_dram_region", "cargo:rustc-cfg=soc_has_multiple_xtal_options", "cargo:rustc-cfg=assist_debug_has_sp_monitor", "cargo:rustc-cfg=gpio_gpio_function=\"1\"", @@ -707,7 +708,6 @@ impl Chip { "cargo:rustc-cfg=uart_ram_size=\"128\"", "cargo:rustc-cfg=bt_controller=\"npl\"", "cargo:rustc-cfg=phy_combo_module", - "cargo:rustc-cfg=has_dram_region", ], }, Self::Esp32c3 => Config { @@ -819,6 +819,7 @@ impl Chip { "soc_rc_fast_clk_default_is_set", "soc_rc_slow_clock=\"136000\"", "soc_rc_slow_clock_is_set", + "has_dram_region", "soc_xtal_frequency=\"40\"", "aes_dma", "aes_dma_mode_ecb", @@ -873,7 +874,6 @@ impl Chip { "phy_combo_module", "phy_backed_up_digital_register_count=\"21\"", "phy_backed_up_digital_register_count_is_set", - "has_dram_region", ], cfgs: &[ "cargo:rustc-cfg=esp32c3", @@ -981,6 +981,7 @@ impl Chip { "cargo:rustc-cfg=soc_rc_fast_clk_default_is_set", "cargo:rustc-cfg=soc_rc_slow_clock=\"136000\"", "cargo:rustc-cfg=soc_rc_slow_clock_is_set", + "cargo:rustc-cfg=has_dram_region", "cargo:rustc-cfg=soc_xtal_frequency=\"40\"", "cargo:rustc-cfg=aes_dma", "cargo:rustc-cfg=aes_dma_mode_ecb", @@ -1035,7 +1036,6 @@ impl Chip { "cargo:rustc-cfg=phy_combo_module", "cargo:rustc-cfg=phy_backed_up_digital_register_count=\"21\"", "cargo:rustc-cfg=phy_backed_up_digital_register_count_is_set", - "cargo:rustc-cfg=has_dram_region", ], }, Self::Esp32c6 => Config { @@ -1199,6 +1199,7 @@ impl Chip { "soc_rc_fast_clk_default_is_set", "soc_rc_slow_clock=\"136000\"", "soc_rc_slow_clock_is_set", + "has_dram_region", "soc_xtal_frequency=\"40\"", "aes_dma", "aes_dma_mode_ecb", @@ -1258,7 +1259,6 @@ impl Chip { "wifi_has_wifi6", "bt_controller=\"npl\"", "phy_combo_module", - "has_dram_region", ], cfgs: &[ "cargo:rustc-cfg=esp32c6", @@ -1418,6 +1418,7 @@ impl Chip { "cargo:rustc-cfg=soc_rc_fast_clk_default_is_set", "cargo:rustc-cfg=soc_rc_slow_clock=\"136000\"", "cargo:rustc-cfg=soc_rc_slow_clock_is_set", + "cargo:rustc-cfg=has_dram_region", "cargo:rustc-cfg=soc_xtal_frequency=\"40\"", "cargo:rustc-cfg=aes_dma", "cargo:rustc-cfg=aes_dma_mode_ecb", @@ -1477,7 +1478,6 @@ impl Chip { "cargo:rustc-cfg=wifi_has_wifi6", "cargo:rustc-cfg=bt_controller=\"npl\"", "cargo:rustc-cfg=phy_combo_module", - "cargo:rustc-cfg=has_dram_region", ], }, Self::Esp32h2 => Config { @@ -1618,6 +1618,7 @@ impl Chip { "soc_rc_fast_clk_default_is_set", "soc_rc_slow_clock=\"136000\"", "soc_rc_slow_clock_is_set", + "has_dram_region", "soc_xtal_frequency=\"32\"", "aes_dma", "aes_dma_mode_ecb", @@ -1671,7 +1672,6 @@ impl Chip { "uart_ram_size=\"128\"", "uart_peripheral_controls_mem_clk", "bt_controller=\"npl\"", - "has_dram_region", ], cfgs: &[ "cargo:rustc-cfg=esp32h2", @@ -1808,6 +1808,7 @@ impl Chip { "cargo:rustc-cfg=soc_rc_fast_clk_default_is_set", "cargo:rustc-cfg=soc_rc_slow_clock=\"136000\"", "cargo:rustc-cfg=soc_rc_slow_clock_is_set", + "cargo:rustc-cfg=has_dram_region", "cargo:rustc-cfg=soc_xtal_frequency=\"32\"", "cargo:rustc-cfg=aes_dma", "cargo:rustc-cfg=aes_dma_mode_ecb", @@ -1861,7 +1862,6 @@ impl Chip { "cargo:rustc-cfg=uart_ram_size=\"128\"", "cargo:rustc-cfg=uart_peripheral_controls_mem_clk", "cargo:rustc-cfg=bt_controller=\"npl\"", - "cargo:rustc-cfg=has_dram_region", ], }, Self::Esp32s2 => Config { @@ -1997,6 +1997,7 @@ impl Chip { "soc_rc_fast_clk_default_is_set", "soc_rc_slow_clock=\"90000\"", "soc_rc_slow_clock_is_set", + "has_dram_region", "soc_xtal_frequency=\"40\"", "aes_dma", "aes_dma_mode_ecb", @@ -2043,7 +2044,6 @@ impl Chip { "timergroup_default_clock_source=\"0\"", "timergroup_default_clock_source_is_set", "uart_ram_size=\"128\"", - "has_dram_region", ], cfgs: &[ "cargo:rustc-cfg=esp32s2", @@ -2175,6 +2175,7 @@ impl Chip { "cargo:rustc-cfg=soc_rc_fast_clk_default_is_set", "cargo:rustc-cfg=soc_rc_slow_clock=\"90000\"", "cargo:rustc-cfg=soc_rc_slow_clock_is_set", + "cargo:rustc-cfg=has_dram_region", "cargo:rustc-cfg=soc_xtal_frequency=\"40\"", "cargo:rustc-cfg=aes_dma", "cargo:rustc-cfg=aes_dma_mode_ecb", @@ -2221,7 +2222,6 @@ impl Chip { "cargo:rustc-cfg=timergroup_default_clock_source=\"0\"", "cargo:rustc-cfg=timergroup_default_clock_source_is_set", "cargo:rustc-cfg=uart_ram_size=\"128\"", - "cargo:rustc-cfg=has_dram_region", ], }, Self::Esp32s3 => Config { @@ -2370,6 +2370,7 @@ impl Chip { "soc_rc_fast_clk_default_is_set", "soc_rc_slow_clock=\"136000\"", "soc_rc_slow_clock_is_set", + "has_dram_region", "soc_xtal_frequency=\"40\"", "aes_dma", "aes_dma_mode_ecb", @@ -2425,7 +2426,6 @@ impl Chip { "phy_combo_module", "phy_backed_up_digital_register_count=\"21\"", "phy_backed_up_digital_register_count_is_set", - "has_dram_region", ], cfgs: &[ "cargo:rustc-cfg=esp32s3", @@ -2570,6 +2570,7 @@ impl Chip { "cargo:rustc-cfg=soc_rc_fast_clk_default_is_set", "cargo:rustc-cfg=soc_rc_slow_clock=\"136000\"", "cargo:rustc-cfg=soc_rc_slow_clock_is_set", + "cargo:rustc-cfg=has_dram_region", "cargo:rustc-cfg=soc_xtal_frequency=\"40\"", "cargo:rustc-cfg=aes_dma", "cargo:rustc-cfg=aes_dma_mode_ecb", @@ -2625,7 +2626,6 @@ impl Chip { "cargo:rustc-cfg=phy_combo_module", "cargo:rustc-cfg=phy_backed_up_digital_register_count=\"21\"", "cargo:rustc-cfg=phy_backed_up_digital_register_count_is_set", - "cargo:rustc-cfg=has_dram_region", ], }, } @@ -2773,6 +2773,7 @@ pub fn emit_check_cfg_directives() { println!("cargo:rustc-check-cfg=cfg(soc_ref_tick_hz_is_set)"); println!("cargo:rustc-check-cfg=cfg(soc_rc_fast_clk_default_is_set)"); println!("cargo:rustc-check-cfg=cfg(soc_rc_slow_clock_is_set)"); + println!("cargo:rustc-check-cfg=cfg(has_dram_region)"); println!("cargo:rustc-check-cfg=cfg(soc_has_multiple_xtal_options)"); println!("cargo:rustc-check-cfg=cfg(aes_endianness_configurable)"); println!("cargo:rustc-check-cfg=cfg(gpio_has_bank_1)"); diff --git a/esp-metadata-generated/src/_generated_esp32.rs b/esp-metadata-generated/src/_generated_esp32.rs index 7c80c3da65..6778fdf1de 100644 --- a/esp-metadata-generated/src/_generated_esp32.rs +++ b/esp-metadata-generated/src/_generated_esp32.rs @@ -262,14 +262,6 @@ macro_rules! property { true }; } -/// Macro to get the address range of the given memory region. -#[macro_export] -#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))] -macro_rules! memory_range { - ("DRAM") => { - 1073405952..1073741824 - }; -} #[macro_export] #[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))] macro_rules! for_each_soc_xtal_options { @@ -620,6 +612,14 @@ macro_rules! implement_peripheral_clocks { } }; } +/// Macro to get the address range of the given memory region. +#[macro_export] +#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))] +macro_rules! memory_range { + ("DRAM") => { + 1073405952..1073741824 + }; +} #[macro_export] #[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))] macro_rules! for_each_aes_key_length { diff --git a/esp-metadata-generated/src/_generated_esp32c2.rs b/esp-metadata-generated/src/_generated_esp32c2.rs index 8d71bef595..5a0102fe7e 100644 --- a/esp-metadata-generated/src/_generated_esp32c2.rs +++ b/esp-metadata-generated/src/_generated_esp32c2.rs @@ -208,14 +208,6 @@ macro_rules! property { true }; } -/// Macro to get the address range of the given memory region. -#[macro_export] -#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))] -macro_rules! memory_range { - ("DRAM") => { - 1070202880..1070465024 - }; -} #[macro_export] #[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))] macro_rules! for_each_soc_xtal_options { @@ -424,6 +416,14 @@ macro_rules! implement_peripheral_clocks { } }; } +/// Macro to get the address range of the given memory region. +#[macro_export] +#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))] +macro_rules! memory_range { + ("DRAM") => { + 1070202880..1070465024 + }; +} #[macro_export] #[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))] macro_rules! for_each_sha_algorithm { diff --git a/esp-metadata-generated/src/_generated_esp32c3.rs b/esp-metadata-generated/src/_generated_esp32c3.rs index 83d4f92082..5d711e684b 100644 --- a/esp-metadata-generated/src/_generated_esp32c3.rs +++ b/esp-metadata-generated/src/_generated_esp32c3.rs @@ -277,14 +277,6 @@ macro_rules! property { stringify!(21) }; } -/// Macro to get the address range of the given memory region. -#[macro_export] -#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))] -macro_rules! memory_range { - ("DRAM") => { - 1070071808..1070465024 - }; -} #[macro_export] #[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))] macro_rules! for_each_soc_xtal_options { @@ -614,6 +606,14 @@ macro_rules! implement_peripheral_clocks { } }; } +/// Macro to get the address range of the given memory region. +#[macro_export] +#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))] +macro_rules! memory_range { + ("DRAM") => { + 1070071808..1070465024 + }; +} #[macro_export] #[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))] macro_rules! for_each_aes_key_length { diff --git a/esp-metadata-generated/src/_generated_esp32c6.rs b/esp-metadata-generated/src/_generated_esp32c6.rs index e23b23ce3b..0607cb2cd5 100644 --- a/esp-metadata-generated/src/_generated_esp32c6.rs +++ b/esp-metadata-generated/src/_generated_esp32c6.rs @@ -283,14 +283,6 @@ macro_rules! property { true }; } -/// Macro to get the address range of the given memory region. -#[macro_export] -#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))] -macro_rules! memory_range { - ("DRAM") => { - 1082130432..1082654720 - }; -} #[macro_export] #[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))] macro_rules! for_each_soc_xtal_options { @@ -727,6 +719,14 @@ macro_rules! implement_peripheral_clocks { } }; } +/// Macro to get the address range of the given memory region. +#[macro_export] +#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))] +macro_rules! memory_range { + ("DRAM") => { + 1082130432..1082654720 + }; +} #[macro_export] #[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))] macro_rules! for_each_aes_key_length { diff --git a/esp-metadata-generated/src/_generated_esp32h2.rs b/esp-metadata-generated/src/_generated_esp32h2.rs index 96c96c6fb5..08c9539be7 100644 --- a/esp-metadata-generated/src/_generated_esp32h2.rs +++ b/esp-metadata-generated/src/_generated_esp32h2.rs @@ -268,14 +268,6 @@ macro_rules! property { false }; } -/// Macro to get the address range of the given memory region. -#[macro_export] -#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))] -macro_rules! memory_range { - ("DRAM") => { - 1082130432..1082458112 - }; -} #[macro_export] #[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))] macro_rules! for_each_soc_xtal_options { @@ -704,6 +696,14 @@ macro_rules! implement_peripheral_clocks { } }; } +/// Macro to get the address range of the given memory region. +#[macro_export] +#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))] +macro_rules! memory_range { + ("DRAM") => { + 1082130432..1082458112 + }; +} #[macro_export] #[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))] macro_rules! for_each_aes_key_length { diff --git a/esp-metadata-generated/src/_generated_esp32s2.rs b/esp-metadata-generated/src/_generated_esp32s2.rs index 39d741ceb4..df525706e8 100644 --- a/esp-metadata-generated/src/_generated_esp32s2.rs +++ b/esp-metadata-generated/src/_generated_esp32s2.rs @@ -268,14 +268,6 @@ macro_rules! property { false }; } -/// Macro to get the address range of the given memory region. -#[macro_export] -#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))] -macro_rules! memory_range { - ("DRAM") => { - 1073414144..1073741824 - }; -} #[macro_export] #[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))] macro_rules! for_each_soc_xtal_options { @@ -724,6 +716,14 @@ macro_rules! implement_peripheral_clocks { } }; } +/// Macro to get the address range of the given memory region. +#[macro_export] +#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))] +macro_rules! memory_range { + ("DRAM") => { + 1073414144..1073741824 + }; +} #[macro_export] #[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))] macro_rules! for_each_aes_key_length { diff --git a/esp-metadata-generated/src/_generated_esp32s3.rs b/esp-metadata-generated/src/_generated_esp32s3.rs index 4f0cdf20b5..1b09e360e1 100644 --- a/esp-metadata-generated/src/_generated_esp32s3.rs +++ b/esp-metadata-generated/src/_generated_esp32s3.rs @@ -271,14 +271,6 @@ macro_rules! property { stringify!(21) }; } -/// Macro to get the address range of the given memory region. -#[macro_export] -#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))] -macro_rules! memory_range { - ("DRAM") => { - 1070104576..1070596096 - }; -} #[macro_export] #[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))] macro_rules! for_each_soc_xtal_options { @@ -738,6 +730,14 @@ macro_rules! implement_peripheral_clocks { } }; } +/// Macro to get the address range of the given memory region. +#[macro_export] +#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))] +macro_rules! memory_range { + ("DRAM") => { + 1070104576..1070596096 + }; +} #[macro_export] #[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))] macro_rules! for_each_aes_key_length { diff --git a/esp-metadata/devices/esp32.toml b/esp-metadata/devices/esp32.toml index 8d9702a88c..9291c52ca1 100644 --- a/esp-metadata/devices/esp32.toml +++ b/esp-metadata/devices/esp32.toml @@ -98,14 +98,16 @@ symbols = [ "ulp_supported", ] -memory = [{ name = "dram", start = 0x3FFA_E000, end = 0x4000_0000 }] - [device.soc] ref_tick_hz = 1_000_000 rc_fast_clk_default = 8_500_000 rc_slow_clock = 150_000 xtal_options = [26, 40] +memory_map = { ranges = [ + { name = "dram", start = 0x3FFA_E000, end = 0x4000_0000 }, +] } + # PeripheralClockControl templates. # # Clock control code is generated by recursively substituting fields into the `clk_en_template` and `rst_template` templates. diff --git a/esp-metadata/devices/esp32c2.toml b/esp-metadata/devices/esp32c2.toml index 3d51f6f11f..67e2ef4964 100644 --- a/esp-metadata/devices/esp32c2.toml +++ b/esp-metadata/devices/esp32c2.toml @@ -77,13 +77,16 @@ symbols = [ "gpio_support_deepsleep_wakeup", ] -memory = [{ name = "dram", start = 0x3FCA_0000, end = 0x3FCE_0000 }] - [device.soc] cpu_has_csr_pc = true rc_fast_clk_default = 17_500_000 rc_slow_clock = 136_000 xtal_options = [26, 40] + +memory_map = { ranges = [ + { name = "dram", start = 0x3FCA_0000, end = 0x3FCE_0000 }, +] } + peripheral_clocks = { templates = [ # templates { name = "clk_en_template", value = "{{control}}::regs().{{clk_en_register}}().modify(|_, w| w.{{clk_en_field}}().bit(enable));" }, diff --git a/esp-metadata/devices/esp32c3.toml b/esp-metadata/devices/esp32c3.toml index 4eb58eab78..5da6b25b4f 100644 --- a/esp-metadata/devices/esp32c3.toml +++ b/esp-metadata/devices/esp32c3.toml @@ -85,13 +85,16 @@ symbols = [ "gpio_support_deepsleep_wakeup", ] -memory = [{ name = "dram", start = 0x3FC8_0000, end = 0x3FCE_0000 }] - [device.soc] cpu_has_csr_pc = true rc_fast_clk_default = 17_500_000 rc_slow_clock = 136_000 xtal_options = [40] + +memory_map = { ranges = [ + { name = "dram", start = 0x3FC8_0000, end = 0x3FCE_0000 }, +] } + peripheral_clocks = { templates = [ # templates { name = "clk_en_template", value = "{{control}}::regs().{{clk_en_register}}().modify(|_, w| w.{{clk_en_field}}().bit(enable));" }, diff --git a/esp-metadata/devices/esp32c6.toml b/esp-metadata/devices/esp32c6.toml index b111902759..a3530189c1 100644 --- a/esp-metadata/devices/esp32c6.toml +++ b/esp-metadata/devices/esp32c6.toml @@ -127,14 +127,17 @@ symbols = [ "pm_support_ext1_wakeup", ] -memory = [{ name = "dram", start = 0x4080_0000, end = 0x4088_0000 }] - [device.soc] cpu_has_csr_pc = true cpu_has_prv_mode = true rc_fast_clk_default = 17_500_000 rc_slow_clock = 136_000 xtal_options = [40] + +memory_map = { ranges = [ + { name = "dram", start = 0x4080_0000, end = 0x4088_0000 }, +] } + peripheral_clocks = { templates = [ # templates { name = "default_clk_en_template", value = "{{control}}::regs().{{conf_register}}().modify(|_, w| w.{{clk_en_field}}().bit(enable));" }, diff --git a/esp-metadata/devices/esp32h2.toml b/esp-metadata/devices/esp32h2.toml index 2952f7c1c5..33441e582b 100644 --- a/esp-metadata/devices/esp32h2.toml +++ b/esp-metadata/devices/esp32h2.toml @@ -106,14 +106,17 @@ symbols = [ "rom_md5_bsd", ] -memory = [{ name = "dram", start = 0x4080_0000, end = 0x4085_0000 }] - [device.soc] cpu_has_csr_pc = true cpu_has_prv_mode = true rc_fast_clk_default = 8_500_000 rc_slow_clock = 136_000 xtal_options = [32] + +memory_map = { ranges = [ + { name = "dram", start = 0x4080_0000, end = 0x4085_0000 }, +] } + peripheral_clocks = { templates = [ # templates { name = "default_clk_en_template", value = "{{control}}::regs().{{conf_register}}().modify(|_, w| w.{{clk_en_field}}().bit(enable));" }, diff --git a/esp-metadata/devices/esp32s2.toml b/esp-metadata/devices/esp32s2.toml index 1d4c7e70d4..ccdce1da81 100644 --- a/esp-metadata/devices/esp32s2.toml +++ b/esp-metadata/devices/esp32s2.toml @@ -100,13 +100,16 @@ symbols = [ "riscv_coproc_supported", ] -memory = [{ name = "dram", start = 0x3FFB_0000, end = 0x4000_0000 }] - [device.soc] ref_tick_hz = 1_000_000 rc_fast_clk_default = 8_500_000 rc_slow_clock = 90_000 xtal_options = [40] + +memory_map = { ranges = [ + { name = "dram", start = 0x3FFB_0000, end = 0x4000_0000 }, +] } + peripheral_clocks = { templates = [ # templates { name = "clk_en_template", value = "{{control}}::regs().{{clk_en_register}}().modify(|_, w| w.{{clk_en_field}}().bit(enable));" }, diff --git a/esp-metadata/devices/esp32s3.toml b/esp-metadata/devices/esp32s3.toml index 011955cd9d..4f23252f7f 100644 --- a/esp-metadata/devices/esp32s3.toml +++ b/esp-metadata/devices/esp32s3.toml @@ -110,12 +110,15 @@ symbols = [ "riscv_coproc_supported", ] -memory = [{ name = "dram", start = 0x3FC8_8000, end = 0x3FD0_0000 }] - [device.soc] rc_fast_clk_default = 17_500_000 rc_slow_clock = 136_000 xtal_options = [40] + +memory_map = { ranges = [ + { name = "dram", start = 0x3FC8_8000, end = 0x3FD0_0000 }, +] } + peripheral_clocks = { templates = [ # templates { name = "clk_en_template", value = "{{control}}::regs().{{clk_en_register}}().modify(|_, w| w.{{clk_en_field}}().bit(enable));" }, diff --git a/esp-metadata/src/cfg.rs b/esp-metadata/src/cfg.rs index 81a8fe03eb..974abe1659 100644 --- a/esp-metadata/src/cfg.rs +++ b/esp-metadata/src/cfg.rs @@ -296,6 +296,7 @@ driver_configs![ xtal_options: Vec, #[serde(default)] peripheral_clocks: PeripheralClocks, + memory_map: MemoryMap, } }, diff --git a/esp-metadata/src/cfg/soc.rs b/esp-metadata/src/cfg/soc.rs index 008d99daa5..cf71b76d73 100644 --- a/esp-metadata/src/cfg/soc.rs +++ b/esp-metadata/src/cfg/soc.rs @@ -1,10 +1,11 @@ -use std::{collections::HashMap, str::FromStr}; +use std::{collections::HashMap, ops::Range, str::FromStr}; use anyhow::{Context, Result}; use convert_case::{Boundary, Case, Casing, pattern}; use proc_macro2::TokenStream; +use quote::quote; -use crate::cfg::Value; +use crate::{cfg::Value, number}; impl super::SocProperties { pub(super) fn computed_properties(&self) -> impl Iterator { @@ -26,6 +27,54 @@ impl super::SocProperties { } } +/// Memory region. +#[derive(Debug, Clone, PartialEq, Eq, serde::Deserialize, serde::Serialize)] +pub struct MemoryRange { + name: String, + #[serde(flatten)] + range: Range, +} + +/// Memory regions. +#[derive(Debug, Clone, PartialEq, Eq, serde::Deserialize, serde::Serialize)] +pub struct MemoryMap { + pub ranges: Vec, +} + +impl super::GenericProperty for MemoryMap { + fn macros(&self) -> Option { + let region_branches = self.ranges.iter().map(|region| { + let name = region.name.to_uppercase(); + let start = number(region.range.start as usize); + let end = number(region.range.end as usize); + + quote! { + ( #name ) => { + #start .. #end + }; + } + }); + + Some(quote! { + /// Macro to get the address range of the given memory region. + #[macro_export] + #[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))] + macro_rules! memory_range { + #(#region_branches)* + } + }) + } + + fn cfgs(&self) -> Option> { + Some( + self.ranges + .iter() + .map(|region| format!("has_{}_region", region.name.to_lowercase())) + .collect(), + ) + } +} + /// A named template. Can contain `{{placeholder}}` placeholders that will be substituted with /// actual values. #[derive(Debug, Clone, PartialEq, Eq, serde::Deserialize, serde::Serialize)] @@ -125,7 +174,7 @@ impl PeripheralClocks { }) .collect::>>()?; - Ok(quote::quote! { + Ok(quote! { /// Implement the `Peripheral` enum and enable/disable/reset functions. /// /// This macro is intended to be placed in `esp_hal::system`. diff --git a/esp-metadata/src/lib.rs b/esp-metadata/src/lib.rs index a5d3cd7d0d..a790fb6d89 100644 --- a/esp-metadata/src/lib.rs +++ b/esp-metadata/src/lib.rs @@ -274,7 +274,6 @@ struct Device { peripherals: Vec, symbols: Vec, - memory: Vec, // Peripheral driver configuration: #[serde(flatten)] @@ -320,7 +319,6 @@ impl Config { trm: String::new(), peripherals: Vec::new(), symbols: Vec::new(), - memory: Vec::new(), peri_config: PeriConfig::default(), }, all_symbols: OnceLock::new(), @@ -372,14 +370,6 @@ impl Config { &self.device.symbols } - /// Memory regions. - /// - /// Will be available as env-variables `REGION--START` / - /// `REGION--END` - pub fn memory(&self) -> &[MemoryRegion] { - &self.device.memory - } - /// All configuration values for the device. pub fn all(&self) -> &[String] { self.all_symbols.get_or_init(|| { @@ -457,26 +447,7 @@ impl Config { } fn generate_properties(&self) -> TokenStream { - let mut tokens = TokenStream::new(); - let chip_name = self.name(); - // Public API, can't use a private macro: - tokens.extend(quote! { - /// The name of the chip as `&str` - /// - /// # Example - /// - /// ```rust, no_run - /// use esp_hal::chip; - /// let chip_name = chip!(); - #[doc = concat!("assert_eq!(chip_name, ", chip!(), ")")] - /// ``` - #[macro_export] - #[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))] - macro_rules! chip { - () => { #chip_name }; - } - }); // Translate the chip properties into a macro that can be used in esp-hal: let arch = self.device.arch.as_ref(); @@ -522,8 +493,22 @@ impl Config { } }); - // Not public API, can use a private macro: - tokens.extend(quote! { + quote! { + /// The name of the chip as `&str` + /// + /// # Example + /// + /// ```rust, no_run + /// use esp_hal::chip; + /// let chip_name = chip!(); + #[doc = concat!("assert_eq!(chip_name, ", chip!(), ")")] + /// ``` + #[macro_export] + #[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))] + macro_rules! chip { + () => { #chip_name }; + } + /// The properties of this chip and its drivers. #[macro_export] #[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))] @@ -535,32 +520,9 @@ impl Config { ("trm") => { #trm }; #(#peripheral_properties)* } - }); - - let region_branches = self.memory().iter().map(|region| { - let name = region.name.to_uppercase(); - let start = number(region.start as usize); - let end = number(region.end as usize); - - quote! { - ( #name ) => { - #start .. #end - }; - } - }); - - tokens.extend(quote! { - /// Macro to get the address range of the given memory region. - #[macro_export] - #[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))] - macro_rules! memory_range { - #(#region_branches)* - } #(#macros)* - }); - - tokens + } } fn generate_gpios(&self) -> TokenStream { @@ -667,11 +629,6 @@ impl Config { cfgs.push(symbol.replace('.', "_")); } - // Define env-vars for all memory regions - for memory in self.memory() { - cfgs.push(format!("has_{}_region", memory.name.to_lowercase())); - } - cfgs } From 9d13ce027445f378a84556fc917e5972f23a0b1a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?D=C3=A1niel=20Buga?= Date: Wed, 15 Oct 2025 17:22:02 +0200 Subject: [PATCH 2/3] Add dram2_uninit to metadata --- esp-hal/ld/esp32/memory.x | 2 +- esp-metadata-generated/src/_build_script_utils.rs | 15 +++++++++++++++ esp-metadata-generated/src/_generated_esp32.rs | 9 +++++++++ esp-metadata-generated/src/_generated_esp32c2.rs | 9 +++++++++ esp-metadata-generated/src/_generated_esp32c3.rs | 9 +++++++++ esp-metadata-generated/src/_generated_esp32c6.rs | 9 +++++++++ esp-metadata-generated/src/_generated_esp32h2.rs | 9 +++++++++ esp-metadata-generated/src/_generated_esp32s2.rs | 9 +++++++++ esp-metadata-generated/src/_generated_esp32s3.rs | 9 +++++++++ esp-metadata/devices/esp32.toml | 1 + esp-metadata/devices/esp32c2.toml | 1 + esp-metadata/devices/esp32c3.toml | 1 + esp-metadata/devices/esp32c6.toml | 1 + esp-metadata/devices/esp32h2.toml | 1 + esp-metadata/devices/esp32s2.toml | 1 + esp-metadata/devices/esp32s3.toml | 1 + esp-metadata/src/cfg/soc.rs | 7 +++++++ hil-test/Cargo.toml | 7 +++++++ 18 files changed, 100 insertions(+), 1 deletion(-) diff --git a/esp-hal/ld/esp32/memory.x b/esp-hal/ld/esp32/memory.x index 5807c5bdd7..74dc01267d 100644 --- a/esp-hal/ld/esp32/memory.x +++ b/esp-hal/ld/esp32/memory.x @@ -34,7 +34,7 @@ MEMORY reserved_rom_stack_pro : ORIGIN = 0x3ffe1320, len = 11264 reserved_rom_stack_app : ORIGIN = 0x3ffe5230, len = 11264 - dram2_seg : ORIGIN = 0x3ffe7e30, len = 98767 /* the rest of DRAM after the rom data segments and rom stacks in the middle */ + dram2_seg : ORIGIN = 0x3ffe7e30, len = 98768 /* the rest of DRAM after the rom data segments and rom stacks in the middle */ /* external flash The 0x20 offset is a convenience for the app binary image generation. diff --git a/esp-metadata-generated/src/_build_script_utils.rs b/esp-metadata-generated/src/_build_script_utils.rs index 013a832659..7860ef7e56 100644 --- a/esp-metadata-generated/src/_build_script_utils.rs +++ b/esp-metadata-generated/src/_build_script_utils.rs @@ -271,6 +271,7 @@ impl Chip { "soc_rc_slow_clock=\"150000\"", "soc_rc_slow_clock_is_set", "has_dram_region", + "has_dram2_uninit_region", "soc_has_multiple_xtal_options", "aes_endianness_configurable", "gpio_has_bank_1", @@ -433,6 +434,7 @@ impl Chip { "cargo:rustc-cfg=soc_rc_slow_clock=\"150000\"", "cargo:rustc-cfg=soc_rc_slow_clock_is_set", "cargo:rustc-cfg=has_dram_region", + "cargo:rustc-cfg=has_dram2_uninit_region", "cargo:rustc-cfg=soc_has_multiple_xtal_options", "cargo:rustc-cfg=aes_endianness_configurable", "cargo:rustc-cfg=gpio_has_bank_1", @@ -558,6 +560,7 @@ impl Chip { "soc_rc_slow_clock=\"136000\"", "soc_rc_slow_clock_is_set", "has_dram_region", + "has_dram2_uninit_region", "soc_has_multiple_xtal_options", "assist_debug_has_sp_monitor", "gpio_gpio_function=\"1\"", @@ -679,6 +682,7 @@ impl Chip { "cargo:rustc-cfg=soc_rc_slow_clock=\"136000\"", "cargo:rustc-cfg=soc_rc_slow_clock_is_set", "cargo:rustc-cfg=has_dram_region", + "cargo:rustc-cfg=has_dram2_uninit_region", "cargo:rustc-cfg=soc_has_multiple_xtal_options", "cargo:rustc-cfg=assist_debug_has_sp_monitor", "cargo:rustc-cfg=gpio_gpio_function=\"1\"", @@ -820,6 +824,7 @@ impl Chip { "soc_rc_slow_clock=\"136000\"", "soc_rc_slow_clock_is_set", "has_dram_region", + "has_dram2_uninit_region", "soc_xtal_frequency=\"40\"", "aes_dma", "aes_dma_mode_ecb", @@ -982,6 +987,7 @@ impl Chip { "cargo:rustc-cfg=soc_rc_slow_clock=\"136000\"", "cargo:rustc-cfg=soc_rc_slow_clock_is_set", "cargo:rustc-cfg=has_dram_region", + "cargo:rustc-cfg=has_dram2_uninit_region", "cargo:rustc-cfg=soc_xtal_frequency=\"40\"", "cargo:rustc-cfg=aes_dma", "cargo:rustc-cfg=aes_dma_mode_ecb", @@ -1200,6 +1206,7 @@ impl Chip { "soc_rc_slow_clock=\"136000\"", "soc_rc_slow_clock_is_set", "has_dram_region", + "has_dram2_uninit_region", "soc_xtal_frequency=\"40\"", "aes_dma", "aes_dma_mode_ecb", @@ -1419,6 +1426,7 @@ impl Chip { "cargo:rustc-cfg=soc_rc_slow_clock=\"136000\"", "cargo:rustc-cfg=soc_rc_slow_clock_is_set", "cargo:rustc-cfg=has_dram_region", + "cargo:rustc-cfg=has_dram2_uninit_region", "cargo:rustc-cfg=soc_xtal_frequency=\"40\"", "cargo:rustc-cfg=aes_dma", "cargo:rustc-cfg=aes_dma_mode_ecb", @@ -1619,6 +1627,7 @@ impl Chip { "soc_rc_slow_clock=\"136000\"", "soc_rc_slow_clock_is_set", "has_dram_region", + "has_dram2_uninit_region", "soc_xtal_frequency=\"32\"", "aes_dma", "aes_dma_mode_ecb", @@ -1809,6 +1818,7 @@ impl Chip { "cargo:rustc-cfg=soc_rc_slow_clock=\"136000\"", "cargo:rustc-cfg=soc_rc_slow_clock_is_set", "cargo:rustc-cfg=has_dram_region", + "cargo:rustc-cfg=has_dram2_uninit_region", "cargo:rustc-cfg=soc_xtal_frequency=\"32\"", "cargo:rustc-cfg=aes_dma", "cargo:rustc-cfg=aes_dma_mode_ecb", @@ -1998,6 +2008,7 @@ impl Chip { "soc_rc_slow_clock=\"90000\"", "soc_rc_slow_clock_is_set", "has_dram_region", + "has_dram2_uninit_region", "soc_xtal_frequency=\"40\"", "aes_dma", "aes_dma_mode_ecb", @@ -2176,6 +2187,7 @@ impl Chip { "cargo:rustc-cfg=soc_rc_slow_clock=\"90000\"", "cargo:rustc-cfg=soc_rc_slow_clock_is_set", "cargo:rustc-cfg=has_dram_region", + "cargo:rustc-cfg=has_dram2_uninit_region", "cargo:rustc-cfg=soc_xtal_frequency=\"40\"", "cargo:rustc-cfg=aes_dma", "cargo:rustc-cfg=aes_dma_mode_ecb", @@ -2371,6 +2383,7 @@ impl Chip { "soc_rc_slow_clock=\"136000\"", "soc_rc_slow_clock_is_set", "has_dram_region", + "has_dram2_uninit_region", "soc_xtal_frequency=\"40\"", "aes_dma", "aes_dma_mode_ecb", @@ -2571,6 +2584,7 @@ impl Chip { "cargo:rustc-cfg=soc_rc_slow_clock=\"136000\"", "cargo:rustc-cfg=soc_rc_slow_clock_is_set", "cargo:rustc-cfg=has_dram_region", + "cargo:rustc-cfg=has_dram2_uninit_region", "cargo:rustc-cfg=soc_xtal_frequency=\"40\"", "cargo:rustc-cfg=aes_dma", "cargo:rustc-cfg=aes_dma_mode_ecb", @@ -2774,6 +2788,7 @@ pub fn emit_check_cfg_directives() { println!("cargo:rustc-check-cfg=cfg(soc_rc_fast_clk_default_is_set)"); println!("cargo:rustc-check-cfg=cfg(soc_rc_slow_clock_is_set)"); println!("cargo:rustc-check-cfg=cfg(has_dram_region)"); + println!("cargo:rustc-check-cfg=cfg(has_dram2_uninit_region)"); println!("cargo:rustc-check-cfg=cfg(soc_has_multiple_xtal_options)"); println!("cargo:rustc-check-cfg=cfg(aes_endianness_configurable)"); println!("cargo:rustc-check-cfg=cfg(gpio_has_bank_1)"); diff --git a/esp-metadata-generated/src/_generated_esp32.rs b/esp-metadata-generated/src/_generated_esp32.rs index 6778fdf1de..9b3aeac781 100644 --- a/esp-metadata-generated/src/_generated_esp32.rs +++ b/esp-metadata-generated/src/_generated_esp32.rs @@ -619,6 +619,15 @@ macro_rules! memory_range { ("DRAM") => { 1073405952..1073741824 }; + (size as str, "DRAM") => { + "335872" + }; + ("DRAM2_UNINIT") => { + 1073643056..1073741824 + }; + (size as str, "DRAM2_UNINIT") => { + "98768" + }; } #[macro_export] #[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))] diff --git a/esp-metadata-generated/src/_generated_esp32c2.rs b/esp-metadata-generated/src/_generated_esp32c2.rs index 5a0102fe7e..9158576409 100644 --- a/esp-metadata-generated/src/_generated_esp32c2.rs +++ b/esp-metadata-generated/src/_generated_esp32c2.rs @@ -423,6 +423,15 @@ macro_rules! memory_range { ("DRAM") => { 1070202880..1070465024 }; + (size as str, "DRAM") => { + "262144" + }; + ("DRAM2_UNINIT") => { + 1070393344..1070459760 + }; + (size as str, "DRAM2_UNINIT") => { + "66416" + }; } #[macro_export] #[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))] diff --git a/esp-metadata-generated/src/_generated_esp32c3.rs b/esp-metadata-generated/src/_generated_esp32c3.rs index 5d711e684b..8d10b8dd8d 100644 --- a/esp-metadata-generated/src/_generated_esp32c3.rs +++ b/esp-metadata-generated/src/_generated_esp32c3.rs @@ -613,6 +613,15 @@ macro_rules! memory_range { ("DRAM") => { 1070071808..1070465024 }; + (size as str, "DRAM") => { + "393216" + }; + ("DRAM2_UNINIT") => { + 1070392320..1070458640 + }; + (size as str, "DRAM2_UNINIT") => { + "66320" + }; } #[macro_export] #[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))] diff --git a/esp-metadata-generated/src/_generated_esp32c6.rs b/esp-metadata-generated/src/_generated_esp32c6.rs index 0607cb2cd5..96f3af0587 100644 --- a/esp-metadata-generated/src/_generated_esp32c6.rs +++ b/esp-metadata-generated/src/_generated_esp32c6.rs @@ -726,6 +726,15 @@ macro_rules! memory_range { ("DRAM") => { 1082130432..1082654720 }; + (size as str, "DRAM") => { + "524288" + }; + ("DRAM2_UNINIT") => { + 1082582544..1082648080 + }; + (size as str, "DRAM2_UNINIT") => { + "65536" + }; } #[macro_export] #[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))] diff --git a/esp-metadata-generated/src/_generated_esp32h2.rs b/esp-metadata-generated/src/_generated_esp32h2.rs index 08c9539be7..1213c10a7a 100644 --- a/esp-metadata-generated/src/_generated_esp32h2.rs +++ b/esp-metadata-generated/src/_generated_esp32h2.rs @@ -703,6 +703,15 @@ macro_rules! memory_range { ("DRAM") => { 1082130432..1082458112 }; + (size as str, "DRAM") => { + "327680" + }; + ("DRAM2_UNINIT") => { + 1082388432..1082457824 + }; + (size as str, "DRAM2_UNINIT") => { + "69392" + }; } #[macro_export] #[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))] diff --git a/esp-metadata-generated/src/_generated_esp32s2.rs b/esp-metadata-generated/src/_generated_esp32s2.rs index df525706e8..af8c44dea1 100644 --- a/esp-metadata-generated/src/_generated_esp32s2.rs +++ b/esp-metadata-generated/src/_generated_esp32s2.rs @@ -723,6 +723,15 @@ macro_rules! memory_range { ("DRAM") => { 1073414144..1073741824 }; + (size as str, "DRAM") => { + "327680" + }; + ("DRAM2_UNINIT") => { + 1073602560..1073741824 + }; + (size as str, "DRAM2_UNINIT") => { + "139264" + }; } #[macro_export] #[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))] diff --git a/esp-metadata-generated/src/_generated_esp32s3.rs b/esp-metadata-generated/src/_generated_esp32s3.rs index 1b09e360e1..954d60b61a 100644 --- a/esp-metadata-generated/src/_generated_esp32s3.rs +++ b/esp-metadata-generated/src/_generated_esp32s3.rs @@ -737,6 +737,15 @@ macro_rules! memory_range { ("DRAM") => { 1070104576..1070596096 }; + (size as str, "DRAM") => { + "491520" + }; + ("DRAM2_UNINIT") => { + 1070446336..1070520080 + }; + (size as str, "DRAM2_UNINIT") => { + "73744" + }; } #[macro_export] #[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))] diff --git a/esp-metadata/devices/esp32.toml b/esp-metadata/devices/esp32.toml index 9291c52ca1..053dbc2907 100644 --- a/esp-metadata/devices/esp32.toml +++ b/esp-metadata/devices/esp32.toml @@ -106,6 +106,7 @@ xtal_options = [26, 40] memory_map = { ranges = [ { name = "dram", start = 0x3FFA_E000, end = 0x4000_0000 }, + { name = "dram2_uninit", start = 0x3FFE_7E30, end = 0x4000_0000 }, ] } # PeripheralClockControl templates. diff --git a/esp-metadata/devices/esp32c2.toml b/esp-metadata/devices/esp32c2.toml index 67e2ef4964..4fab5ae977 100644 --- a/esp-metadata/devices/esp32c2.toml +++ b/esp-metadata/devices/esp32c2.toml @@ -85,6 +85,7 @@ xtal_options = [26, 40] memory_map = { ranges = [ { name = "dram", start = 0x3FCA_0000, end = 0x3FCE_0000 }, + { name = "dram2_uninit", start = 0x3FCC_E800, end = 0x3FCD_EB70 }, ] } peripheral_clocks = { templates = [ diff --git a/esp-metadata/devices/esp32c3.toml b/esp-metadata/devices/esp32c3.toml index 5da6b25b4f..fc8aed8bfb 100644 --- a/esp-metadata/devices/esp32c3.toml +++ b/esp-metadata/devices/esp32c3.toml @@ -93,6 +93,7 @@ xtal_options = [40] memory_map = { ranges = [ { name = "dram", start = 0x3FC8_0000, end = 0x3FCE_0000 }, + { name = "dram2_uninit", start = 0x3FCCE400, end = 0x3FCD_E710 }, ] } peripheral_clocks = { templates = [ diff --git a/esp-metadata/devices/esp32c6.toml b/esp-metadata/devices/esp32c6.toml index a3530189c1..71b739be77 100644 --- a/esp-metadata/devices/esp32c6.toml +++ b/esp-metadata/devices/esp32c6.toml @@ -136,6 +136,7 @@ xtal_options = [40] memory_map = { ranges = [ { name = "dram", start = 0x4080_0000, end = 0x4088_0000 }, + { name = "dram2_uninit", start = 0x4086_E610, end = 0x4087_E610 }, ] } peripheral_clocks = { templates = [ diff --git a/esp-metadata/devices/esp32h2.toml b/esp-metadata/devices/esp32h2.toml index 33441e582b..60cc3eb573 100644 --- a/esp-metadata/devices/esp32h2.toml +++ b/esp-metadata/devices/esp32h2.toml @@ -115,6 +115,7 @@ xtal_options = [32] memory_map = { ranges = [ { name = "dram", start = 0x4080_0000, end = 0x4085_0000 }, + { name = "dram2_uninit", start = 0x4083_EFD0, end = 0x4084_FEE0 }, ] } peripheral_clocks = { templates = [ diff --git a/esp-metadata/devices/esp32s2.toml b/esp-metadata/devices/esp32s2.toml index ccdce1da81..5e5f846b29 100644 --- a/esp-metadata/devices/esp32s2.toml +++ b/esp-metadata/devices/esp32s2.toml @@ -108,6 +108,7 @@ xtal_options = [40] memory_map = { ranges = [ { name = "dram", start = 0x3FFB_0000, end = 0x4000_0000 }, + { name = "dram2_uninit", start = 0x3FFD_E000, end = 0x4000_0000 }, ] } peripheral_clocks = { templates = [ diff --git a/esp-metadata/devices/esp32s3.toml b/esp-metadata/devices/esp32s3.toml index 4f23252f7f..75cbe04f71 100644 --- a/esp-metadata/devices/esp32s3.toml +++ b/esp-metadata/devices/esp32s3.toml @@ -117,6 +117,7 @@ xtal_options = [40] memory_map = { ranges = [ { name = "dram", start = 0x3FC8_8000, end = 0x3FD0_0000 }, + { name = "dram2_uninit", start = 0x3FCD_B700, end = 0x3FCE_D710 }, ] } peripheral_clocks = { templates = [ diff --git a/esp-metadata/src/cfg/soc.rs b/esp-metadata/src/cfg/soc.rs index cf71b76d73..5e1e332165 100644 --- a/esp-metadata/src/cfg/soc.rs +++ b/esp-metadata/src/cfg/soc.rs @@ -47,11 +47,18 @@ impl super::GenericProperty for MemoryMap { let name = region.name.to_uppercase(); let start = number(region.range.start as usize); let end = number(region.range.end as usize); + let size = format!( + "{}", + region.range.end as usize - region.range.start as usize + ); quote! { ( #name ) => { #start .. #end }; + ( size as str, #name ) => { + #size + }; } }); diff --git a/hil-test/Cargo.toml b/hil-test/Cargo.toml index beb4250158..32e235420d 100644 --- a/hil-test/Cargo.toml +++ b/hil-test/Cargo.toml @@ -168,6 +168,7 @@ embassy = ["dep:esp-rtos", "esp-rtos/embassy"] esp32 = [ "embedded-test/xtensa-semihosting", "esp-hal/esp32", + "esp-alloc/esp32", "esp-radio?/esp32", "esp-storage?/esp32", "esp-bootloader-esp-idf/esp32", @@ -176,6 +177,7 @@ esp32 = [ ] esp32c2 = [ "esp-hal/esp32c2", + "esp-alloc/esp32c2", "esp-radio?/esp32c2", "esp-storage?/esp32c2", "esp-bootloader-esp-idf/esp32c2", @@ -184,6 +186,7 @@ esp32c2 = [ ] esp32c3 = [ "esp-hal/esp32c3", + "esp-alloc/esp32c3", "esp-radio?/esp32c3", "esp-storage?/esp32c3", "esp-bootloader-esp-idf/esp32c3", @@ -192,6 +195,7 @@ esp32c3 = [ ] esp32c6 = [ "esp-hal/esp32c6", + "esp-alloc/esp32c6", "esp-radio?/esp32c6", "esp-storage?/esp32c6", "esp-bootloader-esp-idf/esp32c6", @@ -200,6 +204,7 @@ esp32c6 = [ ] esp32h2 = [ "esp-hal/esp32h2", + "esp-alloc/esp32h2", "esp-radio?/esp32h2", "esp-storage?/esp32h2", "esp-bootloader-esp-idf/esp32h2", @@ -209,6 +214,7 @@ esp32h2 = [ esp32s2 = [ "embedded-test/xtensa-semihosting", "esp-hal/esp32s2", + "esp-alloc/esp32s2", "esp-radio?/esp32s2", "esp-storage?/esp32s2", "esp-bootloader-esp-idf/esp32s2", @@ -218,6 +224,7 @@ esp32s2 = [ esp32s3 = [ "embedded-test/xtensa-semihosting", "esp-hal/esp32s3", + "esp-alloc/esp32s3", "esp-radio?/esp32s3", "esp-storage?/esp32s3", "esp-bootloader-esp-idf/esp32s3", From 499763174d14fa96332430b38eaf18e2706f19a0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?D=C3=A1niel=20Buga?= Date: Fri, 17 Oct 2025 13:55:31 +0200 Subject: [PATCH 3/3] Make ram(reclaimed) depend on the idf bootloader --- esp-bootloader-esp-idf/Cargo.toml | 16 +++++++++------- esp-bootloader-esp-idf/src/lib.rs | 10 ++++++++++ esp-hal-procmacros/Cargo.toml | 3 +++ esp-hal-procmacros/src/ram.rs | 13 ++++++++++++- 4 files changed, 34 insertions(+), 8 deletions(-) diff --git a/esp-bootloader-esp-idf/Cargo.toml b/esp-bootloader-esp-idf/Cargo.toml index f40b0d73d3..487a1ad72a 100644 --- a/esp-bootloader-esp-idf/Cargo.toml +++ b/esp-bootloader-esp-idf/Cargo.toml @@ -33,6 +33,8 @@ cfg-if = "1" defmt = { version = "1.0.1", optional = true } document-features = "0.2" esp-config = { version = "0.6.0", path = "../esp-config" } +esp-hal-procmacros = { version = "0.20.0", path = "../esp-hal-procmacros", features = ["__esp_idf_bootloader"] } +esp-metadata-generated = { version = "0.2.0", path = "../esp-metadata-generated" } esp-rom-sys = { version = "0.1.2", path = "../esp-rom-sys", optional = true } embedded-storage = "0.3.1" log-04 = { package = "log", version = "0.4", optional = true } @@ -64,19 +66,19 @@ std = ["dep:crc", "dep:md-5"] #! One of the following features must be enabled to select the target chip: ## -esp32c2 = ["esp-rom-sys/esp32c2"] +esp32c2 = ["esp-rom-sys/esp32c2", "esp-metadata-generated/esp32c2"] ## -esp32c3 = ["esp-rom-sys/esp32c3"] +esp32c3 = ["esp-rom-sys/esp32c3", "esp-metadata-generated/esp32c3"] ## -esp32c6 = ["esp-rom-sys/esp32c6"] +esp32c6 = ["esp-rom-sys/esp32c6", "esp-metadata-generated/esp32c6"] ## -esp32h2 = ["esp-rom-sys/esp32h2"] +esp32h2 = ["esp-rom-sys/esp32h2", "esp-metadata-generated/esp32h2"] ## -esp32 = ["esp-rom-sys/esp32"] +esp32 = ["esp-rom-sys/esp32", "esp-metadata-generated/esp32"] ## -esp32s2 = ["esp-rom-sys/esp32s2"] +esp32s2 = ["esp-rom-sys/esp32s2", "esp-metadata-generated/esp32s2"] ## -esp32s3 = ["esp-rom-sys/esp32s3"] +esp32s3 = ["esp-rom-sys/esp32s3", "esp-metadata-generated/esp32s3"] # "md-5" is hidden behind `std` feature and `cargo machete` incorrectly marks it as unused. [package.metadata.cargo-machete] diff --git a/esp-bootloader-esp-idf/src/lib.rs b/esp-bootloader-esp-idf/src/lib.rs index 0bcfc01e4b..4fce91bf8d 100644 --- a/esp-bootloader-esp-idf/src/lib.rs +++ b/esp-bootloader-esp-idf/src/lib.rs @@ -72,6 +72,16 @@ //! } //! ``` //! +//! ## Reclaimed memory +//! +//! After the bootloader has started the application, the `.dram2_uninit` region becomes available +//! for use. This region can be used for dynamic memory allocation or other purposes, but the data +//! placed there cannot be initialized (i.e. it must be `MaybeUninit`). For convenience, you can +//! use the `#[esp_hal::ram(reclaimed)]` attribute, which will also check that the variable can be +//! placed in the reclaimed memory. +#![doc = ""] +#![cfg_attr(not(feature = "std"), doc = concat!("For ", esp_metadata_generated::chip!(), " the size of the reclaimed memory is ", esp_metadata_generated::memory_range!(size as str, "DRAM2_UNINIT")," bytes."))] +#![doc = ""] //! ## Additional configuration //! //! We've exposed some configuration options that don't fit into cargo diff --git a/esp-hal-procmacros/Cargo.toml b/esp-hal-procmacros/Cargo.toml index c093fd56dc..46432b7ecd 100644 --- a/esp-hal-procmacros/Cargo.toml +++ b/esp-hal-procmacros/Cargo.toml @@ -47,3 +47,6 @@ is-lp-core = [] ## Provide an `#[entry]` macro for running applications on the ESP32-S2/S3's ## ULP core. is-ulp-core = [] + +# Enables `ram(reclaimed)` +__esp_idf_bootloader = [] diff --git a/esp-hal-procmacros/src/ram.rs b/esp-hal-procmacros/src/ram.rs index 0c0fa5f293..d92dd59189 100644 --- a/esp-hal-procmacros/src/ram.rs +++ b/esp-hal-procmacros/src/ram.rs @@ -81,7 +81,18 @@ pub fn ram(args: TokenStream, input: TokenStream) -> TokenStream { .into(); }; let arg = match ident { - i if i == "reclaimed" => &mut dram2_uninit, + i if i == "reclaimed" => { + if !cfg!(feature = "__esp_idf_bootloader") { + return syn::Error::new( + ident.span(), + "`ram(reclaimed)` requires the esp-idf bootloader", + ) + .into_compile_error() + .into(); + } + + &mut dram2_uninit + } _ => { return syn::Error::new( ident.span(),