efuse: Implement write support

Author: kyrias

Cargo.lock

@@ -50,6 +50,7 @@ log             = "0.4"
 md-5            = "0.10"
 miette          = "7.6"
 object          = "0.37"
+reed-solomon    = "0.2.1"
 regex           = { version = "1.11", optional = true }
 serde           = { version = "1.0", features = ["derive"] }
 serialport      = { version = "4.7", default-features = false, optional = true }

espflash/Cargo.toml

@@ -683,6 +683,19 @@ impl Connection {
         Ok(())
     }
 
+    /// Updates a register by applying the new value to the masked out portion
+    /// of the old value.
+    // TODO: Is this the API we want?  For many cases it's convenient to let this
+    // function handle       it, but the resulting API feels kind of
+    // non-obvious.
+    pub(crate) fn update_reg(&mut self, addr: u32, mask: u32, new_value: u32) -> Result<(), Error> {
+        let masked_new_value = new_value.checked_shl(mask.trailing_zeros()).unwrap_or(0) & mask;
+
+        let masked_old_value = self.read_reg(addr)? & !mask;
+
+        self.write_reg(addr, masked_old_value | masked_new_value, None)
+    }
+
     /// Reads a register command with a timeout.
     pub(crate) fn read(&mut self, len: usize) -> Result<Option<Vec<u8>>, Error> {
         let mut tmp = Vec::with_capacity(1024);

espflash/src/connection/mod.rs

@@ -367,6 +367,22 @@ pub enum Error {
     /// Specified eFuse block does not exist
     #[error("specified eFuse block does not exist: {0}")]
     InvalidEfuseBlock(u32),
+
+    /// Unsupported crystall frequency
+    #[error("Unsupported crystal frequency: {0}")]
+    UnsupportedXtalFrequency(String),
+
+    /// Failed to write eFuse
+    #[error("Failed to write eFuse: {0}")]
+    WritingEfuseFailed(String),
+
+    /// Timed out while waiting for eFuse controller to return to idle
+    #[error("Timed out while waiting for eFuse controller to return to idle")]
+    TimedOutWaitingForEfuseController,
+
+    /// Tried to use an unsupported eFuse coding scheme
+    #[error("Tried to use an unsupported eFuse coding scheme: {0}")]
+    UnsupportedEfuseCodingScheme(String)
 }
 
 #[cfg(feature = "serialport")]

espflash/src/error.rs

@@ -2,7 +2,7 @@
 //!
 //! This file was automatically generated, please do not edit it manually!
 //!
-//! Generated: 2025-11-26 21:42
+//! Generated: 2025-12-05 18:05
 //! Version:   369d2d860d34e777c0f7d545a7dfc3c4
 
 #![allow(unused)]
@@ -12,23 +12,63 @@ use super::{EfuseBlock, EfuseField};
 /// All eFuse blocks available on this device.
 pub(crate) const BLOCKS: &[EfuseBlock] = &[
     EfuseBlock {
+        index: 0u8,
         length: 7u8,
-        read_address: 1073061888u32,
+        read_address: 0x3ff5a000u32,
+        write_address: 0x3ff5a01cu32,
     },
     EfuseBlock {
+        index: 1u8,
         length: 8u8,
-        read_address: 1073061944u32,
+        read_address: 0x3ff5a038u32,
+        write_address: 0x3ff5a098u32,
     },
     EfuseBlock {
+        index: 2u8,
         length: 8u8,
-        read_address: 1073061976u32,
+        read_address: 0x3ff5a058u32,
+        write_address: 0x3ff5a0b8u32,
     },
     EfuseBlock {
+        index: 3u8,
         length: 8u8,
-        read_address: 1073062008u32,
+        read_address: 0x3ff5a078u32,
+        write_address: 0x3ff5a0d8u32,
     },
 ];
 
+/// Defined eFuse registers and commands
+pub(crate) mod defines {
+    use super::super::EfuseBlockErrors;
+    pub(crate) const BLOCK_ERRORS: &[EfuseBlockErrors] = &[];
+    pub(crate) const EFUSE_CMD_READ: u32 = 0x1;
+    pub(crate) const EFUSE_BLK0_RDATA3_REG: u32 = 0x3ff5a00c;
+    pub(crate) const EFUSE_MEM_SIZE: u32 = 0x120;
+    pub(crate) const CODING_SCHEME_NONE_RECOVERY: u32 = 0x3;
+    pub(crate) const EFUSE_CMD_WRITE: u32 = 0x2;
+    pub(crate) const EFUSE_CLK_SEL0_MASK: u32 = 0xff;
+    pub(crate) const EFUSE_REG_DEC_STATUS_MASK: u32 = 0xfff;
+    pub(crate) const CODING_SCHEME_34: u32 = 0x1;
+    pub(crate) const EFUSE_CLK_REG: u32 = 0x3ff5a0f8;
+    pub(crate) const EFUSE_CODING_SCHEME_WORD: u32 = 0x6;
+    pub(crate) const EFUSE_DAC_CLK_DIV_MASK: u32 = 0xff;
+    pub(crate) const EFUSE_CODING_SCHEME_MASK: u32 = 0x3;
+    pub(crate) const EFUSE_CLK_SEL1_MASK: u32 = 0xff00;
+    pub(crate) const CODING_SCHEME_RS: u32 = 0x4;
+    pub(crate) const EFUSE_RD_CHIP_VER_REV2: u32 = 0x100000;
+    pub(crate) const EFUSE_REG_CONF: u32 = 0x3ff5a0fc;
+    pub(crate) const EFUSE_RD_CHIP_VER_REV1: u32 = 0x8000;
+    pub(crate) const EFUSE_CONF_WRITE: u32 = 0x5a5a;
+    pub(crate) const EFUSE_CMD_OP_MASK: u32 = 0x3;
+    pub(crate) const CODING_SCHEME_NONE: u32 = 0x0;
+    pub(crate) const CODING_SCHEME_REPEAT: u32 = 0x2;
+    pub(crate) const EFUSE_BLK0_RDATA5_REG: u32 = 0x3ff5a014;
+    pub(crate) const EFUSE_CONF_READ: u32 = 0x5aa5;
+    pub(crate) const EFUSE_REG_DEC_STATUS: u32 = 0x3ff5a11c;
+    pub(crate) const EFUSE_DAC_CONF_REG: u32 = 0x3ff5a118;
+    pub(crate) const EFUSE_REG_CMD: u32 = 0x3ff5a104;
+}
+
 /// Efuse write disable mask
 pub const WR_DIS: EfuseField = EfuseField::new(0, 0, 0, 16);
 /// Disable reading from BlOCK1-3

espflash/src/target/efuse/esp32.rs

@@ -2,7 +2,7 @@
 //!
 //! This file was automatically generated, please do not edit it manually!
 //!
-//! Generated: 2025-11-26 21:42
+//! Generated: 2025-12-05 18:05
 //! Version:   897499b0349a608b895d467abbcf006b
 
 #![allow(unused)]
@@ -12,23 +12,99 @@ use super::{EfuseBlock, EfuseField};
 /// All eFuse blocks available on this device.
 pub(crate) const BLOCKS: &[EfuseBlock] = &[
     EfuseBlock {
+        index: 0u8,
         length: 2u8,
-        read_address: 1610647596u32,
+        read_address: 0x6000882cu32,
+        write_address: 0x60008800u32,
     },
     EfuseBlock {
+        index: 1u8,
         length: 3u8,
-        read_address: 1610647604u32,
+        read_address: 0x60008834u32,
+        write_address: 0x60008800u32,
     },
     EfuseBlock {
+        index: 2u8,
         length: 8u8,
-        read_address: 1610647616u32,
+        read_address: 0x60008840u32,
+        write_address: 0x60008800u32,
     },
     EfuseBlock {
+        index: 3u8,
         length: 8u8,
-        read_address: 1610647648u32,
+        read_address: 0x60008860u32,
+        write_address: 0x60008800u32,
     },
 ];
 
+/// Defined eFuse registers and commands
+pub(crate) mod defines {
+    use super::super::EfuseBlockErrors;
+    pub(crate) const BLOCK_ERRORS: &[EfuseBlockErrors] = &[
+        EfuseBlockErrors {
+            err_num_reg: 0x60008880u32,
+            err_num_mask: None,
+            err_num_offset: None,
+            fail_bit_reg: 0x60008880u32,
+            fail_bit_offset: None,
+        },
+        EfuseBlockErrors {
+            err_num_reg: 0x60008884u32,
+            err_num_mask: Some(0x7u32),
+            err_num_offset: Some(0x0u32),
+            fail_bit_reg: 0x60008884u32,
+            fail_bit_offset: Some(0x3u32),
+        },
+        EfuseBlockErrors {
+            err_num_reg: 0x60008884u32,
+            err_num_mask: Some(0x7u32),
+            err_num_offset: Some(0x4u32),
+            fail_bit_reg: 0x60008884u32,
+            fail_bit_offset: Some(0x7u32),
+        },
+        EfuseBlockErrors {
+            err_num_reg: 0x60008884u32,
+            err_num_mask: Some(0x7u32),
+            err_num_offset: Some(0x8u32),
+            fail_bit_reg: 0x60008884u32,
+            fail_bit_offset: Some(0xbu32),
+        },
+    ];
+    pub(crate) const EFUSE_DAC_NUM_M: u32 = 0x1fe00;
+    pub(crate) const EFUSE_PGM_CMD: u32 = 0x2;
+    pub(crate) const EFUSE_PWR_ON_NUM_M: u32 = 0xffff00;
+    pub(crate) const EFUSE_DAC_NUM_S: u32 = 0x9;
+    pub(crate) const EFUSE_RD_RS_ERR_REG: u32 = 0x60008884;
+    pub(crate) const EFUSE_PGM_DATA0_REG: u32 = 0x60008800;
+    pub(crate) const EFUSE_READ_CMD: u32 = 0x1;
+    pub(crate) const EFUSE_PWR_OFF_NUM_M: u32 = 0xffff;
+    pub(crate) const EFUSE_WR_TIM_CONF0_REG: u32 = 0x60008910;
+    pub(crate) const EFUSE_WR_TIM_CONF1_REG: u32 = 0x60008914;
+    pub(crate) const EFUSE_MEM_SIZE: u32 = 0x200;
+    pub(crate) const CODING_SCHEME_34: u32 = 0x1;
+    pub(crate) const CODING_SCHEME_NONE: u32 = 0x0;
+    pub(crate) const EFUSE_PWR_OFF_NUM_S: u32 = 0x0;
+    pub(crate) const CODING_SCHEME_REPEAT: u32 = 0x2;
+    pub(crate) const EFUSE_TPGM_INACTIVE_S: u32 = 0x8;
+    pub(crate) const EFUSE_CLK_REG: u32 = 0x60008888;
+    pub(crate) const CODING_SCHEME_NONE_RECOVERY: u32 = 0x3;
+    pub(crate) const EFUSE_PWR_ON_NUM_S: u32 = 0x8;
+    pub(crate) const EFUSE_PGM_CMD_MASK: u32 = 0x3;
+    pub(crate) const EFUSE_WRITE_OP_CODE: u32 = 0x5a5a;
+    pub(crate) const EFUSE_STATUS_REG: u32 = 0x60008890;
+    pub(crate) const EFUSE_CMD_REG: u32 = 0x60008894;
+    pub(crate) const EFUSE_CONF_REG: u32 = 0x6000888c;
+    pub(crate) const EFUSE_TPGM_INACTIVE_M: u32 = 0xff00;
+    pub(crate) const EFUSE_DAC_CONF_REG: u32 = 0x60008908;
+    pub(crate) const EFUSE_RD_REPEAT_ERR_REG: u32 = 0x60008880;
+    pub(crate) const CODING_SCHEME_RS: u32 = 0x4;
+    pub(crate) const EFUSE_DAC_CLK_DIV_S: u32 = 0x0;
+    pub(crate) const EFUSE_PGM_CHECK_VALUE0_REG: u32 = 0x60008820;
+    pub(crate) const EFUSE_WR_TIM_CONF2_REG: u32 = 0x60008918;
+    pub(crate) const EFUSE_DAC_CLK_DIV_M: u32 = 0xff;
+    pub(crate) const EFUSE_READ_OP_CODE: u32 = 0x5aa5;
+}
+
 /// Disable programming of individual eFuses
 pub const WR_DIS: EfuseField = EfuseField::new(0, 0, 0, 8);
 ///