eFuse write support

.cargo/config.toml

@@ -1,3 +1,4 @@
 [alias]
 xtask = "run --package xtask --"
+xgenerate-efuse-fields = "run --package xtask --features=efuse-generator -- generate-efuse-fields"
 xrun = "run --package espflash --"

.github/workflows/ci.yml

@@ -123,7 +123,7 @@ jobs:
       - uses: actions/checkout@v4
       - uses: dtolnay/rust-toolchain@stable
 
-      - run: cargo check -p xtask
+      - run: cargo check -p xtask --all-features
 
   # --------------------------------------------------------------------------
   # Test

.github/workflows/hil.yml

@@ -119,4 +119,4 @@ jobs:
           echo "$PWD/xtask_app" >> "$GITHUB_PATH"
 
       - name: Run all tests
-        run: xtask run-tests --chip ${{ matrix.board.mcu }} -t 60 --no-build
+        run: xtask run-tests --chip ${{ matrix.board.mcu }} -t 60 --no-build

CHANGELOG.md

@@ -21,7 +21,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 
 ### Fixed
 
-- Corrected eFuse BLOCK0 definitions for ESP32-C2, ESP32-C3, and ESP32-S3 (#961)
+- Corrected eFuse block address calculations. (#971)
 - Fixed Secure Download Mode detection on ESP32-P4 (#972)
 - Several fixes in `read_efuse` (#969)
 - Fixed a problem in detecting the app-descriptor for a project if `strip = true` is used (#975)

espflash/Cargo.toml

@@ -50,6 +50,7 @@ log             = "0.4"
 md-5            = "0.10"
 miette          = "7.6"
 object          = "0.37"
+reed-solomon    = "0.2.1"
 regex           = { version = "1.11", optional = true }
 serde           = { version = "1.0", features = ["derive"] }
 serialport      = { version = "4.7", default-features = false, optional = true }

espflash/src/connection/mod.rs

@@ -683,6 +683,19 @@ impl Connection {
         Ok(())
     }
 
+    /// Updates a register by applying the new value to the masked out portion
+    /// of the old value.
+    // TODO: Is this the API we want?  For many cases it's convenient to let this
+    // function handle       it, but the resulting API feels kind of
+    // non-obvious.
+    pub(crate) fn update_reg(&mut self, addr: u32, mask: u32, new_value: u32) -> Result<(), Error> {
+        let masked_new_value = new_value.checked_shl(mask.trailing_zeros()).unwrap_or(0) & mask;
+
+        let masked_old_value = self.read_reg(addr)? & !mask;
+
+        self.write_reg(addr, masked_old_value | masked_new_value, None)
+    }
+
     /// Reads a register command with a timeout.
     pub(crate) fn read(&mut self, len: usize) -> Result<Option<Vec<u8>>, Error> {
         let mut tmp = Vec::with_capacity(1024);

espflash/src/error.rs

@@ -363,6 +363,26 @@ pub enum Error {
     /// The efuse field is larger than 32 bit.
     #[error("Requested efuse field is larger than 32 bit. Use `read_efuse_le`.")]
     EfuseFieldTooLarge,
+
+    /// Specified eFuse block does not exist
+    #[error("specified eFuse block does not exist: {0}")]
+    InvalidEfuseBlock(u32),
+
+    /// Unsupported crystall frequency
+    #[error("Unsupported crystal frequency: {0}")]
+    UnsupportedXtalFrequency(String),
+
+    /// Failed to write eFuse
+    #[error("Failed to write eFuse: {0}")]
+    WritingEfuseFailed(String),
+
+    /// Timed out while waiting for eFuse controller to return to idle
+    #[error("Timed out while waiting for eFuse controller to return to idle")]
+    TimedOutWaitingForEfuseController,
+
+    /// Tried to use an unsupported eFuse coding scheme
+    #[error("Tried to use an unsupported eFuse coding scheme: {0}")]
+    UnsupportedEfuseCodingScheme(String),
 }
 
 #[cfg(feature = "serialport")]

espflash/src/target/efuse/esp32.rs

@@ -2,15 +2,72 @@
 //!
 //! This file was automatically generated, please do not edit it manually!
 //!
-//! Generated: 2025-11-19 12:31
+//! Generated: 2025-12-05 18:05
 //! Version:   369d2d860d34e777c0f7d545a7dfc3c4
 
 #![allow(unused)]
 
-use super::EfuseField;
+use super::{EfuseBlock, EfuseField};
 
-/// Total size in bytes of each block
-pub(crate) const BLOCK_SIZES: &[u32] = &[28, 32, 32, 32];
+/// All eFuse blocks available on this device.
+pub(crate) const BLOCKS: &[EfuseBlock] = &[
+    EfuseBlock {
+        index: 0u8,
+        length: 7u8,
+        read_address: 0x3ff5a000u32,
+        write_address: 0x3ff5a01cu32,
+    },
+    EfuseBlock {
+        index: 1u8,
+        length: 8u8,
+        read_address: 0x3ff5a038u32,
+        write_address: 0x3ff5a098u32,
+    },
+    EfuseBlock {
+        index: 2u8,
+        length: 8u8,
+        read_address: 0x3ff5a058u32,
+        write_address: 0x3ff5a0b8u32,
+    },
+    EfuseBlock {
+        index: 3u8,
+        length: 8u8,
+        read_address: 0x3ff5a078u32,
+        write_address: 0x3ff5a0d8u32,
+    },
+];
+
+/// Defined eFuse registers and commands
+pub(crate) mod defines {
+    use super::super::EfuseBlockErrors;
+    pub(crate) const BLOCK_ERRORS: &[EfuseBlockErrors] = &[];
+    pub(crate) const EFUSE_CMD_READ: u32 = 0x1;
+    pub(crate) const EFUSE_BLK0_RDATA3_REG: u32 = 0x3ff5a00c;
+    pub(crate) const EFUSE_MEM_SIZE: u32 = 0x120;
+    pub(crate) const CODING_SCHEME_NONE_RECOVERY: u32 = 0x3;
+    pub(crate) const EFUSE_CMD_WRITE: u32 = 0x2;
+    pub(crate) const EFUSE_CLK_SEL0_MASK: u32 = 0xff;
+    pub(crate) const EFUSE_REG_DEC_STATUS_MASK: u32 = 0xfff;
+    pub(crate) const CODING_SCHEME_34: u32 = 0x1;
+    pub(crate) const EFUSE_CLK_REG: u32 = 0x3ff5a0f8;
+    pub(crate) const EFUSE_CODING_SCHEME_WORD: u32 = 0x6;
+    pub(crate) const EFUSE_DAC_CLK_DIV_MASK: u32 = 0xff;
+    pub(crate) const EFUSE_CODING_SCHEME_MASK: u32 = 0x3;
+    pub(crate) const EFUSE_CLK_SEL1_MASK: u32 = 0xff00;
+    pub(crate) const CODING_SCHEME_RS: u32 = 0x4;
+    pub(crate) const EFUSE_RD_CHIP_VER_REV2: u32 = 0x100000;
+    pub(crate) const EFUSE_REG_CONF: u32 = 0x3ff5a0fc;
+    pub(crate) const EFUSE_RD_CHIP_VER_REV1: u32 = 0x8000;
+    pub(crate) const EFUSE_CONF_WRITE: u32 = 0x5a5a;
+    pub(crate) const EFUSE_CMD_OP_MASK: u32 = 0x3;
+    pub(crate) const CODING_SCHEME_NONE: u32 = 0x0;
+    pub(crate) const CODING_SCHEME_REPEAT: u32 = 0x2;
+    pub(crate) const EFUSE_BLK0_RDATA5_REG: u32 = 0x3ff5a014;
+    pub(crate) const EFUSE_CONF_READ: u32 = 0x5aa5;
+    pub(crate) const EFUSE_REG_DEC_STATUS: u32 = 0x3ff5a11c;
+    pub(crate) const EFUSE_DAC_CONF_REG: u32 = 0x3ff5a118;
+    pub(crate) const EFUSE_REG_CMD: u32 = 0x3ff5a104;
+}
 
 /// Efuse write disable mask
 pub const WR_DIS: EfuseField = EfuseField::new(0, 0, 0, 16);