Refactor call ABI.

Author: reitermarkus

src/librustc_target/abi/call/xtensa.rs

@@ -9,28 +9,27 @@ const MAX_RET_IN_REGS_SIZE: u64 = 2 * 32;
 
 fn classify_ret_ty<Ty>(arg: &mut ArgAbi<'_, Ty>, xlen: u64) {
     // The rules for return and argument types are the same, so defer to
-    // classifyArgumentType.
-    classify_arg_ty(arg, xlen, &mut 2); // two as max return size
+    // classify_arg_ty.
+    let mut remaining_gpr = 2;
+    let fixed = true;
+    classify_arg_ty(arg, xlen, fixed, &mut remaining_gpr);
 }
 
-fn classify_arg_ty<Ty>(arg: &mut ArgAbi<'_, Ty>, xlen: u64, remaining_gpr: &mut u64) {
-    // Determine the number of GPRs needed to pass the current argument
-    // according to the ABI. 2*XLen-aligned varargs are passed in "aligned"
-    // register pairs, so may consume 3 registers.
+fn classify_arg_ty<Ty>(arg: &mut ArgAbi<'_, Ty>, xlen: u64, fixed: bool, remaining_gpr: &mut u64) {
+    assert!(*remaining_gpr <= NUM_ARG_GPR, "Arg GPR tracking underflow");
 
     let arg_size = arg.layout.size;
-    if arg_size.bits() > MAX_ARG_IN_REGS_SIZE {
-        arg.make_indirect();
-        return;
-    }
+    let alignment = arg.layout.details.align.abi;
 
-    let alignment = arg.layout.align.abi;
-    let mut required_gpr = 1u64; // at least one per arg
+    // Determine the number of GPRs needed to pass the current argument
+    // according to the ABI. 2*XLen-aligned varargs are passed in "aligned"
+    // register pairs, so may consume 3 registers.
+    let mut required_gpr = 1u64;
 
-    if alignment.bits() == 2 * xlen {
+    if !fixed && alignment.bits() == 2 * xlen {
         required_gpr = 2 + (*remaining_gpr % 2);
     } else if arg_size.bits() > xlen && arg_size.bits() <= MAX_ARG_IN_REGS_SIZE {
-        required_gpr = (arg_size.bits() + (xlen - 1)) / xlen;
+        required_gpr = (arg_size.bits() + xlen - 1) / xlen;
     }
 
     let mut stack_required = false;
@@ -40,63 +39,53 @@ fn classify_arg_ty<Ty>(arg: &mut ArgAbi<'_, Ty>, xlen: u64, remaining_gpr: &mut
     }
     *remaining_gpr -= required_gpr;
 
-    // if  a value can fit in a reg and the
-    // stack is not required, extend
     if !arg.layout.is_aggregate() {
-        // non-aggregate types
+        // All integral types are promoted to XLen width, unless passed on the
+        // stack.
         if arg_size.bits() < xlen && !stack_required {
             arg.extend_integer_width_to(xlen);
+            return;
         }
-    } else if arg_size.bits() as u64 <= MAX_ARG_IN_REGS_SIZE {
-        // aggregate types
-        // Aggregates which are <= 4*32 will be passed in registers if possible,
-        // so coerce to integers.
 
+        return;
+    }
+
+    // Aggregates which are <= 4 * 32 will be passed in registers if possible,
+    // so coerce to integers.
+    if size.bits() as u64 <= MAX_ARG_IN_REGS_SIZE {
         // Use a single XLen int if possible, 2*XLen if 2*XLen alignment is
         // required, and a 2-element XLen array if only XLen alignment is
         // required.
-        // if alignment == 2 * xlen {
-        //     arg.extend_integer_width_to(xlen * 2);
-        // } else {
-        //     arg.extend_integer_width_to(arg_size + (xlen - 1) / xlen);
-        // }
-        if alignment.bits() == 2 * xlen {
+        if arg_size.bits() <= xlen {
+            arg.cast_to(Uniform { unit: Reg::i32(), total: arg_size });
+            return;
+        } else if alignment.bits() == 2 * xlen {
             arg.cast_to(Uniform { unit: Reg::i64(), total: arg_size });
+            return;
         } else {
-            //FIXME array type - this should be a homogenous array type
-            // arg.extend_integer_width_to(arg_size + (xlen - 1) / xlen);
+            arg.extend_integer_width_to((arg_size.bits() + xlen - 1) / xlen);
+            return;
         }
-    } else {
-        // if we get here the stack is required
-        assert!(stack_required);
-        arg.make_indirect();
     }
 
-    // if arg_size as u64 <= MAX_ARG_IN_REGS_SIZE {
-    //     let align = arg.layout.align.abi.bytes();
-    //     let total = arg.layout.size;
-    //     arg.cast_to(Uniform {
-    //         unit: if align <= 4 { Reg::i32() } else { Reg::i64() },
-    //         total
-    //     });
-    //     return;
-    // }
+    arg.make_indirect();
 }
 
-pub fn compute_abi_info<Ty>(fabi: &mut FnAbi<'_, Ty>, xlen: u64) {
-    if !fabi.ret.is_ignore() {
-        classify_ret_ty(&mut fabi.ret, xlen);
+pub fn compute_abi_info<Ty>(fty: &mut FnAbi<'_, Ty>, xlen: u64) {
+    if !fty.ret.is_ignore() {
+        classify_ret_ty(&mut fty.ret, xlen);
     }
 
     let return_indirect =
-        fabi.ret.layout.size.bits() > MAX_RET_IN_REGS_SIZE || fabi.ret.is_indirect();
+        fty.ret.is_indirect() || fty.ret.layout.size.bits() > MAX_RET_IN_REGS_SIZE;
 
     let mut remaining_gpr = if return_indirect { NUM_ARG_GPR - 1 } else { NUM_ARG_GPR };
 
-    for arg in &mut fabi.args {
+    for arg in &mut fty.args {
         if arg.is_ignore() {
             continue;
         }
-        classify_arg_ty(arg, xlen, &mut remaining_gpr);
+        let fixed = true;
+        classify_arg_ty(arg, xlen, fixed, &mut remaining_gpr);
     }
 }