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Jason2866Jason2866
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move in Esp.cpp
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4 files changed

+122
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‎cores/esp32/Esp.cpp‎

Lines changed: 112 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -516,3 +516,115 @@ uint64_t EspClass::getEfuseMac(void) {
516516
esp_efuse_mac_get_default((uint8_t *)(&_chipmacid));
517517
return _chipmacid;
518518
}
519+
520+
// ============================================================================
521+
// Flash Frequency Runtime Detection
522+
// ============================================================================
523+
524+
// Define SPI0 base addresses for different chips
525+
#if CONFIG_IDF_TARGET_ESP32S3
526+
#define FLASH_SPI0_BASE 0x60003000
527+
#elif CONFIG_IDF_TARGET_ESP32S2
528+
#define FLASH_SPI0_BASE 0x3f402000
529+
#elif CONFIG_IDF_TARGET_ESP32C3
530+
#define FLASH_SPI0_BASE 0x60002000
531+
#elif CONFIG_IDF_TARGET_ESP32C2
532+
#define FLASH_SPI0_BASE 0x60002000
533+
#elif CONFIG_IDF_TARGET_ESP32C6
534+
#define FLASH_SPI0_BASE 0x60003000
535+
#elif CONFIG_IDF_TARGET_ESP32H2
536+
#define FLASH_SPI0_BASE 0x60003000
537+
#elif CONFIG_IDF_TARGET_ESP32
538+
#define FLASH_SPI0_BASE 0x3ff42000
539+
#else
540+
#define FLASH_SPI0_BASE 0x60003000 // Default for new chips
541+
#endif
542+
543+
// Register offsets
544+
#define FLASH_CORE_CLK_SEL_OFFSET 0x80
545+
#define FLASH_CLOCK_OFFSET 0x14
546+
547+
/**
548+
* @brief Read the source clock frequency from hardware registers
549+
* @return Source clock frequency in MHz (80, 120, 160, or 240)
550+
*/
551+
uint8_t EspClass::getFlashSourceFrequencyMHz(void) {
552+
#if CONFIG_IDF_TARGET_ESP32
553+
// ESP32 classic supports 40 MHz and 80 MHz
554+
// Note: ESP32 uses the PLL clock (80 MHz) as source and divides it
555+
return 80; // Always 80 MHz source, divider determines 40/80 MHz
556+
#else
557+
volatile uint32_t* core_clk_reg = (volatile uint32_t*)(FLASH_SPI0_BASE + FLASH_CORE_CLK_SEL_OFFSET);
558+
uint32_t core_clk_sel = (*core_clk_reg) & 0x3; // Bits 0-1
559+
560+
uint8_t source_freq = 80; // Default
561+
562+
#if CONFIG_IDF_TARGET_ESP32S3
563+
switch (core_clk_sel) {
564+
case 0: source_freq = 80; break;
565+
case 1: source_freq = 120; break;
566+
case 2: source_freq = 160; break;
567+
case 3: source_freq = 240; break;
568+
}
569+
#elif CONFIG_IDF_TARGET_ESP32S2
570+
switch (core_clk_sel) {
571+
case 0: source_freq = 80; break;
572+
case 1: source_freq = 120; break;
573+
case 2: source_freq = 160; break;
574+
}
575+
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || \
576+
CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
577+
switch (core_clk_sel) {
578+
case 0: source_freq = 80; break;
579+
case 1: source_freq = 120; break;
580+
}
581+
#else
582+
switch (core_clk_sel) {
583+
case 0: source_freq = 80; break;
584+
case 1: source_freq = 120; break;
585+
default: source_freq = 80; break;
586+
}
587+
#endif
588+
589+
return source_freq;
590+
#endif
591+
}
592+
593+
/**
594+
* @brief Read the clock divider from hardware registers
595+
* @return Clock divider value (1 = no division, 2 = divide by 2, etc.)
596+
*/
597+
uint8_t EspClass::getFlashClockDivider(void) {
598+
volatile uint32_t* clock_reg = (volatile uint32_t*)(FLASH_SPI0_BASE + FLASH_CLOCK_OFFSET);
599+
uint32_t clock_val = *clock_reg;
600+
601+
// Bit 31: if set, clock is 1:1 (no divider)
602+
if (clock_val & (1 << 31)) {
603+
return 1;
604+
}
605+
606+
// Bits 16-23: clkdiv_pre
607+
uint8_t clkdiv_pre = (clock_val >> 16) & 0xFF;
608+
return clkdiv_pre + 1;
609+
}
610+
611+
/**
612+
* @brief Get the actual flash frequency in MHz
613+
* @return Flash frequency in MHz
614+
*/
615+
uint32_t EspClass::getFlashFrequencyMHz(void) {
616+
uint8_t source = getFlashSourceFrequencyMHz();
617+
uint8_t divider = getFlashClockDivider();
618+
619+
if (divider == 0) divider = 1; // Safety check
620+
621+
return source / divider;
622+
}
623+
624+
/**
625+
* @brief Check if High Performance Mode is enabled
626+
* @return true if flash runs > 80 MHz, false otherwise
627+
*/
628+
bool EspClass::isFlashHighPerformanceModeEnabled(void) {
629+
return getFlashFrequencyMHz() > 80;
630+
}

‎cores/esp32/Esp.h‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -92,6 +92,12 @@ class EspClass {
9292
uint32_t getFlashChipSpeed();
9393
FlashMode_t getFlashChipMode();
9494

95+
// Flash frequency runtime detection
96+
uint32_t getFlashFrequencyMHz();
97+
uint8_t getFlashSourceFrequencyMHz();
98+
uint8_t getFlashClockDivider();
99+
bool isFlashHighPerformanceModeEnabled();
100+
95101
uint32_t magicFlashChipSize(uint8_t flashByte);
96102
uint32_t magicFlashChipSpeed(uint8_t flashByte);
97103
FlashMode_t magicFlashChipMode(uint8_t flashByte);

‎cores/esp32/chip-debug-report.cpp‎

Lines changed: 4 additions & 116 deletions
Original file line numberDiff line numberDiff line change
@@ -142,14 +142,14 @@ static void printFlashInfo(void) {
142142
chip_report_printf(" Page Size : %8lu B (%6.1f KB)\n", g_rom_flashchip.page_size, b2kb(g_rom_flashchip.page_size));
143143

144144
// Runtime flash frequency detection from hardware registers
145-
uint32_t actual_freq = getFlashFrequencyMHz();
146-
uint8_t source_freq = getFlashSourceFrequencyMHz();
147-
uint8_t divider = getFlashClockDivider();
145+
uint32_t actual_freq = ESP.getFlashFrequencyMHz();
146+
uint8_t source_freq = ESP.getFlashSourceFrequencyMHz();
147+
uint8_t divider = ESP.getFlashClockDivider();
148148

149149
chip_report_printf(" Bus Speed : %lu MHz\n", actual_freq);
150150
chip_report_printf(" Flash Frequency : %lu MHz (source: %u MHz, divider: %u)\n", actual_freq, source_freq, divider);
151151

152-
if (isFlashHighPerformanceModeEnabled()) {
152+
if (ESP.isFlashHighPerformanceModeEnabled()) {
153153
chip_report_printf(" HPM Mode : Enabled (> 80 MHz)\n");
154154
}
155155

@@ -341,115 +341,3 @@ void printAfterSetupInfo(void) {
341341
chip_report_printf("============ After Setup End =============\n");
342342
delay(20); //allow the print to finish
343343
}
344-
345-
// ============================================================================
346-
// Flash Frequency Runtime Detection
347-
// ============================================================================
348-
349-
// Define SPI0 base addresses for different chips
350-
#if CONFIG_IDF_TARGET_ESP32S3
351-
#define FLASH_SPI0_BASE 0x60003000
352-
#elif CONFIG_IDF_TARGET_ESP32S2
353-
#define FLASH_SPI0_BASE 0x3f402000
354-
#elif CONFIG_IDF_TARGET_ESP32C3
355-
#define FLASH_SPI0_BASE 0x60002000
356-
#elif CONFIG_IDF_TARGET_ESP32C2
357-
#define FLASH_SPI0_BASE 0x60002000
358-
#elif CONFIG_IDF_TARGET_ESP32C6
359-
#define FLASH_SPI0_BASE 0x60003000
360-
#elif CONFIG_IDF_TARGET_ESP32H2
361-
#define FLASH_SPI0_BASE 0x60003000
362-
#elif CONFIG_IDF_TARGET_ESP32
363-
#define FLASH_SPI0_BASE 0x3ff42000
364-
#else
365-
#define FLASH_SPI0_BASE 0x60003000 // Default for new chips
366-
#endif
367-
368-
// Register offsets
369-
#define FLASH_CORE_CLK_SEL_OFFSET 0x80
370-
#define FLASH_CLOCK_OFFSET 0x14
371-
372-
/**
373-
* @brief Read the source clock frequency from hardware registers
374-
* @return Source clock frequency in MHz (80, 120, 160, or 240)
375-
*/
376-
uint8_t getFlashSourceFrequencyMHz(void) {
377-
#if CONFIG_IDF_TARGET_ESP32
378-
// ESP32 classic supports 40 MHz and 80 MHz
379-
// Note: ESP32 uses the PLL clock (80 MHz) as source and divides it
380-
return 80; // Always 80 MHz source, divider determines 40/80 MHz
381-
#else
382-
volatile uint32_t* core_clk_reg = (volatile uint32_t*)(FLASH_SPI0_BASE + FLASH_CORE_CLK_SEL_OFFSET);
383-
uint32_t core_clk_sel = (*core_clk_reg) & 0x3; // Bits 0-1
384-
385-
uint8_t source_freq = 80; // Default
386-
387-
#if CONFIG_IDF_TARGET_ESP32S3
388-
switch (core_clk_sel) {
389-
case 0: source_freq = 80; break;
390-
case 1: source_freq = 120; break;
391-
case 2: source_freq = 160; break;
392-
case 3: source_freq = 240; break;
393-
}
394-
#elif CONFIG_IDF_TARGET_ESP32S2
395-
switch (core_clk_sel) {
396-
case 0: source_freq = 80; break;
397-
case 1: source_freq = 120; break;
398-
case 2: source_freq = 160; break;
399-
}
400-
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || \
401-
CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
402-
switch (core_clk_sel) {
403-
case 0: source_freq = 80; break;
404-
case 1: source_freq = 120; break;
405-
}
406-
#else
407-
switch (core_clk_sel) {
408-
case 0: source_freq = 80; break;
409-
case 1: source_freq = 120; break;
410-
default: source_freq = 80; break;
411-
}
412-
#endif
413-
414-
return source_freq;
415-
#endif
416-
}
417-
418-
/**
419-
* @brief Read the clock divider from hardware registers
420-
* @return Clock divider value (1 = no division, 2 = divide by 2, etc.)
421-
*/
422-
uint8_t getFlashClockDivider(void) {
423-
volatile uint32_t* clock_reg = (volatile uint32_t*)(FLASH_SPI0_BASE + FLASH_CLOCK_OFFSET);
424-
uint32_t clock_val = *clock_reg;
425-
426-
// Bit 31: if set, clock is 1:1 (no divider)
427-
if (clock_val & (1 << 31)) {
428-
return 1;
429-
}
430-
431-
// Bits 16-23: clkdiv_pre
432-
uint8_t clkdiv_pre = (clock_val >> 16) & 0xFF;
433-
return clkdiv_pre + 1;
434-
}
435-
436-
/**
437-
* @brief Get the actual flash frequency in MHz
438-
* @return Flash frequency in MHz
439-
*/
440-
uint32_t getFlashFrequencyMHz(void) {
441-
uint8_t source = getFlashSourceFrequencyMHz();
442-
uint8_t divider = getFlashClockDivider();
443-
444-
if (divider == 0) divider = 1; // Safety check
445-
446-
return source / divider;
447-
}
448-
449-
/**
450-
* @brief Check if High Performance Mode is enabled
451-
* @return true if flash runs > 80 MHz, false otherwise
452-
*/
453-
bool isFlashHighPerformanceModeEnabled(void) {
454-
return getFlashFrequencyMHz() > 80;
455-
}

‎cores/esp32/chip-debug-report.h‎

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -5,13 +5,5 @@
55
*/
66
#pragma once
77

8-
#include <stdint.h>
9-
108
void printBeforeSetupInfo(void);
119
void printAfterSetupInfo(void);
12-
13-
// Flash frequency runtime detection
14-
uint32_t getFlashFrequencyMHz(void);
15-
uint8_t getFlashSourceFrequencyMHz(void);
16-
uint8_t getFlashClockDivider(void);
17-
bool isFlashHighPerformanceModeEnabled(void);

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