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change(esp_hw_support): switch lp_cpu power mode with clock src to save lp_cpu working power
1 parent e051b92 commit 04b2afe

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13 files changed

+58
-50
lines changed

13 files changed

+58
-50
lines changed

‎components/esp_hw_support/include/esp_private/esp_pmu.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -49,6 +49,7 @@ typedef enum {
4949
#define RTC_SLEEP_DIG_USE_8M BIT(16)
5050
#define RTC_SLEEP_USE_ADC_TESEN_MONITOR BIT(17)
5151
#define RTC_SLEEP_NO_ULTRA_LOW BIT(18) //!< Avoid using ultra low power in deep sleep, in which RTCIO cannot be used as input, and RTCMEM can't work under high temperature
52+
#define RTC_SLEEP_XTAL_AS_RTC_FAST BIT(19)
5253

5354
#if SOC_PM_SUPPORT_EXT0_WAKEUP
5455
#define RTC_EXT0_TRIG_EN PMU_EXT0_WAKEUP_EN //!< EXT0 wakeup

‎components/esp_hw_support/port/esp32/include/soc/rtc.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -245,7 +245,7 @@ void rtc_clk_apll_enable(bool enable);
245245
*
246246
* @return
247247
* - 0 Failed
248-
* - else Sucess
248+
* - else Success
249249
*/
250250
uint32_t rtc_clk_apll_coeff_calc(uint32_t freq, uint32_t *_o_div, uint32_t *_sdm0, uint32_t *_sdm1, uint32_t *_sdm2);
251251

@@ -517,7 +517,7 @@ typedef struct rtc_sleep_config_s {
517517
#define RTC_SLEEP_DIG_USE_8M BIT(16)
518518
#define RTC_SLEEP_USE_ADC_TESEN_MONITOR BIT(17)
519519
#define RTC_SLEEP_NO_ULTRA_LOW BIT(18) //!< Avoid using ultra low power in deep sleep, in which RTCIO cannot be used as input, and RTCMEM can't work under high temperature
520-
520+
#define RTC_SLEEP_XTAL_AS_RTC_FAST BIT(19)
521521
/**
522522
* Default initializer for rtc_sleep_config_t
523523
*

‎components/esp_hw_support/port/esp32c2/include/soc/rtc.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -562,6 +562,7 @@ typedef struct {
562562
#define RTC_SLEEP_DIG_USE_8M BIT(16)
563563
#define RTC_SLEEP_USE_ADC_TESEN_MONITOR BIT(17)
564564
#define RTC_SLEEP_NO_ULTRA_LOW BIT(18) //!< Avoid using ultra low power in deep sleep, in which RTCIO cannot be used as input, and RTCMEM can't work under high temperature
565+
#define RTC_SLEEP_XTAL_AS_RTC_FAST BIT(19)
565566

566567
/**
567568
* Default initializer for rtc_sleep_config_t

‎components/esp_hw_support/port/esp32c3/include/soc/rtc.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -608,6 +608,7 @@ typedef struct {
608608
#define RTC_SLEEP_DIG_USE_8M BIT(16)
609609
#define RTC_SLEEP_USE_ADC_TESEN_MONITOR BIT(17)
610610
#define RTC_SLEEP_NO_ULTRA_LOW BIT(18) //!< Avoid using ultra low power in deep sleep, in which RTCIO cannot be used as input, and RTCMEM can't work under high temperature
611+
#define RTC_SLEEP_XTAL_AS_RTC_FAST BIT(19)
611612

612613
/**
613614
* Default initializer for rtc_sleep_config_t

‎components/esp_hw_support/port/esp32c6/pmu_sleep.c‎

Lines changed: 19 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -192,41 +192,35 @@ static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
192192

193193
const pmu_sleep_config_t* pmu_sleep_config_default(
194194
pmu_sleep_config_t *config,
195-
uint32_t pd_flags,
195+
uint32_t sleep_flags,
196196
uint32_t adjustment,
197197
uint32_t slowclk_period,
198198
uint32_t fastclk_period,
199199
bool dslp
200200
)
201201
{
202-
pmu_sleep_power_config_t power_default = PMU_SLEEP_POWER_CONFIG_DEFAULT(pd_flags);
203-
204-
uint32_t iram_pd_flags = 0;
205-
iram_pd_flags |= (pd_flags & PMU_SLEEP_PD_MEM_G0) ? BIT(0) : 0;
206-
iram_pd_flags |= (pd_flags & PMU_SLEEP_PD_MEM_G1) ? BIT(1) : 0;
207-
iram_pd_flags |= (pd_flags & PMU_SLEEP_PD_MEM_G2) ? BIT(2) : 0;
208-
iram_pd_flags |= (pd_flags & PMU_SLEEP_PD_MEM_G3) ? BIT(3) : 0;
202+
pmu_sleep_power_config_t power_default = PMU_SLEEP_POWER_CONFIG_DEFAULT(sleep_flags);
209203
config->power = power_default;
210204

211-
pmu_sleep_param_config_t param_default = PMU_SLEEP_PARAM_CONFIG_DEFAULT(pd_flags);
212-
config->param = *pmu_sleep_param_config_default(&param_default, &power_default, pd_flags, adjustment, slowclk_period, fastclk_period);
205+
pmu_sleep_param_config_t param_default = PMU_SLEEP_PARAM_CONFIG_DEFAULT(sleep_flags);
206+
config->param = *pmu_sleep_param_config_default(&param_default, &power_default, sleep_flags, adjustment, slowclk_period, fastclk_period);
213207

214208
if (dslp) {
215209
config->param.lp_sys.analog_wait_target_cycle = rtc_time_us_to_slowclk(PMU_LP_ANALOG_WAIT_TARGET_TIME_DSLP_US, slowclk_period);
216-
pmu_sleep_analog_config_t analog_default = PMU_SLEEP_ANALOG_DSLP_CONFIG_DEFAULT(pd_flags);
210+
pmu_sleep_analog_config_t analog_default = PMU_SLEEP_ANALOG_DSLP_CONFIG_DEFAULT(sleep_flags);
217211
analog_default.lp_sys[LP(SLEEP)].analog.dbg_atten = get_dslp_dbg();
218212
analog_default.lp_sys[LP(SLEEP)].analog.dbias = get_dslp_lp_dbias();
219213
config->analog = analog_default;
220214
} else {
221-
pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_LSLP_CONFIG_DEFAULT(pd_flags);
215+
pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_LSLP_CONFIG_DEFAULT(sleep_flags);
222216
config->digital = digital_default;
223217

224-
pmu_sleep_analog_config_t analog_default = PMU_SLEEP_ANALOG_LSLP_CONFIG_DEFAULT(pd_flags);
218+
pmu_sleep_analog_config_t analog_default = PMU_SLEEP_ANALOG_LSLP_CONFIG_DEFAULT(sleep_flags);
225219
analog_default.hp_sys.analog.dbg_atten = get_lslp_dbg();
226220
analog_default.hp_sys.analog.dbias = get_lslp_hp_dbias();
227221
analog_default.lp_sys[LP(SLEEP)].analog.dbias = PMU_LP_DBIAS_LIGHTSLEEP_0V7_DEFAULT;
228222

229-
if (!(pd_flags & PMU_SLEEP_PD_XTAL)){
223+
if (!(sleep_flags & PMU_SLEEP_PD_XTAL)){
230224
analog_default.hp_sys.analog.pd_cur = PMU_PD_CUR_SLEEP_ON;
231225
analog_default.hp_sys.analog.bias_sleep = PMU_BIASSLP_SLEEP_ON;
232226
analog_default.hp_sys.analog.dbg_atten = PMU_DBG_ATTEN_ACTIVE_DEFAULT;
@@ -236,14 +230,24 @@ const pmu_sleep_config_t* pmu_sleep_config_default(
236230
analog_default.lp_sys[LP(SLEEP)].analog.bias_sleep = PMU_BIASSLP_SLEEP_ON;
237231
analog_default.lp_sys[LP(SLEEP)].analog.dbg_atten = PMU_DBG_ATTEN_ACTIVE_DEFAULT;
238232
analog_default.lp_sys[LP(SLEEP)].analog.dbias = get_act_lp_dbias();
239-
} else if (!(pd_flags & PMU_SLEEP_PD_RC_FAST)) {
233+
} else if (!(sleep_flags & PMU_SLEEP_PD_RC_FAST)) {
240234
analog_default.hp_sys.analog.dbias = get_act_hp_dbias();
241235
analog_default.lp_sys[LP(SLEEP)].analog.dbg_atten = PMU_DBG_ATTEN_LIGHTSLEEP_NODROP;
242236
analog_default.lp_sys[LP(SLEEP)].analog.dbias = get_act_lp_dbias();
243237
}
244238

245239
config->analog = analog_default;
246240
}
241+
242+
if (sleep_flags & RTC_SLEEP_XTAL_AS_RTC_FAST) {
243+
// Keep XTAL on in HP_SLEEP state if it is the clock source of RTC_FAST
244+
power_default.hp_sys.xtal.xpd_xtal = 1;
245+
config->analog.hp_sys.analog.pd_cur = PMU_PD_CUR_SLEEP_ON;
246+
config->analog.hp_sys.analog.bias_sleep = PMU_BIASSLP_SLEEP_ON;
247+
config->analog.hp_sys.analog.dbg_atten = PMU_DBG_ATTEN_ACTIVE_DEFAULT;
248+
config->analog.hp_sys.analog.dbias = get_act_hp_dbias();
249+
}
250+
247251
return config;
248252
}
249253

‎components/esp_hw_support/port/esp32c6/private_include/pmu_param.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -365,8 +365,8 @@ typedef struct {
365365
#define PMU_SLEEP_ANALOG_DSLP_CONFIG_DEFAULT(pd_flags) { \
366366
.hp_sys = { \
367367
.analog = { \
368-
.pd_cur = PMU_PD_CUR_SLEEP_ON, \
369-
.bias_sleep = PMU_BIASSLP_SLEEP_ON, \
368+
.pd_cur = PMU_PD_CUR_SLEEP_DEFAULT, \
369+
.bias_sleep = PMU_BIASSLP_SLEEP_DEFAULT, \
370370
.xpd = PMU_HP_XPD_DEEPSLEEP, \
371371
.dbg_atten = PMU_DBG_HP_DEEPSLEEP \
372372
} \

‎components/esp_hw_support/port/esp32p4/pmu_sleep.c‎

Lines changed: 19 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -138,58 +138,44 @@ static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
138138

139139
const pmu_sleep_config_t* pmu_sleep_config_default(
140140
pmu_sleep_config_t *config,
141-
uint32_t pd_flags,
141+
uint32_t sleep_flags,
142142
uint32_t adjustment,
143143
uint32_t slowclk_period,
144144
uint32_t fastclk_period,
145145
bool dslp
146146
)
147147
{
148-
pmu_sleep_power_config_t power_default = PMU_SLEEP_POWER_CONFIG_DEFAULT(pd_flags);
149-
150-
uint32_t iram_pd_flags = 0;
151-
iram_pd_flags |= (pd_flags & PMU_SLEEP_PD_MEM_G0) ? BIT(0) : 0;
152-
iram_pd_flags |= (pd_flags & PMU_SLEEP_PD_MEM_G1) ? BIT(1) : 0;
153-
iram_pd_flags |= (pd_flags & PMU_SLEEP_PD_MEM_G2) ? BIT(2) : 0;
154-
iram_pd_flags |= (pd_flags & PMU_SLEEP_PD_MEM_G3) ? BIT(3) : 0;
148+
pmu_sleep_power_config_t power_default = PMU_SLEEP_POWER_CONFIG_DEFAULT(sleep_flags);
155149

156150
if (dslp) {
157151
config->param.lp_sys.analog_wait_target_cycle = rtc_time_us_to_slowclk(PMU_LP_ANALOG_WAIT_TARGET_TIME_DSLP_US, slowclk_period);
158152

159-
pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(pd_flags);
153+
pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(sleep_flags);
160154
config->digital = digital_default;
161155

162-
pmu_sleep_analog_config_t analog_default = PMU_SLEEP_ANALOG_DSLP_CONFIG_DEFAULT(pd_flags);
163-
#if CONFIG_RTC_FAST_CLK_SRC_XTAL
164-
analog_default.hp_sys.analog.pd_cur = PMU_PD_CUR_SLEEP_ON;
165-
analog_default.hp_sys.analog.bias_sleep = PMU_BIASSLP_SLEEP_ON;
166-
analog_default.hp_sys.analog.dbg_atten = PMU_DBG_ATTEN_ACTIVE_DEFAULT;
167-
#endif
156+
pmu_sleep_analog_config_t analog_default = PMU_SLEEP_ANALOG_DSLP_CONFIG_DEFAULT(sleep_flags);
168157
config->analog = analog_default;
169158
} else {
170159
// Get light sleep digital_default
171-
pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_LSLP_CONFIG_DEFAULT(pd_flags);
160+
pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_LSLP_CONFIG_DEFAULT(sleep_flags);
172161
config->digital = digital_default;
173162

174163
// Get light sleep analog default
175-
pmu_sleep_analog_config_t analog_default = PMU_SLEEP_ANALOG_LSLP_CONFIG_DEFAULT(pd_flags);
164+
pmu_sleep_analog_config_t analog_default = PMU_SLEEP_ANALOG_LSLP_CONFIG_DEFAULT(sleep_flags);
176165

177-
#if !CONFIG_ESP_SLEEP_POWER_DOWN_FLASH
166+
#if CONFIG_SPIRAM
178167
analog_default.hp_sys.analog.pd_cur = PMU_PD_CUR_SLEEP_ON;
179168
analog_default.lp_sys[PMU_MODE_LP_SLEEP].analog.pd_cur = PMU_PD_CUR_SLEEP_ON;
180169
#endif
181170

182-
#if !CONFIG_RTC_FAST_CLK_SRC_XTAL
183-
if (!(pd_flags & PMU_SLEEP_PD_XTAL))
184-
#endif
171+
if (!(sleep_flags & PMU_SLEEP_PD_XTAL))
185172
{
186173
// Analog parameters in HP_SLEEP
187174
analog_default.hp_sys.analog.pd_cur = PMU_PD_CUR_SLEEP_ON;
188175
analog_default.hp_sys.analog.bias_sleep = PMU_BIASSLP_SLEEP_ON;
189176
analog_default.hp_sys.analog.dbg_atten = PMU_DBG_ATTEN_ACTIVE_DEFAULT;
190-
}
177+
analog_default.hp_sys.analog.dbias = HP_CALI_ACTIVE_DBIAS_DEFAULT;
191178

192-
if (!(pd_flags & PMU_SLEEP_PD_XTAL)) {
193179
// Analog parameters in LP_SLEEP
194180
analog_default.lp_sys[LP(SLEEP)].analog.pd_cur = PMU_PD_CUR_SLEEP_ON;
195181
analog_default.lp_sys[LP(SLEEP)].analog.bias_sleep = PMU_BIASSLP_SLEEP_ON;
@@ -207,13 +193,18 @@ const pmu_sleep_config_t* pmu_sleep_config_default(
207193
config->analog = analog_default;
208194
}
209195

210-
#if CONFIG_RTC_FAST_CLK_SRC_XTAL
211-
power_default.hp_sys.xtal.xpd_xtal = 1;
212-
#endif
196+
if (sleep_flags & RTC_SLEEP_XTAL_AS_RTC_FAST) {
197+
// Keep XTAL on in HP_SLEEP state if it is the clock source of RTC_FAST
198+
power_default.hp_sys.xtal.xpd_xtal = 1;
199+
config->analog.hp_sys.analog.pd_cur = PMU_PD_CUR_SLEEP_ON;
200+
config->analog.hp_sys.analog.bias_sleep = PMU_BIASSLP_SLEEP_ON;
201+
config->analog.hp_sys.analog.dbg_atten = PMU_DBG_ATTEN_ACTIVE_DEFAULT;
202+
config->analog.hp_sys.analog.dbias = HP_CALI_ACTIVE_DBIAS_DEFAULT;
203+
}
213204

214205
config->power = power_default;
215-
pmu_sleep_param_config_t param_default = PMU_SLEEP_PARAM_CONFIG_DEFAULT(pd_flags);
216-
config->param = *pmu_sleep_param_config_default(&param_default, &power_default, pd_flags, adjustment, slowclk_period, fastclk_period);
206+
pmu_sleep_param_config_t param_default = PMU_SLEEP_PARAM_CONFIG_DEFAULT(sleep_flags);
207+
config->param = *pmu_sleep_param_config_default(&param_default, &power_default, sleep_flags, adjustment, slowclk_period, fastclk_period);
217208

218209
return config;
219210
}

‎components/esp_hw_support/port/esp32p4/private_include/pmu_param.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -382,8 +382,8 @@ typedef struct {
382382
#define PMU_SLEEP_ANALOG_DSLP_CONFIG_DEFAULT(pd_flags) { \
383383
.hp_sys = { \
384384
.analog = { \
385-
.pd_cur = PMU_PD_CUR_SLEEP_ON, \
386-
.bias_sleep = PMU_BIASSLP_SLEEP_ON, \
385+
.pd_cur = PMU_PD_CUR_SLEEP_DEFAULT, \
386+
.bias_sleep = PMU_BIASSLP_SLEEP_DEFAULT, \
387387
.xpd = PMU_HP_XPD_DEEPSLEEP, \
388388
.dbg_atten = PMU_DBG_HP_DEEPSLEEP \
389389
} \

‎components/esp_hw_support/port/esp32s2/include/soc/rtc.h‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -331,7 +331,7 @@ void rtc_clk_apll_enable(bool enable);
331331
*
332332
* @return
333333
* - 0 Failed
334-
* - else Sucess
334+
* - else Success
335335
*/
336336
uint32_t rtc_clk_apll_coeff_calc(uint32_t freq, uint32_t *_o_div, uint32_t *_sdm0, uint32_t *_sdm1, uint32_t *_sdm2);
337337

@@ -633,6 +633,7 @@ typedef struct {
633633
#define RTC_SLEEP_DIG_USE_8M BIT(16)
634634
#define RTC_SLEEP_USE_ADC_TESEN_MONITOR BIT(17)
635635
#define RTC_SLEEP_NO_ULTRA_LOW BIT(18) //!< Avoid using ultra low power in deep sleep, in which RTCIO cannot be used as input, and RTCMEM can't work under high temperature
636+
#define RTC_SLEEP_XTAL_AS_RTC_FAST BIT(19)
636637

637638
/**
638639
* Default initializer for rtc_sleep_config_t

‎components/esp_hw_support/port/esp32s3/include/soc/rtc.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -619,6 +619,7 @@ typedef struct {
619619
#define RTC_SLEEP_DIG_USE_8M BIT(16)
620620
#define RTC_SLEEP_USE_ADC_TESEN_MONITOR BIT(17)
621621
#define RTC_SLEEP_NO_ULTRA_LOW BIT(18) //!< Avoid using ultra low power in deep sleep, in which RTCIO cannot be used as input, and RTCMEM can't work under high temperature
622+
#define RTC_SLEEP_XTAL_AS_RTC_FAST BIT(19)
622623

623624
/**
624625
* Default initializer for rtc_sleep_config_t

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