feat(rom): update rom for c5 eco2

Breaking: Starting from this commit, ESP-IDF can only support ESP32-C5 v1.0 (ECO2)

Author: L-KAYA

Kconfig

@@ -118,6 +118,8 @@ mainmenu "Espressif IoT Development Framework Configuration"
         default "y" if IDF_TARGET="esp32c5"
         select FREERTOS_UNICORE
         select IDF_TARGET_ARCH_RISCV
+        # TODO: [ESPTOOL-1044] remove when stub supported
+        select ESPTOOLPY_NO_STUB
 
     config IDF_TARGET_ESP32P4
         bool

components/bootloader/subproject/main/ld/esp32c5/bootloader.ld

@@ -7,20 +7,20 @@
  *  Make sure the bootloader can load into main memory without overwriting itself.
  *
  *  ESP32-C5 ROM static data usage is as follows:
- *  - 0x4084e9a0 - 0x4085c9a0: Shared buffers, used in UART/USB/SPI download mode only
- *  - 0x4085c9a0 - 0x4085e9a0: PRO CPU stack, can be reclaimed as heap after RTOS startup
- *  - 0x4085e9a0 - 0x40860000: ROM .bss and .data (not easily reclaimable)
+ *  - 0x4084e5a0 - 0x4085c5a0: Shared buffers, used in UART/USB/SPI download mode only
+ *  - 0x4085c5a0 - 0x4085e5a0: PRO CPU stack, can be reclaimed as heap after RTOS startup
+ *  - 0x4085e5a0 - 0x40860000: ROM .bss and .data (not easily reclaimable)
  *
  *  The 2nd stage bootloader can take space up to the end of ROM shared
- *  buffers area (0x4085c9a0).
+ *  buffers area (0x4085c5a0).
  */
 
-/* We consider 0x4085c9a0 to be the last usable address for 2nd stage bootloader stack overhead, dram_seg,
+/* We consider 0x4085c5a0 to be the last usable address for 2nd stage bootloader stack overhead, dram_seg,
  * and work out iram_seg and iram_loader_seg addresses from there, backwards.
  */
 
 /* These lengths can be adjusted, if necessary: */
-bootloader_usable_dram_end = 0x4085c9a0;
+bootloader_usable_dram_end = 0x4085c5a0;
 bootloader_stack_overhead = 0x2000; /* For safety margin between bootloader data section and startup stacks */
 bootloader_dram_seg_len = 0x5000;
 bootloader_iram_loader_seg_len = 0x7000;
@@ -45,7 +45,7 @@ MEMORY
  * 2. Update the value in this assert.
  * 3. Update SRAM_DRAM_END in components/esp_system/ld/esp32c5/memory.ld.in to the same value.
  */
-ASSERT(bootloader_iram_loader_seg_start == 0x4084E9A0, "bootloader_iram_loader_seg_start inconsistent with SRAM_DRAM_END");
+ASSERT(bootloader_iram_loader_seg_start == 0x4084e5a0, "bootloader_iram_loader_seg_start inconsistent with SRAM_DRAM_END");
 
 /* Default entry point: */
 ENTRY(call_start_cpu0);
@@ -277,32 +277,32 @@ SECTIONS
 /**
  *  Appendix: Memory Usage of ROM bootloader
  *
- * 0x4084e9a0 ------------------> _dram0_0_start
+ * 0x4084e5a0 ------------------> _dram0_0_start
  *            |               |
  *            |               |
  *            |               |   1. Large buffers that are only used in certain boot modes, see shared_buffers.h
  *            |               |
  *            |               |
- * 0x4085c9a0 ------------------> __stack_sentry
+ * 0x4085c5a0 ------------------> __stack_sentry
  *            |               |
  *            |               |   2. Startup pro cpu stack (freed when IDF app is running)
  *            |               |
- * 0x4085e9a0 ------------------> __stack (pro cpu)
+ * 0x4085e5a0 ------------------> __stack (pro cpu)
  *            |               |
  *            |               |
  *            |               |   3. Shared memory only used in startup code or nonos/early boot*
  *            |               |      (can be freed when IDF runs)
  *            |               |
  *            |               |
- * 0x4085f500 ------------------> _dram0_rtos_reserved_start
+ * 0x4085f4f8 ------------------> _dram0_rtos_reserved_start
  *            |               |
  *            |               |
  *            |               |   4. Shared memory used in startup code and when IDF runs
  *            |               |
  *            |               |
- * 0x4085fc5c ------------------> _dram0_rtos_reserved_end
+ * 0x4085fbb4 ------------------> _dram0_rtos_reserved_end
  *            |               |
- * 0x4085fc70 ------------------> _data_start_interface
+ * 0x4085fc60 ------------------> _data_start_interface
  *            |               |
  *            |               |   5. End of DRAM is the 'interface' data with constant addresses (ECO compatible)
  *            |               |

components/esp_hw_support/port/esp32c5/Kconfig.hw_support

@@ -1,6 +1,6 @@
 choice ESP32C5_REV_MIN
     prompt "Minimum Supported ESP32-C5 Revision"
-    default ESP32C5_REV_MIN_0
+    default ESP32C5_REV_MIN_100
     help
         Required minimum chip revision. ESP-IDF will check for it and
         reject to boot if the chip revision fails the check.
@@ -9,16 +9,13 @@ choice ESP32C5_REV_MIN
         The complied binary will only support chips above this revision,
         this will also help to reduce binary size.
 
-    config ESP32C5_REV_MIN_0
-        bool "Rev v0.0 (ECO0)"
-    config ESP32C5_REV_MIN_1
-        bool "Rev v0.1 (ECO1)"
+    config ESP32C5_REV_MIN_100
+        bool "Rev v1.0 (ECO2)"
 endchoice
 
 config ESP32C5_REV_MIN_FULL
     int
-    default 0 if ESP32C5_REV_MIN_0
-    default 1 if ESP32C5_REV_MIN_1
+    default 100 if ESP32C5_REV_MIN_100
 
 config ESP_REV_MIN_FULL
     int
@@ -28,15 +25,15 @@ config ESP_REV_MIN_FULL
     # MAX Revision
     #
 
-    comment "Maximum Supported ESP32-C5 Revision (Rev v0.99)"
+    comment "Maximum Supported ESP32-C5 Revision (Rev v1.99)"
     # Maximum revision that IDF supports.
     # It can not be changed by user.
     # Only Espressif can change it when a new version will be supported in IDF.
     # Supports all chips starting from ESP32C5_REV_MIN_FULL to ESP32C5_REV_MAX_FULL
 
 config ESP32C5_REV_MAX_FULL
     int
-    default 99
+    default 199
     # keep in sync the "Maximum Supported Revision" description with this value
 
 config ESP_REV_MAX_FULL

components/esp_rom/esp32c5/Kconfig.soc_caps.in

@@ -75,7 +75,7 @@ config ESP_ROM_HAS_NEWLIB
     bool
     default y
 
-config ESP_ROM_HAS_NEWLIB_NORMAL_FORMAT
+config ESP_ROM_HAS_NEWLIB_NANO_FORMAT
     bool
     default y
 

components/esp_rom/esp32c5/esp_rom_caps.h

@@ -24,7 +24,7 @@
 #define ESP_ROM_HAS_SPI_FLASH_MMAP          (1) // ROM has the implementation of SPI Flash mmap driver
 #define ESP_ROM_WITHOUT_REGI2C              (1) // ROM has no regi2c APIs       TODO: IDF-10110 need refactor
 #define ESP_ROM_HAS_NEWLIB                  (1) // ROM has newlib (at least parts of it) functions included
-#define ESP_ROM_HAS_NEWLIB_NORMAL_FORMAT    (1) // ROM has the newlib normal/full version of formatting functions (as opposed to the nano versions)
+#define ESP_ROM_HAS_NEWLIB_NANO_FORMAT      (1) // ROM has the newlib nano version of formatting functions
 #define ESP_ROM_WDT_INIT_PATCH              (1) // ROM version does not configure the clock
 #define ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE    (1) // ROM needs to set cache MMU size according to instruction and rodata for flash mmap
 #define ESP_ROM_RAM_APP_NEEDS_MMU_INIT      (1) // ROM doesn't init cache MMU when it's a RAM APP, needs MMU hal to init

components/esp_rom/esp32c5/ld/esp32c5.rom.api.ld

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */

components/esp_rom/esp32c5/ld/esp32c5.rom.coexist.ld

@@ -1,14 +1,14 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 /* ROM function interface esp32c5.rom.coexist.ld for esp32c5
  *
  *
- * Generated from ./target/esp32c5/interface-esp32c5.yml md5sum f5c146321f24f88ad1f27234da5aed11
+ * Generated from ./target/esp32c5/interface-esp32c5.yml md5sum 4dfe6ccc311ca3575012c23e3753353c
  *
- * Compatible with ROM where ECO version equal or greater to 0.
+ * Compatible with ROM where ECO version equal or greater to 2.
  *
  * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
  */

components/esp_rom/esp32c5/ld/esp32c5.rom.heap.ld

@@ -1,14 +1,14 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 /* ROM function interface esp32c5.rom.heap.ld for esp32c5
  *
  *
- * Generated from ./target/esp32c5/interface-esp32c5.yml md5sum f5c146321f24f88ad1f27234da5aed11
+ * Generated from ./target/esp32c5/interface-esp32c5.yml md5sum 4dfe6ccc311ca3575012c23e3753353c
  *
- * Compatible with ROM where ECO version equal or greater to 0.
+ * Compatible with ROM where ECO version equal or greater to 2.
  *
  * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
  */

components/esp_rom/esp32c5/ld/esp32c5.rom.ld

@@ -1,14 +1,14 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 /* ROM function interface esp32c5.rom.ld for esp32c5
  *
  *
- * Generated from ./target/esp32c5/interface-esp32c5.yml md5sum f5c146321f24f88ad1f27234da5aed11
+ * Generated from ./target/esp32c5/interface-esp32c5.yml md5sum 4dfe6ccc311ca3575012c23e3753353c
  *
- * Compatible with ROM where ECO version equal or greater to 0.
+ * Compatible with ROM where ECO version equal or greater to 2.
  *
  * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
  */
@@ -429,3 +429,60 @@ usb_serial_device_rx_one_char = 0x40000ab8;
 usb_serial_device_rx_one_char_block = 0x40000abc;
 usb_serial_device_tx_flush = 0x40000ac0;
 usb_serial_device_tx_one_char = 0x40000ac4;
+
+
+/***************************************
+ Group recovery_bootloader
+ ***************************************/
+
+/* Functions */
+ets_get_bootloader_offset = 0x40001544;
+ets_set_bootloader_offset = 0x40001548;
+
+
+/***************************************
+ Group lldesc
+ ***************************************/
+
+/* Functions */
+lldesc_build_chain = 0x4000154c;
+
+
+/***************************************
+ Group sip
+ ***************************************/
+
+/* Functions */
+sip_after_tx_complete = 0x40001550;
+sip_alloc_to_host_evt = 0x40001554;
+sip_download_begin = 0x40001558;
+sip_get_ptr = 0x4000155c;
+sip_get_state = 0x40001560;
+sip_init_attach = 0x40001564;
+sip_install_rx_ctrl_cb = 0x40001568;
+sip_install_rx_data_cb = 0x4000156c;
+sip_is_active = 0x40001570;
+sip_post_init = 0x40001574;
+sip_reclaim_from_host_cmd = 0x40001578;
+sip_reclaim_tx_data_pkt = 0x4000157c;
+sip_send = 0x40001580;
+sip_to_host_chain_append = 0x40001584;
+sip_to_host_evt_send_done = 0x40001588;
+
+
+/***************************************
+ Group slc
+ ***************************************/
+
+/* Functions */
+slc_add_credits = 0x4000158c;
+slc_enable = 0x40001590;
+slc_from_host_chain_fetch = 0x40001594;
+slc_from_host_chain_recycle = 0x40001598;
+slc_has_pkt_to_host = 0x4000159c;
+slc_init_attach = 0x400015a0;
+slc_init_credit = 0x400015a4;
+slc_reattach = 0x400015a8;
+slc_send_to_host_chain = 0x400015ac;
+slc_set_host_io_max_window = 0x400015b0;
+slc_to_host_chain_recycle = 0x400015b4;

components/esp_rom/esp32c5/ld/esp32c5.rom.libc.ld

@@ -3,6 +3,21 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+/* ROM function interface esp32c5.rom.libc.ld for esp32c5
+ *
+ *
+ * Generated from ./target/esp32c5/interface-esp32c5.yml md5sum e68b5b3e3d244713e5743335f3857c57
+ *
+ * Compatible with ROM where ECO version equal or greater to 0.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+
+/***************************************
+ Group libc
+ ***************************************/
+
+/* Functions */
 esp_rom_newlib_init_common_mutexes = 0x400004b4;
 memset = 0x400004b8;
 strlen = 0x400004d8;