Merge branch 'feat/support_weight_arbitration_on_c61' into 'master'

feat(gdma): support gdma weighted arbitration on c61 v1.0

Closes IDF-12882, IDF-9310, and IDF-12090

See merge request espressif/esp-idf!39710

Author: Kainarx

components/esp_hw_support/test_apps/dma/sdkconfig.defaults.esp32c61

@@ -0,0 +1,2 @@
+CONFIG_SPIRAM=y
+CONFIG_SPIRAM_SPEED_80M=y

components/hal/esp32c61/include/hal/ahb_dma_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -22,6 +22,7 @@ extern "C" {
 #define AHB_DMA_LL_GET_HW(id) (((id) == 0) ? (&AHB_DMA) : NULL)
 
 #define GDMA_LL_CHANNEL_MAX_PRIORITY 5 // supported priority levels: [0,5]
+#define GDMA_LL_CHANNEL_MAX_WEIGHT   15  // supported weight levels: [0,15]
 
 #define GDMA_LL_RX_EVENT_MASK       (0x7F)
 #define GDMA_LL_TX_EVENT_MASK       (0x3F)
@@ -130,6 +131,25 @@ static inline void ahb_dma_ll_set_default_memory_range(ahb_dma_dev_t *dev)
     dev->intr_mem_end_addr.val = 0x44000000;
 }
 
+/**
+ * @brief Enable the weighted arbitration for AHB-DMA
+ */
+static inline void ahb_dma_ll_enable_weighted_arb(ahb_dma_dev_t *dev, bool enable)
+{
+    dev->weight_en.weight_en = enable;
+}
+
+/**
+ * @brief Set the weighted arbitration timeout for AHB-DMA
+ *
+ * @param timeout AHB bus clock cycle
+ */
+static inline void ahb_dma_ll_set_weighted_arb_timeout(ahb_dma_dev_t *dev, uint32_t timeout)
+{
+    HAL_ASSERT(timeout != 0 && timeout <= 65535);
+    dev->arb_timeout.arb_timeout_num = timeout;
+}
+
 ///////////////////////////////////// RX /////////////////////////////////////////
 /**
  * @brief Get DMA RX channel interrupt status word
@@ -212,6 +232,9 @@ static inline void ahb_dma_ll_rx_set_burst_size(ahb_dma_dev_t *dev, uint32_t cha
     case 32:
         burst_mode = 2; // incr8
         break;
+    case 64:
+        burst_mode = 3; // incr16
+        break;
     default:
         HAL_ASSERT(false);
         break;
@@ -380,6 +403,22 @@ static inline void ahb_dma_ll_rx_enable_etm_task(ahb_dma_dev_t *dev, uint32_t ch
     dev->channel[channel].in.in_conf0.in_etm_en_chn = enable;
 }
 
+/**
+ * @brief Enable the weighted arbitration optimize for DMA RX channel
+ */
+static inline void ahb_dma_ll_rx_enable_weighted_arb_opt(ahb_dma_dev_t *dev, uint32_t channel, bool enable)
+{
+    dev->in_crc_arb[channel].arb_weight_opt.rx_arb_weight_opt_dis_chn = !enable;
+}
+
+/**
+ * @brief Set the weight for DMA RX channel
+ */
+static inline void ahb_dma_ll_rx_set_weight(ahb_dma_dev_t *dev, uint32_t channel, uint32_t weight)
+{
+    dev->in_crc_arb[channel].ch_arb_weight.rx_arb_weight_value_chn = weight;
+}
+
 ///////////////////////////////////// TX /////////////////////////////////////////
 /**
  * @brief Get DMA TX channel interrupt status word
@@ -462,6 +501,9 @@ static inline void ahb_dma_ll_tx_set_burst_size(ahb_dma_dev_t *dev, uint32_t cha
     case 32:
         burst_mode = 2; // incr8
         break;
+    case 64:
+        burst_mode = 3; // incr16
+        break;
     default:
         HAL_ASSERT(false);
         break;
@@ -628,6 +670,22 @@ static inline void ahb_dma_ll_tx_enable_etm_task(ahb_dma_dev_t *dev, uint32_t ch
     dev->channel[channel].out.out_conf0.out_etm_en_chn = enable;
 }
 
+/**
+ * @brief Enable the weighted arbitration optimize for DMA TX channel
+ */
+static inline void ahb_dma_ll_tx_enable_weighted_arb_opt(ahb_dma_dev_t *dev, uint32_t channel, bool enable)
+{
+    dev->out_crc_arb[channel].arb_weight_opt.tx_arb_weight_opt_dis_chn = !enable;
+}
+
+/**
+ * @brief Set the weight for DMA TX channel
+ */
+static inline void ahb_dma_ll_tx_set_weight(ahb_dma_dev_t *dev, uint32_t channel, uint32_t weight)
+{
+    dev->out_crc_arb[channel].ch_arb_weight.tx_arb_weight_value_chn = weight;
+}
+
 #ifdef __cplusplus
 }
 #endif

components/soc/esp32c61/include/soc/Kconfig.soc_caps.in

@@ -367,6 +367,14 @@ config SOC_GDMA_SUPPORT_SLEEP_RETENTION
     bool
     default y
 
+config SOC_AHB_GDMA_SUPPORT_PSRAM
+    bool
+    default y
+
+config SOC_GDMA_SUPPORT_WEIGHTED_ARBITRATION
+    bool
+    default y
+
 config SOC_ETM_GROUPS
     int
     default 1
@@ -779,6 +787,10 @@ config SOC_SPIRAM_XIP_SUPPORTED
     bool
     default y
 
+config SOC_PSRAM_DMA_CAPABLE
+    bool
+    default y
+
 config SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE
     bool
     default y

components/soc/esp32c61/include/soc/soc_caps.h

@@ -152,6 +152,8 @@
 #define SOC_GDMA_PAIRS_PER_GROUP_MAX    2
 #define SOC_GDMA_SUPPORT_ETM            1  // Support ETM submodule
 #define SOC_GDMA_SUPPORT_SLEEP_RETENTION    1
+#define SOC_AHB_GDMA_SUPPORT_PSRAM 1
+#define SOC_GDMA_SUPPORT_WEIGHTED_ARBITRATION   1
 
 /*-------------------------- ETM CAPS --------------------------------------*/
 #define SOC_ETM_GROUPS                  1U  // Number of ETM groups
@@ -335,6 +337,7 @@
 
 /*-------------------------- SPIRAM CAPS ----------------------------------------*/
 #define SOC_SPIRAM_XIP_SUPPORTED        1
+#define SOC_PSRAM_DMA_CAPABLE           1
 
 /*-------------------------- SPI MEM CAPS ---------------------------------------*/
 #define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE                (1)

components/soc/esp32c61/register/soc/ahb_dma_struct.h

@@ -1050,117 +1050,61 @@ typedef union {
     uint32_t val;
 } ahb_dma_out_done_des_addr_ch1_reg_t;
 
-/** Type of tx_ch_arb_weight_ch0 register
- *  TX channel 0 arbitration weight configuration register
+/** Type of tx_ch_arb_weight_chn register
+ *  TX channel n arbitration weight configuration register
  */
 typedef union {
     struct {
-        /** tx_arb_weight_value_ch0 : R/W; bitpos: [3:0]; default: 0;
+        /** tx_arb_weight_value_chn : R/W; bitpos: [3:0]; default: 0;
          *  Configures the weight(i.e the number of tokens) of TX channel0
          */
-        uint32_t tx_arb_weight_value_ch0:4;
+        uint32_t tx_arb_weight_value_chn:4;
         uint32_t reserved_4:28;
     };
     uint32_t val;
-} ahb_dma_tx_ch_arb_weight_ch0_reg_t;
+} ahb_dma_tx_ch_arb_weight_chn_reg_t;
 
-/** Type of tx_arb_weight_opt_dir_ch0 register
- *  TX channel 0 weight arbitration optimization enable register
+/** Type of tx_arb_weight_opt_dir_chn register
+ *  TX channel n weight arbitration optimization enable register
  */
 typedef union {
     struct {
-        /** tx_arb_weight_opt_dis_ch0 : R/W; bitpos: [0]; default: 0;
+        /** tx_arb_weight_opt_dis_chn : R/W; bitpos: [0]; default: 0;
          *  reserved
          */
-        uint32_t tx_arb_weight_opt_dis_ch0:1;
+        uint32_t tx_arb_weight_opt_dis_chn:1;
         uint32_t reserved_1:31;
     };
     uint32_t val;
-} ahb_dma_tx_arb_weight_opt_dir_ch0_reg_t;
+} ahb_dma_tx_arb_weight_opt_dir_chn_reg_t;
 
-/** Type of tx_ch_arb_weight_ch1 register
- *  TX channel 1 arbitration weight configuration register
+/** Type of rx_ch_arb_weight_chn register
+ *  RX channel n arbitration weight configuration register
  */
 typedef union {
     struct {
-        /** tx_arb_weight_value_ch1 : R/W; bitpos: [3:0]; default: 0;
-         *  Configures the weight(i.e the number of tokens) of TX channel1
-         */
-        uint32_t tx_arb_weight_value_ch1:4;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} ahb_dma_tx_ch_arb_weight_ch1_reg_t;
-
-/** Type of tx_arb_weight_opt_dir_ch1 register
- *  TX channel 1 weight arbitration optimization enable register
- */
-typedef union {
-    struct {
-        /** tx_arb_weight_opt_dis_ch1 : R/W; bitpos: [0]; default: 0;
-         *  reserved
-         */
-        uint32_t tx_arb_weight_opt_dis_ch1:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} ahb_dma_tx_arb_weight_opt_dir_ch1_reg_t;
-
-/** Type of rx_ch_arb_weight_ch0 register
- *  RX channel 0 arbitration weight configuration register
- */
-typedef union {
-    struct {
-        /** rx_arb_weight_value_ch0 : R/W; bitpos: [3:0]; default: 0;
+        /** rx_arb_weight_value_chn : R/W; bitpos: [3:0]; default: 0;
          *  Configures the weight(i.e the number of tokens) of RX channel0
          */
-        uint32_t rx_arb_weight_value_ch0:4;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} ahb_dma_rx_ch_arb_weight_ch0_reg_t;
-
-/** Type of rx_arb_weight_opt_dir_ch0 register
- *  RX channel 0 weight arbitration optimization enable register
- */
-typedef union {
-    struct {
-        /** rx_arb_weight_opt_dis_ch0 : R/W; bitpos: [0]; default: 0;
-         *  reserved
-         */
-        uint32_t rx_arb_weight_opt_dis_ch0:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} ahb_dma_rx_arb_weight_opt_dir_ch0_reg_t;
-
-/** Type of rx_ch_arb_weight_ch1 register
- *  RX channel 1 arbitration weight configuration register
- */
-typedef union {
-    struct {
-        /** rx_arb_weight_value_ch1 : R/W; bitpos: [3:0]; default: 0;
-         *  Configures the weight(i.e the number of tokens) of RX channel1
-         */
-        uint32_t rx_arb_weight_value_ch1:4;
+        uint32_t rx_arb_weight_value_chn:4;
         uint32_t reserved_4:28;
     };
     uint32_t val;
-} ahb_dma_rx_ch_arb_weight_ch1_reg_t;
+} ahb_dma_rx_ch_arb_weight_chn_reg_t;
 
-/** Type of rx_arb_weight_opt_dir_ch1 register
- *  RX channel 1 weight arbitration optimization enable register
+/** Type of rx_arb_weight_opt_dir_chn register
+ *  RX channel n weight arbitration optimization enable register
  */
 typedef union {
     struct {
-        /** rx_arb_weight_opt_dis_ch1 : R/W; bitpos: [0]; default: 0;
+        /** rx_arb_weight_opt_dis_chn : R/W; bitpos: [0]; default: 0;
          *  reserved
          */
-        uint32_t rx_arb_weight_opt_dis_ch1:1;
+        uint32_t rx_arb_weight_opt_dis_chn:1;
         uint32_t reserved_1:31;
     };
     uint32_t val;
-} ahb_dma_rx_arb_weight_opt_dir_ch1_reg_t;
+} ahb_dma_rx_arb_weight_opt_dir_chn_reg_t;
 
 /** Type of in_link_addr_chn register
  *  Link list descriptor address configuration of RX channel 0
@@ -1453,6 +1397,18 @@ typedef struct {
     uint32_t reserved_out[7];
 } ahb_dma_chn_reg_t;
 
+typedef struct {
+    uint32_t reserved[8];
+    ahb_dma_tx_ch_arb_weight_chn_reg_t ch_arb_weight;
+    ahb_dma_tx_arb_weight_opt_dir_chn_reg_t arb_weight_opt;
+} ahb_dma_out_crc_arb_chn_reg_t;
+
+typedef struct {
+    uint32_t reserved[8];
+    ahb_dma_rx_ch_arb_weight_chn_reg_t ch_arb_weight;
+    ahb_dma_rx_arb_weight_opt_dir_chn_reg_t arb_weight_opt;
+} ahb_dma_in_crc_arb_chn_reg_t;
+
 typedef struct {
     volatile ahb_dma_in_int_chn_reg_t in_intr[2];
     uint32_t reserved_020[4];
@@ -1463,18 +1419,10 @@ typedef struct {
     volatile ahb_dma_date_reg_t date;
     uint32_t reserved_06c;
     volatile ahb_dma_chn_reg_t channel[2];
-    uint32_t reserved_1db[59];
-    volatile ahb_dma_tx_ch_arb_weight_ch0_reg_t tx_ch_arb_weight_ch0;
-    volatile ahb_dma_tx_arb_weight_opt_dir_ch0_reg_t tx_arb_weight_opt_dir_ch0;
-    uint32_t reserved_2e4[8];
-    volatile ahb_dma_tx_ch_arb_weight_ch1_reg_t tx_ch_arb_weight_ch1;
-    volatile ahb_dma_tx_arb_weight_opt_dir_ch1_reg_t tx_arb_weight_opt_dir_ch1;
-    uint32_t reserved_30c[18];
-    volatile ahb_dma_rx_ch_arb_weight_ch0_reg_t rx_ch_arb_weight_ch0;
-    volatile ahb_dma_rx_arb_weight_opt_dir_ch0_reg_t rx_arb_weight_opt_dir_ch0;
-    uint32_t reserved_35c[8];
-    volatile ahb_dma_rx_ch_arb_weight_ch1_reg_t rx_ch_arb_weight_ch1;
-    volatile ahb_dma_rx_arb_weight_opt_dir_ch1_reg_t rx_arb_weight_opt_dir_ch1;
+    uint32_t reserved_1db[51];
+    volatile ahb_dma_out_crc_arb_chn_reg_t out_crc_arb[2];
+    uint32_t reserved_30c[10];
+    volatile ahb_dma_in_crc_arb_chn_reg_t in_crc_arb[2];
     uint32_t reserved_384[10];
     volatile ahb_dma_in_link_addr_chn_reg_t in_link_addr[2];
     uint32_t reserved_3b4;