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L-KAYAL-KAYA
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Merge branch 'feature/support_c5_eco2_soc' into 'master'
feat(soc): support esp32c5 eco2 soc See merge request espressif/esp-idf!38425
2 parents eb0d367 + 849ff88 commit 0f1fd5a

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75 files changed

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lines changed

‎components/hal/esp32c5/include/hal/assist_debug_ll.h‎

Lines changed: 16 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -9,8 +9,11 @@
99
#pragma once
1010

1111
#include "soc/assist_debug_reg.h"
12-
#define ASSIST_DEBUG_SP_SPILL_BITS (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA | ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA)
13-
#define ASSIST_DEBUG_CORE_0_MONITOR_REG ASSIST_DEBUG_CORE_0_MONTR_ENA_REG
12+
#define BUS_MONITOR_SP_SPILL_BITS (BUS_MONITOR_CORE_0_SP_SPILL_MIN_ENA | BUS_MONITOR_CORE_0_SP_SPILL_MAX_ENA)
13+
#define BUS_MONITOR_CORE_0_MONITOR_REG BUS_MONITOR_CORE_0_MONTR_ENA_REG
14+
// Compatible alias
15+
#define ASSIST_DEBUG_SP_SPILL_BITS BUS_MONITOR_SP_SPILL_BITS
16+
#define ASSIST_DEBUG_CORE_0_MONITOR_REG BUS_MONITOR_CORE_0_MONITOR_REG
1417

1518
#ifndef __ASSEMBLER__
1619

@@ -60,57 +63,57 @@ extern "C" {
6063

6164
FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_monitor_enable(__attribute__((unused)) uint32_t core_id)
6265
{
63-
REG_SET_BIT(ASSIST_DEBUG_CORE_0_MONTR_ENA_REG, ASSIST_DEBUG_SP_SPILL_BITS);
66+
REG_SET_BIT(BUS_MONITOR_CORE_0_MONTR_ENA_REG, BUS_MONITOR_SP_SPILL_BITS);
6467
}
6568

6669
FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_monitor_disable(__attribute__((unused)) uint32_t core_id)
6770
{
68-
REG_CLR_BIT(ASSIST_DEBUG_CORE_0_MONTR_ENA_REG, ASSIST_DEBUG_SP_SPILL_BITS);
71+
REG_CLR_BIT(BUS_MONITOR_CORE_0_MONTR_ENA_REG, BUS_MONITOR_SP_SPILL_BITS);
6972
}
7073

7174
FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_enable(__attribute__((unused)) uint32_t core_id)
7275
{
73-
REG_SET_BIT(ASSIST_DEBUG_CORE_0_INTR_ENA_REG, ASSIST_DEBUG_SP_SPILL_BITS);
76+
REG_SET_BIT(BUS_MONITOR_CORE_0_INTR_ENA_REG, BUS_MONITOR_SP_SPILL_BITS);
7477
}
7578

7679
FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_disable(__attribute__((unused)) uint32_t core_id)
7780
{
78-
REG_CLR_BIT(ASSIST_DEBUG_CORE_0_INTR_ENA_REG, ASSIST_DEBUG_SP_SPILL_BITS);
81+
REG_CLR_BIT(BUS_MONITOR_CORE_0_INTR_ENA_REG, BUS_MONITOR_SP_SPILL_BITS);
7982
}
8083

8184
FORCE_INLINE_ATTR bool assist_debug_ll_sp_spill_is_fired(__attribute__((unused)) uint32_t core_id)
8285
{
83-
return REG_READ(ASSIST_DEBUG_CORE_0_INTR_RAW_REG) & ASSIST_DEBUG_SP_SPILL_BITS;
86+
return REG_READ(BUS_MONITOR_CORE_0_INTR_RAW_REG) & BUS_MONITOR_SP_SPILL_BITS;
8487
}
8588

8689
FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_clear(__attribute__((unused)) uint32_t core_id)
8790
{
88-
REG_WRITE(ASSIST_DEBUG_CORE_0_INTR_CLR_REG, ASSIST_DEBUG_SP_SPILL_BITS);
91+
REG_WRITE(BUS_MONITOR_CORE_0_INTR_CLR_REG, BUS_MONITOR_SP_SPILL_BITS);
8992
}
9093

9194
FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_set_min(__attribute__((unused)) uint32_t core_id, uint32_t min)
9295
{
93-
REG_WRITE(ASSIST_DEBUG_CORE_0_SP_MIN_REG, min);
96+
REG_WRITE(BUS_MONITOR_CORE_0_SP_MIN_REG, min);
9497
}
9598

9699
FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_min(__attribute__((unused)) uint32_t core_id)
97100
{
98-
return REG_READ(ASSIST_DEBUG_CORE_0_SP_MIN_REG);
101+
return REG_READ(BUS_MONITOR_CORE_0_SP_MIN_REG);
99102
}
100103

101104
FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_set_max(__attribute__((unused)) uint32_t core_id, uint32_t max)
102105
{
103-
REG_WRITE(ASSIST_DEBUG_CORE_0_SP_MAX_REG, max);
106+
REG_WRITE(BUS_MONITOR_CORE_0_SP_MAX_REG, max);
104107
}
105108

106109
FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_max(__attribute__((unused)) uint32_t core_id)
107110
{
108-
return REG_READ(ASSIST_DEBUG_CORE_0_SP_MAX_REG);
111+
return REG_READ(BUS_MONITOR_CORE_0_SP_MAX_REG);
109112
}
110113

111114
FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_pc(__attribute__((unused)) uint32_t core_id)
112115
{
113-
return REG_READ(ASSIST_DEBUG_CORE_0_SP_PC_REG);
116+
return REG_READ(BUS_MONITOR_CORE_0_SP_PC_REG);
114117
}
115118

116119
FORCE_INLINE_ATTR void assist_debug_ll_enable_bus_clock(bool enable)

‎components/hal/esp32c5/include/hal/uart_ll.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -561,7 +561,7 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw)
561561
FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len)
562562
{
563563
for (int i = 0; i < (int)rd_len; i++) {
564-
buf[i] = hw->fifo.rxfifo_rd_byte;
564+
buf[i] = hw->fifo.val;
565565
}
566566
}
567567

‎components/hal/esp32c5/include/hal/usb_serial_jtag_ll.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -116,7 +116,7 @@ static inline int usb_serial_jtag_ll_read_rxfifo(uint8_t *buf, uint32_t rd_len)
116116
int i;
117117
for (i = 0; i < (int)rd_len; i++) {
118118
if (!USB_SERIAL_JTAG.ep1_conf.serial_out_ep_data_avail) break;
119-
buf[i] = USB_SERIAL_JTAG.ep1.rdwr_byte;
119+
buf[i] = USB_SERIAL_JTAG.ep1.val;
120120
}
121121
return i;
122122
}
@@ -135,7 +135,7 @@ static inline int usb_serial_jtag_ll_write_txfifo(const uint8_t *buf, uint32_t w
135135
int i;
136136
for (i = 0; i < (int)wr_len; i++) {
137137
if (!USB_SERIAL_JTAG.ep1_conf.serial_in_ep_data_free) break;
138-
USB_SERIAL_JTAG.ep1.rdwr_byte = buf[i];
138+
USB_SERIAL_JTAG.ep1.val = buf[i];
139139
}
140140
return i;
141141
}

‎components/soc/esp32c5/include/soc/assist_debug_reg.h‎

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,21 @@
1+
/**
2+
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
#pragma once
7+
8+
#include "soc/bus_monitor_reg.h"
9+
10+
// Compatible alias
11+
#define DR_REG_ASSIST_DEBUG_BASE DR_REG_BUS_MONITOR_BASE
12+
13+
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG BUS_MONITOR_CORE_0_DEBUG_MODE_REG
14+
#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE BUS_MONITOR_CORE_0_DEBUG_MODULE_ACTIVE
15+
16+
#define ASSIST_DEBUG_CORE_0_SP_MIN_REG BUS_MONITOR_CORE_0_SP_MIN_REG
17+
#define ASSIST_DEBUG_CORE_0_SP_MAX_REG BUS_MONITOR_CORE_0_SP_MAX_REG
18+
19+
#define ASSIST_DEBUG_CORE_0_RCD_EN_REG BUS_MONITOR_CORE_0_RCD_EN_REG
20+
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN BUS_MONITOR_CORE_0_RCD_PDEBUGEN
21+
#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN BUS_MONITOR_CORE_0_RCD_RECORDEN

‎components/soc/esp32c5/include/soc/gpio_sig_map.h‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -152,6 +152,7 @@
152152
#define PWM0_F2_IN_IDX 85
153153
#define PWM0_OUT2B_IDX 85
154154
#define PWM0_CAP0_IN_IDX 86
155+
#define PARL_TX_CS_O_IDX 86
155156
#define PWM0_CAP1_IN_IDX 87
156157
#define PWM0_CAP2_IN_IDX 88
157158
#define GPIO_EVENT_MATRIX_IN0_IDX 89
@@ -165,6 +166,7 @@
165166
#define CLK_OUT_OUT1_IDX 93
166167
#define CLK_OUT_OUT2_IDX 94
167168
#define CLK_OUT_OUT3_IDX 95
169+
#define SDIO_TOHOST_INT_OUT_IDX 96
168170
#define SIG_IN_FUNC_97_IDX 97
169171
#define SIG_IN_FUNC97_IDX 97
170172
#define SIG_IN_FUNC_98_IDX 98
@@ -242,5 +244,5 @@
242244
#define ANT_SEL13_IDX 151
243245
#define ANT_SEL14_IDX 152
244246
#define ANT_SEL15_IDX 153
245-
#define SIG_GPIO_OUT_IDX 256
246247
// version date 2311280
248+
#define SIG_GPIO_OUT_IDX 256

‎components/soc/esp32c5/include/soc/pmu_icg_mapping.h‎

Lines changed: 60 additions & 60 deletions
Original file line numberDiff line numberDiff line change
@@ -1,67 +1,67 @@
11
/*
2-
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
66

77
#pragma once
88

9-
#define PMU_ICG_APB_ENA_CAN0 18
10-
#define PMU_ICG_APB_ENA_CAN1 19
11-
#define PMU_ICG_APB_ENA_GDMA 1
12-
#define PMU_ICG_APB_ENA_I2C 13
13-
#define PMU_ICG_APB_ENA_I2S 4
14-
#define PMU_ICG_APB_ENA_INTMTX 3
15-
#define PMU_ICG_APB_ENA_IOMUX 26
16-
#define PMU_ICG_APB_ENA_LEDC 14
17-
#define PMU_ICG_APB_ENA_MEM_MONITOR 25
18-
#define PMU_ICG_APB_ENA_MSPI 5
19-
#define PMU_ICG_APB_ENA_PARL 23
20-
#define PMU_ICG_APB_ENA_PCNT 20
21-
#define PMU_ICG_APB_ENA_PVT_MONITOR 27
22-
#define PMU_ICG_APB_ENA_PWM 21
23-
#define PMU_ICG_APB_ENA_REGDMA 24
24-
#define PMU_ICG_APB_ENA_RMT 15
25-
#define PMU_ICG_APB_ENA_SARADC 9
26-
#define PMU_ICG_APB_ENA_SEC 0
27-
#define PMU_ICG_APB_ENA_SOC_ETM 22
28-
#define PMU_ICG_APB_ENA_SPI2 2
29-
#define PMU_ICG_APB_ENA_SYSTIMER 16
30-
#define PMU_ICG_APB_ENA_TG0 11
31-
#define PMU_ICG_APB_ENA_TG1 12
32-
#define PMU_ICG_APB_ENA_UART0 6
33-
#define PMU_ICG_APB_ENA_UART1 7
34-
#define PMU_ICG_APB_ENA_UHCI 8
35-
#define PMU_ICG_APB_ENA_USB_DEVICE 17
36-
#define PMU_ICG_FUNC_ENA_CAN0 31
37-
#define PMU_ICG_FUNC_ENA_CAN1 30
38-
#define PMU_ICG_FUNC_ENA_I2C 29
39-
#define PMU_ICG_FUNC_ENA_I2S_RX 2
40-
#define PMU_ICG_FUNC_ENA_I2S_TX 7
41-
#define PMU_ICG_FUNC_ENA_IOMUX 28
42-
#define PMU_ICG_FUNC_ENA_LEDC 27
43-
#define PMU_ICG_FUNC_ENA_MEM_MONITOR 10
44-
#define PMU_ICG_FUNC_ENA_MSPI 26
45-
#define PMU_ICG_FUNC_ENA_PARL_RX 25
46-
#define PMU_ICG_FUNC_ENA_PARL_TX 24
47-
#define PMU_ICG_FUNC_ENA_PVT_MONITOR 23
48-
#define PMU_ICG_FUNC_ENA_PWM 22
49-
#define PMU_ICG_FUNC_ENA_RMT 21
50-
#define PMU_ICG_FUNC_ENA_SARADC 20
51-
#define PMU_ICG_FUNC_ENA_SEC 19
52-
#define PMU_ICG_FUNC_ENA_SPI2 1
53-
#define PMU_ICG_FUNC_ENA_SYSTIMER 18
54-
#define PMU_ICG_FUNC_ENA_TG0 14
55-
#define PMU_ICG_FUNC_ENA_TG1 13
56-
#define PMU_ICG_FUNC_ENA_TSENS 12
57-
#define PMU_ICG_FUNC_ENA_UART0 3
58-
#define PMU_ICG_FUNC_ENA_UART1 4
59-
#define PMU_ICG_FUNC_ENA_USB_DEVICE 6
60-
#define PMU_ICG_FUNC_ENA_GDMA 0
61-
#define PMU_ICG_FUNC_ENA_SOC_ETM 16
62-
#define PMU_ICG_FUNC_ENA_REGDMA 8
63-
#define PMU_ICG_FUNC_ENA_RETENTION 9
64-
#define PMU_ICG_FUNC_ENA_SDIO_SLAVE 11
65-
#define PMU_ICG_FUNC_ENA_UHCI 5
66-
#define PMU_ICG_FUNC_ENA_HPCORE 17
67-
#define PMU_ICG_FUNC_ENA_HPBUS 15
9+
#define PMU_ICG_APB_ENA_SEC 0
10+
#define PMU_ICG_APB_ENA_GDMA 1
11+
#define PMU_ICG_APB_ENA_SPI2 2
12+
#define PMU_ICG_APB_ENA_INTMTX 3
13+
#define PMU_ICG_APB_ENA_I2S 4
14+
#define PMU_ICG_APB_ENA_MSPI 5
15+
#define PMU_ICG_APB_ENA_UART0 6
16+
#define PMU_ICG_APB_ENA_UART1 7
17+
#define PMU_ICG_APB_ENA_UHCI 8
18+
#define PMU_ICG_APB_ENA_SARADC 9
19+
#define PMU_ICG_APB_ENA_TG0 11
20+
#define PMU_ICG_APB_ENA_TG1 12
21+
#define PMU_ICG_APB_ENA_I2C 13
22+
#define PMU_ICG_APB_ENA_LEDC 14
23+
#define PMU_ICG_APB_ENA_RMT 15
24+
#define PMU_ICG_APB_ENA_SYSTIMER 16
25+
#define PMU_ICG_APB_ENA_USB_DEVICE 17
26+
#define PMU_ICG_APB_ENA_TWAI0 18
27+
#define PMU_ICG_APB_ENA_TWAI1 19
28+
#define PMU_ICG_APB_ENA_PCNT 20
29+
#define PMU_ICG_APB_ENA_PWM 21
30+
#define PMU_ICG_APB_ENA_SOC_ETM 22
31+
#define PMU_ICG_APB_ENA_PARL 23
32+
#define PMU_ICG_APB_ENA_REGDMA 24
33+
#define PMU_ICG_APB_ENA_MEM_MONITOR 25
34+
#define PMU_ICG_APB_ENA_IOMUX 26
35+
#define PMU_ICG_APB_ENA_PVT_MONITOR 27
36+
#define PMU_ICG_FUNC_ENA_GDMA 0
37+
#define PMU_ICG_FUNC_ENA_SPI2 1
38+
#define PMU_ICG_FUNC_ENA_I2S_RX 2
39+
#define PMU_ICG_FUNC_ENA_UART0 3
40+
#define PMU_ICG_FUNC_ENA_UART1 4
41+
#define PMU_ICG_FUNC_ENA_UHCI 5
42+
#define PMU_ICG_FUNC_ENA_USB_DEVICE 6
43+
#define PMU_ICG_FUNC_ENA_I2S_TX 7
44+
#define PMU_ICG_FUNC_ENA_REGDMA 8
45+
#define PMU_ICG_FUNC_ENA_RETENTION 9
46+
#define PMU_ICG_FUNC_ENA_MEM_MONITOR 10
47+
#define PMU_ICG_FUNC_ENA_SDIO_SLAVE 11
48+
#define PMU_ICG_FUNC_ENA_TSENS 12
49+
#define PMU_ICG_FUNC_ENA_TG1 13
50+
#define PMU_ICG_FUNC_ENA_TG0 14
51+
#define PMU_ICG_FUNC_ENA_HPBUS 15
52+
#define PMU_ICG_FUNC_ENA_SOC_ETM 16
53+
#define PMU_ICG_FUNC_ENA_HPCORE 17
54+
#define PMU_ICG_FUNC_ENA_SYSTIMER 18
55+
#define PMU_ICG_FUNC_ENA_SEC 19
56+
#define PMU_ICG_FUNC_ENA_SARADC 20
57+
#define PMU_ICG_FUNC_ENA_RMT 21
58+
#define PMU_ICG_FUNC_ENA_PWM 22
59+
#define PMU_ICG_FUNC_ENA_PVT_MONITOR 23
60+
#define PMU_ICG_FUNC_ENA_PARL_TX 24
61+
#define PMU_ICG_FUNC_ENA_PARL_RX 25
62+
#define PMU_ICG_FUNC_ENA_MSPI 26
63+
#define PMU_ICG_FUNC_ENA_LEDC 27
64+
#define PMU_ICG_FUNC_ENA_IOMUX 28
65+
#define PMU_ICG_FUNC_ENA_I2C 29
66+
#define PMU_ICG_FUNC_ENA_TWAI1 30
67+
#define PMU_ICG_FUNC_ENA_TWAI0 31

‎components/soc/esp32c5/ld/esp32c5.peripherals.ld‎

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -27,6 +27,9 @@ PROVIDE ( PCNT = 0x60012000 );
2727
PROVIDE ( SOC_ETM = 0x60013000 );
2828
PROVIDE ( MCPWM0 = 0x60014000 );
2929
PROVIDE ( PARL_IO = 0x60015000 );
30+
PROVIDE ( HINF = 0x60016000 );
31+
PROVIDE ( SLC = 0x60017000 );
32+
PROVIDE ( HOST = 0x60018000 );
3033
PROVIDE ( PVT_MONITOR = 0x60019000 );
3134
PROVIDE ( PSRAM_MEM_MONITOR = 0x6001A000 );
3235
PROVIDE ( AHB_DMA = 0x60080000 );
@@ -53,6 +56,7 @@ PROVIDE ( PCR = 0x60096000 );
5356
PROVIDE ( TEE = 0x60098000 );
5457
PROVIDE ( HP_APM = 0x60099000 );
5558
PROVIDE ( LP_APM0 = 0x60099800 );
59+
PROVIDE ( CPU_APM = 0x6009A000 );
5660
PROVIDE ( MISC = 0x6009F000 );
5761

5862
PROVIDE ( IEEE802154 = 0x600A3000 ); /* TODO: [ESP32C5] IDF-9140 Check the address */
@@ -82,6 +86,6 @@ PROVIDE ( LP_GPIO = 0x600B4400 );
8286
PROVIDE ( EFUSE = 0x600B4800 );
8387
PROVIDE ( OTP_DEBUG = 0x600B4D00 );
8488
PROVIDE ( TRACE = 0x600C0000 );
85-
PROVIDE ( ASSIST_DEBUG = 0x600C2000 );
89+
PROVIDE ( BUS_MONITOR = 0x600C2000 );
8690
PROVIDE ( INTPRI = 0x600C5000 );
8791
PROVIDE ( CACHE = 0x600C8000 );

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