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feat(mmu): use cache freeze for mmap apis
1 parent a3cf646 commit 10d4e71

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9 files changed

+246
-54
lines changed

9 files changed

+246
-54
lines changed

components/esp_mm/CMakeLists.txt

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -14,14 +14,15 @@ set(srcs)
1414
if(NOT CONFIG_APP_BUILD_TYPE_PURE_RAM_APP)
1515
set(srcs "esp_mmu_map.c"
1616
"port/${target}/ext_mem_layout.c"
17-
"esp_cache.c")
17+
"esp_cache_msync.c"
18+
"esp_cache_utils.c")
1819

1920
if(CONFIG_IDF_TARGET_ESP32)
2021
list(APPEND srcs "cache_esp32.c")
2122
endif()
2223
else()
2324
if(CONFIG_SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE)
24-
list(APPEND srcs "esp_cache.c")
25+
list(APPEND srcs "esp_cache_msync.c")
2526
endif()
2627
endif()
2728

components/esp_mm/esp_cache.c renamed to components/esp_mm/esp_cache_msync.c

Lines changed: 0 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -147,42 +147,6 @@ esp_err_t esp_cache_msync(void *addr, size_t size, int flags)
147147
return ESP_OK;
148148
}
149149

150-
void esp_cache_suspend_ext_mem_cache(void)
151-
{
152-
#if (CONFIG_SPIRAM && SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE)
153-
/**
154-
* before suspending the external mem cache, writeback internal mem cache content back to external mem cache
155-
* to avoid stuck issue caused by internal mem cache auto-writeback
156-
*/
157-
cache_ll_writeback_all(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA, CACHE_LL_ID_ALL);
158-
#endif
159-
cache_hal_suspend(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
160-
}
161-
162-
void esp_cache_resume_ext_mem_cache(void)
163-
{
164-
cache_hal_resume(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
165-
}
166-
167-
#if SOC_CACHE_FREEZE_SUPPORTED
168-
void esp_cache_freeze_ext_mem_cache(void)
169-
{
170-
#if (CONFIG_SPIRAM && SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE)
171-
/**
172-
* before freezing the external mem cache, writeback internal mem cache content back to external mem cache
173-
* to avoid stuck issue caused by internal mem cache auto-writeback
174-
*/
175-
cache_ll_writeback_all(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA, CACHE_LL_ID_ALL);
176-
#endif
177-
cache_hal_freeze(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
178-
}
179-
180-
void esp_cache_unfreeze_ext_mem_cache(void)
181-
{
182-
cache_hal_unfreeze(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
183-
}
184-
#endif //#if SOC_CACHE_FREEZE_SUPPORTED
185-
186150
//The esp_cache_aligned_malloc function is marked deprecated but also called by other
187151
//(also deprecated) functions in this file. In order to work around that generating warnings, it's
188152
//split into a non-deprecated internal function and the stubbed external deprecated function.
Lines changed: 114 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,114 @@
1+
/*
2+
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
#include <sys/param.h>
8+
#include <inttypes.h>
9+
#include <string.h>
10+
#include "sys/lock.h"
11+
#include "sdkconfig.h"
12+
#include "esp_check.h"
13+
#include "esp_log.h"
14+
#include "freertos/FreeRTOS.h"
15+
#include "esp_memory_utils.h"
16+
#include "soc/soc_caps.h"
17+
#include "hal/cache_hal.h"
18+
#include "hal/cache_ll.h"
19+
#include "esp_private/esp_cache_private.h"
20+
#include "esp_private/critical_section.h"
21+
#if __riscv
22+
#include "riscv/rv_utils.h"
23+
#endif
24+
25+
#define ALIGN_UP_BY(num, align) (((num) + ((align) - 1)) & ~((align) - 1))
26+
27+
void esp_cache_suspend_ext_mem_cache(void)
28+
{
29+
#if (CONFIG_SPIRAM && SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE)
30+
/**
31+
* before suspending the external mem cache, writeback internal mem cache content back to external mem cache
32+
* to avoid stuck issue caused by internal mem cache auto-writeback
33+
*/
34+
cache_ll_writeback_all(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA, CACHE_LL_ID_ALL);
35+
#endif
36+
cache_hal_suspend(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
37+
}
38+
39+
void esp_cache_resume_ext_mem_cache(void)
40+
{
41+
cache_hal_resume(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
42+
}
43+
44+
/*-----------------------------------------------------------------------------
45+
* Cache Freeze Related
46+
*----------------------------------------------------------------------------*/
47+
#if SOC_CACHE_FREEZE_SUPPORTED
48+
DEFINE_CRIT_SECTION_LOCK_STATIC(s_spinlock);
49+
50+
void esp_cache_freeze_ext_mem_cache(void)
51+
{
52+
#if (CONFIG_SPIRAM && SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE)
53+
#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
54+
int cpuid = xPortGetCoreID();
55+
uint32_t other_cpuid = (cpuid == 0) ? 1 : 0;
56+
esp_cpu_stall(other_cpuid);
57+
#else
58+
//single core mode, don't need to stall other core
59+
#endif
60+
/**
61+
* before freezing the external mem cache, writeback internal mem cache content back to external mem cache
62+
* to avoid stuck issue caused by internal mem cache auto-writeback
63+
*/
64+
cache_ll_writeback_all(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA, CACHE_LL_ID_ALL);
65+
#endif
66+
67+
cache_hal_freeze(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
68+
69+
#if (CONFIG_SPIRAM && SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE)
70+
#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
71+
esp_cpu_unstall(other_cpuid);
72+
#else
73+
//single core mode, don't need to unstall other core
74+
#endif
75+
#endif
76+
}
77+
78+
void esp_cache_unfreeze_ext_mem_cache(void)
79+
{
80+
cache_hal_unfreeze(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
81+
}
82+
83+
static inline bool s_task_stack_is_sane_when_cache_frozen(void)
84+
{
85+
const void *sp = (const void *)esp_cpu_get_sp();
86+
87+
return esp_ptr_in_dram(sp)
88+
#if CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
89+
|| esp_ptr_in_rtc_dram_fast(sp)
90+
#endif
91+
;
92+
}
93+
94+
void esp_cache_freeze_caches_disable_interrupts(void)
95+
{
96+
assert(s_task_stack_is_sane_when_cache_frozen());
97+
esp_os_enter_critical_safe(&s_spinlock);
98+
99+
/**
100+
* - disable non-iram interrupt on current core
101+
* - current core call cache freeze
102+
* - external access from other cores will hang on cache
103+
*/
104+
esp_intr_noniram_disable();
105+
esp_cache_freeze_ext_mem_cache();
106+
}
107+
108+
void esp_cache_unfreeze_caches_enable_interrupts(void)
109+
{
110+
esp_cache_unfreeze_ext_mem_cache();
111+
esp_intr_noniram_enable();
112+
esp_os_exit_critical_safe(&s_spinlock);
113+
}
114+
#endif

components/esp_mm/esp_mmu_map.c

Lines changed: 41 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,7 @@
2727

2828
#include "esp_private/cache_utils.h"
2929
#include "esp_private/esp_cache_esp32_private.h"
30+
#include "esp_private/esp_cache_private.h"
3031
#include "esp_private/esp_mmu_map_private.h"
3132
#include "ext_mem_layout.h"
3233
#include "esp_mmu_map.h"
@@ -373,6 +374,26 @@ IRAM_ATTR esp_err_t esp_mmu_paddr_find_caps(const esp_paddr_t paddr, mmu_mem_cap
373374
return ESP_OK;
374375
}
375376

377+
static void IRAM_ATTR NOINLINE_ATTR s_stop_cache(void)
378+
{
379+
#if SOC_CACHE_FREEZE_SUPPORTED && !CONFIG_IDF_TARGET_ESP32P4
380+
// On P4, due to limitations on stalling another core, we temporarily use cache disable/enable
381+
esp_cache_freeze_caches_disable_interrupts();
382+
#else
383+
spi_flash_disable_interrupts_caches_and_other_cpu();
384+
#endif
385+
}
386+
387+
static void IRAM_ATTR NOINLINE_ATTR s_start_cache(void)
388+
{
389+
#if SOC_CACHE_FREEZE_SUPPORTED && !CONFIG_IDF_TARGET_ESP32P4
390+
// On P4, due to limitations on stalling another core, we temporarily use cache disable/enable
391+
esp_cache_unfreeze_caches_enable_interrupts();
392+
#else
393+
spi_flash_enable_interrupts_caches_and_other_cpu();
394+
#endif
395+
}
396+
376397
static void IRAM_ATTR NOINLINE_ATTR s_do_cache_invalidate(uint32_t vaddr_start, uint32_t size)
377398
{
378399
#if CONFIG_IDF_TARGET_ESP32
@@ -416,10 +437,8 @@ static void IRAM_ATTR NOINLINE_ATTR s_do_mapping(mmu_target_t target, uint32_t v
416437
{
417438
/**
418439
* Disable Cache, after this function, involved code and data should be placed in internal RAM.
419-
*
420-
* @note we call this for now, but this will be refactored to move out of `spi_flash`
421440
*/
422-
spi_flash_disable_interrupts_caches_and_other_cpu();
441+
s_stop_cache();
423442

424443
uint32_t actual_mapped_len = s_mapping_operation(target, vaddr_start, paddr_start, size);
425444

@@ -433,7 +452,7 @@ static void IRAM_ATTR NOINLINE_ATTR s_do_mapping(mmu_target_t target, uint32_t v
433452
s_do_cache_invalidate(vaddr_start, size);
434453

435454
//enable Cache, after this function, internal RAM access is no longer mandatory
436-
spi_flash_enable_interrupts_caches_and_other_cpu();
455+
s_start_cache();
437456

438457
ESP_EARLY_LOGV(TAG, "actual_mapped_len is 0x%"PRIx32, actual_mapped_len);
439458
}
@@ -613,15 +632,13 @@ static void IRAM_ATTR NOINLINE_ATTR s_do_unmapping(uint32_t vaddr_start, uint32_
613632
{
614633
/**
615634
* Disable Cache, after this function, involved code and data should be placed in internal RAM.
616-
*
617-
* @note we call this for now, but this will be refactored to move out of `spi_flash`
618635
*/
619-
spi_flash_disable_interrupts_caches_and_other_cpu();
636+
s_stop_cache();
620637

621638
s_unmapping_operation(vaddr_start, size);
622639

623640
//enable Cache, after this function, internal RAM access is no longer mandatory
624-
spi_flash_enable_interrupts_caches_and_other_cpu();
641+
s_start_cache();
625642
}
626643

627644
esp_err_t esp_mmu_unmap(void *ptr)
@@ -759,8 +776,11 @@ esp_err_t IRAM_ATTR esp_mmu_map_dump_mapped_blocks_private(void)
759776
static bool NOINLINE_ATTR IRAM_ATTR s_vaddr_to_paddr(uint32_t vaddr, esp_paddr_t *out_paddr, mmu_target_t *out_target)
760777
{
761778
uint32_t mmu_id = 0;
762-
//we call this for now, but this will be refactored to move out of `spi_flash`
763-
spi_flash_disable_interrupts_caches_and_other_cpu();
779+
/**
780+
* Disable Cache, after this function, involved code and data should be placed in internal RAM.
781+
*/
782+
s_stop_cache();
783+
764784
#if SOC_MMU_PER_EXT_MEM_TARGET
765785
mmu_id = mmu_hal_get_id_from_vaddr(vaddr);
766786
#endif
@@ -770,7 +790,9 @@ static bool NOINLINE_ATTR IRAM_ATTR s_vaddr_to_paddr(uint32_t vaddr, esp_paddr_t
770790
is_mapped = mmu_hal_vaddr_to_paddr(1, vaddr, out_paddr, out_target);
771791
}
772792
#endif
773-
spi_flash_enable_interrupts_caches_and_other_cpu();
793+
794+
//enable Cache, after this function, internal RAM access is no longer mandatory
795+
s_start_cache();
774796

775797
return is_mapped;
776798
}
@@ -794,14 +816,19 @@ esp_err_t esp_mmu_vaddr_to_paddr(void *vaddr, esp_paddr_t *out_paddr, mmu_target
794816

795817
static bool NOINLINE_ATTR IRAM_ATTR s_paddr_to_vaddr(esp_paddr_t paddr, mmu_target_t target, mmu_vaddr_t type, uint32_t *out_vaddr)
796818
{
797-
//we call this for now, but this will be refactored to move out of `spi_flash`
798-
spi_flash_disable_interrupts_caches_and_other_cpu();
819+
/**
820+
* Disable Cache, after this function, involved code and data should be placed in internal RAM.
821+
*/
822+
s_stop_cache();
823+
799824
uint32_t mmu_id = 0;
800825
#if SOC_MMU_PER_EXT_MEM_TARGET
801826
mmu_id = mmu_hal_get_id_from_target(target);
802827
#endif
803828
bool found = mmu_hal_paddr_to_vaddr(mmu_id, paddr, target, type, out_vaddr);
804-
spi_flash_enable_interrupts_caches_and_other_cpu();
829+
830+
//enable Cache, after this function, internal RAM access is no longer mandatory
831+
s_start_cache();
805832

806833
return found;
807834
}

components/esp_mm/include/esp_private/esp_cache_private.h

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -53,6 +53,18 @@ void esp_cache_freeze_ext_mem_cache(void);
5353
* @note This API must be called after a `esp_cache_freeze_ext_mem_cache`
5454
*/
5555
void esp_cache_unfreeze_ext_mem_cache(void);
56+
57+
/**
58+
* @brief Freeze external memory cache and disable non-iram interrupts
59+
*
60+
* @note This API will enter a critical section, you will need to call `esp_cache_unfreeze_caches_enable_interrupts` to exit it.
61+
*/
62+
void esp_cache_freeze_caches_disable_interrupts(void);
63+
64+
/**
65+
* @brief Unfreeze external memory cache and re-enable non-iram interrupts
66+
*/
67+
void esp_cache_unfreeze_caches_enable_interrupts(void);
5668
#endif
5769

5870
/**

components/esp_mm/linker.lf

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,8 @@ archive: libesp_mm.a
33
entries:
44

55
if APP_BUILD_TYPE_PURE_RAM_APP = n:
6-
esp_cache (noflash)
6+
esp_cache_msync (noflash)
7+
esp_cache_utils (noflash)
78

89
if IDF_TARGET_ESP32 = y:
910
cache_esp32 (noflash)

components/esp_mm/test_apps/mm/main/CMakeLists.txt

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,9 +6,12 @@ if(CONFIG_SOC_CACHE_WRITEBACK_SUPPORTED)
66
list(APPEND srcs "test_cache_msync.c")
77
endif()
88

9+
if(CONFIG_SOC_CACHE_FREEZE_SUPPORTED)
10+
list(APPEND srcs "test_cache_utils.c")
11+
endif()
912

1013
# In order for the cases defined by `TEST_CASE` to be linked into the final elf,
1114
# the component can be registered as WHOLE_ARCHIVE
1215
idf_component_register(SRCS ${srcs}
13-
PRIV_REQUIRES unity esp_partition spi_flash esp_mm driver esp_timer test_mm_utils
16+
PRIV_REQUIRES unity esp_partition spi_flash esp_mm driver esp_timer test_mm_utils test_utils
1417
WHOLE_ARCHIVE)
Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,3 @@
1+
dependencies:
2+
test_utils:
3+
path: ${IDF_PATH}/tools/unit-test-app/components/test_utils

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