Merge branch 'refactor/mspi_clk_src_refactor' into 'master'

mspi: clk src refactor

Closes IDF-10464

See merge request espressif/esp-idf!35365

Author: Icarus113

components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c

@@ -53,7 +53,7 @@ void IRAM_ATTR bootloader_init_mspi_clock(void)
     // Set source mspi pll clock as 80M in bootloader stage.
     // SPLL clock on C5 is 480MHz , and mspi_pll needs 80MHz
     // in this stage, set divider as 6
-    mspi_ll_clock_src_sel(MSPI_CLK_SRC_SPLL);
+    _mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_SPLL);
     mspi_ll_fast_set_hs_divider(6);
 }
 

components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c

@@ -51,7 +51,7 @@ void IRAM_ATTR bootloader_init_mspi_clock(void)
     // Set source mspi pll clock as 80M in bootloader stage.
     // SPLL clock on C61 is 480MHz , and mspi_pll needs 80MHz
     // in this stage, set divider as 6
-    mspi_ll_clock_src_sel(MSPI_CLK_SRC_SPLL);
+    _mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_DEFAULT);
     mspi_ll_fast_set_hs_divider(6);
 }
 

components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c

@@ -19,7 +19,7 @@
 #include "bootloader_init.h"
 #include "hal/mmu_hal.h"
 #include "hal/mmu_ll.h"
-#include "hal/spimem_flash_ll.h"
+#include "hal/mspi_timing_tuning_ll.h"
 #include "hal/cache_hal.h"
 #include "hal/cache_ll.h"
 #include "esp_private/bootloader_flash_internal.h"
@@ -44,8 +44,8 @@ void IRAM_ATTR bootloader_flash_cs_timing_config(void)
 
 void IRAM_ATTR bootloader_init_mspi_clock(void)
 {
-    _spimem_flash_ll_select_clk_source(0, FLASH_CLK_SRC_SPLL);
-    _spimem_ctrlr_ll_set_core_clock(0, 6);
+    _mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_SPLL);
+    _mspi_timing_ll_set_flash_core_clock(0, 80);
 }
 
 void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr)

components/esp_hw_support/mspi_timing_tuning/mspi_timing_tuning.c

@@ -16,23 +16,19 @@
 #include "hal/spi_flash_hal.h"
 #include "hal/cache_hal.h"
 #include "hal/cache_ll.h"
+#include "hal/mspi_timing_tuning_ll.h"
 #include "esp_private/mspi_timing_tuning.h"
 #include "esp_private/mspi_timing_config.h"
 #include "mspi_timing_by_mspi_delay.h"
 #include "mspi_timing_by_dqs.h"
 #include "mspi_timing_by_flash_delay.h"
 #if SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY || SOC_MEMSPI_TIMING_TUNING_BY_DQS || SOC_MEMSPI_TIMING_TUNING_BY_FLASH_DELAY
 #include "mspi_timing_tuning_configs.h"
-#include "hal/mspi_timing_tuning_ll.h"
 #endif
 #if SOC_MEMSPI_CLK_SRC_IS_INDEPENDENT
 #include "hal/spimem_flash_ll.h"
 #endif
 
-#if CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61 // TODO: IDF-10464
-#include "hal/mspi_timing_tuning_ll.h"
-#endif
-
 #if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
 #include "esp_ipc_isr.h"
 #endif
@@ -469,13 +465,9 @@ void mspi_timing_psram_tuning(void)
  *----------------------------------------------------------------------------*/
 void mspi_timing_enter_low_speed_mode(bool control_spi1)
 {
-#if SOC_MEMSPI_FLASH_CLK_SRC_IS_INDEPENDENT
-#if CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61 // TODO: IDF-10464
-    mspi_ll_clock_src_sel(MSPI_CLK_SRC_XTAL);
-#else
-    spimem_flash_ll_set_clock_source(MSPI_CLK_SRC_ROM_DEFAULT);
+#if MSPI_TIMING_LL_FLASH_CLK_SRC_CHANGEABLE
+    _mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_ROM_DEFAULT);
 #endif
-#endif  //SOC_MEMSPI_FLASH_CLK_SRC_IS_INDEPENDENT
 
 #if SOC_SPI_MEM_SUPPORT_TIMING_TUNING
     /**
@@ -509,13 +501,9 @@ void mspi_timing_enter_low_speed_mode(bool control_spi1)
  */
 void mspi_timing_enter_high_speed_mode(bool control_spi1)
 {
-#if SOC_MEMSPI_FLASH_CLK_SRC_IS_INDEPENDENT
-#if CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61// TODO: IDF-10464
-    mspi_ll_clock_src_sel(MSPI_CLK_SRC_SPLL);
-#else
-    spimem_flash_ll_set_clock_source(MSPI_CLK_SRC_DEFAULT);
+#if MSPI_TIMING_LL_FLASH_CLK_SRC_CHANGEABLE
+    _mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_DEFAULT);
 #endif
-#endif  //SOC_MEMSPI_FLASH_CLK_SRC_IS_INDEPENDENT
 
 #if SOC_SPI_MEM_SUPPORT_TIMING_TUNING
     /**

components/esp_hw_support/mspi_timing_tuning/port/esp32p4/mspi_timing_config.c

@@ -40,7 +40,7 @@ void mspi_timing_config_set_flash_clock(uint32_t flash_freq_mhz, mspi_timing_spe
 #if MSPI_TIMING_FLASH_NEEDS_TUNING
     assert(HP_SYS_CLKRST.peri_clk_ctrl00.reg_flash_clk_src_sel == 1);
 
-    uint32_t core_clock_mhz = MSPI_TIMING_SPLL_FREQ_MHZ / MSPI_TIMING_LL_FLASH_CORE_CLK_DIV;
+    uint32_t core_clock_mhz = MSPI_TIMING_SPLL_FREQ_MHZ / MSPI_TIMING_LL_HP_FLASH_CORE_CLK_DIV;
     assert(core_clock_mhz == 120);
     uint32_t freqdiv = core_clock_mhz / flash_freq_mhz;
 

components/hal/esp32/include/hal/mspi_timing_tuning_ll.h

@@ -0,0 +1,7 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//For compatibility

components/hal/esp32c2/include/hal/mspi_timing_tuning_ll.h

@@ -0,0 +1,7 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//For compatibility

components/hal/esp32c3/include/hal/mspi_timing_tuning_ll.h

@@ -0,0 +1,7 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//For compatibility

components/hal/esp32c5/include/hal/mspi_timing_tuning_ll.h

@@ -21,21 +21,24 @@ extern "C" {
 
 /************************** MSPI pll clock configurations **************************/
 
-/**
- * @brief Select mspi clock source
+/*
+ * @brief Select FLASH clock source
  *
- * @param clk_src the clock source of mspi clock
+ * @param mspi_id      mspi_id
+ * @param clk_src      clock source, see valid sources in type `soc_periph_flash_clk_src_t`
  */
-static inline __attribute__((always_inline)) void mspi_ll_clock_src_sel(soc_periph_mspi_clk_src_t clk_src)
+__attribute__((always_inline))
+static inline void _mspi_timing_ll_set_flash_clk_src(uint32_t mspi_id, soc_periph_flash_clk_src_t clk_src)
 {
+    HAL_ASSERT(mspi_id == 0);
     switch (clk_src) {
-    case MSPI_CLK_SRC_XTAL:
+    case FLASH_CLK_SRC_XTAL:
         PCR.mspi_clk_conf.mspi_func_clk_sel = 0;
         break;
-    case MSPI_CLK_SRC_RC_FAST:
+    case FLASH_CLK_SRC_RC_FAST:
         PCR.mspi_clk_conf.mspi_func_clk_sel = 1;
         break;
-    case MSPI_CLK_SRC_SPLL:
+    case FLASH_CLK_SRC_SPLL:
         PCR.mspi_clk_conf.mspi_func_clk_sel = 2;
         break;
     default:

components/hal/esp32c6/include/hal/mspi_timing_tuning_ll.h

@@ -0,0 +1,7 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//For compatibility