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Merge branch 'feat/esp32c61_wifi_sleep' into 'master'
esp32c61 wifi legacy sleep and modem state support Closes PM-206, PM-234, IDF-10627, and IDF-10630 See merge request espressif/esp-idf!33711
2 parents 816013f + 9f030d1 commit 1635905

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13 files changed

+162
-25
lines changed

13 files changed

+162
-25
lines changed

‎components/esp_hw_support/lowpower/port/esp32c61/sleep_clock.c‎

Lines changed: 17 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -13,19 +13,31 @@ static const char *TAG = "sleep_clock";
1313
esp_err_t sleep_clock_system_retention_init(void *arg)
1414
{
1515
const static sleep_retention_entries_config_t pcr_regs_retention[] = {
16-
[0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(0), DR_REG_PCR_BASE, DR_REG_PCR_BASE, 63, 0, 0, 0xfd73ffff, 0xfdffffff, 0xe001, 0x0), .owner = ENTRY(0) | ENTRY(1) },
16+
[0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(0), PCR_AHB_FREQ_CONF_REG, 0, PCR_AHB_DIV_NUM, 1, 0), .owner = ENTRY(0) | ENTRY(1) }, /* Set AHB bus frequency to XTAL frequency */
17+
[1] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(1), PCR_BUS_CLK_UPDATE_REG, 1, PCR_BUS_CLOCK_UPDATE, 1, 0), .owner = ENTRY(0) | ENTRY(1) },
18+
#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
19+
[2] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(2), DR_REG_PCR_BASE, DR_REG_PCR_BASE, 63, 0, 0, 0xfd73ffff, 0xfdffffff, 0xe001, 0x0), .owner = ENTRY(0) | ENTRY(1) }
20+
#endif
1721
};
1822

1923
esp_err_t err = sleep_retention_entries_create(pcr_regs_retention, ARRAY_SIZE(pcr_regs_retention), REGDMA_LINK_PRI_SYS_CLK, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
2024
ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for system (PCR) retention");
25+
26+
const static sleep_retention_entries_config_t modem_ahb_config[] = {
27+
[0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(3), PCR_AHB_FREQ_CONF_REG, 3, PCR_AHB_DIV_NUM, 1, 0), .owner = ENTRY(1) }, /* Set AHB bus frequency to 40 MHz under PMU MODEM state */
28+
[1] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(4), PCR_BUS_CLK_UPDATE_REG, 1, PCR_BUS_CLOCK_UPDATE, 1, 0), .owner = ENTRY(1) },
29+
};
30+
err = sleep_retention_entries_create(modem_ahb_config, ARRAY_SIZE(modem_ahb_config), REGDMA_LINK_PRI_4, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
31+
ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for system (PCR) retention, 4 level priority");
32+
2133
ESP_LOGI(TAG, "System Power, Clock and Reset sleep retention initialization");
2234
return ESP_OK;
2335
}
2436

2537
#if CONFIG_MAC_BB_PD || CONFIG_BT_LE_SLEEP_ENABLE || CONFIG_IEEE802154_SLEEP_ENABLE
2638
esp_err_t sleep_clock_modem_retention_init(void *arg)
2739
{
28-
#define N_REGS_SYSCON() (((MODEM_SYSCON_MEM_CONF_REG - MODEM_SYSCON_TEST_CONF_REG) / 4) + 1)
40+
#define N_REGS_SYSCON() (((MODEM_SYSCON_MEM_RF2_CONF_REG - MODEM_SYSCON_TEST_CONF_REG) / 4) + 1)
2941

3042
const static sleep_retention_entries_config_t modem_regs_retention[] = {
3143
[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEMSYSCON_LINK(0), MODEM_SYSCON_TEST_CONF_REG, MODEM_SYSCON_TEST_CONF_REG, N_REGS_SYSCON(), 0, 0), .owner = ENTRY(0) | ENTRY(1) }, /* MODEM SYSCON */
@@ -35,6 +47,8 @@ esp_err_t sleep_clock_modem_retention_init(void *arg)
3547
ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for modem (SYSCON) retention, 1 level priority");
3648
ESP_LOGI(TAG, "Modem Power, Clock and Reset sleep retention initialization");
3749
return ESP_OK;
50+
51+
#undef N_REGS_SYSCON
3852
}
3953
#endif
4054

@@ -83,6 +97,7 @@ ESP_SYSTEM_INIT_FN(sleep_clock_startup_init, SECONDARY, BIT(0), 106)
8397
#if CONFIG_MAC_BB_PD || CONFIG_BT_LE_SLEEP_ENABLE || CONFIG_IEEE802154_SLEEP_ENABLE
8498
init_param = (sleep_retention_module_init_param_t) {
8599
.cbs = { .create = { .handle = sleep_clock_modem_retention_init, .arg = NULL } },
100+
.depends = BIT(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM),
86101
.attribute = SLEEP_RETENTION_MODULE_ATTR_PASSIVE
87102
};
88103
sleep_retention_module_init(SLEEP_RETENTION_MODULE_CLOCK_MODEM, &init_param);

‎components/esp_hw_support/lowpower/port/esp32c61/sleep_modem_state.c‎

Lines changed: 118 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,118 @@
1+
/*
2+
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
#include "soc/soc_caps.h"
7+
#include "soc/i2c_ana_mst_reg.h"
8+
#include "soc/pmu_reg.h"
9+
10+
#include "modem/modem_syscon_reg.h"
11+
#include "modem/modem_lpcon_reg.h"
12+
13+
#include "esp_private/esp_pau.h"
14+
#include "esp_private/sleep_modem.h"
15+
#include "esp_private/sleep_retention.h"
16+
17+
#if SOC_PM_SUPPORT_PMU_MODEM_STATE
18+
19+
#define SARADC_TSENS_REG (0x6000e058)
20+
#define SARADC_TSENS_PU (BIT(22))
21+
#define PMU_RF_PWR_REG (0x600b0158)
22+
23+
#define FECOEX_SET_FREQ_SET_CHAN_REG (0x600a001c)
24+
#define FECOEX_SET_CHAN_EN (BIT(17))
25+
#define FECOEX_SET_FREQ_SET_CHAN_ST_REG (0x600a0028)
26+
#define FECOEX_SET_CHAN_DONE (BIT(8))
27+
#define FECOEX_AGC_CONF_REG (0x600a7030)
28+
#define FECOEX_AGC_DIS (BIT(29))
29+
30+
#define WDEVTXQ_BLOCK (0x600a4ca8)
31+
#define WDEV_RXBLOCK (BIT(12))
32+
33+
esp_err_t sleep_modem_state_phy_link_init(void **link_head)
34+
{
35+
esp_err_t err = ESP_OK;
36+
37+
#if SOC_PM_PAU_REGDMA_LINK_WIFIMAC
38+
static regdma_link_config_t wifi_modem_config[] = {
39+
[0] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x00), MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN, MODEM_LPCON_CLK_I2C_MST_EN_M, 1, 0), /* I2C MST enable */
40+
41+
/* PMU or software to trigger enable RF PHY */
42+
[1] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x01), I2C_ANA_MST_ANA_CONF0_REG, 0x8, 0xc, 1, 0), /* BBPLL calibration enable */
43+
[2] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x02), PMU_RF_PWR_REG, 0xf0000000, 0xf0000000, 1, 0),
44+
[3] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x03), SARADC_TSENS_REG, SARADC_TSENS_PU, 0x400000, 1, 0),
45+
46+
[4] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x04), I2C_ANA_MST_I2C_BURST_CONF_REG, 0, 0xffffffff, 1, 0),
47+
[5] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x05), PMU_DATE_REG, ~I2C_ANA_MST_BURST_DONE, 0x1, 1, 0),
48+
[6] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x06), PMU_DATE_REG, ~I2C_ANA_MST_BURST_DONE, 0x1, 1, 0),
49+
[7] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x07), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE, 0x1, 1, 0),
50+
51+
[8] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x08), FECOEX_SET_FREQ_SET_CHAN_REG, FECOEX_SET_CHAN_EN, 0x20000, 1, 0),
52+
[9] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x09), FECOEX_SET_FREQ_SET_CHAN_REG, 0, 0x20000, 1, 0),
53+
[10] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0a), PMU_DATE_REG, ~FECOEX_SET_CHAN_DONE, 0x100, 1, 0),
54+
[11] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x0b), PMU_DATE_REG, ~FECOEX_SET_CHAN_DONE, 0x100, 1, 0),
55+
[12] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x0c), FECOEX_SET_FREQ_SET_CHAN_ST_REG, FECOEX_SET_CHAN_DONE, 0x100, 1, 0),
56+
[13] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0d), MODEM_SYSCON_WIFI_BB_CFG_REG, BIT(1), 0x2, 1, 0),
57+
[14] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0e), FECOEX_AGC_CONF_REG, 0, 0x20000000, 1, 0),
58+
59+
/* PMU to trigger enable RXBLOCK */
60+
[15] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0f), WDEVTXQ_BLOCK, 0, 0x1000, 1, 0),
61+
62+
/* PMU or software to trigger disable RF PHY */
63+
[16] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x10), FECOEX_AGC_CONF_REG, FECOEX_AGC_DIS, 0x20000000, 0, 1),
64+
[17] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x11), MODEM_SYSCON_WIFI_BB_CFG_REG, 0, 0x2, 0, 1),
65+
[18] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x12), FECOEX_SET_FREQ_SET_CHAN_REG, 0, 0x4000, 0, 1),
66+
[19] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x13), I2C_ANA_MST_I2C_BURST_CONF_REG, 0, 0xffffffff, 0, 1),
67+
[20] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x14), PMU_DATE_REG, ~I2C_ANA_MST_BURST_DONE, 0x1, 0, 1),
68+
[21] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x15), PMU_DATE_REG, ~I2C_ANA_MST_BURST_DONE, 0x1, 0, 1),
69+
[22] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x16), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE, 0x1, 0, 1),
70+
[23] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x17), SARADC_TSENS_REG, 0, 0x400000, 0, 1),
71+
[24] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x18), PMU_RF_PWR_REG, 0, 0xf0000000, 0, 1),
72+
[25] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x19), I2C_ANA_MST_ANA_CONF0_REG, 0x4, 0xc, 0, 1), /* BBPLL calibration disable */
73+
74+
[26] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1a), MODEM_LPCON_CLK_CONF_REG, 0, MODEM_LPCON_CLK_I2C_MST_EN_M, 0, 1), /* I2C MST disable */
75+
76+
/* PMU to trigger disable RXBLOCK */
77+
[27] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1b), PMU_DATE_REG, ~0, 0x6000, 0, 1),
78+
[28] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x1c), PMU_DATE_REG, ~0, 0x6000, 0, 1),
79+
[29] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x1d), WDEVTXQ_BLOCK, 0, 0x6000, 0, 1),
80+
[30] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1e), WDEVTXQ_BLOCK, WDEV_RXBLOCK, 0x1000, 0, 1),
81+
[31] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1f), PMU_DATE_REG, ~0, 0x6000, 0, 1),
82+
[32] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x20), PMU_DATE_REG, ~0, 0x6000, 0, 1),
83+
[33] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x21), WDEVTXQ_BLOCK, 0, 0x6000, 0, 1),
84+
85+
[34] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x22), PMU_SLP_WAKEUP_CNTL7_REG, 0x200000, 0xffff0000, 1, 0),
86+
[35] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x23), PMU_SLP_WAKEUP_CNTL7_REG, 0x9730000, 0xffff0000, 0, 1)
87+
};
88+
extern uint32_t phy_ana_i2c_master_burst_rf_onoff(bool on);
89+
wifi_modem_config[4].write_wait.value = phy_ana_i2c_master_burst_rf_onoff(true);
90+
wifi_modem_config[19].write_wait.value = phy_ana_i2c_master_burst_rf_onoff(false);
91+
92+
void *link = NULL;
93+
for (int i = ARRAY_SIZE(wifi_modem_config) - 1; (err == ESP_OK) && (i >= 0); i--) {
94+
void *next = regdma_link_init_safe(&wifi_modem_config[i], false, 0, link);
95+
if (next) {
96+
link = next;
97+
} else {
98+
regdma_link_destroy(link, 0);
99+
err = ESP_ERR_NO_MEM;
100+
}
101+
}
102+
if (err == ESP_OK) {
103+
pau_regdma_set_modem_link_addr(link);
104+
*link_head = link;
105+
}
106+
#endif
107+
return err;
108+
}
109+
110+
esp_err_t sleep_modem_state_phy_link_deinit(void *link_head)
111+
{
112+
#if SOC_PM_PAU_REGDMA_LINK_WIFIMAC
113+
regdma_link_destroy(link_head, 0);
114+
#endif
115+
return ESP_OK;
116+
}
117+
118+
#endif /* SOC_PM_SUPPORT_PMU_MODEM_STATE */

‎components/esp_hw_support/port/esp32c61/pmu_param.c‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -283,8 +283,8 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m
283283
.hp_active_retention_mode = 0, \
284284
.hp_sleep2active_retention_en = 0, \
285285
.hp_modem2active_retention_en = 0, \
286-
.hp_sleep2active_backup_clk_sel = 0, \
287-
.hp_modem2active_backup_clk_sel = 1, \
286+
.hp_sleep2active_backup_clk_sel = SOC_CPU_CLK_SRC_XTAL, \
287+
.hp_modem2active_backup_clk_sel = SOC_CPU_CLK_SRC_PLL_F160M, \
288288
.hp_sleep2active_backup_mode = PMU_HP_RETENTION_REGDMA_CONFIG(0, 0), \
289289
.hp_modem2active_backup_mode = PMU_HP_RETENTION_REGDMA_CONFIG(0, 2), \
290290
.hp_sleep2active_backup_en = 0, \
@@ -308,7 +308,7 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m
308308
.hp_sleep2modem_backup_modem_clk_code = 1, \
309309
.hp_modem_retention_mode = 0, \
310310
.hp_sleep2modem_retention_en = 0, \
311-
.hp_sleep2modem_backup_clk_sel = 0, \
311+
.hp_sleep2modem_backup_clk_sel = SOC_CPU_CLK_SRC_XTAL, \
312312
.hp_sleep2modem_backup_mode = PMU_HP_RETENTION_REGDMA_CONFIG(0, 1), \
313313
.hp_sleep2modem_backup_en = 0, \
314314
}, \
@@ -332,8 +332,8 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m
332332
.hp_sleep_retention_mode = 0, \
333333
.hp_modem2sleep_retention_en = 0, \
334334
.hp_active2sleep_retention_en = 0, \
335-
.hp_modem2sleep_backup_clk_sel = 0, \
336-
.hp_active2sleep_backup_clk_sel = 0, \
335+
.hp_modem2sleep_backup_clk_sel = SOC_CPU_CLK_SRC_XTAL, \
336+
.hp_active2sleep_backup_clk_sel = SOC_CPU_CLK_SRC_XTAL, \
337337
.hp_modem2sleep_backup_mode = PMU_HP_RETENTION_REGDMA_CONFIG(1, 1), \
338338
.hp_active2sleep_backup_mode = PMU_HP_RETENTION_REGDMA_CONFIG(1, 0), \
339339
.hp_modem2sleep_backup_en = 0, \

‎components/esp_hw_support/port/esp32c61/private_include/pmu_param.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -469,7 +469,7 @@ typedef struct pmu_sleep_machine_constant {
469469
}, \
470470
.hp = { \
471471
.min_slp_time_us = 450, \
472-
.clock_domain_sync_time_us = 150, \
472+
.clock_domain_sync_time_us = 35, \
473473
.system_dfs_up_work_time_us = 124, \
474474
.analog_wait_time_us = 154, \
475475
.isolate_wait_time_us = 1, \

‎components/esp_phy/lib‎

‎components/esp_phy/src/phy_override.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -74,7 +74,7 @@ void phy_set_pwdet_power(bool en)
7474
#endif
7575
}
7676

77-
void phy_set_tsens_power(bool en)
77+
void IRAM_ATTR phy_set_tsens_power(bool en)
7878
{
7979
#if CONFIG_SOC_TEMP_SENSOR_SUPPORTED // TODO: [ESP32C5] IDF-8727 remove me when fix IDF-8727
8080
if (s_wifi_tsens_xpd_flag == en) {

‎components/esp_rom/esp32c61/ld/esp32c61.rom.phy.ld‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -177,8 +177,8 @@ phy_dac_rate_set = 0x400012b8;
177177
phy_encode_i2c_master = 0x400012bc;
178178
phy_i2c_master_fill = 0x400012c0;
179179
phy_i2c_master_mem_txcap = 0x400012c4;
180-
phy_i2c_master_cmd_mem_init = 0x400012c8;
181-
phy_i2c_master_mem_cfg = 0x400012cc;
180+
/* phy_i2c_master_cmd_mem_init = 0x400012c8; */
181+
/* phy_i2c_master_mem_cfg = 0x400012cc; */
182182
phy_pbus_force_mode = 0x400012d0;
183183
phy_pbus_rd_addr = 0x400012d4;
184184
phy_pbus_rd_shift = 0x400012d8;

‎components/esp_wifi/lib‎

Submodule lib updated 61 files

‎components/soc/esp32c61/include/soc/Kconfig.soc_caps.in‎

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -811,6 +811,14 @@ config SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH
811811
int
812812
default 12
813813

814+
config SOC_PM_SUPPORT_WIFI_WAKEUP
815+
bool
816+
default y
817+
818+
config SOC_PM_SUPPORT_BEACON_WAKEUP
819+
bool
820+
default y
821+
814822
config SOC_PM_SUPPORT_EXT1_WAKEUP
815823
bool
816824
default y
@@ -861,7 +869,7 @@ config SOC_PM_SUPPORT_RTC_PERIPH_PD
861869

862870
config SOC_PM_SUPPORT_PMU_MODEM_STATE
863871
bool
864-
default n
872+
default y
865873

866874
config SOC_PM_CPU_RETENTION_BY_SW
867875
bool

‎components/soc/esp32c61/include/soc/soc_caps.h‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -414,8 +414,8 @@
414414

415415
// TODO: IDF-5351 (Copy from esp32c3, need check)
416416
/*-------------------------- Power Management CAPS ----------------------------*/
417-
// #define SOC_PM_SUPPORT_WIFI_WAKEUP (1)
418-
// #define SOC_PM_SUPPORT_BEACON_WAKEUP (1)
417+
#define SOC_PM_SUPPORT_WIFI_WAKEUP (1)
418+
#define SOC_PM_SUPPORT_BEACON_WAKEUP (1)
419419
// #define SOC_PM_SUPPORT_BT_WAKEUP (1)
420420
#define SOC_PM_SUPPORT_EXT1_WAKEUP (1)
421421
#define SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN (1) /*!<Supports one bit per pin to configure the EXT1 trigger level */
@@ -430,7 +430,7 @@
430430
#define SOC_PM_SUPPORT_MAC_BB_PD (1)
431431
#define SOC_PM_SUPPORT_RTC_PERIPH_PD (1)
432432

433-
#define SOC_PM_SUPPORT_PMU_MODEM_STATE (0)
433+
#define SOC_PM_SUPPORT_PMU_MODEM_STATE (1)
434434
/* macro redefine for pass esp_wifi headers md5sum check */
435435
#define MAC_SUPPORT_PMU_MODEM_STATE SOC_PM_SUPPORT_PMU_MODEM_STATE
436436

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