Merge branch 'feature/support_c5_eco2_rom' into 'master'

feat(rom): update rom for c5 eco2

See merge request espressif/esp-idf!38297

Author: L-KAYA

.gitlab/ci/default-build-test-rules.yml

@@ -15,6 +15,7 @@ extra_default_build_targets:
 bypass_check_test_targets:
   - esp32h21
   - esp32h4
+  - esp32c5
 
 #
 # These lines would

Kconfig

@@ -118,6 +118,8 @@ mainmenu "Espressif IoT Development Framework Configuration"
         default "y" if IDF_TARGET="esp32c5"
         select FREERTOS_UNICORE
         select IDF_TARGET_ARCH_RISCV
+        # TODO: [ESPTOOL-1044] remove when stub supported
+        select IDF_ENV_BRINGUP
 
     config IDF_TARGET_ESP32P4
         bool

components/bootloader/subproject/main/ld/esp32c5/bootloader.ld

@@ -7,20 +7,20 @@
  *  Make sure the bootloader can load into main memory without overwriting itself.
  *
  *  ESP32-C5 ROM static data usage is as follows:
- *  - 0x4084e9a0 - 0x4085c9a0: Shared buffers, used in UART/USB/SPI download mode only
- *  - 0x4085c9a0 - 0x4085e9a0: PRO CPU stack, can be reclaimed as heap after RTOS startup
- *  - 0x4085e9a0 - 0x40860000: ROM .bss and .data (not easily reclaimable)
+ *  - 0x4084e5a0 - 0x4085c5a0: Shared buffers, used in UART/USB/SPI download mode only
+ *  - 0x4085c5a0 - 0x4085e5a0: PRO CPU stack, can be reclaimed as heap after RTOS startup
+ *  - 0x4085e5a0 - 0x40860000: ROM .bss and .data (not easily reclaimable)
  *
  *  The 2nd stage bootloader can take space up to the end of ROM shared
- *  buffers area (0x4085c9a0).
+ *  buffers area (0x4085c5a0).
  */
 
-/* We consider 0x4085c9a0 to be the last usable address for 2nd stage bootloader stack overhead, dram_seg,
+/* We consider 0x4085c5a0 to be the last usable address for 2nd stage bootloader stack overhead, dram_seg,
  * and work out iram_seg and iram_loader_seg addresses from there, backwards.
  */
 
 /* These lengths can be adjusted, if necessary: */
-bootloader_usable_dram_end = 0x4085c9a0;
+bootloader_usable_dram_end = 0x4085c5a0;
 bootloader_stack_overhead = 0x2000; /* For safety margin between bootloader data section and startup stacks */
 bootloader_dram_seg_len = 0x5000;
 bootloader_iram_loader_seg_len = 0x7000;
@@ -45,7 +45,7 @@ MEMORY
  * 2. Update the value in this assert.
  * 3. Update SRAM_DRAM_END in components/esp_system/ld/esp32c5/memory.ld.in to the same value.
  */
-ASSERT(bootloader_iram_loader_seg_start == 0x4084E9A0, "bootloader_iram_loader_seg_start inconsistent with SRAM_DRAM_END");
+ASSERT(bootloader_iram_loader_seg_start == 0x4084e5a0, "bootloader_iram_loader_seg_start inconsistent with SRAM_DRAM_END");
 
 /* Default entry point: */
 ENTRY(call_start_cpu0);
@@ -277,32 +277,32 @@ SECTIONS
 /**
  *  Appendix: Memory Usage of ROM bootloader
  *
- * 0x4084e9a0 ------------------> _dram0_0_start
+ * 0x4084e5a0 ------------------> _dram0_0_start
  *            |               |
  *            |               |
  *            |               |   1. Large buffers that are only used in certain boot modes, see shared_buffers.h
  *            |               |
  *            |               |
- * 0x4085c9a0 ------------------> __stack_sentry
+ * 0x4085c5a0 ------------------> __stack_sentry
  *            |               |
  *            |               |   2. Startup pro cpu stack (freed when IDF app is running)
  *            |               |
- * 0x4085e9a0 ------------------> __stack (pro cpu)
+ * 0x4085e5a0 ------------------> __stack (pro cpu)
  *            |               |
  *            |               |
  *            |               |   3. Shared memory only used in startup code or nonos/early boot*
  *            |               |      (can be freed when IDF runs)
  *            |               |
  *            |               |
- * 0x4085f500 ------------------> _dram0_rtos_reserved_start
+ * 0x4085f4f8 ------------------> _dram0_rtos_reserved_start
  *            |               |
  *            |               |
  *            |               |   4. Shared memory used in startup code and when IDF runs
  *            |               |
  *            |               |
- * 0x4085fc5c ------------------> _dram0_rtos_reserved_end
+ * 0x4085fbb4 ------------------> _dram0_rtos_reserved_end
  *            |               |
- * 0x4085fc70 ------------------> _data_start_interface
+ * 0x4085fc60 ------------------> _data_start_interface
  *            |               |
  *            |               |   5. End of DRAM is the 'interface' data with constant addresses (ECO compatible)
  *            |               |

components/esp_hw_support/lowpower/port/esp32c5/sleep_clock.c

@@ -118,7 +118,9 @@ bool clock_domain_pd_allowed(void)
      * necessary to check the state of CLOCK_MODEM to determine MODEM domain on
      * or off. The clock and reset of digital peripherals are managed through
      * PCR, with TOP domain similar to MODEM domain. */
+#if SOC_WIFI_SUPPORTED || SOC_BLE_SUPPORTED || SOC_IEEE802154_SUPPORTED
     sleep_retention_module_bitmap_t modem_clk_dep_modules = (sleep_retention_module_bitmap_t){ .bitmap = { 0 } };
+#endif
 #if SOC_WIFI_SUPPORTED
     modem_clk_dep_modules.bitmap[SLEEP_RETENTION_MODULE_WIFI_MAC >> 5] |= BIT(SLEEP_RETENTION_MODULE_WIFI_MAC % 32);
     modem_clk_dep_modules.bitmap[SLEEP_RETENTION_MODULE_WIFI_BB >> 5] |= BIT(SLEEP_RETENTION_MODULE_WIFI_BB % 32);

components/esp_hw_support/port/esp32c5/Kconfig.hw_support

@@ -1,6 +1,6 @@
 choice ESP32C5_REV_MIN
     prompt "Minimum Supported ESP32-C5 Revision"
-    default ESP32C5_REV_MIN_0
+    default ESP32C5_REV_MIN_100
     help
         Required minimum chip revision. ESP-IDF will check for it and
         reject to boot if the chip revision fails the check.
@@ -9,16 +9,13 @@ choice ESP32C5_REV_MIN
         The complied binary will only support chips above this revision,
         this will also help to reduce binary size.
 
-    config ESP32C5_REV_MIN_0
-        bool "Rev v0.0 (ECO0)"
-    config ESP32C5_REV_MIN_1
-        bool "Rev v0.1 (ECO1)"
+    config ESP32C5_REV_MIN_100
+        bool "Rev v1.0 (ECO2)"
 endchoice
 
 config ESP32C5_REV_MIN_FULL
     int
-    default 0 if ESP32C5_REV_MIN_0
-    default 1 if ESP32C5_REV_MIN_1
+    default 100 if ESP32C5_REV_MIN_100
 
 config ESP_REV_MIN_FULL
     int
@@ -28,15 +25,15 @@ config ESP_REV_MIN_FULL
     # MAX Revision
     #
 
-    comment "Maximum Supported ESP32-C5 Revision (Rev v0.99)"
+    comment "Maximum Supported ESP32-C5 Revision (Rev v1.99)"
     # Maximum revision that IDF supports.
     # It can not be changed by user.
     # Only Espressif can change it when a new version will be supported in IDF.
     # Supports all chips starting from ESP32C5_REV_MIN_FULL to ESP32C5_REV_MAX_FULL
 
 config ESP32C5_REV_MAX_FULL
     int
-    default 99
+    default 199
     # keep in sync the "Maximum Supported Revision" description with this value
 
 config ESP_REV_MAX_FULL

components/esp_rom/esp32c5/Kconfig.soc_caps.in

@@ -75,7 +75,7 @@ config ESP_ROM_HAS_NEWLIB
     bool
     default y
 
-config ESP_ROM_HAS_NEWLIB_NORMAL_FORMAT
+config ESP_ROM_HAS_NEWLIB_NANO_FORMAT
     bool
     default y
 

components/esp_rom/esp32c5/esp_rom_caps.h

@@ -24,7 +24,7 @@
 #define ESP_ROM_HAS_SPI_FLASH_MMAP          (1) // ROM has the implementation of SPI Flash mmap driver
 #define ESP_ROM_WITHOUT_REGI2C              (1) // ROM has no regi2c APIs       TODO: IDF-10110 need refactor
 #define ESP_ROM_HAS_NEWLIB                  (1) // ROM has newlib (at least parts of it) functions included
-#define ESP_ROM_HAS_NEWLIB_NORMAL_FORMAT    (1) // ROM has the newlib normal/full version of formatting functions (as opposed to the nano versions)
+#define ESP_ROM_HAS_NEWLIB_NANO_FORMAT      (1) // ROM has the newlib nano version of formatting functions
 #define ESP_ROM_WDT_INIT_PATCH              (1) // ROM version does not configure the clock
 #define ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE    (1) // ROM needs to set cache MMU size according to instruction and rodata for flash mmap
 #define ESP_ROM_RAM_APP_NEEDS_MMU_INIT      (1) // ROM doesn't init cache MMU when it's a RAM APP, needs MMU hal to init

components/esp_rom/esp32c5/ld/esp32c5.rom.api.ld

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */

components/esp_rom/esp32c5/ld/esp32c5.rom.coexist.ld

@@ -1,14 +1,14 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 /* ROM function interface esp32c5.rom.coexist.ld for esp32c5
  *
  *
- * Generated from ./target/esp32c5/interface-esp32c5.yml md5sum f5c146321f24f88ad1f27234da5aed11
+ * Generated from ./target/esp32c5/interface-esp32c5.yml md5sum 4dfe6ccc311ca3575012c23e3753353c
  *
- * Compatible with ROM where ECO version equal or greater to 0.
+ * Compatible with ROM where ECO version equal or greater to 2.
  *
  * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
  */

components/esp_rom/esp32c5/ld/esp32c5.rom.heap.ld

@@ -1,14 +1,14 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 /* ROM function interface esp32c5.rom.heap.ld for esp32c5
  *
  *
- * Generated from ./target/esp32c5/interface-esp32c5.yml md5sum f5c146321f24f88ad1f27234da5aed11
+ * Generated from ./target/esp32c5/interface-esp32c5.yml md5sum 4dfe6ccc311ca3575012c23e3753353c
  *
- * Compatible with ROM where ECO version equal or greater to 0.
+ * Compatible with ROM where ECO version equal or greater to 2.
  *
  * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
  */