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Merge branch 'feat/h21_spi_driver_support' into 'master'
feat(driver_spi): h21 spi driver support Closes IDF-11583 and IDF-11587 See merge request espressif/esp-idf!37442
2 parents a25e7ab + 83c0999 commit 1e30aa7

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‎components/driver/test_apps/components/test_driver_utils/include/test_spi_utils.h‎

Lines changed: 10 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -282,11 +282,18 @@ void spitest_gpio_input_sel(uint32_t gpio_num, int func, uint32_t signal_idx);
282282

283283
//Note this cs_num is the ID of the connected devices' ID, e.g. if 2 devices are connected to the bus,
284284
//then the cs_num of the 1st and 2nd devices are 0 and 1 respectively.
285-
void same_pin_func_sel(spi_bus_config_t bus, spi_device_interface_config_t dev, uint8_t cs_num);
285+
//Enable `soft_master` to connect to soft spi master instead of hardware master.
286+
void same_pin_func_sel(spi_bus_config_t bus, uint8_t cs_pin, uint8_t cs_dev_id, bool soft_master);
286287

287288
// Soft simulated spi master host for slave testing
288-
// TODO: `speed_hz` is not implemented yet, temp to max 500Hz
289+
// `speed_hz` max 500kHz
289290
// TODO: mode 0 only
290-
void spi_master_trans_impl_gpio(spi_bus_config_t bus, uint8_t cs_pin, uint8_t speed_hz, void *tx, void *rx, uint32_t len);
291+
void spi_master_trans_impl_gpio(spi_bus_config_t bus, uint8_t cs_pin, uint32_t speed_hz, uint8_t *tx, uint8_t *rx, uint32_t len, bool hold_cs);
292+
293+
// Send/Receive long buffer by soft spi master in segments to the slave_hd through its DMA, refer to `essl_spi_wrdma/essl_spi_rddma`
294+
void essl_sspi_hd_dma_trans_seg(spi_bus_config_t bus, uint8_t cs_pin, uint32_t speed_hz, bool is_rx, void *buffer, int len, int seg_len);
295+
296+
// Write/Read the shared buffer of the slave_hd by soft spi master, refer to `essl_spi_wrbuf/essl_spi_rdbuf`
297+
void essl_sspi_hd_buffer_trans(spi_bus_config_t bus, uint8_t cs_pin, uint32_t speed_hz, spi_command_t cmd, uint8_t addr, void *buffer, uint32_t len);
291298

292299
#endif //_TEST_COMMON_SPI_H_

‎components/driver/test_apps/components/test_driver_utils/test_spi_utils.c‎

Lines changed: 59 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,7 @@
99
#include "driver/gpio.h"
1010
#include "esp_private/gpio.h"
1111
#include "hal/gpio_hal.h"
12+
#include "hal/spi_ll.h"
1213
#include "esp_rom_gpio.h"
1314

1415
int test_freq_default[] = TEST_FREQ_DEFAULT();
@@ -232,49 +233,81 @@ void spitest_gpio_input_sel(uint32_t gpio_num, int func, uint32_t signal_idx)
232233
esp_rom_gpio_connect_in_signal(gpio_num, signal_idx, 0);
233234
}
234235

235-
//Note this cs_dev_id is the ID of the connected devices' ID, e.g. if 2 devices are connected to the bus,
236-
//then the cs_dev_id of the 1st and 2nd devices are 0 and 1 respectively.
237-
void same_pin_func_sel(spi_bus_config_t bus, spi_device_interface_config_t dev, uint8_t cs_dev_id)
236+
void same_pin_func_sel(spi_bus_config_t bus, uint8_t cs_pin, uint8_t cs_dev_id, bool soft_master)
238237
{
239-
spitest_gpio_output_sel(bus.mosi_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spid_out);
238+
spitest_gpio_output_sel(bus.mosi_io_num, FUNC_GPIO, soft_master ? SIG_GPIO_OUT_IDX : spi_periph_signal[TEST_SPI_HOST].spid_out);
240239
spitest_gpio_input_sel(bus.mosi_io_num, FUNC_GPIO, spi_periph_signal[TEST_SLAVE_HOST].spid_in);
241240

242241
spitest_gpio_output_sel(bus.miso_io_num, FUNC_GPIO, spi_periph_signal[TEST_SLAVE_HOST].spiq_out);
243-
spitest_gpio_input_sel(bus.miso_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spiq_in);
242+
spitest_gpio_input_sel(bus.miso_io_num, FUNC_GPIO, soft_master ? SIG_GPIO_OUT_IDX : spi_periph_signal[TEST_SPI_HOST].spiq_in);
244243

245-
spitest_gpio_output_sel(dev.spics_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spics_out[cs_dev_id]);
246-
spitest_gpio_input_sel(dev.spics_io_num, FUNC_GPIO, spi_periph_signal[TEST_SLAVE_HOST].spics_in);
244+
gpio_set_level(cs_pin, 1); //ensure CS is inactive when select to soft_master and before transaction start
245+
spitest_gpio_output_sel(cs_pin, FUNC_GPIO, soft_master ? SIG_GPIO_OUT_IDX : spi_periph_signal[TEST_SPI_HOST].spics_out[cs_dev_id]);
246+
spitest_gpio_input_sel(cs_pin, FUNC_GPIO, spi_periph_signal[TEST_SLAVE_HOST].spics_in);
247247

248-
spitest_gpio_output_sel(bus.sclk_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spiclk_out);
248+
spitest_gpio_output_sel(bus.sclk_io_num, FUNC_GPIO, soft_master ? SIG_GPIO_OUT_IDX : spi_periph_signal[TEST_SPI_HOST].spiclk_out);
249249
spitest_gpio_input_sel(bus.sclk_io_num, FUNC_GPIO, spi_periph_signal[TEST_SLAVE_HOST].spiclk_in);
250250
}
251251

252-
void spi_master_trans_impl_gpio(spi_bus_config_t bus, uint8_t cs_pin, uint8_t speed_hz, void *tx, void *rx, uint32_t len)
252+
#define GPIO_MAX_FREQ 500*1000 //max of soft spi clock at delay(0)
253+
void spi_master_trans_impl_gpio(spi_bus_config_t bus, uint8_t cs_pin, uint32_t speed_hz, uint8_t *tx, uint8_t *rx, uint32_t len, bool hold_cs)
253254
{
254-
uint8_t *u8_tx = tx, *u8_rx = rx;
255-
gpio_set_level(cs_pin, 1); //ensure CS is inactive before transaction start
256-
esp_rom_gpio_connect_out_signal(cs_pin, SIG_GPIO_OUT_IDX, 0, 0);
257-
esp_rom_gpio_connect_out_signal(bus.sclk_io_num, SIG_GPIO_OUT_IDX, 0, 0);
258-
esp_rom_gpio_connect_out_signal(bus.mosi_io_num, SIG_GPIO_OUT_IDX, 0, 0);
259-
esp_rom_gpio_connect_in_signal(bus.miso_io_num, SIG_GPIO_OUT_IDX, 0);
260-
261-
gpio_set_level(cs_pin, 0);
262-
vTaskDelay(1); // cs_ena_pre_trans
255+
gpio_dev_t *hw = GPIO_LL_GET_HW(0);
256+
uint32_t half_duty_us = speed_hz ? ((GPIO_MAX_FREQ + speed_hz / 2) / speed_hz / 2) : 0;
257+
258+
gpio_ll_set_level(hw, cs_pin, 0);
263259
for (uint32_t index = 0; index < len; index ++) {
264260
uint8_t rx_data = 0;
265261
for (uint8_t bit = 0x80; bit > 0; bit >>= 1) {
266262
// mode 0, output data first
267-
gpio_set_level(bus.mosi_io_num, (u8_tx) ? (u8_tx[index] & bit) : 0);
268-
vTaskDelay(1);
269-
gpio_set_level(bus.sclk_io_num, 1);
263+
gpio_ll_set_level(hw, bus.mosi_io_num, (tx) ? (tx[index] & bit) : 0);
264+
esp_rom_delay_us(half_duty_us);
270265
rx_data <<= 1;
271266
rx_data |= gpio_get_level(bus.miso_io_num);
272-
vTaskDelay(1);
273-
gpio_set_level(bus.sclk_io_num, 0);
267+
gpio_ll_set_level(hw, bus.sclk_io_num, 1);
268+
esp_rom_delay_us(half_duty_us);
269+
gpio_ll_set_level(hw, bus.sclk_io_num, 0);
274270
}
275-
if (u8_rx) {
276-
u8_rx[index] = rx_data;
271+
if (rx) {
272+
rx[index] = rx_data;
277273
}
278274
}
279-
gpio_set_level(cs_pin, 1);
275+
if (!hold_cs) {
276+
gpio_ll_set_level(hw, cs_pin, 1);
277+
}
278+
}
279+
280+
#if SOC_SPI_SUPPORT_SLAVE_HD_VER2
281+
void essl_sspi_hd_dma_trans_seg(spi_bus_config_t bus, uint8_t cs_pin, uint32_t speed_hz, bool is_rx, void *buffer, int len, int seg_len)
282+
{
283+
uint8_t cmd_addr_dummy[3] = {0, 0, 0};
284+
uint8_t *tx = is_rx ? NULL : buffer;
285+
uint8_t *rx = is_rx ? buffer : NULL;
286+
287+
seg_len = (seg_len > 0) ? seg_len : len;
288+
cmd_addr_dummy[0] = spi_ll_get_slave_hd_base_command(is_rx ? SPI_CMD_HD_RDDMA : SPI_CMD_HD_WRDMA);
289+
while (len > 0) {
290+
spi_master_trans_impl_gpio(bus, cs_pin, speed_hz, cmd_addr_dummy, NULL, sizeof(cmd_addr_dummy), true);
291+
292+
int send_len = (seg_len <= len) ? seg_len : len;
293+
spi_master_trans_impl_gpio(bus, cs_pin, speed_hz, tx, rx, send_len, false);
294+
len -= send_len;
295+
tx += tx ? send_len : 0;
296+
rx += rx ? send_len : 0;
297+
}
298+
299+
cmd_addr_dummy[0] = spi_ll_get_slave_hd_base_command(is_rx ? SPI_CMD_HD_INT0 : SPI_CMD_HD_WR_END);
300+
spi_master_trans_impl_gpio(bus, cs_pin, speed_hz, cmd_addr_dummy, NULL, sizeof(cmd_addr_dummy), false);
301+
}
302+
303+
void essl_sspi_hd_buffer_trans(spi_bus_config_t bus, uint8_t cs_pin, uint32_t speed_hz, spi_command_t cmd, uint8_t addr, void *buffer, uint32_t len)
304+
{
305+
uint8_t cmd_addr_dummy[3] = {0, addr, 0};
306+
cmd_addr_dummy[0] = spi_ll_get_slave_hd_base_command(cmd);
307+
uint8_t *tx = (cmd == SPI_CMD_HD_RDBUF) ? NULL : buffer;
308+
uint8_t *rx = (cmd == SPI_CMD_HD_RDBUF) ? buffer : NULL;
309+
310+
spi_master_trans_impl_gpio(bus, cs_pin, speed_hz, cmd_addr_dummy, NULL, sizeof(cmd_addr_dummy), true);
311+
spi_master_trans_impl_gpio(bus, cs_pin, speed_hz, tx, rx, len, false);
280312
}
313+
#endif //SOC_SPI_SUPPORT_SLAVE_HD_VER2

‎components/driver/test_apps/touch_sensor_v1/pytest_touch_sensor_v1.py‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,4 +15,4 @@
1515
)
1616
@idf_parametrize('target', ['esp32'], indirect=['target'])
1717
def test_touch_sensor_v1(dut: Dut) -> None:
18-
dut.run_all_single_board_cases(timeout=60)
18+
dut.run_all_single_board_cases(timeout=60, reset=True)

‎components/esp_driver_sdspi/test_apps/sdspi/README.md‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,2 +1,2 @@
1-
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
2-
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
1+
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
2+
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |

‎components/esp_driver_spi/src/gpspi/spi_master.c‎

Lines changed: 6 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -115,8 +115,8 @@ We have two bits to control the interrupt:
115115
#include "esp_private/periph_ctrl.h"
116116
#include "esp_private/spi_common_internal.h"
117117
#include "esp_private/spi_master_internal.h"
118+
#include "esp_private/esp_clk_tree_common.h"
118119
#include "driver/spi_master.h"
119-
#include "esp_clk_tree.h"
120120
#include "clk_ctrl_os.h"
121121
#include "esp_log.h"
122122
#include "esp_check.h"
@@ -415,12 +415,10 @@ esp_err_t spi_bus_add_device(spi_host_device_t host_id, const spi_device_interfa
415415
SPI_CHECK(periph_rtc_dig_clk8m_enable(), "the selected clock not available", ESP_ERR_INVALID_STATE);
416416
}
417417
#endif
418-
spi_clock_source_t clk_src = SPI_CLK_SRC_DEFAULT;
418+
spi_clock_source_t clk_src = dev_config->clock_source ? dev_config->clock_source : SPI_CLK_SRC_DEFAULT;
419419
uint32_t clock_source_hz = 0;
420420
uint32_t clock_source_div = 1;
421-
if (dev_config->clock_source) {
422-
clk_src = dev_config->clock_source;
423-
}
421+
esp_clk_tree_enable_src(clk_src, true);
424422
esp_clk_tree_src_get_freq_hz(clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clock_source_hz);
425423
#if SPI_LL_SUPPORT_CLK_SRC_PRE_DIV
426424
SPI_CHECK((dev_config->clock_speed_hz > 0) && (dev_config->clock_speed_hz <= MIN(clock_source_hz / 2, (80 * 1000000))), "invalid sclk speed", ESP_ERR_INVALID_ARG);
@@ -584,7 +582,7 @@ esp_err_t spi_bus_remove_device(spi_device_handle_t handle)
584582
}
585583

586584
#if SOC_SPI_SUPPORT_CLK_RC_FAST
587-
if (handle->cfg.clock_source == SPI_CLK_SRC_RC_FAST) {
585+
if (handle->hal_dev.timing_conf.clock_source == SPI_CLK_SRC_RC_FAST) {
588586
// If no transactions from other device, acquire the bus to switch module clock to `SPI_CLK_SRC_DEFAULT`
589587
// because `SPI_CLK_SRC_RC_FAST` will be disabled then, which block following transactions
590588
if (handle->host->cur_cs == DEV_NUM_MAX) {
@@ -597,6 +595,7 @@ esp_err_t spi_bus_remove_device(spi_device_handle_t handle)
597595
periph_rtc_dig_clk8m_disable();
598596
}
599597
#endif
598+
esp_clk_tree_enable_src(handle->hal_dev.timing_conf.clock_source, false);
600599

601600
//return
602601
int spics_io_num = handle->cfg.spics_io_num;

‎components/esp_driver_spi/test_apps/components/spi_bench_mark/include/spi_performance.h‎

Lines changed: 74 additions & 58 deletions
Original file line numberDiff line numberDiff line change
@@ -1,93 +1,109 @@
11
/*
2-
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
66

77
#pragma once
88

99
#if CONFIG_IDF_TARGET_ESP32
10-
#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ 16*1000*1000
11-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 15
12-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 15
10+
#define IDF_TARGET_MAX_SPI_CLK_FREQ 16*1000*1000
11+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA 15
12+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU 15
1313
#if !CONFIG_FREERTOS_SMP // IDF-5223
14-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 34 // TODO: IDF-5180
15-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 30 // TODO: IDF-5180
14+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA 34 // TODO: IDF-5180
15+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU 30 // TODO: IDF-5180
1616
#else
17-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 50
18-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 50
17+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA 50
18+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU 50
1919
#endif
2020

2121
#elif CONFIG_IDF_TARGET_ESP32S2
22-
#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ 40*1000*1000
23-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 15
24-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 15
25-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 32
26-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 30
22+
#define IDF_TARGET_MAX_SPI_CLK_FREQ 40*1000*1000
23+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA 15
24+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU 15
25+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA 32
26+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU 30
2727

2828
#elif CONFIG_IDF_TARGET_ESP32S3
29-
#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ 40*1000*1000
30-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 15
31-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 15
32-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 32
33-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 30
29+
#define IDF_TARGET_MAX_SPI_CLK_FREQ 40*1000*1000
30+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA 15
31+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU 15
32+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA 32
33+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU 30
3434

3535
#elif CONFIG_IDF_TARGET_ESP32C2
36-
#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ 40*1000*1000
37-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 23
38-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 18
39-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 47
40-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 42
36+
#define IDF_TARGET_MAX_SPI_CLK_FREQ 40*1000*1000
37+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA 23
38+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU 18
39+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA 47
40+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU 42
4141

4242
#elif CONFIG_IDF_TARGET_ESP32C3
43-
#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ 40*1000*1000
43+
#define IDF_TARGET_MAX_SPI_CLK_FREQ 40*1000*1000
4444
#if !CONFIG_FREERTOS_SMP // IDF-5223
45-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 15
46-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 15
47-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 33
48-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 30
45+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA 15
46+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU 15
47+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA 33
48+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU 30
4949
#else
50-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 17
51-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 17
52-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 60
53-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 60
50+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA 17
51+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU 17
52+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA 60
53+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU 60
5454
#endif
5555

5656
#elif CONFIG_IDF_TARGET_ESP32C6
57-
#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ 26666*1000
58-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 35 //TODO: IDF-9551, check perform
59-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 17
60-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 32
61-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 15
57+
#define IDF_TARGET_MAX_SPI_CLK_FREQ 26666*1000
58+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA 35 //TODO: IDF-9551, check perform
59+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA 17
60+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU 32
61+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU 15
6262

6363
#elif CONFIG_IDF_TARGET_ESP32H2
64-
#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ 24*1000*1000
65-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 32
66-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 25
67-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 61
68-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 54
64+
#define IDF_TARGET_MAX_SPI_CLK_FREQ 24*1000*1000
65+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA 32
66+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU 25
67+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA 61
68+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU 54
6969

7070
#elif CONFIG_IDF_TARGET_ESP32P4
71-
#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ 20*1000*1000
72-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 44
73-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 28
74-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 26
75-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 12
71+
#define IDF_TARGET_MAX_SPI_CLK_FREQ 20*1000*1000
72+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA 44
73+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA 28
74+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU 26
75+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU 12
7676

7777
#elif CONFIG_IDF_TARGET_ESP32C5
78-
#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ 40*1000*1000
79-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 24
80-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 15
81-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 22
82-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 12
78+
#define IDF_TARGET_MAX_SPI_CLK_FREQ 40*1000*1000
79+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA 24
80+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA 15
81+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU 22
82+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU 12
8383

8484
#elif CONFIG_IDF_TARGET_ESP32C61
85-
#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ 40*1000*1000
86-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 32
87-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 19
88-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 29
89-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 14
85+
#define IDF_TARGET_MAX_SPI_CLK_FREQ 40*1000*1000
86+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA 32
87+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA 19
88+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU 29
89+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU 14
9090

91+
#elif CONFIG_IDF_TARGET_ESP32H21
92+
#if SOC_CLK_TREE_SUPPORTED
93+
//TODO: [ESP32H21] IDF-11521 update perform data according to `TEST_CASE("spi_speed", "[spi]")`
94+
//Also update this value in doc spi_master.rst:535
95+
#define IDF_TARGET_MAX_SPI_CLK_FREQ 32*1000*1000
96+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA 0 // need update to real_val + 3
97+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA 0 // need update to real_val + 3
98+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU 0 // need update to real_val + 3
99+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU 0 // need update to real_val + 3
91100
#else
92-
#pragma message "`spi_performance.h` is not updated with your target"
101+
// Remove after SOC_CLK_TREE_SUPPORTED
102+
#define IDF_TARGET_MAX_SPI_CLK_FREQ 32*1000*1000
103+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA 1000
104+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA 1000
105+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU 1000
106+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU 1000
107+
#endif
108+
93109
#endif

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