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Commit 22f6319

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author
Chai Ji’e
committed
Merge branch 'feat/support_different_pwr_glitch_dref_to_fit_eco_esp32c61' into 'master'
feat(power_glich): power glitch initial for esp32c5/esp32c61, only detect vddpst pwr_glitch, not support esp32c5_eco0 & eco32c61_eco0/1 no longer See merge request espressif/esp-idf!35206
2 parents 0e85a78 + 1db7914 commit 22f6319

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8 files changed

+59
-31
lines changed

8 files changed

+59
-31
lines changed

‎components/bootloader_support/private_include/bootloader_soc.h‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -25,12 +25,11 @@ void bootloader_ana_super_wdt_reset_config(bool enable);
2525
void bootloader_ana_clock_glitch_reset_config(bool enable);
2626

2727
/**
28-
* @brief Configure analog power glitch reset & glitch reset dref
28+
* @brief Configure analog power glitch reset
2929
*
3030
* @param enable Boolean to enable or disable power glitch reset
31-
* @param dref voltage threshold
3231
*/
33-
void bootloader_power_glitch_reset_config(bool enable, uint8_t dref);
32+
void bootloader_power_glitch_reset_config(bool enable);
3433

3534
#ifdef __cplusplus
3635
}

‎components/bootloader_support/src/esp32c5/bootloader_esp32c5.c‎

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -94,11 +94,7 @@ static inline void bootloader_ana_reset_config(void)
9494
{
9595
//Enable BOD reset (mode1)
9696
brownout_ll_ana_reset_enable(true);
97-
if (efuse_hal_chip_revision() == 0) {
98-
// decrease power glitch reset voltage to avoid start the glitch reset
99-
uint8_t power_glitch_dref = 0;
100-
bootloader_power_glitch_reset_config(true, power_glitch_dref);
101-
}
97+
bootloader_power_glitch_reset_config(true);
10298
}
10399

104100
esp_err_t bootloader_init(void)

‎components/bootloader_support/src/esp32c5/bootloader_soc.c‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -17,18 +17,18 @@ void bootloader_ana_clock_glitch_reset_config(bool enable)
1717
(void)enable;
1818
}
1919

20-
void bootloader_power_glitch_reset_config(bool enable, uint8_t dref)
20+
void bootloader_power_glitch_reset_config(bool enable)
2121
{
22-
assert(dref < 8);
23-
REG_SET_FIELD(LP_ANA_FIB_ENABLE_REG, LP_ANA_ANA_FIB_PWR_GLITCH_ENA, 0);
22+
//only detect VDDPST POWER GLITCH
23+
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
24+
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
25+
REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_XPD_VDET_PERIF, 0);
26+
REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_XPD_VDET_XTAL, 0);
27+
REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_XPD_VDET_PLL, 0);
28+
29+
REG_SET_FIELD(LP_ANA_FIB_ENABLE_REG, LP_ANA_ANA_FIB_PWR_GLITCH_ENA, 0);//default val for chip from ECO1
2430
if (enable) {
25-
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
26-
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
27-
REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_PERIF, dref);
28-
REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_VDDPST, dref);
29-
REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_XTAL, dref);
30-
REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_PLL, dref);
31-
REG_SET_FIELD(LP_ANA_POWER_GLITCH_CNTL_REG, LP_ANA_PWR_GLITCH_RESET_ENA, 0xf);
31+
REG_SET_FIELD(LP_ANA_POWER_GLITCH_CNTL_REG, LP_ANA_PWR_GLITCH_RESET_ENA, 0xf);//default val for chip from ECO1
3232
} else {
3333
REG_SET_FIELD(LP_ANA_POWER_GLITCH_CNTL_REG, LP_ANA_PWR_GLITCH_RESET_ENA, 0);
3434
}

‎components/bootloader_support/src/esp32c61/bootloader_esp32c61.c‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -95,8 +95,7 @@ static inline void bootloader_ana_reset_config(void)
9595
{
9696
//Enable BOD reset (mode1)
9797
brownout_ll_ana_reset_enable(true);
98-
uint8_t power_glitch_dref = 0;
99-
bootloader_power_glitch_reset_config(true, power_glitch_dref);
98+
bootloader_power_glitch_reset_config(true);
10099
}
101100

102101
esp_err_t bootloader_init(void)

‎components/bootloader_support/src/esp32c61/bootloader_soc.c‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -17,18 +17,18 @@ void bootloader_ana_clock_glitch_reset_config(bool enable)
1717
(void)enable;
1818
}
1919

20-
void bootloader_power_glitch_reset_config(bool enable, uint8_t dref)
20+
void bootloader_power_glitch_reset_config(bool enable)
2121
{
22-
assert(dref < 8);
23-
REG_SET_FIELD(LP_ANA_FIB_ENABLE_REG, LP_ANA_ANA_FIB_PWR_GLITCH_ENA, 0);
22+
//only detect VDDPST POWER GLITCH
23+
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
24+
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
25+
REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_XPD_VDET_PERIF, 0);
26+
REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_XPD_VDET_PLLBB, 0);
27+
REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_XPD_VDET_PLL, 0);
28+
29+
REG_SET_FIELD(LP_ANA_FIB_ENABLE_REG, LP_ANA_ANA_FIB_PWR_GLITCH_ENA, 0);//default val for chip from ECO2
2430
if (enable) {
25-
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
26-
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
27-
REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_PERIF, dref);
28-
REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_VDDPST, dref);
29-
REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_PLLBB, dref);
30-
REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_PLL, dref);
31-
REG_SET_FIELD(LP_ANA_POWER_GLITCH_CNTL_REG, LP_ANA_POWER_GLITCH_RESET_ENA, 0xf);
31+
REG_SET_FIELD(LP_ANA_POWER_GLITCH_CNTL_REG, LP_ANA_POWER_GLITCH_RESET_ENA, 0xf);//default val for chip from ECO2
3232
} else {
3333
REG_SET_FIELD(LP_ANA_POWER_GLITCH_CNTL_REG, LP_ANA_POWER_GLITCH_RESET_ENA, 0);
3434
}

‎components/esp_hw_support/port/esp32c61/rtc_clk_init.c‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -78,6 +78,8 @@ void rtc_clk_init(rtc_clk_config_t cfg)
7878
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_SCK_DCAP, cfg.slow_clk_dcap);
7979
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_ENIF_RTC_DREG, 1);
8080
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_ENIF_DIG_DREG, 1);
81+
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_DIG_REG, 0);
82+
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_RTC_REG, 0);
8183

8284
uint32_t hp_cali_dbias = get_act_hp_dbias();
8385
uint32_t lp_cali_dbias = get_act_lp_dbias();

‎components/soc/esp32c5/include/soc/regi2c_saradc.h‎

Lines changed: 17 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -90,6 +90,22 @@
9090
#define ADC_SAR2_ENCAL_GND_ADDR_MSB 0x3
9191
#define ADC_SAR2_ENCAL_GND_ADDR_LSB 0x3
9292

93+
#define POWER_GLITCH_XPD_VDET_PERIF 10
94+
#define POWER_GLITCH_XPD_VDET_PERIF_MSB 0
95+
#define POWER_GLITCH_XPD_VDET_PERIF_LSB 0
96+
97+
#define POWER_GLITCH_XPD_VDET_VDDPST 10
98+
#define POWER_GLITCH_XPD_VDET_VDDPST_MSB 1
99+
#define POWER_GLITCH_XPD_VDET_VDDPST_LSB 1
100+
101+
#define POWER_GLITCH_XPD_VDET_XTAL 10
102+
#define POWER_GLITCH_XPD_VDET_XTAL_MSB 2
103+
#define POWER_GLITCH_XPD_VDET_XTAL_LSB 2
104+
105+
#define POWER_GLITCH_XPD_VDET_PLL 10
106+
#define POWER_GLITCH_XPD_VDET_PLL_MSB 3
107+
#define POWER_GLITCH_XPD_VDET_PLL_LSB 3
108+
93109
#define POWER_GLITCH_DREF_VDET_PERIF 11
94110
#define POWER_GLITCH_DREF_VDET_PERIF_MSB 2
95111
#define POWER_GLITCH_DREF_VDET_PERIF_LSB 0

‎components/soc/esp32c61/include/soc/regi2c_saradc.h‎

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -78,6 +78,22 @@
7878
#define I2C_SAR2_ENCAL_GND_MSB 7
7979
#define I2C_SAR2_ENCAL_GND_LSB 7
8080

81+
#define POWER_GLITCH_XPD_VDET_PERIF 10
82+
#define POWER_GLITCH_XPD_VDET_PERIF_MSB 0
83+
#define POWER_GLITCH_XPD_VDET_PERIF_LSB 0
84+
85+
#define POWER_GLITCH_XPD_VDET_VDDPST 10
86+
#define POWER_GLITCH_XPD_VDET_VDDPST_MSB 1
87+
#define POWER_GLITCH_XPD_VDET_VDDPST_LSB 1
88+
89+
#define POWER_GLITCH_XPD_VDET_PLLBB 10
90+
#define POWER_GLITCH_XPD_VDET_PLLBB_MSB 2
91+
#define POWER_GLITCH_XPD_VDET_PLLBB_LSB 2
92+
93+
#define POWER_GLITCH_XPD_VDET_PLL 10
94+
#define POWER_GLITCH_XPD_VDET_PLL_MSB 3
95+
#define POWER_GLITCH_XPD_VDET_PLL_LSB 3
96+
8197
#define POWER_GLITCH_DREF_VDET_PERIF 11
8298
#define POWER_GLITCH_DREF_VDET_PERIF_MSB 2
8399
#define POWER_GLITCH_DREF_VDET_PERIF_LSB 0

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