feat: add i2s & etm sleep retention entry on H4

L-KAYA · L-KAYA · commit 263a056486a7 · 2025-07-22T10:05:12.000+08:00
diff --git a/components/esp_driver_i2s/CMakeLists.txt b/components/esp_driver_i2s/CMakeLists.txt
@@ -37,4 +37,5 @@ endif()
 idf_component_register(SRCS ${srcs}
                     INCLUDE_DIRS ${include}
                     PRIV_REQUIRES esp_driver_gpio esp_pm esp_mm
+                    LDFRAGMENTS linker.lf
                     )
diff --git a/components/esp_driver_i2s/i2s_common.c b/components/esp_driver_i2s/i2s_common.c
@@ -575,7 +575,7 @@ uint32_t i2s_get_source_clk_freq(i2s_clock_src_t clk_src, uint32_t mclk_freq_hz)
 }
 
 #if SOC_GDMA_SUPPORTED
-static bool IRAM_ATTR i2s_dma_rx_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data)
+static bool i2s_dma_rx_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data)
 {
     i2s_chan_handle_t handle = (i2s_chan_handle_t)user_data;
     BaseType_t need_yield1 = 0;
@@ -606,7 +606,7 @@ static bool IRAM_ATTR i2s_dma_rx_callback(gdma_channel_handle_t dma_chan, gdma_e
     return need_yield1 | need_yield2 | user_need_yield;
 }
 
-static bool IRAM_ATTR i2s_dma_tx_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data)
+static bool i2s_dma_tx_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data)
 {
     i2s_chan_handle_t handle = (i2s_chan_handle_t)user_data;
     BaseType_t need_yield1 = 0;
@@ -653,7 +653,7 @@ static bool IRAM_ATTR i2s_dma_tx_callback(gdma_channel_handle_t dma_chan, gdma_e
 
 #else
 
-static void IRAM_ATTR i2s_dma_rx_callback(void *arg)
+static void i2s_dma_rx_callback(void *arg)
 {
     BaseType_t need_yield1 = 0;
     BaseType_t need_yield2 = 0;
@@ -691,7 +691,7 @@ static void IRAM_ATTR i2s_dma_rx_callback(void *arg)
     }
 }
 
-static void IRAM_ATTR i2s_dma_tx_callback(void *arg)
+static void i2s_dma_tx_callback(void *arg)
 {
     BaseType_t need_yield1 = 0;
     BaseType_t need_yield2 = 0;
@@ -1485,7 +1485,7 @@ void i2s_sync_reset_fifo_count(i2s_chan_handle_t tx_handle)
 }
 #endif  // SOC_I2S_SUPPORTS_TX_SYNC_CNT
 
-#if SOC_I2S_SUPPORTS_ETM_SYNC
+#if SOC_I2S_SUPPORTS_TX_FIFO_SYNC
 uint32_t i2s_sync_get_fifo_sync_diff_count(i2s_chan_handle_t tx_handle)
 {
     return i2s_ll_tx_get_fifo_sync_diff_count(tx_handle->controller->hal.dev);
diff --git a/components/esp_driver_i2s/i2s_etm.c b/components/esp_driver_i2s/i2s_etm.c
@@ -84,9 +84,9 @@ esp_err_t i2s_new_etm_task(i2s_chan_handle_t handle, const i2s_etm_task_config_t
 {
     ESP_RETURN_ON_FALSE(handle && config && out_task, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
     ESP_RETURN_ON_FALSE(config->task_type < I2S_ETM_TASK_MAX, ESP_ERR_INVALID_ARG, TAG, "invalid task type");
-#if SOC_I2S_SUPPORTS_ETM_SYNC
-    ESP_RETURN_ON_FALSE(config->task_type != I2S_ETM_TASK_SYNC_CHECK || handle->dir == I2S_DIR_TX,
-                        ESP_ERR_NOT_SUPPORTED, TAG, "rx is not supported");
+#if SOC_I2S_SUPPORTS_TX_FIFO_SYNC
+    ESP_RETURN_ON_FALSE(config->task_type != I2S_ETM_TASK_SYNC_FIFO || handle->dir == I2S_DIR_TX,
+                        ESP_ERR_NOT_SUPPORTED, TAG, "rx does not support sync check");
 #endif
 
     i2s_etm_task_t *task = heap_caps_calloc(1, sizeof(i2s_etm_task_t), ETM_MEM_ALLOC_CAPS);
diff --git a/components/esp_driver_i2s/include/esp_private/i2s_sync.h b/components/esp_driver_i2s/include/esp_private/i2s_sync.h
@@ -21,6 +21,7 @@
 
 #include <stdint.h>
 #include "driver/i2s_types.h"
+#include "esp_err.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -31,7 +32,7 @@ extern "C" {
 /**
  * @brief Get the counter number of BCLK ticks
  * @note  The BCLK tick count reflects the real data that have sent on line
- * @note  It will be reset automatically when `I2S_ETM_TASK_SYNC_CHECK` is triggered
+ * @note  It will be reset automatically when `I2S_ETM_TASK_SYNC_FIFO` is triggered
  *
  * @param[in] tx_handle The I2S tx channel handle
  * @return
@@ -44,7 +45,7 @@ uint32_t i2s_sync_get_bclk_count(i2s_chan_handle_t tx_handle);
  * @note  The FIFO count reflects how many slots have processed
  *        Normally, fifo_cnt = slot_bit_width * bclk_cnt
  *        If fifo_cnt < slot_bit_width * bclk_cnt, that means some data are still stuck in the I2S controller
- * @note  It will be reset automatically when `I2S_ETM_TASK_SYNC_CHECK` is triggered
+ * @note  It will be reset automatically when `I2S_ETM_TASK_SYNC_FIFO` is triggered
  *
  * @param[in] tx_handle The I2S tx channel handle
  * @return
@@ -68,7 +69,7 @@ void i2s_sync_reset_fifo_count(i2s_chan_handle_t tx_handle);
 
 #endif  // SOC_I2S_SUPPORTS_TX_SYNC_CNT
 
-#if SOC_I2S_SUPPORTS_ETM_SYNC
+#if SOC_I2S_SUPPORTS_TX_FIFO_SYNC
 /**
  * @brief I2S hardware FIFO synchronization supplement mode
  * @note  When the FIFO sync difference count is out of threshold, the hardware will supplement data automatically
diff --git a/components/esp_driver_i2s/linker.lf b/components/esp_driver_i2s/linker.lf
@@ -1,13 +1,16 @@
 [mapping:i2s_driver]
 archive: libesp_driver_i2s.a
 entries:
+    if I2S_ISR_IRAM_SAFE = y:
+        i2s_common: i2s_dma_rx_callback (noflash)
+        i2s_common: i2s_dma_tx_callback (noflash)
     if I2S_CTRL_FUNC_IN_IRAM = y:
         if SOC_I2S_SUPPORTS_TX_SYNC_CNT = y:
             i2s_common: i2s_sync_get_bclk_count (noflash)
             i2s_common: i2s_sync_get_fifo_count (noflash)
             i2s_common: i2s_sync_reset_bclk_count (noflash)
             i2s_common: i2s_sync_reset_fifo_count (noflash)
-        if SOC_I2S_SUPPORTS_ETM_SYNC = y:
+        if SOC_I2S_SUPPORTS_TX_FIFO_SYNC = y:
             i2s_common: i2s_sync_get_fifo_sync_diff_count (noflash)
             i2s_common: i2s_sync_reset_fifo_sync_diff_count (noflash)
             i2s_common: i2s_sync_enable_hw_fifo_sync (noflash)
diff --git a/components/esp_driver_i2s/test_apps/i2s/sdkconfig.ci.iram_safe b/components/esp_driver_i2s/test_apps/i2s/sdkconfig.ci.iram_safe
@@ -1,5 +1,6 @@
 CONFIG_COMPILER_DUMP_RTL_FILES=y
 CONFIG_I2S_ISR_IRAM_SAFE=y
+CONFIG_I2S_CTRL_FUNC_IN_IRAM=y
 CONFIG_COMPILER_OPTIMIZATION_NONE=y
 # silent the error check, as the error string are stored in rodata, causing RTL check failure
 CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT=y
diff --git a/components/hal/esp32h4/include/hal/i2s_ll.h b/components/hal/esp32h4/include/hal/i2s_ll.h
@@ -60,12 +60,12 @@ extern "C" {
                                          [I2S_DIR_RX - 1] = {  \
                                              [I2S_ETM_TASK_START] = I2S0_TASK_START_RX, \
                                              [I2S_ETM_TASK_STOP] = I2S0_TASK_STOP_RX, \
-                                             [I2S_ETM_TASK_SYNC_CHECK] = -1, \
+                                             [I2S_ETM_TASK_SYNC_FIFO] = -1, \
                                             },  \
                                         [I2S_DIR_TX - 1] = {  \
                                             [I2S_ETM_TASK_START] = I2S0_TASK_START_TX, \
                                             [I2S_ETM_TASK_STOP] = I2S0_TASK_STOP_TX, \
-                                            [I2S_ETM_TASK_SYNC_CHECK] = I2S0_TASK_SYNC_CHECK, \
+                                            [I2S_ETM_TASK_SYNC_FIFO] = I2S0_TASK_SYNC_CHECK, \
                                          }}}[i2s_port][(chan_dir) - 1][task]
 #define I2S_LL_ETM_MAX_THRESH_NUM       (0x3FFFUL)
 
@@ -1344,7 +1344,7 @@ static inline void i2s_ll_tx_set_hw_fifo_sync_static_suppl_data(i2s_dev_t *hw, u
  * @brief Set the TX ETM synchronization ideal count
  *
  * @param hw Peripheral I2S hardware instance address.
- * @param ideal_cnt The ideal FIFO count when I2S_ETM_TASK_SYNC_CHECK triggered.
+ * @param ideal_cnt The ideal FIFO count when I2S_ETM_TASK_SYNC_FIFO triggered.
  */
 __attribute__((always_inline))
 static inline void i2s_ll_tx_set_etm_sync_ideal_cnt(i2s_dev_t *hw, uint32_t ideal_cnt)
diff --git a/components/hal/include/hal/i2s_types.h b/components/hal/include/hal/i2s_types.h
@@ -233,8 +233,8 @@ typedef enum {
 typedef enum {
     I2S_ETM_TASK_START,     /*!< Start the I2S channel */
     I2S_ETM_TASK_STOP,      /*!< Stop the I2S channel */
-#if SOC_I2S_SUPPORTS_ETM_SYNC
-    I2S_ETM_TASK_SYNC_CHECK, /*!< Check the I2S TX channel sync status */
+#if SOC_I2S_SUPPORTS_TX_FIFO_SYNC
+    I2S_ETM_TASK_SYNC_FIFO, /*!< Check the I2S TX channel sync status */
 #endif
     I2S_ETM_TASK_MAX,       /*!< Maximum number of tasks */
 } i2s_etm_task_type_t;
diff --git a/components/soc/esp32/register/soc/i2s_reg.h b/components/soc/esp32/register/soc/i2s_reg.h
@@ -1,15 +1,17 @@
 /*
- * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-#ifndef _SOC_I2S_REG_H_
-#define _SOC_I2S_REG_H_
+#pragma once
 
 #include "soc/soc.h"
 
-#define REG_I2S_BASE( i ) ( DR_REG_I2S_BASE + ((i)*0x1E000))
+#ifdef __cplusplus
+extern "C" {
+#endif
 
+#define REG_I2S_BASE( i ) ( DR_REG_I2S_BASE + ((i)*0x1E000))
 
 #define I2S_CONF_REG(i)          (REG_I2S_BASE(i) + 0x0008)
 /* I2S_SIG_LOOPBACK : R/W ;bitpos:[18] ;default: 1'b0 ; */
@@ -1511,7 +1513,6 @@
 #define I2S_I2SDATE_V  0xFFFFFFFF
 #define I2S_I2SDATE_S  0
 
-
-
-
-#endif /*_SOC_I2S_REG_H_ */
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c3/include/soc/soc.h b/components/soc/esp32c3/include/soc/soc.h
@@ -20,7 +20,6 @@
 #define REG_UART_BASE(i)                        (DR_REG_UART_BASE + (i) * 0x10000)
 #define REG_UART_AHB_BASE(i)                    (0x60000000 + (i) * 0x10000)
 #define UART_FIFO_AHB_REG(i)                    (REG_UART_AHB_BASE(i) + 0x0)
-#define REG_I2S_BASE(i)                         (DR_REG_I2S_BASE)                       // only one I2S on C3
 #define REG_TIMG_BASE(i)                        (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
 #define REG_SPI_MEM_BASE(i)                     (DR_REG_SPI0_BASE - (i) * 0x1000)
 #define REG_SPI_BASE(i)                         (((i)==2) ? (DR_REG_SPI2_BASE) : (0))   // only one GPSPI
diff --git a/components/soc/esp32c3/register/soc/i2s_reg.h b/components/soc/esp32c3/register/soc/i2s_reg.h
@@ -1,16 +1,18 @@
 /*
- * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-#ifndef _SOC_I2S_REG_H_
-#define _SOC_I2S_REG_H_
+#pragma once
 
+#include "soc/soc.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc/soc.h"
+
+#define REG_I2S_BASE(i)                         (DR_REG_I2S_BASE)                       // only one I2S on C3
+
 #define I2S_INT_RAW_REG(i)          (REG_I2S_BASE(i) + 0x000c)
 /* I2S_TX_HUNG_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
 /*description: The raw interrupt status bit  for the i2s_tx_hung_int interrupt*/
@@ -1037,7 +1039,3 @@ T12_5[2:0]).*/
 #ifdef __cplusplus
 }
 #endif
-
-
-
-#endif /*_SOC_I2S_REG_H_ */
diff --git a/components/soc/esp32c5/include/soc/soc.h b/components/soc/esp32c5/include/soc/soc.h
@@ -18,7 +18,6 @@
 
 #define REG_UHCI_BASE(i)                        (DR_REG_UHCI_BASE)                       // only one UHCI on C5
 #define REG_UART_BASE(i)                        (DR_REG_UART0_BASE + (i) * 0x1000)       // UART0 and UART1
-#define REG_I2S_BASE(i)                         (DR_REG_I2S_BASE)                        // only one I2S on C5
 #define REG_TIMG_BASE(i)                        (DR_REG_TIMERG0_BASE + (i) * 0x1000)     // TIMERG0 and TIMERG1
 #define REG_SPI_MEM_BASE(i)                     (DR_REG_SPIMEM0_BASE + (i) * 0x1000)     // SPIMEM0 and SPIMEM1
 #define REG_I2C_BASE(i)                         (DR_REG_I2C_BASE)                        // only one I2C on C5
diff --git a/components/soc/esp32c5/register/soc/i2s_reg.h b/components/soc/esp32c5/register/soc/i2s_reg.h
@@ -11,6 +11,8 @@
 extern "C" {
 #endif
 
+#define REG_I2S_BASE(i)                         (DR_REG_I2S_BASE)                        // only one I2S on C5
+
 /** I2S_INT_RAW_REG register
  *  I2S interrupt raw register, valid in level.
  */
diff --git a/components/soc/esp32c6/include/soc/soc.h b/components/soc/esp32c6/include/soc/soc.h
@@ -20,7 +20,6 @@
 #define REG_UART_BASE(i)                        (DR_REG_UART_BASE + (i) * 0x1000)        // UART0 and UART1
 #define REG_UART_AHB_BASE(i)                    (0x60000000 + (i) * 0x10000)
 #define UART_FIFO_AHB_REG(i)                    (REG_UART_AHB_BASE(i) + 0x0)
-#define REG_I2S_BASE(i)                         (DR_REG_I2S_BASE)                        // only one I2S on C6
 #define REG_TIMG_BASE(i)                        (DR_REG_TIMERGROUP0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1
 #define REG_SPI_MEM_BASE(i)                     (DR_REG_SPI0_BASE + (i) * 0x1000)        // SPIMEM0 and SPIMEM1
 #define REG_SPI_BASE(i)                         (((i)==2) ? (DR_REG_SPI2_BASE) : (0))    // only one GPSPI on C6
diff --git a/components/soc/esp32c6/register/soc/i2s_reg.h b/components/soc/esp32c6/register/soc/i2s_reg.h
@@ -11,6 +11,8 @@
 extern "C" {
 #endif
 
+#define REG_I2S_BASE(i)                         (DR_REG_I2S_BASE)                        // only one I2S on C6
+
 /** I2S_INT_RAW_REG register
  *  I2S interrupt raw register, valid in level.
  */
diff --git a/components/soc/esp32c61/include/soc/soc.h b/components/soc/esp32c61/include/soc/soc.h
@@ -19,7 +19,6 @@
 #define REG_UART_BASE(i)                        (DR_REG_UART0_BASE + (i) * 0x1000)       // UART0 and UART1
 #define REG_UART_AHB_BASE(i)                    (0x60000000 + (i) * 0x10000)
 #define UART_FIFO_AHB_REG(i)                    (REG_UART_AHB_BASE(i) + 0x0)
-#define REG_I2S_BASE(i)                         (DR_REG_I2S_BASE)                        // only one I2S on C61
 #define REG_TIMG_BASE(i)                        (DR_REG_TIMG0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1
 #define REG_SPI_MEM_BASE(i)                     (DR_REG_MSPI0_BASE + (i) * 0x1000)        // SPIMEM0 and SPIMEM1
 #define REG_I2C_BASE(i)                         (DR_REG_I2C_EXT_BASE)                    // only one I2C on C61
diff --git a/components/soc/esp32c61/register/soc/i2s_reg.h b/components/soc/esp32c61/register/soc/i2s_reg.h
@@ -11,6 +11,8 @@
 extern "C" {
 #endif
 
+#define REG_I2S_BASE(i)                         (DR_REG_I2S_BASE)                        // only one I2S on C61
+
 /** I2S_INT_RAW_REG register
  *  I2S interrupt raw register, valid in level.
  */
diff --git a/components/soc/esp32h2/include/soc/soc.h b/components/soc/esp32h2/include/soc/soc.h
@@ -20,7 +20,6 @@
 #define REG_UART_BASE(i)                        (DR_REG_UART_BASE + (i) * 0x1000)
 #define REG_UART_AHB_BASE(i)                    (0x60000000 + (i) * 0x10000)
 #define UART_FIFO_AHB_REG(i)                    (REG_UART_AHB_BASE(i) + 0x0)
-#define REG_I2S_BASE(i)                         (DR_REG_I2S_BASE)                       // only one I2S on H2
 #define REG_TIMG_BASE(i)                        (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
 #define REG_SPI_MEM_BASE(i)                     (DR_REG_SPI0_BASE + (i) * 0x1000)
 #define REG_SPI_BASE(i)                         (((i)==2) ? (DR_REG_SPI2_BASE) : (0))    // only one GPSPI
diff --git a/components/soc/esp32h2/register/soc/i2s_reg.h b/components/soc/esp32h2/register/soc/i2s_reg.h
@@ -11,6 +11,8 @@
 extern "C" {
 #endif
 
+#define REG_I2S_BASE(i)                         (DR_REG_I2S_BASE)                       // only one I2S on H2
+
 /** I2S_INT_RAW_REG register
  *  I2S interrupt raw register, valid in level.
  */
diff --git a/components/soc/esp32h4/etm_periph.c b/components/soc/esp32h4/etm_periph.c
@@ -7,4 +7,38 @@
 #include "soc/etm_periph.h"
 #include "soc/soc_etm_reg.h"
 
-// TODO: [ESP32H4] IDF-12356 Support sleep retention
+/**
+ * ETM Registers to be saved during sleep retention
+ * - Channel configuration registers, e.g.: SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_TASK_ID_REG
+*/
+#define ETM_RETENTION_REGS_CNT ((SOC_ETM_CH49_TASK_ID_REG - SOC_ETM_CH0_EVT_ID_REG) / 4 + 1)
+
+static const regdma_entries_config_t etm_regdma_entries[] = {
+    // backup stage: save the status of enabled channels
+    // restore stage: store the enabled channels
+    [0] = {
+        .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x00),
+                                              SOC_ETM_CH_ENA_AD0_REG, SOC_ETM_CH_ENA_AD0_SET_REG, 1, 0, 0),
+        .owner = ENTRY(0) | ENTRY(2),
+    },
+    [1] = {
+        .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x01),
+                                              SOC_ETM_CH_ENA_AD1_REG, SOC_ETM_CH_ENA_AD1_SET_REG, 1, 0, 0),
+        .owner = ENTRY(0) | ENTRY(2),
+    },
+    // backup stage: save configuration registers
+    // restore stage: restore the configuration registers
+    [2] = {
+        .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x02),
+                                              SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_EVT_ID_REG, ETM_RETENTION_REGS_CNT, 0, 0),
+        .owner = ENTRY(0) | ENTRY(2),
+    },
+};
+
+const etm_reg_retention_info_t etm_reg_retention_info[SOC_ETM_GROUPS] = {
+    [0] = {
+        .module = SLEEP_RETENTION_MODULE_ETM0,
+        .regdma_entry_array = etm_regdma_entries,
+        .array_size = ARRAY_SIZE(etm_regdma_entries)
+    },
+};
diff --git a/components/soc/esp32h4/i2s_periph.c b/components/soc/esp32h4/i2s_periph.c
@@ -32,3 +32,46 @@ const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_NUM] = {
         .irq          = ETS_I2S_INTR_SOURCE,
     }
 };
+
+/**
+ * I2S Registers to be saved during sleep retention
+ * - I2S_INT_ENA_REG
+ * - I2S_RX_CONF_REG
+ * - I2S_TX_CONF_REG
+ * - I2S_RX_CONF1_REG
+ * - I2S_TX_CONF1_REG
+ * - I2S_TX_PCM2PDM_CONF_REG
+ * - I2S_TX_PCM2PDM_CONF1_REG
+ * - I2S_RX_TDM_CTRL_REG
+ * - I2S_TX_TDM_CTRL_REG
+ * - I2S_RXEOF_NUM_REG
+ * - I2S_ETM_CONF_REG
+ * - I2S_IDEAL_CNT_REG
+ * - I2S_SYNC_SW_THRES_REG
+ * - I2S_SYNC_HW_THRES_REG
+ * - I2S_HW_SYNC_CONF_REG
+ * - I2S_HW_SYNC_DATA_REG
+*/
+
+#define I2S_RETENTION_REGS_CNT 16
+#define I2S_RETENTION_REGS_BASE(i) (I2S_INT_ENA_REG(i))
+static const uint32_t i2s_regs_map[4] = {0xf191b079, 0x0, 0x0, 0x0};
+#define I2S_SLEEP_RETENTION_ENTRIES(i2s_port) {  \
+    [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(  \
+                REGDMA_I2S_LINK(0x00), \
+                I2S_RETENTION_REGS_BASE(i2s_port), \
+                I2S_RETENTION_REGS_BASE(i2s_port), \
+                I2S_RETENTION_REGS_CNT, 0, 0, \
+                i2s_regs_map[0], i2s_regs_map[1], \
+                i2s_regs_map[2], i2s_regs_map[3]), \
+            .owner = ENTRY(0) | ENTRY(2) }, \
+};
+static const regdma_entries_config_t i2s0_regs_retention[] = I2S_SLEEP_RETENTION_ENTRIES(0);
+
+const i2s_reg_retention_info_t i2s_reg_retention_info[SOC_I2S_NUM] = {
+    [0] = {
+        .retention_module = SLEEP_RETENTION_MODULE_I2S0,
+        .entry_array = i2s0_regs_retention,
+        .array_size = ARRAY_SIZE(i2s0_regs_retention)
+    },
+};
diff --git a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
diff --git a/components/soc/esp32h4/include/soc/soc_caps.h b/components/soc/esp32h4/include/soc/soc_caps.h
diff --git a/components/soc/esp32h4/register/soc/i2s_reg.h b/components/soc/esp32h4/register/soc/i2s_reg.h
diff --git a/components/soc/esp32h4/register/soc/soc_etm_reg.h b/components/soc/esp32h4/register/soc/soc_etm_reg.h
diff --git a/components/soc/esp32p4/include/soc/soc.h b/components/soc/esp32p4/include/soc/soc.h
diff --git a/components/soc/esp32p4/register/hw_ver1/soc/i2s_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/i2s_reg.h
diff --git a/components/soc/esp32s2/include/soc/soc.h b/components/soc/esp32s2/include/soc/soc.h
diff --git a/components/soc/esp32s2/register/soc/i2s_reg.h b/components/soc/esp32s2/register/soc/i2s_reg.h
diff --git a/components/soc/esp32s3/include/soc/soc.h b/components/soc/esp32s3/include/soc/soc.h
diff --git a/components/soc/esp32s3/register/soc/i2s_reg.h b/components/soc/esp32s3/register/soc/i2s_reg.h

Original file line number	Diff line number	Diff line change
`@@ -37,4 +37,5 @@ endif()`
`37`	`37`	`idf_component_register(SRCS ${srcs}`
`38`	`38`	`INCLUDE_DIRS ${include}`
`39`	`39`	`PRIV_REQUIRES esp_driver_gpio esp_pm esp_mm`
	`40`	`+ LDFRAGMENTS linker.lf`
`40`	`41`	`)`
Original file line number	Diff line number	Diff line change
`@@ -575,7 +575,7 @@ uint32_t i2s_get_source_clk_freq(i2s_clock_src_t clk_src, uint32_t mclk_freq_hz)`
`575`	`575`	`}`
`576`	`576`
`577`	`577`	`#if SOC_GDMA_SUPPORTED`
`578`		`-static bool IRAM_ATTR i2s_dma_rx_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t event_data, void user_data)`
	`578`	`+static bool i2s_dma_rx_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t event_data, void user_data)`
`579`	`579`	`{`
`580`	`580`	`i2s_chan_handle_t handle = (i2s_chan_handle_t)user_data;`
`581`	`581`	`BaseType_t need_yield1 = 0;`
`@@ -606,7 +606,7 @@ static bool IRAM_ATTR i2s_dma_rx_callback(gdma_channel_handle_t dma_chan, gdma_e`
`606`	`606`	`return need_yield1 \| need_yield2 \| user_need_yield;`
`607`	`607`	`}`
`608`	`608`
`609`		`-static bool IRAM_ATTR i2s_dma_tx_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t event_data, void user_data)`
	`609`	`+static bool i2s_dma_tx_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t event_data, void user_data)`
`610`	`610`	`{`
`611`	`611`	`i2s_chan_handle_t handle = (i2s_chan_handle_t)user_data;`
`612`	`612`	`BaseType_t need_yield1 = 0;`
`@@ -653,7 +653,7 @@ static bool IRAM_ATTR i2s_dma_tx_callback(gdma_channel_handle_t dma_chan, gdma_e`
`653`	`653`
`654`	`654`	`#else`
`655`	`655`
`656`		`-static void IRAM_ATTR i2s_dma_rx_callback(void *arg)`
	`656`	`+static void i2s_dma_rx_callback(void *arg)`
`657`	`657`	`{`
`658`	`658`	`BaseType_t need_yield1 = 0;`
`659`	`659`	`BaseType_t need_yield2 = 0;`
`@@ -691,7 +691,7 @@ static void IRAM_ATTR i2s_dma_rx_callback(void *arg)`
`691`	`691`	`}`
`692`	`692`	`}`
`693`	`693`
`694`		`-static void IRAM_ATTR i2s_dma_tx_callback(void *arg)`
	`694`	`+static void i2s_dma_tx_callback(void *arg)`
`695`	`695`	`{`
`696`	`696`	`BaseType_t need_yield1 = 0;`
`697`	`697`	`BaseType_t need_yield2 = 0;`
`@@ -1485,7 +1485,7 @@ void i2s_sync_reset_fifo_count(i2s_chan_handle_t tx_handle)`
`1485`	`1485`	`}`
`1486`	`1486`	`#endif // SOC_I2S_SUPPORTS_TX_SYNC_CNT`
`1487`	`1487`
`1488`		`-#if SOC_I2S_SUPPORTS_ETM_SYNC`
	`1488`	`+#if SOC_I2S_SUPPORTS_TX_FIFO_SYNC`
`1489`	`1489`	`uint32_t i2s_sync_get_fifo_sync_diff_count(i2s_chan_handle_t tx_handle)`
`1490`	`1490`	`{`
`1491`	`1491`	`return i2s_ll_tx_get_fifo_sync_diff_count(tx_handle->controller->hal.dev);`