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ESP-MariusESP-Marius
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feat(intr): clean up and support interrupts on H21
1 parent 4c5e1a0 commit 267a877

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17 files changed

+149
-28
lines changed

17 files changed

+149
-28
lines changed

‎components/esp_hw_support/port/esp32h21/esp_cpu_intr.c‎

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -10,13 +10,11 @@
1010
void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_desc_ret)
1111
{
1212
/* On the ESP32-H21, interrupt:
13-
* - 1 is for Wi-Fi
1413
* - 6 for "permanently disabled interrupt"
1514
*
1615
* Interrupts 3, 4 and 7 are unavailable for PULP CPU as they are bound to Core-Local Interrupts (CLINT)
1716
*/
18-
//TODO: [ESP32H21] IDF-11537
19-
const uint32_t rsvd_mask = BIT(1) | BIT(3) | BIT(4) | BIT(6) | BIT(7);
17+
const uint32_t rsvd_mask = BIT(3) | BIT(4) | BIT(6) | BIT(7);
2018

2119
intr_desc_ret->priority = 1;
2220
intr_desc_ret->type = ESP_CPU_INTR_TYPE_NA;

‎components/esp_system/crosscore_int.c‎

Lines changed: 5 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -11,6 +11,7 @@
1111
#include "esp_intr_alloc.h"
1212
#include "esp_debug_helpers.h"
1313
#include "soc/periph_defs.h"
14+
#include "soc/system_intr.h"
1415
#include "hal/crosscore_int_ll.h"
1516

1617
#include "freertos/FreeRTOS.h"
@@ -20,10 +21,6 @@
2021
#include "esp_gdbstub.h"
2122
#endif
2223

23-
#if CONFIG_IDF_TARGET_ESP32H21
24-
#define ETS_FROM_CPU_INTR0_SOURCE ETS_CPU_INTR_FROM_CPU_0_SOURCE
25-
#endif
26-
2724
#define REASON_YIELD BIT(0)
2825
#define REASON_FREQ_SWITCH BIT(1)
2926
#define REASON_PRINT_BACKTRACE BIT(2)
@@ -98,12 +95,12 @@ void esp_crosscore_int_init(void)
9895
esp_err_t err __attribute__((unused)) = ESP_OK;
9996
#if CONFIG_FREERTOS_NUMBER_OF_CORES > 1
10097
if (esp_cpu_get_core_id() == 0) {
101-
err = esp_intr_alloc(ETS_FROM_CPU_INTR0_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void*)&reason[0], NULL);
98+
err = esp_intr_alloc(SYS_CPU_INTR_FROM_CPU_0_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void*)&reason[0], NULL);
10299
} else {
103-
err = esp_intr_alloc(ETS_FROM_CPU_INTR1_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void*)&reason[1], NULL);
100+
err = esp_intr_alloc(SYS_CPU_INTR_FROM_CPU_1_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void*)&reason[1], NULL);
104101
}
105102
#else
106-
err = esp_intr_alloc(ETS_FROM_CPU_INTR0_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void*)&reason[0], NULL);
103+
err = esp_intr_alloc(SYS_CPU_INTR_FROM_CPU_0_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void*)&reason[0], NULL);
107104
#endif
108105
ESP_ERROR_CHECK(err);
109106
}

‎components/esp_system/int_wdt.c‎

Lines changed: 4 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -12,6 +12,7 @@
1212
#include "hal/wdt_hal.h"
1313
#include "hal/mwdt_ll.h"
1414
#include "hal/timer_ll.h"
15+
#include "soc/system_intr.h"
1516
#include "freertos/FreeRTOS.h"
1617
#include "esp_cpu.h"
1718
#include "esp_check.h"
@@ -28,15 +29,10 @@
2829
#include "esp_private/sleep_retention.h"
2930
#endif
3031

31-
#if CONFIG_IDF_TARGET_ESP32H21
32-
#define ETS_TG0_WDT_LEVEL_INTR_SOURCE ETS_TG0_WDT_INTR_SOURCE
33-
#define ETS_TG1_WDT_LEVEL_INTR_SOURCE ETS_TG1_WDT_INTR_SOURCE
34-
#endif
35-
3632
#if SOC_TIMER_GROUPS > 1
3733

3834
/* If we have two hardware timer groups, use the second one for interrupt watchdog. */
39-
#define WDT_LEVEL_INTR_SOURCE ETS_TG1_WDT_LEVEL_INTR_SOURCE
35+
#define WDT_LEVEL_INTR_SOURCE SYS_TG1_WDT_INTR_SOURCE
4036
#define IWDT_PRESCALER MWDT_LL_DEFAULT_CLK_PRESCALER // Tick period of 500us if WDT source clock is 80MHz
4137
#define IWDT_TICKS_PER_US 500
4238
#define IWDT_INSTANCE WDT_MWDT1
@@ -46,7 +42,7 @@
4642

4743
#else
4844

49-
#define WDT_LEVEL_INTR_SOURCE ETS_TG0_WDT_LEVEL_INTR_SOURCE
45+
#define WDT_LEVEL_INTR_SOURCE SYS_TG0_WDT_INTR_SOURCE
5046
#define IWDT_PRESCALER MWDT_LL_DEFAULT_CLK_PRESCALER // Tick period of 500us if WDT source clock is 80MHz
5147
#define IWDT_TICKS_PER_US 500
5248
#define IWDT_INSTANCE WDT_MWDT0

‎components/esp_system/task_wdt/task_wdt_impl_timergroup.c‎

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -11,6 +11,7 @@
1111
#include "hal/wdt_hal.h"
1212
#include "hal/mwdt_ll.h"
1313
#include "hal/timer_ll.h"
14+
#include "soc/system_intr.h"
1415
#include "esp_check.h"
1516
#include "esp_err.h"
1617
#include "esp_attr.h"
@@ -29,11 +30,8 @@
2930
#define TWDT_PRESCALER MWDT_LL_DEFAULT_CLK_PRESCALER // Tick period of 500us if WDT source clock is 80MHz
3031
#define TWDT_PERIPH_MODULE PERIPH_TIMG0_MODULE
3132
#define TWDT_TIMER_GROUP 0
32-
#if CONFIG_IDF_TARGET_ESP32H21
33-
#define TWDT_INTR_SOURCE ETS_TG0_WDT_INTR_SOURCE
34-
#else
35-
#define TWDT_INTR_SOURCE ETS_TG0_WDT_LEVEL_INTR_SOURCE
36-
#endif
33+
#define TWDT_INTR_SOURCE SYS_TG0_WDT_INTR_SOURCE
34+
3735
/**
3836
* Context for the software implementation of the Task WatchDog Timer.
3937
* This will be passed as a parameter to public functions below. */

‎components/hal/esp32h21/include/hal/crosscore_int_ll.h‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8,8 +8,6 @@
88
#include "esp_attr.h"
99
#include "soc/intpri_reg.h"
1010

11-
//TODO: [ESP32H21] IDF-11537, inherit from h2
12-
1311
#ifdef __cplusplus
1412
extern "C" {
1513
#endif

‎components/soc/esp32/include/soc/system_intr.h‎

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,13 @@
1+
/**
2+
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
#pragma once
7+
8+
// Maps misc system interrupt to hardware interrupt names
9+
#define SYS_CPU_INTR_FROM_CPU_0_SOURCE ETS_FROM_CPU_INTR0_SOURCE
10+
#define SYS_CPU_INTR_FROM_CPU_1_SOURCE ETS_FROM_CPU_INTR1_SOURCE
11+
12+
#define SYS_TG0_WDT_INTR_SOURCE ETS_TG0_WDT_LEVEL_INTR_SOURCE
13+
#define SYS_TG1_WDT_INTR_SOURCE ETS_TG1_WDT_LEVEL_INTR_SOURCE

‎components/soc/esp32c2/include/soc/system_intr.h‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,12 @@
1+
/**
2+
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
#pragma once
7+
8+
// Maps misc system interrupt to hardware interrupt names
9+
#define SYS_CPU_INTR_FROM_CPU_0_SOURCE ETS_FROM_CPU_INTR0_SOURCE
10+
11+
#define SYS_TG0_WDT_INTR_SOURCE ETS_TG0_WDT_LEVEL_INTR_SOURCE
12+
#define SYS_TG1_WDT_INTR_SOURCE ETS_TG1_WDT_LEVEL_INTR_SOURCE

‎components/soc/esp32c3/include/soc/system_intr.h‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,12 @@
1+
/**
2+
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
#pragma once
7+
8+
// Maps misc system interrupt to hardware interrupt names
9+
#define SYS_CPU_INTR_FROM_CPU_0_SOURCE ETS_FROM_CPU_INTR0_SOURCE
10+
11+
#define SYS_TG0_WDT_INTR_SOURCE ETS_TG0_WDT_LEVEL_INTR_SOURCE
12+
#define SYS_TG1_WDT_INTR_SOURCE ETS_TG1_WDT_LEVEL_INTR_SOURCE

‎components/soc/esp32c5/include/soc/system_intr.h‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,12 @@
1+
/**
2+
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
#pragma once
7+
8+
// Maps misc system interrupt to hardware interrupt names
9+
#define SYS_CPU_INTR_FROM_CPU_0_SOURCE ETS_FROM_CPU_INTR0_SOURCE
10+
11+
#define SYS_TG0_WDT_INTR_SOURCE ETS_TG0_WDT_LEVEL_INTR_SOURCE
12+
#define SYS_TG1_WDT_INTR_SOURCE ETS_TG1_WDT_LEVEL_INTR_SOURCE

‎components/soc/esp32c6/include/soc/system_intr.h‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,12 @@
1+
/**
2+
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
#pragma once
7+
8+
// Maps misc system interrupt to hardware interrupt names
9+
#define SYS_CPU_INTR_FROM_CPU_0_SOURCE ETS_FROM_CPU_INTR0_SOURCE
10+
11+
#define SYS_TG0_WDT_INTR_SOURCE ETS_TG0_WDT_LEVEL_INTR_SOURCE
12+
#define SYS_TG1_WDT_INTR_SOURCE ETS_TG1_WDT_LEVEL_INTR_SOURCE

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