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Merge branch 'bugfix/esp_idf_esp32_reject_sleep' into 'master'
fix(esp_hw_support): fix the configuration of reject sources Closes IDFGH-15823 See merge request espressif/esp-idf!41852
2 parents 553d103 + ad0eb8e commit 28c4172

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5 files changed

+25
-4
lines changed

5 files changed

+25
-4
lines changed

‎components/esp_hw_support/port/esp32/rtc_sleep.c‎

Lines changed: 14 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -266,7 +266,13 @@ static uint32_t rtc_sleep_finish(void);
266266
uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt)
267267
{
268268
REG_SET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, RTC_CNTL_WAKEUP_ENA, wakeup_opt);
269-
WRITE_PERI_REG(RTC_CNTL_SLP_REJECT_CONF_REG, reject_opt);
269+
/* In ESP32, only GPIO and SDIO can be as reject source during light sleep. */
270+
if (reject_opt & RTC_GPIO_TRIG_EN) {
271+
REG_SET_BIT(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_GPIO_REJECT_EN);
272+
};
273+
if (reject_opt & RTC_SDIO_TRIG_EN) {
274+
REG_SET_BIT(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_SDIO_REJECT_EN);
275+
};
270276

271277
SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG,
272278
RTC_CNTL_SLP_REJECT_INT_CLR | RTC_CNTL_SLP_WAKEUP_INT_CLR);
@@ -288,7 +294,13 @@ uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt)
288294
uint32_t rtc_deep_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt)
289295
{
290296
REG_SET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, RTC_CNTL_WAKEUP_ENA, wakeup_opt);
291-
WRITE_PERI_REG(RTC_CNTL_SLP_REJECT_CONF_REG, reject_opt);
297+
/* In ESP32, only GPIO and SDIO can be as reject source during deep sleep. */
298+
if (reject_opt & RTC_GPIO_TRIG_EN) {
299+
REG_SET_BIT(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_GPIO_REJECT_EN);
300+
};
301+
if (reject_opt & RTC_SDIO_TRIG_EN) {
302+
REG_SET_BIT(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_SDIO_REJECT_EN);
303+
};
292304

293305
SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG,
294306
RTC_CNTL_SLP_REJECT_INT_CLR | RTC_CNTL_SLP_WAKEUP_INT_CLR);

‎components/esp_hw_support/port/esp32c2/rtc_sleep.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -210,6 +210,7 @@ uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp
210210

211211
SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG,
212212
RTC_CNTL_SLP_REJECT_INT_CLR | RTC_CNTL_SLP_WAKEUP_INT_CLR);
213+
REG_SET_BIT(RTC_CNTL_STATE0_REG, RTC_CNTL_SLP_REJECT_CAUSE_CLR);
213214

214215
/* Start entry into sleep mode */
215216
SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN);

‎components/esp_hw_support/port/esp32c3/rtc_sleep.c‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -261,6 +261,7 @@ uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp
261261

262262
SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG,
263263
RTC_CNTL_SLP_REJECT_INT_CLR | RTC_CNTL_SLP_WAKEUP_INT_CLR);
264+
REG_SET_BIT(RTC_CNTL_STATE0_REG, RTC_CNTL_SLP_REJECT_CAUSE_CLR);
264265

265266
/* Start entry into sleep mode */
266267
SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN);
@@ -279,10 +280,11 @@ uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp
279280
uint32_t rtc_deep_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt)
280281
{
281282
REG_SET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, RTC_CNTL_WAKEUP_ENA, wakeup_opt);
282-
WRITE_PERI_REG(RTC_CNTL_SLP_REJECT_CONF_REG, reject_opt);
283+
REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_SLEEP_REJECT_ENA, reject_opt);
283284

284285
SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG,
285286
RTC_CNTL_SLP_REJECT_INT_CLR | RTC_CNTL_SLP_WAKEUP_INT_CLR);
287+
REG_SET_BIT(RTC_CNTL_STATE0_REG, RTC_CNTL_SLP_REJECT_CAUSE_CLR);
286288

287289
/* Calculate RTC Fast Memory CRC (for wake stub) & go to deep sleep
288290

‎components/esp_hw_support/port/esp32s2/rtc_sleep.c‎

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -269,6 +269,7 @@ uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp
269269

270270
SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG,
271271
RTC_CNTL_SLP_REJECT_INT_CLR | RTC_CNTL_SLP_WAKEUP_INT_CLR);
272+
REG_SET_BIT(RTC_CNTL_STATE0_REG, RTC_CNTL_SLP_REJECT_CAUSE_CLR);
272273

273274
/* Start entry into sleep mode */
274275
SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN);
@@ -287,10 +288,14 @@ uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp
287288
uint32_t rtc_deep_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt)
288289
{
289290
REG_SET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, RTC_CNTL_WAKEUP_ENA, wakeup_opt);
290-
WRITE_PERI_REG(RTC_CNTL_SLP_REJECT_CONF_REG, reject_opt);
291+
REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_SLEEP_REJECT_ENA, reject_opt);
292+
if (reject_opt != 0) {
293+
REG_SET_BIT(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_DEEP_SLP_REJECT_EN);
294+
}
291295

292296
SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG,
293297
RTC_CNTL_SLP_REJECT_INT_CLR | RTC_CNTL_SLP_WAKEUP_INT_CLR);
298+
REG_SET_BIT(RTC_CNTL_STATE0_REG, RTC_CNTL_SLP_REJECT_CAUSE_CLR);
294299

295300
/* Calculate RTC Fast Memory CRC (for wake stub) & go to deep sleep
296301

‎components/esp_hw_support/port/esp32s3/rtc_sleep.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -273,6 +273,7 @@ __attribute__((weak)) uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t rej
273273

274274
SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG,
275275
RTC_CNTL_SLP_REJECT_INT_CLR | RTC_CNTL_SLP_WAKEUP_INT_CLR);
276+
REG_SET_BIT(RTC_CNTL_STATE0_REG, RTC_CNTL_SLP_REJECT_CAUSE_CLR);
276277

277278
/* Start entry into sleep mode */
278279
SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN);

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